system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = (blockIdx.x * blockDim.x) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if (global_index_1d < num_coordinates)
{
unsigned int image_index_1d = d_coordinates[imgSize - global_index_1d - 1];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for (int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++)
{
for (int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++)
{
int2 image_offset_index_2d = make_int2(x, y);
int2 image_offset_index_2d_clamped = make_int2(min(nx - 1, max(0, image_offset_index_2d.x)), min(ny - 1, max(0, image_offset_index_2d.y)));
int image_offset_index_1d_clamped = (nx * image_offset_index_2d_clamped.y) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[image_offset_index_1d_clamped];
unsigned char b_value = d_b[image_offset_index_1d_clamped];
unsigned int gb_average = (g_value + b_value) / 2;
//printf("heya\t");
d_r_output[image_offset_index_1d_clamped] = (unsigned char)gb_average;
}
}
}
} | .text
.file "remove_redness_from_coordinates.hip"
.globl _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii # -- Begin function _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 4, 0x90
.type _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@function
_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii: # @_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .Lfunc_end0-_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@object # @_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .rodata,"a",@progbits
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 3, 0x0
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
.quad _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff037212 */
/* 0x000fe200078e33ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R3, R4, c[0x0][0x18c], R3 ; /* 0x0000630004037a24 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ I2F.U32.RP R0, c[0x0][0x190] ; /* 0x0000640000007b06 */
/* 0x000e300000209000 */
/*00e0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R6, R0, 0xffffffe, RZ ; /* 0x0ffffffe00067810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a07 */
/*0130*/ IMAD R5, R5, c[0x0][0x190], RZ ; /* 0x0000640005057a24 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fe200078e0006 */
/*0150*/ LOP3.LUT R6, RZ, c[0x0][0x190], RZ, 0x33, !PT ; /* 0x00006400ff067a12 */
/* 0x000fca00078e33ff */
/*0160*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x004fc800078e00ff */
/*0170*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a07 */
/*0180*/ IMAD R2, R3, c[0x0][0x190], R2 ; /* 0x0000640003027a24 */
/* 0x000fca00078e0202 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R2, R2, -c[0x0][0x190], RZ ; /* 0x8000640002020a10 */
/* 0x000fe40007ffe0ff */
/*01b0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe40003f26070 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x190], PT ; /* 0x00006400ff007a0c */
/* 0x000fd60003f05070 */
/*01e0*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fc80007ffe0ff */
/*01f0*/ SEL R7, R6, R7, !P0 ; /* 0x0000000706077207 */
/* 0x000fc80004000000 */
/*0200*/ LOP3.LUT R7, R7, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff07077812 */
/* 0x000fc800078ec0ff */
/*0210*/ IADD3 R5, R7.reuse, -c[0x0][0x194], RZ ; /* 0x8000650007057a10 */
/* 0x040fe40007ffe0ff */
/*0220*/ IADD3 R0, R7, c[0x0][0x194], RZ ; /* 0x0000650007007a10 */
/* 0x000fc80007ffe0ff */
/*0230*/ ISETP.GT.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44270 */
/*0240*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R3, R2, -c[0x0][0x190], RZ ; /* 0x8000640002037a10 */
/* 0x000fe20007ffe0ff */
/*0260*/ ULDC UR4, c[0x0][0x18c] ; /* 0x0000630000047ab9 */
/* 0x000fe20000000800 */
/*0270*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0280*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0290*/ @P0 SEL R6, R3, R2, P1 ; /* 0x0000000203060207 */
/* 0x000fc80000800000 */
/*02a0*/ LOP3.LUT R7, R6, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff06077812 */
/* 0x000fc800078ec0ff */
/*02b0*/ IADD3 R2, R7.reuse, -c[0x0][0x198], RZ ; /* 0x8000660007027a10 */
/* 0x040fe40007ffe0ff */
/*02c0*/ IADD3 R3, R7, c[0x0][0x198], RZ ; /* 0x0000660007037a10 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IMNMX R9, RZ, R2, !PT ; /* 0x00000002ff097217 */
/* 0x000fe40007800200 */
/*02e0*/ IMNMX R8, R2, R3, !PT ; /* 0x0000000302087217 */
/* 0x000fe40007800200 */
/*02f0*/ IMNMX R9, R9, R4, PT ; /* 0x0000000409097217 */
/* 0x000fe40003800200 */
/*0300*/ IADD3 R8, R8, c[0x0][0x198], RZ ; /* 0x0000660008087a10 */
/* 0x000fc80007ffe0ff */
/*0310*/ IADD3 R24, -R6, 0x1, R8 ; /* 0x0000000106187810 */
/* 0x000fe20007ffe108 */
/*0320*/ IMAD.IADD R7, R8, 0x1, -R7 ; /* 0x0000000108077824 */
/* 0x000fe200078e0a07 */
/*0330*/ IADD3 R6, R2.reuse, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x040fe40007ffe0ff */
/*0340*/ IADD3 R8, R2.reuse, 0x3, RZ ; /* 0x0000000302087810 */
/* 0x040fe40007ffe0ff */
/*0350*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f06070 */
/*0360*/ IADD3 R7, R2, 0x2, RZ ; /* 0x0000000202077810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IMNMX R11, RZ, R6, !PT ; /* 0x00000006ff0b7217 */
/* 0x000fc40007800200 */
/*0380*/ IMNMX R13, RZ, R7, !PT ; /* 0x00000007ff0d7217 */
/* 0x000fe40007800200 */
/*0390*/ IMNMX R10, R4.reuse, R11, PT ; /* 0x0000000b040a7217 */
/* 0x040fe40003800200 */
/*03a0*/ IMNMX R11, R4, R13, PT ; /* 0x0000000d040b7217 */
/* 0x000fe40003800200 */
/*03b0*/ LOP3.LUT R24, R24, 0x3, RZ, 0xc0, !PT ; /* 0x0000000318187812 */
/* 0x000fe400078ec0ff */
/*03c0*/ ISETP.GT.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe20003f24270 */
/*03d0*/ BSSY B0, 0xb90 ; /* 0x000007b000007945 */
/* 0x000fd80003800000 */
/*03e0*/ @P1 BRA 0xb80 ; /* 0x0000079000001947 */
/* 0x001fea0003800000 */
/*03f0*/ ISETP.NE.AND P1, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f25270 */
/*0400*/ BSSY B1, 0x740 ; /* 0x0000033000017945 */
/* 0x000fe20003800000 */
/*0410*/ IMNMX R26, RZ, R5, !PT ; /* 0x00000005ff1a7217 */
/* 0x000fe20007800200 */
/*0420*/ IMAD.MOV.U32 R18, RZ, RZ, R2 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0002 */
/*0430*/ IMNMX R26, R26, UR4, PT ; /* 0x000000041a1a7c17 */
/* 0x000fce000b800200 */
/*0440*/ @!P1 BRA 0x730 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD R16, R26, c[0x0][0x190], R9 ; /* 0x000064001a107a24 */
/* 0x000fca00078e0209 */
/*0460*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0470*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0480*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0490*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*04a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*04b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*04c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*04d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*04e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe40000ffe4ff */
/*04f0*/ ISETP.NE.AND P1, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fe20003f25270 */
/*0500*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0510*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0520*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0530*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0006 */
/*0540*/ @!P1 BRA 0x730 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD R16, R26, c[0x0][0x190], R10 ; /* 0x000064001a107a24 */
/* 0x001fca00078e020a */
/*0560*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0570*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0580*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0590*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*05a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*05b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*05c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*05d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*05e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe40000ffe4ff */
/*05f0*/ ISETP.NE.AND P1, PT, R24, 0x2, PT ; /* 0x000000021800780c */
/* 0x000fe20003f25270 */
/*0600*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0610*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0620*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0630*/ IMAD.MOV.U32 R18, RZ, RZ, R7 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0007 */
/*0640*/ @!P1 BRA 0x730 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD R16, R26, c[0x0][0x190], R11 ; /* 0x000064001a107a24 */
/* 0x001fca00078e020b */
/*0660*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0670*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0680*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0690*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*06a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*06b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*06c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*06d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*06e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe20000ffe4ff */
/*06f0*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0700*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0710*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0720*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0008 */
/*0730*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0740*/ @!P0 BRA 0xb80 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0750*/ IADD3 R28, R18, 0x3, RZ ; /* 0x00000003121c7810 */
/* 0x000fc80007ffe0ff */
/*0760*/ IADD3 R12, R28, -0x3, RZ ; /* 0xfffffffd1c0c7810 */
/* 0x001fc80007ffe0ff */
/*0770*/ IMNMX R13, RZ, R12, !PT ; /* 0x0000000cff0d7217 */
/* 0x000fc80007800200 */
/*0780*/ IMNMX R13, R4, R13, PT ; /* 0x0000000d040d7217 */
/* 0x000fca0003800200 */
/*0790*/ IMAD R22, R26, c[0x0][0x190], R13 ; /* 0x000064001a167a24 */
/* 0x000fca00078e020d */
/*07a0*/ SHF.R.S32.HI R19, RZ, 0x1f, R22 ; /* 0x0000001fff137819 */
/* 0x001fe40000011416 */
/*07b0*/ IADD3 R12, P2, R22.reuse, c[0x0][0x170], RZ ; /* 0x00005c00160c7a10 */
/* 0x040fe40007f5e0ff */
/*07c0*/ IADD3 R14, P1, R22, c[0x0][0x178], RZ ; /* 0x00005e00160e7a10 */
/* 0x000fe40007f3e0ff */
/*07d0*/ IADD3.X R13, R19.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00130d7a10 */
/* 0x040fe400017fe4ff */
/*07e0*/ IADD3.X R15, R19, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00130f7a10 */
/* 0x000fc80000ffe4ff */
/*07f0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*0800*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*0810*/ IADD3 R16, R28, -0x2, RZ ; /* 0xfffffffe1c107810 */
/* 0x000fc80007ffe0ff */
/*0820*/ IMNMX R17, RZ, R16, !PT ; /* 0x00000010ff117217 */
/* 0x000fc80007800200 */
/*0830*/ IMNMX R17, R4, R17, PT ; /* 0x0000001104117217 */
/* 0x000fca0003800200 */
/*0840*/ IMAD R16, R26, c[0x0][0x190], R17 ; /* 0x000064001a107a24 */
/* 0x000fe200078e0211 */
/*0850*/ IADD3 R22, P1, R22, c[0x0][0x180], RZ ; /* 0x0000600016167a10 */
/* 0x000fc80007f3e0ff */
/*0860*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0870*/ IADD3 R18, P3, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c0010127a10 */
/* 0x040fe40007f7e0ff */
/*0880*/ IADD3 R20, P2, R16, c[0x0][0x178], RZ ; /* 0x00005e0010147a10 */
/* 0x000fe40007f5e0ff */
/*0890*/ IADD3.X R23, R19, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610013177a10 */
/* 0x000fe40000ffe4ff */
/*08a0*/ IADD3.X R19, R17.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0011137a10 */
/* 0x040fe40001ffe4ff */
/*08b0*/ IADD3.X R21, R17, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f0011157a10 */
/* 0x000fe200017fe4ff */
/*08c0*/ IMAD.IADD R25, R14, 0x1, R13 ; /* 0x000000010e197824 */
/* 0x004fca00078e020d */
/*08d0*/ SHF.R.U32.HI R29, RZ, 0x1, R25 ; /* 0x00000001ff1d7819 */
/* 0x000fca0000011619 */
/*08e0*/ STG.E.U8 [R22.64], R29 ; /* 0x0000001d16007986 */
/* 0x0001e8000c101106 */
/*08f0*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000e28000c1e1100 */
/*0900*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000612137981 */
/* 0x000e22000c1e1100 */
/*0910*/ IADD3 R12, R28, -0x1, RZ ; /* 0xffffffff1c0c7810 */
/* 0x000fc80007ffe0ff */
/*0920*/ IMNMX R13, RZ, R12, !PT ; /* 0x0000000cff0d7217 */
/* 0x000fc80007800200 */
/*0930*/ IMNMX R13, R4, R13, PT ; /* 0x0000000d040d7217 */
/* 0x000fca0003800200 */
/*0940*/ IMAD R27, R26, c[0x0][0x190], R13 ; /* 0x000064001a1b7a24 */
/* 0x000fe200078e020d */
/*0950*/ IADD3 R12, P1, R16, c[0x0][0x180], RZ ; /* 0x00006000100c7a10 */
/* 0x000fc80007f3e0ff */
/*0960*/ SHF.R.S32.HI R25, RZ, 0x1f, R27 ; /* 0x0000001fff197819 */
/* 0x000fe4000001141b */
/*0970*/ IADD3 R16, P3, R27.reuse, c[0x0][0x170], RZ ; /* 0x00005c001b107a10 */
/* 0x040fe40007f7e0ff */
/*0980*/ IADD3 R14, P2, R27, c[0x0][0x178], RZ ; /* 0x00005e001b0e7a10 */
/* 0x000fe40007f5e0ff */
/*0990*/ IADD3.X R13, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x00006100110d7a10 */
/* 0x000fe40000ffe4ff */
/*09a0*/ IADD3.X R17, R25.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0019117a10 */
/* 0x040fe40001ffe4ff */
/*09b0*/ IADD3.X R15, R25, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f00190f7a10 */
/* 0x000fe200017fe4ff */
/*09c0*/ IMAD.IADD R22, R20, 0x1, R19 ; /* 0x0000000114167824 */
/* 0x001fca00078e0213 */
/*09d0*/ SHF.R.U32.HI R19, RZ, 0x1, R22 ; /* 0x00000001ff137819 */
/* 0x000fca0000011616 */
/*09e0*/ STG.E.U8 [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101106 */
/*09f0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x0002a8000c1e1100 */
/*0a00*/ LDG.E.U8 R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea2000c1e1100 */
/*0a10*/ IMNMX R21, RZ, R28, !PT ; /* 0x0000001cff157217 */
/* 0x000fc80007800200 */
/*0a20*/ IMNMX R21, R4, R21, PT ; /* 0x0000001504157217 */
/* 0x000fe40003800200 */
/*0a30*/ IADD3 R22, P1, R27, c[0x0][0x180], RZ ; /* 0x000060001b167a10 */
/* 0x000fc60007f3e0ff */
/*0a40*/ IMAD R15, R26, c[0x0][0x190], R21 ; /* 0x000064001a0f7a24 */
/* 0x002fe200078e0215 */
/*0a50*/ IADD3.X R23, R25, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610019177a10 */
/* 0x000fc80000ffe4ff */
/*0a60*/ SHF.R.S32.HI R29, RZ, 0x1f, R15 ; /* 0x0000001fff1d7819 */
/* 0x000fe4000001140f */
/*0a70*/ IADD3 R20, P3, R15.reuse, c[0x0][0x170], RZ ; /* 0x00005c000f147a10 */
/* 0x040fe40007f7e0ff */
/*0a80*/ IADD3 R18, P2, R15, c[0x0][0x178], RZ ; /* 0x00005e000f127a10 */
/* 0x000fe40007f5e0ff */
/*0a90*/ IADD3.X R21, R29.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d001d157a10 */
/* 0x040fe40001ffe4ff */
/*0aa0*/ IADD3.X R19, R29, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f001d137a10 */
/* 0x001fe200017fe4ff */
/*0ab0*/ IMAD.IADD R27, R14, 0x1, R17 ; /* 0x000000010e1b7824 */
/* 0x004fca00078e0211 */
/*0ac0*/ SHF.R.U32.HI R27, RZ, 0x1, R27 ; /* 0x00000001ff1b7819 */
/* 0x000fca000001161b */
/*0ad0*/ STG.E.U8 [R22.64], R27 ; /* 0x0000001b16007986 */
/* 0x0001e8000c101106 */
/*0ae0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea8000c1e1100 */
/*0af0*/ LDG.E.U8 R21, [R20.64] ; /* 0x0000000614157981 */
/* 0x000ea2000c1e1100 */
/*0b00*/ IADD3 R12, P1, R15, c[0x0][0x180], RZ ; /* 0x000060000f0c7a10 */
/* 0x000fc80007f3e0ff */
/*0b10*/ IADD3.X R13, R29, c[0x0][0x184], RZ, P1, !PT ; /* 0x000061001d0d7a10 */
/* 0x000fe40000ffe4ff */
/*0b20*/ ISETP.GE.AND P1, PT, R28.reuse, R3, PT ; /* 0x000000031c00720c */
/* 0x040fe40003f26270 */
/*0b30*/ IADD3 R28, R28, 0x4, RZ ; /* 0x000000041c1c7810 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD.IADD R14, R18, 0x1, R21 ; /* 0x00000001120e7824 */
/* 0x004fca00078e0215 */
/*0b50*/ SHF.R.U32.HI R15, RZ, 0x1, R14 ; /* 0x00000001ff0f7819 */
/* 0x000fca000001160e */
/*0b60*/ STG.E.U8 [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001e2000c101106 */
/*0b70*/ @!P1 BRA 0x760 ; /* 0xfffffbe000009947 */
/* 0x000fea000383ffff */
/*0b80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b90*/ ISETP.GE.AND P1, PT, R5.reuse, R0, PT ; /* 0x000000000500720c */
/* 0x040fe40003f26270 */
/*0ba0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fd60007ffe0ff */
/*0bb0*/ @!P1 BRA 0x3c0 ; /* 0xfffff80000009947 */
/* 0x000fea000383ffff */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 8
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@function
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x34
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xad_u32 v0, v1, -1, s7
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_sub_i32 s4, 0, s3
global_load_b32 v0, v[0:1], off
v_cvt_f32_u32_e32 v1, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v2, v1, s3
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s3
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_perm_b32 v2, v1, v0, 0x5040100
v_lshrrev_b32_e32 v0, 16, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s6, v0
v_add_nc_u32_e32 v0, s6, v0
v_cmp_le_i32_e32 vcc_lo, v1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b32 s12, s[0:1], 0x38
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x20
v_and_b32_e32 v3, 0xffff, v2
s_add_i32 s11, s3, -1
s_add_i32 s2, s2, -1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v2, s12, v3
v_add_nc_u32_e32 v3, s12, v3
s_lshl_b32 s0, s12, 1
s_or_b32 s12, s0, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, v2, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v3, 1, v1
v_cmp_eq_u32_e64 s0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v1, v3
s_or_b32 s10, s0, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_7
.LBB0_4:
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_3
v_maxmin_i32 v3, v1, 0, s2
v_mov_b32_e32 v4, v2
s_mov_b32 s14, s12
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v3, v3, s3
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_maxmin_i32 v5, v4, 0, s11
v_add_nc_u32_e32 v4, 1, v4
s_add_i32 s14, s14, -1
s_cmp_eq_u32 s14, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v5, v3
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_u32 v7, s1, s6, v9
v_add_co_u32 v5, s0, s4, v9
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s1, s7, v10, s1
v_add_co_ci_u32_e64 v6, s0, s5, v10, s0
global_load_u8 v7, v[7:8], off
global_load_u8 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v7, v5, v7
v_add_co_u32 v5, s0, s8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, s9, v10, s0
v_lshrrev_b16 v7, 1, v7
global_store_b8 v[5:6], v7, off
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .Lfunc_end0-_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00041cdf_00000000-6_remove_redness_from_coordinates.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
.type _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii, @function
_Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii, .-_Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, @function
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .-_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "remove_redness_from_coordinates.hip"
.globl _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii # -- Begin function _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 4, 0x90
.type _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@function
_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii: # @_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.cfi_startproc
# %bb.0:
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $200, %rsp
.cfi_adjust_cfa_offset -200
retq
.Lfunc_end0:
.size _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .Lfunc_end0-_Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@object # @_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .rodata,"a",@progbits
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 3, 0x0
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
.quad _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii"
.size .L__unnamed_1, 55
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z46__device_stub__remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define SYMBOL_NUM 256
#define MAX_CODE_LEN (SYMBOL_NUM - 1)
#define GRID_X (1u << 12)
#define GRID_Y 1
#define BLOCK_X (1u << 10)
#define BLOCK_Y 1
#define RAW_BUFF_SIZE (GRID_X * GRID_Y * BLOCK_X * BLOCK_Y)
#define DEF_IDX \
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
#define CUDA_SAFE_CALL(func) \
do { \
cudaError_t err = (func); \
if (err != cudaSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
cudaGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len);
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len);
int main(int argc, char** argv)
{
if (argc != 3) {
fprintf(stderr, "Usage: %s raw_data huffman_table\n", argv[0]);
exit(EXIT_FAILURE);
}
// Read raw data
char* raw_data_h = (char*)calloc(RAW_BUFF_SIZE, 1);
size_t raw_len = 0;
{
printf("Reading raw data ... ");
FILE* raw_file = fopen(argv[1], "r");
size_t r;
while ((r = fread(
raw_data_h + raw_len, 1, RAW_BUFF_SIZE - raw_len, raw_file))
!= 0) {
raw_len += r;
}
fclose(raw_file);
printf("done. Read %zu bytes.\n", raw_len);
}
char* raw_data;
CUDA_SAFE_CALL(cudaMalloc((void**)&raw_data, raw_len));
CUDA_SAFE_CALL(cudaMemcpy(
raw_data, raw_data_h, raw_len, cudaMemcpyHostToDevice));
// Read Huffman table
bool* code_h = (bool*)calloc(MAX_CODE_LEN * SYMBOL_NUM, sizeof(bool));
size_t* code_len_h = (size_t*)calloc(SYMBOL_NUM, sizeof(size_t));
{
printf("Reading Huffman table ... ");
FILE* hufftable_file = fopen(argv[2], "r");
int c;
while (fscanf(hufftable_file, "%d", &c) != EOF) {
size_t len;
int _ = fscanf(hufftable_file, "%zu", &len);
code_len_h[c] = len;
for (size_t j = 0; j < len; j++) {
int b;
int _ = fscanf(hufftable_file, "%d", &b);
code_h[c * MAX_CODE_LEN + j] = b;
}
}
fclose(hufftable_file);
printf("done.\n");
}
bool* code;
CUDA_SAFE_CALL(cudaMalloc(
(void**)&code, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool)));
CUDA_SAFE_CALL(cudaMemcpy(
code, code_h, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool),
cudaMemcpyHostToDevice));
size_t* code_len;
CUDA_SAFE_CALL(cudaMalloc((void**)&code_len, SYMBOL_NUM * sizeof(size_t)));
CUDA_SAFE_CALL(cudaMemcpy(
code_len, code_len_h, SYMBOL_NUM * sizeof(size_t),
cudaMemcpyHostToDevice));
// free(code_h);
// Run on CUDA
dim3 grid(GRID_X, GRID_Y);
dim3 block(BLOCK_X, BLOCK_Y, 1);
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
// Prefix sum of code length
size_t* len_ps_h = (size_t*)calloc(raw_len, sizeof(size_t));
prefixSumHost(raw_data_h, code_len_h, len_ps_h, raw_len);
// prefixSum<<<grid, block>>>(raw_data, code_len, len_ps, raw_len);
CUDA_SAFE_CALL(cudaThreadSynchronize());
size_t* len_ps;
CUDA_SAFE_CALL(cudaMalloc((void**)&len_ps, raw_len * sizeof(size_t)));
CUDA_SAFE_CALL(cudaMemcpy(
len_ps, len_ps_h, raw_len * sizeof(size_t), cudaMemcpyHostToDevice));
/* {
size_t* len_ps_h = (size_t*)malloc(sizeof(size_t) * raw_len);
CUDA_SAFE_CALL(cudaMemcpy(
len_ps_h, len_ps, sizeof(size_t) * raw_len, cudaMemcpyDeviceToHost));
for (size_t i = 0; i < raw_len; i++)
printf("%zu\n", len_ps_h[i]);
} */
size_t len_ps_end;
CUDA_SAFE_CALL(cudaMemcpy(
&len_ps_end, &len_ps[raw_len - 1], sizeof(size_t),
cudaMemcpyDeviceToHost));
size_t bytes_len = len_ps_end + code_len_h[raw_data_h[raw_len - 1]];
printf("bytes len: %zu\n", bytes_len);
// free(code_len_h);
// free(raw_data_h);
if (bytes_len > RAW_BUFF_SIZE) {
fprintf(stderr, "Bytes stream overflowed\n");
exit(EXIT_FAILURE);
}
bool* bytes;
CUDA_SAFE_CALL(cudaMalloc((void**)&bytes, sizeof(bool) * bytes_len));
genByteStream<<<grid, block>>>(
raw_data, code, code_len, len_ps, bytes, raw_len);
CUDA_SAFE_CALL(cudaThreadSynchronize());
// CUDA_SAFE_CALL(cudaFree(len_ps));
// CUDA_SAFE_CALL(cudaFree(code_len));
// CUDA_SAFE_CALL(cudaFree(code));
// CUDA_SAFE_CALL(cudaFree(raw_data));
uint8_t* bits;
size_t bits_len = bytes_len / 8 + 1;
printf("bits len: %zu\n", bits_len);
CUDA_SAFE_CALL(cudaMalloc((void**)&bits, bits_len));
compressByteStream<<<grid, block>>>(bytes, bits, bits_len);
CUDA_SAFE_CALL(cudaThreadSynchronize());
// CUDA_SAFE_CALL(cudaFree(bits));
// CUDA_SAFE_CALL(cudaFree(bytes));
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("bytes: %zu sec: %lf bytes/sec: %lf\n",
raw_len, sec, raw_len / sec);
return 0;
}
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
len_ps[0] = 0;
for (size_t i = 1; i < raw_len; i++) {
len_ps[i] = len_ps[i - 1] + code_len[raw_data[i - 1]];
}
}
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
DEF_IDX;
if (2 * idx + 1 < raw_len) {
len_ps[2 * idx] = code_len[raw_data[2 * idx]];
len_ps[2 * idx + 1] = code_len[raw_data[2 * idx + 1]];
}
__syncthreads();
// build sum in place up the tree
size_t offset = 1;
for (size_t d = raw_len >> 1; d > 0; d >>= 1) {
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
len_ps[bi] += len_ps[ai];
}
offset *= 2;
}
// clear the last element
if (idx == 0)
len_ps[raw_len - 1] = 0;
// traverse down tree & build scan
for (size_t d = 1; d < raw_len; d *= 2) {
offset >>= 1;
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
size_t t = len_ps[ai];
len_ps[ai] = len_ps[bi];
len_ps[bi] += t;
}
}
}
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len)
{
DEF_IDX;
if (idx < raw_len) {
size_t start_pos = len_ps[idx];
char symbol = raw_data[idx];
for (size_t i = 0, len = code_len[symbol]; i < len; i++) {
bytes[start_pos + i] = code[symbol * MAX_CODE_LEN + i];
}
}
}
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len)
{
DEF_IDX;
if (idx < bits_len) {
for (size_t i = 0; i < 8; i++) {
bits[idx] |= (uint8_t)bytes[8 * idx + i] << (7 - i);
}
}
} | code for sm_80
Function : _Z18compressByteStreamPbPhm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ LEA R4, P1, R0.reuse, c[0x0][0x160], 0x3 ; /* 0x0000580000047a11 */
/* 0x040fe200078218ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IADD3 R2, P0, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x040fe40007f1e0ff */
/*00a0*/ LEA.HI.X R5, R0, c[0x0][0x164], RZ, 0x3, P1 ; /* 0x0000590000057a11 */
/* 0x000fc600008f1cff */
/*00b0*/ IMAD.X R3, RZ, RZ, c[0x0][0x16c], P0 ; /* 0x00005b00ff037624 */
/* 0x000fe400000e06ff */
/*00c0*/ LDG.E.U8 R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea8000c1e1100 */
/*00d0*/ LDG.E.U8 R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ee2000c1e1100 */
/*00e0*/ IMAD.SHL.U32 R0, R0, 0x80, RZ ; /* 0x0000008000007824 */
/* 0x004fca00078e00ff */
/*00f0*/ LOP3.LUT R7, R7, R0, RZ, 0xfc, !PT ; /* 0x0000000007077212 */
/* 0x008fca00078efcff */
/*0100*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101104 */
/*0110*/ LDG.E.U8 R0, [R4.64+0x1] ; /* 0x0000010404007981 */
/* 0x000ea4000c1e1100 */
/*0120*/ IMAD.SHL.U32 R0, R0, 0x40, RZ ; /* 0x0000004000007824 */
/* 0x004fca00078e00ff */
/*0130*/ LOP3.LUT R9, R7, R0, RZ, 0xfc, !PT ; /* 0x0000000007097212 */
/* 0x000fca00078efcff */
/*0140*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x0003e8000c101104 */
/*0150*/ LDG.E.U8 R0, [R4.64+0x2] ; /* 0x0000020404007981 */
/* 0x000ea4000c1e1100 */
/*0160*/ IMAD.SHL.U32 R0, R0, 0x20, RZ ; /* 0x0000002000007824 */
/* 0x004fca00078e00ff */
/*0170*/ LOP3.LUT R11, R9, R0, RZ, 0xfc, !PT ; /* 0x00000000090b7212 */
/* 0x000fca00078efcff */
/*0180*/ STG.E.U8 [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x0005e8000c101104 */
/*0190*/ LDG.E.U8 R0, [R4.64+0x3] ; /* 0x0000030404007981 */
/* 0x000ee4000c1e1100 */
/*01a0*/ IMAD.SHL.U32 R0, R0, 0x10, RZ ; /* 0x0000001000007824 */
/* 0x008fca00078e00ff */
/*01b0*/ LOP3.LUT R7, R11, R0, RZ, 0xfc, !PT ; /* 0x000000000b077212 */
/* 0x001fca00078efcff */
/*01c0*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101104 */
/*01d0*/ LDG.E.U8 R0, [R4.64+0x4] ; /* 0x0000040404007981 */
/* 0x000ee4000c1e1100 */
/*01e0*/ IMAD.SHL.U32 R0, R0, 0x8, RZ ; /* 0x0000000800007824 */
/* 0x008fca00078e00ff */
/*01f0*/ LOP3.LUT R9, R7, R0, RZ, 0xfc, !PT ; /* 0x0000000007097212 */
/* 0x002fca00078efcff */
/*0200*/ STG.E.U8 [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101104 */
/*0210*/ LDG.E.U8 R0, [R4.64+0x5] ; /* 0x0000050404007981 */
/* 0x000ee4000c1e1100 */
/*0220*/ IMAD.SHL.U32 R0, R0, 0x4, RZ ; /* 0x0000000400007824 */
/* 0x008fca00078e00ff */
/*0230*/ LOP3.LUT R11, R9, R0, RZ, 0xfc, !PT ; /* 0x00000000090b7212 */
/* 0x004fca00078efcff */
/*0240*/ STG.E.U8 [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101104 */
/*0250*/ LDG.E.U8 R0, [R4.64+0x6] ; /* 0x0000060404007981 */
/* 0x000ea4000c1e1100 */
/*0260*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x004fca00078e00ff */
/*0270*/ LOP3.LUT R7, R11, R0, RZ, 0xfc, !PT ; /* 0x000000000b077212 */
/* 0x001fca00078efcff */
/*0280*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe8000c101104 */
/*0290*/ LDG.E.U8 R0, [R4.64+0x7] ; /* 0x0000070404007981 */
/* 0x000ea4000c1e1100 */
/*02a0*/ LOP3.LUT R13, R7, R0, RZ, 0xfc, !PT ; /* 0x00000000070d7212 */
/* 0x004fca00078efcff */
/*02b0*/ STG.E.U8 [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe2000c101104 */
/*02c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02d0*/ BRA 0x2d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13genByteStreamPcPbPmS1_S0_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.U32.AND.EX P0, PT, RZ, c[0x0][0x18c], PT, P0 ; /* 0x00006300ff007a0c */
/* 0x000fda0003f06100 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R4, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000047a10 */
/* 0x000fe20007f1e0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0090*/ IMAD.X R5, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff057624 */
/* 0x000fca00000e06ff */
/*00a0*/ LDG.E.U8 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe200078e00ff */
/*00c0*/ PRMT R8, R4, 0x8880, RZ ; /* 0x0000888004087816 */
/* 0x004fca00000000ff */
/*00d0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fcc00078e0209 */
/*00e0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*00f0*/ LEA R2, P1, R0, c[0x0][0x178], 0x3 ; /* 0x00005e0000027a11 */
/* 0x000fc800078218ff */
/*0100*/ LEA.HI.X R3, R0, c[0x0][0x17c], RZ, 0x3, P1 ; /* 0x00005f0000037a11 */
/* 0x000fe400008f1cff */
/*0110*/ ISETP.NE.U32.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x004fc80003f05070 */
/*0120*/ ISETP.NE.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0003f05300 */
/*0130*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0140*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f62000c1e1b00 */
/*0150*/ IADD3 R0, P0, R8.reuse, -0x1, RZ ; /* 0xffffffff08007810 */
/* 0x040fe20007f1e0ff */
/*0160*/ BSSY B0, 0x400 ; /* 0x0000029000007945 */
/* 0x000fe20003800000 */
/*0170*/ LOP3.LUT R6, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308067812 */
/* 0x000fe200078ec0ff */
/*0180*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e00ff */
/*0190*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*01a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*01b0*/ IADD3.X R0, R9, -0x1, RZ, P0, !PT ; /* 0xffffffff09007810 */
/* 0x000fe400007fe4ff */
/*01c0*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05070 */
/*01d0*/ ISETP.GE.U32.AND.EX P1, PT, R0, RZ, PT, P1 ; /* 0x000000ff0000720c */
/* 0x000fc40003f26110 */
/*01e0*/ PRMT R13, R4, 0x8880, RZ ; /* 0x00008880040d7816 */
/* 0x000fe400000000ff */
/*01f0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40003f05300 */
/*0200*/ SHF.R.S32.HI R0, RZ, 0x1f, R13 ; /* 0x0000001fff007819 */
/* 0x000fce000001140d */
/*0210*/ @!P1 BRA 0x3f0 ; /* 0x000001d000009947 */
/* 0x000fea0003800000 */
/*0220*/ IMAD.MOV.U32 R4, RZ, RZ, 0xff ; /* 0x000000ffff047424 */
/* 0x000fe200078e00ff */
/*0230*/ IADD3 R25, P1, -R8, R6, RZ ; /* 0x0000000608197210 */
/* 0x000fe20007f3e1ff */
/*0240*/ IMAD R11, R0, 0xff, RZ ; /* 0x000000ff000b7824 */
/* 0x000fe200078e02ff */
/*0250*/ IADD3 R23, P2, R2, c[0x0][0x180], RZ ; /* 0x0000600002177a10 */
/* 0x020fe20007f5e0ff */
/*0260*/ IMAD.WIDE.U32 R4, R13, R4, c[0x0][0x168] ; /* 0x00005a000d047625 */
/* 0x000fc600078e0004 */
/*0270*/ IADD3.X R16, R3, c[0x0][0x184], RZ, P2, !PT ; /* 0x0000610003107a10 */
/* 0x000fe200017fe4ff */
/*0280*/ IMAD.X R20, RZ, RZ, ~R9, P1 ; /* 0x000000ffff147224 */
/* 0x000fe400008e0e09 */
/*0290*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e00ff */
/*02a0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.IADD R18, R5, 0x1, R11 ; /* 0x0000000105127824 */
/* 0x000fe400078e020b */
/*02c0*/ IADD3 R10, P1, R12, R4, RZ ; /* 0x000000040c0a7210 */
/* 0x000fca0007f3e0ff */
/*02d0*/ IMAD.X R11, R7, 0x1, R18, P1 ; /* 0x00000001070b7824 */
/* 0x000fca00008e0612 */
/*02e0*/ LDG.E.U8 R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x001ea2000c1e1100 */
/*02f0*/ IADD3 R8, P1, R12, R23, RZ ; /* 0x000000170c087210 */
/* 0x000fca0007f3e0ff */
/*0300*/ IMAD.X R9, R7, 0x1, R16, P1 ; /* 0x0000000107097824 */
/* 0x000fca00008e0610 */
/*0310*/ STG.E.U8 [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0041e8000c101104 */
/*0320*/ LDG.E.U8 R17, [R10.64+0x1] ; /* 0x000001040a117981 */
/* 0x000ea8000c1e1100 */
/*0330*/ STG.E.U8 [R8.64+0x1], R17 ; /* 0x0000011108007986 */
/* 0x0041e8000c101104 */
/*0340*/ LDG.E.U8 R19, [R10.64+0x2] ; /* 0x000002040a137981 */
/* 0x000ea2000c1e1100 */
/*0350*/ IADD3 R12, P1, R12, 0x4, RZ ; /* 0x000000040c0c7810 */
/* 0x000fc60007f3e0ff */
/*0360*/ STG.E.U8 [R8.64+0x2], R19 ; /* 0x0000021308007986 */
/* 0x0041e8000c101104 */
/*0370*/ LDG.E.U8 R21, [R10.64+0x3] ; /* 0x000003040a157981 */
/* 0x000ea2000c1e1100 */
/*0380*/ IADD3 R14, P2, R12, R25, RZ ; /* 0x000000190c0e7210 */
/* 0x000fe20007f5e0ff */
/*0390*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fc600008e0607 */
/*03a0*/ ISETP.NE.U32.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25070 */
/*03b0*/ IMAD.X R14, R7, 0x1, R20, P2 ; /* 0x00000001070e7824 */
/* 0x000fca00010e0614 */
/*03c0*/ ISETP.NE.AND.EX P1, PT, R14, RZ, PT, P1 ; /* 0x000000ff0e00720c */
/* 0x000fe20003f25310 */
/*03d0*/ STG.E.U8 [R8.64+0x3], R21 ; /* 0x0000031508007986 */
/* 0x0041d8000c101104 */
/*03e0*/ @P1 BRA 0x2c0 ; /* 0xfffffed000001947 */
/* 0x000fea000383ffff */
/*03f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0400*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0410*/ IMAD.MOV.U32 R4, RZ, RZ, R12 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000c */
/*0420*/ IADD3 R12, P0, P1, R12, c[0x0][0x180], R2 ; /* 0x000060000c0c7a10 */
/* 0x020fe2000791e002 */
/*0430*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0440*/ IADD3 R6, P3, RZ, -R6, RZ ; /* 0x80000006ff067210 */
/* 0x000fe20007f7e0ff */
/*0450*/ IMAD R9, R0, 0xff, RZ ; /* 0x000000ff00097824 */
/* 0x001fe400078e02ff */
/*0460*/ IMAD.WIDE.U32 R4, R13, 0xff, R4 ; /* 0x000000ff0d047825 */
/* 0x000fe200078e0004 */
/*0470*/ IADD3.X R13, R7, c[0x0][0x184], R3, P0, P1 ; /* 0x00006100070d7a10 */
/* 0x000fc600007e2403 */
/*0480*/ IMAD.X R0, RZ, RZ, -0x1, P3 ; /* 0xffffffffff007424 */
/* 0x000fe200018e06ff */
/*0490*/ IADD3 R4, P2, R4, c[0x0][0x168], RZ ; /* 0x00005a0004047a10 */
/* 0x000fc80007f5e0ff */
/*04a0*/ IADD3.X R7, R9, c[0x0][0x16c], R5, P2, !PT ; /* 0x00005b0009077a10 */
/* 0x000fc600017fe405 */
/*04b0*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0004 */
/*04c0*/ IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0007 */
/*04d0*/ LDG.E.U8 R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x0000a2000c1e1100 */
/*04e0*/ IADD3 R6, P0, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007f1e0ff */
/*04f0*/ IADD3 R4, P2, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fc60007f5e0ff */
/*0500*/ IMAD.X R0, RZ, RZ, R0, P0 ; /* 0x000000ffff007224 */
/* 0x000fe200000e0600 */
/*0510*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05070 */
/*0520*/ IMAD.X R7, RZ, RZ, R7, P2 ; /* 0x000000ffff077224 */
/* 0x000fe400010e0607 */
/*0530*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x001fe200078e000c */
/*0540*/ ISETP.NE.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe20003f05300 */
/*0550*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000d */
/*0560*/ IADD3 R12, P1, R12, 0x1, RZ ; /* 0x000000010c0c7810 */
/* 0x000fca0007f3e0ff */
/*0570*/ IMAD.X R13, RZ, RZ, R13, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e060d */
/*0580*/ STG.E.U8 [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0041ea000c101104 */
/*0590*/ @P0 BRA 0x4b0 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*05a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05b0*/ BRA 0x5b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9prefixSumPcPmS0_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.WIDE.U32 R2, R0, 0x2, RZ ; /* 0x0000000200027825 */
/* 0x000fca00078e00ff */
/*0070*/ LOP3.LUT R4, R2, 0x1, RZ, 0xfc, !PT ; /* 0x0000000102047812 */
/* 0x000fc800078efcff */
/*0080*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc80003f26070 */
/*0090*/ ISETP.GE.U32.AND.EX P1, PT, R3, c[0x0][0x17c], PT, P1 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f26110 */
/*00a0*/ @!P1 IADD3 R10, P0, R2, c[0x0][0x160], RZ ; /* 0x00005800020a9a10 */
/* 0x000fc80007f1e0ff */
/*00b0*/ @!P1 IADD3.X R11, R3, c[0x0][0x164], RZ, P0, !PT ; /* 0x00005900030b9a10 */
/* 0x000fca00007fe4ff */
/*00c0*/ @!P1 LDG.E.S8 R6, [R10.64] ; /* 0x000000060a069981 */
/* 0x000ea2000c1e1300 */
/*00d0*/ @!P1 IMAD.MOV.U32 R15, RZ, RZ, 0x8 ; /* 0x00000008ff0f9424 */
/* 0x000fe400078e00ff */
/*00e0*/ @!P1 IMAD.MOV.U32 R13, RZ, RZ, 0x10 ; /* 0x00000010ff0d9424 */
/* 0x000fe400078e00ff */
/*00f0*/ @!P1 IMAD.WIDE R6, R6, R15, c[0x0][0x168] ; /* 0x00005a0006069625 */
/* 0x004fcc00078e020f */
/*0100*/ @!P1 LDG.E.64 R6, [R6.64] ; /* 0x0000000606069981 */
/* 0x000ea2000c1e1b00 */
/*0110*/ @!P1 IMAD.WIDE.U32 R12, R0, R13, c[0x0][0x170] ; /* 0x00005c00000c9625 */
/* 0x000fca00078e000d */
/*0120*/ @!P1 STG.E.64 [R12.64], R6 ; /* 0x000000060c009986 */
/* 0x0041e8000c101b06 */
/*0130*/ @!P1 LDG.E.S8 R14, [R10.64+0x1] ; /* 0x000001060a0e9981 */
/* 0x000ea2000c1e1300 */
/*0140*/ USHF.R.U64 UR4, UR4, 0x1, UR5 ; /* 0x0000000104047899 */
/* 0x000fe40008001205 */
/*0150*/ USHF.R.U32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe20008011605 */
/*0160*/ ISETP.NE.AND P3, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc60003f65270 */
/*0170*/ ISETP.NE.U32.AND P2, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf45070 */
/*0180*/ @!P1 IMAD.WIDE R14, R14, R15, c[0x0][0x168] ; /* 0x00005a000e0e9625 */
/* 0x004fcc00078e020f */
/*0190*/ @!P1 LDG.E.64 R14, [R14.64] ; /* 0x000000060e0e9981 */
/* 0x000ea2000c1e1b00 */
/*01a0*/ ISETP.NE.AND.EX P2, PT, RZ, UR5, PT, P2 ; /* 0x00000005ff007c0c */
/* 0x000fe2000bf45320 */
/*01b0*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff097624 */
/* 0x000fe400078e00ff */
/*01d0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe200078e00ff */
/*01e0*/ @!P3 LEA R6, P4, R8.reuse, c[0x0][0x170], 0x3 ; /* 0x00005c000806ba11 */
/* 0x041fe400078818ff */
/*01f0*/ ISETP.GE.U32.AND P0, PT, R8.reuse, 0x2, PT ; /* 0x000000020800780c */
/* 0x040fe40003f06070 */
/*0200*/ @!P3 LEA.HI.X R7, R8, c[0x0][0x174], R9, 0x3, P4 ; /* 0x00005d000807ba11 */
/* 0x000fe200020f1c09 */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*0220*/ @!P1 STG.E.64 [R12.64+0x8], R14 ; /* 0x0000080e0c009986 */
/* 0x0041e8000c101b06 */
/*0230*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0240*/ @!P2 BRA 0x3f0 ; /* 0x000001a00000a947 */
/* 0x000fea0003800000 */
/*0250*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fe400078e00ff */
/*0260*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fc400078e00ff */
/*0270*/ IMAD.U32 R10, RZ, RZ, UR5 ; /* 0x00000005ff0a7e24 */
/* 0x000fe2000f8e00ff */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.LT.U32.AND P1, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc8000bf21070 */
/*02a0*/ ISETP.GT.U32.AND.EX P1, PT, R10, RZ, PT, P1 ; /* 0x000000ff0a00720c */
/* 0x000fda0003f24110 */
/*02b0*/ @P1 IMAD R12, R8, R4.reuse, RZ ; /* 0x00000004080c1224 */
/* 0x081fe400078e02ff */
/*02c0*/ @P1 IMAD.WIDE.U32 R10, R5, R4, RZ ; /* 0x00000004050a1225 */
/* 0x000fc800078e00ff */
/*02d0*/ @P1 IMAD R13, R3, R5, R12 ; /* 0x00000005030d1224 */
/* 0x000fe200078e020c */
/*02e0*/ @P1 LEA R12, P2, R10, c[0x0][0x170], 0x3 ; /* 0x00005c000a0c1a11 */
/* 0x000fc600078418ff */
/*02f0*/ @P1 IMAD.IADD R11, R11, 0x1, R13 ; /* 0x000000010b0b1824 */
/* 0x000fe200078e020d */
/*0300*/ @P1 LEA R14, P4, R5, R12, 0x3 ; /* 0x0000000c050e1211 */
/* 0x000fc800078818ff */
/*0310*/ @P1 LEA.HI.X R13, R10, c[0x0][0x174], R11, 0x3, P2 ; /* 0x00005d000a0d1a11 */
/* 0x000fc800010f1c0b */
/*0320*/ @P1 LEA.HI.X R15, R5.reuse, R13, R8.reuse, 0x3, P4 ; /* 0x0000000d050f1211 */
/* 0x140fe400020f1c08 */
/*0330*/ @P1 LDG.E.64 R12, [R12.64+-0x8] ; /* 0xfffff8060c0c1981 */
/* 0x000ea8000c1e1b00 */
/*0340*/ @P1 LDG.E.64 R10, [R14.64+-0x8] ; /* 0xfffff8060e0a1981 */
/* 0x000ea2000c1e1b00 */
/*0350*/ USHF.R.U64 UR4, UR4, 0x1, UR5 ; /* 0x0000000104047899 */
/* 0x000fe20008001205 */
/*0360*/ SHF.L.U64.HI R8, R5.reuse, 0x1, R8 ; /* 0x0000000105087819 */
/* 0x040fe20000010208 */
/*0370*/ USHF.R.U32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe20008011605 */
/*0380*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*0390*/ @P1 IADD3 R10, P2, R10, R12, RZ ; /* 0x0000000c0a0a1210 */
/* 0x004fca0007f5e0ff */
/*03a0*/ @P1 IMAD.X R11, R11, 0x1, R13, P2 ; /* 0x000000010b0b1824 */
/* 0x000fca00010e060d */
/*03b0*/ @P1 STG.E.64 [R14.64+-0x8], R10 ; /* 0xfffff80a0e001986 */
/* 0x0001e2000c101b06 */
/*03c0*/ ISETP.NE.U32.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fc8000bf25070 */
/*03d0*/ ISETP.NE.AND.EX P1, PT, RZ, UR5, PT, P1 ; /* 0x00000005ff007c0c */
/* 0x000fda000bf25310 */
/*03e0*/ @P1 BRA 0x270 ; /* 0xfffffe8000001947 */
/* 0x001fea000383ffff */
/*03f0*/ ISETP.GE.U32.AND.EX P0, PT, R9, RZ, PT, P0 ; /* 0x000000ff0900720c */
/* 0x000fe20003f06100 */
/*0400*/ @!P3 STG.E.64 [R6.64+-0x8], RZ ; /* 0xfffff8ff0600b986 */
/* 0x0003d8000c101b06 */
/*0410*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0420*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x002fe400078e00ff */
/*0430*/ IMAD.MOV.U32 R18, RZ, RZ, RZ ; /* 0x000000ffff127224 */
/* 0x000fe400078e00ff */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0450*/ ISETP.GT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fe40003f04070 */
/*0460*/ SHF.R.U64 R5, R5, 0x1, R8.reuse ; /* 0x0000000105057819 */
/* 0x100fe40000001208 */
/*0470*/ ISETP.GT.U32.AND.EX P0, PT, R18, RZ, PT, P0 ; /* 0x000000ff1200720c */
/* 0x000fe40003f04100 */
/*0480*/ SHF.R.U32.HI R8, RZ, 0x1, R8 ; /* 0x00000001ff087819 */
/* 0x000fd60000011608 */
/*0490*/ @P0 IMAD R6, R8, R4.reuse, RZ ; /* 0x0000000408060224 */
/* 0x080fe400078e02ff */
/*04a0*/ @P0 IMAD.WIDE.U32 R10, R5, R4, RZ ; /* 0x00000004050a0225 */
/* 0x000fc800078e00ff */
/*04b0*/ @P0 IMAD R7, R3, R5, R6 ; /* 0x0000000503070224 */
/* 0x000fe200078e0206 */
/*04c0*/ @P0 LEA R16, P1, R10, c[0x0][0x170], 0x3 ; /* 0x00005c000a100a11 */
/* 0x000fc600078218ff */
/*04d0*/ @P0 IMAD.IADD R7, R11, 0x1, R7 ; /* 0x000000010b070824 */
/* 0x000fe200078e0207 */
/*04e0*/ @P0 LEA R6, P2, R5, R16, 0x3 ; /* 0x0000001005060211 */
/* 0x000fc800078418ff */
/*04f0*/ @P0 LEA.HI.X R17, R10, c[0x0][0x174], R7, 0x3, P1 ; /* 0x00005d000a110a11 */
/* 0x000fc800008f1c07 */
/*0500*/ @P0 LEA.HI.X R7, R5, R17, R8, 0x3, P2 ; /* 0x0000001105070211 */
/* 0x000fe200010f1c08 */
/*0510*/ @P0 LDG.E.64 R10, [R16.64+-0x8] ; /* 0xfffff806100a0981 */
/* 0x000ea8000c1e1b00 */
/*0520*/ @P0 LDG.E.64 R12, [R6.64+-0x8] ; /* 0xfffff806060c0981 */
/* 0x001ee8000c1e1b00 */
/*0530*/ @P0 STG.E.64 [R16.64+-0x8], R12 ; /* 0xfffff80c10000986 */
/* 0x0081e8000c101b06 */
/*0540*/ @P0 LDG.E.64 R14, [R6.64+-0x8] ; /* 0xfffff806060e0981 */
/* 0x000ea2000c1e1b00 */
/*0550*/ SHF.L.U64.HI R18, R9.reuse, 0x1, R18 ; /* 0x0000000109127819 */
/* 0x040fe20000010212 */
/*0560*/ IMAD.SHL.U32 R9, R9, 0x2, RZ ; /* 0x0000000209097824 */
/* 0x000fe200078e00ff */
/*0570*/ @P0 IADD3 R10, P1, R10, R14, RZ ; /* 0x0000000e0a0a0210 */
/* 0x004fca0007f3e0ff */
/*0580*/ @P0 IMAD.X R11, R11, 0x1, R15, P1 ; /* 0x000000010b0b0824 */
/* 0x000fca00008e060f */
/*0590*/ @P0 STG.E.64 [R6.64+-0x8], R10 ; /* 0xfffff80a06000986 */
/* 0x0001e2000c101b06 */
/*05a0*/ ISETP.GE.U32.AND P0, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fc80003f06070 */
/*05b0*/ ISETP.GE.U32.AND.EX P0, PT, R18, c[0x0][0x17c], PT, P0 ; /* 0x00005f0012007a0c */
/* 0x000fda0003f06100 */
/*05c0*/ @!P0 BRA 0x440 ; /* 0xfffffe7000008947 */
/* 0x001fea000383ffff */
/*05d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05e0*/ BRA 0x5e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define SYMBOL_NUM 256
#define MAX_CODE_LEN (SYMBOL_NUM - 1)
#define GRID_X (1u << 12)
#define GRID_Y 1
#define BLOCK_X (1u << 10)
#define BLOCK_Y 1
#define RAW_BUFF_SIZE (GRID_X * GRID_Y * BLOCK_X * BLOCK_Y)
#define DEF_IDX \
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
#define CUDA_SAFE_CALL(func) \
do { \
cudaError_t err = (func); \
if (err != cudaSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
cudaGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len);
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len);
int main(int argc, char** argv)
{
if (argc != 3) {
fprintf(stderr, "Usage: %s raw_data huffman_table\n", argv[0]);
exit(EXIT_FAILURE);
}
// Read raw data
char* raw_data_h = (char*)calloc(RAW_BUFF_SIZE, 1);
size_t raw_len = 0;
{
printf("Reading raw data ... ");
FILE* raw_file = fopen(argv[1], "r");
size_t r;
while ((r = fread(
raw_data_h + raw_len, 1, RAW_BUFF_SIZE - raw_len, raw_file))
!= 0) {
raw_len += r;
}
fclose(raw_file);
printf("done. Read %zu bytes.\n", raw_len);
}
char* raw_data;
CUDA_SAFE_CALL(cudaMalloc((void**)&raw_data, raw_len));
CUDA_SAFE_CALL(cudaMemcpy(
raw_data, raw_data_h, raw_len, cudaMemcpyHostToDevice));
// Read Huffman table
bool* code_h = (bool*)calloc(MAX_CODE_LEN * SYMBOL_NUM, sizeof(bool));
size_t* code_len_h = (size_t*)calloc(SYMBOL_NUM, sizeof(size_t));
{
printf("Reading Huffman table ... ");
FILE* hufftable_file = fopen(argv[2], "r");
int c;
while (fscanf(hufftable_file, "%d", &c) != EOF) {
size_t len;
int _ = fscanf(hufftable_file, "%zu", &len);
code_len_h[c] = len;
for (size_t j = 0; j < len; j++) {
int b;
int _ = fscanf(hufftable_file, "%d", &b);
code_h[c * MAX_CODE_LEN + j] = b;
}
}
fclose(hufftable_file);
printf("done.\n");
}
bool* code;
CUDA_SAFE_CALL(cudaMalloc(
(void**)&code, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool)));
CUDA_SAFE_CALL(cudaMemcpy(
code, code_h, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool),
cudaMemcpyHostToDevice));
size_t* code_len;
CUDA_SAFE_CALL(cudaMalloc((void**)&code_len, SYMBOL_NUM * sizeof(size_t)));
CUDA_SAFE_CALL(cudaMemcpy(
code_len, code_len_h, SYMBOL_NUM * sizeof(size_t),
cudaMemcpyHostToDevice));
// free(code_h);
// Run on CUDA
dim3 grid(GRID_X, GRID_Y);
dim3 block(BLOCK_X, BLOCK_Y, 1);
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
// Prefix sum of code length
size_t* len_ps_h = (size_t*)calloc(raw_len, sizeof(size_t));
prefixSumHost(raw_data_h, code_len_h, len_ps_h, raw_len);
// prefixSum<<<grid, block>>>(raw_data, code_len, len_ps, raw_len);
CUDA_SAFE_CALL(cudaThreadSynchronize());
size_t* len_ps;
CUDA_SAFE_CALL(cudaMalloc((void**)&len_ps, raw_len * sizeof(size_t)));
CUDA_SAFE_CALL(cudaMemcpy(
len_ps, len_ps_h, raw_len * sizeof(size_t), cudaMemcpyHostToDevice));
/* {
size_t* len_ps_h = (size_t*)malloc(sizeof(size_t) * raw_len);
CUDA_SAFE_CALL(cudaMemcpy(
len_ps_h, len_ps, sizeof(size_t) * raw_len, cudaMemcpyDeviceToHost));
for (size_t i = 0; i < raw_len; i++)
printf("%zu\n", len_ps_h[i]);
} */
size_t len_ps_end;
CUDA_SAFE_CALL(cudaMemcpy(
&len_ps_end, &len_ps[raw_len - 1], sizeof(size_t),
cudaMemcpyDeviceToHost));
size_t bytes_len = len_ps_end + code_len_h[raw_data_h[raw_len - 1]];
printf("bytes len: %zu\n", bytes_len);
// free(code_len_h);
// free(raw_data_h);
if (bytes_len > RAW_BUFF_SIZE) {
fprintf(stderr, "Bytes stream overflowed\n");
exit(EXIT_FAILURE);
}
bool* bytes;
CUDA_SAFE_CALL(cudaMalloc((void**)&bytes, sizeof(bool) * bytes_len));
genByteStream<<<grid, block>>>(
raw_data, code, code_len, len_ps, bytes, raw_len);
CUDA_SAFE_CALL(cudaThreadSynchronize());
// CUDA_SAFE_CALL(cudaFree(len_ps));
// CUDA_SAFE_CALL(cudaFree(code_len));
// CUDA_SAFE_CALL(cudaFree(code));
// CUDA_SAFE_CALL(cudaFree(raw_data));
uint8_t* bits;
size_t bits_len = bytes_len / 8 + 1;
printf("bits len: %zu\n", bits_len);
CUDA_SAFE_CALL(cudaMalloc((void**)&bits, bits_len));
compressByteStream<<<grid, block>>>(bytes, bits, bits_len);
CUDA_SAFE_CALL(cudaThreadSynchronize());
// CUDA_SAFE_CALL(cudaFree(bits));
// CUDA_SAFE_CALL(cudaFree(bytes));
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("bytes: %zu sec: %lf bytes/sec: %lf\n",
raw_len, sec, raw_len / sec);
return 0;
}
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
len_ps[0] = 0;
for (size_t i = 1; i < raw_len; i++) {
len_ps[i] = len_ps[i - 1] + code_len[raw_data[i - 1]];
}
}
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
DEF_IDX;
if (2 * idx + 1 < raw_len) {
len_ps[2 * idx] = code_len[raw_data[2 * idx]];
len_ps[2 * idx + 1] = code_len[raw_data[2 * idx + 1]];
}
__syncthreads();
// build sum in place up the tree
size_t offset = 1;
for (size_t d = raw_len >> 1; d > 0; d >>= 1) {
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
len_ps[bi] += len_ps[ai];
}
offset *= 2;
}
// clear the last element
if (idx == 0)
len_ps[raw_len - 1] = 0;
// traverse down tree & build scan
for (size_t d = 1; d < raw_len; d *= 2) {
offset >>= 1;
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
size_t t = len_ps[ai];
len_ps[ai] = len_ps[bi];
len_ps[bi] += t;
}
}
}
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len)
{
DEF_IDX;
if (idx < raw_len) {
size_t start_pos = len_ps[idx];
char symbol = raw_data[idx];
for (size_t i = 0, len = code_len[symbol]; i < len; i++) {
bytes[start_pos + i] = code[symbol * MAX_CODE_LEN + i];
}
}
}
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len)
{
DEF_IDX;
if (idx < bits_len) {
for (size_t i = 0; i < 8; i++) {
bits[idx] |= (uint8_t)bytes[8 * idx + i] << (7 - i);
}
}
} | .file "tmpxft_0001922b_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13prefixSumHostPcPmS0_m
.type _Z13prefixSumHostPcPmS0_m, @function
_Z13prefixSumHostPcPmS0_m:
.LFB2058:
.cfi_startproc
endbr64
movq $0, (%rdx)
cmpq $1, %rcx
jbe .L3
movl $1, %eax
.L5:
movsbq -1(%rdi,%rax), %r9
movq -8(%rdx,%rax,8), %r8
addq (%rsi,%r9,8), %r8
movq %r8, (%rdx,%rax,8)
addq $1, %rax
cmpq %rax, %rcx
jne .L5
.L3:
ret
.cfi_endproc
.LFE2058:
.size _Z13prefixSumHostPcPmS0_m, .-_Z13prefixSumHostPcPmS0_m
.globl _Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m
.type _Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m, @function
_Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9prefixSumPcPmS0_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m, .-_Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m
.globl _Z9prefixSumPcPmS0_m
.type _Z9prefixSumPcPmS0_m, @function
_Z9prefixSumPcPmS0_m:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9prefixSumPcPmS0_m, .-_Z9prefixSumPcPmS0_m
.globl _Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m
.type _Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m, @function
_Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13genByteStreamPcPbPmS1_S0_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m, .-_Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m
.globl _Z13genByteStreamPcPbPmS1_S0_m
.type _Z13genByteStreamPcPbPmS1_S0_m, @function
_Z13genByteStreamPcPbPmS1_S0_m:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13genByteStreamPcPbPmS1_S0_m, .-_Z13genByteStreamPcPbPmS1_S0_m
.globl _Z41__device_stub__Z18compressByteStreamPbPhmPbPhm
.type _Z41__device_stub__Z18compressByteStreamPbPhmPbPhm, @function
_Z41__device_stub__Z18compressByteStreamPbPhmPbPhm:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18compressByteStreamPbPhm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z41__device_stub__Z18compressByteStreamPbPhmPbPhm, .-_Z41__device_stub__Z18compressByteStreamPbPhmPbPhm
.globl _Z18compressByteStreamPbPhm
.type _Z18compressByteStreamPbPhm, @function
_Z18compressByteStreamPbPhm:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18compressByteStreamPbPhmPbPhm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z18compressByteStreamPbPhm, .-_Z18compressByteStreamPbPhm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: %s raw_data huffman_table\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Reading raw data ... "
.LC2:
.string "r"
.LC3:
.string "done. Read %zu bytes.\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ordovicia/huffman-coding-cuda/master/main.cu"
.align 8
.LC5:
.string "[Error] %s (error code: %d) at %s line %d\n"
.section .rodata.str1.1
.LC6:
.string "Reading Huffman table ... "
.LC7:
.string "%zu"
.LC8:
.string "%d"
.LC9:
.string "done.\n"
.LC10:
.string "bytes len: %zu\n"
.LC11:
.string "Bytes stream overflowed\n"
.LC12:
.string "bits len: %zu\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "bytes: %zu sec: %lf bytes/sec: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L61
movl $1, %esi
movl $4194304, %edi
call calloc@PLT
movq %rax, (%rsp)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rbx), %rdi
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl $0, %r13d
movl $4194304, %r12d
jmp .L33
.L61:
movq (%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
addq %r15, %r13
.L33:
movq %r12, %rcx
subq %r13, %rcx
movl $4194304, %esi
cmpq %rsi, %r13
cmovnb %r13, %rsi
subq %r13, %rsi
movq (%rsp), %rax
leaq (%rax,%r13), %rdi
movq %rbp, %r8
movl $1, %edx
call __fread_chk@PLT
movq %rax, %r15
testq %rax, %rax
jne .L34
movq %rbp, %rdi
call fclose@PLT
movq %r13, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L62
movl $1, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L63
movl $1, %esi
movl $65280, %edi
call calloc@PLT
movq %rax, %r14
movl $8, %esi
movl $256, %edi
call calloc@PLT
movq %rax, 8(%rsp)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rbx), %rdi
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
leaq 100(%rsp), %rax
movq %rax, 16(%rsp)
leaq .LC8(%rip), %r12
leaq 128(%rsp), %rax
movq %rax, 24(%rsp)
.L37:
movq 16(%rsp), %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L64
movq 24(%rsp), %rdx
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq 128(%rsp), %rax
movslq 100(%rsp), %rdx
movq 8(%rsp), %rcx
movq %rax, (%rcx,%rdx,8)
testq %rax, %rax
je .L37
movq %r15, %rbx
.L39:
leaq 112(%rsp), %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 100(%rsp), %edx
movl %edx, %eax
sall $8, %eax
subl %edx, %eax
cltq
leaq (%r14,%rbx), %rdx
cmpl $0, 112(%rsp)
setne (%rdx,%rax)
addq $1, %rbx
cmpq 128(%rsp), %rbx
jb .L39
jmp .L37
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $65
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L63:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $66
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L64:
.cfi_restore_state
movq %rbp, %rdi
call fclose@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rdi
movl $65280, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L65
movl $1, %ecx
movl $65280, %edx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L66
leaq 48(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L67
movl $1, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L68
movl $4096, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1024, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $8, %esi
movq %r13, %rdi
call calloc@PLT
movq %rax, %rbx
movq %r13, %rcx
movq %rax, %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z13prefixSumHostPcPmS0_m
call cudaThreadSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L69
leaq 0(,%r13,8), %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L70
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L71
movq 56(%rsp), %rax
leaq -8(%rax,%rbp), %rsi
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L72
movq (%rsp), %rax
movsbq -1(%rax,%r13), %rax
movq 64(%rsp), %rbx
movq 8(%rsp), %rcx
addq (%rcx,%rax,8), %rbx
movq %rbx, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq $4194304, %rbx
ja .L73
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L74
movl 108(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movq 88(%rsp), %rdi
movl 96(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L51:
call cudaThreadSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L76
shrq $3, %rbx
addq $1, %rbx
movq %rbx, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L77
movl 108(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movq 88(%rsp), %rdi
movl 96(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L54:
call cudaThreadSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L79
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 136(%rsp), %rax
subq 120(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC13(%rip), %xmm0
movq 128(%rsp), %rax
subq 112(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
testq %r13, %r13
js .L56
pxor %xmm1, %xmm1
cvtsi2sdq %r13, %xmm1
.L57:
divsd %xmm0, %xmm1
movq %r13, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L80
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $93
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L66:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $95
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L67:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $99
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L68:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $100
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L69:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $118
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L70:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $121
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %r12d, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L71:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $122
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L72:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $134
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L73:
.cfi_restore_state
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $149
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L75:
.cfi_restore_state
movq %r13, %r9
movq 72(%rsp), %r8
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m
jmp .L51
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $152
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L77:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $162
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L78:
.cfi_restore_state
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z41__device_stub__Z18compressByteStreamPbPhmPbPhm
jmp .L54
.L79:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $164
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L56:
.cfi_restore_state
movq %r13, %rax
shrq %rax
movq %r13, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
jmp .L57
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z18compressByteStreamPbPhm"
.section .rodata.str1.8
.align 8
.LC16:
.string "_Z13genByteStreamPcPbPmS1_S0_m"
.section .rodata.str1.1
.LC17:
.string "_Z9prefixSumPcPmS0_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z18compressByteStreamPbPhm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z13genByteStreamPcPbPmS1_S0_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z9prefixSumPcPmS0_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC13:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define SYMBOL_NUM 256
#define MAX_CODE_LEN (SYMBOL_NUM - 1)
#define GRID_X (1u << 12)
#define GRID_Y 1
#define BLOCK_X (1u << 10)
#define BLOCK_Y 1
#define RAW_BUFF_SIZE (GRID_X * GRID_Y * BLOCK_X * BLOCK_Y)
#define DEF_IDX \
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
#define CUDA_SAFE_CALL(func) \
do { \
cudaError_t err = (func); \
if (err != cudaSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
cudaGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len);
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len);
int main(int argc, char** argv)
{
if (argc != 3) {
fprintf(stderr, "Usage: %s raw_data huffman_table\n", argv[0]);
exit(EXIT_FAILURE);
}
// Read raw data
char* raw_data_h = (char*)calloc(RAW_BUFF_SIZE, 1);
size_t raw_len = 0;
{
printf("Reading raw data ... ");
FILE* raw_file = fopen(argv[1], "r");
size_t r;
while ((r = fread(
raw_data_h + raw_len, 1, RAW_BUFF_SIZE - raw_len, raw_file))
!= 0) {
raw_len += r;
}
fclose(raw_file);
printf("done. Read %zu bytes.\n", raw_len);
}
char* raw_data;
CUDA_SAFE_CALL(cudaMalloc((void**)&raw_data, raw_len));
CUDA_SAFE_CALL(cudaMemcpy(
raw_data, raw_data_h, raw_len, cudaMemcpyHostToDevice));
// Read Huffman table
bool* code_h = (bool*)calloc(MAX_CODE_LEN * SYMBOL_NUM, sizeof(bool));
size_t* code_len_h = (size_t*)calloc(SYMBOL_NUM, sizeof(size_t));
{
printf("Reading Huffman table ... ");
FILE* hufftable_file = fopen(argv[2], "r");
int c;
while (fscanf(hufftable_file, "%d", &c) != EOF) {
size_t len;
int _ = fscanf(hufftable_file, "%zu", &len);
code_len_h[c] = len;
for (size_t j = 0; j < len; j++) {
int b;
int _ = fscanf(hufftable_file, "%d", &b);
code_h[c * MAX_CODE_LEN + j] = b;
}
}
fclose(hufftable_file);
printf("done.\n");
}
bool* code;
CUDA_SAFE_CALL(cudaMalloc(
(void**)&code, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool)));
CUDA_SAFE_CALL(cudaMemcpy(
code, code_h, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool),
cudaMemcpyHostToDevice));
size_t* code_len;
CUDA_SAFE_CALL(cudaMalloc((void**)&code_len, SYMBOL_NUM * sizeof(size_t)));
CUDA_SAFE_CALL(cudaMemcpy(
code_len, code_len_h, SYMBOL_NUM * sizeof(size_t),
cudaMemcpyHostToDevice));
// free(code_h);
// Run on CUDA
dim3 grid(GRID_X, GRID_Y);
dim3 block(BLOCK_X, BLOCK_Y, 1);
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
// Prefix sum of code length
size_t* len_ps_h = (size_t*)calloc(raw_len, sizeof(size_t));
prefixSumHost(raw_data_h, code_len_h, len_ps_h, raw_len);
// prefixSum<<<grid, block>>>(raw_data, code_len, len_ps, raw_len);
CUDA_SAFE_CALL(cudaThreadSynchronize());
size_t* len_ps;
CUDA_SAFE_CALL(cudaMalloc((void**)&len_ps, raw_len * sizeof(size_t)));
CUDA_SAFE_CALL(cudaMemcpy(
len_ps, len_ps_h, raw_len * sizeof(size_t), cudaMemcpyHostToDevice));
/* {
size_t* len_ps_h = (size_t*)malloc(sizeof(size_t) * raw_len);
CUDA_SAFE_CALL(cudaMemcpy(
len_ps_h, len_ps, sizeof(size_t) * raw_len, cudaMemcpyDeviceToHost));
for (size_t i = 0; i < raw_len; i++)
printf("%zu\n", len_ps_h[i]);
} */
size_t len_ps_end;
CUDA_SAFE_CALL(cudaMemcpy(
&len_ps_end, &len_ps[raw_len - 1], sizeof(size_t),
cudaMemcpyDeviceToHost));
size_t bytes_len = len_ps_end + code_len_h[raw_data_h[raw_len - 1]];
printf("bytes len: %zu\n", bytes_len);
// free(code_len_h);
// free(raw_data_h);
if (bytes_len > RAW_BUFF_SIZE) {
fprintf(stderr, "Bytes stream overflowed\n");
exit(EXIT_FAILURE);
}
bool* bytes;
CUDA_SAFE_CALL(cudaMalloc((void**)&bytes, sizeof(bool) * bytes_len));
genByteStream<<<grid, block>>>(
raw_data, code, code_len, len_ps, bytes, raw_len);
CUDA_SAFE_CALL(cudaThreadSynchronize());
// CUDA_SAFE_CALL(cudaFree(len_ps));
// CUDA_SAFE_CALL(cudaFree(code_len));
// CUDA_SAFE_CALL(cudaFree(code));
// CUDA_SAFE_CALL(cudaFree(raw_data));
uint8_t* bits;
size_t bits_len = bytes_len / 8 + 1;
printf("bits len: %zu\n", bits_len);
CUDA_SAFE_CALL(cudaMalloc((void**)&bits, bits_len));
compressByteStream<<<grid, block>>>(bytes, bits, bits_len);
CUDA_SAFE_CALL(cudaThreadSynchronize());
// CUDA_SAFE_CALL(cudaFree(bits));
// CUDA_SAFE_CALL(cudaFree(bytes));
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("bytes: %zu sec: %lf bytes/sec: %lf\n",
raw_len, sec, raw_len / sec);
return 0;
}
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
len_ps[0] = 0;
for (size_t i = 1; i < raw_len; i++) {
len_ps[i] = len_ps[i - 1] + code_len[raw_data[i - 1]];
}
}
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
DEF_IDX;
if (2 * idx + 1 < raw_len) {
len_ps[2 * idx] = code_len[raw_data[2 * idx]];
len_ps[2 * idx + 1] = code_len[raw_data[2 * idx + 1]];
}
__syncthreads();
// build sum in place up the tree
size_t offset = 1;
for (size_t d = raw_len >> 1; d > 0; d >>= 1) {
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
len_ps[bi] += len_ps[ai];
}
offset *= 2;
}
// clear the last element
if (idx == 0)
len_ps[raw_len - 1] = 0;
// traverse down tree & build scan
for (size_t d = 1; d < raw_len; d *= 2) {
offset >>= 1;
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
size_t t = len_ps[ai];
len_ps[ai] = len_ps[bi];
len_ps[bi] += t;
}
}
}
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len)
{
DEF_IDX;
if (idx < raw_len) {
size_t start_pos = len_ps[idx];
char symbol = raw_data[idx];
for (size_t i = 0, len = code_len[symbol]; i < len; i++) {
bytes[start_pos + i] = code[symbol * MAX_CODE_LEN + i];
}
}
}
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len)
{
DEF_IDX;
if (idx < bits_len) {
for (size_t i = 0; i < 8; i++) {
bits[idx] |= (uint8_t)bytes[8 * idx + i] << (7 - i);
}
}
} | #include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define SYMBOL_NUM 256
#define MAX_CODE_LEN (SYMBOL_NUM - 1)
#define GRID_X (1u << 12)
#define GRID_Y 1
#define BLOCK_X (1u << 10)
#define BLOCK_Y 1
#define RAW_BUFF_SIZE (GRID_X * GRID_Y * BLOCK_X * BLOCK_Y)
#define DEF_IDX \
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
#define CUDA_SAFE_CALL(func) \
do { \
hipError_t err = (func); \
if (err != hipSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
hipGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len);
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len);
int main(int argc, char** argv)
{
if (argc != 3) {
fprintf(stderr, "Usage: %s raw_data huffman_table\n", argv[0]);
exit(EXIT_FAILURE);
}
// Read raw data
char* raw_data_h = (char*)calloc(RAW_BUFF_SIZE, 1);
size_t raw_len = 0;
{
printf("Reading raw data ... ");
FILE* raw_file = fopen(argv[1], "r");
size_t r;
while ((r = fread(
raw_data_h + raw_len, 1, RAW_BUFF_SIZE - raw_len, raw_file))
!= 0) {
raw_len += r;
}
fclose(raw_file);
printf("done. Read %zu bytes.\n", raw_len);
}
char* raw_data;
CUDA_SAFE_CALL(hipMalloc((void**)&raw_data, raw_len));
CUDA_SAFE_CALL(hipMemcpy(
raw_data, raw_data_h, raw_len, hipMemcpyHostToDevice));
// Read Huffman table
bool* code_h = (bool*)calloc(MAX_CODE_LEN * SYMBOL_NUM, sizeof(bool));
size_t* code_len_h = (size_t*)calloc(SYMBOL_NUM, sizeof(size_t));
{
printf("Reading Huffman table ... ");
FILE* hufftable_file = fopen(argv[2], "r");
int c;
while (fscanf(hufftable_file, "%d", &c) != EOF) {
size_t len;
int _ = fscanf(hufftable_file, "%zu", &len);
code_len_h[c] = len;
for (size_t j = 0; j < len; j++) {
int b;
int _ = fscanf(hufftable_file, "%d", &b);
code_h[c * MAX_CODE_LEN + j] = b;
}
}
fclose(hufftable_file);
printf("done.\n");
}
bool* code;
CUDA_SAFE_CALL(hipMalloc(
(void**)&code, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool)));
CUDA_SAFE_CALL(hipMemcpy(
code, code_h, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool),
hipMemcpyHostToDevice));
size_t* code_len;
CUDA_SAFE_CALL(hipMalloc((void**)&code_len, SYMBOL_NUM * sizeof(size_t)));
CUDA_SAFE_CALL(hipMemcpy(
code_len, code_len_h, SYMBOL_NUM * sizeof(size_t),
hipMemcpyHostToDevice));
// free(code_h);
// Run on CUDA
dim3 grid(GRID_X, GRID_Y);
dim3 block(BLOCK_X, BLOCK_Y, 1);
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
// Prefix sum of code length
size_t* len_ps_h = (size_t*)calloc(raw_len, sizeof(size_t));
prefixSumHost(raw_data_h, code_len_h, len_ps_h, raw_len);
// prefixSum<<<grid, block>>>(raw_data, code_len, len_ps, raw_len);
CUDA_SAFE_CALL(hipDeviceSynchronize());
size_t* len_ps;
CUDA_SAFE_CALL(hipMalloc((void**)&len_ps, raw_len * sizeof(size_t)));
CUDA_SAFE_CALL(hipMemcpy(
len_ps, len_ps_h, raw_len * sizeof(size_t), hipMemcpyHostToDevice));
/* {
size_t* len_ps_h = (size_t*)malloc(sizeof(size_t) * raw_len);
CUDA_SAFE_CALL(cudaMemcpy(
len_ps_h, len_ps, sizeof(size_t) * raw_len, cudaMemcpyDeviceToHost));
for (size_t i = 0; i < raw_len; i++)
printf("%zu\n", len_ps_h[i]);
} */
size_t len_ps_end;
CUDA_SAFE_CALL(hipMemcpy(
&len_ps_end, &len_ps[raw_len - 1], sizeof(size_t),
hipMemcpyDeviceToHost));
size_t bytes_len = len_ps_end + code_len_h[raw_data_h[raw_len - 1]];
printf("bytes len: %zu\n", bytes_len);
// free(code_len_h);
// free(raw_data_h);
if (bytes_len > RAW_BUFF_SIZE) {
fprintf(stderr, "Bytes stream overflowed\n");
exit(EXIT_FAILURE);
}
bool* bytes;
CUDA_SAFE_CALL(hipMalloc((void**)&bytes, sizeof(bool) * bytes_len));
genByteStream<<<grid, block>>>(
raw_data, code, code_len, len_ps, bytes, raw_len);
CUDA_SAFE_CALL(hipDeviceSynchronize());
// CUDA_SAFE_CALL(cudaFree(len_ps));
// CUDA_SAFE_CALL(cudaFree(code_len));
// CUDA_SAFE_CALL(cudaFree(code));
// CUDA_SAFE_CALL(cudaFree(raw_data));
uint8_t* bits;
size_t bits_len = bytes_len / 8 + 1;
printf("bits len: %zu\n", bits_len);
CUDA_SAFE_CALL(hipMalloc((void**)&bits, bits_len));
compressByteStream<<<grid, block>>>(bytes, bits, bits_len);
CUDA_SAFE_CALL(hipDeviceSynchronize());
// CUDA_SAFE_CALL(cudaFree(bits));
// CUDA_SAFE_CALL(cudaFree(bytes));
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("bytes: %zu sec: %lf bytes/sec: %lf\n",
raw_len, sec, raw_len / sec);
return 0;
}
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
len_ps[0] = 0;
for (size_t i = 1; i < raw_len; i++) {
len_ps[i] = len_ps[i - 1] + code_len[raw_data[i - 1]];
}
}
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
DEF_IDX;
if (2 * idx + 1 < raw_len) {
len_ps[2 * idx] = code_len[raw_data[2 * idx]];
len_ps[2 * idx + 1] = code_len[raw_data[2 * idx + 1]];
}
__syncthreads();
// build sum in place up the tree
size_t offset = 1;
for (size_t d = raw_len >> 1; d > 0; d >>= 1) {
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
len_ps[bi] += len_ps[ai];
}
offset *= 2;
}
// clear the last element
if (idx == 0)
len_ps[raw_len - 1] = 0;
// traverse down tree & build scan
for (size_t d = 1; d < raw_len; d *= 2) {
offset >>= 1;
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
size_t t = len_ps[ai];
len_ps[ai] = len_ps[bi];
len_ps[bi] += t;
}
}
}
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len)
{
DEF_IDX;
if (idx < raw_len) {
size_t start_pos = len_ps[idx];
char symbol = raw_data[idx];
for (size_t i = 0, len = code_len[symbol]; i < len; i++) {
bytes[start_pos + i] = code[symbol * MAX_CODE_LEN + i];
}
}
}
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len)
{
DEF_IDX;
if (idx < bits_len) {
for (size_t i = 0; i < 8; i++) {
bits[idx] |= (uint8_t)bytes[8 * idx + i] << (7 - i);
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define SYMBOL_NUM 256
#define MAX_CODE_LEN (SYMBOL_NUM - 1)
#define GRID_X (1u << 12)
#define GRID_Y 1
#define BLOCK_X (1u << 10)
#define BLOCK_Y 1
#define RAW_BUFF_SIZE (GRID_X * GRID_Y * BLOCK_X * BLOCK_Y)
#define DEF_IDX \
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
#define CUDA_SAFE_CALL(func) \
do { \
hipError_t err = (func); \
if (err != hipSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
hipGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len);
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len);
int main(int argc, char** argv)
{
if (argc != 3) {
fprintf(stderr, "Usage: %s raw_data huffman_table\n", argv[0]);
exit(EXIT_FAILURE);
}
// Read raw data
char* raw_data_h = (char*)calloc(RAW_BUFF_SIZE, 1);
size_t raw_len = 0;
{
printf("Reading raw data ... ");
FILE* raw_file = fopen(argv[1], "r");
size_t r;
while ((r = fread(
raw_data_h + raw_len, 1, RAW_BUFF_SIZE - raw_len, raw_file))
!= 0) {
raw_len += r;
}
fclose(raw_file);
printf("done. Read %zu bytes.\n", raw_len);
}
char* raw_data;
CUDA_SAFE_CALL(hipMalloc((void**)&raw_data, raw_len));
CUDA_SAFE_CALL(hipMemcpy(
raw_data, raw_data_h, raw_len, hipMemcpyHostToDevice));
// Read Huffman table
bool* code_h = (bool*)calloc(MAX_CODE_LEN * SYMBOL_NUM, sizeof(bool));
size_t* code_len_h = (size_t*)calloc(SYMBOL_NUM, sizeof(size_t));
{
printf("Reading Huffman table ... ");
FILE* hufftable_file = fopen(argv[2], "r");
int c;
while (fscanf(hufftable_file, "%d", &c) != EOF) {
size_t len;
int _ = fscanf(hufftable_file, "%zu", &len);
code_len_h[c] = len;
for (size_t j = 0; j < len; j++) {
int b;
int _ = fscanf(hufftable_file, "%d", &b);
code_h[c * MAX_CODE_LEN + j] = b;
}
}
fclose(hufftable_file);
printf("done.\n");
}
bool* code;
CUDA_SAFE_CALL(hipMalloc(
(void**)&code, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool)));
CUDA_SAFE_CALL(hipMemcpy(
code, code_h, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool),
hipMemcpyHostToDevice));
size_t* code_len;
CUDA_SAFE_CALL(hipMalloc((void**)&code_len, SYMBOL_NUM * sizeof(size_t)));
CUDA_SAFE_CALL(hipMemcpy(
code_len, code_len_h, SYMBOL_NUM * sizeof(size_t),
hipMemcpyHostToDevice));
// free(code_h);
// Run on CUDA
dim3 grid(GRID_X, GRID_Y);
dim3 block(BLOCK_X, BLOCK_Y, 1);
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
// Prefix sum of code length
size_t* len_ps_h = (size_t*)calloc(raw_len, sizeof(size_t));
prefixSumHost(raw_data_h, code_len_h, len_ps_h, raw_len);
// prefixSum<<<grid, block>>>(raw_data, code_len, len_ps, raw_len);
CUDA_SAFE_CALL(hipDeviceSynchronize());
size_t* len_ps;
CUDA_SAFE_CALL(hipMalloc((void**)&len_ps, raw_len * sizeof(size_t)));
CUDA_SAFE_CALL(hipMemcpy(
len_ps, len_ps_h, raw_len * sizeof(size_t), hipMemcpyHostToDevice));
/* {
size_t* len_ps_h = (size_t*)malloc(sizeof(size_t) * raw_len);
CUDA_SAFE_CALL(cudaMemcpy(
len_ps_h, len_ps, sizeof(size_t) * raw_len, cudaMemcpyDeviceToHost));
for (size_t i = 0; i < raw_len; i++)
printf("%zu\n", len_ps_h[i]);
} */
size_t len_ps_end;
CUDA_SAFE_CALL(hipMemcpy(
&len_ps_end, &len_ps[raw_len - 1], sizeof(size_t),
hipMemcpyDeviceToHost));
size_t bytes_len = len_ps_end + code_len_h[raw_data_h[raw_len - 1]];
printf("bytes len: %zu\n", bytes_len);
// free(code_len_h);
// free(raw_data_h);
if (bytes_len > RAW_BUFF_SIZE) {
fprintf(stderr, "Bytes stream overflowed\n");
exit(EXIT_FAILURE);
}
bool* bytes;
CUDA_SAFE_CALL(hipMalloc((void**)&bytes, sizeof(bool) * bytes_len));
genByteStream<<<grid, block>>>(
raw_data, code, code_len, len_ps, bytes, raw_len);
CUDA_SAFE_CALL(hipDeviceSynchronize());
// CUDA_SAFE_CALL(cudaFree(len_ps));
// CUDA_SAFE_CALL(cudaFree(code_len));
// CUDA_SAFE_CALL(cudaFree(code));
// CUDA_SAFE_CALL(cudaFree(raw_data));
uint8_t* bits;
size_t bits_len = bytes_len / 8 + 1;
printf("bits len: %zu\n", bits_len);
CUDA_SAFE_CALL(hipMalloc((void**)&bits, bits_len));
compressByteStream<<<grid, block>>>(bytes, bits, bits_len);
CUDA_SAFE_CALL(hipDeviceSynchronize());
// CUDA_SAFE_CALL(cudaFree(bits));
// CUDA_SAFE_CALL(cudaFree(bytes));
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("bytes: %zu sec: %lf bytes/sec: %lf\n",
raw_len, sec, raw_len / sec);
return 0;
}
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
len_ps[0] = 0;
for (size_t i = 1; i < raw_len; i++) {
len_ps[i] = len_ps[i - 1] + code_len[raw_data[i - 1]];
}
}
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
DEF_IDX;
if (2 * idx + 1 < raw_len) {
len_ps[2 * idx] = code_len[raw_data[2 * idx]];
len_ps[2 * idx + 1] = code_len[raw_data[2 * idx + 1]];
}
__syncthreads();
// build sum in place up the tree
size_t offset = 1;
for (size_t d = raw_len >> 1; d > 0; d >>= 1) {
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
len_ps[bi] += len_ps[ai];
}
offset *= 2;
}
// clear the last element
if (idx == 0)
len_ps[raw_len - 1] = 0;
// traverse down tree & build scan
for (size_t d = 1; d < raw_len; d *= 2) {
offset >>= 1;
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
size_t t = len_ps[ai];
len_ps[ai] = len_ps[bi];
len_ps[bi] += t;
}
}
}
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len)
{
DEF_IDX;
if (idx < raw_len) {
size_t start_pos = len_ps[idx];
char symbol = raw_data[idx];
for (size_t i = 0, len = code_len[symbol]; i < len; i++) {
bytes[start_pos + i] = code[symbol * MAX_CODE_LEN + i];
}
}
}
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len)
{
DEF_IDX;
if (idx < bits_len) {
for (size_t i = 0; i < 8; i++) {
bits[idx] |= (uint8_t)bytes[8 * idx + i] << (7 - i);
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9prefixSumPcPmS0_m
.globl _Z9prefixSumPcPmS0_m
.p2align 8
.type _Z9prefixSumPcPmS0_m,@function
_Z9prefixSumPcPmS0_m:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
s_mov_b32 s2, exec_lo
v_lshlrev_b64 v[5:6], 1, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_or_b32_e32 v3, 1, v5
v_mov_b32_e32 v4, v6
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[6:7], v[3:4]
s_cbranch_execz .LBB0_2
s_load_b128 s[8:11], s[0:1], 0x0
v_lshlrev_b64 v[9:10], 3, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v7, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v8, vcc_lo, s9, v6, vcc_lo
global_load_i8 v0, v[7:8], off
s_waitcnt vmcnt(0)
v_bfe_i32 v7, v0, 0, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v11, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v4, vcc_lo
s_waitcnt vmcnt(0)
global_store_b64 v[9:10], v[7:8], off
global_load_i8 v0, v[11:12], off
v_lshlrev_b64 v[9:10], 3, v[3:4]
s_waitcnt vmcnt(0)
v_bfe_i32 v7, v0, 0, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 3, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s10, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b64 v[7:8], v[7:8], off
s_waitcnt vmcnt(0)
global_store_b64 v[9:10], v[7:8], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_u64_e64 s0, s[6:7], 2
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], 1
s_cbranch_vccnz .LBB0_8
v_add_co_u32 v0, vcc_lo, v5, 2
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v6, vcc_lo
s_add_u32 s10, s4, -8
s_addc_u32 s11, s5, -1
s_mov_b64 s[2:3], s[6:7]
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_lshr_b64 s[8:9], s[2:3], 1
s_mov_b32 s12, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u64_e64 s[8:9], v[1:2]
s_cbranch_execz .LBB0_6
v_mul_lo_u32 v12, s1, v3
v_mul_lo_u32 v13, s0, v4
v_mad_u64_u32 v[8:9], null, s0, v3, 0
v_mul_lo_u32 v14, s1, v0
v_mul_lo_u32 v15, s0, v7
v_mad_u64_u32 v[10:11], null, s0, v0, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v9, v9, v13, v12
v_add3_u32 v11, v11, v15, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[8:9], 3, v[8:9]
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, s10, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s11, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s10, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v11, vcc_lo
s_clause 0x1
global_load_b64 v[8:9], v[8:9], off
global_load_b64 v[12:13], v[10:11], off
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v12, v8
v_add_co_ci_u32_e32 v9, vcc_lo, v13, v9, vcc_lo
global_store_b64 v[10:11], v[8:9], off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s12
v_cmp_lt_u64_e64 s2, s[2:3], 4
s_lshl_b64 s[0:1], s[0:1], 1
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_8
s_mov_b64 s[2:3], s[8:9]
s_branch .LBB0_4
.LBB0_8:
s_mov_b32 s2, exec_lo
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v0, 0
s_lshl_b64 s[8:9], s[6:7], 3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_u32 s8, s4, s8
v_mov_b32_e32 v8, v7
s_addc_u32 s9, s5, s9
global_store_b64 v0, v[7:8], s[8:9] offset:-8
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s2
v_cmp_lt_u64_e64 s2, s[6:7], 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_15
v_add_co_u32 v0, vcc_lo, v5, 2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
s_add_u32 s4, s4, -8
s_addc_u32 s5, s5, -1
s_mov_b64 s[2:3], 1
s_branch .LBB0_13
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
s_lshl_b64 s[2:3], s[2:3], 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s8, s[2:3], s[6:7]
s_and_b32 vcc_lo, exec_lo, s8
s_cbranch_vccnz .LBB0_15
.LBB0_13:
s_lshr_b64 s[0:1], s[0:1], 1
s_mov_b32 s8, exec_lo
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
v_cmpx_gt_u64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_12
v_mul_lo_u32 v8, s1, v0
v_mul_lo_u32 v9, s0, v5
v_mad_u64_u32 v[6:7], null, s0, v0, 0
v_mul_lo_u32 v12, s1, v3
v_mul_lo_u32 v13, s0, v4
v_mad_u64_u32 v[10:11], null, s0, v3, 0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v7, v7, v9, v8
v_add3_u32 v11, v11, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[6:7]
v_lshlrev_b64 v[10:11], 3, v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
s_clause 0x1
global_load_b64 v[8:9], v[6:7], off
global_load_b64 v[12:13], v[10:11], off
s_waitcnt vmcnt(1)
global_store_b64 v[10:11], v[8:9], off
global_load_b64 v[8:9], v[6:7], off
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v8, v12
v_add_co_ci_u32_e32 v9, vcc_lo, v9, v13, vcc_lo
global_store_b64 v[6:7], v[8:9], off
s_branch .LBB0_12
.LBB0_15:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9prefixSumPcPmS0_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9prefixSumPcPmS0_m, .Lfunc_end0-_Z9prefixSumPcPmS0_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13genByteStreamPcPbPmS1_S0_m
.globl _Z13genByteStreamPcPbPmS1_S0_m
.p2align 8
.type _Z13genByteStreamPcPbPmS1_S0_m,@function
_Z13genByteStreamPcPbPmS1_S0_m:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x3c
s_load_b64 s[2:3], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mov_b32_e32 v3, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB1_4
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[4:5], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
s_mov_b32 s2, 0
global_load_i8 v0, v[0:1], off
s_waitcnt vmcnt(0)
v_bfe_i32 v4, v0, 0, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_load_b64 v[0:1], v[0:1], off
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, 0, v[0:1]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_4
s_load_b128 s[4:7], s[0:1], 0x18
v_lshlrev_b64 v[2:3], 3, v[2:3]
s_load_b64 s[0:1], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[5:6], v[2:3], off
v_mul_i32_i24_e32 v2, 0xff, v4
v_mul_hi_i32_i24_e32 v3, 0xff, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v6, vcc_lo
.p2align 6
.LBB1_3:
global_load_u8 v6, v[2:3], off
v_add_co_u32 v0, vcc_lo, v0, -1
v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b8 v[4:5], v6, off
v_add_co_u32 v4, s0, v4, 1
v_add_co_ci_u32_e64 v5, s0, 0, v5, s0
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB1_3
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13genByteStreamPcPbPmS1_S0_m
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13genByteStreamPcPbPmS1_S0_m, .Lfunc_end1-_Z13genByteStreamPcPbPmS1_S0_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z18compressByteStreamPbPhm
.globl _Z18compressByteStreamPbPhm
.p2align 8
.type _Z18compressByteStreamPbPhm,@function
_Z18compressByteStreamPbPhm:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mov_b32_e32 v3, 0
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB2_3
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
v_lshlrev_b64 v[2:3], 3, v[2:3]
global_load_u8 v4, v[0:1], off
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_mov_b64 s[0:1], 0
.LBB2_2:
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_add_co_u32 v5, vcc_lo, v2, s0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v3, vcc_lo
s_xor_b32 s2, s0, 7
s_add_u32 s0, s0, 1
s_addc_u32 s1, s1, 0
global_load_u8 v5, v[5:6], off
s_cmp_lg_u64 s[0:1], 8
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v5, s2, v5
s_delay_alu instid0(VALU_DEP_1)
v_or_b32_e32 v4, v4, v5
global_store_b8 v[0:1], v4, off
s_cbranch_scc1 .LBB2_2
.LBB2_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18compressByteStreamPbPhm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z18compressByteStreamPbPhm, .Lfunc_end2-_Z18compressByteStreamPbPhm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9prefixSumPcPmS0_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9prefixSumPcPmS0_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13genByteStreamPcPbPmS1_S0_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13genByteStreamPcPbPmS1_S0_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18compressByteStreamPbPhm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18compressByteStreamPbPhm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <stdbool.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#define SYMBOL_NUM 256
#define MAX_CODE_LEN (SYMBOL_NUM - 1)
#define GRID_X (1u << 12)
#define GRID_Y 1
#define BLOCK_X (1u << 10)
#define BLOCK_Y 1
#define RAW_BUFF_SIZE (GRID_X * GRID_Y * BLOCK_X * BLOCK_Y)
#define DEF_IDX \
size_t idx = blockDim.x * blockIdx.x + threadIdx.x;
#define CUDA_SAFE_CALL(func) \
do { \
hipError_t err = (func); \
if (err != hipSuccess) { \
fprintf(stderr, "[Error] %s (error code: %d) at %s line %d\n", \
hipGetErrorString(err), err, __FILE__, __LINE__); \
exit(err); \
} \
} while (0)
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len);
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len);
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len);
int main(int argc, char** argv)
{
if (argc != 3) {
fprintf(stderr, "Usage: %s raw_data huffman_table\n", argv[0]);
exit(EXIT_FAILURE);
}
// Read raw data
char* raw_data_h = (char*)calloc(RAW_BUFF_SIZE, 1);
size_t raw_len = 0;
{
printf("Reading raw data ... ");
FILE* raw_file = fopen(argv[1], "r");
size_t r;
while ((r = fread(
raw_data_h + raw_len, 1, RAW_BUFF_SIZE - raw_len, raw_file))
!= 0) {
raw_len += r;
}
fclose(raw_file);
printf("done. Read %zu bytes.\n", raw_len);
}
char* raw_data;
CUDA_SAFE_CALL(hipMalloc((void**)&raw_data, raw_len));
CUDA_SAFE_CALL(hipMemcpy(
raw_data, raw_data_h, raw_len, hipMemcpyHostToDevice));
// Read Huffman table
bool* code_h = (bool*)calloc(MAX_CODE_LEN * SYMBOL_NUM, sizeof(bool));
size_t* code_len_h = (size_t*)calloc(SYMBOL_NUM, sizeof(size_t));
{
printf("Reading Huffman table ... ");
FILE* hufftable_file = fopen(argv[2], "r");
int c;
while (fscanf(hufftable_file, "%d", &c) != EOF) {
size_t len;
int _ = fscanf(hufftable_file, "%zu", &len);
code_len_h[c] = len;
for (size_t j = 0; j < len; j++) {
int b;
int _ = fscanf(hufftable_file, "%d", &b);
code_h[c * MAX_CODE_LEN + j] = b;
}
}
fclose(hufftable_file);
printf("done.\n");
}
bool* code;
CUDA_SAFE_CALL(hipMalloc(
(void**)&code, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool)));
CUDA_SAFE_CALL(hipMemcpy(
code, code_h, MAX_CODE_LEN * SYMBOL_NUM * sizeof(bool),
hipMemcpyHostToDevice));
size_t* code_len;
CUDA_SAFE_CALL(hipMalloc((void**)&code_len, SYMBOL_NUM * sizeof(size_t)));
CUDA_SAFE_CALL(hipMemcpy(
code_len, code_len_h, SYMBOL_NUM * sizeof(size_t),
hipMemcpyHostToDevice));
// free(code_h);
// Run on CUDA
dim3 grid(GRID_X, GRID_Y);
dim3 block(BLOCK_X, BLOCK_Y, 1);
struct timeval time_start, time_end;
gettimeofday(&time_start, NULL);
// Prefix sum of code length
size_t* len_ps_h = (size_t*)calloc(raw_len, sizeof(size_t));
prefixSumHost(raw_data_h, code_len_h, len_ps_h, raw_len);
// prefixSum<<<grid, block>>>(raw_data, code_len, len_ps, raw_len);
CUDA_SAFE_CALL(hipDeviceSynchronize());
size_t* len_ps;
CUDA_SAFE_CALL(hipMalloc((void**)&len_ps, raw_len * sizeof(size_t)));
CUDA_SAFE_CALL(hipMemcpy(
len_ps, len_ps_h, raw_len * sizeof(size_t), hipMemcpyHostToDevice));
/* {
size_t* len_ps_h = (size_t*)malloc(sizeof(size_t) * raw_len);
CUDA_SAFE_CALL(cudaMemcpy(
len_ps_h, len_ps, sizeof(size_t) * raw_len, cudaMemcpyDeviceToHost));
for (size_t i = 0; i < raw_len; i++)
printf("%zu\n", len_ps_h[i]);
} */
size_t len_ps_end;
CUDA_SAFE_CALL(hipMemcpy(
&len_ps_end, &len_ps[raw_len - 1], sizeof(size_t),
hipMemcpyDeviceToHost));
size_t bytes_len = len_ps_end + code_len_h[raw_data_h[raw_len - 1]];
printf("bytes len: %zu\n", bytes_len);
// free(code_len_h);
// free(raw_data_h);
if (bytes_len > RAW_BUFF_SIZE) {
fprintf(stderr, "Bytes stream overflowed\n");
exit(EXIT_FAILURE);
}
bool* bytes;
CUDA_SAFE_CALL(hipMalloc((void**)&bytes, sizeof(bool) * bytes_len));
genByteStream<<<grid, block>>>(
raw_data, code, code_len, len_ps, bytes, raw_len);
CUDA_SAFE_CALL(hipDeviceSynchronize());
// CUDA_SAFE_CALL(cudaFree(len_ps));
// CUDA_SAFE_CALL(cudaFree(code_len));
// CUDA_SAFE_CALL(cudaFree(code));
// CUDA_SAFE_CALL(cudaFree(raw_data));
uint8_t* bits;
size_t bits_len = bytes_len / 8 + 1;
printf("bits len: %zu\n", bits_len);
CUDA_SAFE_CALL(hipMalloc((void**)&bits, bits_len));
compressByteStream<<<grid, block>>>(bytes, bits, bits_len);
CUDA_SAFE_CALL(hipDeviceSynchronize());
// CUDA_SAFE_CALL(cudaFree(bits));
// CUDA_SAFE_CALL(cudaFree(bytes));
gettimeofday(&time_end, NULL);
double sec = (double)(time_end.tv_sec - time_start.tv_sec)
+ (double)(time_end.tv_usec - time_start.tv_usec) / 1e6;
printf("bytes: %zu sec: %lf bytes/sec: %lf\n",
raw_len, sec, raw_len / sec);
return 0;
}
void prefixSumHost(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
len_ps[0] = 0;
for (size_t i = 1; i < raw_len; i++) {
len_ps[i] = len_ps[i - 1] + code_len[raw_data[i - 1]];
}
}
__global__ void prefixSum(
char* raw_data, size_t* code_len, size_t* len_ps, size_t raw_len)
{
DEF_IDX;
if (2 * idx + 1 < raw_len) {
len_ps[2 * idx] = code_len[raw_data[2 * idx]];
len_ps[2 * idx + 1] = code_len[raw_data[2 * idx + 1]];
}
__syncthreads();
// build sum in place up the tree
size_t offset = 1;
for (size_t d = raw_len >> 1; d > 0; d >>= 1) {
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
len_ps[bi] += len_ps[ai];
}
offset *= 2;
}
// clear the last element
if (idx == 0)
len_ps[raw_len - 1] = 0;
// traverse down tree & build scan
for (size_t d = 1; d < raw_len; d *= 2) {
offset >>= 1;
__syncthreads();
if (idx < d) {
size_t ai = offset * (2 * idx + 1) - 1;
size_t bi = offset * (2 * idx + 2) - 1;
size_t t = len_ps[ai];
len_ps[ai] = len_ps[bi];
len_ps[bi] += t;
}
}
}
__global__ void genByteStream(
char* raw_data, bool* code, size_t* code_len, size_t* len_ps, bool* bytes,
size_t raw_len)
{
DEF_IDX;
if (idx < raw_len) {
size_t start_pos = len_ps[idx];
char symbol = raw_data[idx];
for (size_t i = 0, len = code_len[symbol]; i < len; i++) {
bytes[start_pos + i] = code[symbol * MAX_CODE_LEN + i];
}
}
}
__global__ void compressByteStream(bool* bytes, uint8_t* bits, size_t bits_len)
{
DEF_IDX;
if (idx < bits_len) {
for (size_t i = 0; i < 8; i++) {
bits[idx] |= (uint8_t)bytes[8 * idx + i] << (7 - i);
}
}
} | .text
.file "main.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_2:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r13
cmpl $3, %edi
jne .LBB0_47
# %bb.1:
movl $4194304, %edi # imm = 0x400000
movl $1, %esi
callq calloc
movq %rax, %r12
xorl %r14d, %r14d
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 8(%r13), %rdi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r15
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rbx
leaq (%r12,%r14), %rdi
movl $4194304, %edx # imm = 0x400000
subq %r14, %rdx
movl $1, %esi
movq %r15, %rcx
callq fread
addq %rax, %r14
testq %rax, %rax
jne .LBB0_2
# %bb.3:
movq %r15, %rdi
callq fclose
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
leaq 136(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_4
# %bb.6:
movq 136(%rsp), %rdi
movq %r12, 200(%rsp) # 8-byte Spill
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_7
# %bb.8:
movl $65280, %edi # imm = 0xFF00
movl $1, %esi
callq calloc
movq %rax, %r12
movl $256, %edi # imm = 0x100
movl $8, %esi
callq calloc
movq %rax, %r15
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 16(%r13), %rdi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r13
leaq 96(%rsp), %rdx
movl $.L.str.7, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB0_14
# %bb.9: # %.lr.ph169.preheader
leaq 8(%rsp), %rbp
jmp .LBB0_10
.p2align 4, 0x90
.LBB0_13: # %._crit_edge
# in Loop: Header=BB0_10 Depth=1
movl $.L.str.7, %esi
movq %r13, %rdi
leaq 96(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB0_14
.LBB0_10: # %.lr.ph169
# =>This Loop Header: Depth=1
# Child Loop BB0_12 Depth 2
movl $.L.str.8, %esi
movq %r13, %rdi
leaq 144(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq 144(%rsp), %rax
movslq 96(%rsp), %rcx
movq %rax, (%r15,%rcx,8)
testq %rax, %rax
je .LBB0_13
# %bb.11: # %.lr.ph.preheader
# in Loop: Header=BB0_10 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_12: # %.lr.ph
# Parent Loop BB0_10 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.7, %esi
movq %r13, %rdi
movq %rbp, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movslq 96(%rsp), %rax
movq %rax, %rcx
shlq $8, %rcx
subq %rax, %rcx
addq %r12, %rcx
cmpl $0, 8(%rsp)
setne (%r14,%rcx)
incq %r14
cmpq 144(%rsp), %r14
jb .LBB0_12
jmp .LBB0_13
.LBB0_14: # %._crit_edge170
movq %r13, %rdi
callq fclose
movl $.Lstr, %edi
callq puts@PLT
leaq 128(%rsp), %rdi
movl $65280, %esi # imm = 0xFF00
callq hipMalloc
testl %eax, %eax
jne .LBB0_15
# %bb.16:
movq 128(%rsp), %rdi
movl $65280, %edx # imm = 0xFF00
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_17
# %bb.18:
leaq 120(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
testl %eax, %eax
movq 200(%rsp), %r14 # 8-byte Reload
jne .LBB0_19
# %bb.20:
movq 120(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_21
# %bb.22:
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $8, %esi
movq %rbx, %rdi
callq calloc
movq %rax, %r12
movq $0, (%rax)
cmpq $2, %rbx
jb .LBB0_25
# %bb.23: # %.lr.ph.i.preheader
movq (%r12), %rax
leaq -1(%rbx), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_24: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movsbq (%r14,%rdx), %rsi
addq (%r15,%rsi,8), %rax
movq %rax, 8(%r12,%rdx,8)
incq %rdx
cmpq %rdx, %rcx
jne .LBB0_24
.LBB0_25: # %_Z13prefixSumHostPcPmS0_m.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_26
# %bb.27:
leaq (,%rbx,8), %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_28
# %bb.29:
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_30
# %bb.31:
leaq -8(,%rbx,8), %rsi
addq 24(%rsp), %rsi
leaq 208(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_32
# %bb.33:
leaq -1(%rbx), %rax
movsbq (%r14,%rax), %rax
movq (%r15,%rax,8), %r14
addq 208(%rsp), %r14
movl $.L.str.10, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
cmpq $4194305, %r14 # imm = 0x400001
jae .LBB0_48
# %bb.34:
leaq 112(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_35
# %bb.36:
movabsq $4294968320, %r15 # imm = 0x100000400
leaq 3072(%r15), %r12
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_38
# %bb.37:
movq 136(%rsp), %rax
movq 128(%rsp), %rcx
movq 120(%rsp), %rdx
movq 24(%rsp), %rsi
movq 112(%rsp), %rdi
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rsi, 48(%rsp)
movq %rdi, 40(%rsp)
movq %rbx, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 224(%rsp), %rdx
leaq 216(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z13genByteStreamPcPbPmS1_S0_m, %edi
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
pushq 232(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_38:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_39
# %bb.40:
shrq $3, %r14
incq %r14
movl $.L.str.12, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_41
# %bb.42:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_44
# %bb.43:
movq 112(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r14, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z18compressByteStreamPbPhm, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_44:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_45
# %bb.46:
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 144(%rsp), %rax
movq 152(%rsp), %rcx
subq 96(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 104(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
movq %rbx, %xmm2
punpckldq .LCPI0_1(%rip), %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
subpd .LCPI0_2(%rip), %xmm2
movapd %xmm2, %xmm1
unpckhpd %xmm2, %xmm1 # xmm1 = xmm1[1],xmm2[1]
addsd %xmm2, %xmm1
divsd %xmm0, %xmm1
movl $.L.str.13, %edi
movq %rbx, %rsi
movb $2, %al
callq printf
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_47:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rdi
movq (%r13), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $65, %r9d
jmp .LBB0_5
.LBB0_7:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $67, %r9d
jmp .LBB0_5
.LBB0_15:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $94, %r9d
jmp .LBB0_5
.LBB0_17:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $97, %r9d
jmp .LBB0_5
.LBB0_19:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $99, %r9d
jmp .LBB0_5
.LBB0_21:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $102, %r9d
jmp .LBB0_5
.LBB0_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $118, %r9d
jmp .LBB0_5
.LBB0_28:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $121, %r9d
jmp .LBB0_5
.LBB0_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $123, %r9d
jmp .LBB0_5
.LBB0_32:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $136, %r9d
jmp .LBB0_5
.LBB0_48:
movq stderr(%rip), %rcx
movl $.L.str.11, %edi
movl $24, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB0_35:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $149, %r9d
jmp .LBB0_5
.LBB0_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $152, %r9d
jmp .LBB0_5
.LBB0_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $162, %r9d
jmp .LBB0_5
.LBB0_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $164, %r9d
.LBB0_5:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z13prefixSumHostPcPmS0_m # -- Begin function _Z13prefixSumHostPcPmS0_m
.p2align 4, 0x90
.type _Z13prefixSumHostPcPmS0_m,@function
_Z13prefixSumHostPcPmS0_m: # @_Z13prefixSumHostPcPmS0_m
.cfi_startproc
# %bb.0:
movq $0, (%rdx)
cmpq $2, %rcx
jb .LBB1_3
# %bb.1: # %.lr.ph.preheader
decq %rcx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsbq (%rdi,%rax), %r8
movq (%rsi,%r8,8), %r8
addq (%rdx,%rax,8), %r8
movq %r8, 8(%rdx,%rax,8)
incq %rax
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13prefixSumHostPcPmS0_m, .Lfunc_end1-_Z13prefixSumHostPcPmS0_m
.cfi_endproc
# -- End function
.globl _Z28__device_stub__genByteStreamPcPbPmS1_S0_m # -- Begin function _Z28__device_stub__genByteStreamPcPbPmS1_S0_m
.p2align 4, 0x90
.type _Z28__device_stub__genByteStreamPcPbPmS1_S0_m,@function
_Z28__device_stub__genByteStreamPcPbPmS1_S0_m: # @_Z28__device_stub__genByteStreamPcPbPmS1_S0_m
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13genByteStreamPcPbPmS1_S0_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z28__device_stub__genByteStreamPcPbPmS1_S0_m, .Lfunc_end2-_Z28__device_stub__genByteStreamPcPbPmS1_S0_m
.cfi_endproc
# -- End function
.globl _Z33__device_stub__compressByteStreamPbPhm # -- Begin function _Z33__device_stub__compressByteStreamPbPhm
.p2align 4, 0x90
.type _Z33__device_stub__compressByteStreamPbPhm,@function
_Z33__device_stub__compressByteStreamPbPhm: # @_Z33__device_stub__compressByteStreamPbPhm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18compressByteStreamPbPhm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z33__device_stub__compressByteStreamPbPhm, .Lfunc_end3-_Z33__device_stub__compressByteStreamPbPhm
.cfi_endproc
# -- End function
.globl _Z24__device_stub__prefixSumPcPmS0_m # -- Begin function _Z24__device_stub__prefixSumPcPmS0_m
.p2align 4, 0x90
.type _Z24__device_stub__prefixSumPcPmS0_m,@function
_Z24__device_stub__prefixSumPcPmS0_m: # @_Z24__device_stub__prefixSumPcPmS0_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9prefixSumPcPmS0_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z24__device_stub__prefixSumPcPmS0_m, .Lfunc_end4-_Z24__device_stub__prefixSumPcPmS0_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9prefixSumPcPmS0_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13genByteStreamPcPbPmS1_S0_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18compressByteStreamPbPhm, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s raw_data huffman_table\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Reading raw data ... "
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "done. Read %zu bytes.\n"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[Error] %s (error code: %d) at %s line %d\n"
.size .L.str.4, 43
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ordovicia/huffman-coding-cuda/master/main.hip"
.size .L.str.5, 103
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Reading Huffman table ... "
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%zu"
.size .L.str.8, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "bytes len: %zu\n"
.size .L.str.10, 16
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Bytes stream overflowed\n"
.size .L.str.11, 25
.type _Z13genByteStreamPcPbPmS1_S0_m,@object # @_Z13genByteStreamPcPbPmS1_S0_m
.section .rodata,"a",@progbits
.globl _Z13genByteStreamPcPbPmS1_S0_m
.p2align 3, 0x0
_Z13genByteStreamPcPbPmS1_S0_m:
.quad _Z28__device_stub__genByteStreamPcPbPmS1_S0_m
.size _Z13genByteStreamPcPbPmS1_S0_m, 8
.type .L.str.12,@object # @.str.12
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.12:
.asciz "bits len: %zu\n"
.size .L.str.12, 15
.type _Z18compressByteStreamPbPhm,@object # @_Z18compressByteStreamPbPhm
.section .rodata,"a",@progbits
.globl _Z18compressByteStreamPbPhm
.p2align 3, 0x0
_Z18compressByteStreamPbPhm:
.quad _Z33__device_stub__compressByteStreamPbPhm
.size _Z18compressByteStreamPbPhm, 8
.type .L.str.13,@object # @.str.13
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.13:
.asciz "bytes: %zu sec: %lf bytes/sec: %lf\n"
.size .L.str.13, 36
.type _Z9prefixSumPcPmS0_m,@object # @_Z9prefixSumPcPmS0_m
.section .rodata,"a",@progbits
.globl _Z9prefixSumPcPmS0_m
.p2align 3, 0x0
_Z9prefixSumPcPmS0_m:
.quad _Z24__device_stub__prefixSumPcPmS0_m
.size _Z9prefixSumPcPmS0_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9prefixSumPcPmS0_m"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13genByteStreamPcPbPmS1_S0_m"
.size .L__unnamed_2, 31
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18compressByteStreamPbPhm"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "done."
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__genByteStreamPcPbPmS1_S0_m
.addrsig_sym _Z33__device_stub__compressByteStreamPbPhm
.addrsig_sym _Z24__device_stub__prefixSumPcPmS0_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13genByteStreamPcPbPmS1_S0_m
.addrsig_sym _Z18compressByteStreamPbPhm
.addrsig_sym _Z9prefixSumPcPmS0_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001922b_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13prefixSumHostPcPmS0_m
.type _Z13prefixSumHostPcPmS0_m, @function
_Z13prefixSumHostPcPmS0_m:
.LFB2058:
.cfi_startproc
endbr64
movq $0, (%rdx)
cmpq $1, %rcx
jbe .L3
movl $1, %eax
.L5:
movsbq -1(%rdi,%rax), %r9
movq -8(%rdx,%rax,8), %r8
addq (%rsi,%r9,8), %r8
movq %r8, (%rdx,%rax,8)
addq $1, %rax
cmpq %rax, %rcx
jne .L5
.L3:
ret
.cfi_endproc
.LFE2058:
.size _Z13prefixSumHostPcPmS0_m, .-_Z13prefixSumHostPcPmS0_m
.globl _Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m
.type _Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m, @function
_Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9prefixSumPcPmS0_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m, .-_Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m
.globl _Z9prefixSumPcPmS0_m
.type _Z9prefixSumPcPmS0_m, @function
_Z9prefixSumPcPmS0_m:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9prefixSumPcPmS0_mPcPmS0_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9prefixSumPcPmS0_m, .-_Z9prefixSumPcPmS0_m
.globl _Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m
.type _Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m, @function
_Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m:
.LFB2085:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13genByteStreamPcPbPmS1_S0_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m, .-_Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m
.globl _Z13genByteStreamPcPbPmS1_S0_m
.type _Z13genByteStreamPcPbPmS1_S0_m, @function
_Z13genByteStreamPcPbPmS1_S0_m:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13genByteStreamPcPbPmS1_S0_m, .-_Z13genByteStreamPcPbPmS1_S0_m
.globl _Z41__device_stub__Z18compressByteStreamPbPhmPbPhm
.type _Z41__device_stub__Z18compressByteStreamPbPhmPbPhm, @function
_Z41__device_stub__Z18compressByteStreamPbPhmPbPhm:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18compressByteStreamPbPhm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z41__device_stub__Z18compressByteStreamPbPhmPbPhm, .-_Z41__device_stub__Z18compressByteStreamPbPhmPbPhm
.globl _Z18compressByteStreamPbPhm
.type _Z18compressByteStreamPbPhm, @function
_Z18compressByteStreamPbPhm:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z18compressByteStreamPbPhmPbPhm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z18compressByteStreamPbPhm, .-_Z18compressByteStreamPbPhm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Usage: %s raw_data huffman_table\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Reading raw data ... "
.LC2:
.string "r"
.LC3:
.string "done. Read %zu bytes.\n"
.section .rodata.str1.8
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/ordovicia/huffman-coding-cuda/master/main.cu"
.align 8
.LC5:
.string "[Error] %s (error code: %d) at %s line %d\n"
.section .rodata.str1.1
.LC6:
.string "Reading Huffman table ... "
.LC7:
.string "%zu"
.LC8:
.string "%d"
.LC9:
.string "done.\n"
.LC10:
.string "bytes len: %zu\n"
.LC11:
.string "Bytes stream overflowed\n"
.LC12:
.string "bits len: %zu\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "bytes: %zu sec: %lf bytes/sec: %lf\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $168, %rsp
.cfi_def_cfa_offset 224
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L61
movl $1, %esi
movl $4194304, %edi
call calloc@PLT
movq %rax, (%rsp)
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rbx), %rdi
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl $0, %r13d
movl $4194304, %r12d
jmp .L33
.L61:
movq (%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
addq %r15, %r13
.L33:
movq %r12, %rcx
subq %r13, %rcx
movl $4194304, %esi
cmpq %rsi, %r13
cmovnb %r13, %rsi
subq %r13, %rsi
movq (%rsp), %rax
leaq (%rax,%r13), %rdi
movq %rbp, %r8
movl $1, %edx
call __fread_chk@PLT
movq %rax, %r15
testq %rax, %rax
jne .L34
movq %rbp, %rdi
call fclose@PLT
movq %r13, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L62
movl $1, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L63
movl $1, %esi
movl $65280, %edi
call calloc@PLT
movq %rax, %r14
movl $8, %esi
movl $256, %edi
call calloc@PLT
movq %rax, 8(%rsp)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 16(%rbx), %rdi
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
leaq 100(%rsp), %rax
movq %rax, 16(%rsp)
leaq .LC8(%rip), %r12
leaq 128(%rsp), %rax
movq %rax, 24(%rsp)
.L37:
movq 16(%rsp), %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
je .L64
movq 24(%rsp), %rdx
leaq .LC7(%rip), %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movq 128(%rsp), %rax
movslq 100(%rsp), %rdx
movq 8(%rsp), %rcx
movq %rax, (%rcx,%rdx,8)
testq %rax, %rax
je .L37
movq %r15, %rbx
.L39:
leaq 112(%rsp), %rdx
movq %r12, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 100(%rsp), %edx
movl %edx, %eax
sall $8, %eax
subl %edx, %eax
cltq
leaq (%r14,%rbx), %rdx
cmpl $0, 112(%rsp)
setne (%rdx,%rax)
addq $1, %rbx
cmpq 128(%rsp), %rbx
jb .L39
jmp .L37
.L62:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $65
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L63:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $66
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L64:
.cfi_restore_state
movq %rbp, %rdi
call fclose@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 40(%rsp), %rdi
movl $65280, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L65
movl $1, %ecx
movl $65280, %edx
movq %r14, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L66
leaq 48(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L67
movl $1, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L68
movl $4096, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1024, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $8, %esi
movq %r13, %rdi
call calloc@PLT
movq %rax, %rbx
movq %r13, %rcx
movq %rax, %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z13prefixSumHostPcPmS0_m
call cudaThreadSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L69
leaq 0(,%r13,8), %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl %eax, %r12d
testl %eax, %eax
jne .L70
movl $1, %ecx
movq %rbp, %rdx
movq %rbx, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L71
movq 56(%rsp), %rax
leaq -8(%rax,%rbp), %rsi
leaq 64(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
call cudaMemcpy@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L72
movq (%rsp), %rax
movsbq -1(%rax,%r13), %rax
movq 64(%rsp), %rbx
movq 8(%rsp), %rcx
addq (%rcx,%rax,8), %rbx
movq %rbx, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpq $4194304, %rbx
ja .L73
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L74
movl 108(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movq 88(%rsp), %rdi
movl 96(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L75
.L51:
call cudaThreadSynchronize@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L76
shrq $3, %rbx
addq $1, %rbx
movq %rbx, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl %eax, %ebp
testl %eax, %eax
jne .L77
movl 108(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movq 88(%rsp), %rdi
movl 96(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L78
.L54:
call cudaThreadSynchronize@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L79
leaq 128(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 136(%rsp), %rax
subq 120(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC13(%rip), %xmm0
movq 128(%rsp), %rax
subq 112(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
testq %r13, %r13
js .L56
pxor %xmm1, %xmm1
cvtsi2sdq %r13, %xmm1
.L57:
divsd %xmm0, %xmm1
movq %r13, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L80
movl $0, %eax
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L65:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $93
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L66:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $95
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L67:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $99
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L68:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $100
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L69:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $118
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L70:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $121
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %r12d, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %r12d, %edi
call exit@PLT
.L71:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $122
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L72:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $134
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L73:
.cfi_restore_state
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L74:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $149
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L75:
.cfi_restore_state
movq %r13, %r9
movq 72(%rsp), %r8
movq 56(%rsp), %rcx
movq 48(%rsp), %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z44__device_stub__Z13genByteStreamPcPbPmS1_S0_mPcPbPmS1_S0_m
jmp .L51
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $152
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L77:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $162
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebp, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebp, %edi
call exit@PLT
.L78:
.cfi_restore_state
movq %rbx, %rdx
movq 80(%rsp), %rsi
movq 72(%rsp), %rdi
call _Z41__device_stub__Z18compressByteStreamPbPhmPbPhm
jmp .L54
.L79:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
subq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 232
pushq $164
.cfi_def_cfa_offset 240
leaq .LC4(%rip), %r9
movl %ebx, %r8d
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl %ebx, %edi
call exit@PLT
.L56:
.cfi_restore_state
movq %r13, %rax
shrq %rax
movq %r13, %rdx
andl $1, %edx
orq %rdx, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm1
jmp .L57
.L80:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z18compressByteStreamPbPhm"
.section .rodata.str1.8
.align 8
.LC16:
.string "_Z13genByteStreamPcPbPmS1_S0_m"
.section .rodata.str1.1
.LC17:
.string "_Z9prefixSumPcPmS0_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z18compressByteStreamPbPhm(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z13genByteStreamPcPbPmS1_S0_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC17(%rip), %rdx
movq %rdx, %rcx
leaq _Z9prefixSumPcPmS0_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC13:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI0_1:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI0_2:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $232, %rsp
.cfi_def_cfa_offset 288
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r13
cmpl $3, %edi
jne .LBB0_47
# %bb.1:
movl $4194304, %edi # imm = 0x400000
movl $1, %esi
callq calloc
movq %rax, %r12
xorl %r14d, %r14d
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movq 8(%r13), %rdi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r15
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rbx
leaq (%r12,%r14), %rdi
movl $4194304, %edx # imm = 0x400000
subq %r14, %rdx
movl $1, %esi
movq %r15, %rcx
callq fread
addq %rax, %r14
testq %rax, %rax
jne .LBB0_2
# %bb.3:
movq %r15, %rdi
callq fclose
movl $.L.str.3, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
leaq 136(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_4
# %bb.6:
movq 136(%rsp), %rdi
movq %r12, 200(%rsp) # 8-byte Spill
movq %r12, %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_7
# %bb.8:
movl $65280, %edi # imm = 0xFF00
movl $1, %esi
callq calloc
movq %rax, %r12
movl $256, %edi # imm = 0x100
movl $8, %esi
callq calloc
movq %rax, %r15
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 16(%r13), %rdi
movl $.L.str.2, %esi
callq fopen
movq %rax, %r13
leaq 96(%rsp), %rdx
movl $.L.str.7, %esi
movq %rax, %rdi
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB0_14
# %bb.9: # %.lr.ph169.preheader
leaq 8(%rsp), %rbp
jmp .LBB0_10
.p2align 4, 0x90
.LBB0_13: # %._crit_edge
# in Loop: Header=BB0_10 Depth=1
movl $.L.str.7, %esi
movq %r13, %rdi
leaq 96(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
cmpl $-1, %eax
je .LBB0_14
.LBB0_10: # %.lr.ph169
# =>This Loop Header: Depth=1
# Child Loop BB0_12 Depth 2
movl $.L.str.8, %esi
movq %r13, %rdi
leaq 144(%rsp), %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movq 144(%rsp), %rax
movslq 96(%rsp), %rcx
movq %rax, (%r15,%rcx,8)
testq %rax, %rax
je .LBB0_13
# %bb.11: # %.lr.ph.preheader
# in Loop: Header=BB0_10 Depth=1
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB0_12: # %.lr.ph
# Parent Loop BB0_10 Depth=1
# => This Inner Loop Header: Depth=2
movl $.L.str.7, %esi
movq %r13, %rdi
movq %rbp, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movslq 96(%rsp), %rax
movq %rax, %rcx
shlq $8, %rcx
subq %rax, %rcx
addq %r12, %rcx
cmpl $0, 8(%rsp)
setne (%r14,%rcx)
incq %r14
cmpq 144(%rsp), %r14
jb .LBB0_12
jmp .LBB0_13
.LBB0_14: # %._crit_edge170
movq %r13, %rdi
callq fclose
movl $.Lstr, %edi
callq puts@PLT
leaq 128(%rsp), %rdi
movl $65280, %esi # imm = 0xFF00
callq hipMalloc
testl %eax, %eax
jne .LBB0_15
# %bb.16:
movq 128(%rsp), %rdi
movl $65280, %edx # imm = 0xFF00
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_17
# %bb.18:
leaq 120(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
testl %eax, %eax
movq 200(%rsp), %r14 # 8-byte Reload
jne .LBB0_19
# %bb.20:
movq 120(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_21
# %bb.22:
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl $8, %esi
movq %rbx, %rdi
callq calloc
movq %rax, %r12
movq $0, (%rax)
cmpq $2, %rbx
jb .LBB0_25
# %bb.23: # %.lr.ph.i.preheader
movq (%r12), %rax
leaq -1(%rbx), %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB0_24: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movsbq (%r14,%rdx), %rsi
addq (%r15,%rsi,8), %rax
movq %rax, 8(%r12,%rdx,8)
incq %rdx
cmpq %rdx, %rcx
jne .LBB0_24
.LBB0_25: # %_Z13prefixSumHostPcPmS0_m.exit
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_26
# %bb.27:
leaq (,%rbx,8), %r13
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_28
# %bb.29:
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_30
# %bb.31:
leaq -8(,%rbx,8), %rsi
addq 24(%rsp), %rsi
leaq 208(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_32
# %bb.33:
leaq -1(%rbx), %rax
movsbq (%r14,%rax), %rax
movq (%r15,%rax,8), %r14
addq 208(%rsp), %r14
movl $.L.str.10, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
cmpq $4194305, %r14 # imm = 0x400001
jae .LBB0_48
# %bb.34:
leaq 112(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_35
# %bb.36:
movabsq $4294968320, %r15 # imm = 0x100000400
leaq 3072(%r15), %r12
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_38
# %bb.37:
movq 136(%rsp), %rax
movq 128(%rsp), %rcx
movq 120(%rsp), %rdx
movq 24(%rsp), %rsi
movq 112(%rsp), %rdi
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rsi, 48(%rsp)
movq %rdi, 40(%rsp)
movq %rbx, 32(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 224(%rsp), %rdx
leaq 216(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z13genByteStreamPcPbPmS1_S0_m, %edi
pushq 216(%rsp)
.cfi_adjust_cfa_offset 8
pushq 232(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_38:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_39
# %bb.40:
shrq $3, %r14
incq %r14
movl $.L.str.12, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB0_41
# %bb.42:
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_44
# %bb.43:
movq 112(%rsp), %rax
movq 32(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r14, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 144(%rsp)
leaq 80(%rsp), %rax
movq %rax, 152(%rsp)
leaq 72(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 8(%rsp), %rsi
movl 16(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z18compressByteStreamPbPhm, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_44:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB0_45
# %bb.46:
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 144(%rsp), %rax
movq 152(%rsp), %rcx
subq 96(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 104(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
movq %rbx, %xmm2
punpckldq .LCPI0_1(%rip), %xmm2 # xmm2 = xmm2[0],mem[0],xmm2[1],mem[1]
subpd .LCPI0_2(%rip), %xmm2
movapd %xmm2, %xmm1
unpckhpd %xmm2, %xmm1 # xmm1 = xmm1[1],xmm2[1]
addsd %xmm2, %xmm1
divsd %xmm0, %xmm1
movl $.L.str.13, %edi
movq %rbx, %rsi
movb $2, %al
callq printf
xorl %eax, %eax
addq $232, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_47:
.cfi_def_cfa_offset 288
movq stderr(%rip), %rdi
movq (%r13), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB0_4:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $65, %r9d
jmp .LBB0_5
.LBB0_7:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $67, %r9d
jmp .LBB0_5
.LBB0_15:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $94, %r9d
jmp .LBB0_5
.LBB0_17:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $97, %r9d
jmp .LBB0_5
.LBB0_19:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $99, %r9d
jmp .LBB0_5
.LBB0_21:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $102, %r9d
jmp .LBB0_5
.LBB0_26:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $118, %r9d
jmp .LBB0_5
.LBB0_28:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $121, %r9d
jmp .LBB0_5
.LBB0_30:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $123, %r9d
jmp .LBB0_5
.LBB0_32:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $136, %r9d
jmp .LBB0_5
.LBB0_48:
movq stderr(%rip), %rcx
movl $.L.str.11, %edi
movl $24, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.LBB0_35:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $149, %r9d
jmp .LBB0_5
.LBB0_39:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $152, %r9d
jmp .LBB0_5
.LBB0_41:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $162, %r9d
jmp .LBB0_5
.LBB0_45:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.4, %esi
movl $.L.str.5, %r8d
movq %rbx, %rdi
movq %rax, %rdx
movl %ebp, %ecx
movl $164, %r9d
.LBB0_5:
xorl %eax, %eax
callq fprintf
movl %ebp, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z13prefixSumHostPcPmS0_m # -- Begin function _Z13prefixSumHostPcPmS0_m
.p2align 4, 0x90
.type _Z13prefixSumHostPcPmS0_m,@function
_Z13prefixSumHostPcPmS0_m: # @_Z13prefixSumHostPcPmS0_m
.cfi_startproc
# %bb.0:
movq $0, (%rdx)
cmpq $2, %rcx
jb .LBB1_3
# %bb.1: # %.lr.ph.preheader
decq %rcx
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movsbq (%rdi,%rax), %r8
movq (%rsi,%r8,8), %r8
addq (%rdx,%rax,8), %r8
movq %r8, 8(%rdx,%rax,8)
incq %rax
cmpq %rax, %rcx
jne .LBB1_2
.LBB1_3: # %._crit_edge
retq
.Lfunc_end1:
.size _Z13prefixSumHostPcPmS0_m, .Lfunc_end1-_Z13prefixSumHostPcPmS0_m
.cfi_endproc
# -- End function
.globl _Z28__device_stub__genByteStreamPcPbPmS1_S0_m # -- Begin function _Z28__device_stub__genByteStreamPcPbPmS1_S0_m
.p2align 4, 0x90
.type _Z28__device_stub__genByteStreamPcPbPmS1_S0_m,@function
_Z28__device_stub__genByteStreamPcPbPmS1_S0_m: # @_Z28__device_stub__genByteStreamPcPbPmS1_S0_m
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13genByteStreamPcPbPmS1_S0_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z28__device_stub__genByteStreamPcPbPmS1_S0_m, .Lfunc_end2-_Z28__device_stub__genByteStreamPcPbPmS1_S0_m
.cfi_endproc
# -- End function
.globl _Z33__device_stub__compressByteStreamPbPhm # -- Begin function _Z33__device_stub__compressByteStreamPbPhm
.p2align 4, 0x90
.type _Z33__device_stub__compressByteStreamPbPhm,@function
_Z33__device_stub__compressByteStreamPbPhm: # @_Z33__device_stub__compressByteStreamPbPhm
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18compressByteStreamPbPhm, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z33__device_stub__compressByteStreamPbPhm, .Lfunc_end3-_Z33__device_stub__compressByteStreamPbPhm
.cfi_endproc
# -- End function
.globl _Z24__device_stub__prefixSumPcPmS0_m # -- Begin function _Z24__device_stub__prefixSumPcPmS0_m
.p2align 4, 0x90
.type _Z24__device_stub__prefixSumPcPmS0_m,@function
_Z24__device_stub__prefixSumPcPmS0_m: # @_Z24__device_stub__prefixSumPcPmS0_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9prefixSumPcPmS0_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z24__device_stub__prefixSumPcPmS0_m, .Lfunc_end4-_Z24__device_stub__prefixSumPcPmS0_m
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9prefixSumPcPmS0_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13genByteStreamPcPbPmS1_S0_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18compressByteStreamPbPhm, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s raw_data huffman_table\n"
.size .L.str, 34
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Reading raw data ... "
.size .L.str.1, 22
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "r"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "done. Read %zu bytes.\n"
.size .L.str.3, 23
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[Error] %s (error code: %d) at %s line %d\n"
.size .L.str.4, 43
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/ordovicia/huffman-coding-cuda/master/main.hip"
.size .L.str.5, 103
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Reading Huffman table ... "
.size .L.str.6, 27
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "%d"
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "%zu"
.size .L.str.8, 4
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "bytes len: %zu\n"
.size .L.str.10, 16
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Bytes stream overflowed\n"
.size .L.str.11, 25
.type _Z13genByteStreamPcPbPmS1_S0_m,@object # @_Z13genByteStreamPcPbPmS1_S0_m
.section .rodata,"a",@progbits
.globl _Z13genByteStreamPcPbPmS1_S0_m
.p2align 3, 0x0
_Z13genByteStreamPcPbPmS1_S0_m:
.quad _Z28__device_stub__genByteStreamPcPbPmS1_S0_m
.size _Z13genByteStreamPcPbPmS1_S0_m, 8
.type .L.str.12,@object # @.str.12
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.12:
.asciz "bits len: %zu\n"
.size .L.str.12, 15
.type _Z18compressByteStreamPbPhm,@object # @_Z18compressByteStreamPbPhm
.section .rodata,"a",@progbits
.globl _Z18compressByteStreamPbPhm
.p2align 3, 0x0
_Z18compressByteStreamPbPhm:
.quad _Z33__device_stub__compressByteStreamPbPhm
.size _Z18compressByteStreamPbPhm, 8
.type .L.str.13,@object # @.str.13
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.13:
.asciz "bytes: %zu sec: %lf bytes/sec: %lf\n"
.size .L.str.13, 36
.type _Z9prefixSumPcPmS0_m,@object # @_Z9prefixSumPcPmS0_m
.section .rodata,"a",@progbits
.globl _Z9prefixSumPcPmS0_m
.p2align 3, 0x0
_Z9prefixSumPcPmS0_m:
.quad _Z24__device_stub__prefixSumPcPmS0_m
.size _Z9prefixSumPcPmS0_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9prefixSumPcPmS0_m"
.size .L__unnamed_1, 21
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13genByteStreamPcPbPmS1_S0_m"
.size .L__unnamed_2, 31
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z18compressByteStreamPbPhm"
.size .L__unnamed_3, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "done."
.size .Lstr, 6
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__genByteStreamPcPbPmS1_S0_m
.addrsig_sym _Z33__device_stub__compressByteStreamPbPhm
.addrsig_sym _Z24__device_stub__prefixSumPcPmS0_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13genByteStreamPcPbPmS1_S0_m
.addrsig_sym _Z18compressByteStreamPbPhm
.addrsig_sym _Z9prefixSumPcPmS0_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __device__ float backwardRelu (float forward, float chain)
{
if(forward > 0.0) {
return chain;
}
else {
return 0.0;
}
}
extern "C"
__global__ void backwardReluKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardRelu(forward[index], chain[index]);
}
} | code for sm_80
Function : backwardReluKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fc80003f04000 */
/*00e0*/ FSEL R9, R4, RZ, P0 ; /* 0x000000ff04097208 */
/* 0x008fca0000000000 */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ float backwardRelu (float forward, float chain)
{
if(forward > 0.0) {
return chain;
}
else {
return 0.0;
}
}
extern "C"
__global__ void backwardReluKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardRelu(forward[index], chain[index]);
}
} | .file "tmpxft_0010919d_00000000-6_BackwardReluKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12backwardReluff
.type _Z12backwardReluff, @function
_Z12backwardReluff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z12backwardReluff, .-_Z12backwardReluff
.globl _Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_
.type _Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_, @function
_Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq backwardReluKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_, .-_Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_
.globl backwardReluKernel
.type backwardReluKernel, @function
backwardReluKernel:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size backwardReluKernel, .-backwardReluKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "backwardReluKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq backwardReluKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ float backwardRelu (float forward, float chain)
{
if(forward > 0.0) {
return chain;
}
else {
return 0.0;
}
}
extern "C"
__global__ void backwardReluKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardRelu(forward[index], chain[index]);
}
} | #include <hip/hip_runtime.h>
__device__ float backwardRelu (float forward, float chain)
{
if(forward > 0.0) {
return chain;
}
else {
return 0.0;
}
}
extern "C"
__global__ void backwardReluKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardRelu(forward[index], chain[index]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__device__ float backwardRelu (float forward, float chain)
{
if(forward > 0.0) {
return chain;
}
else {
return 0.0;
}
}
extern "C"
__global__ void backwardReluKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardRelu(forward[index], chain[index]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected backwardReluKernel
.globl backwardReluKernel
.p2align 8
.type backwardReluKernel,@function
backwardReluKernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(1)
v_cmp_lt_f32_e32 vcc_lo, 0, v2
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v2, 0, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel backwardReluKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size backwardReluKernel, .Lfunc_end0-backwardReluKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: backwardReluKernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: backwardReluKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__device__ float backwardRelu (float forward, float chain)
{
if(forward > 0.0) {
return chain;
}
else {
return 0.0;
}
}
extern "C"
__global__ void backwardReluKernel (int length, float *forward, float *chain, float *destination)
{
int index = blockDim.x * blockIdx.x + threadIdx.x;
if(index < length) {
destination[index] = backwardRelu(forward[index], chain[index]);
}
} | .text
.file "BackwardReluKernel.hip"
.globl __device_stub__backwardReluKernel # -- Begin function __device_stub__backwardReluKernel
.p2align 4, 0x90
.type __device_stub__backwardReluKernel,@function
__device_stub__backwardReluKernel: # @__device_stub__backwardReluKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $backwardReluKernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__backwardReluKernel, .Lfunc_end0-__device_stub__backwardReluKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $backwardReluKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type backwardReluKernel,@object # @backwardReluKernel
.section .rodata,"a",@progbits
.globl backwardReluKernel
.p2align 3, 0x0
backwardReluKernel:
.quad __device_stub__backwardReluKernel
.size backwardReluKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "backwardReluKernel"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__backwardReluKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym backwardReluKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : backwardReluKernel
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x160], PT ; /* 0x0000580006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R6, R7, c[0x0][0x168] ; /* 0x00005a0006027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x170] ; /* 0x00005c0006047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ FSETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720b */
/* 0x004fc80003f04000 */
/*00e0*/ FSEL R9, R4, RZ, P0 ; /* 0x000000ff04097208 */
/* 0x008fca0000000000 */
/*00f0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected backwardReluKernel
.globl backwardReluKernel
.p2align 8
.type backwardReluKernel,@function
backwardReluKernel:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
s_waitcnt vmcnt(1)
v_cmp_lt_f32_e32 vcc_lo, 0, v2
s_waitcnt vmcnt(0)
v_cndmask_b32_e32 v2, 0, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel backwardReluKernel
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size backwardReluKernel, .Lfunc_end0-backwardReluKernel
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: backwardReluKernel
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: backwardReluKernel.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010919d_00000000-6_BackwardReluKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12backwardReluff
.type _Z12backwardReluff, @function
_Z12backwardReluff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z12backwardReluff, .-_Z12backwardReluff
.globl _Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_
.type _Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_, @function
_Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq backwardReluKernel(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_, .-_Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_
.globl backwardReluKernel
.type backwardReluKernel, @function
backwardReluKernel:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z18backwardReluKerneliPfS_S_iPfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size backwardReluKernel, .-backwardReluKernel
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "backwardReluKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq backwardReluKernel(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BackwardReluKernel.hip"
.globl __device_stub__backwardReluKernel # -- Begin function __device_stub__backwardReluKernel
.p2align 4, 0x90
.type __device_stub__backwardReluKernel,@function
__device_stub__backwardReluKernel: # @__device_stub__backwardReluKernel
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 4(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 80(%rsp)
leaq 72(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $backwardReluKernel, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__backwardReluKernel, .Lfunc_end0-__device_stub__backwardReluKernel
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $backwardReluKernel, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type backwardReluKernel,@object # @backwardReluKernel
.section .rodata,"a",@progbits
.globl backwardReluKernel
.p2align 3, 0x0
backwardReluKernel:
.quad __device_stub__backwardReluKernel
.size backwardReluKernel, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "backwardReluKernel"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__backwardReluKernel
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym backwardReluKernel
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void kernel_test1_write(char* _ptr, char* end_ptr, unsigned int* err)
{
unsigned int i;
unsigned long* ptr = (unsigned long*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned long*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned long); i++){
ptr[i] =(unsigned long) & ptr[i];
}
return;
} | code for sm_80
Function : _Z18kernel_test1_writePcS_Pj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e240000002500 */
/*0020*/ IMAD.SHL.U32 R4, R4, 0x100000, RZ ; /* 0x0010000004047824 */
/* 0x001fca00078e00ff */
/*0030*/ IADD3 R0, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004007a10 */
/* 0x000fc80007f3e0ff */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06070 */
/*0050*/ IMAD.X R0, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff007624 */
/* 0x000fca00008e06ff */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R0, c[0x0][0x16c], PT, P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x004fe200078e00ff */
/*00c0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x040fe20007f1e0ff */
/*00d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x10 ; /* 0x00000010ff097424 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R5, R5, 0x20, RZ ; /* 0x0000002005057810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x18 ; /* 0x00000018ff0b7424 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R6, P1, P2, R4, c[0x0][0x160], R7 ; /* 0x0000580004067a10 */
/* 0x000fe20007a3e007 */
/*0110*/ IMAD.MOV.U32 R13, RZ, RZ, 0x20 ; /* 0x00000020ff0d7424 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3.X R3, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x040fe200007fe4ff */
/*0130*/ IMAD.MOV.U32 R15, RZ, RZ, 0x28 ; /* 0x00000028ff0f7424 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P1, P2 ; /* 0x0000590000077a10 */
/* 0x000fe20000fe44ff */
/*0150*/ IMAD.MOV.U32 R17, RZ, RZ, 0x30 ; /* 0x00000030ff117424 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R8, P2, P3, R4.reuse, c[0x0][0x160], R9 ; /* 0x0000580004087a10 */
/* 0x040fe20007b5e009 */
/*0170*/ IMAD.MOV.U32 R19, RZ, RZ, 0x40 ; /* 0x00000040ff137424 */
/* 0x000fe200078e00ff */
/*0180*/ IADD3 R10, P0, P1, R4, c[0x0][0x160], R11 ; /* 0x00005800040a7a10 */
/* 0x000fe2000791e00b */
/*0190*/ STG.E.64 [R2.64+0x8], R6 ; /* 0x0000080602007986 */
/* 0x0001e2000c101b04 */
/*01a0*/ IADD3.X R9, R0.reuse, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000097a10 */
/* 0x040fe200017e64ff */
/*01b0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x50 ; /* 0x00000050ff157424 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3.X R11, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000b7a10 */
/* 0x000fe200007e24ff */
/*01d0*/ STG.E.64 [R2.64], R2 ; /* 0x0000000202007986 */
/* 0x000fe2000c101b04 */
/*01e0*/ IADD3 R12, P4, P5, R4, c[0x0][0x160], R13 ; /* 0x00005800040c7a10 */
/* 0x000fc40007d9e00d */
/*01f0*/ IADD3 R14, P2, P3, R4.reuse, c[0x0][0x160], R15 ; /* 0x00005800040e7a10 */
/* 0x040fe20007b5e00f */
/*0200*/ STG.E.64 [R2.64+0x10], R8 ; /* 0x0000100802007986 */
/* 0x0003e2000c101b04 */
/*0210*/ IADD3 R16, P0, P1, R4, c[0x0][0x160], R17 ; /* 0x0000580004107a10 */
/* 0x000fe4000791e011 */
/*0220*/ IADD3.X R13, R0.reuse, c[0x0][0x164], RZ, P4, P5 ; /* 0x00005900000d7a10 */
/* 0x040fe200027ea4ff */
/*0230*/ STG.E.64 [R2.64+0x18], R10 ; /* 0x0000180a02007986 */
/* 0x0005e2000c101b04 */
/*0240*/ IADD3.X R15, R0.reuse, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000f7a10 */
/* 0x040fe200017e64ff */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, 0x38 ; /* 0x00000038ff077424 */
/* 0x001fe200078e00ff */
/*0260*/ IADD3.X R17, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590000117a10 */
/* 0x000fe200007e24ff */
/*0270*/ STG.E.64 [R2.64+0x20], R12 ; /* 0x0000200c02007986 */
/* 0x0001e6000c101b04 */
/*0280*/ IADD3 R6, P2, P3, R4.reuse, c[0x0][0x160], R7 ; /* 0x0000580004067a10 */
/* 0x040fe20007b5e007 */
/*0290*/ STG.E.64 [R2.64+0x28], R14 ; /* 0x0000280e02007986 */
/* 0x0007e2000c101b04 */
/*02a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x48 ; /* 0x00000048ff097424 */
/* 0x002fe200078e00ff */
/*02b0*/ IADD3 R8, P0, P1, R4, c[0x0][0x160], R19 ; /* 0x0000580004087a10 */
/* 0x000fc4000791e013 */
/*02c0*/ STG.E.64 [R2.64+0x30], R16 ; /* 0x0000301002007986 */
/* 0x0003e2000c101b04 */
/*02d0*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fe200017e64ff */
/*02e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x58 ; /* 0x00000058ff0b7424 */
/* 0x004fe200078e00ff */
/*02f0*/ IADD3 R10, P4, P5, R4, c[0x0][0x160], R9 ; /* 0x00005800040a7a10 */
/* 0x000fe20007d9e009 */
/*0300*/ IMAD.MOV.U32 R19, RZ, RZ, 0x68 ; /* 0x00000068ff137424 */
/* 0x000fe200078e00ff */
/*0310*/ IADD3.X R9, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590000097a10 */
/* 0x000fe200007e24ff */
/*0320*/ STG.E.64 [R2.64+0x38], R6 ; /* 0x0000380602007986 */
/* 0x0005e2000c101b04 */
/*0330*/ IADD3 R12, P2, P3, R4.reuse, c[0x0][0x160], R21 ; /* 0x00005800040c7a10 */
/* 0x041fe20007b5e015 */
/*0340*/ IMAD.MOV.U32 R21, RZ, RZ, 0x78 ; /* 0x00000078ff157424 */
/* 0x000fe200078e00ff */
/*0350*/ IADD3 R14, P0, P1, R4, c[0x0][0x160], R11 ; /* 0x00005800040e7a10 */
/* 0x008fe2000791e00b */
/*0360*/ STG.E.64 [R2.64+0x40], R8 ; /* 0x0000400802007986 */
/* 0x0001e2000c101b04 */
/*0370*/ IADD3.X R11, R0.reuse, c[0x0][0x164], RZ, P4, P5 ; /* 0x00005900000b7a10 */
/* 0x040fe200027ea4ff */
/*0380*/ IMAD.MOV.U32 R17, RZ, RZ, 0x60 ; /* 0x00000060ff117424 */
/* 0x002fe200078e00ff */
/*0390*/ IADD3.X R13, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000d7a10 */
/* 0x000fc400017e64ff */
/*03a0*/ IADD3.X R15, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000f7a10 */
/* 0x000fe200007e24ff */
/*03b0*/ STG.E.64 [R2.64+0x48], R10 ; /* 0x0000480a02007986 */
/* 0x0003e2000c101b04 */
/*03c0*/ IADD3 R16, P0, P1, R4.reuse, c[0x0][0x160], R19 ; /* 0x0000580004107a10 */
/* 0x040fe2000791e013 */
/*03d0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x90 ; /* 0x00000090ff137424 */
/* 0x000fe200078e00ff */
/*03e0*/ IADD3 R6, P2, P3, R4, c[0x0][0x160], R17 ; /* 0x0000580004067a10 */
/* 0x004fe20007b5e011 */
/*03f0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x70 ; /* 0x00000070ff117424 */
/* 0x000fe200078e00ff */
/*0400*/ STG.E.64 [R2.64+0x58], R14 ; /* 0x0000580e02007986 */
/* 0x0005e2000c101b04 */
/*0410*/ IMAD.MOV.U32 R9, RZ, RZ, 0x80 ; /* 0x00000080ff097424 */
/* 0x001fe200078e00ff */
/*0420*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fe400017e64ff */
/*0430*/ STG.E.64 [R2.64+0x50], R12 ; /* 0x0000500c02007986 */
/* 0x0001e2000c101b04 */
/*0440*/ IADD3 R8, P4, P5, R4, c[0x0][0x160], R17 ; /* 0x0000580004087a10 */
/* 0x000fc40007d9e011 */
/*0450*/ IADD3.X R17, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590000117a10 */
/* 0x000fe200007e24ff */
/*0460*/ STG.E.64 [R2.64+0x60], R6 ; /* 0x0000600602007986 */
/* 0x0007e2000c101b04 */
/*0470*/ IADD3 R10, P2, P3, R4, c[0x0][0x160], R21 ; /* 0x00005800040a7a10 */
/* 0x002fe20007b5e015 */
/*0480*/ IMAD.MOV.U32 R21, RZ, RZ, 0xa0 ; /* 0x000000a0ff157424 */
/* 0x000fe400078e00ff */
/*0490*/ STG.E.64 [R2.64+0x68], R16 ; /* 0x0000681002007986 */
/* 0x0003e2000c101b04 */
/*04a0*/ IADD3.X R11, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000b7a10 */
/* 0x000fe200017e64ff */
/*04b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x88 ; /* 0x00000088ff0f7424 */
/* 0x004fe200078e00ff */
/*04c0*/ IADD3 R12, P0, P1, R4, c[0x0][0x160], R9 ; /* 0x00005800040c7a10 */
/* 0x001fc6000791e009 */
/*04d0*/ STG.E.64 [R2.64+0x78], R10 ; /* 0x0000780a02007986 */
/* 0x0001e2000c101b04 */
/*04e0*/ IADD3.X R9, R0, c[0x0][0x164], RZ, P4, P5 ; /* 0x0000590000097a10 */
/* 0x000fe400027ea4ff */
/*04f0*/ IADD3 R6, P2, P3, R4, c[0x0][0x160], R15 ; /* 0x0000580004067a10 */
/* 0x008fe20007b5e00f */
/*0500*/ IMAD.MOV.U32 R15, RZ, RZ, 0x98 ; /* 0x00000098ff0f7424 */
/* 0x000fe200078e00ff */
/*0510*/ IADD3.X R13, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000d7a10 */
/* 0x000fe200007e24ff */
/*0520*/ STG.E.64 [R2.64+0x70], R8 ; /* 0x0000700802007986 */
/* 0x0005e2000c101b04 */
/*0530*/ IADD3 R14, P0, P1, R4, c[0x0][0x160], R19 ; /* 0x00005800040e7a10 */
/* 0x000fe2000791e013 */
/*0540*/ IMAD.MOV.U32 R17, RZ, RZ, 0xa8 ; /* 0x000000a8ff117424 */
/* 0x002fe200078e00ff */
/*0550*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fe200017e64ff */
/*0560*/ STG.E.64 [R2.64+0x80], R12 ; /* 0x0000800c02007986 */
/* 0x0003e2000c101b04 */
/*0570*/ IMAD.MOV.U32 R19, RZ, RZ, 0xb8 ; /* 0x000000b8ff137424 */
/* 0x000fe200078e00ff */
/*0580*/ IADD3 R10, P2, P3, R4, c[0x0][0x160], R21 ; /* 0x00005800040a7a10 */
/* 0x001fc40007b5e015 */
/*0590*/ STG.E.64 [R2.64+0x88], R6 ; /* 0x0000880602007986 */
/* 0x0001e2000c101b04 */
/*05a0*/ IMAD.MOV.U32 R21, RZ, RZ, 0xc8 ; /* 0x000000c8ff157424 */
/* 0x000fe200078e00ff */
/*05b0*/ IADD3.X R11, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000b7a10 */
/* 0x000fe400017e64ff */
/*05c0*/ IADD3 R8, P4, P5, R4, c[0x0][0x160], R15 ; /* 0x0000580004087a10 */
/* 0x004fe40007d9e00f */
/*05d0*/ IADD3.X R15, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000f7a10 */
/* 0x000fe200007e24ff */
/*05e0*/ STG.E.64 [R2.64+0xa0], R10 ; /* 0x0000a00a02007986 */
/* 0x0005e2000c101b04 */
/*05f0*/ IADD3 R12, P0, P1, R4, c[0x0][0x160], R17 ; /* 0x00005800040c7a10 */
/* 0x002fe2000791e011 */
/*0600*/ IMAD.MOV.U32 R17, RZ, RZ, 0xb0 ; /* 0x000000b0ff117424 */
/* 0x000fe200078e00ff */
/*0610*/ IADD3.X R9, R0.reuse, c[0x0][0x164], RZ, P4, P5 ; /* 0x0000590000097a10 */
/* 0x040fe200027ea4ff */
/*0620*/ STG.E.64 [R2.64+0x90], R14 ; /* 0x0000900e02007986 */
/* 0x0003e2000c101b04 */
/*0630*/ IADD3.X R13, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000d7a10 */
/* 0x000fc400007e24ff */
/*0640*/ IADD3 R6, P2, P3, R4.reuse, c[0x0][0x160], R17 ; /* 0x0000580004067a10 */
/* 0x041fe20007b5e011 */
/*0650*/ IMAD.MOV.U32 R17, RZ, RZ, 0xc0 ; /* 0x000000c0ff117424 */
/* 0x000fe200078e00ff */
/*0660*/ IADD3 R16, P0, P1, R4, c[0x0][0x160], R19 ; /* 0x0000580004107a10 */
/* 0x000fe2000791e013 */
/*0670*/ STG.E.64 [R2.64+0x98], R8 ; /* 0x0000980802007986 */
/* 0x0001e2000c101b04 */
/*0680*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fe200017e64ff */
/*0690*/ IMAD.MOV.U32 R19, RZ, RZ, 0xe0 ; /* 0x000000e0ff137424 */
/* 0x000fe400078e00ff */
/*06a0*/ STG.E.64 [R2.64+0xa8], R12 ; /* 0x0000a80c02007986 */
/* 0x0007e2000c101b04 */
/*06b0*/ IADD3 R10, P2, P3, R4, c[0x0][0x160], R21 ; /* 0x00005800040a7a10 */
/* 0x004fe20007b5e015 */
/*06c0*/ IMAD.MOV.U32 R21, RZ, RZ, 0xf0 ; /* 0x000000f0ff157424 */
/* 0x000fe400078e00ff */
/*06d0*/ IMAD.MOV.U32 R15, RZ, RZ, 0xd0 ; /* 0x000000d0ff0f7424 */
/* 0x002fe200078e00ff */
/*06e0*/ STG.E.64 [R2.64+0xb0], R6 ; /* 0x0000b00602007986 */
/* 0x0003e2000c101b04 */
/*06f0*/ IADD3.X R11, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000b7a10 */
/* 0x000fc400017e64ff */
/*0700*/ IADD3 R8, P4, P5, R4, c[0x0][0x160], R17 ; /* 0x0000580004087a10 */
/* 0x001fc60007d9e011 */
/*0710*/ STG.E.64 [R2.64+0xc8], R10 ; /* 0x0000c80a02007986 */
/* 0x0001e2000c101b04 */
/*0720*/ IADD3.X R17, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590000117a10 */
/* 0x000fe400007e24ff */
/*0730*/ IADD3 R12, P0, P1, R4, c[0x0][0x160], R15 ; /* 0x00005800040c7a10 */
/* 0x008fe2000791e00f */
/*0740*/ IMAD.MOV.U32 R15, RZ, RZ, 0xd8 ; /* 0x000000d8ff0f7424 */
/* 0x000fe200078e00ff */
/*0750*/ IADD3.X R9, R0.reuse, c[0x0][0x164], RZ, P4, P5 ; /* 0x0000590000097a10 */
/* 0x040fe200027ea4ff */
/*0760*/ STG.E.64 [R2.64+0xb8], R16 ; /* 0x0000b81002007986 */
/* 0x0005e2000c101b04 */
/*0770*/ IADD3.X R13, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000d7a10 */
/* 0x000fe400007e24ff */
/*0780*/ IADD3 R6, P2, P3, R4.reuse, c[0x0][0x160], R15 ; /* 0x0000580004067a10 */
/* 0x042fe20007b5e00f */
/*0790*/ IMAD.MOV.U32 R15, RZ, RZ, 0xe8 ; /* 0x000000e8ff0f7424 */
/* 0x000fe200078e00ff */
/*07a0*/ IADD3 R14, P0, P1, R4, c[0x0][0x160], R19 ; /* 0x00005800040e7a10 */
/* 0x000fe2000791e013 */
/*07b0*/ STG.E.64 [R2.64+0xc0], R8 ; /* 0x0000c00802007986 */
/* 0x0003e2000c101b04 */
/*07c0*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fc400017e64ff */
/*07d0*/ IADD3 R10, P2, P3, R4, c[0x0][0x160], R21 ; /* 0x00005800040a7a10 */
/* 0x001fe20007b5e015 */
/*07e0*/ STG.E.64 [R2.64+0xd0], R12 ; /* 0x0000d00c02007986 */
/* 0x0001e6000c101b04 */
/*07f0*/ IADD3.X R11, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000b7a10 */
/* 0x000fe200017e64ff */
/*0800*/ IMAD.MOV.U32 R17, RZ, RZ, 0xf8 ; /* 0x000000f8ff117424 */
/* 0x004fe200078e00ff */
/*0810*/ STG.E.64 [R2.64+0xd8], R6 ; /* 0x0000d80602007986 */
/* 0x0005e8000c101b04 */
/*0820*/ STG.E.64 [R2.64+0xf0], R10 ; /* 0x0000f00a02007986 */
/* 0x0005e2000c101b04 */
/*0830*/ IADD3 R8, P4, P5, R4, c[0x0][0x160], R15 ; /* 0x0000580004087a10 */
/* 0x002fc40007d9e00f */
/*0840*/ IADD3.X R15, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000f7a10 */
/* 0x000fe400007e24ff */
/*0850*/ IADD3 R12, P0, P1, R4, c[0x0][0x160], R17 ; /* 0x00005800040c7a10 */
/* 0x001fe4000791e011 */
/*0860*/ IADD3.X R9, R0.reuse, c[0x0][0x164], RZ, P4, P5 ; /* 0x0000590000097a10 */
/* 0x040fe200027ea4ff */
/*0870*/ STG.E.64 [R2.64+0xe0], R14 ; /* 0x0000e00e02007986 */
/* 0x0005e2000c101b04 */
/*0880*/ IADD3.X R13, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000d7a10 */
/* 0x000fe400007e24ff */
/*0890*/ ISETP.NE.AND P0, PT, R5, 0x20000, PT ; /* 0x000200000500780c */
/* 0x000fe20003f05270 */
/*08a0*/ STG.E.64 [R2.64+0xe8], R8 ; /* 0x0000e80802007986 */
/* 0x0005e2000c101b04 */
/*08b0*/ IADD3 R4, P1, R4, 0x100, RZ ; /* 0x0000010004047810 */
/* 0x000fc60007f3e0ff */
/*08c0*/ STG.E.64 [R2.64+0xf8], R12 ; /* 0x0000f80c02007986 */
/* 0x0005e4000c101b04 */
/*08d0*/ IMAD.X R0, RZ, RZ, R0, P1 ; /* 0x000000ffff007224 */
/* 0x000fcc00008e0600 */
/*08e0*/ @P0 BRA 0xb0 ; /* 0xfffff7c000000947 */
/* 0x000fea000383ffff */
/*08f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void kernel_test1_write(char* _ptr, char* end_ptr, unsigned int* err)
{
unsigned int i;
unsigned long* ptr = (unsigned long*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned long*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned long); i++){
ptr[i] =(unsigned long) & ptr[i];
}
return;
} | .file "tmpxft_0003231c_00000000-6_kernel_test1_write.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj
.type _Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj, @function
_Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kernel_test1_writePcS_Pj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj, .-_Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj
.globl _Z18kernel_test1_writePcS_Pj
.type _Z18kernel_test1_writePcS_Pj, @function
_Z18kernel_test1_writePcS_Pj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernel_test1_writePcS_Pj, .-_Z18kernel_test1_writePcS_Pj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kernel_test1_writePcS_Pj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_test1_writePcS_Pj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void kernel_test1_write(char* _ptr, char* end_ptr, unsigned int* err)
{
unsigned int i;
unsigned long* ptr = (unsigned long*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned long*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned long); i++){
ptr[i] =(unsigned long) & ptr[i];
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_test1_write(char* _ptr, char* end_ptr, unsigned int* err)
{
unsigned int i;
unsigned long* ptr = (unsigned long*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned long*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned long); i++){
ptr[i] =(unsigned long) & ptr[i];
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_test1_write(char* _ptr, char* end_ptr, unsigned int* err)
{
unsigned int i;
unsigned long* ptr = (unsigned long*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned long*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned long); i++){
ptr[i] =(unsigned long) & ptr[i];
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernel_test1_writePcS_Pj
.globl _Z18kernel_test1_writePcS_Pj
.p2align 8
.type _Z18kernel_test1_writePcS_Pj,@function
_Z18kernel_test1_writePcS_Pj:
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b32 s4, s15, 20
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s2, s[0:1], s[2:3]
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_3
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 0x100000
global_store_b64 v0, v[1:2], s[4:5]
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernel_test1_writePcS_Pj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernel_test1_writePcS_Pj, .Lfunc_end0-_Z18kernel_test1_writePcS_Pj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernel_test1_writePcS_Pj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kernel_test1_writePcS_Pj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void kernel_test1_write(char* _ptr, char* end_ptr, unsigned int* err)
{
unsigned int i;
unsigned long* ptr = (unsigned long*) (_ptr + blockIdx.x*BLOCKSIZE);
if (ptr >= (unsigned long*) end_ptr) {
return;
}
for (i = 0;i < BLOCKSIZE/sizeof(unsigned long); i++){
ptr[i] =(unsigned long) & ptr[i];
}
return;
} | .text
.file "kernel_test1_write.hip"
.globl _Z33__device_stub__kernel_test1_writePcS_Pj # -- Begin function _Z33__device_stub__kernel_test1_writePcS_Pj
.p2align 4, 0x90
.type _Z33__device_stub__kernel_test1_writePcS_Pj,@function
_Z33__device_stub__kernel_test1_writePcS_Pj: # @_Z33__device_stub__kernel_test1_writePcS_Pj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kernel_test1_writePcS_Pj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__kernel_test1_writePcS_Pj, .Lfunc_end0-_Z33__device_stub__kernel_test1_writePcS_Pj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_test1_writePcS_Pj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernel_test1_writePcS_Pj,@object # @_Z18kernel_test1_writePcS_Pj
.section .rodata,"a",@progbits
.globl _Z18kernel_test1_writePcS_Pj
.p2align 3, 0x0
_Z18kernel_test1_writePcS_Pj:
.quad _Z33__device_stub__kernel_test1_writePcS_Pj
.size _Z18kernel_test1_writePcS_Pj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernel_test1_writePcS_Pj"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernel_test1_writePcS_Pj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernel_test1_writePcS_Pj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18kernel_test1_writePcS_Pj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e240000002500 */
/*0020*/ IMAD.SHL.U32 R4, R4, 0x100000, RZ ; /* 0x0010000004047824 */
/* 0x001fca00078e00ff */
/*0030*/ IADD3 R0, P1, R4, c[0x0][0x160], RZ ; /* 0x0000580004007a10 */
/* 0x000fc80007f3e0ff */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe20003f06070 */
/*0050*/ IMAD.X R0, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff007624 */
/* 0x000fca00008e06ff */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R0, c[0x0][0x16c], PT, P0 ; /* 0x00005b0000007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*00b0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x004fe200078e00ff */
/*00c0*/ IADD3 R2, P0, R4.reuse, c[0x0][0x160], RZ ; /* 0x0000580004027a10 */
/* 0x040fe20007f1e0ff */
/*00d0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x10 ; /* 0x00000010ff097424 */
/* 0x000fe200078e00ff */
/*00e0*/ IADD3 R5, R5, 0x20, RZ ; /* 0x0000002005057810 */
/* 0x000fe20007ffe0ff */
/*00f0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x18 ; /* 0x00000018ff0b7424 */
/* 0x000fe200078e00ff */
/*0100*/ IADD3 R6, P1, P2, R4, c[0x0][0x160], R7 ; /* 0x0000580004067a10 */
/* 0x000fe20007a3e007 */
/*0110*/ IMAD.MOV.U32 R13, RZ, RZ, 0x20 ; /* 0x00000020ff0d7424 */
/* 0x000fe200078e00ff */
/*0120*/ IADD3.X R3, R0.reuse, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590000037a10 */
/* 0x040fe200007fe4ff */
/*0130*/ IMAD.MOV.U32 R15, RZ, RZ, 0x28 ; /* 0x00000028ff0f7424 */
/* 0x000fe200078e00ff */
/*0140*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P1, P2 ; /* 0x0000590000077a10 */
/* 0x000fe20000fe44ff */
/*0150*/ IMAD.MOV.U32 R17, RZ, RZ, 0x30 ; /* 0x00000030ff117424 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R8, P2, P3, R4.reuse, c[0x0][0x160], R9 ; /* 0x0000580004087a10 */
/* 0x040fe20007b5e009 */
/*0170*/ IMAD.MOV.U32 R19, RZ, RZ, 0x40 ; /* 0x00000040ff137424 */
/* 0x000fe200078e00ff */
/*0180*/ IADD3 R10, P0, P1, R4, c[0x0][0x160], R11 ; /* 0x00005800040a7a10 */
/* 0x000fe2000791e00b */
/*0190*/ STG.E.64 [R2.64+0x8], R6 ; /* 0x0000080602007986 */
/* 0x0001e2000c101b04 */
/*01a0*/ IADD3.X R9, R0.reuse, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000097a10 */
/* 0x040fe200017e64ff */
/*01b0*/ IMAD.MOV.U32 R21, RZ, RZ, 0x50 ; /* 0x00000050ff157424 */
/* 0x000fe200078e00ff */
/*01c0*/ IADD3.X R11, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000b7a10 */
/* 0x000fe200007e24ff */
/*01d0*/ STG.E.64 [R2.64], R2 ; /* 0x0000000202007986 */
/* 0x000fe2000c101b04 */
/*01e0*/ IADD3 R12, P4, P5, R4, c[0x0][0x160], R13 ; /* 0x00005800040c7a10 */
/* 0x000fc40007d9e00d */
/*01f0*/ IADD3 R14, P2, P3, R4.reuse, c[0x0][0x160], R15 ; /* 0x00005800040e7a10 */
/* 0x040fe20007b5e00f */
/*0200*/ STG.E.64 [R2.64+0x10], R8 ; /* 0x0000100802007986 */
/* 0x0003e2000c101b04 */
/*0210*/ IADD3 R16, P0, P1, R4, c[0x0][0x160], R17 ; /* 0x0000580004107a10 */
/* 0x000fe4000791e011 */
/*0220*/ IADD3.X R13, R0.reuse, c[0x0][0x164], RZ, P4, P5 ; /* 0x00005900000d7a10 */
/* 0x040fe200027ea4ff */
/*0230*/ STG.E.64 [R2.64+0x18], R10 ; /* 0x0000180a02007986 */
/* 0x0005e2000c101b04 */
/*0240*/ IADD3.X R15, R0.reuse, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000f7a10 */
/* 0x040fe200017e64ff */
/*0250*/ IMAD.MOV.U32 R7, RZ, RZ, 0x38 ; /* 0x00000038ff077424 */
/* 0x001fe200078e00ff */
/*0260*/ IADD3.X R17, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590000117a10 */
/* 0x000fe200007e24ff */
/*0270*/ STG.E.64 [R2.64+0x20], R12 ; /* 0x0000200c02007986 */
/* 0x0001e6000c101b04 */
/*0280*/ IADD3 R6, P2, P3, R4.reuse, c[0x0][0x160], R7 ; /* 0x0000580004067a10 */
/* 0x040fe20007b5e007 */
/*0290*/ STG.E.64 [R2.64+0x28], R14 ; /* 0x0000280e02007986 */
/* 0x0007e2000c101b04 */
/*02a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x48 ; /* 0x00000048ff097424 */
/* 0x002fe200078e00ff */
/*02b0*/ IADD3 R8, P0, P1, R4, c[0x0][0x160], R19 ; /* 0x0000580004087a10 */
/* 0x000fc4000791e013 */
/*02c0*/ STG.E.64 [R2.64+0x30], R16 ; /* 0x0000301002007986 */
/* 0x0003e2000c101b04 */
/*02d0*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fe200017e64ff */
/*02e0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x58 ; /* 0x00000058ff0b7424 */
/* 0x004fe200078e00ff */
/*02f0*/ IADD3 R10, P4, P5, R4, c[0x0][0x160], R9 ; /* 0x00005800040a7a10 */
/* 0x000fe20007d9e009 */
/*0300*/ IMAD.MOV.U32 R19, RZ, RZ, 0x68 ; /* 0x00000068ff137424 */
/* 0x000fe200078e00ff */
/*0310*/ IADD3.X R9, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590000097a10 */
/* 0x000fe200007e24ff */
/*0320*/ STG.E.64 [R2.64+0x38], R6 ; /* 0x0000380602007986 */
/* 0x0005e2000c101b04 */
/*0330*/ IADD3 R12, P2, P3, R4.reuse, c[0x0][0x160], R21 ; /* 0x00005800040c7a10 */
/* 0x041fe20007b5e015 */
/*0340*/ IMAD.MOV.U32 R21, RZ, RZ, 0x78 ; /* 0x00000078ff157424 */
/* 0x000fe200078e00ff */
/*0350*/ IADD3 R14, P0, P1, R4, c[0x0][0x160], R11 ; /* 0x00005800040e7a10 */
/* 0x008fe2000791e00b */
/*0360*/ STG.E.64 [R2.64+0x40], R8 ; /* 0x0000400802007986 */
/* 0x0001e2000c101b04 */
/*0370*/ IADD3.X R11, R0.reuse, c[0x0][0x164], RZ, P4, P5 ; /* 0x00005900000b7a10 */
/* 0x040fe200027ea4ff */
/*0380*/ IMAD.MOV.U32 R17, RZ, RZ, 0x60 ; /* 0x00000060ff117424 */
/* 0x002fe200078e00ff */
/*0390*/ IADD3.X R13, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000d7a10 */
/* 0x000fc400017e64ff */
/*03a0*/ IADD3.X R15, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000f7a10 */
/* 0x000fe200007e24ff */
/*03b0*/ STG.E.64 [R2.64+0x48], R10 ; /* 0x0000480a02007986 */
/* 0x0003e2000c101b04 */
/*03c0*/ IADD3 R16, P0, P1, R4.reuse, c[0x0][0x160], R19 ; /* 0x0000580004107a10 */
/* 0x040fe2000791e013 */
/*03d0*/ IMAD.MOV.U32 R19, RZ, RZ, 0x90 ; /* 0x00000090ff137424 */
/* 0x000fe200078e00ff */
/*03e0*/ IADD3 R6, P2, P3, R4, c[0x0][0x160], R17 ; /* 0x0000580004067a10 */
/* 0x004fe20007b5e011 */
/*03f0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x70 ; /* 0x00000070ff117424 */
/* 0x000fe200078e00ff */
/*0400*/ STG.E.64 [R2.64+0x58], R14 ; /* 0x0000580e02007986 */
/* 0x0005e2000c101b04 */
/*0410*/ IMAD.MOV.U32 R9, RZ, RZ, 0x80 ; /* 0x00000080ff097424 */
/* 0x001fe200078e00ff */
/*0420*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fe400017e64ff */
/*0430*/ STG.E.64 [R2.64+0x50], R12 ; /* 0x0000500c02007986 */
/* 0x0001e2000c101b04 */
/*0440*/ IADD3 R8, P4, P5, R4, c[0x0][0x160], R17 ; /* 0x0000580004087a10 */
/* 0x000fc40007d9e011 */
/*0450*/ IADD3.X R17, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590000117a10 */
/* 0x000fe200007e24ff */
/*0460*/ STG.E.64 [R2.64+0x60], R6 ; /* 0x0000600602007986 */
/* 0x0007e2000c101b04 */
/*0470*/ IADD3 R10, P2, P3, R4, c[0x0][0x160], R21 ; /* 0x00005800040a7a10 */
/* 0x002fe20007b5e015 */
/*0480*/ IMAD.MOV.U32 R21, RZ, RZ, 0xa0 ; /* 0x000000a0ff157424 */
/* 0x000fe400078e00ff */
/*0490*/ STG.E.64 [R2.64+0x68], R16 ; /* 0x0000681002007986 */
/* 0x0003e2000c101b04 */
/*04a0*/ IADD3.X R11, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000b7a10 */
/* 0x000fe200017e64ff */
/*04b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x88 ; /* 0x00000088ff0f7424 */
/* 0x004fe200078e00ff */
/*04c0*/ IADD3 R12, P0, P1, R4, c[0x0][0x160], R9 ; /* 0x00005800040c7a10 */
/* 0x001fc6000791e009 */
/*04d0*/ STG.E.64 [R2.64+0x78], R10 ; /* 0x0000780a02007986 */
/* 0x0001e2000c101b04 */
/*04e0*/ IADD3.X R9, R0, c[0x0][0x164], RZ, P4, P5 ; /* 0x0000590000097a10 */
/* 0x000fe400027ea4ff */
/*04f0*/ IADD3 R6, P2, P3, R4, c[0x0][0x160], R15 ; /* 0x0000580004067a10 */
/* 0x008fe20007b5e00f */
/*0500*/ IMAD.MOV.U32 R15, RZ, RZ, 0x98 ; /* 0x00000098ff0f7424 */
/* 0x000fe200078e00ff */
/*0510*/ IADD3.X R13, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000d7a10 */
/* 0x000fe200007e24ff */
/*0520*/ STG.E.64 [R2.64+0x70], R8 ; /* 0x0000700802007986 */
/* 0x0005e2000c101b04 */
/*0530*/ IADD3 R14, P0, P1, R4, c[0x0][0x160], R19 ; /* 0x00005800040e7a10 */
/* 0x000fe2000791e013 */
/*0540*/ IMAD.MOV.U32 R17, RZ, RZ, 0xa8 ; /* 0x000000a8ff117424 */
/* 0x002fe200078e00ff */
/*0550*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fe200017e64ff */
/*0560*/ STG.E.64 [R2.64+0x80], R12 ; /* 0x0000800c02007986 */
/* 0x0003e2000c101b04 */
/*0570*/ IMAD.MOV.U32 R19, RZ, RZ, 0xb8 ; /* 0x000000b8ff137424 */
/* 0x000fe200078e00ff */
/*0580*/ IADD3 R10, P2, P3, R4, c[0x0][0x160], R21 ; /* 0x00005800040a7a10 */
/* 0x001fc40007b5e015 */
/*0590*/ STG.E.64 [R2.64+0x88], R6 ; /* 0x0000880602007986 */
/* 0x0001e2000c101b04 */
/*05a0*/ IMAD.MOV.U32 R21, RZ, RZ, 0xc8 ; /* 0x000000c8ff157424 */
/* 0x000fe200078e00ff */
/*05b0*/ IADD3.X R11, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000b7a10 */
/* 0x000fe400017e64ff */
/*05c0*/ IADD3 R8, P4, P5, R4, c[0x0][0x160], R15 ; /* 0x0000580004087a10 */
/* 0x004fe40007d9e00f */
/*05d0*/ IADD3.X R15, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000f7a10 */
/* 0x000fe200007e24ff */
/*05e0*/ STG.E.64 [R2.64+0xa0], R10 ; /* 0x0000a00a02007986 */
/* 0x0005e2000c101b04 */
/*05f0*/ IADD3 R12, P0, P1, R4, c[0x0][0x160], R17 ; /* 0x00005800040c7a10 */
/* 0x002fe2000791e011 */
/*0600*/ IMAD.MOV.U32 R17, RZ, RZ, 0xb0 ; /* 0x000000b0ff117424 */
/* 0x000fe200078e00ff */
/*0610*/ IADD3.X R9, R0.reuse, c[0x0][0x164], RZ, P4, P5 ; /* 0x0000590000097a10 */
/* 0x040fe200027ea4ff */
/*0620*/ STG.E.64 [R2.64+0x90], R14 ; /* 0x0000900e02007986 */
/* 0x0003e2000c101b04 */
/*0630*/ IADD3.X R13, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000d7a10 */
/* 0x000fc400007e24ff */
/*0640*/ IADD3 R6, P2, P3, R4.reuse, c[0x0][0x160], R17 ; /* 0x0000580004067a10 */
/* 0x041fe20007b5e011 */
/*0650*/ IMAD.MOV.U32 R17, RZ, RZ, 0xc0 ; /* 0x000000c0ff117424 */
/* 0x000fe200078e00ff */
/*0660*/ IADD3 R16, P0, P1, R4, c[0x0][0x160], R19 ; /* 0x0000580004107a10 */
/* 0x000fe2000791e013 */
/*0670*/ STG.E.64 [R2.64+0x98], R8 ; /* 0x0000980802007986 */
/* 0x0001e2000c101b04 */
/*0680*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fe200017e64ff */
/*0690*/ IMAD.MOV.U32 R19, RZ, RZ, 0xe0 ; /* 0x000000e0ff137424 */
/* 0x000fe400078e00ff */
/*06a0*/ STG.E.64 [R2.64+0xa8], R12 ; /* 0x0000a80c02007986 */
/* 0x0007e2000c101b04 */
/*06b0*/ IADD3 R10, P2, P3, R4, c[0x0][0x160], R21 ; /* 0x00005800040a7a10 */
/* 0x004fe20007b5e015 */
/*06c0*/ IMAD.MOV.U32 R21, RZ, RZ, 0xf0 ; /* 0x000000f0ff157424 */
/* 0x000fe400078e00ff */
/*06d0*/ IMAD.MOV.U32 R15, RZ, RZ, 0xd0 ; /* 0x000000d0ff0f7424 */
/* 0x002fe200078e00ff */
/*06e0*/ STG.E.64 [R2.64+0xb0], R6 ; /* 0x0000b00602007986 */
/* 0x0003e2000c101b04 */
/*06f0*/ IADD3.X R11, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000b7a10 */
/* 0x000fc400017e64ff */
/*0700*/ IADD3 R8, P4, P5, R4, c[0x0][0x160], R17 ; /* 0x0000580004087a10 */
/* 0x001fc60007d9e011 */
/*0710*/ STG.E.64 [R2.64+0xc8], R10 ; /* 0x0000c80a02007986 */
/* 0x0001e2000c101b04 */
/*0720*/ IADD3.X R17, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x0000590000117a10 */
/* 0x000fe400007e24ff */
/*0730*/ IADD3 R12, P0, P1, R4, c[0x0][0x160], R15 ; /* 0x00005800040c7a10 */
/* 0x008fe2000791e00f */
/*0740*/ IMAD.MOV.U32 R15, RZ, RZ, 0xd8 ; /* 0x000000d8ff0f7424 */
/* 0x000fe200078e00ff */
/*0750*/ IADD3.X R9, R0.reuse, c[0x0][0x164], RZ, P4, P5 ; /* 0x0000590000097a10 */
/* 0x040fe200027ea4ff */
/*0760*/ STG.E.64 [R2.64+0xb8], R16 ; /* 0x0000b81002007986 */
/* 0x0005e2000c101b04 */
/*0770*/ IADD3.X R13, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000d7a10 */
/* 0x000fe400007e24ff */
/*0780*/ IADD3 R6, P2, P3, R4.reuse, c[0x0][0x160], R15 ; /* 0x0000580004067a10 */
/* 0x042fe20007b5e00f */
/*0790*/ IMAD.MOV.U32 R15, RZ, RZ, 0xe8 ; /* 0x000000e8ff0f7424 */
/* 0x000fe200078e00ff */
/*07a0*/ IADD3 R14, P0, P1, R4, c[0x0][0x160], R19 ; /* 0x00005800040e7a10 */
/* 0x000fe2000791e013 */
/*07b0*/ STG.E.64 [R2.64+0xc0], R8 ; /* 0x0000c00802007986 */
/* 0x0003e2000c101b04 */
/*07c0*/ IADD3.X R7, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x0000590000077a10 */
/* 0x000fc400017e64ff */
/*07d0*/ IADD3 R10, P2, P3, R4, c[0x0][0x160], R21 ; /* 0x00005800040a7a10 */
/* 0x001fe20007b5e015 */
/*07e0*/ STG.E.64 [R2.64+0xd0], R12 ; /* 0x0000d00c02007986 */
/* 0x0001e6000c101b04 */
/*07f0*/ IADD3.X R11, R0, c[0x0][0x164], RZ, P2, P3 ; /* 0x00005900000b7a10 */
/* 0x000fe200017e64ff */
/*0800*/ IMAD.MOV.U32 R17, RZ, RZ, 0xf8 ; /* 0x000000f8ff117424 */
/* 0x004fe200078e00ff */
/*0810*/ STG.E.64 [R2.64+0xd8], R6 ; /* 0x0000d80602007986 */
/* 0x0005e8000c101b04 */
/*0820*/ STG.E.64 [R2.64+0xf0], R10 ; /* 0x0000f00a02007986 */
/* 0x0005e2000c101b04 */
/*0830*/ IADD3 R8, P4, P5, R4, c[0x0][0x160], R15 ; /* 0x0000580004087a10 */
/* 0x002fc40007d9e00f */
/*0840*/ IADD3.X R15, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000f7a10 */
/* 0x000fe400007e24ff */
/*0850*/ IADD3 R12, P0, P1, R4, c[0x0][0x160], R17 ; /* 0x00005800040c7a10 */
/* 0x001fe4000791e011 */
/*0860*/ IADD3.X R9, R0.reuse, c[0x0][0x164], RZ, P4, P5 ; /* 0x0000590000097a10 */
/* 0x040fe200027ea4ff */
/*0870*/ STG.E.64 [R2.64+0xe0], R14 ; /* 0x0000e00e02007986 */
/* 0x0005e2000c101b04 */
/*0880*/ IADD3.X R13, R0, c[0x0][0x164], RZ, P0, P1 ; /* 0x00005900000d7a10 */
/* 0x000fe400007e24ff */
/*0890*/ ISETP.NE.AND P0, PT, R5, 0x20000, PT ; /* 0x000200000500780c */
/* 0x000fe20003f05270 */
/*08a0*/ STG.E.64 [R2.64+0xe8], R8 ; /* 0x0000e80802007986 */
/* 0x0005e2000c101b04 */
/*08b0*/ IADD3 R4, P1, R4, 0x100, RZ ; /* 0x0000010004047810 */
/* 0x000fc60007f3e0ff */
/*08c0*/ STG.E.64 [R2.64+0xf8], R12 ; /* 0x0000f80c02007986 */
/* 0x0005e4000c101b04 */
/*08d0*/ IMAD.X R0, RZ, RZ, R0, P1 ; /* 0x000000ffff007224 */
/* 0x000fcc00008e0600 */
/*08e0*/ @P0 BRA 0xb0 ; /* 0xfffff7c000000947 */
/* 0x000fea000383ffff */
/*08f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18kernel_test1_writePcS_Pj
.globl _Z18kernel_test1_writePcS_Pj
.p2align 8
.type _Z18kernel_test1_writePcS_Pj,@function
_Z18kernel_test1_writePcS_Pj:
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b32 s4, s15, 20
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u64_e64 s2, s[0:1], s[2:3]
s_and_b32 vcc_lo, exec_lo, s2
s_cbranch_vccnz .LBB0_3
v_mov_b32_e32 v0, 0
s_mov_b64 s[2:3], 0
.LBB0_2:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_u32 s4, s0, s2
s_addc_u32 s5, s1, s3
v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5
s_add_u32 s2, s2, 8
s_addc_u32 s3, s3, 0
s_cmp_lg_u32 s2, 0x100000
global_store_b64 v0, v[1:2], s[4:5]
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18kernel_test1_writePcS_Pj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18kernel_test1_writePcS_Pj, .Lfunc_end0-_Z18kernel_test1_writePcS_Pj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18kernel_test1_writePcS_Pj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18kernel_test1_writePcS_Pj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0003231c_00000000-6_kernel_test1_write.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj
.type _Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj, @function
_Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18kernel_test1_writePcS_Pj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj, .-_Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj
.globl _Z18kernel_test1_writePcS_Pj
.type _Z18kernel_test1_writePcS_Pj, @function
_Z18kernel_test1_writePcS_Pj:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z18kernel_test1_writePcS_PjPcS_Pj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18kernel_test1_writePcS_Pj, .-_Z18kernel_test1_writePcS_Pj
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z18kernel_test1_writePcS_Pj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18kernel_test1_writePcS_Pj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_test1_write.hip"
.globl _Z33__device_stub__kernel_test1_writePcS_Pj # -- Begin function _Z33__device_stub__kernel_test1_writePcS_Pj
.p2align 4, 0x90
.type _Z33__device_stub__kernel_test1_writePcS_Pj,@function
_Z33__device_stub__kernel_test1_writePcS_Pj: # @_Z33__device_stub__kernel_test1_writePcS_Pj
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18kernel_test1_writePcS_Pj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z33__device_stub__kernel_test1_writePcS_Pj, .Lfunc_end0-_Z33__device_stub__kernel_test1_writePcS_Pj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18kernel_test1_writePcS_Pj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18kernel_test1_writePcS_Pj,@object # @_Z18kernel_test1_writePcS_Pj
.section .rodata,"a",@progbits
.globl _Z18kernel_test1_writePcS_Pj
.p2align 3, 0x0
_Z18kernel_test1_writePcS_Pj:
.quad _Z33__device_stub__kernel_test1_writePcS_Pj
.size _Z18kernel_test1_writePcS_Pj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18kernel_test1_writePcS_Pj"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__kernel_test1_writePcS_Pj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18kernel_test1_writePcS_Pj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* jacobi.c - Poisson problem in 3d
*
*/
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu2(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
double temp;
int j_index=threadIdx.y + blockIdx.y*blockDim.y;
int k_index= threadIdx.x + blockIdx.x*blockDim.x;
int i_index=threadIdx.z + blockIdx.z*blockDim.z;
//printf("%d %d %d \n", j_index, k_index, i_index);
if ((j_index<N-2) && (k_index<N-2) && (i_index<N-2)){
temp=prev_u[i_index][j_index+1][k_index+1] + prev_u[i_index+2][j_index+1][k_index+1]+
prev_u[i_index+1][j_index][k_index+1] + prev_u[i_index+1][j_index+2][k_index+1] +
prev_u[i_index+1][j_index+1][k_index]+ prev_u[i_index+1][j_index+1][k_index+2] + step_width*step_width*f[i_index+1][j_index+1][k_index+1];
u[i_index+1][j_index+1][k_index+1]=temp*denominator;
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} | code for sm_80
Function : _Z11jacobi_gpu2PPPdS1_S1_idd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R21, SR_CTAID.X ; /* 0x0000000000157919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0050*/ S2R R23, SR_CTAID.Y ; /* 0x0000000000177919 */
/* 0x000e680000002600 */
/*0060*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*0070*/ S2R R11, SR_CTAID.Z ; /* 0x00000000000b7919 */
/* 0x000ea80000002700 */
/*0080*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000ea20000002300 */
/*0090*/ IMAD R21, R21, c[0x0][0x0], R2 ; /* 0x0000000015157a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R21, UR4, PT ; /* 0x0000000415007c0c */
/* 0x000fe2000bf06270 */
/*00b0*/ IMAD R23, R23, c[0x0][0x4], R0 ; /* 0x0000010017177a24 */
/* 0x002fca00078e0200 */
/*00c0*/ ISETP.GE.OR P0, PT, R23, UR4, P0 ; /* 0x0000000417007c0c */
/* 0x000fe20008706670 */
/*00d0*/ IMAD R11, R11, c[0x0][0x8], R4 ; /* 0x000002000b0b7a24 */
/* 0x004fca00078e0204 */
/*00e0*/ ISETP.GE.OR P0, PT, R11, UR4, P0 ; /* 0x000000040b007c0c */
/* 0x000fda0008706670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff007435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0120*/ IMAD.WIDE R2, R11, R0, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x000fca00078e0200 */
/*0130*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0140*/ LDG.E.64 R8, [R2.64+0x10] ; /* 0x0000100402087981 */
/* 0x000ee8000c1e1b00 */
/*0150*/ LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080402107981 */
/* 0x000f22000c1e1b00 */
/*0160*/ IMAD.WIDE R6, R11, R0, c[0x0][0x170] ; /* 0x00005c000b067625 */
/* 0x000fcc00078e0200 */
/*0170*/ LDG.E.64 R6, [R6.64+0x8] ; /* 0x0000080406067981 */
/* 0x000f62000c1e1b00 */
/*0180*/ IADD3 R13, R23, 0x1, RZ ; /* 0x00000001170d7810 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD.WIDE R10, R11, R0, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fcc00078e0200 */
/*01a0*/ LDG.E.64 R10, [R10.64+0x8] ; /* 0x000008040a0a7981 */
/* 0x000f62000c1e1b00 */
/*01b0*/ IMAD.WIDE R14, R13, 0x8, R4 ; /* 0x000000080d0e7825 */
/* 0x004fc800078e0204 */
/*01c0*/ IMAD.WIDE R18, R13, 0x8, R8 ; /* 0x000000080d127825 */
/* 0x008fe400078e0208 */
/*01d0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*01e0*/ IMAD.WIDE R22, R23, 0x8, R16 ; /* 0x0000000817167825 */
/* 0x010fe400078e0210 */
/*01f0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee8000c1e1b00 */
/*0200*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000f28000c1e1b00 */
/*0210*/ LDG.E.64 R4, [R22.64+0x10] ; /* 0x0000100416047981 */
/* 0x000f28000c1e1b00 */
/*0220*/ LDG.E.64 R2, [R22.64+0x8] ; /* 0x0000080416027981 */
/* 0x000f22000c1e1b00 */
/*0230*/ IMAD.WIDE R24, R13, 0x8, R6 ; /* 0x000000080d187825 */
/* 0x020fca00078e0206 */
/*0240*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x000f62000c1e1b00 */
/*0250*/ IADD3 R17, R21, 0x1, RZ ; /* 0x0000000115117810 */
/* 0x000fe20007ffe0ff */
/*0260*/ IMAD.WIDE R10, R13, 0x8, R10 ; /* 0x000000080d0a7825 */
/* 0x000fcc00078e020a */
/*0270*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f62000c1e1b00 */
/*0280*/ IMAD.WIDE R14, R17, 0x8, R14 ; /* 0x00000008110e7825 */
/* 0x004fc800078e020e */
/*0290*/ IMAD.WIDE R18, R17.reuse, 0x8, R18 ; /* 0x0000000811127825 */
/* 0x048fe400078e0212 */
/*02a0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*02b0*/ IMAD.WIDE R8, R17.reuse, 0x8, R8 ; /* 0x0000000811087825 */
/* 0x050fe400078e0208 */
/*02c0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1b00 */
/*02d0*/ IMAD.WIDE R4, R17, 0x8, R4 ; /* 0x0000000811047825 */
/* 0x000fe400078e0204 */
/*02e0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1b00 */
/*02f0*/ IMAD.WIDE R22, R21, 0x8, R2 ; /* 0x0000000815167825 */
/* 0x000fc400078e0202 */
/*0300*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f28000c1e1b00 */
/*0310*/ LDG.E.64 R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000f22000c1e1b00 */
/*0320*/ IMAD.WIDE R6, R17, 0x8, R6 ; /* 0x0000000811067825 */
/* 0x020fc600078e0206 */
/*0330*/ LDG.E.64 R2, [R22.64+0x10] ; /* 0x0000100416027981 */
/* 0x000f68000c1e1b00 */
/*0340*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1b00 */
/*0350*/ DADD R14, R18, R14 ; /* 0x00000000120e7229 */
/* 0x004ecc000000000e */
/*0360*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x008f0c0000000008 */
/*0370*/ DADD R8, R8, R4 ; /* 0x0000000008087229 */
/* 0x0100640000000004 */
/*0380*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x001fe40000000f00 */
/*0390*/ MOV R5, c[0x0][0x184] ; /* 0x0000610000057a02 */
/* 0x000fe40000000f00 */
/*03a0*/ DADD R8, R8, R20 ; /* 0x0000000008087229 */
/* 0x002f480000000014 */
/*03b0*/ DMUL R4, R4, c[0x0][0x180] ; /* 0x0000600004047a28 */
/* 0x000fc80000000000 */
/*03c0*/ DADD R2, R8, R2 ; /* 0x0000000008027229 */
/* 0x020e0c0000000002 */
/*03d0*/ DFMA R2, R6, R4, R2 ; /* 0x000000040602722b */
/* 0x0010640000000002 */
/*03e0*/ IMAD.WIDE R4, R17, 0x8, R10 ; /* 0x0000000811047825 */
/* 0x001fc800078e020a */
/*03f0*/ DMUL R2, R2, c[0x0][0x188] ; /* 0x0000620002027a28 */
/* 0x002e0e0000000000 */
/*0400*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* jacobi.c - Poisson problem in 3d
*
*/
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu2(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
double temp;
int j_index=threadIdx.y + blockIdx.y*blockDim.y;
int k_index= threadIdx.x + blockIdx.x*blockDim.x;
int i_index=threadIdx.z + blockIdx.z*blockDim.z;
//printf("%d %d %d \n", j_index, k_index, i_index);
if ((j_index<N-2) && (k_index<N-2) && (i_index<N-2)){
temp=prev_u[i_index][j_index+1][k_index+1] + prev_u[i_index+2][j_index+1][k_index+1]+
prev_u[i_index+1][j_index][k_index+1] + prev_u[i_index+1][j_index+2][k_index+1] +
prev_u[i_index+1][j_index+1][k_index]+ prev_u[i_index+1][j_index+1][k_index+2] + step_width*step_width*f[i_index+1][j_index+1][k_index+1];
u[i_index+1][j_index+1][k_index+1]=temp*denominator;
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} | .file "tmpxft_001bd585_00000000-6_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13print_matrix2PPPdi
.type _Z13print_matrix2PPPdi, @function
_Z13print_matrix2PPPdi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13print_matrix2PPPdi, .-_Z13print_matrix2PPPdi
.globl _Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd
.type _Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd, @function
_Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11jacobi_gpu2PPPdS1_S1_idd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd, .-_Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd
.globl _Z11jacobi_gpu2PPPdS1_S1_idd
.type _Z11jacobi_gpu2PPPdS1_S1_idd, @function
_Z11jacobi_gpu2PPPdS1_S1_idd:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11jacobi_gpu2PPPdS1_S1_idd, .-_Z11jacobi_gpu2PPPdS1_S1_idd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11jacobi_gpu2PPPdS1_S1_idd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11jacobi_gpu2PPPdS1_S1_idd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* jacobi.c - Poisson problem in 3d
*
*/
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu2(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
double temp;
int j_index=threadIdx.y + blockIdx.y*blockDim.y;
int k_index= threadIdx.x + blockIdx.x*blockDim.x;
int i_index=threadIdx.z + blockIdx.z*blockDim.z;
//printf("%d %d %d \n", j_index, k_index, i_index);
if ((j_index<N-2) && (k_index<N-2) && (i_index<N-2)){
temp=prev_u[i_index][j_index+1][k_index+1] + prev_u[i_index+2][j_index+1][k_index+1]+
prev_u[i_index+1][j_index][k_index+1] + prev_u[i_index+1][j_index+2][k_index+1] +
prev_u[i_index+1][j_index+1][k_index]+ prev_u[i_index+1][j_index+1][k_index+2] + step_width*step_width*f[i_index+1][j_index+1][k_index+1];
u[i_index+1][j_index+1][k_index+1]=temp*denominator;
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} | /* jacobi.c - Poisson problem in 3d
*
*/
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu2(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
double temp;
int j_index=threadIdx.y + blockIdx.y*blockDim.y;
int k_index= threadIdx.x + blockIdx.x*blockDim.x;
int i_index=threadIdx.z + blockIdx.z*blockDim.z;
//printf("%d %d %d \n", j_index, k_index, i_index);
if ((j_index<N-2) && (k_index<N-2) && (i_index<N-2)){
temp=prev_u[i_index][j_index+1][k_index+1] + prev_u[i_index+2][j_index+1][k_index+1]+
prev_u[i_index+1][j_index][k_index+1] + prev_u[i_index+1][j_index+2][k_index+1] +
prev_u[i_index+1][j_index+1][k_index]+ prev_u[i_index+1][j_index+1][k_index+2] + step_width*step_width*f[i_index+1][j_index+1][k_index+1];
u[i_index+1][j_index+1][k_index+1]=temp*denominator;
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* jacobi.c - Poisson problem in 3d
*
*/
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu2(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
double temp;
int j_index=threadIdx.y + blockIdx.y*blockDim.y;
int k_index= threadIdx.x + blockIdx.x*blockDim.x;
int i_index=threadIdx.z + blockIdx.z*blockDim.z;
//printf("%d %d %d \n", j_index, k_index, i_index);
if ((j_index<N-2) && (k_index<N-2) && (i_index<N-2)){
temp=prev_u[i_index][j_index+1][k_index+1] + prev_u[i_index+2][j_index+1][k_index+1]+
prev_u[i_index+1][j_index][k_index+1] + prev_u[i_index+1][j_index+2][k_index+1] +
prev_u[i_index+1][j_index+1][k_index]+ prev_u[i_index+1][j_index+1][k_index+2] + step_width*step_width*f[i_index+1][j_index+1][k_index+1];
u[i_index+1][j_index+1][k_index+1]=temp*denominator;
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11jacobi_gpu2PPPdS1_S1_idd
.globl _Z11jacobi_gpu2PPPdS1_S1_idd
.p2align 8
.type _Z11jacobi_gpu2PPPdS1_S1_idd,@function
_Z11jacobi_gpu2PPPdS1_S1_idd:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v5, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[0:1], null, s13, s2, v[4:5]
v_mad_u64_u32 v[3:4], null, s15, s3, v[5:6]
s_add_i32 s4, s4, -2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max3_i32 v1, v2, v0, v3
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v15, vcc_lo, v3, 8
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
s_clause 0x1
global_load_b64 v[7:8], v[5:6], off
global_load_b64 v[5:6], v[5:6], off offset:16
v_add_co_u32 v3, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v16, vcc_lo
global_load_b64 v[9:10], v[3:4], off
v_add_co_u32 v3, vcc_lo, s2, v15
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v16, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x20
global_load_b64 v[11:12], v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[2:3]
v_add_co_u32 v17, vcc_lo, v1, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(3)
v_add_co_u32 v3, vcc_lo, v7, v17
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, v8, v18, vcc_lo
s_waitcnt vmcnt(2)
v_add_co_u32 v5, vcc_lo, v5, v17
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v18, vcc_lo
flat_load_b64 v[3:4], v[3:4]
flat_load_b64 v[5:6], v[5:6]
s_waitcnt vmcnt(3)
v_add_co_u32 v1, vcc_lo, v9, v1
v_add_co_ci_u32_e32 v2, vcc_lo, v10, v2, vcc_lo
s_clause 0x1
flat_load_b64 v[7:8], v[1:2]
flat_load_b64 v[13:14], v[1:2] offset:16
v_add_co_u32 v1, vcc_lo, v9, v17
v_add_co_ci_u32_e32 v2, vcc_lo, v10, v18, vcc_lo
flat_load_b64 v[9:10], v[1:2]
s_waitcnt vmcnt(5)
v_add_co_u32 v1, vcc_lo, v11, v17
v_add_co_ci_u32_e32 v2, vcc_lo, v12, v18, vcc_lo
flat_load_b64 v[11:12], v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v16, vcc_lo
global_load_b64 v[15:16], v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v19, vcc_lo, v0, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(6) lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, v3, v19
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, v4, v20, vcc_lo
s_waitcnt vmcnt(5)
v_add_co_u32 v4, vcc_lo, v5, v19
v_add_co_ci_u32_e32 v5, vcc_lo, v6, v20, vcc_lo
flat_load_b64 v[2:3], v[2:3]
flat_load_b64 v[4:5], v[4:5]
s_waitcnt vmcnt(6)
v_add_co_u32 v6, vcc_lo, v7, v19
v_add_co_ci_u32_e32 v7, vcc_lo, v8, v20, vcc_lo
s_waitcnt vmcnt(5)
v_add_co_u32 v13, vcc_lo, v13, v19
v_add_co_ci_u32_e32 v14, vcc_lo, v14, v20, vcc_lo
flat_load_b64 v[6:7], v[6:7]
s_waitcnt vmcnt(5)
v_add_co_u32 v0, vcc_lo, v9, v0
flat_load_b64 v[13:14], v[13:14]
v_add_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
s_clause 0x1
flat_load_b64 v[8:9], v[0:1]
flat_load_b64 v[0:1], v[0:1] offset:16
s_waitcnt vmcnt(7)
v_add_co_u32 v10, vcc_lo, v11, v19
v_add_co_ci_u32_e32 v11, vcc_lo, v12, v20, vcc_lo
s_waitcnt vmcnt(6)
v_add_co_u32 v15, vcc_lo, v15, v17
v_add_co_ci_u32_e32 v16, vcc_lo, v16, v18, vcc_lo
flat_load_b64 v[10:11], v[10:11]
flat_load_b64 v[15:16], v[15:16]
s_waitcnt vmcnt(6) lgkmcnt(6)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_waitcnt vmcnt(5) lgkmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
s_waitcnt vmcnt(4) lgkmcnt(4)
v_add_f64 v[2:3], v[2:3], v[13:14]
s_waitcnt vmcnt(3) lgkmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_waitcnt vmcnt(2) lgkmcnt(2)
v_add_f64 v[0:1], v[2:3], v[0:1]
v_mul_f64 v[2:3], s[0:1], s[0:1]
s_waitcnt vmcnt(1) lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fma_f64 v[0:1], v[2:3], v[10:11], v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, v15, v19
v_add_co_ci_u32_e32 v3, vcc_lo, v16, v20, vcc_lo
v_mul_f64 v[0:1], v[0:1], s[2:3]
flat_store_b64 v[2:3], v[0:1]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11jacobi_gpu2PPPdS1_S1_idd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11jacobi_gpu2PPPdS1_S1_idd, .Lfunc_end0-_Z11jacobi_gpu2PPPdS1_S1_idd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11jacobi_gpu2PPPdS1_S1_idd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11jacobi_gpu2PPPdS1_S1_idd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* jacobi.c - Poisson problem in 3d
*
*/
#include <hip/hip_runtime.h>
#include <math.h>
#include <stdio.h>
__device__ void print_matrix2(double*** A, int N){
int i,j,k;
for (i=0; i<N; i++){
printf("\n %d -th Layer \n", i);
for(j=0; j<N; j++){
for(k=0; k<N; k++){
printf("%lf \t", A[i][j][k]);
}
printf("\n");
}
}
}
__global__ void jacobi_gpu2(double*** u, double***prev_u, double*** f, int N, double step_width, double denominator) {
double temp;
int j_index=threadIdx.y + blockIdx.y*blockDim.y;
int k_index= threadIdx.x + blockIdx.x*blockDim.x;
int i_index=threadIdx.z + blockIdx.z*blockDim.z;
//printf("%d %d %d \n", j_index, k_index, i_index);
if ((j_index<N-2) && (k_index<N-2) && (i_index<N-2)){
temp=prev_u[i_index][j_index+1][k_index+1] + prev_u[i_index+2][j_index+1][k_index+1]+
prev_u[i_index+1][j_index][k_index+1] + prev_u[i_index+1][j_index+2][k_index+1] +
prev_u[i_index+1][j_index+1][k_index]+ prev_u[i_index+1][j_index+1][k_index+2] + step_width*step_width*f[i_index+1][j_index+1][k_index+1];
u[i_index+1][j_index+1][k_index+1]=temp*denominator;
}
//printf("On the GPU we now have matrix:\n");
//print_matrix2(u,N);
} | .text
.file "jacobi.hip"
.globl _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd # -- Begin function _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd
.p2align 4, 0x90
.type _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd,@function
_Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd: # @_Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11jacobi_gpu2PPPdS1_S1_idd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd, .Lfunc_end0-_Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11jacobi_gpu2PPPdS1_S1_idd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11jacobi_gpu2PPPdS1_S1_idd,@object # @_Z11jacobi_gpu2PPPdS1_S1_idd
.section .rodata,"a",@progbits
.globl _Z11jacobi_gpu2PPPdS1_S1_idd
.p2align 3, 0x0
_Z11jacobi_gpu2PPPdS1_S1_idd:
.quad _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd
.size _Z11jacobi_gpu2PPPdS1_S1_idd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11jacobi_gpu2PPPdS1_S1_idd"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11jacobi_gpu2PPPdS1_S1_idd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11jacobi_gpu2PPPdS1_S1_idd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R21, SR_CTAID.X ; /* 0x0000000000157919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIADD3 UR4, UR4, -0x2, URZ ; /* 0xfffffffe04047890 */
/* 0x000fe2000fffe03f */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0050*/ S2R R23, SR_CTAID.Y ; /* 0x0000000000177919 */
/* 0x000e680000002600 */
/*0060*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002200 */
/*0070*/ S2R R11, SR_CTAID.Z ; /* 0x00000000000b7919 */
/* 0x000ea80000002700 */
/*0080*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000ea20000002300 */
/*0090*/ IMAD R21, R21, c[0x0][0x0], R2 ; /* 0x0000000015157a24 */
/* 0x001fca00078e0202 */
/*00a0*/ ISETP.GE.AND P0, PT, R21, UR4, PT ; /* 0x0000000415007c0c */
/* 0x000fe2000bf06270 */
/*00b0*/ IMAD R23, R23, c[0x0][0x4], R0 ; /* 0x0000010017177a24 */
/* 0x002fca00078e0200 */
/*00c0*/ ISETP.GE.OR P0, PT, R23, UR4, P0 ; /* 0x0000000417007c0c */
/* 0x000fe20008706670 */
/*00d0*/ IMAD R11, R11, c[0x0][0x8], R4 ; /* 0x000002000b0b7a24 */
/* 0x004fca00078e0204 */
/*00e0*/ ISETP.GE.OR P0, PT, R11, UR4, P0 ; /* 0x000000040b007c0c */
/* 0x000fda0008706670 */
/*00f0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0100*/ HFMA2.MMA R0, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff007435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0120*/ IMAD.WIDE R2, R11, R0, c[0x0][0x168] ; /* 0x00005a000b027625 */
/* 0x000fca00078e0200 */
/*0130*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea8000c1e1b00 */
/*0140*/ LDG.E.64 R8, [R2.64+0x10] ; /* 0x0000100402087981 */
/* 0x000ee8000c1e1b00 */
/*0150*/ LDG.E.64 R16, [R2.64+0x8] ; /* 0x0000080402107981 */
/* 0x000f22000c1e1b00 */
/*0160*/ IMAD.WIDE R6, R11, R0, c[0x0][0x170] ; /* 0x00005c000b067625 */
/* 0x000fcc00078e0200 */
/*0170*/ LDG.E.64 R6, [R6.64+0x8] ; /* 0x0000080406067981 */
/* 0x000f62000c1e1b00 */
/*0180*/ IADD3 R13, R23, 0x1, RZ ; /* 0x00000001170d7810 */
/* 0x000fe20007ffe0ff */
/*0190*/ IMAD.WIDE R10, R11, R0, c[0x0][0x160] ; /* 0x000058000b0a7625 */
/* 0x000fcc00078e0200 */
/*01a0*/ LDG.E.64 R10, [R10.64+0x8] ; /* 0x000008040a0a7981 */
/* 0x000f62000c1e1b00 */
/*01b0*/ IMAD.WIDE R14, R13, 0x8, R4 ; /* 0x000000080d0e7825 */
/* 0x004fc800078e0204 */
/*01c0*/ IMAD.WIDE R18, R13, 0x8, R8 ; /* 0x000000080d127825 */
/* 0x008fe400078e0208 */
/*01d0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*01e0*/ IMAD.WIDE R22, R23, 0x8, R16 ; /* 0x0000000817167825 */
/* 0x010fe400078e0210 */
/*01f0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee8000c1e1b00 */
/*0200*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x000f28000c1e1b00 */
/*0210*/ LDG.E.64 R4, [R22.64+0x10] ; /* 0x0000100416047981 */
/* 0x000f28000c1e1b00 */
/*0220*/ LDG.E.64 R2, [R22.64+0x8] ; /* 0x0000080416027981 */
/* 0x000f22000c1e1b00 */
/*0230*/ IMAD.WIDE R24, R13, 0x8, R6 ; /* 0x000000080d187825 */
/* 0x020fca00078e0206 */
/*0240*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x000f62000c1e1b00 */
/*0250*/ IADD3 R17, R21, 0x1, RZ ; /* 0x0000000115117810 */
/* 0x000fe20007ffe0ff */
/*0260*/ IMAD.WIDE R10, R13, 0x8, R10 ; /* 0x000000080d0a7825 */
/* 0x000fcc00078e020a */
/*0270*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000f62000c1e1b00 */
/*0280*/ IMAD.WIDE R14, R17, 0x8, R14 ; /* 0x00000008110e7825 */
/* 0x004fc800078e020e */
/*0290*/ IMAD.WIDE R18, R17.reuse, 0x8, R18 ; /* 0x0000000811127825 */
/* 0x048fe400078e0212 */
/*02a0*/ LDG.E.64 R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ea4000c1e1b00 */
/*02b0*/ IMAD.WIDE R8, R17.reuse, 0x8, R8 ; /* 0x0000000811087825 */
/* 0x050fe400078e0208 */
/*02c0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea4000c1e1b00 */
/*02d0*/ IMAD.WIDE R4, R17, 0x8, R4 ; /* 0x0000000811047825 */
/* 0x000fe400078e0204 */
/*02e0*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ee4000c1e1b00 */
/*02f0*/ IMAD.WIDE R22, R21, 0x8, R2 ; /* 0x0000000815167825 */
/* 0x000fc400078e0202 */
/*0300*/ LDG.E.64 R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000f28000c1e1b00 */
/*0310*/ LDG.E.64 R20, [R22.64] ; /* 0x0000000416147981 */
/* 0x000f22000c1e1b00 */
/*0320*/ IMAD.WIDE R6, R17, 0x8, R6 ; /* 0x0000000811067825 */
/* 0x020fc600078e0206 */
/*0330*/ LDG.E.64 R2, [R22.64+0x10] ; /* 0x0000100416027981 */
/* 0x000f68000c1e1b00 */
/*0340*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000f62000c1e1b00 */
/*0350*/ DADD R14, R18, R14 ; /* 0x00000000120e7229 */
/* 0x004ecc000000000e */
/*0360*/ DADD R8, R14, R8 ; /* 0x000000000e087229 */
/* 0x008f0c0000000008 */
/*0370*/ DADD R8, R8, R4 ; /* 0x0000000008087229 */
/* 0x0100640000000004 */
/*0380*/ MOV R4, c[0x0][0x180] ; /* 0x0000600000047a02 */
/* 0x001fe40000000f00 */
/*0390*/ MOV R5, c[0x0][0x184] ; /* 0x0000610000057a02 */
/* 0x000fe40000000f00 */
/*03a0*/ DADD R8, R8, R20 ; /* 0x0000000008087229 */
/* 0x002f480000000014 */
/*03b0*/ DMUL R4, R4, c[0x0][0x180] ; /* 0x0000600004047a28 */
/* 0x000fc80000000000 */
/*03c0*/ DADD R2, R8, R2 ; /* 0x0000000008027229 */
/* 0x020e0c0000000002 */
/*03d0*/ DFMA R2, R6, R4, R2 ; /* 0x000000040602722b */
/* 0x0010640000000002 */
/*03e0*/ IMAD.WIDE R4, R17, 0x8, R10 ; /* 0x0000000811047825 */
/* 0x001fc800078e020a */
/*03f0*/ DMUL R2, R2, c[0x0][0x188] ; /* 0x0000620002027a28 */
/* 0x002e0e0000000000 */
/*0400*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x001fe2000c101b04 */
/*0410*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0420*/ BRA 0x420; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11jacobi_gpu2PPPdS1_S1_idd
.globl _Z11jacobi_gpu2PPPdS1_S1_idd
.p2align 8
.type _Z11jacobi_gpu2PPPdS1_S1_idd,@function
_Z11jacobi_gpu2PPPdS1_S1_idd:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x3c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v5, v0, 20, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s2, 16
s_and_b32 s2, s2, 0xffff
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s14, s5, v[1:2]
v_mad_u64_u32 v[0:1], null, s13, s2, v[4:5]
v_mad_u64_u32 v[3:4], null, s15, s3, v[5:6]
s_add_i32 s4, s4, -2
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max3_i32 v1, v2, v0, v3
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v15, vcc_lo, v3, 8
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
s_clause 0x1
global_load_b64 v[7:8], v[5:6], off
global_load_b64 v[5:6], v[5:6], off offset:16
v_add_co_u32 v3, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v16, vcc_lo
global_load_b64 v[9:10], v[3:4], off
v_add_co_u32 v3, vcc_lo, s2, v15
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v16, vcc_lo
s_load_b128 s[0:3], s[0:1], 0x20
global_load_b64 v[11:12], v[3:4], off
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 3, v[2:3]
v_add_co_u32 v17, vcc_lo, v1, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, 0, v2, vcc_lo
s_waitcnt vmcnt(3)
v_add_co_u32 v3, vcc_lo, v7, v17
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, v8, v18, vcc_lo
s_waitcnt vmcnt(2)
v_add_co_u32 v5, vcc_lo, v5, v17
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v18, vcc_lo
flat_load_b64 v[3:4], v[3:4]
flat_load_b64 v[5:6], v[5:6]
s_waitcnt vmcnt(3)
v_add_co_u32 v1, vcc_lo, v9, v1
v_add_co_ci_u32_e32 v2, vcc_lo, v10, v2, vcc_lo
s_clause 0x1
flat_load_b64 v[7:8], v[1:2]
flat_load_b64 v[13:14], v[1:2] offset:16
v_add_co_u32 v1, vcc_lo, v9, v17
v_add_co_ci_u32_e32 v2, vcc_lo, v10, v18, vcc_lo
flat_load_b64 v[9:10], v[1:2]
s_waitcnt vmcnt(5)
v_add_co_u32 v1, vcc_lo, v11, v17
v_add_co_ci_u32_e32 v2, vcc_lo, v12, v18, vcc_lo
flat_load_b64 v[11:12], v[1:2]
v_add_co_u32 v1, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v16, vcc_lo
global_load_b64 v[15:16], v[1:2], off
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
v_add_co_u32 v19, vcc_lo, v0, 8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v20, vcc_lo, 0, v1, vcc_lo
s_waitcnt vmcnt(6) lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, v3, v19
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, v4, v20, vcc_lo
s_waitcnt vmcnt(5)
v_add_co_u32 v4, vcc_lo, v5, v19
v_add_co_ci_u32_e32 v5, vcc_lo, v6, v20, vcc_lo
flat_load_b64 v[2:3], v[2:3]
flat_load_b64 v[4:5], v[4:5]
s_waitcnt vmcnt(6)
v_add_co_u32 v6, vcc_lo, v7, v19
v_add_co_ci_u32_e32 v7, vcc_lo, v8, v20, vcc_lo
s_waitcnt vmcnt(5)
v_add_co_u32 v13, vcc_lo, v13, v19
v_add_co_ci_u32_e32 v14, vcc_lo, v14, v20, vcc_lo
flat_load_b64 v[6:7], v[6:7]
s_waitcnt vmcnt(5)
v_add_co_u32 v0, vcc_lo, v9, v0
flat_load_b64 v[13:14], v[13:14]
v_add_co_ci_u32_e32 v1, vcc_lo, v10, v1, vcc_lo
s_clause 0x1
flat_load_b64 v[8:9], v[0:1]
flat_load_b64 v[0:1], v[0:1] offset:16
s_waitcnt vmcnt(7)
v_add_co_u32 v10, vcc_lo, v11, v19
v_add_co_ci_u32_e32 v11, vcc_lo, v12, v20, vcc_lo
s_waitcnt vmcnt(6)
v_add_co_u32 v15, vcc_lo, v15, v17
v_add_co_ci_u32_e32 v16, vcc_lo, v16, v18, vcc_lo
flat_load_b64 v[10:11], v[10:11]
flat_load_b64 v[15:16], v[15:16]
s_waitcnt vmcnt(6) lgkmcnt(6)
v_add_f64 v[2:3], v[2:3], v[4:5]
s_waitcnt vmcnt(5) lgkmcnt(5)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[6:7]
s_waitcnt vmcnt(4) lgkmcnt(4)
v_add_f64 v[2:3], v[2:3], v[13:14]
s_waitcnt vmcnt(3) lgkmcnt(3)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f64 v[2:3], v[2:3], v[8:9]
s_waitcnt vmcnt(2) lgkmcnt(2)
v_add_f64 v[0:1], v[2:3], v[0:1]
v_mul_f64 v[2:3], s[0:1], s[0:1]
s_waitcnt vmcnt(1) lgkmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_fma_f64 v[0:1], v[2:3], v[10:11], v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, v15, v19
v_add_co_ci_u32_e32 v3, vcc_lo, v16, v20, vcc_lo
v_mul_f64 v[0:1], v[0:1], s[2:3]
flat_store_b64 v[2:3], v[0:1]
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11jacobi_gpu2PPPdS1_S1_idd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11jacobi_gpu2PPPdS1_S1_idd, .Lfunc_end0-_Z11jacobi_gpu2PPPdS1_S1_idd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11jacobi_gpu2PPPdS1_S1_idd
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11jacobi_gpu2PPPdS1_S1_idd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001bd585_00000000-6_jacobi.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13print_matrix2PPPdi
.type _Z13print_matrix2PPPdi, @function
_Z13print_matrix2PPPdi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z13print_matrix2PPPdi, .-_Z13print_matrix2PPPdi
.globl _Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd
.type _Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd, @function
_Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movsd %xmm0, 8(%rsp)
movsd %xmm1, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11jacobi_gpu2PPPdS1_S1_idd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd, .-_Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd
.globl _Z11jacobi_gpu2PPPdS1_S1_idd
.type _Z11jacobi_gpu2PPPdS1_S1_idd, @function
_Z11jacobi_gpu2PPPdS1_S1_idd:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z11jacobi_gpu2PPPdS1_S1_iddPPPdS1_S1_idd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11jacobi_gpu2PPPdS1_S1_idd, .-_Z11jacobi_gpu2PPPdS1_S1_idd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11jacobi_gpu2PPPdS1_S1_idd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11jacobi_gpu2PPPdS1_S1_idd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "jacobi.hip"
.globl _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd # -- Begin function _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd
.p2align 4, 0x90
.type _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd,@function
_Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd: # @_Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 4(%rsp)
movsd %xmm0, 64(%rsp)
movsd %xmm1, 56(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11jacobi_gpu2PPPdS1_S1_idd, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd, .Lfunc_end0-_Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11jacobi_gpu2PPPdS1_S1_idd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11jacobi_gpu2PPPdS1_S1_idd,@object # @_Z11jacobi_gpu2PPPdS1_S1_idd
.section .rodata,"a",@progbits
.globl _Z11jacobi_gpu2PPPdS1_S1_idd
.p2align 3, 0x0
_Z11jacobi_gpu2PPPdS1_S1_idd:
.quad _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd
.size _Z11jacobi_gpu2PPPdS1_S1_idd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11jacobi_gpu2PPPdS1_S1_idd"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__jacobi_gpu2PPPdS1_S1_idd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11jacobi_gpu2PPPdS1_S1_idd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void initialize_clause_output_predict(int *clause_output, int *all_exclude)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// Initialize clause output
for (int j = index; j < CLAUSES; j += stride) {
clause_output[j] = 1;
all_exclude[j] = 1;
}
} | code for sm_80
Function : _Z32initialize_clause_output_predictPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x270f, PT ; /* 0x0000270f0300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x2e0 ; /* 0x0000025000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a00 */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fcc0003f45070 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0100*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0110*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fd200078e02ff */
/*0120*/ IMAD.HI.U32 R6, R5, R7, R4 ; /* 0x0000000705067227 */
/* 0x000fe200078e0004 */
/*0130*/ IADD3 R5, -R3, 0x270f, RZ ; /* 0x0000270f03057810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.MOV R2, RZ, RZ, -R6 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a06 */
/*0160*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0180*/ @P0 IADD3 R5, -R0, R5, RZ ; /* 0x0000000500050210 */
/* 0x000fe40007ffe1ff */
/*0190*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*01d0*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*01f0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0200*/ @!P0 BRA 0x2d0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0220*/ MOV R9, 0x1 ; /* 0x0000000100097802 */
/* 0x000fc60000000f00 */
/*0230*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0240*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0206 */
/*0250*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0260*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c101904 */
/*0270*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fe400078e0203 */
/*0280*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0290*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0003e2000c101904 */
/*02a0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02b0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x002fce00078e0204 */
/*02c0*/ @P0 BRA 0x250 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*02f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0300*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fd200078e00ff */
/*0310*/ IMAD.WIDE R4, R3, R2, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x001fc800078e0202 */
/*0320*/ IMAD.WIDE R6, R3, R2, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fe200078e0202 */
/*0330*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0001e2000c101904 */
/*0340*/ IADD3 R3, R0.reuse, R3, R0 ; /* 0x0000000300037210 */
/* 0x040fe40007ffe000 */
/*0350*/ IMAD.WIDE R8, R0.reuse, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x040fe200078e0204 */
/*0360*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x0001e2000c101904 */
/*0370*/ IADD3 R3, R0.reuse, R3, R0 ; /* 0x0000000300037210 */
/* 0x040fe40007ffe000 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0206 */
/*0390*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x0001e2000c101904 */
/*03a0*/ ISETP.GE.AND P0, PT, R3, 0x2710, PT ; /* 0x000027100300780c */
/* 0x000fc40003f06270 */
/*03b0*/ IMAD.WIDE R12, R0.reuse, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x040fe200078e0208 */
/*03c0*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0001e6000c101904 */
/*03d0*/ IMAD.WIDE R14, R0.reuse, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020a */
/*03e0*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0001e6000c101904 */
/*03f0*/ IMAD.WIDE R16, R0.reuse, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x040fe200078e020c */
/*0400*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0001e6000c101904 */
/*0410*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fe200078e020e */
/*0420*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0001e8000c101904 */
/*0430*/ STG.E [R18.64], R21 ; /* 0x0000001512007986 */
/* 0x0001e2000c101904 */
/*0440*/ @!P0 BRA 0x310 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void initialize_clause_output_predict(int *clause_output, int *all_exclude)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// Initialize clause output
for (int j = index; j < CLAUSES; j += stride) {
clause_output[j] = 1;
all_exclude[j] = 1;
}
} | .file "tmpxft_00036962_00000000-6_initialize_clause_output_predict.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_
.type _Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_, @function
_Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z32initialize_clause_output_predictPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_, .-_Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_
.globl _Z32initialize_clause_output_predictPiS_
.type _Z32initialize_clause_output_predictPiS_, @function
_Z32initialize_clause_output_predictPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32initialize_clause_output_predictPiS_, .-_Z32initialize_clause_output_predictPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32initialize_clause_output_predictPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32initialize_clause_output_predictPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void initialize_clause_output_predict(int *clause_output, int *all_exclude)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// Initialize clause output
for (int j = index; j < CLAUSES; j += stride) {
clause_output[j] = 1;
all_exclude[j] = 1;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initialize_clause_output_predict(int *clause_output, int *all_exclude)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// Initialize clause output
for (int j = index; j < CLAUSES; j += stride) {
clause_output[j] = 1;
all_exclude[j] = 1;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initialize_clause_output_predict(int *clause_output, int *all_exclude)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// Initialize clause output
for (int j = index; j < CLAUSES; j += stride) {
clause_output[j] = 1;
all_exclude[j] = 1;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32initialize_clause_output_predictPiS_
.globl _Z32initialize_clause_output_predictPiS_
.p2align 8
.type _Z32initialize_clause_output_predictPiS_,@function
_Z32initialize_clause_output_predictPiS_:
s_load_b32 s4, s[0:1], 0x1c
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x2710, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x270f, v1
v_add_co_u32 v2, s0, v2, s8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
global_store_b32 v[4:5], v0, off
global_store_b32 v[6:7], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32initialize_clause_output_predictPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32initialize_clause_output_predictPiS_, .Lfunc_end0-_Z32initialize_clause_output_predictPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32initialize_clause_output_predictPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32initialize_clause_output_predictPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void initialize_clause_output_predict(int *clause_output, int *all_exclude)
{
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
// Initialize clause output
for (int j = index; j < CLAUSES; j += stride) {
clause_output[j] = 1;
all_exclude[j] = 1;
}
} | .text
.file "initialize_clause_output_predict.hip"
.globl _Z47__device_stub__initialize_clause_output_predictPiS_ # -- Begin function _Z47__device_stub__initialize_clause_output_predictPiS_
.p2align 4, 0x90
.type _Z47__device_stub__initialize_clause_output_predictPiS_,@function
_Z47__device_stub__initialize_clause_output_predictPiS_: # @_Z47__device_stub__initialize_clause_output_predictPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z32initialize_clause_output_predictPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z47__device_stub__initialize_clause_output_predictPiS_, .Lfunc_end0-_Z47__device_stub__initialize_clause_output_predictPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32initialize_clause_output_predictPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32initialize_clause_output_predictPiS_,@object # @_Z32initialize_clause_output_predictPiS_
.section .rodata,"a",@progbits
.globl _Z32initialize_clause_output_predictPiS_
.p2align 3, 0x0
_Z32initialize_clause_output_predictPiS_:
.quad _Z47__device_stub__initialize_clause_output_predictPiS_
.size _Z32initialize_clause_output_predictPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32initialize_clause_output_predictPiS_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__initialize_clause_output_predictPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32initialize_clause_output_predictPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z32initialize_clause_output_predictPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R3, R3, c[0x0][0x0], R0 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GT.AND P0, PT, R3, 0x270f, PT ; /* 0x0000270f0300780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ MOV R0, c[0x0][0x0] ; /* 0x0000000000007a02 */
/* 0x000fe20000000f00 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x2e0 ; /* 0x0000025000007945 */
/* 0x000fe60003800000 */
/*0090*/ IMAD R0, R0, c[0x0][0xc], RZ ; /* 0x0000030000007a24 */
/* 0x000fc800078e02ff */
/*00a0*/ I2F.U32.RP R2, R0 ; /* 0x0000000000027306 */
/* 0x000e220000209000 */
/*00b0*/ IMAD.MOV R7, RZ, RZ, -R0 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a00 */
/*00c0*/ ISETP.NE.U32.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fcc0003f45070 */
/*00d0*/ MUFU.RCP R2, R2 ; /* 0x0000000200027308 */
/* 0x001e240000001000 */
/*00e0*/ IADD3 R4, R2, 0xffffffe, RZ ; /* 0x0ffffffe02047810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*0100*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*0110*/ IMAD R7, R7, R5, RZ ; /* 0x0000000507077224 */
/* 0x002fd200078e02ff */
/*0120*/ IMAD.HI.U32 R6, R5, R7, R4 ; /* 0x0000000705067227 */
/* 0x000fe200078e0004 */
/*0130*/ IADD3 R5, -R3, 0x270f, RZ ; /* 0x0000270f03057810 */
/* 0x000fca0007ffe1ff */
/*0140*/ IMAD.HI.U32 R6, R6, R5, RZ ; /* 0x0000000506067227 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.MOV R2, RZ, RZ, -R6 ; /* 0x000000ffff027224 */
/* 0x000fc800078e0a06 */
/*0160*/ IMAD R5, R0, R2, R5 ; /* 0x0000000200057224 */
/* 0x000fca00078e0205 */
/*0170*/ ISETP.GE.U32.AND P0, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f06070 */
/*0180*/ @P0 IADD3 R5, -R0, R5, RZ ; /* 0x0000000500050210 */
/* 0x000fe40007ffe1ff */
/*0190*/ @P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106060810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f26070 */
/*01b0*/ @P1 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106061810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ @!P2 LOP3.LUT R6, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff06a212 */
/* 0x000fc800078e33ff */
/*01d0*/ IADD3 R2, R6.reuse, 0x1, RZ ; /* 0x0000000106027810 */
/* 0x040fe40007ffe0ff */
/*01e0*/ ISETP.GE.U32.AND P1, PT, R6, 0x3, PT ; /* 0x000000030600780c */
/* 0x000fe40003f26070 */
/*01f0*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fda000780c0ff */
/*0200*/ @!P0 BRA 0x2d0 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0210*/ IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff067424 */
/* 0x000fe200078e00ff */
/*0220*/ MOV R9, 0x1 ; /* 0x0000000100097802 */
/* 0x000fc60000000f00 */
/*0230*/ IMAD.WIDE R4, R3, R6, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fc800078e0206 */
/*0240*/ IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fc800078e0206 */
/*0250*/ IADD3 R2, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe20007ffe0ff */
/*0260*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001e2000c101904 */
/*0270*/ IMAD.IADD R3, R0, 0x1, R3 ; /* 0x0000000100037824 */
/* 0x000fe400078e0203 */
/*0280*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe20003f05270 */
/*0290*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x0003e2000c101904 */
/*02a0*/ IMAD.WIDE R6, R0, 0x4, R6 ; /* 0x0000000400067825 */
/* 0x001fc800078e0206 */
/*02b0*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x002fce00078e0204 */
/*02c0*/ @P0 BRA 0x250 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*02f0*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0300*/ IMAD.MOV.U32 R21, RZ, RZ, 0x1 ; /* 0x00000001ff157424 */
/* 0x000fd200078e00ff */
/*0310*/ IMAD.WIDE R4, R3, R2, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x001fc800078e0202 */
/*0320*/ IMAD.WIDE R6, R3, R2, c[0x0][0x168] ; /* 0x00005a0003067625 */
/* 0x000fe200078e0202 */
/*0330*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x0001e2000c101904 */
/*0340*/ IADD3 R3, R0.reuse, R3, R0 ; /* 0x0000000300037210 */
/* 0x040fe40007ffe000 */
/*0350*/ IMAD.WIDE R8, R0.reuse, 0x4, R4 ; /* 0x0000000400087825 */
/* 0x040fe200078e0204 */
/*0360*/ STG.E [R6.64], R21 ; /* 0x0000001506007986 */
/* 0x0001e2000c101904 */
/*0370*/ IADD3 R3, R0.reuse, R3, R0 ; /* 0x0000000300037210 */
/* 0x040fe40007ffe000 */
/*0380*/ IMAD.WIDE R10, R0, 0x4, R6 ; /* 0x00000004000a7825 */
/* 0x000fe200078e0206 */
/*0390*/ STG.E [R8.64], R21 ; /* 0x0000001508007986 */
/* 0x0001e2000c101904 */
/*03a0*/ ISETP.GE.AND P0, PT, R3, 0x2710, PT ; /* 0x000027100300780c */
/* 0x000fc40003f06270 */
/*03b0*/ IMAD.WIDE R12, R0.reuse, 0x4, R8 ; /* 0x00000004000c7825 */
/* 0x040fe200078e0208 */
/*03c0*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0001e6000c101904 */
/*03d0*/ IMAD.WIDE R14, R0.reuse, 0x4, R10 ; /* 0x00000004000e7825 */
/* 0x040fe200078e020a */
/*03e0*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0001e6000c101904 */
/*03f0*/ IMAD.WIDE R16, R0.reuse, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x040fe200078e020c */
/*0400*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0001e6000c101904 */
/*0410*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x000fe200078e020e */
/*0420*/ STG.E [R16.64], R21 ; /* 0x0000001510007986 */
/* 0x0001e8000c101904 */
/*0430*/ STG.E [R18.64], R21 ; /* 0x0000001512007986 */
/* 0x0001e2000c101904 */
/*0440*/ @!P0 BRA 0x310 ; /* 0xfffffec000008947 */
/* 0x000fea000383ffff */
/*0450*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0460*/ BRA 0x460; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z32initialize_clause_output_predictPiS_
.globl _Z32initialize_clause_output_predictPiS_
.p2align 8
.type _Z32initialize_clause_output_predictPiS_,@function
_Z32initialize_clause_output_predictPiS_:
s_load_b32 s4, s[0:1], 0x1c
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x2710, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s8
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[8:9], s[2:3], 2
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_nc_u32_e32 v1, s2, v1
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x270f, v1
v_add_co_u32 v2, s0, v2, s8
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
s_or_b32 s1, vcc_lo, s1
global_store_b32 v[4:5], v0, off
global_store_b32 v[6:7], v0, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32initialize_clause_output_predictPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z32initialize_clause_output_predictPiS_, .Lfunc_end0-_Z32initialize_clause_output_predictPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32initialize_clause_output_predictPiS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32initialize_clause_output_predictPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00036962_00000000-6_initialize_clause_output_predict.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_
.type _Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_, @function
_Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z32initialize_clause_output_predictPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_, .-_Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_
.globl _Z32initialize_clause_output_predictPiS_
.type _Z32initialize_clause_output_predictPiS_, @function
_Z32initialize_clause_output_predictPiS_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z32initialize_clause_output_predictPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z32initialize_clause_output_predictPiS_, .-_Z32initialize_clause_output_predictPiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32initialize_clause_output_predictPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32initialize_clause_output_predictPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "initialize_clause_output_predict.hip"
.globl _Z47__device_stub__initialize_clause_output_predictPiS_ # -- Begin function _Z47__device_stub__initialize_clause_output_predictPiS_
.p2align 4, 0x90
.type _Z47__device_stub__initialize_clause_output_predictPiS_,@function
_Z47__device_stub__initialize_clause_output_predictPiS_: # @_Z47__device_stub__initialize_clause_output_predictPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z32initialize_clause_output_predictPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z47__device_stub__initialize_clause_output_predictPiS_, .Lfunc_end0-_Z47__device_stub__initialize_clause_output_predictPiS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32initialize_clause_output_predictPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z32initialize_clause_output_predictPiS_,@object # @_Z32initialize_clause_output_predictPiS_
.section .rodata,"a",@progbits
.globl _Z32initialize_clause_output_predictPiS_
.p2align 3, 0x0
_Z32initialize_clause_output_predictPiS_:
.quad _Z47__device_stub__initialize_clause_output_predictPiS_
.size _Z32initialize_clause_output_predictPiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z32initialize_clause_output_predictPiS_"
.size .L__unnamed_1, 41
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z47__device_stub__initialize_clause_output_predictPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z32initialize_clause_output_predictPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
using namespace std;
#include <cuda_runtime.h>
#include <curand_kernel.h>
#define NUM_THREADS 1024
cudaStream_t stream;
int features = 1024;
int sampels = 10000;
int classes = 10;
float ** training_x; //3500 * 784
float ** training_y; //3500 * 1
float ** testing_x; //145 * 784
float ** testing_y; //145 * 1
float ** label_onehot; //3500 * 10
void getData(float * res, char buff[])
{
char *token = strtok(buff," ,");
int counter=0;
while( token != NULL )
{
counter++;
res[counter-1] = atof(token);
token = strtok(NULL," ,");
}
}
void readCSV(char* file, float** mat, int x_dim, int y_dim)
{
FILE* stream = fopen(file, "r");
int size_per_pic = y_dim * 30;
char line[size_per_pic];
int num;
if (stream == NULL) {
perror ("Error opening file");
return;
}
int i = 0;
while (fgets(line, size_per_pic, stream))
{
char* tmp = strdup(line);
getData(mat[i], tmp);
i++;
}
}
void malloc_host(void){
training_x = (float**)malloc(sizeof(float*) * 10000);
for(int i = 0; i < 10000; i++){
training_x[i] = (float*)malloc(sizeof(float) * 1024);
}
training_y = (float**)malloc(sizeof(float*) * 10000);
for(int i = 0; i < 10000; i++){
training_y[i] = (float*)malloc(sizeof(float) * 1);
}
testing_x = (float **)malloc(sizeof(float*) * 2000);
for(int i = 0; i < 2000; i++){
testing_x[i] = (float*)malloc(sizeof(float) * 1024);
}
testing_y = (float **)malloc(sizeof(float*) * 2000);
for(int i = 0; i < 2000; i++){
testing_y[i] = (float*)malloc(sizeof(float) * 1);
}
label_onehot = (float **)malloc(sizeof(float*) * 10000);
for (int i = 0; i < 10000; i++)
{
label_onehot[i] = (float*)malloc(sizeof(float) * 10);
}
}
__global__ void Mult_GPU( float *a, float *b, float *result, const int M, const int N, const int S) // M should be batch size
{
int threadId = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (threadId < M * S)
{
int row = threadId / S;
int column = threadId % S;
result[threadId] = 0;
for (int i = 0; i < N; i++)
{
result[threadId] += a[row * N + i] * b[i * S + column];
}
}
}
__global__ void softmax_sum( float *predict, float *sum, const int label_size, const int data_size ){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
sum[tid] += exp(predict[tid * label_size + i]);
}
}
}
__global__ void max( float *predict, float *max, const int label_size, const int data_size ){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
int max_index = 0;
max[tid] = predict[tid * label_size];
if(predict[tid * label_size + max_index] < predict[tid * label_size + i]){
max[tid] = predict[tid * label_size + i];
}
}
}
}
__global__ void normalize(float *predict, float *max, const int label_size, const int data_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
predict[tid * label_size + i] -= max[tid];
}
}
}
__global__ void softmax( float *softmax_value, float *predict, float *sum,const int label_size, const int data_size ){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
softmax_value[tid * label_size + i] = exp(predict[tid * label_size + i]) / sum[tid];
}
}
}
__global__ void dz(float *softmax_value, float *label, float *dz, const int label_size, const int data_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
dz[tid * label_size + i] = softmax_value[tid * label_size + i] - label[tid * label_size + i];
}
}
}
__global__ void grad(float *train_data, float *dz, float *grad, const int label_size, const int data_size, const int weight_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < weight_size){
for(int i = 0; i < label_size; i++){
for(int j = 0; j < data_size; j++)
grad[tid * label_size + i] += train_data[j * weight_size + tid] * grad[j * label_size + i];
}
}
}
__global__ void weight_update(float *weight, float *grad, const int label_size, const int weight_size, const float learning_rate){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < weight_size){
for(int i = 0; i < label_size; i++){
grad[tid * label_size + i] /= 10000;
weight[tid * label_size + i] -= (learning_rate * grad[tid * label_size + i]);
}
}
}
__global__ void initialize_dz(float *dz, const int label_size, const int data_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
dz[tid * label_size + i] = 0;
}
}
}
__global__ void initialize_grad(float *grad, const int label_size, const int weight_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < weight_size){
for(int i = 0; i < label_size; i++){
grad[tid * label_size + i] = 0;
}
}
}
__global__ void initialize(float *sum, float *predict, const int data_size, const int label_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
sum[tid] = 0;
for(int i = 0; i < label_size; i++){
predict[tid * label_size + i] = 0;
}
}
}
int main(){
// malloc_host();
malloc_host();
readCSV("training_x.csv", training_x, 10000,1024);
readCSV("training_y.csv", training_y, 1024, 1);
readCSV("testing_x.csv", testing_x, 2000, 1024);
readCSV("testing_y.csv", testing_y, 2000, 1);
printf("label %f\n", training_y[9998][0]);
float learning_rate = 0.01;
int iter = 1;
int data_size = 10000;
int label_size = 10;
int weight_size = 1024;
int tratin_data_bytes = 10000 * 1024 * sizeof(float);
int weight_bytes = 1024 * 10 * sizeof(float);
int predict_bytes = 10000 * 10 * sizeof(float);
float *h_train_data = (float *) malloc( tratin_data_bytes ) ;
float *h_train_data_T = (float *) malloc( tratin_data_bytes ) ;
float *h_label_onehot = (float *) malloc( predict_bytes ) ;
float *h_weight = (float *) malloc( weight_bytes ) ;
float *h_predict = (float *) malloc( predict_bytes ) ;
float *h_max = (float *) malloc( 10000 * sizeof(float) ) ;
float *h_sum = (float *) malloc( 10000 * sizeof(float) ) ;
float *h_softmax = (float *) malloc( predict_bytes ) ;
float *h_dz = (float *) malloc( predict_bytes ) ;
float *h_grad = (float *) malloc( weight_bytes ) ;
////////////////////// Initialize //////////////////////
////////////////////// One Hot //////////////////////
for(int i = 0; i < data_size; i++){
for(int j = 0; j < weight_size; j++){
h_train_data_T[j * 10000 + i] = training_x[i][j];
}
}
for(int i = 0; i < data_size; i++){
label_onehot[i][(int(training_y[i][0] - 1))] = 1;
if(i == 1){
printf("training_y : %f\n", training_y[1][0]);
for(int j = 0; j < 10; j++) printf("onehot : %f\n", label_onehot[i][j]);
}
}
for(int i = 0; i < data_size; i++){
for(int j = 0; j < label_size; j++){
h_label_onehot[i * label_size + j] = label_onehot[i][j];
}
}
for(int i = 0; i < data_size; i++){
for(int j = 0; j < weight_size; j++){
h_train_data[i * weight_size + j] = training_x[i][j];
}
}
for(int i = 0; i < weight_size; i++){
for(int j = 0; j < label_size; j++){
h_weight[i * label_size + j] = 1 ;
}
}
//////////////////// Initialize //////////////////////
///////////////////////////////// GPU_SIDE ///////////////////////////////////
float *d_train_data, *d_train_data_T, *d_label, * d_weight, *d_predict, *d_predict_sum, *d_sum, *d_max, *d_softmax_value;
float *d_dz, *d_grad;
cudaGetErrorString(cudaMalloc( (void **) &d_train_data, tratin_data_bytes )) ;
cudaGetErrorString(cudaMalloc( (void **) &d_train_data_T, tratin_data_bytes )) ;
cudaGetErrorString(cudaMalloc( (void **) &d_label, predict_bytes)) ;
cudaGetErrorString(cudaMalloc( (void **) &d_predict, predict_bytes)) ;
cudaGetErrorString(cudaMalloc( (void **) &d_weight, weight_bytes)) ;
cudaGetErrorString(cudaMalloc( (void **) &d_sum, 10000 * sizeof(float))) ;
cudaGetErrorString(cudaMalloc( (void **) &d_softmax_value, predict_bytes)) ;
cudaGetErrorString(cudaMalloc( (void **) &d_dz, predict_bytes)) ;
cudaGetErrorString(cudaMalloc( (void **) &d_grad, weight_bytes)) ;
cudaGetErrorString(cudaMalloc( (void **) &d_max, 10000 * sizeof(float))) ;
// //Configure blockDim
int bdx = 32, bdy = 32;
while(data_size > bdx * 65535)
{
bdx = bdx * 2;
bdy = bdy / 2;
}
while(weight_size > bdy * 65535)
{
bdy = bdy * 2;
bdx = bdx / 2;
}
dim3 blockDim( bdx,bdy ) ; // you will want to configure this
dim3 gridDim( (int)((data_size + blockDim.x-1)/blockDim.x), (int)((weight_size + blockDim.y-1)/blockDim.y) ) ;
//////////////////////////////// invoke Kernel (Logistic Regression) ////////////////////////////////
cudaGetErrorString(cudaMemcpy( d_train_data_T, h_train_data_T, tratin_data_bytes, cudaMemcpyHostToDevice )) ;
cudaGetErrorString(cudaMemcpy( d_train_data, h_train_data, tratin_data_bytes, cudaMemcpyHostToDevice )) ;
cudaGetErrorString(cudaMemcpy( d_weight, h_weight, weight_bytes, cudaMemcpyHostToDevice )) ;
cudaGetErrorString(cudaMemcpy( d_label, h_label_onehot, predict_bytes, cudaMemcpyHostToDevice )) ;
for(int train = 0; train < 10; train++){
//Initialize
initialize<<<gridDim, blockDim>>>(d_sum, d_predict, data_size, label_size);
cudaGetErrorString(cudaDeviceSynchronize());
initialize_dz<<<gridDim, blockDim>>>(d_dz, label_size, data_size);
cudaGetErrorString(cudaDeviceSynchronize());
initialize_grad<<<gridDim, blockDim>>>(d_grad, label_size, weight_size);
cudaGetErrorString(cudaDeviceSynchronize());
// DOT
Mult_GPU<<<gridDim, blockDim>>>( d_train_data, d_weight, d_predict, data_size, weight_size, label_size) ;
cudaGetErrorString(cudaDeviceSynchronize());
max<<<gridDim, blockDim>>>( d_predict, d_max, label_size, data_size );
cudaGetErrorString(cudaDeviceSynchronize());
normalize<<<gridDim, blockDim>>>(d_predict, d_max, label_size, data_size);
cudaGetErrorString(cudaDeviceSynchronize());
// Softmax
softmax_sum<<<gridDim, blockDim>>>( d_predict, d_sum, label_size, data_size );
cudaGetErrorString(cudaDeviceSynchronize());
softmax<<<gridDim, blockDim>>>( d_softmax_value, d_predict, d_sum, label_size, data_size );
cudaGetErrorString(cudaDeviceSynchronize());
// Weight Update
dz<<<gridDim, blockDim>>>(d_softmax_value, d_label, d_dz, label_size, data_size);
cudaGetErrorString(cudaDeviceSynchronize());
Mult_GPU<<<gridDim, blockDim>>>( d_train_data_T, d_dz, d_grad, weight_size, data_size, label_size) ;
cudaGetErrorString(cudaDeviceSynchronize());
weight_update<<<gridDim, blockDim>>>(d_weight, d_grad, label_size, weight_size, learning_rate);
cudaGetErrorString(cudaDeviceSynchronize());
}
/////////////////////// Test //////////////////////////
cudaGetErrorString(cudaMemcpy( h_predict, d_predict, predict_bytes, cudaMemcpyDeviceToHost )) ;
cudaGetErrorString(cudaMemcpy( h_softmax, d_softmax_value, predict_bytes, cudaMemcpyDeviceToHost )) ;
cudaGetErrorString(cudaMemcpy( h_weight, d_weight, weight_bytes, cudaMemcpyDeviceToHost )) ;
cudaGetErrorString(cudaMemcpy( h_max, d_max, 10000 * sizeof(float), cudaMemcpyDeviceToHost )) ;
// int count = 0;
// for(int i = 0; i < data_size; i++){
// if(h_sum[i] == 10.0) count++;
// printf("max : %f\n", h_sum[i]);
// }
// printf("count 10 num = %d\n", count);
for(int i = 0; i < weight_size * label_size; i++){
printf("dz: %f\n", h_weight[i]);
}
// for(int i = 0; i < 10000; i++){
// printf("max: %f\n", log(h_max[i]) );
// }
// for(int i = 0; i < data_size * label_size; i++){
// // printf("softmax: %f\n", log(h_sum[i / label_size]) );
// printf("softmax: %f\n", h_softmax[i] );
// }
// float total_error = 0;
// for(int i = 0; i < data_size; i++){
// for(int j = 0; j < label_size; j++){
// total_error -= label_onehot[i][j] * log(h_softmax[i * label_size + j]) ;
// }
// }
// printf("error: %f\n", total_error );
} | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <math.h>
using namespace std;
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#define NUM_THREADS 1024
hipStream_t stream;
int features = 1024;
int sampels = 10000;
int classes = 10;
float ** training_x; //3500 * 784
float ** training_y; //3500 * 1
float ** testing_x; //145 * 784
float ** testing_y; //145 * 1
float ** label_onehot; //3500 * 10
void getData(float * res, char buff[])
{
char *token = strtok(buff," ,");
int counter=0;
while( token != NULL )
{
counter++;
res[counter-1] = atof(token);
token = strtok(NULL," ,");
}
}
void readCSV(char* file, float** mat, int x_dim, int y_dim)
{
FILE* stream = fopen(file, "r");
int size_per_pic = y_dim * 30;
char line[size_per_pic];
int num;
if (stream == NULL) {
perror ("Error opening file");
return;
}
int i = 0;
while (fgets(line, size_per_pic, stream))
{
char* tmp = strdup(line);
getData(mat[i], tmp);
i++;
}
}
void malloc_host(void){
training_x = (float**)malloc(sizeof(float*) * 10000);
for(int i = 0; i < 10000; i++){
training_x[i] = (float*)malloc(sizeof(float) * 1024);
}
training_y = (float**)malloc(sizeof(float*) * 10000);
for(int i = 0; i < 10000; i++){
training_y[i] = (float*)malloc(sizeof(float) * 1);
}
testing_x = (float **)malloc(sizeof(float*) * 2000);
for(int i = 0; i < 2000; i++){
testing_x[i] = (float*)malloc(sizeof(float) * 1024);
}
testing_y = (float **)malloc(sizeof(float*) * 2000);
for(int i = 0; i < 2000; i++){
testing_y[i] = (float*)malloc(sizeof(float) * 1);
}
label_onehot = (float **)malloc(sizeof(float*) * 10000);
for (int i = 0; i < 10000; i++)
{
label_onehot[i] = (float*)malloc(sizeof(float) * 10);
}
}
__global__ void Mult_GPU( float *a, float *b, float *result, const int M, const int N, const int S) // M should be batch size
{
int threadId = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (threadId < M * S)
{
int row = threadId / S;
int column = threadId % S;
result[threadId] = 0;
for (int i = 0; i < N; i++)
{
result[threadId] += a[row * N + i] * b[i * S + column];
}
}
}
__global__ void softmax_sum( float *predict, float *sum, const int label_size, const int data_size ){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
sum[tid] += exp(predict[tid * label_size + i]);
}
}
}
__global__ void max( float *predict, float *max, const int label_size, const int data_size ){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
int max_index = 0;
max[tid] = predict[tid * label_size];
if(predict[tid * label_size + max_index] < predict[tid * label_size + i]){
max[tid] = predict[tid * label_size + i];
}
}
}
}
__global__ void normalize(float *predict, float *max, const int label_size, const int data_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
predict[tid * label_size + i] -= max[tid];
}
}
}
__global__ void softmax( float *softmax_value, float *predict, float *sum,const int label_size, const int data_size ){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
softmax_value[tid * label_size + i] = exp(predict[tid * label_size + i]) / sum[tid];
}
}
}
__global__ void dz(float *softmax_value, float *label, float *dz, const int label_size, const int data_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
dz[tid * label_size + i] = softmax_value[tid * label_size + i] - label[tid * label_size + i];
}
}
}
__global__ void grad(float *train_data, float *dz, float *grad, const int label_size, const int data_size, const int weight_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < weight_size){
for(int i = 0; i < label_size; i++){
for(int j = 0; j < data_size; j++)
grad[tid * label_size + i] += train_data[j * weight_size + tid] * grad[j * label_size + i];
}
}
}
__global__ void weight_update(float *weight, float *grad, const int label_size, const int weight_size, const float learning_rate){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < weight_size){
for(int i = 0; i < label_size; i++){
grad[tid * label_size + i] /= 10000;
weight[tid * label_size + i] -= (learning_rate * grad[tid * label_size + i]);
}
}
}
__global__ void initialize_dz(float *dz, const int label_size, const int data_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
for(int i = 0; i < label_size; i++){
dz[tid * label_size + i] = 0;
}
}
}
__global__ void initialize_grad(float *grad, const int label_size, const int weight_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < weight_size){
for(int i = 0; i < label_size; i++){
grad[tid * label_size + i] = 0;
}
}
}
__global__ void initialize(float *sum, float *predict, const int data_size, const int label_size){
int tid = (blockIdx.y * blockDim.y + threadIdx.y) * gridDim.x * blockDim.x
+ blockIdx.x * blockDim.x + threadIdx.x;
if (tid < data_size){
sum[tid] = 0;
for(int i = 0; i < label_size; i++){
predict[tid * label_size + i] = 0;
}
}
}
int main(){
// malloc_host();
malloc_host();
readCSV("training_x.csv", training_x, 10000,1024);
readCSV("training_y.csv", training_y, 1024, 1);
readCSV("testing_x.csv", testing_x, 2000, 1024);
readCSV("testing_y.csv", testing_y, 2000, 1);
printf("label %f\n", training_y[9998][0]);
float learning_rate = 0.01;
int iter = 1;
int data_size = 10000;
int label_size = 10;
int weight_size = 1024;
int tratin_data_bytes = 10000 * 1024 * sizeof(float);
int weight_bytes = 1024 * 10 * sizeof(float);
int predict_bytes = 10000 * 10 * sizeof(float);
float *h_train_data = (float *) malloc( tratin_data_bytes ) ;
float *h_train_data_T = (float *) malloc( tratin_data_bytes ) ;
float *h_label_onehot = (float *) malloc( predict_bytes ) ;
float *h_weight = (float *) malloc( weight_bytes ) ;
float *h_predict = (float *) malloc( predict_bytes ) ;
float *h_max = (float *) malloc( 10000 * sizeof(float) ) ;
float *h_sum = (float *) malloc( 10000 * sizeof(float) ) ;
float *h_softmax = (float *) malloc( predict_bytes ) ;
float *h_dz = (float *) malloc( predict_bytes ) ;
float *h_grad = (float *) malloc( weight_bytes ) ;
////////////////////// Initialize //////////////////////
////////////////////// One Hot //////////////////////
for(int i = 0; i < data_size; i++){
for(int j = 0; j < weight_size; j++){
h_train_data_T[j * 10000 + i] = training_x[i][j];
}
}
for(int i = 0; i < data_size; i++){
label_onehot[i][(int(training_y[i][0] - 1))] = 1;
if(i == 1){
printf("training_y : %f\n", training_y[1][0]);
for(int j = 0; j < 10; j++) printf("onehot : %f\n", label_onehot[i][j]);
}
}
for(int i = 0; i < data_size; i++){
for(int j = 0; j < label_size; j++){
h_label_onehot[i * label_size + j] = label_onehot[i][j];
}
}
for(int i = 0; i < data_size; i++){
for(int j = 0; j < weight_size; j++){
h_train_data[i * weight_size + j] = training_x[i][j];
}
}
for(int i = 0; i < weight_size; i++){
for(int j = 0; j < label_size; j++){
h_weight[i * label_size + j] = 1 ;
}
}
//////////////////// Initialize //////////////////////
///////////////////////////////// GPU_SIDE ///////////////////////////////////
float *d_train_data, *d_train_data_T, *d_label, * d_weight, *d_predict, *d_predict_sum, *d_sum, *d_max, *d_softmax_value;
float *d_dz, *d_grad;
hipGetErrorString(hipMalloc( (void **) &d_train_data, tratin_data_bytes )) ;
hipGetErrorString(hipMalloc( (void **) &d_train_data_T, tratin_data_bytes )) ;
hipGetErrorString(hipMalloc( (void **) &d_label, predict_bytes)) ;
hipGetErrorString(hipMalloc( (void **) &d_predict, predict_bytes)) ;
hipGetErrorString(hipMalloc( (void **) &d_weight, weight_bytes)) ;
hipGetErrorString(hipMalloc( (void **) &d_sum, 10000 * sizeof(float))) ;
hipGetErrorString(hipMalloc( (void **) &d_softmax_value, predict_bytes)) ;
hipGetErrorString(hipMalloc( (void **) &d_dz, predict_bytes)) ;
hipGetErrorString(hipMalloc( (void **) &d_grad, weight_bytes)) ;
hipGetErrorString(hipMalloc( (void **) &d_max, 10000 * sizeof(float))) ;
// //Configure blockDim
int bdx = 32, bdy = 32;
while(data_size > bdx * 65535)
{
bdx = bdx * 2;
bdy = bdy / 2;
}
while(weight_size > bdy * 65535)
{
bdy = bdy * 2;
bdx = bdx / 2;
}
dim3 blockDim( bdx,bdy ) ; // you will want to configure this
dim3 gridDim( (int)((data_size + blockDim.x-1)/blockDim.x), (int)((weight_size + blockDim.y-1)/blockDim.y) ) ;
//////////////////////////////// invoke Kernel (Logistic Regression) ////////////////////////////////
hipGetErrorString(hipMemcpy( d_train_data_T, h_train_data_T, tratin_data_bytes, hipMemcpyHostToDevice )) ;
hipGetErrorString(hipMemcpy( d_train_data, h_train_data, tratin_data_bytes, hipMemcpyHostToDevice )) ;
hipGetErrorString(hipMemcpy( d_weight, h_weight, weight_bytes, hipMemcpyHostToDevice )) ;
hipGetErrorString(hipMemcpy( d_label, h_label_onehot, predict_bytes, hipMemcpyHostToDevice )) ;
for(int train = 0; train < 10; train++){
//Initialize
initialize<<<gridDim, blockDim>>>(d_sum, d_predict, data_size, label_size);
hipGetErrorString(hipDeviceSynchronize());
initialize_dz<<<gridDim, blockDim>>>(d_dz, label_size, data_size);
hipGetErrorString(hipDeviceSynchronize());
initialize_grad<<<gridDim, blockDim>>>(d_grad, label_size, weight_size);
hipGetErrorString(hipDeviceSynchronize());
// DOT
Mult_GPU<<<gridDim, blockDim>>>( d_train_data, d_weight, d_predict, data_size, weight_size, label_size) ;
hipGetErrorString(hipDeviceSynchronize());
max<<<gridDim, blockDim>>>( d_predict, d_max, label_size, data_size );
hipGetErrorString(hipDeviceSynchronize());
normalize<<<gridDim, blockDim>>>(d_predict, d_max, label_size, data_size);
hipGetErrorString(hipDeviceSynchronize());
// Softmax
softmax_sum<<<gridDim, blockDim>>>( d_predict, d_sum, label_size, data_size );
hipGetErrorString(hipDeviceSynchronize());
softmax<<<gridDim, blockDim>>>( d_softmax_value, d_predict, d_sum, label_size, data_size );
hipGetErrorString(hipDeviceSynchronize());
// Weight Update
dz<<<gridDim, blockDim>>>(d_softmax_value, d_label, d_dz, label_size, data_size);
hipGetErrorString(hipDeviceSynchronize());
Mult_GPU<<<gridDim, blockDim>>>( d_train_data_T, d_dz, d_grad, weight_size, data_size, label_size) ;
hipGetErrorString(hipDeviceSynchronize());
weight_update<<<gridDim, blockDim>>>(d_weight, d_grad, label_size, weight_size, learning_rate);
hipGetErrorString(hipDeviceSynchronize());
}
/////////////////////// Test //////////////////////////
hipGetErrorString(hipMemcpy( h_predict, d_predict, predict_bytes, hipMemcpyDeviceToHost )) ;
hipGetErrorString(hipMemcpy( h_softmax, d_softmax_value, predict_bytes, hipMemcpyDeviceToHost )) ;
hipGetErrorString(hipMemcpy( h_weight, d_weight, weight_bytes, hipMemcpyDeviceToHost )) ;
hipGetErrorString(hipMemcpy( h_max, d_max, 10000 * sizeof(float), hipMemcpyDeviceToHost )) ;
// int count = 0;
// for(int i = 0; i < data_size; i++){
// if(h_sum[i] == 10.0) count++;
// printf("max : %f\n", h_sum[i]);
// }
// printf("count 10 num = %d\n", count);
for(int i = 0; i < weight_size * label_size; i++){
printf("dz: %f\n", h_weight[i]);
}
// for(int i = 0; i < 10000; i++){
// printf("max: %f\n", log(h_max[i]) );
// }
// for(int i = 0; i < data_size * label_size; i++){
// // printf("softmax: %f\n", log(h_sum[i / label_size]) );
// printf("softmax: %f\n", h_softmax[i] );
// }
// float total_error = 0;
// for(int i = 0; i < data_size; i++){
// for(int j = 0; j < label_size; j++){
// total_error -= label_onehot[i][j] * log(h_softmax[i * label_size + j]) ;
// }
// }
// printf("error: %f\n", total_error );
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#define N (1024*1024)
#define M 1024
__global__ void dot(float *a, float *b, float *c) {
int i = blockDim.x*blockIdx.x + threadIdx.x, j = threadIdx.x;
__shared__ float ab[M];
ab[j] = a[i]*b[i];
__syncthreads();
if (!j) {
float s = 0.;
for (i = 0; i < M; i++)
s += ab[i];
atomicAdd(c, s);
}
}
int main(int argc, char *argv[]) {
int i = 0, size = N*sizeof(float);
float *a, *b, *c, *dev_a, *dev_b, *dev_c;
a = (float *) malloc(size);
b = (float *) malloc(size);
c = (float *) malloc(sizeof(float));
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, sizeof(float));
for (i = 0; i < N; i++) {a[i] = 1.; b[i] = 1.;} *c = 0.;
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, sizeof(float), cudaMemcpyHostToDevice);
dot<<<N/M, M>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, sizeof(float), cudaMemcpyDeviceToHost);
printf("%f\n", *c);
cudaFree(dev_c); cudaFree(dev_b); cudaFree(dev_a);
free(c); free(b); free(a);
return 0;
} | .file "tmpxft_00160529_00000000-6_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPfS_S_PfS_S_
.type _Z26__device_stub__Z3dotPfS_S_PfS_S_, @function
_Z26__device_stub__Z3dotPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3dotPfS_S_PfS_S_, .-_Z26__device_stub__Z3dotPfS_S_PfS_S_
.globl _Z3dotPfS_S_
.type _Z3dotPfS_S_, @function
_Z3dotPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3dotPfS_S_, .-_Z3dotPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm0
.L12:
movss %xmm0, (%rbx,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $0x00000000, (%r12)
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3dotPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#define N (1024*1024)
#define M 1024
__global__ void dot(float *a, float *b, float *c) {
int i = blockDim.x*blockIdx.x + threadIdx.x, j = threadIdx.x;
__shared__ float ab[M];
ab[j] = a[i]*b[i];
__syncthreads();
if (!j) {
float s = 0.;
for (i = 0; i < M; i++)
s += ab[i];
atomicAdd(c, s);
}
}
int main(int argc, char *argv[]) {
int i = 0, size = N*sizeof(float);
float *a, *b, *c, *dev_a, *dev_b, *dev_c;
a = (float *) malloc(size);
b = (float *) malloc(size);
c = (float *) malloc(sizeof(float));
cudaMalloc((void **) &dev_a, size);
cudaMalloc((void **) &dev_b, size);
cudaMalloc((void **) &dev_c, sizeof(float));
for (i = 0; i < N; i++) {a[i] = 1.; b[i] = 1.;} *c = 0.;
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c, sizeof(float), cudaMemcpyHostToDevice);
dot<<<N/M, M>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, sizeof(float), cudaMemcpyDeviceToHost);
printf("%f\n", *c);
cudaFree(dev_c); cudaFree(dev_b); cudaFree(dev_a);
free(c); free(b); free(a);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#define N (1024*1024)
#define M 1024
__global__ void dot(float *a, float *b, float *c) {
int i = blockDim.x*blockIdx.x + threadIdx.x, j = threadIdx.x;
__shared__ float ab[M];
ab[j] = a[i]*b[i];
__syncthreads();
if (!j) {
float s = 0.;
for (i = 0; i < M; i++)
s += ab[i];
atomicAdd(c, s);
}
}
int main(int argc, char *argv[]) {
int i = 0, size = N*sizeof(float);
float *a, *b, *c, *dev_a, *dev_b, *dev_c;
a = (float *) malloc(size);
b = (float *) malloc(size);
c = (float *) malloc(sizeof(float));
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, sizeof(float));
for (i = 0; i < N; i++) {a[i] = 1.; b[i] = 1.;} *c = 0.;
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
hipMemcpy(dev_c, c, sizeof(float), hipMemcpyHostToDevice);
dot<<<N/M, M>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, sizeof(float), hipMemcpyDeviceToHost);
printf("%f\n", *c);
hipFree(dev_c); hipFree(dev_b); hipFree(dev_a);
free(c); free(b); free(a);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define N (1024*1024)
#define M 1024
__global__ void dot(float *a, float *b, float *c) {
int i = blockDim.x*blockIdx.x + threadIdx.x, j = threadIdx.x;
__shared__ float ab[M];
ab[j] = a[i]*b[i];
__syncthreads();
if (!j) {
float s = 0.;
for (i = 0; i < M; i++)
s += ab[i];
atomicAdd(c, s);
}
}
int main(int argc, char *argv[]) {
int i = 0, size = N*sizeof(float);
float *a, *b, *c, *dev_a, *dev_b, *dev_c;
a = (float *) malloc(size);
b = (float *) malloc(size);
c = (float *) malloc(sizeof(float));
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, sizeof(float));
for (i = 0; i < N; i++) {a[i] = 1.; b[i] = 1.;} *c = 0.;
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
hipMemcpy(dev_c, c, sizeof(float), hipMemcpyHostToDevice);
dot<<<N/M, M>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, sizeof(float), hipMemcpyDeviceToHost);
printf("%f\n", *c);
hipFree(dev_c); hipFree(dev_b); hipFree(dev_a);
free(c); free(b); free(a);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3dotPfS_S_
.globl _Z3dotPfS_S_
.p2align 8
.type _Z3dotPfS_S_,@function
_Z3dotPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, 0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[3:4], off
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
v_dual_mul_f32 v1, v3, v1 :: v_dual_lshlrev_b32 v2, 2, v0
ds_store_b32 v2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
.LBB0_2:
v_mov_b32_e32 v1, s2
s_add_i32 s2, s2, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmpk_lg_i32 s2, 0x1000
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v0, v1
s_cbranch_scc1 .LBB0_2
s_mov_b32 s3, exec_lo
s_mov_b32 s2, 0
v_mbcnt_lo_u32_b32 v1, s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
s_and_b32 s4, exec_lo, vcc_lo
s_mov_b32 exec_lo, s4
s_cbranch_execz .LBB0_6
s_load_b64 s[0:1], s[0:1], 0x10
s_bcnt1_i32_b32 s3, s3
v_mov_b32_e32 v3, 0
v_cvt_f32_ubyte0_e32 v1, s3
s_waitcnt lgkmcnt(0)
s_load_b32 s4, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_dual_mul_f32 v2, v0, v1 :: v_dual_mov_b32 v1, s4
.LBB0_5:
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v0, v1, v2
global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v0, v1
v_mov_b32_e32 v1, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_5
.LBB0_6:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dotPfS_S_
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3dotPfS_S_, .Lfunc_end0-_Z3dotPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dotPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dotPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#define N (1024*1024)
#define M 1024
__global__ void dot(float *a, float *b, float *c) {
int i = blockDim.x*blockIdx.x + threadIdx.x, j = threadIdx.x;
__shared__ float ab[M];
ab[j] = a[i]*b[i];
__syncthreads();
if (!j) {
float s = 0.;
for (i = 0; i < M; i++)
s += ab[i];
atomicAdd(c, s);
}
}
int main(int argc, char *argv[]) {
int i = 0, size = N*sizeof(float);
float *a, *b, *c, *dev_a, *dev_b, *dev_c;
a = (float *) malloc(size);
b = (float *) malloc(size);
c = (float *) malloc(sizeof(float));
hipMalloc((void **) &dev_a, size);
hipMalloc((void **) &dev_b, size);
hipMalloc((void **) &dev_c, sizeof(float));
for (i = 0; i < N; i++) {a[i] = 1.; b[i] = 1.;} *c = 0.;
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
hipMemcpy(dev_c, c, sizeof(float), hipMemcpyHostToDevice);
dot<<<N/M, M>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, sizeof(float), hipMemcpyDeviceToHost);
printf("%f\n", *c);
hipFree(dev_c); hipFree(dev_b); hipFree(dev_a);
free(c); free(b); free(a);
return 0;
} | .text
.file "dot.hip"
.globl _Z18__device_stub__dotPfS_S_ # -- Begin function _Z18__device_stub__dotPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPfS_S_,@function
_Z18__device_stub__dotPfS_S_: # @_Z18__device_stub__dotPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPfS_S_, .Lfunc_end0-_Z18__device_stub__dotPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
movl $0, (%r15)
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdi # imm = 0x100000400
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPfS_S_,@object # @_Z3dotPfS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPfS_S_
.p2align 3, 0x0
_Z3dotPfS_S_:
.quad _Z18__device_stub__dotPfS_S_
.size _Z3dotPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00160529_00000000-6_dot.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3dotPfS_S_PfS_S_
.type _Z26__device_stub__Z3dotPfS_S_PfS_S_, @function
_Z26__device_stub__Z3dotPfS_S_PfS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3dotPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3dotPfS_S_PfS_S_, .-_Z26__device_stub__Z3dotPfS_S_PfS_S_
.globl _Z3dotPfS_S_
.type _Z3dotPfS_S_, @function
_Z3dotPfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3dotPfS_S_, .-_Z3dotPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0, %eax
movss .LC0(%rip), %xmm0
.L12:
movss %xmm0, (%rbx,%rax)
movss %xmm0, 0(%rbp,%rax)
addq $4, %rax
cmpq $4194304, %rax
jne .L12
movl $0x00000000, (%r12)
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1024, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movl $2, %ecx
movl $4, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z3dotPfS_S_PfS_S_
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z3dotPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z3dotPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dot.hip"
.globl _Z18__device_stub__dotPfS_S_ # -- Begin function _Z18__device_stub__dotPfS_S_
.p2align 4, 0x90
.type _Z18__device_stub__dotPfS_S_,@function
_Z18__device_stub__dotPfS_S_: # @_Z18__device_stub__dotPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__dotPfS_S_, .Lfunc_end0-_Z18__device_stub__dotPfS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $128, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4, %edi
callq malloc
movq %rax, %r15
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%rbx,%rax,4) # imm = 0x3F800000
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1048576, %rax # imm = 0x100000
jne .LBB1_1
# %bb.2:
movl $0, (%r15)
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq (%rsp), %rdi
movl $4, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294968320, %rdi # imm = 0x100000400
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3dotPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
movl $4, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movss (%r15), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movq (%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $128, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3dotPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3dotPfS_S_,@object # @_Z3dotPfS_S_
.section .rodata,"a",@progbits
.globl _Z3dotPfS_S_
.p2align 3, 0x0
_Z3dotPfS_S_:
.quad _Z18__device_stub__dotPfS_S_
.size _Z3dotPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3dotPfS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__dotPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3dotPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // linear algebra calculation on GPU devices
// By Zheshu Wu, Jun 1, 2018
#include<stdio.h>
#define N 33 * 1024
__global__ void add(int *a, int *b, int *c)
{
// int tid = 0; // CPU zero, so we start at zero
// while (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// tid += 1; // we have one CPU, so we increment by one
// }
// int tid = blockIdx.x; //handle the data at this index
// if (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// }
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N)
{
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x; // increment the index
}
}
int main(int argc, char const *argv[])
{
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
cudaMalloc( (void**)&dev_a, N * sizeof(int) );
cudaMalloc( (void**)&dev_b, N * sizeof(int) );
cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the array 'a' and 'b' on the CPU
for (int i=0; i<N; i++)
{
a[i] = -i;
b[i] = i * i;
}
// add ( a, b, c );
//copy the arrays 'a' and 'b' to the GPU
cudaMemcpy( dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
add<<< 128, 128 >>>(dev_a, dev_b, dev_c);
// copy the array 'c' back from the GPU to the CPU
cudaMemcpy( c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost);
// display the results
// for (int i=0; i<N; i++)
// {
// printf( "%d + %d = %d\n", a[i], b[i], c[i]);
// }
// verify that the GPU did the work we requested
bool success = true;
for (int i=0; i<N; i++)
{
if ((a[i] + b[i]) != c[i])
{
printf( "Error: %d + %d != %d\n", a[i], b[i], c[i] );
success = false;
}
}
if (success) printf( "We did it!\n");
// free the memory allocated on the GPU
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x83ff, PT ; /* 0x000083ff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x8400, PT ; /* 0x000084000000780c */
/* 0x000fe40003f06270 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // linear algebra calculation on GPU devices
// By Zheshu Wu, Jun 1, 2018
#include<stdio.h>
#define N 33 * 1024
__global__ void add(int *a, int *b, int *c)
{
// int tid = 0; // CPU zero, so we start at zero
// while (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// tid += 1; // we have one CPU, so we increment by one
// }
// int tid = blockIdx.x; //handle the data at this index
// if (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// }
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N)
{
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x; // increment the index
}
}
int main(int argc, char const *argv[])
{
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
cudaMalloc( (void**)&dev_a, N * sizeof(int) );
cudaMalloc( (void**)&dev_b, N * sizeof(int) );
cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the array 'a' and 'b' on the CPU
for (int i=0; i<N; i++)
{
a[i] = -i;
b[i] = i * i;
}
// add ( a, b, c );
//copy the arrays 'a' and 'b' to the GPU
cudaMemcpy( dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
add<<< 128, 128 >>>(dev_a, dev_b, dev_c);
// copy the array 'c' back from the GPU to the CPU
cudaMemcpy( c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost);
// display the results
// for (int i=0; i<N; i++)
// {
// printf( "%d + %d = %d\n", a[i], b[i], c[i]);
// }
// verify that the GPU did the work we requested
bool success = true;
for (int i=0; i<N; i++)
{
if ((a[i] + b[i]) != c[i])
{
printf( "Error: %d + %d != %d\n", a[i], b[i], c[i] );
success = false;
}
}
if (success) printf( "We did it!\n");
// free the memory allocated on the GPU
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
return 0;
} | .file "tmpxft_0002e957_00000000-6_linearAlgebra.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error: %d + %d != %d\n"
.LC1:
.string "We did it!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -405504(%rsp), %r11
.cfi_def_cfa 11, 405528
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $72, %rsp
.cfi_def_cfa_offset 405600
movq %fs:40, %rax
movq %rax, 405560(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $135168, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $135168, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $135168, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, %edx
negl %edx
movl %edx, 48(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 135216(%rsp,%rax,4)
addq $1, %rax
cmpq $33792, %rax
jne .L12
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $135168, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 135216(%rsp), %rsi
movl $1, %ecx
movl $135168, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $128, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
leaq 270384(%rsp), %rdi
movl $2, %ecx
movl $135168, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
movl $1, %esi
leaq .LC0(%rip), %rbp
jmp .L15
.L21:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L14:
addq $4, %rbx
cmpq $135168, %rbx
je .L22
.L15:
movl 48(%rsp,%rbx), %edx
movl 135216(%rsp,%rbx), %ecx
movl 270384(%rsp,%rbx), %r8d
leal (%rdx,%rcx), %eax
cmpl %r8d, %eax
je .L14
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
jmp .L14
.L22:
testb %sil, %sil
jne .L23
.L16:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 405560(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $405576, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // linear algebra calculation on GPU devices
// By Zheshu Wu, Jun 1, 2018
#include<stdio.h>
#define N 33 * 1024
__global__ void add(int *a, int *b, int *c)
{
// int tid = 0; // CPU zero, so we start at zero
// while (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// tid += 1; // we have one CPU, so we increment by one
// }
// int tid = blockIdx.x; //handle the data at this index
// if (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// }
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N)
{
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x; // increment the index
}
}
int main(int argc, char const *argv[])
{
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
cudaMalloc( (void**)&dev_a, N * sizeof(int) );
cudaMalloc( (void**)&dev_b, N * sizeof(int) );
cudaMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the array 'a' and 'b' on the CPU
for (int i=0; i<N; i++)
{
a[i] = -i;
b[i] = i * i;
}
// add ( a, b, c );
//copy the arrays 'a' and 'b' to the GPU
cudaMemcpy( dev_a, a, N * sizeof(int), cudaMemcpyHostToDevice);
cudaMemcpy( dev_b, b, N * sizeof(int), cudaMemcpyHostToDevice);
add<<< 128, 128 >>>(dev_a, dev_b, dev_c);
// copy the array 'c' back from the GPU to the CPU
cudaMemcpy( c, dev_c, N * sizeof(int), cudaMemcpyDeviceToHost);
// display the results
// for (int i=0; i<N; i++)
// {
// printf( "%d + %d = %d\n", a[i], b[i], c[i]);
// }
// verify that the GPU did the work we requested
bool success = true;
for (int i=0; i<N; i++)
{
if ((a[i] + b[i]) != c[i])
{
printf( "Error: %d + %d != %d\n", a[i], b[i], c[i] );
success = false;
}
}
if (success) printf( "We did it!\n");
// free the memory allocated on the GPU
cudaFree( dev_a );
cudaFree( dev_b );
cudaFree( dev_c );
return 0;
} | // linear algebra calculation on GPU devices
// By Zheshu Wu, Jun 1, 2018
#include <hip/hip_runtime.h>
#include<stdio.h>
#define N 33 * 1024
__global__ void add(int *a, int *b, int *c)
{
// int tid = 0; // CPU zero, so we start at zero
// while (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// tid += 1; // we have one CPU, so we increment by one
// }
// int tid = blockIdx.x; //handle the data at this index
// if (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// }
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N)
{
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x; // increment the index
}
}
int main(int argc, char const *argv[])
{
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
hipMalloc( (void**)&dev_a, N * sizeof(int) );
hipMalloc( (void**)&dev_b, N * sizeof(int) );
hipMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the array 'a' and 'b' on the CPU
for (int i=0; i<N; i++)
{
a[i] = -i;
b[i] = i * i;
}
// add ( a, b, c );
//copy the arrays 'a' and 'b' to the GPU
hipMemcpy( dev_a, a, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy( dev_b, b, N * sizeof(int), hipMemcpyHostToDevice);
add<<< 128, 128 >>>(dev_a, dev_b, dev_c);
// copy the array 'c' back from the GPU to the CPU
hipMemcpy( c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost);
// display the results
// for (int i=0; i<N; i++)
// {
// printf( "%d + %d = %d\n", a[i], b[i], c[i]);
// }
// verify that the GPU did the work we requested
bool success = true;
for (int i=0; i<N; i++)
{
if ((a[i] + b[i]) != c[i])
{
printf( "Error: %d + %d != %d\n", a[i], b[i], c[i] );
success = false;
}
}
if (success) printf( "We did it!\n");
// free the memory allocated on the GPU
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // linear algebra calculation on GPU devices
// By Zheshu Wu, Jun 1, 2018
#include <hip/hip_runtime.h>
#include<stdio.h>
#define N 33 * 1024
__global__ void add(int *a, int *b, int *c)
{
// int tid = 0; // CPU zero, so we start at zero
// while (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// tid += 1; // we have one CPU, so we increment by one
// }
// int tid = blockIdx.x; //handle the data at this index
// if (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// }
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N)
{
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x; // increment the index
}
}
int main(int argc, char const *argv[])
{
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
hipMalloc( (void**)&dev_a, N * sizeof(int) );
hipMalloc( (void**)&dev_b, N * sizeof(int) );
hipMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the array 'a' and 'b' on the CPU
for (int i=0; i<N; i++)
{
a[i] = -i;
b[i] = i * i;
}
// add ( a, b, c );
//copy the arrays 'a' and 'b' to the GPU
hipMemcpy( dev_a, a, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy( dev_b, b, N * sizeof(int), hipMemcpyHostToDevice);
add<<< 128, 128 >>>(dev_a, dev_b, dev_c);
// copy the array 'c' back from the GPU to the CPU
hipMemcpy( c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost);
// display the results
// for (int i=0; i<N; i++)
// {
// printf( "%d + %d = %d\n", a[i], b[i], c[i]);
// }
// verify that the GPU did the work we requested
bool success = true;
for (int i=0; i<N; i++)
{
if ((a[i] + b[i]) != c[i])
{
printf( "Error: %d + %d != %d\n", a[i], b[i], c[i] );
success = false;
}
}
if (success) printf( "We did it!\n");
// free the memory allocated on the GPU
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x8400, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x83ff, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // linear algebra calculation on GPU devices
// By Zheshu Wu, Jun 1, 2018
#include <hip/hip_runtime.h>
#include<stdio.h>
#define N 33 * 1024
__global__ void add(int *a, int *b, int *c)
{
// int tid = 0; // CPU zero, so we start at zero
// while (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// tid += 1; // we have one CPU, so we increment by one
// }
// int tid = blockIdx.x; //handle the data at this index
// if (tid < N)
// {
// c[tid] = a[tid] + b[tid];
// }
int tid = threadIdx.x + blockIdx.x * blockDim.x;
while (tid < N)
{
c[tid] = a[tid] + b[tid];
tid += blockDim.x * gridDim.x; // increment the index
}
}
int main(int argc, char const *argv[])
{
int a[N], b[N], c[N];
int *dev_a, *dev_b, *dev_c;
// allocate the memory on the GPU
hipMalloc( (void**)&dev_a, N * sizeof(int) );
hipMalloc( (void**)&dev_b, N * sizeof(int) );
hipMalloc( (void**)&dev_c, N * sizeof(int) );
// fill the array 'a' and 'b' on the CPU
for (int i=0; i<N; i++)
{
a[i] = -i;
b[i] = i * i;
}
// add ( a, b, c );
//copy the arrays 'a' and 'b' to the GPU
hipMemcpy( dev_a, a, N * sizeof(int), hipMemcpyHostToDevice);
hipMemcpy( dev_b, b, N * sizeof(int), hipMemcpyHostToDevice);
add<<< 128, 128 >>>(dev_a, dev_b, dev_c);
// copy the array 'c' back from the GPU to the CPU
hipMemcpy( c, dev_c, N * sizeof(int), hipMemcpyDeviceToHost);
// display the results
// for (int i=0; i<N; i++)
// {
// printf( "%d + %d = %d\n", a[i], b[i], c[i]);
// }
// verify that the GPU did the work we requested
bool success = true;
for (int i=0; i<N; i++)
{
if ((a[i] + b[i]) != c[i])
{
printf( "Error: %d + %d != %d\n", a[i], b[i], c[i] );
success = false;
}
}
if (success) printf( "We did it!\n");
// free the memory allocated on the GPU
hipFree( dev_a );
hipFree( dev_b );
hipFree( dev_c );
return 0;
} | .text
.file "linearAlgebra.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $405608, %rsp # imm = 0x63068
.cfi_def_cfa_offset 405632
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
movq %rsp, %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 270432(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 135264(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $33792, %rcx # imm = 0x8400
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 270432(%rsp), %rsi
movl $135168, %edx # imm = 0x21000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 135264(%rsp), %rsi
movl $135168, %edx # imm = 0x21000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967424, %rdi # imm = 0x100000080
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $135168, %edx # imm = 0x21000
movl $2, %ecx
callq hipMemcpy
movb $1, %bl
xorl %r14d, %r14d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r14
cmpq $33792, %r14 # imm = 0x8400
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 270432(%rsp,%r14,4), %esi
movl 135264(%rsp,%r14,4), %edx
leal (%rdx,%rsi), %eax
movl 96(%rsp,%r14,4), %ecx
cmpl %ecx, %eax
je .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
xorl %ebx, %ebx
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
jmp .LBB1_7
.LBB1_8:
testb $1, %bl
je .LBB1_10
# %bb.9:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_10:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $405608, %rsp # imm = 0x63068
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %d + %d != %d\n"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "We did it!"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R0, 0x83ff, PT ; /* 0x000083ff0000780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x001fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R4, R0.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe200078e0207 */
/*00d0*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fca0000000f00 */
/*00e0*/ IMAD R0, R11, c[0x0][0xc], R0 ; /* 0x000003000b007a24 */
/* 0x000fca00078e0200 */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x8400, PT ; /* 0x000084000000780c */
/* 0x000fe40003f06270 */
/*0100*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*0110*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x0001ec000c101904 */
/*0120*/ @!P0 BRA 0x70 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s4, s[0:1], 0x24
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x8400, v1
s_cbranch_execz .LBB0_3
s_load_b32 s9, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s9, s8
s_mov_b32 s8, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x83ff, v1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s8, vcc_lo, s8
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002e957_00000000-6_linearAlgebra.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Error: %d + %d != %d\n"
.LC1:
.string "We did it!\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -405504(%rsp), %r11
.cfi_def_cfa 11, 405528
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $72, %rsp
.cfi_def_cfa_offset 405600
movq %fs:40, %rax
movq %rax, 405560(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $135168, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $135168, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $135168, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, %edx
negl %edx
movl %edx, 48(%rsp,%rax,4)
movl %eax, %edx
imull %eax, %edx
movl %edx, 135216(%rsp,%rax,4)
addq $1, %rax
cmpq $33792, %rax
jne .L12
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $135168, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 135216(%rsp), %rsi
movl $1, %ecx
movl $135168, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $128, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $128, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L13:
leaq 270384(%rsp), %rdi
movl $2, %ecx
movl $135168, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
movl $1, %esi
leaq .LC0(%rip), %rbp
jmp .L15
.L21:
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L14:
addq $4, %rbx
cmpq $135168, %rbx
je .L22
.L15:
movl 48(%rsp,%rbx), %edx
movl 135216(%rsp,%rbx), %ecx
movl 270384(%rsp,%rbx), %r8d
leal (%rdx,%rcx), %eax
cmpl %r8d, %eax
je .L14
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %esi
jmp .L14
.L22:
testb %sil, %sil
jne .L23
.L16:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 405560(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $405576, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC2:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "linearAlgebra.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $405608, %rsp # imm = 0x63068
.cfi_def_cfa_offset 405632
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
leaq 16(%rsp), %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
movq %rsp, %rdi
movl $135168, %esi # imm = 0x21000
callq hipMalloc
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 270432(%rsp,%rcx,4)
movl %ecx, %edx
imull %ecx, %edx
movl %edx, 135264(%rsp,%rcx,4)
incq %rcx
decl %eax
cmpq $33792, %rcx # imm = 0x8400
jne .LBB1_1
# %bb.2:
movq 16(%rsp), %rdi
leaq 270432(%rsp), %rsi
movl $135168, %edx # imm = 0x21000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 135264(%rsp), %rsi
movl $135168, %edx # imm = 0x21000
movl $1, %ecx
callq hipMemcpy
movabsq $4294967424, %rdi # imm = 0x100000080
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 96(%rsp), %rdi
movl $135168, %edx # imm = 0x21000
movl $2, %ecx
callq hipMemcpy
movb $1, %bl
xorl %r14d, %r14d
jmp .LBB1_5
.p2align 4, 0x90
.LBB1_7: # in Loop: Header=BB1_5 Depth=1
incq %r14
cmpq $33792, %r14 # imm = 0x8400
je .LBB1_8
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 270432(%rsp,%r14,4), %esi
movl 135264(%rsp,%r14,4), %edx
leal (%rdx,%rsi), %eax
movl 96(%rsp,%r14,4), %ecx
cmpl %ecx, %eax
je .LBB1_7
# %bb.6: # in Loop: Header=BB1_5 Depth=1
xorl %ebx, %ebx
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
xorl %eax, %eax
callq printf
jmp .LBB1_7
.LBB1_8:
testb $1, %bl
je .LBB1_10
# %bb.9:
movl $.Lstr, %edi
callq puts@PLT
.LBB1_10:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $405608, %rsp # imm = 0x63068
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error: %d + %d != %d\n"
.size .L.str, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "We did it!"
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Assignment 07 Program - moving_average.cu (edited from module 6 for 7)
* Sarah Helble
* 10/16/17
*
* Calculates the average of each index and its neighbors
*
* Usage ./a.out [-v] [-n num_elements] [-b threads_per_block] [-m max_int]
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda.h>
#include <unistd.h>
#define DEFAULT_NUM_ELEMENTS 512
#define DEFAULT_THREADS_PER_BLOCK 256
#define DEFAULT_MAX_INT 30
/**
* Kernel function that takes a moving average of the values in
* @list and puts the results in @averages
* Uses registers to store the calculations.
*/
__global__ void average_window(unsigned int *list, float *averages, int num_elements)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
unsigned int sum;
unsigned int num;
if(idx == 0) {
sum = list[idx] + list[idx+1];
num = 2;
} else if(idx + 1 == num_elements) {
sum = list[idx] + list[idx-1];
num = 2;
} else {
sum = list[idx] + list[idx-1] + list[idx+1];
num = 3;
}
averages[idx] = (float) sum / num;
}
/**
* Fuction to handle the printing of results.
* @list is the original array
* @averages is the result
*/
void print_results(unsigned int *list, float *averages, int num_elements)
{
int i = 0;
printf("\n");
for(i = 0; i < num_elements; i++) {
printf("Original value at index [%d]: %d, average: %f\n", i, list[i], averages[i]);
}
printf("\n");
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_sync(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
cudaEvent_t start, stop;
float duration;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMalloc((void **)&d_list, array_size_in_bytes);
cudaMalloc((void **)&d_averages, float_array_size_in_bytes);
cudaMallocHost((void **)&list, array_size_in_bytes);
cudaMallocHost((void **)&averages, float_array_size_in_bytes);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
cudaEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory */
cudaMemcpy(d_list, list, array_size_in_bytes, cudaMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
cudaMemcpy( averages, d_averages, float_array_size_in_bytes, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
cudaFree(d_list);
cudaFree(d_averages);
/* Free the pinned CPU memory */
cudaFreeHost(list);
cudaFreeHost(averages);
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_async(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
cudaEvent_t start, stop;
float duration;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaStream_t stream;
cudaStreamCreate(&stream);
cudaMalloc((void **)&d_list, array_size_in_bytes);
cudaMalloc((void **)&d_averages, float_array_size_in_bytes);
cudaMallocHost((void **)&list, array_size_in_bytes);
cudaMallocHost((void **)&averages, float_array_size_in_bytes);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
cudaEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory asynchronously */
cudaMemcpyAsync(d_list, list, array_size_in_bytes, cudaMemcpyHostToDevice, stream);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
cudaMemcpyAsync( averages, d_averages, float_array_size_in_bytes, cudaMemcpyDeviceToHost, stream);
cudaStreamSynchronize(stream);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
cudaFree(d_list);
cudaFree(d_averages);
/* Free the pinned CPU memory */
cudaFreeHost(list);
cudaFreeHost(averages);
}
/**
* Entry point for execution. Checks command line arguments
* then passes execution to subordinate function
*/
int main(int argc, char *argv[])
{
int verbosity = 0;
int num_elements = DEFAULT_NUM_ELEMENTS;
int threads_per_block = DEFAULT_THREADS_PER_BLOCK;
int max_int = DEFAULT_MAX_INT;
int c;
while((c = getopt(argc, argv, "vn:b:m:")) != -1) {
switch(c) {
case 'v':
verbosity = 1;
break;
case 'n':
num_elements = atoi(optarg);
break;
case 'b':
threads_per_block = atoi(optarg);
break;
case 'm':
max_int = atoi(optarg);
break;
default:
printf("Error: unrecognized option: %c\n", c);
printf("Usage: %s [-v] [-n num_elements] [-b threads_per_block] [-m max_int]", argv[0]);
exit(-1);
}
}
printf("verbosity: %d\tnum_elements: %d\tthreads_per_block: %d\tmax_int: %d\n",
verbosity, num_elements, threads_per_block, max_int);
/* Do the average with shared memory */
printf("\nFirst Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
/* Do the average with shared memory */
printf("\nFirst Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
return EXIT_SUCCESS;
} | code for sm_80
Function : _Z14average_windowPjPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x210 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R6, RZ, RZ, 0x40000000 ; /* 0x40000000ff067424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0080*/ @!P0 BRA 0x1a0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0009 */
/*00c0*/ IMAD.WIDE.U32 R2, R0.reuse, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x040fe400078e0009 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*00f0*/ IADD3 R7, R0, 0x1, RZ ; /* 0x0000000100077810 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.NE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*0120*/ IMAD.IADD R8, R4, 0x1, R3 ; /* 0x0000000104087824 */
/* 0x004fe400078e0203 */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd000078e00ff */
/*0140*/ @!P0 BRA 0x200 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.WIDE.U32 R4, R7, R9, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fcc00078e0009 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, 0x40400000 ; /* 0x40400000ff067424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x004fe200078e0205 */
/*0190*/ BRA 0x200 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fca00078e00ff */
/*01c0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040404077981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*01f0*/ IMAD.IADD R8, R8, 0x1, R7 ; /* 0x0000000108087824 */
/* 0x004fe400078e0207 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ I2F.U32 R9, R8 ; /* 0x0000000800097306 */
/* 0x000e220000201000 */
/*0220*/ BSSY B0, 0x2e0 ; /* 0x000000b000007945 */
/* 0x000fee0003800000 */
/*0230*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x000e700000001000 */
/*0240*/ FCHK P0, R9, R6 ; /* 0x0000000609007302 */
/* 0x001e220000000000 */
/*0250*/ FFMA R0, R5, -R6, 1 ; /* 0x3f80000005007423 */
/* 0x002fc80000000806 */
/*0260*/ FFMA R0, R5, R0, R5 ; /* 0x0000000005007223 */
/* 0x000fc80000000005 */
/*0270*/ FFMA R5, R9, R0, RZ ; /* 0x0000000009057223 */
/* 0x000fc800000000ff */
/*0280*/ FFMA R4, R5, -R6, R9 ; /* 0x8000000605047223 */
/* 0x000fc80000000009 */
/*0290*/ FFMA R7, R0, R4, R5 ; /* 0x0000000400077223 */
/* 0x000fe20000000005 */
/*02a0*/ @!P0 BRA 0x2d0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*02b0*/ MOV R0, 0x2d0 ; /* 0x000002d000007802 */
/* 0x000fe40000000f00 */
/*02c0*/ CALL.REL.NOINC 0x320 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*02f0*/ LEA.HI.X R5, R2, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f1403 */
/*0300*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ SHF.R.U32.HI R5, RZ, 0x17, R6 ; /* 0x00000017ff057819 */
/* 0x000fe20000011606 */
/*0330*/ BSSY B1, 0x980 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0340*/ SHF.R.U32.HI R4, RZ, 0x17, R9.reuse ; /* 0x00000017ff047819 */
/* 0x100fe40000011609 */
/*0350*/ LOP3.LUT R13, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050d7812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0370*/ LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040a7812 */
/* 0x000fe400078ec0ff */
/*0380*/ IADD3 R11, R13, -0x1, RZ ; /* 0xffffffff0d0b7810 */
/* 0x000fe40007ffe0ff */
/*0390*/ IADD3 R8, R10, -0x1, RZ ; /* 0xffffffff0a087810 */
/* 0x000fc40007ffe0ff */
/*03a0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*03b0*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*03c0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*03d0*/ @!P0 BRA 0x560 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*03e0*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe20003f3c200 */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0009 */
/*0400*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f1c200 */
/*0410*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0420*/ @P0 BRA 0x960 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0430*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0440*/ @!P0 BRA 0x940 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0450*/ FSETP.NEU.FTZ.AND P2, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f5d200 */
/*0460*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*0470*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0480*/ @!P1 BRA !P2, 0x940 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0490*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*04a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*04b0*/ @P1 BRA 0x920 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*04c0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*04d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04e0*/ @P0 BRA 0x8f0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*04f0*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*0500*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0510*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0520*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0530*/ @!P0 FFMA R5, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004058823 */
/* 0x000fe400000000ff */
/*0540*/ @!P1 FFMA R6, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006069823 */
/* 0x000fe200000000ff */
/*0550*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0560*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fe200078eb8ff */
/*0570*/ BSSY B2, 0x8e0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0580*/ IMAD.IADD R9, R6, 0x1, -R9 ; /* 0x0000000106097824 */
/* 0x000fe200078e0a09 */
/*0590*/ IADD3 R6, R10, -0x7f, RZ ; /* 0xffffff810a067810 */
/* 0x000fc60007ffe0ff */
/*05a0*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*05b0*/ FADD.FTZ R8, -R9, -RZ ; /* 0x800000ff09087221 */
/* 0x000fe40000010100 */
/*05c0*/ IMAD R5, R6.reuse, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x040fe200078e0205 */
/*05d0*/ IADD3 R6, R6, 0x7f, -R13 ; /* 0x0000007f06067810 */
/* 0x000fca0007ffe80d */
/*05e0*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x000fe400078e0207 */
/*05f0*/ FFMA R11, R4, R8, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000008 */
/*0600*/ FFMA R10, R4, R11, R4 ; /* 0x0000000b040a7223 */
/* 0x000fc80000000004 */
/*0610*/ FFMA R4, R5, R10, RZ ; /* 0x0000000a05047223 */
/* 0x000fc800000000ff */
/*0620*/ FFMA R11, R8, R4, R5 ; /* 0x00000004080b7223 */
/* 0x000fc80000000005 */
/*0630*/ FFMA R11, R10, R11, R4 ; /* 0x0000000b0a0b7223 */
/* 0x000fc80000000004 */
/*0640*/ FFMA R8, R8, R11, R5 ; /* 0x0000000b08087223 */
/* 0x000fc80000000005 */
/*0650*/ FFMA R4, R10, R8, R11 ; /* 0x000000080a047223 */
/* 0x000fca000000000b */
/*0660*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0670*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0680*/ IMAD.IADD R9, R5, 0x1, R6 ; /* 0x0000000105097824 */
/* 0x000fca00078e0206 */
/*0690*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*06a0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*06b0*/ @!P0 BRA 0x8c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*06c0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*06d0*/ @P0 BRA 0x890 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*06e0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*06f0*/ @P0 BRA 0x8d0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0700*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0710*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0720*/ @!P0 BRA 0x8d0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0730*/ FFMA.RZ R5, R10.reuse, R8.reuse, R11.reuse ; /* 0x000000080a057223 */
/* 0x1c0fe2000000c00b */
/*0740*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*0750*/ FFMA.RM R6, R10.reuse, R8.reuse, R11.reuse ; /* 0x000000080a067223 */
/* 0x1c0fe2000000400b */
/*0760*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0770*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0780*/ FFMA.RP R5, R10, R8, R11 ; /* 0x000000080a057223 */
/* 0x000fe2000000800b */
/*0790*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*07a0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*07b0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*07c0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*07d0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*07e0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*07f0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0800*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0810*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0820*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0830*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0840*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0850*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0860*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0870*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0880*/ BRA 0x8d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0890*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*08a0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*08b0*/ BRA 0x8d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08c0*/ IMAD R4, R6, 0x800000, R4 ; /* 0x0080000006047824 */
/* 0x000fe400078e0204 */
/*08d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x970 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*08f0*/ LOP3.LUT R4, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006047812 */
/* 0x000fc800078e4805 */
/*0900*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0910*/ BRA 0x970 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT R4, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006047812 */
/* 0x000fe200078e4805 */
/*0930*/ BRA 0x970 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0940*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0950*/ BRA 0x970 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0960*/ FADD.FTZ R4, R4, R6 ; /* 0x0000000604047221 */
/* 0x000fe40000010000 */
/*0970*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0980*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0004 */
/*0990*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*09a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*09b0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff64004007950 */
/* 0x000fea0003c3ffff */
/*09c0*/ BRA 0x9c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Assignment 07 Program - moving_average.cu (edited from module 6 for 7)
* Sarah Helble
* 10/16/17
*
* Calculates the average of each index and its neighbors
*
* Usage ./a.out [-v] [-n num_elements] [-b threads_per_block] [-m max_int]
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda.h>
#include <unistd.h>
#define DEFAULT_NUM_ELEMENTS 512
#define DEFAULT_THREADS_PER_BLOCK 256
#define DEFAULT_MAX_INT 30
/**
* Kernel function that takes a moving average of the values in
* @list and puts the results in @averages
* Uses registers to store the calculations.
*/
__global__ void average_window(unsigned int *list, float *averages, int num_elements)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
unsigned int sum;
unsigned int num;
if(idx == 0) {
sum = list[idx] + list[idx+1];
num = 2;
} else if(idx + 1 == num_elements) {
sum = list[idx] + list[idx-1];
num = 2;
} else {
sum = list[idx] + list[idx-1] + list[idx+1];
num = 3;
}
averages[idx] = (float) sum / num;
}
/**
* Fuction to handle the printing of results.
* @list is the original array
* @averages is the result
*/
void print_results(unsigned int *list, float *averages, int num_elements)
{
int i = 0;
printf("\n");
for(i = 0; i < num_elements; i++) {
printf("Original value at index [%d]: %d, average: %f\n", i, list[i], averages[i]);
}
printf("\n");
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_sync(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
cudaEvent_t start, stop;
float duration;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMalloc((void **)&d_list, array_size_in_bytes);
cudaMalloc((void **)&d_averages, float_array_size_in_bytes);
cudaMallocHost((void **)&list, array_size_in_bytes);
cudaMallocHost((void **)&averages, float_array_size_in_bytes);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
cudaEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory */
cudaMemcpy(d_list, list, array_size_in_bytes, cudaMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
cudaMemcpy( averages, d_averages, float_array_size_in_bytes, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
cudaFree(d_list);
cudaFree(d_averages);
/* Free the pinned CPU memory */
cudaFreeHost(list);
cudaFreeHost(averages);
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_async(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
cudaEvent_t start, stop;
float duration;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaStream_t stream;
cudaStreamCreate(&stream);
cudaMalloc((void **)&d_list, array_size_in_bytes);
cudaMalloc((void **)&d_averages, float_array_size_in_bytes);
cudaMallocHost((void **)&list, array_size_in_bytes);
cudaMallocHost((void **)&averages, float_array_size_in_bytes);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
cudaEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory asynchronously */
cudaMemcpyAsync(d_list, list, array_size_in_bytes, cudaMemcpyHostToDevice, stream);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
cudaMemcpyAsync( averages, d_averages, float_array_size_in_bytes, cudaMemcpyDeviceToHost, stream);
cudaStreamSynchronize(stream);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
cudaFree(d_list);
cudaFree(d_averages);
/* Free the pinned CPU memory */
cudaFreeHost(list);
cudaFreeHost(averages);
}
/**
* Entry point for execution. Checks command line arguments
* then passes execution to subordinate function
*/
int main(int argc, char *argv[])
{
int verbosity = 0;
int num_elements = DEFAULT_NUM_ELEMENTS;
int threads_per_block = DEFAULT_THREADS_PER_BLOCK;
int max_int = DEFAULT_MAX_INT;
int c;
while((c = getopt(argc, argv, "vn:b:m:")) != -1) {
switch(c) {
case 'v':
verbosity = 1;
break;
case 'n':
num_elements = atoi(optarg);
break;
case 'b':
threads_per_block = atoi(optarg);
break;
case 'm':
max_int = atoi(optarg);
break;
default:
printf("Error: unrecognized option: %c\n", c);
printf("Usage: %s [-v] [-n num_elements] [-b threads_per_block] [-m max_int]", argv[0]);
exit(-1);
}
}
printf("verbosity: %d\tnum_elements: %d\tthreads_per_block: %d\tmax_int: %d\n",
verbosity, num_elements, threads_per_block, max_int);
/* Do the average with shared memory */
printf("\nFirst Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
/* Do the average with shared memory */
printf("\nFirst Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
return EXIT_SUCCESS;
} | .file "tmpxft_001693ba_00000000-6_moving_average.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Original value at index [%d]: %d, average: %f\n"
.text
.globl _Z13print_resultsPjPfi
.type _Z13print_resultsPjPfi, @function
_Z13print_resultsPjPfi:
.LFB2070:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L4
movslq %ebp, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r14
.L5:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movl (%r12,%rbx,4), %ecx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z13print_resultsPjPfi, .-_Z13print_resultsPjPfi
.globl _Z37__device_stub__Z14average_windowPjPfiPjPfi
.type _Z37__device_stub__Z14average_windowPjPfiPjPfi, @function
_Z37__device_stub__Z14average_windowPjPfiPjPfi:
.LFB2098:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14average_windowPjPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z37__device_stub__Z14average_windowPjPfiPjPfi, .-_Z37__device_stub__Z14average_windowPjPfiPjPfi
.globl _Z14average_windowPjPfi
.type _Z14average_windowPjPfi, @function
_Z14average_windowPjPfi:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14average_windowPjPfiPjPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z14average_windowPjPfi, .-_Z14average_windowPjPfi
.section .rodata.str1.8
.align 8
.LC2:
.string "\tList size: %d, Duration: %fmsn\n"
.text
.globl _Z17exec_kernel_asynciiii
.type _Z17exec_kernel_asynciiii, @function
_Z17exec_kernel_asynciiii:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl %edi, %r15d
movl %esi, %r12d
movl %edx, 12(%rsp)
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movslq %esi, %r13
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaStreamCreate@PLT
leal 0(,%r12,4), %r14d
movslq %r14d, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMallocHost@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMallocHost@PLT
testl %r12d, %r12d
jle .L17
salq $2, %r13
movl $0, %ebx
.L18:
call rand@PLT
movl $0, %edx
divl %ebp
movq 24(%rsp), %rax
movl %edx, (%rax,%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L18
.L17:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %r8
movl $1, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl %r12d, %eax
cltd
idivl 12(%rsp)
movl %eax, %ecx
movl %r12d, %eax
movl $0, %edx
divl %ecx
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl %ecx, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L19:
movq 72(%rsp), %r8
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 72(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
movl %r12d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jne .L25
.L20:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl %r12d, %edx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z37__device_stub__Z14average_windowPjPfiPjPfi
jmp .L19
.L25:
movl %r12d, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z13print_resultsPjPfi
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size _Z17exec_kernel_asynciiii, .-_Z17exec_kernel_asynciiii
.globl _Z16exec_kernel_synciiii
.type _Z16exec_kernel_synciiii, @function
_Z16exec_kernel_synciiii:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %r15d
movl %esi, %r12d
movl %edx, 12(%rsp)
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %esi, %r13
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leal 0(,%r12,4), %r14d
movslq %r14d, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMallocHost@PLT
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMallocHost@PLT
testl %r12d, %r12d
jle .L28
salq $2, %r13
movl $0, %ebx
.L29:
call rand@PLT
movl $0, %edx
divl %ebp
movq 16(%rsp), %rax
movl %edx, (%rax,%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L29
.L28:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
cltd
idivl 12(%rsp)
movl %eax, %ecx
movl %r12d, %eax
movl $0, %edx
divl %ecx
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ecx, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
movl $2, %ecx
movq %r14, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
movl %r12d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jne .L36
.L31:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %r12d, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z14average_windowPjPfiPjPfi
jmp .L30
.L36:
movl %r12d, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z13print_resultsPjPfi
jmp .L31
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size _Z16exec_kernel_synciiii, .-_Z16exec_kernel_synciiii
.section .rodata.str1.8
.align 8
.LC3:
.string "Error: unrecognized option: %c\n"
.align 8
.LC4:
.string "Usage: %s [-v] [-n num_elements] [-b threads_per_block] [-m max_int]"
.section .rodata.str1.1
.LC5:
.string "vn:b:m:"
.section .rodata.str1.8
.align 8
.LC6:
.string "verbosity: %d\tnum_elements: %d\tthreads_per_block: %d\tmax_int: %d\n"
.align 8
.LC7:
.string "\nFirst Run of Averages done synchronously"
.align 8
.LC8:
.string "-----------------------------------------------------------------\n"
.align 8
.LC9:
.string "Second Run of Averages done synchronously"
.align 8
.LC10:
.string "\nFirst Run of Averages done asynchronously"
.align 8
.LC11:
.string "Second Run of Averages done asynchronously"
.text
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebp
movq %rsi, %rbx
movl $30, %r15d
movl $256, %r14d
movl $512, %r13d
movl $0, 12(%rsp)
leaq .LC5(%rip), %r12
jmp .L45
.L41:
movl $1, 12(%rsp)
cmpl $118, %eax
je .L45
.L44:
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L40:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r13d
.L45:
movq %r12, %rdx
movq %rbx, %rsi
movl %ebp, %edi
call getopt@PLT
cmpl $-1, %eax
je .L50
cmpl $110, %eax
je .L40
jg .L41
cmpl $98, %eax
je .L42
cmpl $109, %eax
jne .L44
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r15d
jmp .L45
.L42:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r14d
jmp .L45
.L50:
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movl 12(%rsp), %ebp
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %r14d, %edx
movl %r13d, %esi
movl %ebp, %edi
call _Z16exec_kernel_synciiii
leaq .LC8(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %r14d, %edx
movl %r13d, %esi
movl %ebp, %edi
call _Z16exec_kernel_synciiii
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %r14d, %edx
movl %r13d, %esi
movl %ebp, %edi
call _Z17exec_kernel_asynciiii
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %r14d, %edx
movl %r13d, %esi
movl %ebp, %edi
call _Z17exec_kernel_asynciiii
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z14average_windowPjPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z14average_windowPjPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Assignment 07 Program - moving_average.cu (edited from module 6 for 7)
* Sarah Helble
* 10/16/17
*
* Calculates the average of each index and its neighbors
*
* Usage ./a.out [-v] [-n num_elements] [-b threads_per_block] [-m max_int]
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <cuda.h>
#include <unistd.h>
#define DEFAULT_NUM_ELEMENTS 512
#define DEFAULT_THREADS_PER_BLOCK 256
#define DEFAULT_MAX_INT 30
/**
* Kernel function that takes a moving average of the values in
* @list and puts the results in @averages
* Uses registers to store the calculations.
*/
__global__ void average_window(unsigned int *list, float *averages, int num_elements)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
unsigned int sum;
unsigned int num;
if(idx == 0) {
sum = list[idx] + list[idx+1];
num = 2;
} else if(idx + 1 == num_elements) {
sum = list[idx] + list[idx-1];
num = 2;
} else {
sum = list[idx] + list[idx-1] + list[idx+1];
num = 3;
}
averages[idx] = (float) sum / num;
}
/**
* Fuction to handle the printing of results.
* @list is the original array
* @averages is the result
*/
void print_results(unsigned int *list, float *averages, int num_elements)
{
int i = 0;
printf("\n");
for(i = 0; i < num_elements; i++) {
printf("Original value at index [%d]: %d, average: %f\n", i, list[i], averages[i]);
}
printf("\n");
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_sync(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
cudaEvent_t start, stop;
float duration;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaMalloc((void **)&d_list, array_size_in_bytes);
cudaMalloc((void **)&d_averages, float_array_size_in_bytes);
cudaMallocHost((void **)&list, array_size_in_bytes);
cudaMallocHost((void **)&averages, float_array_size_in_bytes);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
cudaEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory */
cudaMemcpy(d_list, list, array_size_in_bytes, cudaMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
cudaMemcpy( averages, d_averages, float_array_size_in_bytes, cudaMemcpyDeviceToHost);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
cudaFree(d_list);
cudaFree(d_averages);
/* Free the pinned CPU memory */
cudaFreeHost(list);
cudaFreeHost(averages);
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_async(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
cudaEvent_t start, stop;
float duration;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaStream_t stream;
cudaStreamCreate(&stream);
cudaMalloc((void **)&d_list, array_size_in_bytes);
cudaMalloc((void **)&d_averages, float_array_size_in_bytes);
cudaMallocHost((void **)&list, array_size_in_bytes);
cudaMallocHost((void **)&averages, float_array_size_in_bytes);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
cudaEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory asynchronously */
cudaMemcpyAsync(d_list, list, array_size_in_bytes, cudaMemcpyHostToDevice, stream);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
cudaMemcpyAsync( averages, d_averages, float_array_size_in_bytes, cudaMemcpyDeviceToHost, stream);
cudaStreamSynchronize(stream);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
cudaFree(d_list);
cudaFree(d_averages);
/* Free the pinned CPU memory */
cudaFreeHost(list);
cudaFreeHost(averages);
}
/**
* Entry point for execution. Checks command line arguments
* then passes execution to subordinate function
*/
int main(int argc, char *argv[])
{
int verbosity = 0;
int num_elements = DEFAULT_NUM_ELEMENTS;
int threads_per_block = DEFAULT_THREADS_PER_BLOCK;
int max_int = DEFAULT_MAX_INT;
int c;
while((c = getopt(argc, argv, "vn:b:m:")) != -1) {
switch(c) {
case 'v':
verbosity = 1;
break;
case 'n':
num_elements = atoi(optarg);
break;
case 'b':
threads_per_block = atoi(optarg);
break;
case 'm':
max_int = atoi(optarg);
break;
default:
printf("Error: unrecognized option: %c\n", c);
printf("Usage: %s [-v] [-n num_elements] [-b threads_per_block] [-m max_int]", argv[0]);
exit(-1);
}
}
printf("verbosity: %d\tnum_elements: %d\tthreads_per_block: %d\tmax_int: %d\n",
verbosity, num_elements, threads_per_block, max_int);
/* Do the average with shared memory */
printf("\nFirst Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
/* Do the average with shared memory */
printf("\nFirst Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
return EXIT_SUCCESS;
} | /**
* Assignment 07 Program - moving_average.cu (edited from module 6 for 7)
* Sarah Helble
* 10/16/17
*
* Calculates the average of each index and its neighbors
*
* Usage ./a.out [-v] [-n num_elements] [-b threads_per_block] [-m max_int]
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
#define DEFAULT_NUM_ELEMENTS 512
#define DEFAULT_THREADS_PER_BLOCK 256
#define DEFAULT_MAX_INT 30
/**
* Kernel function that takes a moving average of the values in
* @list and puts the results in @averages
* Uses registers to store the calculations.
*/
__global__ void average_window(unsigned int *list, float *averages, int num_elements)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
unsigned int sum;
unsigned int num;
if(idx == 0) {
sum = list[idx] + list[idx+1];
num = 2;
} else if(idx + 1 == num_elements) {
sum = list[idx] + list[idx-1];
num = 2;
} else {
sum = list[idx] + list[idx-1] + list[idx+1];
num = 3;
}
averages[idx] = (float) sum / num;
}
/**
* Fuction to handle the printing of results.
* @list is the original array
* @averages is the result
*/
void print_results(unsigned int *list, float *averages, int num_elements)
{
int i = 0;
printf("\n");
for(i = 0; i < num_elements; i++) {
printf("Original value at index [%d]: %d, average: %f\n", i, list[i], averages[i]);
}
printf("\n");
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_sync(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
hipEvent_t start, stop;
float duration;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMalloc((void **)&d_list, array_size_in_bytes);
hipMalloc((void **)&d_averages, float_array_size_in_bytes);
hipHostMalloc((void **)&list, array_size_in_bytes, hipHostMallocDefault);
hipHostMalloc((void **)&averages, float_array_size_in_bytes, hipHostMallocDefault);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
hipEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory */
hipMemcpy(d_list, list, array_size_in_bytes, hipMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
hipMemcpy( averages, d_averages, float_array_size_in_bytes, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
hipFree(d_list);
hipFree(d_averages);
/* Free the pinned CPU memory */
hipHostFree(list);
hipHostFree(averages);
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_async(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
hipEvent_t start, stop;
float duration;
hipEventCreate(&start);
hipEventCreate(&stop);
hipStream_t stream;
hipStreamCreate(&stream);
hipMalloc((void **)&d_list, array_size_in_bytes);
hipMalloc((void **)&d_averages, float_array_size_in_bytes);
hipHostMalloc((void **)&list, array_size_in_bytes, hipHostMallocDefault);
hipHostMalloc((void **)&averages, float_array_size_in_bytes, hipHostMallocDefault);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
hipEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory asynchronously */
hipMemcpyAsync(d_list, list, array_size_in_bytes, hipMemcpyHostToDevice, stream);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
hipMemcpyAsync( averages, d_averages, float_array_size_in_bytes, hipMemcpyDeviceToHost, stream);
hipStreamSynchronize(stream);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
hipFree(d_list);
hipFree(d_averages);
/* Free the pinned CPU memory */
hipHostFree(list);
hipHostFree(averages);
}
/**
* Entry point for execution. Checks command line arguments
* then passes execution to subordinate function
*/
int main(int argc, char *argv[])
{
int verbosity = 0;
int num_elements = DEFAULT_NUM_ELEMENTS;
int threads_per_block = DEFAULT_THREADS_PER_BLOCK;
int max_int = DEFAULT_MAX_INT;
int c;
while((c = getopt(argc, argv, "vn:b:m:")) != -1) {
switch(c) {
case 'v':
verbosity = 1;
break;
case 'n':
num_elements = atoi(optarg);
break;
case 'b':
threads_per_block = atoi(optarg);
break;
case 'm':
max_int = atoi(optarg);
break;
default:
printf("Error: unrecognized option: %c\n", c);
printf("Usage: %s [-v] [-n num_elements] [-b threads_per_block] [-m max_int]", argv[0]);
exit(-1);
}
}
printf("verbosity: %d\tnum_elements: %d\tthreads_per_block: %d\tmax_int: %d\n",
verbosity, num_elements, threads_per_block, max_int);
/* Do the average with shared memory */
printf("\nFirst Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
/* Do the average with shared memory */
printf("\nFirst Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Assignment 07 Program - moving_average.cu (edited from module 6 for 7)
* Sarah Helble
* 10/16/17
*
* Calculates the average of each index and its neighbors
*
* Usage ./a.out [-v] [-n num_elements] [-b threads_per_block] [-m max_int]
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
#define DEFAULT_NUM_ELEMENTS 512
#define DEFAULT_THREADS_PER_BLOCK 256
#define DEFAULT_MAX_INT 30
/**
* Kernel function that takes a moving average of the values in
* @list and puts the results in @averages
* Uses registers to store the calculations.
*/
__global__ void average_window(unsigned int *list, float *averages, int num_elements)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
unsigned int sum;
unsigned int num;
if(idx == 0) {
sum = list[idx] + list[idx+1];
num = 2;
} else if(idx + 1 == num_elements) {
sum = list[idx] + list[idx-1];
num = 2;
} else {
sum = list[idx] + list[idx-1] + list[idx+1];
num = 3;
}
averages[idx] = (float) sum / num;
}
/**
* Fuction to handle the printing of results.
* @list is the original array
* @averages is the result
*/
void print_results(unsigned int *list, float *averages, int num_elements)
{
int i = 0;
printf("\n");
for(i = 0; i < num_elements; i++) {
printf("Original value at index [%d]: %d, average: %f\n", i, list[i], averages[i]);
}
printf("\n");
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_sync(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
hipEvent_t start, stop;
float duration;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMalloc((void **)&d_list, array_size_in_bytes);
hipMalloc((void **)&d_averages, float_array_size_in_bytes);
hipHostMalloc((void **)&list, array_size_in_bytes, hipHostMallocDefault);
hipHostMalloc((void **)&averages, float_array_size_in_bytes, hipHostMallocDefault);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
hipEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory */
hipMemcpy(d_list, list, array_size_in_bytes, hipMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
hipMemcpy( averages, d_averages, float_array_size_in_bytes, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
hipFree(d_list);
hipFree(d_averages);
/* Free the pinned CPU memory */
hipHostFree(list);
hipHostFree(averages);
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_async(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
hipEvent_t start, stop;
float duration;
hipEventCreate(&start);
hipEventCreate(&stop);
hipStream_t stream;
hipStreamCreate(&stream);
hipMalloc((void **)&d_list, array_size_in_bytes);
hipMalloc((void **)&d_averages, float_array_size_in_bytes);
hipHostMalloc((void **)&list, array_size_in_bytes, hipHostMallocDefault);
hipHostMalloc((void **)&averages, float_array_size_in_bytes, hipHostMallocDefault);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
hipEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory asynchronously */
hipMemcpyAsync(d_list, list, array_size_in_bytes, hipMemcpyHostToDevice, stream);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
hipMemcpyAsync( averages, d_averages, float_array_size_in_bytes, hipMemcpyDeviceToHost, stream);
hipStreamSynchronize(stream);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
hipFree(d_list);
hipFree(d_averages);
/* Free the pinned CPU memory */
hipHostFree(list);
hipHostFree(averages);
}
/**
* Entry point for execution. Checks command line arguments
* then passes execution to subordinate function
*/
int main(int argc, char *argv[])
{
int verbosity = 0;
int num_elements = DEFAULT_NUM_ELEMENTS;
int threads_per_block = DEFAULT_THREADS_PER_BLOCK;
int max_int = DEFAULT_MAX_INT;
int c;
while((c = getopt(argc, argv, "vn:b:m:")) != -1) {
switch(c) {
case 'v':
verbosity = 1;
break;
case 'n':
num_elements = atoi(optarg);
break;
case 'b':
threads_per_block = atoi(optarg);
break;
case 'm':
max_int = atoi(optarg);
break;
default:
printf("Error: unrecognized option: %c\n", c);
printf("Usage: %s [-v] [-n num_elements] [-b threads_per_block] [-m max_int]", argv[0]);
exit(-1);
}
}
printf("verbosity: %d\tnum_elements: %d\tthreads_per_block: %d\tmax_int: %d\n",
verbosity, num_elements, threads_per_block, max_int);
/* Do the average with shared memory */
printf("\nFirst Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
/* Do the average with shared memory */
printf("\nFirst Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
return EXIT_SUCCESS;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14average_windowPjPfi
.globl _Z14average_windowPjPfi
.p2align 8
.type _Z14average_windowPjPfi,@function
_Z14average_windowPjPfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, -1, v1
s_load_b32 s5, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v4, v2
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_clause 0x1
global_load_b32 v0, v[4:5], off
global_load_b32 v2, v[2:3], off
v_add_nc_u32_e32 v4, 1, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s5, v4
s_mov_b32 s5, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
s_and_saveexec_b32 s6, vcc_lo
s_xor_b32 s6, exec_lo, s6
v_mov_b32_e32 v5, 0
s_mov_b32 s5, exec_lo
s_mov_b32 s7, 0x40400000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_or_b32 exec_lo, exec_lo, s6
s_mov_b32 s6, 2.0
s_and_b32 s5, s5, exec_lo
.LBB0_4:
s_or_saveexec_b32 s4, s4
v_mov_b32_e32 v4, s7
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_6
s_load_b32 s7, s[2:3], 0x4
v_mov_b32_e32 v2, s2
v_dual_mov_b32 v4, 2.0 :: v_dual_mov_b32 v3, s3
s_or_b32 s5, s5, exec_lo
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v5, s6
s_and_saveexec_b32 s2, s5
s_cbranch_execz .LBB0_8
global_load_b32 v2, v[2:3], off
v_mov_b32_e32 v5, v4
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v3, v0
s_load_b64 s[0:1], s[0:1], 0x8
v_div_scale_f32 v0, null, v5, v5, v3
v_div_scale_f32 v6, vcc_lo, v3, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v4, 1.0
v_fmac_f32_e32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v4
v_fma_f32 v2, -v0, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v7, v2, v4 :: v_dual_mov_b32 v2, 0
v_fma_f32 v0, -v0, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v0, v4, v7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v4, v5, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14average_windowPjPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14average_windowPjPfi, .Lfunc_end0-_Z14average_windowPjPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14average_windowPjPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14average_windowPjPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Assignment 07 Program - moving_average.cu (edited from module 6 for 7)
* Sarah Helble
* 10/16/17
*
* Calculates the average of each index and its neighbors
*
* Usage ./a.out [-v] [-n num_elements] [-b threads_per_block] [-m max_int]
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <hip/hip_runtime.h>
#include <unistd.h>
#define DEFAULT_NUM_ELEMENTS 512
#define DEFAULT_THREADS_PER_BLOCK 256
#define DEFAULT_MAX_INT 30
/**
* Kernel function that takes a moving average of the values in
* @list and puts the results in @averages
* Uses registers to store the calculations.
*/
__global__ void average_window(unsigned int *list, float *averages, int num_elements)
{
/* Calculate the current index */
const unsigned int idx = (blockIdx.x * blockDim.x) + threadIdx.x;
unsigned int sum;
unsigned int num;
if(idx == 0) {
sum = list[idx] + list[idx+1];
num = 2;
} else if(idx + 1 == num_elements) {
sum = list[idx] + list[idx-1];
num = 2;
} else {
sum = list[idx] + list[idx-1] + list[idx+1];
num = 3;
}
averages[idx] = (float) sum / num;
}
/**
* Fuction to handle the printing of results.
* @list is the original array
* @averages is the result
*/
void print_results(unsigned int *list, float *averages, int num_elements)
{
int i = 0;
printf("\n");
for(i = 0; i < num_elements; i++) {
printf("Original value at index [%d]: %d, average: %f\n", i, list[i], averages[i]);
}
printf("\n");
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_sync(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
hipEvent_t start, stop;
float duration;
hipEventCreate(&start);
hipEventCreate(&stop);
hipMalloc((void **)&d_list, array_size_in_bytes);
hipMalloc((void **)&d_averages, float_array_size_in_bytes);
hipHostMalloc((void **)&list, array_size_in_bytes, hipHostMallocDefault);
hipHostMalloc((void **)&averages, float_array_size_in_bytes, hipHostMallocDefault);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
hipEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory */
hipMemcpy(d_list, list, array_size_in_bytes, hipMemcpyHostToDevice);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
hipMemcpy( averages, d_averages, float_array_size_in_bytes, hipMemcpyDeviceToHost);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
hipFree(d_list);
hipFree(d_averages);
/* Free the pinned CPU memory */
hipHostFree(list);
hipHostFree(averages);
}
/**
* Function that sets up everything for the kernel function
*
* @verbosity is 1 if the function should print detailed results of averages
* verbosity of 0 will only print timing data
*/
void exec_kernel_async(int verbosity, int num_elements, int threads_per_block, int max_int)
{
/* Calculate the size of the array */
int array_size_in_bytes = (sizeof(unsigned int) * (num_elements));
int float_array_size_in_bytes = (sizeof(float) * (num_elements));
int i = 0;
unsigned int *list, *d_list;
float *averages, *d_averages;
hipEvent_t start, stop;
float duration;
hipEventCreate(&start);
hipEventCreate(&stop);
hipStream_t stream;
hipStreamCreate(&stream);
hipMalloc((void **)&d_list, array_size_in_bytes);
hipMalloc((void **)&d_averages, float_array_size_in_bytes);
hipHostMalloc((void **)&list, array_size_in_bytes, hipHostMallocDefault);
hipHostMalloc((void **)&averages, float_array_size_in_bytes, hipHostMallocDefault);
// Fill array with random numbers between 0 and MAX_INT
for(i = 0; i < num_elements; i++) {
list[i] = (unsigned int) rand() % max_int;
}
/* Recording from copy to copy back */
hipEventRecord(start, 0);
/* Copy the CPU memory to the GPU memory asynchronously */
hipMemcpyAsync(d_list, list, array_size_in_bytes, hipMemcpyHostToDevice, stream);
/* Designate the number of blocks and threads */
const unsigned int num_blocks = num_elements/threads_per_block;
const unsigned int num_threads = num_elements/num_blocks;
/* Kernel call */
average_window<<<num_blocks, num_threads>>>(d_list, d_averages, num_elements);
/* Copy the changed GPU memory back to the CPU */
hipMemcpyAsync( averages, d_averages, float_array_size_in_bytes, hipMemcpyDeviceToHost, stream);
hipStreamSynchronize(stream);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&duration, start, stop);
printf("\tList size: %d, Duration: %fmsn\n", num_elements, duration);
if(verbosity) {
print_results(list, averages, num_elements);
}
/* Free the GPU memory */
hipFree(d_list);
hipFree(d_averages);
/* Free the pinned CPU memory */
hipHostFree(list);
hipHostFree(averages);
}
/**
* Entry point for execution. Checks command line arguments
* then passes execution to subordinate function
*/
int main(int argc, char *argv[])
{
int verbosity = 0;
int num_elements = DEFAULT_NUM_ELEMENTS;
int threads_per_block = DEFAULT_THREADS_PER_BLOCK;
int max_int = DEFAULT_MAX_INT;
int c;
while((c = getopt(argc, argv, "vn:b:m:")) != -1) {
switch(c) {
case 'v':
verbosity = 1;
break;
case 'n':
num_elements = atoi(optarg);
break;
case 'b':
threads_per_block = atoi(optarg);
break;
case 'm':
max_int = atoi(optarg);
break;
default:
printf("Error: unrecognized option: %c\n", c);
printf("Usage: %s [-v] [-n num_elements] [-b threads_per_block] [-m max_int]", argv[0]);
exit(-1);
}
}
printf("verbosity: %d\tnum_elements: %d\tthreads_per_block: %d\tmax_int: %d\n",
verbosity, num_elements, threads_per_block, max_int);
/* Do the average with shared memory */
printf("\nFirst Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done synchronously");
exec_kernel_sync(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
/* Do the average with shared memory */
printf("\nFirst Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
printf("Second Run of Averages done asynchronously");
exec_kernel_async(verbosity, num_elements, threads_per_block, max_int);
printf("-----------------------------------------------------------------\n");
return EXIT_SUCCESS;
} | .text
.file "moving_average.hip"
.globl _Z29__device_stub__average_windowPjPfi # -- Begin function _Z29__device_stub__average_windowPjPfi
.p2align 4, 0x90
.type _Z29__device_stub__average_windowPjPfi,@function
_Z29__device_stub__average_windowPjPfi: # @_Z29__device_stub__average_windowPjPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14average_windowPjPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__average_windowPjPfi, .Lfunc_end0-_Z29__device_stub__average_windowPjPfi
.cfi_endproc
# -- End function
.globl _Z13print_resultsPjPfi # -- Begin function _Z13print_resultsPjPfi
.p2align 4, 0x90
.type _Z13print_resultsPjPfi,@function
_Z13print_resultsPjPfi: # @_Z13print_resultsPjPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %edx
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB1_2
.LBB1_3: # %._crit_edge
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z13print_resultsPjPfi, .Lfunc_end1-_Z13print_resultsPjPfi
.cfi_endproc
# -- End function
.globl _Z16exec_kernel_synciiii # -- Begin function _Z16exec_kernel_synciiii
.p2align 4, 0x90
.type _Z16exec_kernel_synciiii,@function
_Z16exec_kernel_synciiii: # @_Z16exec_kernel_synciiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movl %edx, %r15d
movl %esi, %ebx
movl %edi, 48(%rsp) # 4-byte Spill
leal (,%rbx,4), %ebp
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movslq %ebp, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
movl %ebx, %r13d
testl %ebx, %ebx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorl %edx, %edx
divl %r12d
movq 8(%rsp), %rax
movl %edx, (%rax,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebx, %eax
cltd
idivl %r15d
movl %eax, %edi
movl %ebx, %eax
xorl %edx, %edx
divl %edi
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %ebx, 52(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 72(%rsp)
leaq 52(%rsp), %rax
movq %rax, 80(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14average_windowPjPfi, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl %ebx, %esi
movb $1, %al
callq printf
cmpl $0, 48(%rsp) # 4-byte Folded Reload
je .LBB2_10
# %bb.6:
movq 8(%rsp), %r14
movq 32(%rsp), %r15
movl $10, %edi
callq putchar@PLT
testl %ebx, %ebx
jle .LBB2_9
# %bb.7: # %.lr.ph.preheader.i
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_8: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %edx
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB2_8
.LBB2_9: # %_Z13print_resultsPjPfi.exit
movl $10, %edi
callq putchar@PLT
.LBB2_10:
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z16exec_kernel_synciiii, .Lfunc_end2-_Z16exec_kernel_synciiii
.cfi_endproc
# -- End function
.globl _Z17exec_kernel_asynciiii # -- Begin function _Z17exec_kernel_asynciiii
.p2align 4, 0x90
.type _Z17exec_kernel_asynciiii,@function
_Z17exec_kernel_asynciiii: # @_Z17exec_kernel_asynciiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movl %edx, %r15d
movl %esi, %ebx
movl %edi, 48(%rsp) # 4-byte Spill
leal (,%rbx,4), %ebp
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipStreamCreate
movslq %ebp, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
movl %ebx, %r13d
testl %ebx, %ebx
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorl %edx, %edx
divl %r12d
movq (%rsp), %rax
movl %edx, (%rax,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
movq (%rsp), %rsi
movq 8(%rsp), %r8
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movl %ebx, %eax
cltd
idivl %r15d
movl %eax, %edi
movl %ebx, %eax
xorl %edx, %edx
divl %edi
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %ebx, 52(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 72(%rsp)
leaq 52(%rsp), %rax
movq %rax, 80(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14average_windowPjPfi, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %r8
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rdi
callq hipStreamSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl %ebx, %esi
movb $1, %al
callq printf
cmpl $0, 48(%rsp) # 4-byte Folded Reload
je .LBB3_10
# %bb.6:
movq (%rsp), %r14
movq 32(%rsp), %r15
movl $10, %edi
callq putchar@PLT
testl %ebx, %ebx
jle .LBB3_9
# %bb.7: # %.lr.ph.preheader.i
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_8: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %edx
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB3_8
.LBB3_9: # %_Z13print_resultsPjPfi.exit
movl $10, %edi
callq putchar@PLT
.LBB3_10:
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17exec_kernel_asynciiii, .Lfunc_end3-_Z17exec_kernel_asynciiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r13
movl %edi, %ebp
xorl %ebx, %ebx
movl $30, %r14d
movl $256, %r15d # imm = 0x100
movl $512, %r12d # imm = 0x200
.LBB4_1: # %.outer53
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
movl %ebx, %ecx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %ebx
movl $.L.str.3, %edx
movl %ebp, %edi
movq %r13, %rsi
callq getopt
movl $1, %ecx
cmpl $118, %eax
je .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
cmpl $108, %eax
jg .LBB4_7
# %bb.4: # in Loop: Header=BB4_1 Depth=1
cmpl $-1, %eax
je .LBB4_12
# %bb.5: # in Loop: Header=BB4_1 Depth=1
cmpl $98, %eax
jne .LBB4_11
# %bb.6: # in Loop: Header=BB4_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_1 Depth=1
cmpl $109, %eax
je .LBB4_10
# %bb.8: # in Loop: Header=BB4_1 Depth=1
cmpl $110, %eax
jne .LBB4_11
# %bb.9: # in Loop: Header=BB4_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_10: # in Loop: Header=BB4_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB4_1
.LBB4_12:
movl $.L.str.6, %edi
movl %ebx, %esi
movl %r12d, %edx
movl %r15d, %ecx
movl %r14d, %r8d
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl %ebx, %edi
movl %r12d, %esi
movl %r15d, %edx
movl %r14d, %ecx
callq _Z16exec_kernel_synciiii
movl $.Lstr.3, %edi
callq puts@PLT
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl %ebx, %edi
movl %r12d, %esi
movl %r15d, %edx
movl %r14d, %ecx
callq _Z16exec_kernel_synciiii
movl $.Lstr.3, %edi
callq puts@PLT
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl %ebx, %edi
movl %r12d, %esi
movl %r15d, %edx
movl %r14d, %ecx
callq _Z17exec_kernel_asynciiii
movl $.Lstr.3, %edi
callq puts@PLT
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl %ebx, %edi
movl %r12d, %esi
movl %r15d, %edx
movl %r14d, %ecx
callq _Z17exec_kernel_asynciiii
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 64
movl $.L.str.4, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movq (%r13), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14average_windowPjPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14average_windowPjPfi,@object # @_Z14average_windowPjPfi
.section .rodata,"a",@progbits
.globl _Z14average_windowPjPfi
.p2align 3, 0x0
_Z14average_windowPjPfi:
.quad _Z29__device_stub__average_windowPjPfi
.size _Z14average_windowPjPfi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Original value at index [%d]: %d, average: %f\n"
.size .L.str.1, 47
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\tList size: %d, Duration: %fmsn\n"
.size .L.str.2, 33
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "vn:b:m:"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error: unrecognized option: %c\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Usage: %s [-v] [-n num_elements] [-b threads_per_block] [-m max_int]"
.size .L.str.5, 69
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "verbosity: %d\tnum_elements: %d\tthreads_per_block: %d\tmax_int: %d\n"
.size .L.str.6, 66
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\nFirst Run of Averages done synchronously"
.size .L.str.7, 42
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Second Run of Averages done synchronously"
.size .L.str.9, 42
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nFirst Run of Averages done asynchronously"
.size .L.str.10, 43
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Second Run of Averages done asynchronously"
.size .L.str.11, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14average_windowPjPfi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.3,@object # @str.3
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.3:
.asciz "-----------------------------------------------------------------"
.size .Lstr.3, 66
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__average_windowPjPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14average_windowPjPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14average_windowPjPfi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x210 ; /* 0x000001d000007945 */
/* 0x000fe20003800000 */
/*0040*/ IMAD.MOV.U32 R6, RZ, RZ, 0x40000000 ; /* 0x40000000ff067424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0080*/ @!P0 BRA 0x1a0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe20007ffe0ff */
/*00a0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*00b0*/ IMAD.WIDE.U32 R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0009 */
/*00c0*/ IMAD.WIDE.U32 R2, R0.reuse, R9, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x040fe400078e0009 */
/*00d0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*00f0*/ IADD3 R7, R0, 0x1, RZ ; /* 0x0000000100077810 */
/* 0x000fc80007ffe0ff */
/*0100*/ ISETP.NE.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe20003f05270 */
/*0110*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0000 */
/*0120*/ IMAD.IADD R8, R4, 0x1, R3 ; /* 0x0000000104087824 */
/* 0x004fe400078e0203 */
/*0130*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fd000078e00ff */
/*0140*/ @!P0 BRA 0x200 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.WIDE.U32 R4, R7, R9, c[0x0][0x160] ; /* 0x0000580007047625 */
/* 0x000fcc00078e0009 */
/*0160*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, 0x40400000 ; /* 0x40400000ff067424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.IADD R8, R8, 0x1, R5 ; /* 0x0000000108087824 */
/* 0x004fe200078e0205 */
/*0190*/ BRA 0x200 ; /* 0x0000006000007947 */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff047624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fca00078e00ff */
/*01c0*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R7, [R4.64+0x4] ; /* 0x0000040404077981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*01f0*/ IMAD.IADD R8, R8, 0x1, R7 ; /* 0x0000000108087824 */
/* 0x004fe400078e0207 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ I2F.U32 R9, R8 ; /* 0x0000000800097306 */
/* 0x000e220000201000 */
/*0220*/ BSSY B0, 0x2e0 ; /* 0x000000b000007945 */
/* 0x000fee0003800000 */
/*0230*/ MUFU.RCP R5, R6 ; /* 0x0000000600057308 */
/* 0x000e700000001000 */
/*0240*/ FCHK P0, R9, R6 ; /* 0x0000000609007302 */
/* 0x001e220000000000 */
/*0250*/ FFMA R0, R5, -R6, 1 ; /* 0x3f80000005007423 */
/* 0x002fc80000000806 */
/*0260*/ FFMA R0, R5, R0, R5 ; /* 0x0000000005007223 */
/* 0x000fc80000000005 */
/*0270*/ FFMA R5, R9, R0, RZ ; /* 0x0000000009057223 */
/* 0x000fc800000000ff */
/*0280*/ FFMA R4, R5, -R6, R9 ; /* 0x8000000605047223 */
/* 0x000fc80000000009 */
/*0290*/ FFMA R7, R0, R4, R5 ; /* 0x0000000400077223 */
/* 0x000fe20000000005 */
/*02a0*/ @!P0 BRA 0x2d0 ; /* 0x0000002000008947 */
/* 0x001fea0003800000 */
/*02b0*/ MOV R0, 0x2d0 ; /* 0x000002d000007802 */
/* 0x000fe40000000f00 */
/*02c0*/ CALL.REL.NOINC 0x320 ; /* 0x0000005000007944 */
/* 0x000fea0003c00000 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*02f0*/ LEA.HI.X R5, R2, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f1403 */
/*0300*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ SHF.R.U32.HI R5, RZ, 0x17, R6 ; /* 0x00000017ff057819 */
/* 0x000fe20000011606 */
/*0330*/ BSSY B1, 0x980 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0340*/ SHF.R.U32.HI R4, RZ, 0x17, R9.reuse ; /* 0x00000017ff047819 */
/* 0x100fe40000011609 */
/*0350*/ LOP3.LUT R13, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff050d7812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.MOV.U32 R5, RZ, RZ, R9 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0009 */
/*0370*/ LOP3.LUT R10, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff040a7812 */
/* 0x000fe400078ec0ff */
/*0380*/ IADD3 R11, R13, -0x1, RZ ; /* 0xffffffff0d0b7810 */
/* 0x000fe40007ffe0ff */
/*0390*/ IADD3 R8, R10, -0x1, RZ ; /* 0xffffffff0a087810 */
/* 0x000fc40007ffe0ff */
/*03a0*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*03b0*/ ISETP.GT.U32.OR P0, PT, R8, 0xfd, P0 ; /* 0x000000fd0800780c */
/* 0x000fda0000704470 */
/*03c0*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff078224 */
/* 0x000fe200078e00ff */
/*03d0*/ @!P0 BRA 0x560 ; /* 0x0000018000008947 */
/* 0x000fea0003800000 */
/*03e0*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe20003f3c200 */
/*03f0*/ IMAD.MOV.U32 R4, RZ, RZ, R9 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0009 */
/*0400*/ FSETP.GTU.FTZ.AND P0, PT, |R9|, +INF , PT ; /* 0x7f8000000900780b */
/* 0x000fc80003f1c200 */
/*0410*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0420*/ @P0 BRA 0x960 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0430*/ LOP3.LUT P0, RZ, R6, 0x7fffffff, R5, 0xc8, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fda000780c805 */
/*0440*/ @!P0 BRA 0x940 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0450*/ FSETP.NEU.FTZ.AND P2, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f5d200 */
/*0460*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*0470*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0480*/ @!P1 BRA !P2, 0x940 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0490*/ LOP3.LUT P2, RZ, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05ff7812 */
/* 0x000fc8000784c0ff */
/*04a0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*04b0*/ @P1 BRA 0x920 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*04c0*/ LOP3.LUT P1, RZ, R6, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff06ff7812 */
/* 0x000fc8000782c0ff */
/*04d0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*04e0*/ @P0 BRA 0x8f0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*04f0*/ ISETP.GE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f06270 */
/*0500*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*0510*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff070224 */
/* 0x000fe400078e00ff */
/*0520*/ @!P0 IMAD.MOV.U32 R7, RZ, RZ, -0x40 ; /* 0xffffffc0ff078424 */
/* 0x000fe400078e00ff */
/*0530*/ @!P0 FFMA R5, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004058823 */
/* 0x000fe400000000ff */
/*0540*/ @!P1 FFMA R6, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006069823 */
/* 0x000fe200000000ff */
/*0550*/ @!P1 IADD3 R7, R7, 0x40, RZ ; /* 0x0000004007079810 */
/* 0x000fe40007ffe0ff */
/*0560*/ LEA R9, R13, 0xc0800000, 0x17 ; /* 0xc08000000d097811 */
/* 0x000fe200078eb8ff */
/*0570*/ BSSY B2, 0x8e0 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0580*/ IMAD.IADD R9, R6, 0x1, -R9 ; /* 0x0000000106097824 */
/* 0x000fe200078e0a09 */
/*0590*/ IADD3 R6, R10, -0x7f, RZ ; /* 0xffffff810a067810 */
/* 0x000fc60007ffe0ff */
/*05a0*/ MUFU.RCP R4, R9 ; /* 0x0000000900047308 */
/* 0x000e220000001000 */
/*05b0*/ FADD.FTZ R8, -R9, -RZ ; /* 0x800000ff09087221 */
/* 0x000fe40000010100 */
/*05c0*/ IMAD R5, R6.reuse, -0x800000, R5 ; /* 0xff80000006057824 */
/* 0x040fe200078e0205 */
/*05d0*/ IADD3 R6, R6, 0x7f, -R13 ; /* 0x0000007f06067810 */
/* 0x000fca0007ffe80d */
/*05e0*/ IMAD.IADD R6, R6, 0x1, R7 ; /* 0x0000000106067824 */
/* 0x000fe400078e0207 */
/*05f0*/ FFMA R11, R4, R8, 1 ; /* 0x3f800000040b7423 */
/* 0x001fc80000000008 */
/*0600*/ FFMA R10, R4, R11, R4 ; /* 0x0000000b040a7223 */
/* 0x000fc80000000004 */
/*0610*/ FFMA R4, R5, R10, RZ ; /* 0x0000000a05047223 */
/* 0x000fc800000000ff */
/*0620*/ FFMA R11, R8, R4, R5 ; /* 0x00000004080b7223 */
/* 0x000fc80000000005 */
/*0630*/ FFMA R11, R10, R11, R4 ; /* 0x0000000b0a0b7223 */
/* 0x000fc80000000004 */
/*0640*/ FFMA R8, R8, R11, R5 ; /* 0x0000000b08087223 */
/* 0x000fc80000000005 */
/*0650*/ FFMA R4, R10, R8, R11 ; /* 0x000000080a047223 */
/* 0x000fca000000000b */
/*0660*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*0670*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*0680*/ IMAD.IADD R9, R5, 0x1, R6 ; /* 0x0000000105097824 */
/* 0x000fca00078e0206 */
/*0690*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*06a0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*06b0*/ @!P0 BRA 0x8c0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*06c0*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*06d0*/ @P0 BRA 0x890 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*06e0*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*06f0*/ @P0 BRA 0x8d0 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0700*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0710*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0720*/ @!P0 BRA 0x8d0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0730*/ FFMA.RZ R5, R10.reuse, R8.reuse, R11.reuse ; /* 0x000000080a057223 */
/* 0x1c0fe2000000c00b */
/*0740*/ ISETP.NE.AND P2, PT, R9.reuse, RZ, PT ; /* 0x000000ff0900720c */
/* 0x040fe20003f45270 */
/*0750*/ FFMA.RM R6, R10.reuse, R8.reuse, R11.reuse ; /* 0x000000080a067223 */
/* 0x1c0fe2000000400b */
/*0760*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0770*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*0780*/ FFMA.RP R5, R10, R8, R11 ; /* 0x000000080a057223 */
/* 0x000fe2000000800b */
/*0790*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*07a0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*07b0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*07c0*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*07d0*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*07e0*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*07f0*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0800*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0810*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0820*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0830*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0840*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0850*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*0860*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*0870*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*0880*/ BRA 0x8d0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0890*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*08a0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*08b0*/ BRA 0x8d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08c0*/ IMAD R4, R6, 0x800000, R4 ; /* 0x0080000006047824 */
/* 0x000fe400078e0204 */
/*08d0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*08e0*/ BRA 0x970 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*08f0*/ LOP3.LUT R4, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006047812 */
/* 0x000fc800078e4805 */
/*0900*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0910*/ BRA 0x970 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0920*/ LOP3.LUT R4, R6, 0x80000000, R5, 0x48, !PT ; /* 0x8000000006047812 */
/* 0x000fe200078e4805 */
/*0930*/ BRA 0x970 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0940*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0950*/ BRA 0x970 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0960*/ FADD.FTZ R4, R4, R6 ; /* 0x0000000604047221 */
/* 0x000fe40000010000 */
/*0970*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0980*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0004 */
/*0990*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*09a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*09b0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff64004007950 */
/* 0x000fea0003c3ffff */
/*09c0*/ BRA 0x9c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14average_windowPjPfi
.globl _Z14average_windowPjPfi
.p2align 8
.type _Z14average_windowPjPfi,@function
_Z14average_windowPjPfi:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s4, exec_lo
v_cmpx_ne_u32_e32 0, v1
s_xor_b32 s4, exec_lo, s4
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, -1, v1
s_load_b32 s5, s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mov_b32_e32 v4, v2
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_clause 0x1
global_load_b32 v0, v[4:5], off
global_load_b32 v2, v[2:3], off
v_add_nc_u32_e32 v4, 1, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s5, v4
s_mov_b32 s5, 0
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v2, v0
s_and_saveexec_b32 s6, vcc_lo
s_xor_b32 s6, exec_lo, s6
v_mov_b32_e32 v5, 0
s_mov_b32 s5, exec_lo
s_mov_b32 s7, 0x40400000
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_or_b32 exec_lo, exec_lo, s6
s_mov_b32 s6, 2.0
s_and_b32 s5, s5, exec_lo
.LBB0_4:
s_or_saveexec_b32 s4, s4
v_mov_b32_e32 v4, s7
s_xor_b32 exec_lo, exec_lo, s4
s_cbranch_execz .LBB0_6
s_load_b32 s7, s[2:3], 0x4
v_mov_b32_e32 v2, s2
v_dual_mov_b32 v4, 2.0 :: v_dual_mov_b32 v3, s3
s_or_b32 s5, s5, exec_lo
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s7
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v5, s6
s_and_saveexec_b32 s2, s5
s_cbranch_execz .LBB0_8
global_load_b32 v2, v[2:3], off
v_mov_b32_e32 v5, v4
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v0, v2
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v3, v0
s_load_b64 s[0:1], s[0:1], 0x8
v_div_scale_f32 v0, null, v5, v5, v3
v_div_scale_f32 v6, vcc_lo, v3, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v0
s_waitcnt_depctr 0xfff
v_fma_f32 v2, -v0, v4, 1.0
v_fmac_f32_e32 v4, v2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v4
v_fma_f32 v2, -v0, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_fmac_f32 v7, v2, v4 :: v_dual_mov_b32 v2, 0
v_fma_f32 v0, -v0, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v0, v4, v7
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f32 v2, v4, v5, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14average_windowPjPfi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14average_windowPjPfi, .Lfunc_end0-_Z14average_windowPjPfi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14average_windowPjPfi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14average_windowPjPfi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001693ba_00000000-6_moving_average.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2076:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2076:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Original value at index [%d]: %d, average: %f\n"
.text
.globl _Z13print_resultsPjPfi
.type _Z13print_resultsPjPfi, @function
_Z13print_resultsPjPfi:
.LFB2070:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r12
movq %rsi, %r13
movl %edx, %ebp
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebp, %ebp
jle .L4
movslq %ebp, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r14
.L5:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx,4), %xmm0
movl (%r12,%rbx,4), %ecx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L5
.L4:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2070:
.size _Z13print_resultsPjPfi, .-_Z13print_resultsPjPfi
.globl _Z37__device_stub__Z14average_windowPjPfiPjPfi
.type _Z37__device_stub__Z14average_windowPjPfiPjPfi, @function
_Z37__device_stub__Z14average_windowPjPfiPjPfi:
.LFB2098:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14average_windowPjPfi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2098:
.size _Z37__device_stub__Z14average_windowPjPfiPjPfi, .-_Z37__device_stub__Z14average_windowPjPfiPjPfi
.globl _Z14average_windowPjPfi
.type _Z14average_windowPjPfi, @function
_Z14average_windowPjPfi:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z14average_windowPjPfiPjPfi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _Z14average_windowPjPfi, .-_Z14average_windowPjPfi
.section .rodata.str1.8
.align 8
.LC2:
.string "\tList size: %d, Duration: %fmsn\n"
.text
.globl _Z17exec_kernel_asynciiii
.type _Z17exec_kernel_asynciiii, @function
_Z17exec_kernel_asynciiii:
.LFB2072:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movl %edi, %r15d
movl %esi, %r12d
movl %edx, 12(%rsp)
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movslq %esi, %r13
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaStreamCreate@PLT
leal 0(,%r12,4), %r14d
movslq %r14d, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMallocHost@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMallocHost@PLT
testl %r12d, %r12d
jle .L17
salq $2, %r13
movl $0, %ebx
.L18:
call rand@PLT
movl $0, %edx
divl %ebp
movq 24(%rsp), %rax
movl %edx, (%rax,%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L18
.L17:
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 72(%rsp), %r8
movl $1, %ecx
movq %r14, %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpyAsync@PLT
movl %r12d, %eax
cltd
idivl 12(%rsp)
movl %eax, %ecx
movl %r12d, %eax
movl $0, %edx
divl %ecx
movl %eax, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl %ecx, 80(%rsp)
movl $1, 84(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 92(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L19:
movq 72(%rsp), %r8
movl $2, %ecx
movq %r14, %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 72(%rsp), %rdi
call cudaStreamSynchronize@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movq 64(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 92(%rsp), %rdi
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 92(%rsp), %xmm0
movl %r12d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jne .L25
.L20:
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFreeHost@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L26
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl %r12d, %edx
movq 48(%rsp), %rsi
movq 32(%rsp), %rdi
call _Z37__device_stub__Z14average_windowPjPfiPjPfi
jmp .L19
.L25:
movl %r12d, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z13print_resultsPjPfi
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2072:
.size _Z17exec_kernel_asynciiii, .-_Z17exec_kernel_asynciiii
.globl _Z16exec_kernel_synciiii
.type _Z16exec_kernel_synciiii, @function
_Z16exec_kernel_synciiii:
.LFB2071:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %r15d
movl %esi, %r12d
movl %edx, 12(%rsp)
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movslq %esi, %r13
leaq 48(%rsp), %rdi
call cudaEventCreate@PLT
leaq 56(%rsp), %rdi
call cudaEventCreate@PLT
leal 0(,%r12,4), %r14d
movslq %r14d, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r14, %rsi
call cudaMallocHost@PLT
leaq 32(%rsp), %rdi
movq %r14, %rsi
call cudaMallocHost@PLT
testl %r12d, %r12d
jle .L28
salq $2, %r13
movl $0, %ebx
.L29:
call rand@PLT
movl $0, %edx
divl %ebp
movq 16(%rsp), %rax
movl %edx, (%rax,%rbx)
addq $4, %rbx
cmpq %r13, %rbx
jne .L29
.L28:
movl $0, %esi
movq 48(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
cltd
idivl 12(%rsp)
movl %eax, %ecx
movl %r12d, %eax
movl $0, %edx
divl %ecx
movl %eax, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl %ecx, 64(%rsp)
movl $1, 68(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
movl $2, %ecx
movq %r14, %rdx
movq 40(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 56(%rsp), %rdi
call cudaEventRecord@PLT
movq 56(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 76(%rsp), %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 76(%rsp), %xmm0
movl %r12d, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testl %r15d, %r15d
jne .L36
.L31:
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFreeHost@PLT
movq 32(%rsp), %rdi
call cudaFreeHost@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl %r12d, %edx
movq 40(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z37__device_stub__Z14average_windowPjPfiPjPfi
jmp .L30
.L36:
movl %r12d, %edx
movq 32(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z13print_resultsPjPfi
jmp .L31
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size _Z16exec_kernel_synciiii, .-_Z16exec_kernel_synciiii
.section .rodata.str1.8
.align 8
.LC3:
.string "Error: unrecognized option: %c\n"
.align 8
.LC4:
.string "Usage: %s [-v] [-n num_elements] [-b threads_per_block] [-m max_int]"
.section .rodata.str1.1
.LC5:
.string "vn:b:m:"
.section .rodata.str1.8
.align 8
.LC6:
.string "verbosity: %d\tnum_elements: %d\tthreads_per_block: %d\tmax_int: %d\n"
.align 8
.LC7:
.string "\nFirst Run of Averages done synchronously"
.align 8
.LC8:
.string "-----------------------------------------------------------------\n"
.align 8
.LC9:
.string "Second Run of Averages done synchronously"
.align 8
.LC10:
.string "\nFirst Run of Averages done asynchronously"
.align 8
.LC11:
.string "Second Run of Averages done asynchronously"
.text
.globl main
.type main, @function
main:
.LFB2073:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl %edi, %ebp
movq %rsi, %rbx
movl $30, %r15d
movl $256, %r14d
movl $512, %r13d
movl $0, 12(%rsp)
leaq .LC5(%rip), %r12
jmp .L45
.L41:
movl $1, 12(%rsp)
cmpl $118, %eax
je .L45
.L44:
movl %eax, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rbx), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L40:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r13d
.L45:
movq %r12, %rdx
movq %rbx, %rsi
movl %ebp, %edi
call getopt@PLT
cmpl $-1, %eax
je .L50
cmpl $110, %eax
je .L40
jg .L41
cmpl $98, %eax
je .L42
cmpl $109, %eax
jne .L44
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r15d
jmp .L45
.L42:
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %r14d
jmp .L45
.L50:
movl %r15d, %r9d
movl %r14d, %r8d
movl %r13d, %ecx
movl 12(%rsp), %ebp
movl %ebp, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %r14d, %edx
movl %r13d, %esi
movl %ebp, %edi
call _Z16exec_kernel_synciiii
leaq .LC8(%rip), %rbx
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %r14d, %edx
movl %r13d, %esi
movl %ebp, %edi
call _Z16exec_kernel_synciiii
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %r14d, %edx
movl %r13d, %esi
movl %ebp, %edi
call _Z17exec_kernel_asynciiii
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r15d, %ecx
movl %r14d, %edx
movl %r13d, %esi
movl %ebp, %edi
call _Z17exec_kernel_asynciiii
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z14average_windowPjPfi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2101:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z14average_windowPjPfi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2101:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "moving_average.hip"
.globl _Z29__device_stub__average_windowPjPfi # -- Begin function _Z29__device_stub__average_windowPjPfi
.p2align 4, 0x90
.type _Z29__device_stub__average_windowPjPfi,@function
_Z29__device_stub__average_windowPjPfi: # @_Z29__device_stub__average_windowPjPfi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14average_windowPjPfi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__average_windowPjPfi, .Lfunc_end0-_Z29__device_stub__average_windowPjPfi
.cfi_endproc
# -- End function
.globl _Z13print_resultsPjPfi # -- Begin function _Z13print_resultsPjPfi
.p2align 4, 0x90
.type _Z13print_resultsPjPfi,@function
_Z13print_resultsPjPfi: # @_Z13print_resultsPjPfi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movq %rsi, %rbx
movq %rdi, %r14
movl $10, %edi
callq putchar@PLT
testl %ebp, %ebp
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
movl %ebp, %r12d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %edx
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %r15d, %esi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB1_2
.LBB1_3: # %._crit_edge
movl $10, %edi
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z13print_resultsPjPfi, .Lfunc_end1-_Z13print_resultsPjPfi
.cfi_endproc
# -- End function
.globl _Z16exec_kernel_synciiii # -- Begin function _Z16exec_kernel_synciiii
.p2align 4, 0x90
.type _Z16exec_kernel_synciiii,@function
_Z16exec_kernel_synciiii: # @_Z16exec_kernel_synciiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movl %edx, %r15d
movl %esi, %ebx
movl %edi, 48(%rsp) # 4-byte Spill
leal (,%rbx,4), %ebp
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
movslq %ebp, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
movl %ebx, %r13d
testl %ebx, %ebx
jle .LBB2_3
# %bb.1: # %.lr.ph.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorl %edx, %edx
divl %r12d
movq 8(%rsp), %rax
movl %edx, (%rax,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB2_2
.LBB2_3: # %._crit_edge
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
movq 8(%rsp), %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %ebx, %eax
cltd
idivl %r15d
movl %eax, %edi
movl %ebx, %eax
xorl %edx, %edx
divl %edi
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_5
# %bb.4:
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %ebx, 52(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 72(%rsp)
leaq 52(%rsp), %rax
movq %rax, 80(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14average_windowPjPfi, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_5:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl %ebx, %esi
movb $1, %al
callq printf
cmpl $0, 48(%rsp) # 4-byte Folded Reload
je .LBB2_10
# %bb.6:
movq 8(%rsp), %r14
movq 32(%rsp), %r15
movl $10, %edi
callq putchar@PLT
testl %ebx, %ebx
jle .LBB2_9
# %bb.7: # %.lr.ph.preheader.i
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_8: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %edx
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB2_8
.LBB2_9: # %_Z13print_resultsPjPfi.exit
movl $10, %edi
callq putchar@PLT
.LBB2_10:
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z16exec_kernel_synciiii, .Lfunc_end2-_Z16exec_kernel_synciiii
.cfi_endproc
# -- End function
.globl _Z17exec_kernel_asynciiii # -- Begin function _Z17exec_kernel_asynciiii
.p2align 4, 0x90
.type _Z17exec_kernel_asynciiii,@function
_Z17exec_kernel_asynciiii: # @_Z17exec_kernel_asynciiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %r12d
movl %edx, %r15d
movl %esi, %ebx
movl %edi, 48(%rsp) # 4-byte Spill
leal (,%rbx,4), %ebp
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipStreamCreate
movslq %ebp, %r14
leaq 40(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
leaq 32(%rsp), %rdi
movq %r14, %rsi
xorl %edx, %edx
callq hipHostMalloc
movl %ebx, %r13d
testl %ebx, %ebx
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
xorl %edx, %edx
divl %r12d
movq (%rsp), %rax
movl %edx, (%rax,%rbp,4)
incq %rbp
cmpq %rbp, %r13
jne .LBB3_2
.LBB3_3: # %._crit_edge
movq 56(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 40(%rsp), %rdi
movq (%rsp), %rsi
movq 8(%rsp), %r8
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpyAsync
movl %ebx, %eax
cltd
idivl %r15d
movl %eax, %edi
movl %ebx, %eax
xorl %edx, %edx
divl %edi
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq 40(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 144(%rsp)
movq %rcx, 136(%rsp)
movl %ebx, 52(%rsp)
leaq 144(%rsp), %rax
movq %rax, 64(%rsp)
leaq 136(%rsp), %rax
movq %rax, 72(%rsp)
leaq 52(%rsp), %rax
movq %rax, 80(%rsp)
leaq 120(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 120(%rsp), %rsi
movl 128(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14average_windowPjPfi, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
movq 32(%rsp), %rdi
movq 24(%rsp), %rsi
movq 8(%rsp), %r8
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rdi
callq hipStreamSynchronize
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 16(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movl %ebx, %esi
movb $1, %al
callq printf
cmpl $0, 48(%rsp) # 4-byte Folded Reload
je .LBB3_10
# %bb.6:
movq (%rsp), %r14
movq 32(%rsp), %r15
movl $10, %edi
callq putchar@PLT
testl %ebx, %ebx
jle .LBB3_9
# %bb.7: # %.lr.ph.preheader.i
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_8: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%rbx,4), %edx
movss (%r15,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movl %ebx, %esi
movb $1, %al
callq printf
incq %rbx
cmpq %rbx, %r13
jne .LBB3_8
.LBB3_9: # %_Z13print_resultsPjPfi.exit
movl $10, %edi
callq putchar@PLT
.LBB3_10:
movq 40(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipHostFree
movq 32(%rsp), %rdi
callq hipHostFree
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z17exec_kernel_asynciiii, .Lfunc_end3-_Z17exec_kernel_asynciiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r13
movl %edi, %ebp
xorl %ebx, %ebx
movl $30, %r14d
movl $256, %r15d # imm = 0x100
movl $512, %r12d # imm = 0x200
.LBB4_1: # %.outer53
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
movl %ebx, %ecx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl %ecx, %ebx
movl $.L.str.3, %edx
movl %ebp, %edi
movq %r13, %rsi
callq getopt
movl $1, %ecx
cmpl $118, %eax
je .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
cmpl $108, %eax
jg .LBB4_7
# %bb.4: # in Loop: Header=BB4_1 Depth=1
cmpl $-1, %eax
je .LBB4_12
# %bb.5: # in Loop: Header=BB4_1 Depth=1
cmpl $98, %eax
jne .LBB4_11
# %bb.6: # in Loop: Header=BB4_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_7: # in Loop: Header=BB4_1 Depth=1
cmpl $109, %eax
je .LBB4_10
# %bb.8: # in Loop: Header=BB4_1 Depth=1
cmpl $110, %eax
jne .LBB4_11
# %bb.9: # in Loop: Header=BB4_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
jmp .LBB4_1
.p2align 4, 0x90
.LBB4_10: # in Loop: Header=BB4_1 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
jmp .LBB4_1
.LBB4_12:
movl $.L.str.6, %edi
movl %ebx, %esi
movl %r12d, %edx
movl %r15d, %ecx
movl %r14d, %r8d
xorl %eax, %eax
callq printf
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl %ebx, %edi
movl %r12d, %esi
movl %r15d, %edx
movl %r14d, %ecx
callq _Z16exec_kernel_synciiii
movl $.Lstr.3, %edi
callq puts@PLT
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl %ebx, %edi
movl %r12d, %esi
movl %r15d, %edx
movl %r14d, %ecx
callq _Z16exec_kernel_synciiii
movl $.Lstr.3, %edi
callq puts@PLT
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl %ebx, %edi
movl %r12d, %esi
movl %r15d, %edx
movl %r14d, %ecx
callq _Z17exec_kernel_asynciiii
movl $.Lstr.3, %edi
callq puts@PLT
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl %ebx, %edi
movl %r12d, %esi
movl %r15d, %edx
movl %r14d, %ecx
callq _Z17exec_kernel_asynciiii
movl $.Lstr.3, %edi
callq puts@PLT
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_11:
.cfi_def_cfa_offset 64
movl $.L.str.4, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
movq (%r13), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14average_windowPjPfi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14average_windowPjPfi,@object # @_Z14average_windowPjPfi
.section .rodata,"a",@progbits
.globl _Z14average_windowPjPfi
.p2align 3, 0x0
_Z14average_windowPjPfi:
.quad _Z29__device_stub__average_windowPjPfi
.size _Z14average_windowPjPfi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Original value at index [%d]: %d, average: %f\n"
.size .L.str.1, 47
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\tList size: %d, Duration: %fmsn\n"
.size .L.str.2, 33
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "vn:b:m:"
.size .L.str.3, 8
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Error: unrecognized option: %c\n"
.size .L.str.4, 32
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Usage: %s [-v] [-n num_elements] [-b threads_per_block] [-m max_int]"
.size .L.str.5, 69
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "verbosity: %d\tnum_elements: %d\tthreads_per_block: %d\tmax_int: %d\n"
.size .L.str.6, 66
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\nFirst Run of Averages done synchronously"
.size .L.str.7, 42
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Second Run of Averages done synchronously"
.size .L.str.9, 42
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\nFirst Run of Averages done asynchronously"
.size .L.str.10, 43
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Second Run of Averages done asynchronously"
.size .L.str.11, 43
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14average_windowPjPfi"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.3,@object # @str.3
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.3:
.asciz "-----------------------------------------------------------------"
.size .Lstr.3, 66
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__average_windowPjPfi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14average_windowPjPfi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
Group Members : Jose Garcia Kameron Bush
Collatz code for CS 4380 / CS 5351
Copyright (c) 2019 Texas State University. All rights reserved.
Redistribution in source or binary form, with or without modification,
is *not* permitted. Use in source and binary forms, with or without
modification, is only permitted for academic use in CS 4380 or CS 5351
at Texas State University.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Author: Martin Burtscher
*/
#include <cstdio>
#include <algorithm>
#include <cuda.h>
#include <sys/time.h>
static const int ThreadsPerBlock = 512;
static __global__ void collatz(const long upper, int const maxlen[])
{
// compute sequence lengths
//*********has to be only odds*************
const int i = (threadIdx.x + blockIdx.x * (long)blockDim.x) * 2 + 1;
long val = i;
int len = 1;
while (val != 1) {
len++;
if ((val % 2) == 0) {
val = val / 2; // even
} else {
val = 3 * val + 1; // odd
}
}
int * temp = (int *)maxlen[0];
if (len > *temp) { //***********check if pointer correct********
atomicMax(temp, len);
int temp2 = *temp;
maxlen = &temp2;
}
}
static void CheckCuda()
{
cudaError_t e;
cudaDeviceSynchronize();
if (cudaSuccess != (e = cudaGetLastError())) {
fprintf(stderr, "CUDA error %d: %s\n", e, cudaGetErrorString(e));
exit(-1);
}
}
int main(int argc, char *argv[])
{
printf("Collatz v1.2\n");
// check command line
if (argc != 2) {fprintf(stderr, "USAGE: %s upper_bound\n", argv[0]); exit(-1);}
const long upper = atol(argv[1]);
if (upper < 5) {fprintf(stderr, "ERROR: upper_bound must be at least 5\n"); exit(-1);}
if ((upper % 2) != 1) {fprintf(stderr, "ERROR: upper_bound must be an odd number\n"); exit(-1);}
printf("upper bound: %ld\n", upper);
//Initalize
int* const maxlen = new int [1];
maxlen[0] = 0;
// allocate vectors on GPU
int* d_maxlen;
if (cudaSuccess != cudaMalloc((void **)&d_maxlen, 1)) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
// initialize vectors on GPU
if (cudaSuccess != cudaMemcpy(d_maxlen, maxlen, 1, cudaMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
// start time
timeval start, end;
gettimeofday(&start, NULL);
// execute timed code
//**********************see if number of threads correct
collatz<<<(upper + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(upper, d_maxlen);
cudaDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
const double runtime = end.tv_sec - start.tv_sec + (end.tv_usec - start.tv_usec) / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// get result from GPU
CheckCuda();
if (cudaSuccess != cudaMemcpy(maxlen, d_maxlen, 1, cudaMemcpyDeviceToHost)) {fprintf(stderr, "ERROR: copying from device failed\n"); exit(-1);}
// print result
printf("longest sequence: %d elements\n", maxlen[0]);
cudaFree(d_maxlen);
delete [] maxlen;
return 0;
} | code for sm_80
Function : _Z7collatzlPKi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0070*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x004fca0000011402 */
/*0080*/ LD.E R7, [R2.64] ; /* 0x0000000602077980 */
/* 0x000362000c101900 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0209 */
/*00a0*/ BSSY B0, 0x220 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fca00078e00ff */
/*00d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*00e0*/ @!P0 BRA 0x210 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x002fe20007ffe0ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*0110*/ SHF.R.S32.HI R8, RZ, 0x1f, R4 ; /* 0x0000001fff087819 */
/* 0x000fe40000011404 */
/*0120*/ LOP3.LUT R0, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104007812 */
/* 0x000fe400078ec0ff */
/*0130*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f05070 */
/*0150*/ ISETP.NE.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05100 */
/*0160*/ @P0 LEA.HI R0, P1, R8.reuse, R4, RZ, 0x1 ; /* 0x0000000408000211 */
/* 0x040fe200078308ff */
/*0170*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x3 ; /* 0x00000003ff058424 */
/* 0x000fe400078e00ff */
/*0180*/ @!P0 IMAD R11, R8, 0x3, RZ ; /* 0x00000003080b8824 */
/* 0x000fe400078e02ff */
/*0190*/ @P0 IMAD.X R9, RZ, RZ, R8, P1 ; /* 0x000000ffff090224 */
/* 0x000fe400008e0608 */
/*01a0*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x2][0x0] ; /* 0x0080000004048625 */
/* 0x000fc600078e0005 */
/*01b0*/ @P0 SHF.R.S64 R4, R0, 0x1, R9 ; /* 0x0000000100040819 */
/* 0x000fe20000001009 */
/*01c0*/ @!P0 IMAD.IADD R8, R5, 0x1, R11 ; /* 0x0000000105088824 */
/* 0x000fe200078e020b */
/*01d0*/ @P0 SHF.R.S32.HI R8, RZ, 0x1, R9 ; /* 0x00000001ff080819 */
/* 0x000fe40000011409 */
/*01e0*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc80003f05070 */
/*01f0*/ ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f05300 */
/*0200*/ @P0 BRA 0x120 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0220*/ ISETP.GT.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x020fda0003f04270 */
/*0230*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0240*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0250*/ REDUX.MAX.S32 UR5, R6 ; /* 0x00000000060573c4 */
/* 0x000e620000014200 */
/*0260*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0270*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*0280*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*0290*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x002fd8000f8e00ff */
/*02a0*/ @P0 ATOM.E.MAX.S32.STRONG.GPU PT, RZ, [R2.64], R5 ; /* 0x0000000502ff098a */
/* 0x000fe200091ee3c6 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
Group Members : Jose Garcia Kameron Bush
Collatz code for CS 4380 / CS 5351
Copyright (c) 2019 Texas State University. All rights reserved.
Redistribution in source or binary form, with or without modification,
is *not* permitted. Use in source and binary forms, with or without
modification, is only permitted for academic use in CS 4380 or CS 5351
at Texas State University.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Author: Martin Burtscher
*/
#include <cstdio>
#include <algorithm>
#include <cuda.h>
#include <sys/time.h>
static const int ThreadsPerBlock = 512;
static __global__ void collatz(const long upper, int const maxlen[])
{
// compute sequence lengths
//*********has to be only odds*************
const int i = (threadIdx.x + blockIdx.x * (long)blockDim.x) * 2 + 1;
long val = i;
int len = 1;
while (val != 1) {
len++;
if ((val % 2) == 0) {
val = val / 2; // even
} else {
val = 3 * val + 1; // odd
}
}
int * temp = (int *)maxlen[0];
if (len > *temp) { //***********check if pointer correct********
atomicMax(temp, len);
int temp2 = *temp;
maxlen = &temp2;
}
}
static void CheckCuda()
{
cudaError_t e;
cudaDeviceSynchronize();
if (cudaSuccess != (e = cudaGetLastError())) {
fprintf(stderr, "CUDA error %d: %s\n", e, cudaGetErrorString(e));
exit(-1);
}
}
int main(int argc, char *argv[])
{
printf("Collatz v1.2\n");
// check command line
if (argc != 2) {fprintf(stderr, "USAGE: %s upper_bound\n", argv[0]); exit(-1);}
const long upper = atol(argv[1]);
if (upper < 5) {fprintf(stderr, "ERROR: upper_bound must be at least 5\n"); exit(-1);}
if ((upper % 2) != 1) {fprintf(stderr, "ERROR: upper_bound must be an odd number\n"); exit(-1);}
printf("upper bound: %ld\n", upper);
//Initalize
int* const maxlen = new int [1];
maxlen[0] = 0;
// allocate vectors on GPU
int* d_maxlen;
if (cudaSuccess != cudaMalloc((void **)&d_maxlen, 1)) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
// initialize vectors on GPU
if (cudaSuccess != cudaMemcpy(d_maxlen, maxlen, 1, cudaMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
// start time
timeval start, end;
gettimeofday(&start, NULL);
// execute timed code
//**********************see if number of threads correct
collatz<<<(upper + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(upper, d_maxlen);
cudaDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
const double runtime = end.tv_sec - start.tv_sec + (end.tv_usec - start.tv_usec) / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// get result from GPU
CheckCuda();
if (cudaSuccess != cudaMemcpy(maxlen, d_maxlen, 1, cudaMemcpyDeviceToHost)) {fprintf(stderr, "ERROR: copying from device failed\n"); exit(-1);}
// print result
printf("longest sequence: %d elements\n", maxlen[0]);
cudaFree(d_maxlen);
delete [] maxlen;
return 0;
} | .file "tmpxft_001331a5_00000000-6_collatz_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL7collatzlPKi, @function
_ZL7collatzlPKi:
.LFB2364:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL7collatzlPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2364:
.size _ZL7collatzlPKi, .-_ZL7collatzlPKi
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2341:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2341:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Collatz v1.2\n"
.LC1:
.string "USAGE: %s upper_bound\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "ERROR: upper_bound must be at least 5\n"
.align 8
.LC3:
.string "ERROR: upper_bound must be an odd number\n"
.section .rodata.str1.1
.LC4:
.string "upper bound: %ld\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "ERROR: could not allocate memory\n"
.align 8
.LC6:
.string "ERROR: copying to device failed\n"
.section .rodata.str1.1
.LC8:
.string "compute time: %.4f s\n"
.LC9:
.string "CUDA error %d: %s\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "ERROR: copying from device failed\n"
.align 8
.LC11:
.string "longest sequence: %d elements\n"
.text
.globl main
.type main, @function
main:
.LFB2338:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
cmpl $2, %ebp
jne .L20
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
cmpq $4, %rax
jle .L21
movq %rax, %rdx
shrq $63, %rdx
leaq (%rax,%rdx), %rax
andl $1, %eax
subq %rdx, %rax
cmpq $1, %rax
jne .L22
movq %rbx, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, (%rax)
leaq 8(%rsp), %rdi
movl $1, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L23
movl $1, %ecx
movl $1, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L24
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $512, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
leaq 1022(%rbx), %rax
movq %rbx, %rdx
addq $511, %rdx
cmovns %rdx, %rax
sarq $9, %rax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L15:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
movq 48(%rsp), %rax
subq 32(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
movl $2, %ecx
movl $1, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L27
movl 0(%rbp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq (%rbx), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L21:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L25:
movq 8(%rsp), %rsi
movq %rbx, %rdi
call _ZL7collatzlPKi
jmp .L15
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L27:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2338:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z7collatzlPKi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2366:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7collatzlPKi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2366:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
Group Members : Jose Garcia Kameron Bush
Collatz code for CS 4380 / CS 5351
Copyright (c) 2019 Texas State University. All rights reserved.
Redistribution in source or binary form, with or without modification,
is *not* permitted. Use in source and binary forms, with or without
modification, is only permitted for academic use in CS 4380 or CS 5351
at Texas State University.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Author: Martin Burtscher
*/
#include <cstdio>
#include <algorithm>
#include <cuda.h>
#include <sys/time.h>
static const int ThreadsPerBlock = 512;
static __global__ void collatz(const long upper, int const maxlen[])
{
// compute sequence lengths
//*********has to be only odds*************
const int i = (threadIdx.x + blockIdx.x * (long)blockDim.x) * 2 + 1;
long val = i;
int len = 1;
while (val != 1) {
len++;
if ((val % 2) == 0) {
val = val / 2; // even
} else {
val = 3 * val + 1; // odd
}
}
int * temp = (int *)maxlen[0];
if (len > *temp) { //***********check if pointer correct********
atomicMax(temp, len);
int temp2 = *temp;
maxlen = &temp2;
}
}
static void CheckCuda()
{
cudaError_t e;
cudaDeviceSynchronize();
if (cudaSuccess != (e = cudaGetLastError())) {
fprintf(stderr, "CUDA error %d: %s\n", e, cudaGetErrorString(e));
exit(-1);
}
}
int main(int argc, char *argv[])
{
printf("Collatz v1.2\n");
// check command line
if (argc != 2) {fprintf(stderr, "USAGE: %s upper_bound\n", argv[0]); exit(-1);}
const long upper = atol(argv[1]);
if (upper < 5) {fprintf(stderr, "ERROR: upper_bound must be at least 5\n"); exit(-1);}
if ((upper % 2) != 1) {fprintf(stderr, "ERROR: upper_bound must be an odd number\n"); exit(-1);}
printf("upper bound: %ld\n", upper);
//Initalize
int* const maxlen = new int [1];
maxlen[0] = 0;
// allocate vectors on GPU
int* d_maxlen;
if (cudaSuccess != cudaMalloc((void **)&d_maxlen, 1)) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
// initialize vectors on GPU
if (cudaSuccess != cudaMemcpy(d_maxlen, maxlen, 1, cudaMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
// start time
timeval start, end;
gettimeofday(&start, NULL);
// execute timed code
//**********************see if number of threads correct
collatz<<<(upper + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(upper, d_maxlen);
cudaDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
const double runtime = end.tv_sec - start.tv_sec + (end.tv_usec - start.tv_usec) / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// get result from GPU
CheckCuda();
if (cudaSuccess != cudaMemcpy(maxlen, d_maxlen, 1, cudaMemcpyDeviceToHost)) {fprintf(stderr, "ERROR: copying from device failed\n"); exit(-1);}
// print result
printf("longest sequence: %d elements\n", maxlen[0]);
cudaFree(d_maxlen);
delete [] maxlen;
return 0;
} | /*
Group Members : Jose Garcia Kameron Bush
Collatz code for CS 4380 / CS 5351
Copyright (c) 2019 Texas State University. All rights reserved.
Redistribution in source or binary form, with or without modification,
is *not* permitted. Use in source and binary forms, with or without
modification, is only permitted for academic use in CS 4380 or CS 5351
at Texas State University.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Author: Martin Burtscher
*/
#include <cstdio>
#include <algorithm>
#include <hip/hip_runtime.h>
#include <sys/time.h>
static const int ThreadsPerBlock = 512;
static __global__ void collatz(const long upper, int const maxlen[])
{
// compute sequence lengths
//*********has to be only odds*************
const int i = (threadIdx.x + blockIdx.x * (long)blockDim.x) * 2 + 1;
long val = i;
int len = 1;
while (val != 1) {
len++;
if ((val % 2) == 0) {
val = val / 2; // even
} else {
val = 3 * val + 1; // odd
}
}
int * temp = (int *)maxlen[0];
if (len > *temp) { //***********check if pointer correct********
atomicMax(temp, len);
int temp2 = *temp;
maxlen = &temp2;
}
}
static void CheckCuda()
{
hipError_t e;
hipDeviceSynchronize();
if (hipSuccess != (e = hipGetLastError())) {
fprintf(stderr, "CUDA error %d: %s\n", e, hipGetErrorString(e));
exit(-1);
}
}
int main(int argc, char *argv[])
{
printf("Collatz v1.2\n");
// check command line
if (argc != 2) {fprintf(stderr, "USAGE: %s upper_bound\n", argv[0]); exit(-1);}
const long upper = atol(argv[1]);
if (upper < 5) {fprintf(stderr, "ERROR: upper_bound must be at least 5\n"); exit(-1);}
if ((upper % 2) != 1) {fprintf(stderr, "ERROR: upper_bound must be an odd number\n"); exit(-1);}
printf("upper bound: %ld\n", upper);
//Initalize
int* const maxlen = new int [1];
maxlen[0] = 0;
// allocate vectors on GPU
int* d_maxlen;
if (hipSuccess != hipMalloc((void **)&d_maxlen, 1)) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
// initialize vectors on GPU
if (hipSuccess != hipMemcpy(d_maxlen, maxlen, 1, hipMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
// start time
timeval start, end;
gettimeofday(&start, NULL);
// execute timed code
//**********************see if number of threads correct
collatz<<<(upper + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(upper, d_maxlen);
hipDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
const double runtime = end.tv_sec - start.tv_sec + (end.tv_usec - start.tv_usec) / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// get result from GPU
CheckCuda();
if (hipSuccess != hipMemcpy(maxlen, d_maxlen, 1, hipMemcpyDeviceToHost)) {fprintf(stderr, "ERROR: copying from device failed\n"); exit(-1);}
// print result
printf("longest sequence: %d elements\n", maxlen[0]);
hipFree(d_maxlen);
delete [] maxlen;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
Group Members : Jose Garcia Kameron Bush
Collatz code for CS 4380 / CS 5351
Copyright (c) 2019 Texas State University. All rights reserved.
Redistribution in source or binary form, with or without modification,
is *not* permitted. Use in source and binary forms, with or without
modification, is only permitted for academic use in CS 4380 or CS 5351
at Texas State University.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Author: Martin Burtscher
*/
#include <cstdio>
#include <algorithm>
#include <hip/hip_runtime.h>
#include <sys/time.h>
static const int ThreadsPerBlock = 512;
static __global__ void collatz(const long upper, int const maxlen[])
{
// compute sequence lengths
//*********has to be only odds*************
const int i = (threadIdx.x + blockIdx.x * (long)blockDim.x) * 2 + 1;
long val = i;
int len = 1;
while (val != 1) {
len++;
if ((val % 2) == 0) {
val = val / 2; // even
} else {
val = 3 * val + 1; // odd
}
}
int * temp = (int *)maxlen[0];
if (len > *temp) { //***********check if pointer correct********
atomicMax(temp, len);
int temp2 = *temp;
maxlen = &temp2;
}
}
static void CheckCuda()
{
hipError_t e;
hipDeviceSynchronize();
if (hipSuccess != (e = hipGetLastError())) {
fprintf(stderr, "CUDA error %d: %s\n", e, hipGetErrorString(e));
exit(-1);
}
}
int main(int argc, char *argv[])
{
printf("Collatz v1.2\n");
// check command line
if (argc != 2) {fprintf(stderr, "USAGE: %s upper_bound\n", argv[0]); exit(-1);}
const long upper = atol(argv[1]);
if (upper < 5) {fprintf(stderr, "ERROR: upper_bound must be at least 5\n"); exit(-1);}
if ((upper % 2) != 1) {fprintf(stderr, "ERROR: upper_bound must be an odd number\n"); exit(-1);}
printf("upper bound: %ld\n", upper);
//Initalize
int* const maxlen = new int [1];
maxlen[0] = 0;
// allocate vectors on GPU
int* d_maxlen;
if (hipSuccess != hipMalloc((void **)&d_maxlen, 1)) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
// initialize vectors on GPU
if (hipSuccess != hipMemcpy(d_maxlen, maxlen, 1, hipMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
// start time
timeval start, end;
gettimeofday(&start, NULL);
// execute timed code
//**********************see if number of threads correct
collatz<<<(upper + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(upper, d_maxlen);
hipDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
const double runtime = end.tv_sec - start.tv_sec + (end.tv_usec - start.tv_usec) / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// get result from GPU
CheckCuda();
if (hipSuccess != hipMemcpy(maxlen, d_maxlen, 1, hipMemcpyDeviceToHost)) {fprintf(stderr, "ERROR: copying from device failed\n"); exit(-1);}
// print result
printf("longest sequence: %d elements\n", maxlen[0]);
hipFree(d_maxlen);
delete [] maxlen;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL7collatzlPKi,"axG",@progbits,_ZL7collatzlPKi,comdat
.globl _ZL7collatzlPKi
.p2align 8
.type _ZL7collatzlPKi,@function
_ZL7collatzlPKi:
s_load_b32 s2, s[0:1], 0x1c
v_mov_b32_e32 v2, 1
s_mov_b32 s4, 1
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_lshl_u32 v0, s15, v0, 1
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_or_b32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, 1, v[0:1]
s_add_i32 s4, s4, 1
v_mov_b32_e32 v2, s4
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_7
.LBB0_3:
v_and_b32_e32 v2, 1, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v2
s_xor_b32 s5, exec_lo, s5
v_mad_u64_u32 v[2:3], null, v0, 3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v3
v_mad_u64_u32 v[3:4], null, v1, 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i64 v[0:1], 1, v[0:1]
s_branch .LBB0_2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
flat_load_b32 v0, v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_gt_i32_e64 v2, v0
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
flat_atomic_max_i32 v[0:1], v2
.LBB0_10:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL7collatzlPKi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL7collatzlPKi,"axG",@progbits,_ZL7collatzlPKi,comdat
.Lfunc_end0:
.size _ZL7collatzlPKi, .Lfunc_end0-_ZL7collatzlPKi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL7collatzlPKi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL7collatzlPKi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
Group Members : Jose Garcia Kameron Bush
Collatz code for CS 4380 / CS 5351
Copyright (c) 2019 Texas State University. All rights reserved.
Redistribution in source or binary form, with or without modification,
is *not* permitted. Use in source and binary forms, with or without
modification, is only permitted for academic use in CS 4380 or CS 5351
at Texas State University.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Author: Martin Burtscher
*/
#include <cstdio>
#include <algorithm>
#include <hip/hip_runtime.h>
#include <sys/time.h>
static const int ThreadsPerBlock = 512;
static __global__ void collatz(const long upper, int const maxlen[])
{
// compute sequence lengths
//*********has to be only odds*************
const int i = (threadIdx.x + blockIdx.x * (long)blockDim.x) * 2 + 1;
long val = i;
int len = 1;
while (val != 1) {
len++;
if ((val % 2) == 0) {
val = val / 2; // even
} else {
val = 3 * val + 1; // odd
}
}
int * temp = (int *)maxlen[0];
if (len > *temp) { //***********check if pointer correct********
atomicMax(temp, len);
int temp2 = *temp;
maxlen = &temp2;
}
}
static void CheckCuda()
{
hipError_t e;
hipDeviceSynchronize();
if (hipSuccess != (e = hipGetLastError())) {
fprintf(stderr, "CUDA error %d: %s\n", e, hipGetErrorString(e));
exit(-1);
}
}
int main(int argc, char *argv[])
{
printf("Collatz v1.2\n");
// check command line
if (argc != 2) {fprintf(stderr, "USAGE: %s upper_bound\n", argv[0]); exit(-1);}
const long upper = atol(argv[1]);
if (upper < 5) {fprintf(stderr, "ERROR: upper_bound must be at least 5\n"); exit(-1);}
if ((upper % 2) != 1) {fprintf(stderr, "ERROR: upper_bound must be an odd number\n"); exit(-1);}
printf("upper bound: %ld\n", upper);
//Initalize
int* const maxlen = new int [1];
maxlen[0] = 0;
// allocate vectors on GPU
int* d_maxlen;
if (hipSuccess != hipMalloc((void **)&d_maxlen, 1)) {fprintf(stderr, "ERROR: could not allocate memory\n"); exit(-1);}
// initialize vectors on GPU
if (hipSuccess != hipMemcpy(d_maxlen, maxlen, 1, hipMemcpyHostToDevice)) {fprintf(stderr, "ERROR: copying to device failed\n"); exit(-1);}
// start time
timeval start, end;
gettimeofday(&start, NULL);
// execute timed code
//**********************see if number of threads correct
collatz<<<(upper + ThreadsPerBlock - 1) / ThreadsPerBlock, ThreadsPerBlock>>>(upper, d_maxlen);
hipDeviceSynchronize();
// end time
gettimeofday(&end, NULL);
const double runtime = end.tv_sec - start.tv_sec + (end.tv_usec - start.tv_usec) / 1000000.0;
printf("compute time: %.4f s\n", runtime);
// get result from GPU
CheckCuda();
if (hipSuccess != hipMemcpy(maxlen, d_maxlen, 1, hipMemcpyDeviceToHost)) {fprintf(stderr, "ERROR: copying from device failed\n"); exit(-1);}
// print result
printf("longest sequence: %d elements\n", maxlen[0]);
hipFree(d_maxlen);
delete [] maxlen;
return 0;
} | .text
.file "collatz_CUDA.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $.Lstr, %edi
callq puts@PLT
cmpl $2, %ebp
jne .LBB0_16
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpq $4, %rax
jle .LBB0_2
# %bb.4:
movq %rax, %r14
testb $1, %r14b
je .LBB0_5
# %bb.6:
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl $4, %edi
callq _Znam
movq %rax, %rbx
movl $0, (%rax)
leaq 8(%rsp), %rdi
movl $1, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_7
# %bb.8:
movq 8(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_9
# %bb.10:
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %r14, %rax
addq $511, %rax # imm = 0x1FF
shrq $9, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_12
# %bb.11:
movq 8(%rsp), %rax
movq %r14, 88(%rsp)
movq %rax, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rax
movq %rax, 24(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_ZL7collatzlPKi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_12:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 96(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 104(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB0_17
# %bb.13: # %_ZL9CheckCudav.exit
movq 8(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_14
# %bb.15:
movl (%rbx), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_16:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rdi
movq (%rbx), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB0_2:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $38, %esi
jmp .LBB0_3
.LBB0_5:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $41, %esi
jmp .LBB0_3
.LBB0_7:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $33, %esi
jmp .LBB0_3
.LBB0_9:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $32, %esi
jmp .LBB0_3
.LBB0_17:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.10, %esi
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB0_14:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $34, %esi
.LBB0_3:
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL22__device_stub__collatzlPKi
.type _ZL22__device_stub__collatzlPKi,@function
_ZL22__device_stub__collatzlPKi: # @_ZL22__device_stub__collatzlPKi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL7collatzlPKi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _ZL22__device_stub__collatzlPKi, .Lfunc_end1-_ZL22__device_stub__collatzlPKi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL7collatzlPKi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "USAGE: %s upper_bound\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: upper_bound must be at least 5\n"
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ERROR: upper_bound must be an odd number\n"
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "upper bound: %ld\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ERROR: could not allocate memory\n"
.size .L.str.5, 34
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "ERROR: copying to device failed\n"
.size .L.str.6, 33
.type _ZL7collatzlPKi,@object # @_ZL7collatzlPKi
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL7collatzlPKi:
.quad _ZL22__device_stub__collatzlPKi
.size _ZL7collatzlPKi, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "compute time: %.4f s\n"
.size .L.str.7, 22
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "ERROR: copying from device failed\n"
.size .L.str.8, 35
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "longest sequence: %d elements\n"
.size .L.str.9, 31
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "CUDA error %d: %s\n"
.size .L.str.10, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL7collatzlPKi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Collatz v1.2"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL22__device_stub__collatzlPKi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL7collatzlPKi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7collatzlPKi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E R2, [R4.64] ; /* 0x0000000604027981 */
/* 0x000ea8000c1e1900 */
/*0050*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0060*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e220000002100 */
/*0070*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x004fca0000011402 */
/*0080*/ LD.E R7, [R2.64] ; /* 0x0000000602077980 */
/* 0x000362000c101900 */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R9 ; /* 0x0000000000007a24 */
/* 0x001fe200078e0209 */
/*00a0*/ BSSY B0, 0x220 ; /* 0x0000017000007945 */
/* 0x000fe20003800000 */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe400078e00ff */
/*00c0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fca00078e00ff */
/*00d0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*00e0*/ @!P0 BRA 0x210 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R4, R0, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x002fe20007ffe0ff */
/*0100*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*0110*/ SHF.R.S32.HI R8, RZ, 0x1f, R4 ; /* 0x0000001fff087819 */
/* 0x000fe40000011404 */
/*0120*/ LOP3.LUT R0, R4, 0x1, RZ, 0xc0, !PT ; /* 0x0000000104007812 */
/* 0x000fe400078ec0ff */
/*0130*/ IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106067810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.NE.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f05070 */
/*0150*/ ISETP.NE.U32.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fda0003f05100 */
/*0160*/ @P0 LEA.HI R0, P1, R8.reuse, R4, RZ, 0x1 ; /* 0x0000000408000211 */
/* 0x040fe200078308ff */
/*0170*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, 0x3 ; /* 0x00000003ff058424 */
/* 0x000fe400078e00ff */
/*0180*/ @!P0 IMAD R11, R8, 0x3, RZ ; /* 0x00000003080b8824 */
/* 0x000fe400078e02ff */
/*0190*/ @P0 IMAD.X R9, RZ, RZ, R8, P1 ; /* 0x000000ffff090224 */
/* 0x000fe400008e0608 */
/*01a0*/ @!P0 IMAD.WIDE.U32 R4, R4, R5, c[0x2][0x0] ; /* 0x0080000004048625 */
/* 0x000fc600078e0005 */
/*01b0*/ @P0 SHF.R.S64 R4, R0, 0x1, R9 ; /* 0x0000000100040819 */
/* 0x000fe20000001009 */
/*01c0*/ @!P0 IMAD.IADD R8, R5, 0x1, R11 ; /* 0x0000000105088824 */
/* 0x000fe200078e020b */
/*01d0*/ @P0 SHF.R.S32.HI R8, RZ, 0x1, R9 ; /* 0x00000001ff080819 */
/* 0x000fe40000011409 */
/*01e0*/ ISETP.NE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fc80003f05070 */
/*01f0*/ ISETP.NE.AND.EX P0, PT, R8, RZ, PT, P0 ; /* 0x000000ff0800720c */
/* 0x000fda0003f05300 */
/*0200*/ @P0 BRA 0x120 ; /* 0xffffff1000000947 */
/* 0x000fea000383ffff */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0220*/ ISETP.GT.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x020fda0003f04270 */
/*0230*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0240*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0250*/ REDUX.MAX.S32 UR5, R6 ; /* 0x00000000060573c4 */
/* 0x000e620000014200 */
/*0260*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0270*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*0280*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*0290*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x002fd8000f8e00ff */
/*02a0*/ @P0 ATOM.E.MAX.S32.STRONG.GPU PT, RZ, [R2.64], R5 ; /* 0x0000000502ff098a */
/* 0x000fe200091ee3c6 */
/*02b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02c0*/ BRA 0x2c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL7collatzlPKi,"axG",@progbits,_ZL7collatzlPKi,comdat
.globl _ZL7collatzlPKi
.p2align 8
.type _ZL7collatzlPKi,@function
_ZL7collatzlPKi:
s_load_b32 s2, s[0:1], 0x1c
v_mov_b32_e32 v2, 1
s_mov_b32 s4, 1
s_mov_b32 s3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_lshl_u32 v0, s15, v0, 1
v_cmpx_ne_u32_e32 0, v0
s_cbranch_execz .LBB0_8
v_or_b32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u64_e32 vcc_lo, 1, v[0:1]
s_add_i32 s4, s4, 1
v_mov_b32_e32 v2, s4
s_or_b32 s3, vcc_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_7
.LBB0_3:
v_and_b32_e32 v2, 1, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v2
s_xor_b32 s5, exec_lo, s5
v_mad_u64_u32 v[2:3], null, v0, 3, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v0, v3
v_mad_u64_u32 v[3:4], null, v1, 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v0, v2 :: v_dual_mov_b32 v1, v3
s_and_not1_saveexec_b32 s5, s5
s_cbranch_execz .LBB0_2
s_delay_alu instid0(VALU_DEP_1)
v_ashrrev_i64 v[0:1], 1, v[0:1]
s_branch .LBB0_2
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x8
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_ashr_i32 s1, s0, 31
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
flat_load_b32 v0, v[0:1]
s_waitcnt vmcnt(0) lgkmcnt(0)
v_cmpx_gt_i32_e64 v2, v0
s_cbranch_execz .LBB0_10
v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
flat_atomic_max_i32 v[0:1], v2
.LBB0_10:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL7collatzlPKi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL7collatzlPKi,"axG",@progbits,_ZL7collatzlPKi,comdat
.Lfunc_end0:
.size _ZL7collatzlPKi, .Lfunc_end0-_ZL7collatzlPKi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL7collatzlPKi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL7collatzlPKi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001331a5_00000000-6_collatz_CUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL7collatzlPKi, @function
_ZL7collatzlPKi:
.LFB2364:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _ZL7collatzlPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2364:
.size _ZL7collatzlPKi, .-_ZL7collatzlPKi
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2341:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2341:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Collatz v1.2\n"
.LC1:
.string "USAGE: %s upper_bound\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "ERROR: upper_bound must be at least 5\n"
.align 8
.LC3:
.string "ERROR: upper_bound must be an odd number\n"
.section .rodata.str1.1
.LC4:
.string "upper bound: %ld\n"
.section .rodata.str1.8
.align 8
.LC5:
.string "ERROR: could not allocate memory\n"
.align 8
.LC6:
.string "ERROR: copying to device failed\n"
.section .rodata.str1.1
.LC8:
.string "compute time: %.4f s\n"
.LC9:
.string "CUDA error %d: %s\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "ERROR: copying from device failed\n"
.align 8
.LC11:
.string "longest sequence: %d elements\n"
.text
.globl main
.type main, @function
main:
.LFB2338:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $88, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
cmpl $2, %ebp
jne .L20
movq 8(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
cmpq $4, %rax
jle .L21
movq %rax, %rdx
shrq $63, %rdx
leaq (%rax,%rdx), %rax
andl $1, %eax
subq %rdx, %rax
cmpq $1, %rax
jne .L22
movq %rbx, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $4, %edi
call _Znam@PLT
movq %rax, %rbp
movl $0, (%rax)
leaq 8(%rsp), %rdi
movl $1, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L23
movl $1, %ecx
movl $1, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L24
leaq 32(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $512, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
leaq 1022(%rbx), %rax
movq %rbx, %rdx
addq $511, %rdx
cmovns %rdx, %rax
sarq $9, %rax
movl %eax, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 20(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L15:
call cudaDeviceSynchronize@PLT
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 56(%rsp), %rax
subq 40(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC7(%rip), %xmm0
movq 48(%rsp), %rax
subq 32(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L26
movl $2, %ecx
movl $1, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L27
movl 0(%rbp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L28
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq (%rbx), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L21:
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L22:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L23:
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L24:
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L25:
movq 8(%rsp), %rsi
movq %rbx, %rdi
call _ZL7collatzlPKi
jmp .L15
.L26:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl %ebx, %ecx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L27:
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2338:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z7collatzlPKi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2366:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7collatzlPKi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2366:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC7:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "collatz_CUDA.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movl $.Lstr, %edi
callq puts@PLT
cmpl $2, %ebp
jne .LBB0_16
# %bb.1:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cmpq $4, %rax
jle .LBB0_2
# %bb.4:
movq %rax, %r14
testb $1, %r14b
je .LBB0_5
# %bb.6:
movl $.L.str.4, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
movl $4, %edi
callq _Znam
movq %rax, %rbx
movl $0, (%rax)
leaq 8(%rsp), %rdi
movl $1, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB0_7
# %bb.8:
movq 8(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_9
# %bb.10:
leaq 96(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %r14, %rax
addq $511, %rax # imm = 0x1FF
shrq $9, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $512, %rdx # imm = 0x200
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_12
# %bb.11:
movq 8(%rsp), %rax
movq %r14, 88(%rsp)
movq %rax, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 16(%rsp)
leaq 80(%rsp), %rax
movq %rax, 24(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_ZL7collatzlPKi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_12:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
subq 96(%rsp), %rax
cvtsi2sd %rax, %xmm1
subq 104(%rsp), %rcx
cvtsi2sd %rcx, %xmm0
divsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB0_17
# %bb.13: # %_ZL9CheckCudav.exit
movq 8(%rsp), %rsi
movl $1, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB0_14
# %bb.15:
movl (%rbx), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_16:
.cfi_def_cfa_offset 144
movq stderr(%rip), %rdi
movq (%rbx), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB0_2:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $38, %esi
jmp .LBB0_3
.LBB0_5:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $41, %esi
jmp .LBB0_3
.LBB0_7:
movq stderr(%rip), %rcx
movl $.L.str.5, %edi
movl $33, %esi
jmp .LBB0_3
.LBB0_9:
movq stderr(%rip), %rcx
movl $.L.str.6, %edi
movl $32, %esi
jmp .LBB0_3
.LBB0_17:
movq stderr(%rip), %rbx
movl %eax, %edi
movl %eax, %ebp
callq hipGetErrorString
movl $.L.str.10, %esi
movq %rbx, %rdi
movl %ebp, %edx
movq %rax, %rcx
xorl %eax, %eax
callq fprintf
movl $-1, %edi
callq exit
.LBB0_14:
movq stderr(%rip), %rcx
movl $.L.str.8, %edi
movl $34, %esi
.LBB0_3:
movl $1, %edx
callq fwrite@PLT
movl $-1, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function _ZL22__device_stub__collatzlPKi
.type _ZL22__device_stub__collatzlPKi,@function
_ZL22__device_stub__collatzlPKi: # @_ZL22__device_stub__collatzlPKi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_ZL7collatzlPKi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _ZL22__device_stub__collatzlPKi, .Lfunc_end1-_ZL22__device_stub__collatzlPKi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_ZL7collatzlPKi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "USAGE: %s upper_bound\n"
.size .L.str.1, 23
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: upper_bound must be at least 5\n"
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "ERROR: upper_bound must be an odd number\n"
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "upper bound: %ld\n"
.size .L.str.4, 18
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "ERROR: could not allocate memory\n"
.size .L.str.5, 34
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "ERROR: copying to device failed\n"
.size .L.str.6, 33
.type _ZL7collatzlPKi,@object # @_ZL7collatzlPKi
.section .rodata,"a",@progbits
.p2align 3, 0x0
_ZL7collatzlPKi:
.quad _ZL22__device_stub__collatzlPKi
.size _ZL7collatzlPKi, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "compute time: %.4f s\n"
.size .L.str.7, 22
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "ERROR: copying from device failed\n"
.size .L.str.8, 35
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "longest sequence: %d elements\n"
.size .L.str.9, 31
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "CUDA error %d: %s\n"
.size .L.str.10, 19
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_ZL7collatzlPKi"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Collatz v1.2"
.size .Lstr, 13
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZL22__device_stub__collatzlPKi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZL7collatzlPKi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <unistd.h>
struct IntSandwich {
int beginning;
int middle[1];
int end;
};
__global__ void access_offset_kernel(struct IntSandwich *hostMem, int offset) {
#ifdef R
volatile int i = hostMem->middle[offset];
#elif W
hostMem->middle[offset] = 42;
#endif
}
int main(int argc, char** argv) {
if (argc != 3) {
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
int offset = 0;
int c;
while ((c = getopt(argc, argv, "o:")) != -1) {
switch(c) {
case 'o':
offset = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
}
struct IntSandwich *hostMem;
cudaMalloc((void**)&hostMem, sizeof(struct IntSandwich));
access_offset_kernel<<<1,1>>>(hostMem, offset);
cudaFree(hostMem);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z20access_offset_kernelP11IntSandwichi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <unistd.h>
struct IntSandwich {
int beginning;
int middle[1];
int end;
};
__global__ void access_offset_kernel(struct IntSandwich *hostMem, int offset) {
#ifdef R
volatile int i = hostMem->middle[offset];
#elif W
hostMem->middle[offset] = 42;
#endif
}
int main(int argc, char** argv) {
if (argc != 3) {
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
int offset = 0;
int c;
while ((c = getopt(argc, argv, "o:")) != -1) {
switch(c) {
case 'o':
offset = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
}
struct IntSandwich *hostMem;
cudaMalloc((void**)&hostMem, sizeof(struct IntSandwich));
access_offset_kernel<<<1,1>>>(hostMem, offset);
cudaFree(hostMem);
cudaDeviceReset();
return 0;
} | .file "tmpxft_00156b67_00000000-6_struct_global_host_alloc_dynamic_args.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi
.type _Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi, @function
_Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi:
.LFB2095:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20access_offset_kernelP11IntSandwichi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi, .-_Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi
.globl _Z20access_offset_kernelP11IntSandwichi
.type _Z20access_offset_kernelP11IntSandwichi, @function
_Z20access_offset_kernelP11IntSandwichi:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z20access_offset_kernelP11IntSandwichi, .-_Z20access_offset_kernelP11IntSandwichi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s -o <offset>\n"
.LC1:
.string "o:"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L19
movl $0, %ebx
leaq .LC1(%rip), %r12
.L12:
movq %r12, %rdx
movq %rbp, %rsi
movl $3, %edi
call getopt@PLT
cmpl $-1, %eax
je .L20
cmpl $111, %eax
jne .L13
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L12
.L19:
movq (%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
call abort@PLT
.L13:
movq 0(%rbp), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
call abort@PLT
.L20:
leaq 8(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z20access_offset_kernelP11IntSandwichi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20access_offset_kernelP11IntSandwichi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <unistd.h>
struct IntSandwich {
int beginning;
int middle[1];
int end;
};
__global__ void access_offset_kernel(struct IntSandwich *hostMem, int offset) {
#ifdef R
volatile int i = hostMem->middle[offset];
#elif W
hostMem->middle[offset] = 42;
#endif
}
int main(int argc, char** argv) {
if (argc != 3) {
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
int offset = 0;
int c;
while ((c = getopt(argc, argv, "o:")) != -1) {
switch(c) {
case 'o':
offset = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
}
struct IntSandwich *hostMem;
cudaMalloc((void**)&hostMem, sizeof(struct IntSandwich));
access_offset_kernel<<<1,1>>>(hostMem, offset);
cudaFree(hostMem);
cudaDeviceReset();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <unistd.h>
struct IntSandwich {
int beginning;
int middle[1];
int end;
};
__global__ void access_offset_kernel(struct IntSandwich *hostMem, int offset) {
#ifdef R
volatile int i = hostMem->middle[offset];
#elif W
hostMem->middle[offset] = 42;
#endif
}
int main(int argc, char** argv) {
if (argc != 3) {
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
int offset = 0;
int c;
while ((c = getopt(argc, argv, "o:")) != -1) {
switch(c) {
case 'o':
offset = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
}
struct IntSandwich *hostMem;
hipMalloc((void**)&hostMem, sizeof(struct IntSandwich));
access_offset_kernel<<<1,1>>>(hostMem, offset);
hipFree(hostMem);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <unistd.h>
struct IntSandwich {
int beginning;
int middle[1];
int end;
};
__global__ void access_offset_kernel(struct IntSandwich *hostMem, int offset) {
#ifdef R
volatile int i = hostMem->middle[offset];
#elif W
hostMem->middle[offset] = 42;
#endif
}
int main(int argc, char** argv) {
if (argc != 3) {
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
int offset = 0;
int c;
while ((c = getopt(argc, argv, "o:")) != -1) {
switch(c) {
case 'o':
offset = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
}
struct IntSandwich *hostMem;
hipMalloc((void**)&hostMem, sizeof(struct IntSandwich));
access_offset_kernel<<<1,1>>>(hostMem, offset);
hipFree(hostMem);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20access_offset_kernelP11IntSandwichi
.globl _Z20access_offset_kernelP11IntSandwichi
.p2align 8
.type _Z20access_offset_kernelP11IntSandwichi,@function
_Z20access_offset_kernelP11IntSandwichi:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20access_offset_kernelP11IntSandwichi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20access_offset_kernelP11IntSandwichi, .Lfunc_end0-_Z20access_offset_kernelP11IntSandwichi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20access_offset_kernelP11IntSandwichi
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z20access_offset_kernelP11IntSandwichi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <unistd.h>
struct IntSandwich {
int beginning;
int middle[1];
int end;
};
__global__ void access_offset_kernel(struct IntSandwich *hostMem, int offset) {
#ifdef R
volatile int i = hostMem->middle[offset];
#elif W
hostMem->middle[offset] = 42;
#endif
}
int main(int argc, char** argv) {
if (argc != 3) {
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
int offset = 0;
int c;
while ((c = getopt(argc, argv, "o:")) != -1) {
switch(c) {
case 'o':
offset = atoi(optarg);
break;
default:
fprintf(stderr, "Usage: %s -o <offset>\n", argv[0]);
abort();
}
}
struct IntSandwich *hostMem;
hipMalloc((void**)&hostMem, sizeof(struct IntSandwich));
access_offset_kernel<<<1,1>>>(hostMem, offset);
hipFree(hostMem);
hipDeviceReset();
return 0;
} | .text
.file "struct_global_host_alloc_dynamic_args.hip"
.globl _Z35__device_stub__access_offset_kernelP11IntSandwichi # -- Begin function _Z35__device_stub__access_offset_kernelP11IntSandwichi
.p2align 4, 0x90
.type _Z35__device_stub__access_offset_kernelP11IntSandwichi,@function
_Z35__device_stub__access_offset_kernelP11IntSandwichi: # @_Z35__device_stub__access_offset_kernelP11IntSandwichi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20access_offset_kernelP11IntSandwichi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z35__device_stub__access_offset_kernelP11IntSandwichi, .Lfunc_end0-_Z35__device_stub__access_offset_kernelP11IntSandwichi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
cmpl $3, %edi
jne .LBB1_8
# %bb.1: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edx
movl $3, %edi
movq %r14, %rsi
callq getopt
cmpl $111, %eax
jne .LBB1_3
# %bb.7: # in Loop: Header=BB1_2 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
jmp .LBB1_2
.LBB1_3: # %.preheader
cmpl $-1, %eax
jne .LBB1_8
# %bb.4:
leaq 16(%rsp), %rdi
movl $12, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20access_offset_kernelP11IntSandwichi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rdi
movq (%r14), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
callq abort
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20access_offset_kernelP11IntSandwichi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20access_offset_kernelP11IntSandwichi,@object # @_Z20access_offset_kernelP11IntSandwichi
.section .rodata,"a",@progbits
.globl _Z20access_offset_kernelP11IntSandwichi
.p2align 3, 0x0
_Z20access_offset_kernelP11IntSandwichi:
.quad _Z35__device_stub__access_offset_kernelP11IntSandwichi
.size _Z20access_offset_kernelP11IntSandwichi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s -o <offset>\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "o:"
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20access_offset_kernelP11IntSandwichi"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__access_offset_kernelP11IntSandwichi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20access_offset_kernelP11IntSandwichi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20access_offset_kernelP11IntSandwichi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20access_offset_kernelP11IntSandwichi
.globl _Z20access_offset_kernelP11IntSandwichi
.p2align 8
.type _Z20access_offset_kernelP11IntSandwichi,@function
_Z20access_offset_kernelP11IntSandwichi:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20access_offset_kernelP11IntSandwichi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 12
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20access_offset_kernelP11IntSandwichi, .Lfunc_end0-_Z20access_offset_kernelP11IntSandwichi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 12
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20access_offset_kernelP11IntSandwichi
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z20access_offset_kernelP11IntSandwichi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00156b67_00000000-6_struct_global_host_alloc_dynamic_args.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi
.type _Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi, @function
_Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi:
.LFB2095:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z20access_offset_kernelP11IntSandwichi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi, .-_Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi
.globl _Z20access_offset_kernelP11IntSandwichi
.type _Z20access_offset_kernelP11IntSandwichi, @function
_Z20access_offset_kernelP11IntSandwichi:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z20access_offset_kernelP11IntSandwichi, .-_Z20access_offset_kernelP11IntSandwichi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: %s -o <offset>\n"
.LC1:
.string "o:"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jne .L19
movl $0, %ebx
leaq .LC1(%rip), %r12
.L12:
movq %r12, %rdx
movq %rbp, %rsi
movl $3, %edi
call getopt@PLT
cmpl $-1, %eax
je .L20
cmpl $111, %eax
jne .L13
movl $10, %edx
movl $0, %esi
movq optarg(%rip), %rdi
call __isoc23_strtol@PLT
movl %eax, %ebx
jmp .L12
.L19:
movq (%rsi), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
call abort@PLT
.L13:
movq 0(%rbp), %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
call abort@PLT
.L20:
leaq 8(%rsp), %rdi
movl $12, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L15:
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl %ebx, %esi
movq 8(%rsp), %rdi
call _Z53__device_stub__Z20access_offset_kernelP11IntSandwichiP11IntSandwichi
jmp .L15
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "_Z20access_offset_kernelP11IntSandwichi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z20access_offset_kernelP11IntSandwichi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "struct_global_host_alloc_dynamic_args.hip"
.globl _Z35__device_stub__access_offset_kernelP11IntSandwichi # -- Begin function _Z35__device_stub__access_offset_kernelP11IntSandwichi
.p2align 4, 0x90
.type _Z35__device_stub__access_offset_kernelP11IntSandwichi,@function
_Z35__device_stub__access_offset_kernelP11IntSandwichi: # @_Z35__device_stub__access_offset_kernelP11IntSandwichi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z20access_offset_kernelP11IntSandwichi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z35__device_stub__access_offset_kernelP11IntSandwichi, .Lfunc_end0-_Z35__device_stub__access_offset_kernelP11IntSandwichi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %r14
cmpl $3, %edi
jne .LBB1_8
# %bb.1: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edx
movl $3, %edi
movq %r14, %rsi
callq getopt
cmpl $111, %eax
jne .LBB1_3
# %bb.7: # in Loop: Header=BB1_2 Depth=1
movq optarg(%rip), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
jmp .LBB1_2
.LBB1_3: # %.preheader
cmpl $-1, %eax
jne .LBB1_8
# %bb.4:
leaq 16(%rsp), %rdi
movl $12, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20access_offset_kernelP11IntSandwichi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 128
movq stderr(%rip), %rdi
movq (%r14), %rdx
movl $.L.str, %esi
xorl %eax, %eax
callq fprintf
callq abort
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20access_offset_kernelP11IntSandwichi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20access_offset_kernelP11IntSandwichi,@object # @_Z20access_offset_kernelP11IntSandwichi
.section .rodata,"a",@progbits
.globl _Z20access_offset_kernelP11IntSandwichi
.p2align 3, 0x0
_Z20access_offset_kernelP11IntSandwichi:
.quad _Z35__device_stub__access_offset_kernelP11IntSandwichi
.size _Z20access_offset_kernelP11IntSandwichi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Usage: %s -o <offset>\n"
.size .L.str, 23
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "o:"
.size .L.str.1, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z20access_offset_kernelP11IntSandwichi"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__access_offset_kernelP11IntSandwichi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20access_offset_kernelP11IntSandwichi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int d)
{
return (NX*(NY*(d-1)+y)+x);
}
__device__ __forceinline__ size_t gpu_field0_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__global__ void gpu_bc_charge(double *h0, double *h1, double *h2)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y;
perturb = 0;
if (y == 0) {
double multi0c = 2.0*charge0*w0;
double multisc = 2.0*charge0*ws;
double multidc = 2.0*charge0*wd;
// lower plate for charge density
double ht1 = h2[gpu_fieldn_index(x, 0, 1)];
double ht2 = h2[gpu_fieldn_index(x, 0, 2)];
double ht3 = h2[gpu_fieldn_index(x, 0, 3)];
double ht4 = h2[gpu_fieldn_index(x, 0, 4)];
double ht5 = h2[gpu_fieldn_index(x, 0, 5)];
double ht6 = h2[gpu_fieldn_index(x, 0, 6)];
double ht7 = h2[gpu_fieldn_index(x, 0, 7)];
double ht8 = h2[gpu_fieldn_index(x, 0, 8)];
// lower plate for constant charge density
h0[gpu_field0_index(x, 0)] = -h0[gpu_field0_index(x, 0)] + multi0c;
h1[gpu_fieldn_index(x, 0, 3)] = -ht1 + multisc;
h1[gpu_fieldn_index(x, 0, 4)] = -ht2 + multisc;
h1[gpu_fieldn_index(x, 0, 1)] = -ht3 + multisc;
h1[gpu_fieldn_index(x, 0, 2)] = -ht4 + multisc;
h1[gpu_fieldn_index(x, 0, 7)] = -ht5 + multidc;
h1[gpu_fieldn_index(x, 0, 8)] = -ht6 + multidc;
h1[gpu_fieldn_index(x, 0, 5)] = -ht7 + multidc;
h1[gpu_fieldn_index(x, 0, 6)] = -ht8 + multidc;
}
} | code for sm_80
Function : _Z13gpu_bc_chargePdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*0020*/ MOV R2, c[0x4][0x0] ; /* 0x0100000000027a02 */
/* 0x000fe40000000f00 */
/*0030*/ MOV R3, c[0x4][0x4] ; /* 0x0100010000037a02 */
/* 0x000fe40000000f00 */
/*0040*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x001fe2000bf05270 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f4000c101904 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R34, SR_TID.X ; /* 0x0000000000227919 */
/* 0x001e280000002100 */
/*0090*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*00a0*/ IMAD R34, R3, c[0x0][0x0], R34 ; /* 0x0000000003227a24 */
/* 0x001fe200078e0222 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fc800000001ff */
/*00c0*/ IADD3 R10, R34.reuse, 0x3022, RZ ; /* 0x00003022220a7810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ IADD3 R36, R34.reuse, 0x6044, RZ ; /* 0x0000604422247810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ IADD3 R2, R34.reuse, 0x9066, RZ ; /* 0x0000906622027810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IMAD.WIDE.U32 R14, R34.reuse, R3.reuse, c[0x0][0x160] ; /* 0x00005800220e7625 */
/* 0x0c0fe200078e0003 */
/*0100*/ IADD3 R4, R34.reuse, 0xc088, RZ ; /* 0x0000c08822047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ IADD3 R8, R34.reuse, 0xf0aa, RZ ; /* 0x0000f0aa22087810 */
/* 0x040fe20007ffe0ff */
/*0120*/ IMAD.WIDE.U32 R32, R34.reuse, R3.reuse, c[0x0][0x170] ; /* 0x00005c0022207625 */
/* 0x0c0fe200078e0003 */
/*0130*/ IADD3 R0, R34.reuse, 0x120cc, RZ ; /* 0x000120cc22007810 */
/* 0x040fe20007ffe0ff */
/*0140*/ LDG.E.64 R30, [R14.64] ; /* 0x000000040e1e7981 */
/* 0x000ea2000c1e1b00 */
/*0150*/ IADD3 R6, R34, 0x150ee, RZ ; /* 0x000150ee22067810 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD.WIDE.U32 R28, R10, R3, c[0x0][0x170] ; /* 0x00005c000a1c7625 */
/* 0x000fc400078e0003 */
/*0170*/ LDG.E.64 R32, [R32.64] ; /* 0x0000000420207981 */
/* 0x000ee4000c1e1b00 */
/*0180*/ IMAD.WIDE.U32 R24, R36, R3.reuse, c[0x0][0x170] ; /* 0x00005c0024187625 */
/* 0x080fe400078e0003 */
/*0190*/ LDG.E.64 R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000f24000c1e1b00 */
/*01a0*/ IMAD.WIDE.U32 R20, R2, R3.reuse, c[0x0][0x170] ; /* 0x00005c0002147625 */
/* 0x080fe400078e0003 */
/*01b0*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000f64000c1e1b00 */
/*01c0*/ IMAD.WIDE.U32 R18, R4, R3, c[0x0][0x170] ; /* 0x00005c0004127625 */
/* 0x000fc400078e0003 */
/*01d0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f64000c1e1b00 */
/*01e0*/ IMAD.WIDE.U32 R16, R8, R3.reuse, c[0x0][0x170] ; /* 0x00005c0008107625 */
/* 0x080fe400078e0003 */
/*01f0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f64000c1e1b00 */
/*0200*/ IMAD.WIDE.U32 R12, R0, R3.reuse, c[0x0][0x170] ; /* 0x00005c00000c7625 */
/* 0x080fe400078e0003 */
/*0210*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f64000c1e1b00 */
/*0220*/ IMAD.WIDE.U32 R22, R6, R3, c[0x0][0x170] ; /* 0x00005c0006167625 */
/* 0x000fc400078e0003 */
/*0230*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f68000c1e1b00 */
/*0240*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f62000c1e1b00 */
/*0250*/ MOV R26, c[0x3][0x0] ; /* 0x00c00000001a7a02 */
/* 0x000fe40000000f00 */
/*0260*/ MOV R27, c[0x3][0x4] ; /* 0x00c00100001b7a02 */
/* 0x000fcc0000000f00 */
/*0270*/ DADD R26, R26, c[0x3][0x0] ; /* 0x00c000001a1a7629 */
/* 0x000ea20000000000 */
/*0280*/ IMAD.WIDE.U32 R36, R36, R3, c[0x0][0x168] ; /* 0x00005a0024247625 */
/* 0x000fc800078e0003 */
/*0290*/ IMAD.WIDE.U32 R34, R34, R3, c[0x0][0x168] ; /* 0x00005a0022227625 */
/* 0x000fc800078e0003 */
/*02a0*/ IMAD.WIDE.U32 R10, R10, R3, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e0003 */
/*02b0*/ IMAD.WIDE.U32 R6, R6, R3, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0003 */
/*02c0*/ IMAD.WIDE.U32 R4, R4, R3, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0003 */
/*02d0*/ IMAD.WIDE.U32 R8, R8, R3, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0003 */
/*02e0*/ DFMA R30, R26, c[0x3][0x8], -R30 ; /* 0x00c002001a1e7a2b */
/* 0x004e08000000081e */
/*02f0*/ DFMA R32, R26, c[0x3][0x10], -R32 ; /* 0x00c004001a207a2b */
/* 0x008e460000000820 */
/*0300*/ STG.E.64 [R14.64], R30 ; /* 0x0000001e0e007986 */
/* 0x0011e2000c101b04 */
/*0310*/ DFMA R28, R26, c[0x3][0x10], -R28 ; /* 0x00c004001a1c7a2b */
/* 0x010e88000000081c */
/*0320*/ DFMA R24, R26, c[0x3][0x10], -R24 ; /* 0x00c004001a187a2b */
/* 0x020ec80000000818 */
/*0330*/ DFMA R20, R26.reuse, c[0x3][0x10], -R20 ; /* 0x00c004001a147a2b */
/* 0x040f220000000814 */
/*0340*/ STG.E.64 [R36.64], R32 ; /* 0x0000002024007986 */
/* 0x002fe6000c101b04 */
/*0350*/ DFMA R18, R26, c[0x3][0x18], -R18 ; /* 0x00c006001a127a2b */
/* 0x000e620000000812 */
/*0360*/ IMAD.WIDE.U32 R14, R2, R3, c[0x0][0x168] ; /* 0x00005a00020e7625 */
/* 0x001fc600078e0003 */
/*0370*/ DFMA R16, R26, c[0x3][0x18], -R16 ; /* 0x00c006001a107a2b */
/* 0x000e080000000810 */
/*0380*/ DFMA R12, R26.reuse, c[0x3][0x18], -R12 ; /* 0x00c006001a0c7a2b */
/* 0x040f62000000080c */
/*0390*/ STG.E.64 [R14.64], R28 ; /* 0x0000001c0e007986 */
/* 0x004fe6000c101b04 */
/*03a0*/ DFMA R22, R26, c[0x3][0x18], -R22 ; /* 0x00c006001a167a2b */
/* 0x0004240000000816 */
/*03b0*/ IMAD.WIDE.U32 R26, R0, R3, c[0x0][0x168] ; /* 0x00005a00001a7625 */
/* 0x004fe200078e0003 */
/*03c0*/ STG.E.64 [R34.64], R24 ; /* 0x0000001822007986 */
/* 0x008fe8000c101b04 */
/*03d0*/ STG.E.64 [R10.64], R20 ; /* 0x000000140a007986 */
/* 0x010fe8000c101b04 */
/*03e0*/ STG.E.64 [R26.64], R18 ; /* 0x000000121a007986 */
/* 0x002fe8000c101b04 */
/*03f0*/ STG.E.64 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x001fe8000c101b04 */
/*0400*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x020fe8000c101b04 */
/*0410*/ STG.E.64 [R8.64], R22 ; /* 0x0000001608007986 */
/* 0x000fe2000c101b04 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int d)
{
return (NX*(NY*(d-1)+y)+x);
}
__device__ __forceinline__ size_t gpu_field0_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__global__ void gpu_bc_charge(double *h0, double *h1, double *h2)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y;
perturb = 0;
if (y == 0) {
double multi0c = 2.0*charge0*w0;
double multisc = 2.0*charge0*ws;
double multidc = 2.0*charge0*wd;
// lower plate for charge density
double ht1 = h2[gpu_fieldn_index(x, 0, 1)];
double ht2 = h2[gpu_fieldn_index(x, 0, 2)];
double ht3 = h2[gpu_fieldn_index(x, 0, 3)];
double ht4 = h2[gpu_fieldn_index(x, 0, 4)];
double ht5 = h2[gpu_fieldn_index(x, 0, 5)];
double ht6 = h2[gpu_fieldn_index(x, 0, 6)];
double ht7 = h2[gpu_fieldn_index(x, 0, 7)];
double ht8 = h2[gpu_fieldn_index(x, 0, 8)];
// lower plate for constant charge density
h0[gpu_field0_index(x, 0)] = -h0[gpu_field0_index(x, 0)] + multi0c;
h1[gpu_fieldn_index(x, 0, 3)] = -ht1 + multisc;
h1[gpu_fieldn_index(x, 0, 4)] = -ht2 + multisc;
h1[gpu_fieldn_index(x, 0, 1)] = -ht3 + multisc;
h1[gpu_fieldn_index(x, 0, 2)] = -ht4 + multisc;
h1[gpu_fieldn_index(x, 0, 7)] = -ht5 + multidc;
h1[gpu_fieldn_index(x, 0, 8)] = -ht6 + multidc;
h1[gpu_fieldn_index(x, 0, 5)] = -ht7 + multidc;
h1[gpu_fieldn_index(x, 0, 6)] = -ht8 + multidc;
}
} | .file "tmpxft_0011e562_00000000-6_gpu_bc_charge.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_
.type _Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_, @function
_Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13gpu_bc_chargePdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_, .-_Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_
.globl _Z13gpu_bc_chargePdS_S_
.type _Z13gpu_bc_chargePdS_S_, @function
_Z13gpu_bc_chargePdS_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z13gpu_bc_chargePdS_S_, .-_Z13gpu_bc_chargePdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13gpu_bc_chargePdS_S_"
.LC1:
.string "perturb"
.LC2:
.string "charge0"
.LC3:
.string "w0"
.LC4:
.string "ws"
.LC5:
.string "wd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_bc_chargePdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7perturb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7charge0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2w0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2ws(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2wd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2wd
.comm _ZL2wd,8,8
.local _ZL2ws
.comm _ZL2ws,8,8
.local _ZL2w0
.comm _ZL2w0,8,8
.local _ZL7charge0
.comm _ZL7charge0,8,8
.local _ZL7perturb
.comm _ZL7perturb,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int d)
{
return (NX*(NY*(d-1)+y)+x);
}
__device__ __forceinline__ size_t gpu_field0_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__global__ void gpu_bc_charge(double *h0, double *h1, double *h2)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y;
perturb = 0;
if (y == 0) {
double multi0c = 2.0*charge0*w0;
double multisc = 2.0*charge0*ws;
double multidc = 2.0*charge0*wd;
// lower plate for charge density
double ht1 = h2[gpu_fieldn_index(x, 0, 1)];
double ht2 = h2[gpu_fieldn_index(x, 0, 2)];
double ht3 = h2[gpu_fieldn_index(x, 0, 3)];
double ht4 = h2[gpu_fieldn_index(x, 0, 4)];
double ht5 = h2[gpu_fieldn_index(x, 0, 5)];
double ht6 = h2[gpu_fieldn_index(x, 0, 6)];
double ht7 = h2[gpu_fieldn_index(x, 0, 7)];
double ht8 = h2[gpu_fieldn_index(x, 0, 8)];
// lower plate for constant charge density
h0[gpu_field0_index(x, 0)] = -h0[gpu_field0_index(x, 0)] + multi0c;
h1[gpu_fieldn_index(x, 0, 3)] = -ht1 + multisc;
h1[gpu_fieldn_index(x, 0, 4)] = -ht2 + multisc;
h1[gpu_fieldn_index(x, 0, 1)] = -ht3 + multisc;
h1[gpu_fieldn_index(x, 0, 2)] = -ht4 + multisc;
h1[gpu_fieldn_index(x, 0, 7)] = -ht5 + multidc;
h1[gpu_fieldn_index(x, 0, 8)] = -ht6 + multidc;
h1[gpu_fieldn_index(x, 0, 5)] = -ht7 + multidc;
h1[gpu_fieldn_index(x, 0, 6)] = -ht8 + multidc;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int d)
{
return (NX*(NY*(d-1)+y)+x);
}
__device__ __forceinline__ size_t gpu_field0_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__global__ void gpu_bc_charge(double *h0, double *h1, double *h2)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y;
perturb = 0;
if (y == 0) {
double multi0c = 2.0*charge0*w0;
double multisc = 2.0*charge0*ws;
double multidc = 2.0*charge0*wd;
// lower plate for charge density
double ht1 = h2[gpu_fieldn_index(x, 0, 1)];
double ht2 = h2[gpu_fieldn_index(x, 0, 2)];
double ht3 = h2[gpu_fieldn_index(x, 0, 3)];
double ht4 = h2[gpu_fieldn_index(x, 0, 4)];
double ht5 = h2[gpu_fieldn_index(x, 0, 5)];
double ht6 = h2[gpu_fieldn_index(x, 0, 6)];
double ht7 = h2[gpu_fieldn_index(x, 0, 7)];
double ht8 = h2[gpu_fieldn_index(x, 0, 8)];
// lower plate for constant charge density
h0[gpu_field0_index(x, 0)] = -h0[gpu_field0_index(x, 0)] + multi0c;
h1[gpu_fieldn_index(x, 0, 3)] = -ht1 + multisc;
h1[gpu_fieldn_index(x, 0, 4)] = -ht2 + multisc;
h1[gpu_fieldn_index(x, 0, 1)] = -ht3 + multisc;
h1[gpu_fieldn_index(x, 0, 2)] = -ht4 + multisc;
h1[gpu_fieldn_index(x, 0, 7)] = -ht5 + multidc;
h1[gpu_fieldn_index(x, 0, 8)] = -ht6 + multidc;
h1[gpu_fieldn_index(x, 0, 5)] = -ht7 + multidc;
h1[gpu_fieldn_index(x, 0, 6)] = -ht8 + multidc;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int d)
{
return (NX*(NY*(d-1)+y)+x);
}
__device__ __forceinline__ size_t gpu_field0_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__global__ void gpu_bc_charge(double *h0, double *h1, double *h2)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y;
perturb = 0;
if (y == 0) {
double multi0c = 2.0*charge0*w0;
double multisc = 2.0*charge0*ws;
double multidc = 2.0*charge0*wd;
// lower plate for charge density
double ht1 = h2[gpu_fieldn_index(x, 0, 1)];
double ht2 = h2[gpu_fieldn_index(x, 0, 2)];
double ht3 = h2[gpu_fieldn_index(x, 0, 3)];
double ht4 = h2[gpu_fieldn_index(x, 0, 4)];
double ht5 = h2[gpu_fieldn_index(x, 0, 5)];
double ht6 = h2[gpu_fieldn_index(x, 0, 6)];
double ht7 = h2[gpu_fieldn_index(x, 0, 7)];
double ht8 = h2[gpu_fieldn_index(x, 0, 8)];
// lower plate for constant charge density
h0[gpu_field0_index(x, 0)] = -h0[gpu_field0_index(x, 0)] + multi0c;
h1[gpu_fieldn_index(x, 0, 3)] = -ht1 + multisc;
h1[gpu_fieldn_index(x, 0, 4)] = -ht2 + multisc;
h1[gpu_fieldn_index(x, 0, 1)] = -ht3 + multisc;
h1[gpu_fieldn_index(x, 0, 2)] = -ht4 + multisc;
h1[gpu_fieldn_index(x, 0, 7)] = -ht5 + multidc;
h1[gpu_fieldn_index(x, 0, 8)] = -ht6 + multidc;
h1[gpu_fieldn_index(x, 0, 5)] = -ht7 + multidc;
h1[gpu_fieldn_index(x, 0, 6)] = -ht8 + multidc;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13gpu_bc_chargePdS_S_
.globl _Z13gpu_bc_chargePdS_S_
.p2align 8
.type _Z13gpu_bc_chargePdS_S_,@function
_Z13gpu_bc_chargePdS_S_:
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, perturb@rel32@lo+4
s_addc_u32 s3, s3, perturb@rel32@hi+12
s_cmp_lg_u32 s15, 0
global_store_b32 v1, v2, s[2:3]
s_cbranch_scc0 .LBB0_2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_2:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, 0x3022, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v5, 0x6044, v1
v_lshlrev_b64 v[15:16], 3, v[1:2]
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v7, 0x9066, v1
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_dual_mov_b32 v8, v2 :: v_dual_add_nc_u32 v9, 0xc088, v1
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_co_u32 v17, vcc_lo, s0, v15
v_dual_mov_b32 v10, v2 :: v_dual_add_nc_u32 v11, 0xf0aa, v1
v_add_co_ci_u32_e32 v18, vcc_lo, s1, v16, vcc_lo
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v19, vcc_lo, s0, v3
v_dual_mov_b32 v12, v2 :: v_dual_add_nc_u32 v13, 0x120cc, v1
v_add_co_ci_u32_e32 v20, vcc_lo, s1, v4, vcc_lo
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v21, vcc_lo, s0, v5
v_dual_mov_b32 v14, v2 :: v_dual_add_nc_u32 v1, 0x150ee, v1
v_add_co_ci_u32_e32 v22, vcc_lo, s1, v6, vcc_lo
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_add_co_u32 v23, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v24, vcc_lo, s1, v8, vcc_lo
v_add_co_u32 v25, vcc_lo, s0, v9
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_ci_u32_e32 v26, vcc_lo, s1, v10, vcc_lo
v_add_co_u32 v27, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v28, vcc_lo, s1, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_u32 v29, vcc_lo, s0, v13
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_ci_u32_e32 v30, vcc_lo, s1, v14, vcc_lo
v_add_co_u32 v31, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v32, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v33, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v34, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[35:36], v[31:32], off
s_clause 0x7
global_load_b64 v[17:18], v[17:18], off
global_load_b64 v[19:20], v[19:20], off
global_load_b64 v[21:22], v[21:22], off
global_load_b64 v[23:24], v[23:24], off
global_load_b64 v[25:26], v[25:26], off
global_load_b64 v[27:28], v[27:28], off
global_load_b64 v[29:30], v[29:30], off
global_load_b64 v[33:34], v[33:34], off
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, charge0@rel32@lo+4
s_addc_u32 s1, s1, charge0@rel32@hi+12
v_add_co_u32 v15, vcc_lo, s6, v15
s_load_b64 s[0:1], s[0:1], 0x0
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v13, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
s_waitcnt lgkmcnt(0)
v_add_f64 v[37:38], s[0:1], s[0:1]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, w0@rel32@lo+4
s_addc_u32 s1, s1, w0@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, ws@rel32@lo+4
s_addc_u32 s3, s3, ws@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, wd@rel32@lo+4
s_addc_u32 s5, s5, wd@rel32@hi+12
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_load_b64 s[4:5], s[4:5], 0x0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
s_waitcnt vmcnt(8) lgkmcnt(0)
v_fma_f64 v[35:36], v[37:38], s[0:1], -v[35:36]
s_waitcnt vmcnt(7)
v_fma_f64 v[17:18], v[37:38], s[2:3], -v[17:18]
s_waitcnt vmcnt(6)
v_fma_f64 v[19:20], v[37:38], s[2:3], -v[19:20]
s_waitcnt vmcnt(5)
v_fma_f64 v[21:22], v[37:38], s[2:3], -v[21:22]
s_waitcnt vmcnt(4)
v_fma_f64 v[23:24], v[37:38], s[2:3], -v[23:24]
s_waitcnt vmcnt(3)
v_fma_f64 v[25:26], v[37:38], s[4:5], -v[25:26]
s_waitcnt vmcnt(2)
v_fma_f64 v[27:28], v[37:38], s[4:5], -v[27:28]
s_waitcnt vmcnt(1)
v_fma_f64 v[29:30], v[37:38], s[4:5], -v[29:30]
s_waitcnt vmcnt(0)
v_fma_f64 v[33:34], v[37:38], s[4:5], -v[33:34]
global_store_b64 v[31:32], v[35:36], off
s_clause 0x7
global_store_b64 v[5:6], v[17:18], off
global_store_b64 v[7:8], v[19:20], off
global_store_b64 v[15:16], v[21:22], off
global_store_b64 v[2:3], v[23:24], off
global_store_b64 v[13:14], v[25:26], off
global_store_b64 v[0:1], v[27:28], off
global_store_b64 v[9:10], v[29:30], off
global_store_b64 v[11:12], v[33:34], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13gpu_bc_chargePdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 39
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13gpu_bc_chargePdS_S_, .Lfunc_end0-_Z13gpu_bc_chargePdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected perturb
.type perturb,@object
.section .bss,"aw",@nobits
.globl perturb
.p2align 2, 0x0
perturb:
.long 0
.size perturb, 4
.protected charge0
.type charge0,@object
.data
.globl charge0
.p2align 3, 0x0
charge0:
.quad 0x4024000000000000
.size charge0, 8
.protected w0
.type w0,@object
.globl w0
.p2align 3, 0x0
w0:
.quad 0x3fdc71c71c71c71c
.size w0, 8
.protected ws
.type ws,@object
.globl ws
.p2align 3, 0x0
ws:
.quad 0x3fbc71c71c71c71c
.size ws, 8
.protected wd
.type wd,@object
.globl wd
.p2align 3, 0x0
wd:
.quad 0x3f9c71c71c71c71c
.size wd, 8
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym perturb
.addrsig_sym charge0
.addrsig_sym w0
.addrsig_sym ws
.addrsig_sym wd
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13gpu_bc_chargePdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13gpu_bc_chargePdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 39
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ __forceinline__ size_t gpu_fieldn_index(unsigned int x, unsigned int y, unsigned int d)
{
return (NX*(NY*(d-1)+y)+x);
}
__device__ __forceinline__ size_t gpu_field0_index(unsigned int x, unsigned int y)
{
return NX*y+x;
}
__global__ void gpu_bc_charge(double *h0, double *h1, double *h2)
{
unsigned int x = blockIdx.x*blockDim.x + threadIdx.x;
unsigned int y = blockIdx.y;
perturb = 0;
if (y == 0) {
double multi0c = 2.0*charge0*w0;
double multisc = 2.0*charge0*ws;
double multidc = 2.0*charge0*wd;
// lower plate for charge density
double ht1 = h2[gpu_fieldn_index(x, 0, 1)];
double ht2 = h2[gpu_fieldn_index(x, 0, 2)];
double ht3 = h2[gpu_fieldn_index(x, 0, 3)];
double ht4 = h2[gpu_fieldn_index(x, 0, 4)];
double ht5 = h2[gpu_fieldn_index(x, 0, 5)];
double ht6 = h2[gpu_fieldn_index(x, 0, 6)];
double ht7 = h2[gpu_fieldn_index(x, 0, 7)];
double ht8 = h2[gpu_fieldn_index(x, 0, 8)];
// lower plate for constant charge density
h0[gpu_field0_index(x, 0)] = -h0[gpu_field0_index(x, 0)] + multi0c;
h1[gpu_fieldn_index(x, 0, 3)] = -ht1 + multisc;
h1[gpu_fieldn_index(x, 0, 4)] = -ht2 + multisc;
h1[gpu_fieldn_index(x, 0, 1)] = -ht3 + multisc;
h1[gpu_fieldn_index(x, 0, 2)] = -ht4 + multisc;
h1[gpu_fieldn_index(x, 0, 7)] = -ht5 + multidc;
h1[gpu_fieldn_index(x, 0, 8)] = -ht6 + multidc;
h1[gpu_fieldn_index(x, 0, 5)] = -ht7 + multidc;
h1[gpu_fieldn_index(x, 0, 6)] = -ht8 + multidc;
}
} | .text
.file "gpu_bc_charge.hip"
.globl _Z28__device_stub__gpu_bc_chargePdS_S_ # -- Begin function _Z28__device_stub__gpu_bc_chargePdS_S_
.p2align 4, 0x90
.type _Z28__device_stub__gpu_bc_chargePdS_S_,@function
_Z28__device_stub__gpu_bc_chargePdS_S_: # @_Z28__device_stub__gpu_bc_chargePdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13gpu_bc_chargePdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_bc_chargePdS_S_, .Lfunc_end0-_Z28__device_stub__gpu_bc_chargePdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_bc_chargePdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $perturb, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $charge0, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $w0, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $ws, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $wd, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type perturb,@object # @perturb
.local perturb
.comm perturb,4,4
.type charge0,@object # @charge0
.local charge0
.comm charge0,8,8
.type w0,@object # @w0
.local w0
.comm w0,8,8
.type ws,@object # @ws
.local ws
.comm ws,8,8
.type wd,@object # @wd
.local wd
.comm wd,8,8
.type _Z13gpu_bc_chargePdS_S_,@object # @_Z13gpu_bc_chargePdS_S_
.section .rodata,"a",@progbits
.globl _Z13gpu_bc_chargePdS_S_
.p2align 3, 0x0
_Z13gpu_bc_chargePdS_S_:
.quad _Z28__device_stub__gpu_bc_chargePdS_S_
.size _Z13gpu_bc_chargePdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13gpu_bc_chargePdS_S_"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "perturb"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "charge0"
.size .L__unnamed_3, 8
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "w0"
.size .L__unnamed_4, 3
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "ws"
.size .L__unnamed_5, 3
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "wd"
.size .L__unnamed_6, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_bc_chargePdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym perturb
.addrsig_sym charge0
.addrsig_sym w0
.addrsig_sym ws
.addrsig_sym wd
.addrsig_sym _Z13gpu_bc_chargePdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13gpu_bc_chargePdS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2UR UR4, SR_CTAID.Y ; /* 0x00000000000479c3 */
/* 0x000e220000002600 */
/*0020*/ MOV R2, c[0x4][0x0] ; /* 0x0100000000027a02 */
/* 0x000fe40000000f00 */
/*0030*/ MOV R3, c[0x4][0x4] ; /* 0x0100010000037a02 */
/* 0x000fe40000000f00 */
/*0040*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x001fe2000bf05270 */
/*0050*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0060*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001f4000c101904 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ S2R R34, SR_TID.X ; /* 0x0000000000227919 */
/* 0x001e280000002100 */
/*0090*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*00a0*/ IMAD R34, R3, c[0x0][0x0], R34 ; /* 0x0000000003227a24 */
/* 0x001fe200078e0222 */
/*00b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff037435 */
/* 0x000fc800000001ff */
/*00c0*/ IADD3 R10, R34.reuse, 0x3022, RZ ; /* 0x00003022220a7810 */
/* 0x040fe40007ffe0ff */
/*00d0*/ IADD3 R36, R34.reuse, 0x6044, RZ ; /* 0x0000604422247810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ IADD3 R2, R34.reuse, 0x9066, RZ ; /* 0x0000906622027810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IMAD.WIDE.U32 R14, R34.reuse, R3.reuse, c[0x0][0x160] ; /* 0x00005800220e7625 */
/* 0x0c0fe200078e0003 */
/*0100*/ IADD3 R4, R34.reuse, 0xc088, RZ ; /* 0x0000c08822047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ IADD3 R8, R34.reuse, 0xf0aa, RZ ; /* 0x0000f0aa22087810 */
/* 0x040fe20007ffe0ff */
/*0120*/ IMAD.WIDE.U32 R32, R34.reuse, R3.reuse, c[0x0][0x170] ; /* 0x00005c0022207625 */
/* 0x0c0fe200078e0003 */
/*0130*/ IADD3 R0, R34.reuse, 0x120cc, RZ ; /* 0x000120cc22007810 */
/* 0x040fe20007ffe0ff */
/*0140*/ LDG.E.64 R30, [R14.64] ; /* 0x000000040e1e7981 */
/* 0x000ea2000c1e1b00 */
/*0150*/ IADD3 R6, R34, 0x150ee, RZ ; /* 0x000150ee22067810 */
/* 0x000fe20007ffe0ff */
/*0160*/ IMAD.WIDE.U32 R28, R10, R3, c[0x0][0x170] ; /* 0x00005c000a1c7625 */
/* 0x000fc400078e0003 */
/*0170*/ LDG.E.64 R32, [R32.64] ; /* 0x0000000420207981 */
/* 0x000ee4000c1e1b00 */
/*0180*/ IMAD.WIDE.U32 R24, R36, R3.reuse, c[0x0][0x170] ; /* 0x00005c0024187625 */
/* 0x080fe400078e0003 */
/*0190*/ LDG.E.64 R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000f24000c1e1b00 */
/*01a0*/ IMAD.WIDE.U32 R20, R2, R3.reuse, c[0x0][0x170] ; /* 0x00005c0002147625 */
/* 0x080fe400078e0003 */
/*01b0*/ LDG.E.64 R24, [R24.64] ; /* 0x0000000418187981 */
/* 0x000f64000c1e1b00 */
/*01c0*/ IMAD.WIDE.U32 R18, R4, R3, c[0x0][0x170] ; /* 0x00005c0004127625 */
/* 0x000fc400078e0003 */
/*01d0*/ LDG.E.64 R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000f64000c1e1b00 */
/*01e0*/ IMAD.WIDE.U32 R16, R8, R3.reuse, c[0x0][0x170] ; /* 0x00005c0008107625 */
/* 0x080fe400078e0003 */
/*01f0*/ LDG.E.64 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000f64000c1e1b00 */
/*0200*/ IMAD.WIDE.U32 R12, R0, R3.reuse, c[0x0][0x170] ; /* 0x00005c00000c7625 */
/* 0x080fe400078e0003 */
/*0210*/ LDG.E.64 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f64000c1e1b00 */
/*0220*/ IMAD.WIDE.U32 R22, R6, R3, c[0x0][0x170] ; /* 0x00005c0006167625 */
/* 0x000fc400078e0003 */
/*0230*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000f68000c1e1b00 */
/*0240*/ LDG.E.64 R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000f62000c1e1b00 */
/*0250*/ MOV R26, c[0x3][0x0] ; /* 0x00c00000001a7a02 */
/* 0x000fe40000000f00 */
/*0260*/ MOV R27, c[0x3][0x4] ; /* 0x00c00100001b7a02 */
/* 0x000fcc0000000f00 */
/*0270*/ DADD R26, R26, c[0x3][0x0] ; /* 0x00c000001a1a7629 */
/* 0x000ea20000000000 */
/*0280*/ IMAD.WIDE.U32 R36, R36, R3, c[0x0][0x168] ; /* 0x00005a0024247625 */
/* 0x000fc800078e0003 */
/*0290*/ IMAD.WIDE.U32 R34, R34, R3, c[0x0][0x168] ; /* 0x00005a0022227625 */
/* 0x000fc800078e0003 */
/*02a0*/ IMAD.WIDE.U32 R10, R10, R3, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fc800078e0003 */
/*02b0*/ IMAD.WIDE.U32 R6, R6, R3, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0003 */
/*02c0*/ IMAD.WIDE.U32 R4, R4, R3, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0003 */
/*02d0*/ IMAD.WIDE.U32 R8, R8, R3, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0003 */
/*02e0*/ DFMA R30, R26, c[0x3][0x8], -R30 ; /* 0x00c002001a1e7a2b */
/* 0x004e08000000081e */
/*02f0*/ DFMA R32, R26, c[0x3][0x10], -R32 ; /* 0x00c004001a207a2b */
/* 0x008e460000000820 */
/*0300*/ STG.E.64 [R14.64], R30 ; /* 0x0000001e0e007986 */
/* 0x0011e2000c101b04 */
/*0310*/ DFMA R28, R26, c[0x3][0x10], -R28 ; /* 0x00c004001a1c7a2b */
/* 0x010e88000000081c */
/*0320*/ DFMA R24, R26, c[0x3][0x10], -R24 ; /* 0x00c004001a187a2b */
/* 0x020ec80000000818 */
/*0330*/ DFMA R20, R26.reuse, c[0x3][0x10], -R20 ; /* 0x00c004001a147a2b */
/* 0x040f220000000814 */
/*0340*/ STG.E.64 [R36.64], R32 ; /* 0x0000002024007986 */
/* 0x002fe6000c101b04 */
/*0350*/ DFMA R18, R26, c[0x3][0x18], -R18 ; /* 0x00c006001a127a2b */
/* 0x000e620000000812 */
/*0360*/ IMAD.WIDE.U32 R14, R2, R3, c[0x0][0x168] ; /* 0x00005a00020e7625 */
/* 0x001fc600078e0003 */
/*0370*/ DFMA R16, R26, c[0x3][0x18], -R16 ; /* 0x00c006001a107a2b */
/* 0x000e080000000810 */
/*0380*/ DFMA R12, R26.reuse, c[0x3][0x18], -R12 ; /* 0x00c006001a0c7a2b */
/* 0x040f62000000080c */
/*0390*/ STG.E.64 [R14.64], R28 ; /* 0x0000001c0e007986 */
/* 0x004fe6000c101b04 */
/*03a0*/ DFMA R22, R26, c[0x3][0x18], -R22 ; /* 0x00c006001a167a2b */
/* 0x0004240000000816 */
/*03b0*/ IMAD.WIDE.U32 R26, R0, R3, c[0x0][0x168] ; /* 0x00005a00001a7625 */
/* 0x004fe200078e0003 */
/*03c0*/ STG.E.64 [R34.64], R24 ; /* 0x0000001822007986 */
/* 0x008fe8000c101b04 */
/*03d0*/ STG.E.64 [R10.64], R20 ; /* 0x000000140a007986 */
/* 0x010fe8000c101b04 */
/*03e0*/ STG.E.64 [R26.64], R18 ; /* 0x000000121a007986 */
/* 0x002fe8000c101b04 */
/*03f0*/ STG.E.64 [R6.64], R16 ; /* 0x0000001006007986 */
/* 0x001fe8000c101b04 */
/*0400*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x020fe8000c101b04 */
/*0410*/ STG.E.64 [R8.64], R22 ; /* 0x0000001608007986 */
/* 0x000fe2000c101b04 */
/*0420*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0430*/ BRA 0x430; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13gpu_bc_chargePdS_S_
.globl _Z13gpu_bc_chargePdS_S_
.p2align 8
.type _Z13gpu_bc_chargePdS_S_,@function
_Z13gpu_bc_chargePdS_S_:
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, perturb@rel32@lo+4
s_addc_u32 s3, s3, perturb@rel32@hi+12
s_cmp_lg_u32 s15, 0
global_store_b32 v1, v2, s[2:3]
s_cbranch_scc0 .LBB0_2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.LBB0_2:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, 0x3022, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mov_b32 v4, v2 :: v_dual_add_nc_u32 v5, 0x6044, v1
v_lshlrev_b64 v[15:16], 3, v[1:2]
v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v7, 0x9066, v1
v_lshlrev_b64 v[3:4], 3, v[3:4]
v_dual_mov_b32 v8, v2 :: v_dual_add_nc_u32 v9, 0xc088, v1
s_delay_alu instid0(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_co_u32 v17, vcc_lo, s0, v15
v_dual_mov_b32 v10, v2 :: v_dual_add_nc_u32 v11, 0xf0aa, v1
v_add_co_ci_u32_e32 v18, vcc_lo, s1, v16, vcc_lo
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v19, vcc_lo, s0, v3
v_dual_mov_b32 v12, v2 :: v_dual_add_nc_u32 v13, 0x120cc, v1
v_add_co_ci_u32_e32 v20, vcc_lo, s1, v4, vcc_lo
v_lshlrev_b64 v[9:10], 3, v[9:10]
v_add_co_u32 v21, vcc_lo, s0, v5
v_dual_mov_b32 v14, v2 :: v_dual_add_nc_u32 v1, 0x150ee, v1
v_add_co_ci_u32_e32 v22, vcc_lo, s1, v6, vcc_lo
v_lshlrev_b64 v[11:12], 3, v[11:12]
v_add_co_u32 v23, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v24, vcc_lo, s1, v8, vcc_lo
v_add_co_u32 v25, vcc_lo, s0, v9
v_lshlrev_b64 v[13:14], 3, v[13:14]
v_add_co_ci_u32_e32 v26, vcc_lo, s1, v10, vcc_lo
v_add_co_u32 v27, vcc_lo, s0, v11
v_add_co_ci_u32_e32 v28, vcc_lo, s1, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_u32 v29, vcc_lo, s0, v13
v_lshlrev_b64 v[0:1], 3, v[1:2]
v_add_co_ci_u32_e32 v30, vcc_lo, s1, v14, vcc_lo
v_add_co_u32 v31, vcc_lo, s4, v15
v_add_co_ci_u32_e32 v32, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v33, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v34, vcc_lo, s1, v1, vcc_lo
global_load_b64 v[35:36], v[31:32], off
s_clause 0x7
global_load_b64 v[17:18], v[17:18], off
global_load_b64 v[19:20], v[19:20], off
global_load_b64 v[21:22], v[21:22], off
global_load_b64 v[23:24], v[23:24], off
global_load_b64 v[25:26], v[25:26], off
global_load_b64 v[27:28], v[27:28], off
global_load_b64 v[29:30], v[29:30], off
global_load_b64 v[33:34], v[33:34], off
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, charge0@rel32@lo+4
s_addc_u32 s1, s1, charge0@rel32@hi+12
v_add_co_u32 v15, vcc_lo, s6, v15
s_load_b64 s[0:1], s[0:1], 0x0
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
v_add_co_u32 v2, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v13, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
s_waitcnt lgkmcnt(0)
v_add_f64 v[37:38], s[0:1], s[0:1]
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, w0@rel32@lo+4
s_addc_u32 s1, s1, w0@rel32@hi+12
s_getpc_b64 s[2:3]
s_add_u32 s2, s2, ws@rel32@lo+4
s_addc_u32 s3, s3, ws@rel32@hi+12
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, wd@rel32@lo+4
s_addc_u32 s5, s5, wd@rel32@hi+12
s_load_b64 s[0:1], s[0:1], 0x0
s_load_b64 s[2:3], s[2:3], 0x0
s_load_b64 s[4:5], s[4:5], 0x0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
s_waitcnt vmcnt(8) lgkmcnt(0)
v_fma_f64 v[35:36], v[37:38], s[0:1], -v[35:36]
s_waitcnt vmcnt(7)
v_fma_f64 v[17:18], v[37:38], s[2:3], -v[17:18]
s_waitcnt vmcnt(6)
v_fma_f64 v[19:20], v[37:38], s[2:3], -v[19:20]
s_waitcnt vmcnt(5)
v_fma_f64 v[21:22], v[37:38], s[2:3], -v[21:22]
s_waitcnt vmcnt(4)
v_fma_f64 v[23:24], v[37:38], s[2:3], -v[23:24]
s_waitcnt vmcnt(3)
v_fma_f64 v[25:26], v[37:38], s[4:5], -v[25:26]
s_waitcnt vmcnt(2)
v_fma_f64 v[27:28], v[37:38], s[4:5], -v[27:28]
s_waitcnt vmcnt(1)
v_fma_f64 v[29:30], v[37:38], s[4:5], -v[29:30]
s_waitcnt vmcnt(0)
v_fma_f64 v[33:34], v[37:38], s[4:5], -v[33:34]
global_store_b64 v[31:32], v[35:36], off
s_clause 0x7
global_store_b64 v[5:6], v[17:18], off
global_store_b64 v[7:8], v[19:20], off
global_store_b64 v[15:16], v[21:22], off
global_store_b64 v[2:3], v[23:24], off
global_store_b64 v[13:14], v[25:26], off
global_store_b64 v[0:1], v[27:28], off
global_store_b64 v[9:10], v[29:30], off
global_store_b64 v[11:12], v[33:34], off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13gpu_bc_chargePdS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 39
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13gpu_bc_chargePdS_S_, .Lfunc_end0-_Z13gpu_bc_chargePdS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected perturb
.type perturb,@object
.section .bss,"aw",@nobits
.globl perturb
.p2align 2, 0x0
perturb:
.long 0
.size perturb, 4
.protected charge0
.type charge0,@object
.data
.globl charge0
.p2align 3, 0x0
charge0:
.quad 0x4024000000000000
.size charge0, 8
.protected w0
.type w0,@object
.globl w0
.p2align 3, 0x0
w0:
.quad 0x3fdc71c71c71c71c
.size w0, 8
.protected ws
.type ws,@object
.globl ws
.p2align 3, 0x0
ws:
.quad 0x3fbc71c71c71c71c
.size ws, 8
.protected wd
.type wd,@object
.globl wd
.p2align 3, 0x0
wd:
.quad 0x3f9c71c71c71c71c
.size wd, 8
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym perturb
.addrsig_sym charge0
.addrsig_sym w0
.addrsig_sym ws
.addrsig_sym wd
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13gpu_bc_chargePdS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13gpu_bc_chargePdS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 39
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011e562_00000000-6_gpu_bc_charge.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_
.type _Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_, @function
_Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13gpu_bc_chargePdS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_, .-_Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_
.globl _Z13gpu_bc_chargePdS_S_
.type _Z13gpu_bc_chargePdS_S_, @function
_Z13gpu_bc_chargePdS_S_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13gpu_bc_chargePdS_S_PdS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z13gpu_bc_chargePdS_S_, .-_Z13gpu_bc_chargePdS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13gpu_bc_chargePdS_S_"
.LC1:
.string "perturb"
.LC2:
.string "charge0"
.LC3:
.string "w0"
.LC4:
.string "ws"
.LC5:
.string "wd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13gpu_bc_chargePdS_S_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7perturb(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7charge0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2w0(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2ws(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $8, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL2wd(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL2wd
.comm _ZL2wd,8,8
.local _ZL2ws
.comm _ZL2ws,8,8
.local _ZL2w0
.comm _ZL2w0,8,8
.local _ZL7charge0
.comm _ZL7charge0,8,8
.local _ZL7perturb
.comm _ZL7perturb,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_bc_charge.hip"
.globl _Z28__device_stub__gpu_bc_chargePdS_S_ # -- Begin function _Z28__device_stub__gpu_bc_chargePdS_S_
.p2align 4, 0x90
.type _Z28__device_stub__gpu_bc_chargePdS_S_,@function
_Z28__device_stub__gpu_bc_chargePdS_S_: # @_Z28__device_stub__gpu_bc_chargePdS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13gpu_bc_chargePdS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__gpu_bc_chargePdS_S_, .Lfunc_end0-_Z28__device_stub__gpu_bc_chargePdS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13gpu_bc_chargePdS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $perturb, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $charge0, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $w0, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $ws, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $wd, %esi
movl $.L__unnamed_6, %edx
movl $.L__unnamed_6, %ecx
movl $8, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type perturb,@object # @perturb
.local perturb
.comm perturb,4,4
.type charge0,@object # @charge0
.local charge0
.comm charge0,8,8
.type w0,@object # @w0
.local w0
.comm w0,8,8
.type ws,@object # @ws
.local ws
.comm ws,8,8
.type wd,@object # @wd
.local wd
.comm wd,8,8
.type _Z13gpu_bc_chargePdS_S_,@object # @_Z13gpu_bc_chargePdS_S_
.section .rodata,"a",@progbits
.globl _Z13gpu_bc_chargePdS_S_
.p2align 3, 0x0
_Z13gpu_bc_chargePdS_S_:
.quad _Z28__device_stub__gpu_bc_chargePdS_S_
.size _Z13gpu_bc_chargePdS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13gpu_bc_chargePdS_S_"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "perturb"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "charge0"
.size .L__unnamed_3, 8
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "w0"
.size .L__unnamed_4, 3
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "ws"
.size .L__unnamed_5, 3
.type .L__unnamed_6,@object # @5
.L__unnamed_6:
.asciz "wd"
.size .L__unnamed_6, 3
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__gpu_bc_chargePdS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym perturb
.addrsig_sym charge0
.addrsig_sym w0
.addrsig_sym ws
.addrsig_sym wd
.addrsig_sym _Z13gpu_bc_chargePdS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void assisted_activation2_kernel(float alpha, float *output, float *gt_gpu, float *a_avg_gpu, int size, int channels, int batches)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int xy = i % size;
int b = i / size;
float beta = 1 - alpha;
if (b < batches) {
for (int c = 0; c < channels; ++c) {
if(gt_gpu[i] == 0)
output[xy + size*(c + channels*b)] *= beta;
}
}
} | code for sm_80
Function : _Z27assisted_activation2_kernelfPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x180] ; /* 0x0000600000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R0, R4 ; /* 0x0000000400007213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00b0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fca00078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R5, R3, R0, RZ ; /* 0x0000000003057227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*0100*/ IMAD R0, R7, R3, R0 ; /* 0x0000000307007224 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f24070 */
/*0120*/ @!P1 IADD3 R0, R0, -R7.reuse, RZ ; /* 0x8000000700009210 */
/* 0x080fe40007ffe0ff */
/*0130*/ @!P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105059810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f06070 */
/*0150*/ LOP3.LUT R0, R4, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600004007a12 */
/* 0x000fe400078e3cff */
/*0160*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f25270 */
/*0170*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f46270 */
/*0180*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff007624 */
/* 0x000fcc00078e00ff */
/*0190*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f06270 */
/*01b0*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*01c0*/ @!P1 LOP3.LUT R5, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff059a12 */
/* 0x000fc800078e33ff */
/*01d0*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x188], !P0 ; /* 0x0000620005007a0c */
/* 0x000fda0004706670 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a05 */
/*0210*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0230*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0240*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0250*/ IMAD R7, R7, c[0x0][0x180], R4 ; /* 0x0000600007077a24 */
/* 0x000fe200078e0204 */
/*0260*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.WIDE R2, R4, R3, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fe200078e0203 */
/*0280*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fc60000000f00 */
/*0290*/ FADD R4, -R8, 1 ; /* 0x3f80000008047421 */
/* 0x000fca0000000100 */
/*02a0*/ @!P0 BRA 0x5f0 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD R8, R5, c[0x0][0x184], RZ ; /* 0x0000610005087a24 */
/* 0x000fe200078e02ff */
/*02c0*/ IADD3 R9, R0, -c[0x0][0x184], RZ ; /* 0x8000610000097a10 */
/* 0x000fe20007ffe0ff */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*02e0*/ IADD3 R12, R8.reuse, 0x2, RZ ; /* 0x00000002080c7810 */
/* 0x040fe40007ffe0ff */
/*02f0*/ IADD3 R10, R8.reuse, 0x3, RZ ; /* 0x00000003080a7810 */
/* 0x040fe40007ffe0ff */
/*0300*/ IADD3 R14, R8, 0x1, RZ ; /* 0x00000001080e7810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD R11, R12, c[0x0][0x180], R7.reuse ; /* 0x000060000c0b7a24 */
/* 0x100fe400078e0207 */
/*0320*/ IMAD R8, R8, c[0x0][0x180], R7.reuse ; /* 0x0000600008087a24 */
/* 0x100fe400078e0207 */
/*0330*/ IMAD R10, R10, c[0x0][0x180], R7.reuse ; /* 0x000060000a0a7a24 */
/* 0x100fe400078e0207 */
/*0340*/ IMAD R12, R14, c[0x0][0x180], R7 ; /* 0x000060000e0c7a24 */
/* 0x000fc400078e0207 */
/*0350*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0360*/ FSETP.NEU.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720b */
/* 0x004fda0003f0d000 */
/*0370*/ @!P0 MOV R15, 0x4 ; /* 0x00000004000f8802 */
/* 0x000fca0000000f00 */
/*0380*/ @!P0 IMAD.WIDE R14, R8, R15, c[0x0][0x168] ; /* 0x00005a00080e8625 */
/* 0x000fca00078e020f */
/*0390*/ @!P0 LDG.E R13, [R14.64] ; /* 0x000000040e0d8981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ @!P0 FMUL R13, R13, R4 ; /* 0x000000040d0d8220 */
/* 0x004fca0000400000 */
/*03b0*/ @!P0 STG.E [R14.64], R13 ; /* 0x0000000d0e008986 */
/* 0x0001e8000c101904 */
/*03c0*/ @!P0 LDG.E R16, [R2.64] ; /* 0x0000000402108981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ BSSY B0, 0x480 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*03e0*/ @!P0 FSETP.NEU.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000820b */
/* 0x004fda0003f0d000 */
/*03f0*/ @P0 BRA 0x470 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0400*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x001fc800078e00ff */
/*0410*/ IMAD.WIDE R14, R12, R15, c[0x0][0x168] ; /* 0x00005a000c0e7625 */
/* 0x000fca00078e020f */
/*0420*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x000ea4000c1e1900 */
/*0430*/ FMUL R13, R13, R4 ; /* 0x000000040d0d7220 */
/* 0x004fca0000400000 */
/*0440*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0001e8000c101904 */
/*0450*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1900 */
/*0460*/ FSETP.NEU.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720b */
/* 0x004fd00003f0d000 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0480*/ BSSY B0, 0x520 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0490*/ @P0 BRA 0x510 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*04a0*/ HFMA2.MMA R14, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0e7435 */
/* 0x000fd400000001ff */
/*04b0*/ IMAD.WIDE R14, R11, R14, c[0x0][0x168] ; /* 0x00005a000b0e7625 */
/* 0x000fca00078e020e */
/*04c0*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x000ea4000c1e1900 */
/*04d0*/ FMUL R13, R13, R4 ; /* 0x000000040d0d7220 */
/* 0x004fca0000400000 */
/*04e0*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0001e8000c101904 */
/*04f0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1900 */
/*0500*/ FSETP.NEU.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720b */
/* 0x004fd00003f0d000 */
/*0510*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0520*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fc800078e00ff */
/*0530*/ @!P0 IMAD.WIDE R14, R10, R17, c[0x0][0x168] ; /* 0x00005a000a0e8625 */
/* 0x000fca00078e0211 */
/*0540*/ @!P0 LDG.E R13, [R14.64] ; /* 0x000000040e0d8981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD R11, R17.reuse, c[0x0][0x180], R11 ; /* 0x00006000110b7a24 */
/* 0x040fe400078e020b */
/*0570*/ IMAD R12, R17, c[0x0][0x180], R12 ; /* 0x00006000110c7a24 */
/* 0x000fe200078e020c */
/*0580*/ IADD3 R16, R9, R6, RZ ; /* 0x0000000609107210 */
/* 0x000fe20007ffe0ff */
/*0590*/ IMAD R8, R17.reuse, c[0x0][0x180], R8 ; /* 0x0000600011087a24 */
/* 0x040fe400078e0208 */
/*05a0*/ IMAD R10, R17, c[0x0][0x180], R10 ; /* 0x00006000110a7a24 */
/* 0x000fe400078e020a */
/*05b0*/ @!P0 FMUL R13, R13, R4 ; /* 0x000000040d0d8220 */
/* 0x004fca0000400000 */
/*05c0*/ @!P0 STG.E [R14.64], R13 ; /* 0x0000000d0e008986 */
/* 0x0001e2000c101904 */
/*05d0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fda0003f05270 */
/*05e0*/ @P0 BRA 0x350 ; /* 0xfffffd6000000947 */
/* 0x001fea000383ffff */
/*05f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0600*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0610*/ IMAD R6, R5, c[0x0][0x184], R6 ; /* 0x0000610005067a24 */
/* 0x000fc800078e0206 */
/*0620*/ IMAD R5, R6, c[0x0][0x180], R7 ; /* 0x0000600006057a24 */
/* 0x000fe400078e0207 */
/*0630*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea4000c1e1900 */
/*0640*/ FSETP.NEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x004fda0003f0d000 */
/*0650*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff068424 */
/* 0x000fc800078e00ff */
/*0660*/ @!P0 IMAD.WIDE R6, R5, R6, c[0x0][0x168] ; /* 0x00005a0005068625 */
/* 0x000fca00078e0206 */
/*0670*/ @!P0 LDG.E R9, [R6.64] ; /* 0x0000000406098981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0690*/ IADD3 R5, R5, c[0x0][0x180], RZ ; /* 0x0000600005057a10 */
/* 0x000fe20007ffe0ff */
/*06a0*/ @!P0 FMUL R9, R9, R4 ; /* 0x0000000409098220 */
/* 0x004fca0000400000 */
/*06b0*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x0001e2000c101904 */
/*06c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*06d0*/ @P0 BRA 0x630 ; /* 0xffffff5000000947 */
/* 0x001fea000383ffff */
/*06e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06f0*/ BRA 0x6f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void assisted_activation2_kernel(float alpha, float *output, float *gt_gpu, float *a_avg_gpu, int size, int channels, int batches)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int xy = i % size;
int b = i / size;
float beta = 1 - alpha;
if (b < batches) {
for (int c = 0; c < channels; ++c) {
if(gt_gpu[i] == 0)
output[xy + size*(c + channels*b)] *= beta;
}
}
} | .file "tmpxft_000313f5_00000000-6_assisted_activation2_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii
.type _Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii, @function
_Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 44(%rsp)
movq %rdi, 32(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27assisted_activation2_kernelfPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii, .-_Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii
.globl _Z27assisted_activation2_kernelfPfS_S_iii
.type _Z27assisted_activation2_kernelfPfS_S_iii, @function
_Z27assisted_activation2_kernelfPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27assisted_activation2_kernelfPfS_S_iii, .-_Z27assisted_activation2_kernelfPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27assisted_activation2_kernelfPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27assisted_activation2_kernelfPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void assisted_activation2_kernel(float alpha, float *output, float *gt_gpu, float *a_avg_gpu, int size, int channels, int batches)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int xy = i % size;
int b = i / size;
float beta = 1 - alpha;
if (b < batches) {
for (int c = 0; c < channels; ++c) {
if(gt_gpu[i] == 0)
output[xy + size*(c + channels*b)] *= beta;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void assisted_activation2_kernel(float alpha, float *output, float *gt_gpu, float *a_avg_gpu, int size, int channels, int batches)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int xy = i % size;
int b = i / size;
float beta = 1 - alpha;
if (b < batches) {
for (int c = 0; c < channels; ++c) {
if(gt_gpu[i] == 0)
output[xy + size*(c + channels*b)] *= beta;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void assisted_activation2_kernel(float alpha, float *output, float *gt_gpu, float *a_avg_gpu, int size, int channels, int batches)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int xy = i % size;
int b = i / size;
float beta = 1 - alpha;
if (b < batches) {
for (int c = 0; c < channels; ++c) {
if(gt_gpu[i] == 0)
output[xy + size*(c + channels*b)] *= beta;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27assisted_activation2_kernelfPfS_S_iii
.globl _Z27assisted_activation2_kernelfPfS_S_iii
.p2align 8
.type _Z27assisted_activation2_kernelfPfS_S_iii,@function
_Z27assisted_activation2_kernelfPfS_S_iii:
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s4, s6
s_and_b32 s3, s3, 0xffff
s_xor_b32 s7, s7, s6
v_cvt_f32_u32_e32 v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s7
s_cmp_gt_i32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s3, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v3, v0
v_add_nc_u32_e32 v4, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s6, v2
v_add_nc_u32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v3, v0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_cmp_le_u32_e32 vcc_lo, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s6, s[0:1], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v0, s4, v0
s_add_i32 s7, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mad_u64_u32 v[2:3], null, v0, s7, v[1:2]
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v4, 1.0, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v6, vcc_lo
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, s4, v2
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s5, 0
s_cbranch_scc0 .LBB0_5
.LBB0_3:
global_load_b32 v3, v[0:1], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 0, v3
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v4, v3
global_store_b32 v[5:6], v3, off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27assisted_activation2_kernelfPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27assisted_activation2_kernelfPfS_S_iii, .Lfunc_end0-_Z27assisted_activation2_kernelfPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27assisted_activation2_kernelfPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27assisted_activation2_kernelfPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void assisted_activation2_kernel(float alpha, float *output, float *gt_gpu, float *a_avg_gpu, int size, int channels, int batches)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
int xy = i % size;
int b = i / size;
float beta = 1 - alpha;
if (b < batches) {
for (int c = 0; c < channels; ++c) {
if(gt_gpu[i] == 0)
output[xy + size*(c + channels*b)] *= beta;
}
}
} | .text
.file "assisted_activation2_kernel.hip"
.globl _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii # -- Begin function _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii
.p2align 4, 0x90
.type _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii,@function
_Z42__device_stub__assisted_activation2_kernelfPfS_S_iii: # @_Z42__device_stub__assisted_activation2_kernelfPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 20(%rsp)
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27assisted_activation2_kernelfPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii, .Lfunc_end0-_Z42__device_stub__assisted_activation2_kernelfPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27assisted_activation2_kernelfPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27assisted_activation2_kernelfPfS_S_iii,@object # @_Z27assisted_activation2_kernelfPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z27assisted_activation2_kernelfPfS_S_iii
.p2align 3, 0x0
_Z27assisted_activation2_kernelfPfS_S_iii:
.quad _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii
.size _Z27assisted_activation2_kernelfPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27assisted_activation2_kernelfPfS_S_iii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27assisted_activation2_kernelfPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z27assisted_activation2_kernelfPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R7, c[0x0][0x180] ; /* 0x0000600000077a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e260000002500 */
/*0030*/ I2F.RP R0, R7 ; /* 0x0000000700007306 */
/* 0x000e620000209400 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e2e0000002100 */
/*0050*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0060*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fe200078e0205 */
/*0070*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fc80007ffe0ff */
/*0080*/ IABS R0, R4 ; /* 0x0000000400007213 */
/* 0x000fe40000000000 */
/*0090*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 0 ; /* 0x00000000ff027435 */
/* 0x001fe200000001ff */
/*00b0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00c0*/ IMAD R5, R6, R7, RZ ; /* 0x0000000706057224 */
/* 0x000fca00078e02ff */
/*00d0*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fcc00078e0002 */
/*00e0*/ IMAD.HI.U32 R5, R3, R0, RZ ; /* 0x0000000003057227 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD.MOV R3, RZ, RZ, -R5 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a05 */
/*0100*/ IMAD R0, R7, R3, R0 ; /* 0x0000000307007224 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GT.U32.AND P1, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x000fda0003f24070 */
/*0120*/ @!P1 IADD3 R0, R0, -R7.reuse, RZ ; /* 0x8000000700009210 */
/* 0x080fe40007ffe0ff */
/*0130*/ @!P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105059810 */
/* 0x000fe40007ffe0ff */
/*0140*/ ISETP.GE.U32.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f06070 */
/*0150*/ LOP3.LUT R0, R4, c[0x0][0x180], RZ, 0x3c, !PT ; /* 0x0000600004007a12 */
/* 0x000fe400078e3cff */
/*0160*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x180], PT ; /* 0x00006000ff007a0c */
/* 0x000fe40003f25270 */
/*0170*/ ISETP.GE.AND P2, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f46270 */
/*0180*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff007624 */
/* 0x000fcc00078e00ff */
/*0190*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*01a0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f06270 */
/*01b0*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*01c0*/ @!P1 LOP3.LUT R5, RZ, c[0x0][0x180], RZ, 0x33, !PT ; /* 0x00006000ff059a12 */
/* 0x000fc800078e33ff */
/*01d0*/ ISETP.GE.OR P0, PT, R5, c[0x0][0x188], !P0 ; /* 0x0000620005007a0c */
/* 0x000fda0004706670 */
/*01e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01f0*/ IADD3 R2, R0, -0x1, RZ ; /* 0xffffffff00027810 */
/* 0x000fe20007ffe0ff */
/*0200*/ IMAD.MOV R7, RZ, RZ, -R5 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a05 */
/*0210*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fe20000000f00 */
/*0220*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0230*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0240*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0250*/ IMAD R7, R7, c[0x0][0x180], R4 ; /* 0x0000600007077a24 */
/* 0x000fe200078e0204 */
/*0260*/ LOP3.LUT R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe200078ec0ff */
/*0270*/ IMAD.WIDE R2, R4, R3, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fe200078e0203 */
/*0280*/ MOV R6, RZ ; /* 0x000000ff00067202 */
/* 0x000fc60000000f00 */
/*0290*/ FADD R4, -R8, 1 ; /* 0x3f80000008047421 */
/* 0x000fca0000000100 */
/*02a0*/ @!P0 BRA 0x5f0 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*02b0*/ IMAD R8, R5, c[0x0][0x184], RZ ; /* 0x0000610005087a24 */
/* 0x000fe200078e02ff */
/*02c0*/ IADD3 R9, R0, -c[0x0][0x184], RZ ; /* 0x8000610000097a10 */
/* 0x000fe20007ffe0ff */
/*02d0*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fc600078e00ff */
/*02e0*/ IADD3 R12, R8.reuse, 0x2, RZ ; /* 0x00000002080c7810 */
/* 0x040fe40007ffe0ff */
/*02f0*/ IADD3 R10, R8.reuse, 0x3, RZ ; /* 0x00000003080a7810 */
/* 0x040fe40007ffe0ff */
/*0300*/ IADD3 R14, R8, 0x1, RZ ; /* 0x00000001080e7810 */
/* 0x000fe20007ffe0ff */
/*0310*/ IMAD R11, R12, c[0x0][0x180], R7.reuse ; /* 0x000060000c0b7a24 */
/* 0x100fe400078e0207 */
/*0320*/ IMAD R8, R8, c[0x0][0x180], R7.reuse ; /* 0x0000600008087a24 */
/* 0x100fe400078e0207 */
/*0330*/ IMAD R10, R10, c[0x0][0x180], R7.reuse ; /* 0x000060000a0a7a24 */
/* 0x100fe400078e0207 */
/*0340*/ IMAD R12, R14, c[0x0][0x180], R7 ; /* 0x000060000e0c7a24 */
/* 0x000fc400078e0207 */
/*0350*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000ea4000c1e1900 */
/*0360*/ FSETP.NEU.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720b */
/* 0x004fda0003f0d000 */
/*0370*/ @!P0 MOV R15, 0x4 ; /* 0x00000004000f8802 */
/* 0x000fca0000000f00 */
/*0380*/ @!P0 IMAD.WIDE R14, R8, R15, c[0x0][0x168] ; /* 0x00005a00080e8625 */
/* 0x000fca00078e020f */
/*0390*/ @!P0 LDG.E R13, [R14.64] ; /* 0x000000040e0d8981 */
/* 0x000ea4000c1e1900 */
/*03a0*/ @!P0 FMUL R13, R13, R4 ; /* 0x000000040d0d8220 */
/* 0x004fca0000400000 */
/*03b0*/ @!P0 STG.E [R14.64], R13 ; /* 0x0000000d0e008986 */
/* 0x0001e8000c101904 */
/*03c0*/ @!P0 LDG.E R16, [R2.64] ; /* 0x0000000402108981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ BSSY B0, 0x480 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*03e0*/ @!P0 FSETP.NEU.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000820b */
/* 0x004fda0003f0d000 */
/*03f0*/ @P0 BRA 0x470 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0400*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x001fc800078e00ff */
/*0410*/ IMAD.WIDE R14, R12, R15, c[0x0][0x168] ; /* 0x00005a000c0e7625 */
/* 0x000fca00078e020f */
/*0420*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x000ea4000c1e1900 */
/*0430*/ FMUL R13, R13, R4 ; /* 0x000000040d0d7220 */
/* 0x004fca0000400000 */
/*0440*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0001e8000c101904 */
/*0450*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1900 */
/*0460*/ FSETP.NEU.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720b */
/* 0x004fd00003f0d000 */
/*0470*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0480*/ BSSY B0, 0x520 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0490*/ @P0 BRA 0x510 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*04a0*/ HFMA2.MMA R14, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0e7435 */
/* 0x000fd400000001ff */
/*04b0*/ IMAD.WIDE R14, R11, R14, c[0x0][0x168] ; /* 0x00005a000b0e7625 */
/* 0x000fca00078e020e */
/*04c0*/ LDG.E R13, [R14.64] ; /* 0x000000040e0d7981 */
/* 0x000ea4000c1e1900 */
/*04d0*/ FMUL R13, R13, R4 ; /* 0x000000040d0d7220 */
/* 0x004fca0000400000 */
/*04e0*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0001e8000c101904 */
/*04f0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1900 */
/*0500*/ FSETP.NEU.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720b */
/* 0x004fd00003f0d000 */
/*0510*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x001fea0003800000 */
/*0520*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fc800078e00ff */
/*0530*/ @!P0 IMAD.WIDE R14, R10, R17, c[0x0][0x168] ; /* 0x00005a000a0e8625 */
/* 0x000fca00078e0211 */
/*0540*/ @!P0 LDG.E R13, [R14.64] ; /* 0x000000040e0d8981 */
/* 0x000ea2000c1e1900 */
/*0550*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe20007ffe0ff */
/*0560*/ IMAD R11, R17.reuse, c[0x0][0x180], R11 ; /* 0x00006000110b7a24 */
/* 0x040fe400078e020b */
/*0570*/ IMAD R12, R17, c[0x0][0x180], R12 ; /* 0x00006000110c7a24 */
/* 0x000fe200078e020c */
/*0580*/ IADD3 R16, R9, R6, RZ ; /* 0x0000000609107210 */
/* 0x000fe20007ffe0ff */
/*0590*/ IMAD R8, R17.reuse, c[0x0][0x180], R8 ; /* 0x0000600011087a24 */
/* 0x040fe400078e0208 */
/*05a0*/ IMAD R10, R17, c[0x0][0x180], R10 ; /* 0x00006000110a7a24 */
/* 0x000fe400078e020a */
/*05b0*/ @!P0 FMUL R13, R13, R4 ; /* 0x000000040d0d8220 */
/* 0x004fca0000400000 */
/*05c0*/ @!P0 STG.E [R14.64], R13 ; /* 0x0000000d0e008986 */
/* 0x0001e2000c101904 */
/*05d0*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fda0003f05270 */
/*05e0*/ @P0 BRA 0x350 ; /* 0xfffffd6000000947 */
/* 0x001fea000383ffff */
/*05f0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0600*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0610*/ IMAD R6, R5, c[0x0][0x184], R6 ; /* 0x0000610005067a24 */
/* 0x000fc800078e0206 */
/*0620*/ IMAD R5, R6, c[0x0][0x180], R7 ; /* 0x0000600006057a24 */
/* 0x000fe400078e0207 */
/*0630*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea4000c1e1900 */
/*0640*/ FSETP.NEU.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720b */
/* 0x004fda0003f0d000 */
/*0650*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff068424 */
/* 0x000fc800078e00ff */
/*0660*/ @!P0 IMAD.WIDE R6, R5, R6, c[0x0][0x168] ; /* 0x00005a0005068625 */
/* 0x000fca00078e0206 */
/*0670*/ @!P0 LDG.E R9, [R6.64] ; /* 0x0000000406098981 */
/* 0x000ea2000c1e1900 */
/*0680*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fe40007ffe0ff */
/*0690*/ IADD3 R5, R5, c[0x0][0x180], RZ ; /* 0x0000600005057a10 */
/* 0x000fe20007ffe0ff */
/*06a0*/ @!P0 FMUL R9, R9, R4 ; /* 0x0000000409098220 */
/* 0x004fca0000400000 */
/*06b0*/ @!P0 STG.E [R6.64], R9 ; /* 0x0000000906008986 */
/* 0x0001e2000c101904 */
/*06c0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*06d0*/ @P0 BRA 0x630 ; /* 0xffffff5000000947 */
/* 0x001fea000383ffff */
/*06e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06f0*/ BRA 0x6f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z27assisted_activation2_kernelfPfS_S_iii
.globl _Z27assisted_activation2_kernelfPfS_S_iii
.p2align 8
.type _Z27assisted_activation2_kernelfPfS_S_iii,@function
_Z27assisted_activation2_kernelfPfS_S_iii:
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x20
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s6, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s4, s6
s_and_b32 s3, s3, 0xffff
s_xor_b32 s7, s7, s6
v_cvt_f32_u32_e32 v1, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s7
s_cmp_gt_i32 s5, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v0, s3, v3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v0, v3, v0
v_add_nc_u32_e32 v4, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s6, v2
v_add_nc_u32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v0, v4, v0
v_mul_lo_u32 v3, v0, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
v_subrev_nc_u32_e32 v5, s7, v3
v_cmp_le_u32_e32 vcc_lo, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
v_cmp_le_u32_e32 vcc_lo, s7, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, 1, v0
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v0, v0, v2
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_cselect_b32 s2, -1, 0
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_5
s_clause 0x1
s_load_b32 s6, s[0:1], 0x0
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_mul_lo_u32 v0, s4, v0
s_add_i32 s7, s5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_mad_u64_u32 v[2:3], null, v0, s7, v[1:2]
s_waitcnt lgkmcnt(0)
v_sub_f32_e64 v4, 1.0, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v0, vcc_lo, s2, v5
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v6, vcc_lo
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
v_add_nc_u32_e32 v2, s4, v2
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s5, 0
s_cbranch_scc0 .LBB0_5
.LBB0_3:
global_load_b32 v3, v[0:1], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 0, v3
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_co_u32 v5, vcc_lo, s0, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v3, v4, v3
global_store_b32 v[5:6], v3, off
s_branch .LBB0_2
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z27assisted_activation2_kernelfPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z27assisted_activation2_kernelfPfS_S_iii, .Lfunc_end0-_Z27assisted_activation2_kernelfPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z27assisted_activation2_kernelfPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z27assisted_activation2_kernelfPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000313f5_00000000-6_assisted_activation2_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii
.type _Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii, @function
_Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 44(%rsp)
movq %rdi, 32(%rsp)
movq %rsi, 24(%rsp)
movq %rdx, 16(%rsp)
movl %ecx, 40(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z27assisted_activation2_kernelfPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii, .-_Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii
.globl _Z27assisted_activation2_kernelfPfS_S_iii
.type _Z27assisted_activation2_kernelfPfS_S_iii, @function
_Z27assisted_activation2_kernelfPfS_S_iii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z55__device_stub__Z27assisted_activation2_kernelfPfS_S_iiifPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z27assisted_activation2_kernelfPfS_S_iii, .-_Z27assisted_activation2_kernelfPfS_S_iii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z27assisted_activation2_kernelfPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z27assisted_activation2_kernelfPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "assisted_activation2_kernel.hip"
.globl _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii # -- Begin function _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii
.p2align 4, 0x90
.type _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii,@function
_Z42__device_stub__assisted_activation2_kernelfPfS_S_iii: # @_Z42__device_stub__assisted_activation2_kernelfPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movss %xmm0, 20(%rsp)
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 88(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z27assisted_activation2_kernelfPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii, .Lfunc_end0-_Z42__device_stub__assisted_activation2_kernelfPfS_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z27assisted_activation2_kernelfPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z27assisted_activation2_kernelfPfS_S_iii,@object # @_Z27assisted_activation2_kernelfPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z27assisted_activation2_kernelfPfS_S_iii
.p2align 3, 0x0
_Z27assisted_activation2_kernelfPfS_S_iii:
.quad _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii
.size _Z27assisted_activation2_kernelfPfS_S_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z27assisted_activation2_kernelfPfS_S_iii"
.size .L__unnamed_1, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z42__device_stub__assisted_activation2_kernelfPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z27assisted_activation2_kernelfPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //programma per calcolo prodotto puntuale tra 2 matrici
#include <cuda.h>
#include <stdio.h>
#include <iostream>
#include <time.h>
using namespace std;
//input: dimensioni M,N matrici (quindi questo darà il numero totale di thread nella griglia cuda) , n righe threads in blocco, n colonne threads in blocco
//NB: in cuda x indica la direzione righe, y le colonne
__host__ void calcolaProdPuntualeCPU(int *a,int *b,int *c,int m,int n){
for(int i=0;i<m;i++)
for(int j=0;j<n;j++){
c[i*n + j]=a[i*n + j] * b[i*n + j];
}
}
__host__ void stampaMatrice(int *a,int m,int n){
for(int i=0;i<m;i++){
for(int j=0;j<n;j++)
cout<<a[i*n + j]<<" ";
cout<<endl;
}
}
__global__ void calcolaProdPuntualeGPU(int *a,int *b,int *c,int m,int n){
//ottengo indice del thread SULL'INTERA GRIGLIA
//prima riga poi colonna
int indRiga = threadIdx.x + blockIdx.x * blockDim.x;
int indCol = threadIdx.y + blockIdx.y * blockDim.y;
if(indRiga<m && indCol<n)
c[indRiga * n + indCol] = a[indRiga * n + indCol]*b[indRiga * n + indCol];
}
void inizializzaMatrice(int *a,int m,int n){
srand((unsigned int)time(NULL));
for(int i=0;i<m;i++)
for(int j=0;j<n;j++)
a[i*n + j]=1+rand()%10;
}
int main(int argc,char *argv[]){
int m,n,totRigheThreadsInGriglia,totColonneThreadsInGriglia,nRigheThreadsInBlocco,nColonneThreadsInBlocco,nRigheBlocchiInGriglia,nColonneBlocchiInGriglia;
dim3 nBlocchiInGriglia_d3, nThreadsInBlocco_d3; //partono i default constructors
if(argc!=5){
m=5;
n=5;
nRigheThreadsInBlocco=2;
nColonneThreadsInBlocco=2;
}
else{
sscanf(argv[1],"%d",&m); //n righe matrice
sscanf(argv[2],"%d",&n); //n colonne matrice
sscanf(argv[3],"%d",&nRigheThreadsInBlocco); //n righe di un blocco (righe di threads)
sscanf(argv[4],"%d",&nColonneThreadsInBlocco); //n colonne di un blocco (colonne di threads)
}
//si noti che il totale di righe di threads e di colonne di threads nella griglia è uguale proprio al numero di righe matrice e di colonne (per scelta di distribuzione 1 cella = 1 thread)
totRigheThreadsInGriglia = m;
totColonneThreadsInGriglia = n;
//calcolo numero di blocchi (quindi il numero di righe di blocchi e di colonne di blocchi che costituiscono la nostra griglia cuda)
nRigheBlocchiInGriglia = totRigheThreadsInGriglia / nRigheThreadsInBlocco;
if(totRigheThreadsInGriglia % nRigheThreadsInBlocco != 0)
nRigheBlocchiInGriglia++;
nColonneBlocchiInGriglia = totColonneThreadsInGriglia / nColonneThreadsInBlocco;
if(totColonneThreadsInGriglia % nColonneThreadsInBlocco != 0)
nColonneBlocchiInGriglia++;
nBlocchiInGriglia_d3.x = nRigheBlocchiInGriglia; //x è per le righe in cuda
nBlocchiInGriglia_d3.y = nColonneBlocchiInGriglia; //y è per le colonne
nThreadsInBlocco_d3.x = nRigheThreadsInBlocco;
nThreadsInBlocco_d3.y = nColonneThreadsInBlocco;
int *h_a,*h_b,*h_c; //le matrici 2d, siccome i size sono decisi a runtime, e siccome per la mappatura ci serve che siano allocate sequenzialmente, sono allocate dinamicamente (heap host)
//come vettori monodimensionali che simulano l'allocazione per righe della struttura 2d
int *d_a,*d_b,*d_c;
//alloco le strutture sull'heap dell'host
h_a=(int *)malloc(m*n*sizeof(int));
h_b=(int *)malloc(m*n*sizeof(int));
h_c=(int *)malloc(m*n*sizeof(int));
inizializzaMatrice(h_a,m,n);
inizializzaMatrice(h_b,m,n);
calcolaProdPuntualeCPU(h_a,h_b,h_c,m,n);
stampaMatrice(h_c,m,n);
//alloco le strutture in memoria gpu
cudaMalloc((void **)&d_a,m*n*sizeof(int));
cudaMalloc((void **)&d_b,m*n*sizeof(int));
cudaMalloc((void **)&d_c,m*n*sizeof(int));
cudaMemset(d_c,0,m*n*sizeof(int)); //facoltativo
//copio sulla memoria gpu il contenuto delle matrici in memoria ordinaria
cudaMemcpy(d_a,h_a,m*n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,m*n*sizeof(int),cudaMemcpyHostToDevice);
//lancio kernel
calcolaProdPuntualeGPU<<< nBlocchiInGriglia_d3, nThreadsInBlocco_d3 >>>(d_a,d_b,d_c,m,n);
//ricopio il risultato nella memoria host
int *copiedFromGPU = (int *)malloc(n*m*sizeof(int));
cudaMemcpy(copiedFromGPU,d_c,n*m*sizeof(int),cudaMemcpyDeviceToHost);
//stampo
cout<<"---------------------------------------------"<<endl;
stampaMatrice(copiedFromGPU,m,n);
} | code for sm_80
Function : _Z22calcolaProdPuntualeGPUPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //programma per calcolo prodotto puntuale tra 2 matrici
#include <cuda.h>
#include <stdio.h>
#include <iostream>
#include <time.h>
using namespace std;
//input: dimensioni M,N matrici (quindi questo darà il numero totale di thread nella griglia cuda) , n righe threads in blocco, n colonne threads in blocco
//NB: in cuda x indica la direzione righe, y le colonne
__host__ void calcolaProdPuntualeCPU(int *a,int *b,int *c,int m,int n){
for(int i=0;i<m;i++)
for(int j=0;j<n;j++){
c[i*n + j]=a[i*n + j] * b[i*n + j];
}
}
__host__ void stampaMatrice(int *a,int m,int n){
for(int i=0;i<m;i++){
for(int j=0;j<n;j++)
cout<<a[i*n + j]<<" ";
cout<<endl;
}
}
__global__ void calcolaProdPuntualeGPU(int *a,int *b,int *c,int m,int n){
//ottengo indice del thread SULL'INTERA GRIGLIA
//prima riga poi colonna
int indRiga = threadIdx.x + blockIdx.x * blockDim.x;
int indCol = threadIdx.y + blockIdx.y * blockDim.y;
if(indRiga<m && indCol<n)
c[indRiga * n + indCol] = a[indRiga * n + indCol]*b[indRiga * n + indCol];
}
void inizializzaMatrice(int *a,int m,int n){
srand((unsigned int)time(NULL));
for(int i=0;i<m;i++)
for(int j=0;j<n;j++)
a[i*n + j]=1+rand()%10;
}
int main(int argc,char *argv[]){
int m,n,totRigheThreadsInGriglia,totColonneThreadsInGriglia,nRigheThreadsInBlocco,nColonneThreadsInBlocco,nRigheBlocchiInGriglia,nColonneBlocchiInGriglia;
dim3 nBlocchiInGriglia_d3, nThreadsInBlocco_d3; //partono i default constructors
if(argc!=5){
m=5;
n=5;
nRigheThreadsInBlocco=2;
nColonneThreadsInBlocco=2;
}
else{
sscanf(argv[1],"%d",&m); //n righe matrice
sscanf(argv[2],"%d",&n); //n colonne matrice
sscanf(argv[3],"%d",&nRigheThreadsInBlocco); //n righe di un blocco (righe di threads)
sscanf(argv[4],"%d",&nColonneThreadsInBlocco); //n colonne di un blocco (colonne di threads)
}
//si noti che il totale di righe di threads e di colonne di threads nella griglia è uguale proprio al numero di righe matrice e di colonne (per scelta di distribuzione 1 cella = 1 thread)
totRigheThreadsInGriglia = m;
totColonneThreadsInGriglia = n;
//calcolo numero di blocchi (quindi il numero di righe di blocchi e di colonne di blocchi che costituiscono la nostra griglia cuda)
nRigheBlocchiInGriglia = totRigheThreadsInGriglia / nRigheThreadsInBlocco;
if(totRigheThreadsInGriglia % nRigheThreadsInBlocco != 0)
nRigheBlocchiInGriglia++;
nColonneBlocchiInGriglia = totColonneThreadsInGriglia / nColonneThreadsInBlocco;
if(totColonneThreadsInGriglia % nColonneThreadsInBlocco != 0)
nColonneBlocchiInGriglia++;
nBlocchiInGriglia_d3.x = nRigheBlocchiInGriglia; //x è per le righe in cuda
nBlocchiInGriglia_d3.y = nColonneBlocchiInGriglia; //y è per le colonne
nThreadsInBlocco_d3.x = nRigheThreadsInBlocco;
nThreadsInBlocco_d3.y = nColonneThreadsInBlocco;
int *h_a,*h_b,*h_c; //le matrici 2d, siccome i size sono decisi a runtime, e siccome per la mappatura ci serve che siano allocate sequenzialmente, sono allocate dinamicamente (heap host)
//come vettori monodimensionali che simulano l'allocazione per righe della struttura 2d
int *d_a,*d_b,*d_c;
//alloco le strutture sull'heap dell'host
h_a=(int *)malloc(m*n*sizeof(int));
h_b=(int *)malloc(m*n*sizeof(int));
h_c=(int *)malloc(m*n*sizeof(int));
inizializzaMatrice(h_a,m,n);
inizializzaMatrice(h_b,m,n);
calcolaProdPuntualeCPU(h_a,h_b,h_c,m,n);
stampaMatrice(h_c,m,n);
//alloco le strutture in memoria gpu
cudaMalloc((void **)&d_a,m*n*sizeof(int));
cudaMalloc((void **)&d_b,m*n*sizeof(int));
cudaMalloc((void **)&d_c,m*n*sizeof(int));
cudaMemset(d_c,0,m*n*sizeof(int)); //facoltativo
//copio sulla memoria gpu il contenuto delle matrici in memoria ordinaria
cudaMemcpy(d_a,h_a,m*n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,m*n*sizeof(int),cudaMemcpyHostToDevice);
//lancio kernel
calcolaProdPuntualeGPU<<< nBlocchiInGriglia_d3, nThreadsInBlocco_d3 >>>(d_a,d_b,d_c,m,n);
//ricopio il risultato nella memoria host
int *copiedFromGPU = (int *)malloc(n*m*sizeof(int));
cudaMemcpy(copiedFromGPU,d_c,n*m*sizeof(int),cudaMemcpyDeviceToHost);
//stampo
cout<<"---------------------------------------------"<<endl;
stampaMatrice(copiedFromGPU,m,n);
} | .file "tmpxft_00007119_00000000-6_esercizio5.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22calcolaProdPuntualeCPUPiS_S_ii
.type _Z22calcolaProdPuntualeCPUPiS_S_ii, @function
_Z22calcolaProdPuntualeCPUPiS_S_ii:
.LFB3669:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdx, %r9
movl %ecx, %ebx
movl $0, %r11d
movl $0, %r10d
movslq %r8d, %rbp
jmp .L5
.L7:
movslq %r11d, %rcx
leaq 0(,%rcx,4), %rax
addq %rbp, %rcx
salq $2, %rcx
.L6:
movl (%rdi,%rax), %edx
imull (%rsi,%rax), %edx
movl %edx, (%r9,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %r10d
addl %r8d, %r11d
cmpl %r10d, %ebx
je .L3
.L5:
testl %r8d, %r8d
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z22calcolaProdPuntualeCPUPiS_S_ii, .-_Z22calcolaProdPuntualeCPUPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z13stampaMatricePiii
.type _Z13stampaMatricePiii, @function
_Z13stampaMatricePiii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
testl %esi, %esi
jle .L14
movl $0, %r15d
movl $0, %r14d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
jmp .L16
.L25:
call _ZSt16__throw_bad_castv@PLT
.L19:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L20:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, 12(%rsp)
je .L14
.L16:
cmpl $0, 8(%rsp)
jle .L22
movslq %r15d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %r12
.L17:
movl (%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L17
.L22:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L25
cmpb $0, 56(%rbx)
je .L19
movzbl 67(%rbx), %esi
jmp .L20
.L14:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z13stampaMatricePiii, .-_Z13stampaMatricePiii
.globl _Z18inizializzaMatricePiii
.type _Z18inizializzaMatricePiii, @function
_Z18inizializzaMatricePiii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movl %esi, %ebx
movl %esi, 4(%rsp)
movl %edx, %r14d
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
jle .L26
movl $0, %r13d
movl $0, %r12d
movslq %r14d, %rax
movq %rax, 8(%rsp)
jmp .L28
.L30:
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 8(%rsp), %rsi
addq %rsi, %rax
leaq (%r15,%rax,4), %rbp
.L29:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
.L31:
addl $1, %r12d
addl %r14d, %r13d
cmpl %r12d, 4(%rsp)
je .L26
.L28:
testl %r14d, %r14d
jg .L30
jmp .L31
.L26:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z18inizializzaMatricePiii, .-_Z18inizializzaMatricePiii
.globl _Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii
.type _Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii, @function
_Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22calcolaProdPuntualeGPUPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii, .-_Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii
.globl _Z22calcolaProdPuntualeGPUPiS_S_ii
.type _Z22calcolaProdPuntualeGPUPiS_S_ii, @function
_Z22calcolaProdPuntualeGPUPiS_S_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z22calcolaProdPuntualeGPUPiS_S_ii, .-_Z22calcolaProdPuntualeGPUPiS_S_ii
.section .rodata.str1.1
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "---------------------------------------------"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 56(%rsp)
movl $1, 68(%rsp)
cmpl $5, %edi
je .L43
movl $5, 8(%rsp)
movl $5, 12(%rsp)
movl $2, 16(%rsp)
movl $2, 20(%rsp)
movl $2, %edi
movl $5, %r13d
movl $5, %r14d
movl $2, %esi
.L44:
addl $1, %edi
.L45:
movl 20(%rsp), %ecx
movl %r13d, %eax
cltd
idivl %ecx
cmpl $1, %edx
sbbl $-1, %eax
movl %edi, 48(%rsp)
movl %eax, 52(%rsp)
movl %esi, 60(%rsp)
movl %ecx, 64(%rsp)
movl %r14d, %r12d
imull %r13d, %r12d
movslq %r12d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %r12
movl %r13d, %edx
movl %r14d, %esi
movq %rbp, %rdi
call _Z18inizializzaMatricePiii
movl 12(%rsp), %edx
movl 8(%rsp), %esi
movq %rbx, %rdi
call _Z18inizializzaMatricePiii
movl 12(%rsp), %r14d
movl 8(%rsp), %r13d
movl %r14d, %r8d
movl %r13d, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z22calcolaProdPuntualeCPUPiS_S_ii
movl %r14d, %edx
movl %r13d, %esi
movq %r12, %rdi
call _Z13stampaMatricePiii
movl 8(%rsp), %esi
imull 12(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 8(%rsp), %esi
imull 12(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl 8(%rsp), %esi
imull 12(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl 8(%rsp), %edx
imull 12(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl 8(%rsp), %edx
imull 12(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 8(%rsp), %edx
imull 12(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L47:
movl 12(%rsp), %ebx
imull 8(%rsp), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 12(%rsp), %edx
movl 8(%rsp), %esi
movq %rbp, %rdi
call _Z13stampaMatricePiii
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movq %rsi, %rbx
leaq 8(%rsp), %rdx
movq 8(%rsi), %rdi
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 12(%rsp), %rdx
movq 16(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 16(%rsp), %rdx
movq 24(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 20(%rsp), %rdx
movq 32(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movl 8(%rsp), %r14d
movl 12(%rsp), %r13d
movl 16(%rsp), %esi
movl %r14d, %eax
cltd
idivl %esi
movl %eax, %edi
testl %edx, %edx
je .L45
jmp .L44
.L50:
movl 12(%rsp), %r8d
movl 8(%rsp), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii
jmp .L47
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z22calcolaProdPuntualeGPUPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z22calcolaProdPuntualeGPUPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //programma per calcolo prodotto puntuale tra 2 matrici
#include <cuda.h>
#include <stdio.h>
#include <iostream>
#include <time.h>
using namespace std;
//input: dimensioni M,N matrici (quindi questo darà il numero totale di thread nella griglia cuda) , n righe threads in blocco, n colonne threads in blocco
//NB: in cuda x indica la direzione righe, y le colonne
__host__ void calcolaProdPuntualeCPU(int *a,int *b,int *c,int m,int n){
for(int i=0;i<m;i++)
for(int j=0;j<n;j++){
c[i*n + j]=a[i*n + j] * b[i*n + j];
}
}
__host__ void stampaMatrice(int *a,int m,int n){
for(int i=0;i<m;i++){
for(int j=0;j<n;j++)
cout<<a[i*n + j]<<" ";
cout<<endl;
}
}
__global__ void calcolaProdPuntualeGPU(int *a,int *b,int *c,int m,int n){
//ottengo indice del thread SULL'INTERA GRIGLIA
//prima riga poi colonna
int indRiga = threadIdx.x + blockIdx.x * blockDim.x;
int indCol = threadIdx.y + blockIdx.y * blockDim.y;
if(indRiga<m && indCol<n)
c[indRiga * n + indCol] = a[indRiga * n + indCol]*b[indRiga * n + indCol];
}
void inizializzaMatrice(int *a,int m,int n){
srand((unsigned int)time(NULL));
for(int i=0;i<m;i++)
for(int j=0;j<n;j++)
a[i*n + j]=1+rand()%10;
}
int main(int argc,char *argv[]){
int m,n,totRigheThreadsInGriglia,totColonneThreadsInGriglia,nRigheThreadsInBlocco,nColonneThreadsInBlocco,nRigheBlocchiInGriglia,nColonneBlocchiInGriglia;
dim3 nBlocchiInGriglia_d3, nThreadsInBlocco_d3; //partono i default constructors
if(argc!=5){
m=5;
n=5;
nRigheThreadsInBlocco=2;
nColonneThreadsInBlocco=2;
}
else{
sscanf(argv[1],"%d",&m); //n righe matrice
sscanf(argv[2],"%d",&n); //n colonne matrice
sscanf(argv[3],"%d",&nRigheThreadsInBlocco); //n righe di un blocco (righe di threads)
sscanf(argv[4],"%d",&nColonneThreadsInBlocco); //n colonne di un blocco (colonne di threads)
}
//si noti che il totale di righe di threads e di colonne di threads nella griglia è uguale proprio al numero di righe matrice e di colonne (per scelta di distribuzione 1 cella = 1 thread)
totRigheThreadsInGriglia = m;
totColonneThreadsInGriglia = n;
//calcolo numero di blocchi (quindi il numero di righe di blocchi e di colonne di blocchi che costituiscono la nostra griglia cuda)
nRigheBlocchiInGriglia = totRigheThreadsInGriglia / nRigheThreadsInBlocco;
if(totRigheThreadsInGriglia % nRigheThreadsInBlocco != 0)
nRigheBlocchiInGriglia++;
nColonneBlocchiInGriglia = totColonneThreadsInGriglia / nColonneThreadsInBlocco;
if(totColonneThreadsInGriglia % nColonneThreadsInBlocco != 0)
nColonneBlocchiInGriglia++;
nBlocchiInGriglia_d3.x = nRigheBlocchiInGriglia; //x è per le righe in cuda
nBlocchiInGriglia_d3.y = nColonneBlocchiInGriglia; //y è per le colonne
nThreadsInBlocco_d3.x = nRigheThreadsInBlocco;
nThreadsInBlocco_d3.y = nColonneThreadsInBlocco;
int *h_a,*h_b,*h_c; //le matrici 2d, siccome i size sono decisi a runtime, e siccome per la mappatura ci serve che siano allocate sequenzialmente, sono allocate dinamicamente (heap host)
//come vettori monodimensionali che simulano l'allocazione per righe della struttura 2d
int *d_a,*d_b,*d_c;
//alloco le strutture sull'heap dell'host
h_a=(int *)malloc(m*n*sizeof(int));
h_b=(int *)malloc(m*n*sizeof(int));
h_c=(int *)malloc(m*n*sizeof(int));
inizializzaMatrice(h_a,m,n);
inizializzaMatrice(h_b,m,n);
calcolaProdPuntualeCPU(h_a,h_b,h_c,m,n);
stampaMatrice(h_c,m,n);
//alloco le strutture in memoria gpu
cudaMalloc((void **)&d_a,m*n*sizeof(int));
cudaMalloc((void **)&d_b,m*n*sizeof(int));
cudaMalloc((void **)&d_c,m*n*sizeof(int));
cudaMemset(d_c,0,m*n*sizeof(int)); //facoltativo
//copio sulla memoria gpu il contenuto delle matrici in memoria ordinaria
cudaMemcpy(d_a,h_a,m*n*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b,m*n*sizeof(int),cudaMemcpyHostToDevice);
//lancio kernel
calcolaProdPuntualeGPU<<< nBlocchiInGriglia_d3, nThreadsInBlocco_d3 >>>(d_a,d_b,d_c,m,n);
//ricopio il risultato nella memoria host
int *copiedFromGPU = (int *)malloc(n*m*sizeof(int));
cudaMemcpy(copiedFromGPU,d_c,n*m*sizeof(int),cudaMemcpyDeviceToHost);
//stampo
cout<<"---------------------------------------------"<<endl;
stampaMatrice(copiedFromGPU,m,n);
} | //programma per calcolo prodotto puntuale tra 2 matrici
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <time.h>
using namespace std;
//input: dimensioni M,N matrici (quindi questo darà il numero totale di thread nella griglia cuda) , n righe threads in blocco, n colonne threads in blocco
//NB: in cuda x indica la direzione righe, y le colonne
__host__ void calcolaProdPuntualeCPU(int *a,int *b,int *c,int m,int n){
for(int i=0;i<m;i++)
for(int j=0;j<n;j++){
c[i*n + j]=a[i*n + j] * b[i*n + j];
}
}
__host__ void stampaMatrice(int *a,int m,int n){
for(int i=0;i<m;i++){
for(int j=0;j<n;j++)
cout<<a[i*n + j]<<" ";
cout<<endl;
}
}
__global__ void calcolaProdPuntualeGPU(int *a,int *b,int *c,int m,int n){
//ottengo indice del thread SULL'INTERA GRIGLIA
//prima riga poi colonna
int indRiga = threadIdx.x + blockIdx.x * blockDim.x;
int indCol = threadIdx.y + blockIdx.y * blockDim.y;
if(indRiga<m && indCol<n)
c[indRiga * n + indCol] = a[indRiga * n + indCol]*b[indRiga * n + indCol];
}
void inizializzaMatrice(int *a,int m,int n){
srand((unsigned int)time(NULL));
for(int i=0;i<m;i++)
for(int j=0;j<n;j++)
a[i*n + j]=1+rand()%10;
}
int main(int argc,char *argv[]){
int m,n,totRigheThreadsInGriglia,totColonneThreadsInGriglia,nRigheThreadsInBlocco,nColonneThreadsInBlocco,nRigheBlocchiInGriglia,nColonneBlocchiInGriglia;
dim3 nBlocchiInGriglia_d3, nThreadsInBlocco_d3; //partono i default constructors
if(argc!=5){
m=5;
n=5;
nRigheThreadsInBlocco=2;
nColonneThreadsInBlocco=2;
}
else{
sscanf(argv[1],"%d",&m); //n righe matrice
sscanf(argv[2],"%d",&n); //n colonne matrice
sscanf(argv[3],"%d",&nRigheThreadsInBlocco); //n righe di un blocco (righe di threads)
sscanf(argv[4],"%d",&nColonneThreadsInBlocco); //n colonne di un blocco (colonne di threads)
}
//si noti che il totale di righe di threads e di colonne di threads nella griglia è uguale proprio al numero di righe matrice e di colonne (per scelta di distribuzione 1 cella = 1 thread)
totRigheThreadsInGriglia = m;
totColonneThreadsInGriglia = n;
//calcolo numero di blocchi (quindi il numero di righe di blocchi e di colonne di blocchi che costituiscono la nostra griglia cuda)
nRigheBlocchiInGriglia = totRigheThreadsInGriglia / nRigheThreadsInBlocco;
if(totRigheThreadsInGriglia % nRigheThreadsInBlocco != 0)
nRigheBlocchiInGriglia++;
nColonneBlocchiInGriglia = totColonneThreadsInGriglia / nColonneThreadsInBlocco;
if(totColonneThreadsInGriglia % nColonneThreadsInBlocco != 0)
nColonneBlocchiInGriglia++;
nBlocchiInGriglia_d3.x = nRigheBlocchiInGriglia; //x è per le righe in cuda
nBlocchiInGriglia_d3.y = nColonneBlocchiInGriglia; //y è per le colonne
nThreadsInBlocco_d3.x = nRigheThreadsInBlocco;
nThreadsInBlocco_d3.y = nColonneThreadsInBlocco;
int *h_a,*h_b,*h_c; //le matrici 2d, siccome i size sono decisi a runtime, e siccome per la mappatura ci serve che siano allocate sequenzialmente, sono allocate dinamicamente (heap host)
//come vettori monodimensionali che simulano l'allocazione per righe della struttura 2d
int *d_a,*d_b,*d_c;
//alloco le strutture sull'heap dell'host
h_a=(int *)malloc(m*n*sizeof(int));
h_b=(int *)malloc(m*n*sizeof(int));
h_c=(int *)malloc(m*n*sizeof(int));
inizializzaMatrice(h_a,m,n);
inizializzaMatrice(h_b,m,n);
calcolaProdPuntualeCPU(h_a,h_b,h_c,m,n);
stampaMatrice(h_c,m,n);
//alloco le strutture in memoria gpu
hipMalloc((void **)&d_a,m*n*sizeof(int));
hipMalloc((void **)&d_b,m*n*sizeof(int));
hipMalloc((void **)&d_c,m*n*sizeof(int));
hipMemset(d_c,0,m*n*sizeof(int)); //facoltativo
//copio sulla memoria gpu il contenuto delle matrici in memoria ordinaria
hipMemcpy(d_a,h_a,m*n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,m*n*sizeof(int),hipMemcpyHostToDevice);
//lancio kernel
calcolaProdPuntualeGPU<<< nBlocchiInGriglia_d3, nThreadsInBlocco_d3 >>>(d_a,d_b,d_c,m,n);
//ricopio il risultato nella memoria host
int *copiedFromGPU = (int *)malloc(n*m*sizeof(int));
hipMemcpy(copiedFromGPU,d_c,n*m*sizeof(int),hipMemcpyDeviceToHost);
//stampo
cout<<"---------------------------------------------"<<endl;
stampaMatrice(copiedFromGPU,m,n);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //programma per calcolo prodotto puntuale tra 2 matrici
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <time.h>
using namespace std;
//input: dimensioni M,N matrici (quindi questo darà il numero totale di thread nella griglia cuda) , n righe threads in blocco, n colonne threads in blocco
//NB: in cuda x indica la direzione righe, y le colonne
__host__ void calcolaProdPuntualeCPU(int *a,int *b,int *c,int m,int n){
for(int i=0;i<m;i++)
for(int j=0;j<n;j++){
c[i*n + j]=a[i*n + j] * b[i*n + j];
}
}
__host__ void stampaMatrice(int *a,int m,int n){
for(int i=0;i<m;i++){
for(int j=0;j<n;j++)
cout<<a[i*n + j]<<" ";
cout<<endl;
}
}
__global__ void calcolaProdPuntualeGPU(int *a,int *b,int *c,int m,int n){
//ottengo indice del thread SULL'INTERA GRIGLIA
//prima riga poi colonna
int indRiga = threadIdx.x + blockIdx.x * blockDim.x;
int indCol = threadIdx.y + blockIdx.y * blockDim.y;
if(indRiga<m && indCol<n)
c[indRiga * n + indCol] = a[indRiga * n + indCol]*b[indRiga * n + indCol];
}
void inizializzaMatrice(int *a,int m,int n){
srand((unsigned int)time(NULL));
for(int i=0;i<m;i++)
for(int j=0;j<n;j++)
a[i*n + j]=1+rand()%10;
}
int main(int argc,char *argv[]){
int m,n,totRigheThreadsInGriglia,totColonneThreadsInGriglia,nRigheThreadsInBlocco,nColonneThreadsInBlocco,nRigheBlocchiInGriglia,nColonneBlocchiInGriglia;
dim3 nBlocchiInGriglia_d3, nThreadsInBlocco_d3; //partono i default constructors
if(argc!=5){
m=5;
n=5;
nRigheThreadsInBlocco=2;
nColonneThreadsInBlocco=2;
}
else{
sscanf(argv[1],"%d",&m); //n righe matrice
sscanf(argv[2],"%d",&n); //n colonne matrice
sscanf(argv[3],"%d",&nRigheThreadsInBlocco); //n righe di un blocco (righe di threads)
sscanf(argv[4],"%d",&nColonneThreadsInBlocco); //n colonne di un blocco (colonne di threads)
}
//si noti che il totale di righe di threads e di colonne di threads nella griglia è uguale proprio al numero di righe matrice e di colonne (per scelta di distribuzione 1 cella = 1 thread)
totRigheThreadsInGriglia = m;
totColonneThreadsInGriglia = n;
//calcolo numero di blocchi (quindi il numero di righe di blocchi e di colonne di blocchi che costituiscono la nostra griglia cuda)
nRigheBlocchiInGriglia = totRigheThreadsInGriglia / nRigheThreadsInBlocco;
if(totRigheThreadsInGriglia % nRigheThreadsInBlocco != 0)
nRigheBlocchiInGriglia++;
nColonneBlocchiInGriglia = totColonneThreadsInGriglia / nColonneThreadsInBlocco;
if(totColonneThreadsInGriglia % nColonneThreadsInBlocco != 0)
nColonneBlocchiInGriglia++;
nBlocchiInGriglia_d3.x = nRigheBlocchiInGriglia; //x è per le righe in cuda
nBlocchiInGriglia_d3.y = nColonneBlocchiInGriglia; //y è per le colonne
nThreadsInBlocco_d3.x = nRigheThreadsInBlocco;
nThreadsInBlocco_d3.y = nColonneThreadsInBlocco;
int *h_a,*h_b,*h_c; //le matrici 2d, siccome i size sono decisi a runtime, e siccome per la mappatura ci serve che siano allocate sequenzialmente, sono allocate dinamicamente (heap host)
//come vettori monodimensionali che simulano l'allocazione per righe della struttura 2d
int *d_a,*d_b,*d_c;
//alloco le strutture sull'heap dell'host
h_a=(int *)malloc(m*n*sizeof(int));
h_b=(int *)malloc(m*n*sizeof(int));
h_c=(int *)malloc(m*n*sizeof(int));
inizializzaMatrice(h_a,m,n);
inizializzaMatrice(h_b,m,n);
calcolaProdPuntualeCPU(h_a,h_b,h_c,m,n);
stampaMatrice(h_c,m,n);
//alloco le strutture in memoria gpu
hipMalloc((void **)&d_a,m*n*sizeof(int));
hipMalloc((void **)&d_b,m*n*sizeof(int));
hipMalloc((void **)&d_c,m*n*sizeof(int));
hipMemset(d_c,0,m*n*sizeof(int)); //facoltativo
//copio sulla memoria gpu il contenuto delle matrici in memoria ordinaria
hipMemcpy(d_a,h_a,m*n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,m*n*sizeof(int),hipMemcpyHostToDevice);
//lancio kernel
calcolaProdPuntualeGPU<<< nBlocchiInGriglia_d3, nThreadsInBlocco_d3 >>>(d_a,d_b,d_c,m,n);
//ricopio il risultato nella memoria host
int *copiedFromGPU = (int *)malloc(n*m*sizeof(int));
hipMemcpy(copiedFromGPU,d_c,n*m*sizeof(int),hipMemcpyDeviceToHost);
//stampo
cout<<"---------------------------------------------"<<endl;
stampaMatrice(copiedFromGPU,m,n);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22calcolaProdPuntualeGPUPiS_S_ii
.globl _Z22calcolaProdPuntualeGPUPiS_S_ii
.p2align 8
.type _Z22calcolaProdPuntualeGPUPiS_S_ii,@function
_Z22calcolaProdPuntualeGPUPiS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22calcolaProdPuntualeGPUPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22calcolaProdPuntualeGPUPiS_S_ii, .Lfunc_end0-_Z22calcolaProdPuntualeGPUPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22calcolaProdPuntualeGPUPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22calcolaProdPuntualeGPUPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //programma per calcolo prodotto puntuale tra 2 matrici
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <time.h>
using namespace std;
//input: dimensioni M,N matrici (quindi questo darà il numero totale di thread nella griglia cuda) , n righe threads in blocco, n colonne threads in blocco
//NB: in cuda x indica la direzione righe, y le colonne
__host__ void calcolaProdPuntualeCPU(int *a,int *b,int *c,int m,int n){
for(int i=0;i<m;i++)
for(int j=0;j<n;j++){
c[i*n + j]=a[i*n + j] * b[i*n + j];
}
}
__host__ void stampaMatrice(int *a,int m,int n){
for(int i=0;i<m;i++){
for(int j=0;j<n;j++)
cout<<a[i*n + j]<<" ";
cout<<endl;
}
}
__global__ void calcolaProdPuntualeGPU(int *a,int *b,int *c,int m,int n){
//ottengo indice del thread SULL'INTERA GRIGLIA
//prima riga poi colonna
int indRiga = threadIdx.x + blockIdx.x * blockDim.x;
int indCol = threadIdx.y + blockIdx.y * blockDim.y;
if(indRiga<m && indCol<n)
c[indRiga * n + indCol] = a[indRiga * n + indCol]*b[indRiga * n + indCol];
}
void inizializzaMatrice(int *a,int m,int n){
srand((unsigned int)time(NULL));
for(int i=0;i<m;i++)
for(int j=0;j<n;j++)
a[i*n + j]=1+rand()%10;
}
int main(int argc,char *argv[]){
int m,n,totRigheThreadsInGriglia,totColonneThreadsInGriglia,nRigheThreadsInBlocco,nColonneThreadsInBlocco,nRigheBlocchiInGriglia,nColonneBlocchiInGriglia;
dim3 nBlocchiInGriglia_d3, nThreadsInBlocco_d3; //partono i default constructors
if(argc!=5){
m=5;
n=5;
nRigheThreadsInBlocco=2;
nColonneThreadsInBlocco=2;
}
else{
sscanf(argv[1],"%d",&m); //n righe matrice
sscanf(argv[2],"%d",&n); //n colonne matrice
sscanf(argv[3],"%d",&nRigheThreadsInBlocco); //n righe di un blocco (righe di threads)
sscanf(argv[4],"%d",&nColonneThreadsInBlocco); //n colonne di un blocco (colonne di threads)
}
//si noti che il totale di righe di threads e di colonne di threads nella griglia è uguale proprio al numero di righe matrice e di colonne (per scelta di distribuzione 1 cella = 1 thread)
totRigheThreadsInGriglia = m;
totColonneThreadsInGriglia = n;
//calcolo numero di blocchi (quindi il numero di righe di blocchi e di colonne di blocchi che costituiscono la nostra griglia cuda)
nRigheBlocchiInGriglia = totRigheThreadsInGriglia / nRigheThreadsInBlocco;
if(totRigheThreadsInGriglia % nRigheThreadsInBlocco != 0)
nRigheBlocchiInGriglia++;
nColonneBlocchiInGriglia = totColonneThreadsInGriglia / nColonneThreadsInBlocco;
if(totColonneThreadsInGriglia % nColonneThreadsInBlocco != 0)
nColonneBlocchiInGriglia++;
nBlocchiInGriglia_d3.x = nRigheBlocchiInGriglia; //x è per le righe in cuda
nBlocchiInGriglia_d3.y = nColonneBlocchiInGriglia; //y è per le colonne
nThreadsInBlocco_d3.x = nRigheThreadsInBlocco;
nThreadsInBlocco_d3.y = nColonneThreadsInBlocco;
int *h_a,*h_b,*h_c; //le matrici 2d, siccome i size sono decisi a runtime, e siccome per la mappatura ci serve che siano allocate sequenzialmente, sono allocate dinamicamente (heap host)
//come vettori monodimensionali che simulano l'allocazione per righe della struttura 2d
int *d_a,*d_b,*d_c;
//alloco le strutture sull'heap dell'host
h_a=(int *)malloc(m*n*sizeof(int));
h_b=(int *)malloc(m*n*sizeof(int));
h_c=(int *)malloc(m*n*sizeof(int));
inizializzaMatrice(h_a,m,n);
inizializzaMatrice(h_b,m,n);
calcolaProdPuntualeCPU(h_a,h_b,h_c,m,n);
stampaMatrice(h_c,m,n);
//alloco le strutture in memoria gpu
hipMalloc((void **)&d_a,m*n*sizeof(int));
hipMalloc((void **)&d_b,m*n*sizeof(int));
hipMalloc((void **)&d_c,m*n*sizeof(int));
hipMemset(d_c,0,m*n*sizeof(int)); //facoltativo
//copio sulla memoria gpu il contenuto delle matrici in memoria ordinaria
hipMemcpy(d_a,h_a,m*n*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b,m*n*sizeof(int),hipMemcpyHostToDevice);
//lancio kernel
calcolaProdPuntualeGPU<<< nBlocchiInGriglia_d3, nThreadsInBlocco_d3 >>>(d_a,d_b,d_c,m,n);
//ricopio il risultato nella memoria host
int *copiedFromGPU = (int *)malloc(n*m*sizeof(int));
hipMemcpy(copiedFromGPU,d_c,n*m*sizeof(int),hipMemcpyDeviceToHost);
//stampo
cout<<"---------------------------------------------"<<endl;
stampaMatrice(copiedFromGPU,m,n);
} | .text
.file "esercizio5.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22calcolaProdPuntualeCPUPiS_S_ii # -- Begin function _Z22calcolaProdPuntualeCPUPiS_S_ii
.p2align 4, 0x90
.type _Z22calcolaProdPuntualeCPUPiS_S_ii,@function
_Z22calcolaProdPuntualeCPUPiS_S_ii: # @_Z22calcolaProdPuntualeCPUPiS_S_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
movl %r8d, %ecx
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %r8d, %r9d
cmpq %rax, %r10
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %r8d, %r8d
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r9d, %r14d
leaq (%rdx,%r14,4), %r11
leaq (%rsi,%r14,4), %rbx
leaq (%rdi,%r14,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %ebp
imull (%r14,%r15,4), %ebp
movl %ebp, (%r11,%r15,4)
incq %r15
cmpq %r15, %rcx
jne .LBB0_4
jmp .LBB0_5
.LBB0_6:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_7: # %._crit_edge21
retq
.Lfunc_end0:
.size _Z22calcolaProdPuntualeCPUPiS_S_ii, .Lfunc_end0-_Z22calcolaProdPuntualeCPUPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z13stampaMatricePiii # -- Begin function _Z13stampaMatricePiii
.p2align 4, 0x90
.type _Z13stampaMatricePiii,@function
_Z13stampaMatricePiii: # @_Z13stampaMatricePiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_10
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r13d
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
addl %ebx, %ebp
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB1_10
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r15)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_9
.LBB1_10: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z13stampaMatricePiii, .Lfunc_end1-_Z13stampaMatricePiii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii # -- Begin function _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii
.p2align 4, 0x90
.type _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii,@function
_Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii: # @_Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22calcolaProdPuntualeGPUPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii, .Lfunc_end2-_Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z18inizializzaMatricePiii # -- Begin function _Z18inizializzaMatricePiii
.p2align 4, 0x90
.type _Z18inizializzaMatricePiii,@function
_Z18inizializzaMatricePiii: # @_Z18inizializzaMatricePiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, 8(%rsp) # 8-byte Spill
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebx, %r13d
xorl %ebp, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rbp
addl %ebx, %r15d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r15d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z18inizializzaMatricePiii, .Lfunc_end3-_Z18inizializzaMatricePiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB4_1
# %bb.2:
movq 8(%rsi), %rdi
leaq 4(%rsp), %rdx
movq %rsi, %rbx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
movq %rsp, %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 24(%rbx), %rdi
leaq 12(%rsp), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 32(%rbx), %rdi
leaq 8(%rsp), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
jmp .LBB4_3
.LBB4_1:
movl $5, 4(%rsp)
movl $5, (%rsp)
movl $2, 12(%rsp)
movl $2, 8(%rsp)
.LBB4_3:
movl 4(%rsp), %ebp
movl (%rsp), %ebx
movl 12(%rsp), %ecx
movl %ebp, %eax
cltd
movq %rcx, 88(%rsp) # 8-byte Spill
idivl %ecx
# kill: def $eax killed $eax def $rax
cmpl $1, %edx
sbbl $-1, %eax
movq %rax, 80(%rsp) # 8-byte Spill
movl 8(%rsp), %ecx
movl %ebx, %eax
cltd
movq %rcx, 56(%rsp) # 8-byte Spill
idivl %ecx
# kill: def $eax killed $eax def $rax
cmpl $1, %edx
sbbl $-1, %eax
movq %rax, 48(%rsp) # 8-byte Spill
movl %ebx, %eax
imull %ebp, %eax
movslq %eax, %r13
shlq $2, %r13
movq %r13, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB4_9
# %bb.4: # %.preheader.lr.ph.i
xorl %r13d, %r13d
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_8: # %._crit_edge.i
# in Loop: Header=BB4_5 Depth=1
incq %r13
addl %ebx, %r14d
cmpq %rbp, %r13
je .LBB4_9
.LBB4_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
testl %ebx, %ebx
jle .LBB4_8
# %bb.6: # %.lr.ph.i
# in Loop: Header=BB4_5 Depth=1
movl %r14d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_7: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r15,%r12,4)
incq %r12
cmpq %r12, %rbx
jne .LBB4_7
jmp .LBB4_8
.LBB4_9: # %_Z18inizializzaMatricePiii.exit
shlq $32, 48(%rsp) # 8-byte Folded Spill
shlq $32, 56(%rsp) # 8-byte Folded Spill
movl 4(%rsp), %ebx
movl (%rsp), %ebp
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebx, %ebx
jle .LBB4_15
# %bb.10: # %.preheader.lr.ph.i33
xorl %r13d, %r13d
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_14: # %._crit_edge.i37
# in Loop: Header=BB4_11 Depth=1
incq %r13
addl %ebp, %r14d
cmpq %rbx, %r13
je .LBB4_15
.LBB4_11: # %.preheader.i35
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
testl %ebp, %ebp
jle .LBB4_14
# %bb.12: # %.lr.ph.i40
# in Loop: Header=BB4_11 Depth=1
movl %r14d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_11 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r15,%r12,4)
incq %r12
cmpq %r12, %rbp
jne .LBB4_13
jmp .LBB4_14
.LBB4_15: # %_Z18inizializzaMatricePiii.exit45
movq 48(%rsp), %r14 # 8-byte Reload
addq 80(%rsp), %r14 # 8-byte Folded Reload
movq 56(%rsp), %rbx # 8-byte Reload
addq 88(%rsp), %rbx # 8-byte Folded Reload
movl 4(%rsp), %esi
movl (%rsp), %edx
testl %esi, %esi
movq 96(%rsp), %rdi # 8-byte Reload
jle .LBB4_21
# %bb.16: # %.preheader.lr.ph.i46
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB4_17
.p2align 4, 0x90
.LBB4_20: # %._crit_edge.i48
# in Loop: Header=BB4_17 Depth=1
incq %rcx
addl %edx, %eax
cmpq %rsi, %rcx
je .LBB4_21
.LBB4_17: # %.preheader.i47
# =>This Loop Header: Depth=1
# Child Loop BB4_19 Depth 2
testl %edx, %edx
jle .LBB4_20
# %bb.18: # %.lr.ph.i49
# in Loop: Header=BB4_17 Depth=1
movl %eax, %r9d
leaq (%rdi,%r9,4), %r15
movq 24(%rsp), %r8 # 8-byte Reload
leaq (%r8,%r9,4), %r8
movq 16(%rsp), %r10 # 8-byte Reload
leaq (%r10,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_19: # Parent Loop BB4_17 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r8,%r10,4), %r11d
imull (%r9,%r10,4), %r11d
movl %r11d, (%r15,%r10,4)
incq %r10
cmpq %r10, %rdx
jne .LBB4_19
jmp .LBB4_20
.LBB4_21: # %_Z22calcolaProdPuntualeCPUPiS_S_ii.exit
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
callq _Z13stampaMatricePiii
movslq 4(%rsp), %rax
movslq (%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 72(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq (%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq (%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movslq 4(%rsp), %rax
movslq (%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
xorl %esi, %esi
callq hipMemset
movq 72(%rsp), %rdi
movslq 4(%rsp), %rax
movslq (%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 16(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
movslq 4(%rsp), %rax
movslq (%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 24(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 32(%rsp), %rdx
movl 4(%rsp), %esi
movl (%rsp), %edi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 44(%rsp)
movl %edi, 40(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 44(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z22calcolaProdPuntualeGPUPiS_S_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_23:
movslq (%rsp), %rax
movslq 4(%rsp), %r14
imulq %rax, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq 32(%rsp), %rsi
movq %rax, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB4_28
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB4_26
# %bb.25:
movzbl 67(%r14), %eax
jmp .LBB4_27
.LBB4_26:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 4(%rsp), %esi
movl (%rsp), %edx
movq %rbx, %rdi
callq _Z13stampaMatricePiii
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_28:
.cfi_def_cfa_offset 272
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22calcolaProdPuntualeGPUPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z22calcolaProdPuntualeGPUPiS_S_ii,@object # @_Z22calcolaProdPuntualeGPUPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z22calcolaProdPuntualeGPUPiS_S_ii
.p2align 3, 0x0
_Z22calcolaProdPuntualeGPUPiS_S_ii:
.quad _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii
.size _Z22calcolaProdPuntualeGPUPiS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "---------------------------------------------"
.size .L.str.2, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22calcolaProdPuntualeGPUPiS_S_ii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z22calcolaProdPuntualeGPUPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22calcolaProdPuntualeGPUPiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e680000002100 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e620000002500 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R5, c[0x0][0x0], R0 ; /* 0x0000000005007a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ IMAD R9, R4, R3, RZ ; /* 0x0000000304097224 */
/* 0x004fca00078e02ff */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z22calcolaProdPuntualeGPUPiS_S_ii
.globl _Z22calcolaProdPuntualeGPUPiS_S_ii
.p2align 8
.type _Z22calcolaProdPuntualeGPUPiS_S_ii,@function
_Z22calcolaProdPuntualeGPUPiS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_lo_u32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22calcolaProdPuntualeGPUPiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z22calcolaProdPuntualeGPUPiS_S_ii, .Lfunc_end0-_Z22calcolaProdPuntualeGPUPiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22calcolaProdPuntualeGPUPiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z22calcolaProdPuntualeGPUPiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00007119_00000000-6_esercizio5.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22calcolaProdPuntualeCPUPiS_S_ii
.type _Z22calcolaProdPuntualeCPUPiS_S_ii, @function
_Z22calcolaProdPuntualeCPUPiS_S_ii:
.LFB3669:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L11
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
movq %rdx, %r9
movl %ecx, %ebx
movl $0, %r11d
movl $0, %r10d
movslq %r8d, %rbp
jmp .L5
.L7:
movslq %r11d, %rcx
leaq 0(,%rcx,4), %rax
addq %rbp, %rcx
salq $2, %rcx
.L6:
movl (%rdi,%rax), %edx
imull (%rsi,%rax), %edx
movl %edx, (%r9,%rax)
addq $4, %rax
cmpq %rcx, %rax
jne .L6
.L8:
addl $1, %r10d
addl %r8d, %r11d
cmpl %r10d, %ebx
je .L3
.L5:
testl %r8d, %r8d
jg .L7
jmp .L8
.L3:
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore 3
.cfi_restore 6
ret
.cfi_endproc
.LFE3669:
.size _Z22calcolaProdPuntualeCPUPiS_S_ii, .-_Z22calcolaProdPuntualeCPUPiS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z13stampaMatricePiii
.type _Z13stampaMatricePiii, @function
_Z13stampaMatricePiii:
.LFB3670:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
testl %esi, %esi
jle .L14
movl $0, %r15d
movl $0, %r14d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq _ZSt4cout(%rip), %rbp
leaq .LC0(%rip), %r13
jmp .L16
.L25:
call _ZSt16__throw_bad_castv@PLT
.L19:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L20:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r14d
movl 8(%rsp), %eax
addl %eax, %r15d
cmpl %r14d, 12(%rsp)
je .L14
.L16:
cmpl $0, 8(%rsp)
jle .L22
movslq %r15d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %r12
.L17:
movl (%rbx), %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L17
.L22:
movq 0(%rbp), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbx
testq %rbx, %rbx
je .L25
cmpb $0, 56(%rbx)
je .L19
movzbl 67(%rbx), %esi
jmp .L20
.L14:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z13stampaMatricePiii, .-_Z13stampaMatricePiii
.globl _Z18inizializzaMatricePiii
.type _Z18inizializzaMatricePiii, @function
_Z18inizializzaMatricePiii:
.LFB3671:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r15
movl %esi, %ebx
movl %esi, 4(%rsp)
movl %edx, %r14d
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
testl %ebx, %ebx
jle .L26
movl $0, %r13d
movl $0, %r12d
movslq %r14d, %rax
movq %rax, 8(%rsp)
jmp .L28
.L30:
movslq %r13d, %rax
leaq (%r15,%rax,4), %rbx
movq 8(%rsp), %rsi
addq %rsi, %rax
leaq (%r15,%rax,4), %rbp
.L29:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
addl $1, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L29
.L31:
addl $1, %r12d
addl %r14d, %r13d
cmpl %r12d, 4(%rsp)
je .L26
.L28:
testl %r14d, %r14d
jg .L30
jmp .L31
.L26:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _Z18inizializzaMatricePiii, .-_Z18inizializzaMatricePiii
.globl _Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii
.type _Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii, @function
_Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L38
.L34:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L39
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22calcolaProdPuntualeGPUPiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L34
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii, .-_Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii
.globl _Z22calcolaProdPuntualeGPUPiS_S_ii
.type _Z22calcolaProdPuntualeGPUPiS_S_ii, @function
_Z22calcolaProdPuntualeGPUPiS_S_ii:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z22calcolaProdPuntualeGPUPiS_S_ii, .-_Z22calcolaProdPuntualeGPUPiS_S_ii
.section .rodata.str1.1
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "---------------------------------------------"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $80, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 56(%rsp)
movl $1, 68(%rsp)
cmpl $5, %edi
je .L43
movl $5, 8(%rsp)
movl $5, 12(%rsp)
movl $2, 16(%rsp)
movl $2, 20(%rsp)
movl $2, %edi
movl $5, %r13d
movl $5, %r14d
movl $2, %esi
.L44:
addl $1, %edi
.L45:
movl 20(%rsp), %ecx
movl %r13d, %eax
cltd
idivl %ecx
cmpl $1, %edx
sbbl $-1, %eax
movl %edi, 48(%rsp)
movl %eax, 52(%rsp)
movl %esi, 60(%rsp)
movl %ecx, 64(%rsp)
movl %r14d, %r12d
imull %r13d, %r12d
movslq %r12d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbx
movq %r12, %rdi
call malloc@PLT
movq %rax, %r12
movl %r13d, %edx
movl %r14d, %esi
movq %rbp, %rdi
call _Z18inizializzaMatricePiii
movl 12(%rsp), %edx
movl 8(%rsp), %esi
movq %rbx, %rdi
call _Z18inizializzaMatricePiii
movl 12(%rsp), %r14d
movl 8(%rsp), %r13d
movl %r14d, %r8d
movl %r13d, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq %rbp, %rdi
call _Z22calcolaProdPuntualeCPUPiS_S_ii
movl %r14d, %edx
movl %r13d, %esi
movq %r12, %rdi
call _Z13stampaMatricePiii
movl 8(%rsp), %esi
imull 12(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 24(%rsp), %rdi
call cudaMalloc@PLT
movl 8(%rsp), %esi
imull 12(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 32(%rsp), %rdi
call cudaMalloc@PLT
movl 8(%rsp), %esi
imull 12(%rsp), %esi
movslq %esi, %rsi
salq $2, %rsi
leaq 40(%rsp), %rdi
call cudaMalloc@PLT
movl 8(%rsp), %edx
imull 12(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl 8(%rsp), %edx
imull 12(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 8(%rsp), %edx
imull 12(%rsp), %edx
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl 68(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movq 48(%rsp), %rdi
movl 56(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L47:
movl 12(%rsp), %ebx
imull 8(%rsp), %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movl $2, %ecx
movq %rbx, %rdx
movq 40(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl 12(%rsp), %edx
movl 8(%rsp), %esi
movq %rbp, %rdi
call _Z13stampaMatricePiii
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movq %rsi, %rbx
leaq 8(%rsp), %rdx
movq 8(%rsi), %rdi
leaq .LC1(%rip), %rbp
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 12(%rsp), %rdx
movq 16(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 16(%rsp), %rdx
movq 24(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
leaq 20(%rsp), %rdx
movq 32(%rbx), %rdi
movq %rbp, %rsi
movl $0, %eax
call __isoc23_sscanf@PLT
movl 8(%rsp), %r14d
movl 12(%rsp), %r13d
movl 16(%rsp), %esi
movl %r14d, %eax
cltd
idivl %esi
movl %eax, %edi
testl %edx, %edx
je .L45
jmp .L44
.L50:
movl 12(%rsp), %r8d
movl 8(%rsp), %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z48__device_stub__Z22calcolaProdPuntualeGPUPiS_S_iiPiS_S_ii
jmp .L47
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z22calcolaProdPuntualeGPUPiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z22calcolaProdPuntualeGPUPiS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "esercizio5.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z22calcolaProdPuntualeCPUPiS_S_ii # -- Begin function _Z22calcolaProdPuntualeCPUPiS_S_ii
.p2align 4, 0x90
.type _Z22calcolaProdPuntualeCPUPiS_S_ii,@function
_Z22calcolaProdPuntualeCPUPiS_S_ii: # @_Z22calcolaProdPuntualeCPUPiS_S_ii
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_7
# %bb.1: # %.preheader.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %eax
movl %r8d, %ecx
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
incq %r10
addl %r8d, %r9d
cmpq %rax, %r10
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %r8d, %r8d
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r9d, %r14d
leaq (%rdx,%r14,4), %r11
leaq (%rsi,%r14,4), %rbx
leaq (%rdi,%r14,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%rbx,%r15,4), %ebp
imull (%r14,%r15,4), %ebp
movl %ebp, (%r11,%r15,4)
incq %r15
cmpq %r15, %rcx
jne .LBB0_4
jmp .LBB0_5
.LBB0_6:
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB0_7: # %._crit_edge21
retq
.Lfunc_end0:
.size _Z22calcolaProdPuntualeCPUPiS_S_ii, .Lfunc_end0-_Z22calcolaProdPuntualeCPUPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z13stampaMatricePiii # -- Begin function _Z13stampaMatricePiii
.p2align 4, 0x90
.type _Z13stampaMatricePiii,@function
_Z13stampaMatricePiii: # @_Z13stampaMatricePiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_10
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r13d
xorl %ebp, %ebp
xorl %r14d, %r14d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # in Loop: Header=BB1_2 Depth=1
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_2 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r14
addl %ebx, %ebp
cmpq 16(%rsp), %r14 # 8-byte Folded Reload
je .LBB1_10
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %ebx, %ebx
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %ebp, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r15,%r12,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r12
cmpq %r12, %r13
jne .LBB1_4
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_11
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_2 Depth=1
cmpb $0, 56(%r15)
je .LBB1_8
# %bb.7: # in Loop: Header=BB1_2 Depth=1
movzbl 67(%r15), %eax
jmp .LBB1_9
.LBB1_10: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z13stampaMatricePiii, .Lfunc_end1-_Z13stampaMatricePiii
.cfi_endproc
# -- End function
.globl _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii # -- Begin function _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii
.p2align 4, 0x90
.type _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii,@function
_Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii: # @_Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22calcolaProdPuntualeGPUPiS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii, .Lfunc_end2-_Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii
.cfi_endproc
# -- End function
.globl _Z18inizializzaMatricePiii # -- Begin function _Z18inizializzaMatricePiii
.p2align 4, 0x90
.type _Z18inizializzaMatricePiii,@function
_Z18inizializzaMatricePiii: # @_Z18inizializzaMatricePiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, 8(%rsp) # 8-byte Spill
xorl %r15d, %r15d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB3_6
# %bb.1: # %.preheader.lr.ph
movl %ebp, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %ebx, %r13d
xorl %ebp, %ebp
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_5: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %rbp
addl %ebx, %r15d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB3_6
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %ebx, %ebx
jle .LBB3_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %r15d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq %r12, %r13
jne .LBB3_4
jmp .LBB3_5
.LBB3_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z18inizializzaMatricePiii, .Lfunc_end3-_Z18inizializzaMatricePiii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $5, %edi
jne .LBB4_1
# %bb.2:
movq 8(%rsi), %rdi
leaq 4(%rsp), %rdx
movq %rsi, %rbx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 16(%rbx), %rdi
movq %rsp, %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 24(%rbx), %rdi
leaq 12(%rsp), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
movq 32(%rbx), %rdi
leaq 8(%rsp), %rdx
movl $.L.str.1, %esi
xorl %eax, %eax
callq __isoc23_sscanf
jmp .LBB4_3
.LBB4_1:
movl $5, 4(%rsp)
movl $5, (%rsp)
movl $2, 12(%rsp)
movl $2, 8(%rsp)
.LBB4_3:
movl 4(%rsp), %ebp
movl (%rsp), %ebx
movl 12(%rsp), %ecx
movl %ebp, %eax
cltd
movq %rcx, 88(%rsp) # 8-byte Spill
idivl %ecx
# kill: def $eax killed $eax def $rax
cmpl $1, %edx
sbbl $-1, %eax
movq %rax, 80(%rsp) # 8-byte Spill
movl 8(%rsp), %ecx
movl %ebx, %eax
cltd
movq %rcx, 56(%rsp) # 8-byte Spill
idivl %ecx
# kill: def $eax killed $eax def $rax
cmpl $1, %edx
sbbl $-1, %eax
movq %rax, 48(%rsp) # 8-byte Spill
movl %ebx, %eax
imull %ebp, %eax
movslq %eax, %r13
shlq $2, %r13
movq %r13, %rdi
callq malloc
movq %rax, 16(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 96(%rsp) # 8-byte Spill
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebp, %ebp
jle .LBB4_9
# %bb.4: # %.preheader.lr.ph.i
xorl %r13d, %r13d
jmp .LBB4_5
.p2align 4, 0x90
.LBB4_8: # %._crit_edge.i
# in Loop: Header=BB4_5 Depth=1
incq %r13
addl %ebx, %r14d
cmpq %rbp, %r13
je .LBB4_9
.LBB4_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_7 Depth 2
testl %ebx, %ebx
jle .LBB4_8
# %bb.6: # %.lr.ph.i
# in Loop: Header=BB4_5 Depth=1
movl %r14d, %eax
movq 16(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_7: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r15,%r12,4)
incq %r12
cmpq %r12, %rbx
jne .LBB4_7
jmp .LBB4_8
.LBB4_9: # %_Z18inizializzaMatricePiii.exit
shlq $32, 48(%rsp) # 8-byte Folded Spill
shlq $32, 56(%rsp) # 8-byte Folded Spill
movl 4(%rsp), %ebx
movl (%rsp), %ebp
xorl %r14d, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
testl %ebx, %ebx
jle .LBB4_15
# %bb.10: # %.preheader.lr.ph.i33
xorl %r13d, %r13d
jmp .LBB4_11
.p2align 4, 0x90
.LBB4_14: # %._crit_edge.i37
# in Loop: Header=BB4_11 Depth=1
incq %r13
addl %ebp, %r14d
cmpq %rbx, %r13
je .LBB4_15
.LBB4_11: # %.preheader.i35
# =>This Loop Header: Depth=1
# Child Loop BB4_13 Depth 2
testl %ebp, %ebp
jle .LBB4_14
# %bb.12: # %.lr.ph.i40
# in Loop: Header=BB4_11 Depth=1
movl %r14d, %eax
movq 24(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_13: # Parent Loop BB4_11 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
negl %ecx
addl %ecx, %eax
incl %eax
movl %eax, (%r15,%r12,4)
incq %r12
cmpq %r12, %rbp
jne .LBB4_13
jmp .LBB4_14
.LBB4_15: # %_Z18inizializzaMatricePiii.exit45
movq 48(%rsp), %r14 # 8-byte Reload
addq 80(%rsp), %r14 # 8-byte Folded Reload
movq 56(%rsp), %rbx # 8-byte Reload
addq 88(%rsp), %rbx # 8-byte Folded Reload
movl 4(%rsp), %esi
movl (%rsp), %edx
testl %esi, %esi
movq 96(%rsp), %rdi # 8-byte Reload
jle .LBB4_21
# %bb.16: # %.preheader.lr.ph.i46
xorl %eax, %eax
xorl %ecx, %ecx
jmp .LBB4_17
.p2align 4, 0x90
.LBB4_20: # %._crit_edge.i48
# in Loop: Header=BB4_17 Depth=1
incq %rcx
addl %edx, %eax
cmpq %rsi, %rcx
je .LBB4_21
.LBB4_17: # %.preheader.i47
# =>This Loop Header: Depth=1
# Child Loop BB4_19 Depth 2
testl %edx, %edx
jle .LBB4_20
# %bb.18: # %.lr.ph.i49
# in Loop: Header=BB4_17 Depth=1
movl %eax, %r9d
leaq (%rdi,%r9,4), %r15
movq 24(%rsp), %r8 # 8-byte Reload
leaq (%r8,%r9,4), %r8
movq 16(%rsp), %r10 # 8-byte Reload
leaq (%r10,%r9,4), %r9
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB4_19: # Parent Loop BB4_17 Depth=1
# => This Inner Loop Header: Depth=2
movl (%r8,%r10,4), %r11d
imull (%r9,%r10,4), %r11d
movl %r11d, (%r15,%r10,4)
incq %r10
cmpq %r10, %rdx
jne .LBB4_19
jmp .LBB4_20
.LBB4_21: # %_Z22calcolaProdPuntualeCPUPiS_S_ii.exit
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
callq _Z13stampaMatricePiii
movslq 4(%rsp), %rax
movslq (%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 72(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq (%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 64(%rsp), %rdi
callq hipMalloc
movslq 4(%rsp), %rax
movslq (%rsp), %rsi
imulq %rax, %rsi
shlq $2, %rsi
leaq 32(%rsp), %rdi
callq hipMalloc
movq 32(%rsp), %rdi
movslq 4(%rsp), %rax
movslq (%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
xorl %esi, %esi
callq hipMemset
movq 72(%rsp), %rdi
movslq 4(%rsp), %rax
movslq (%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 16(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
movslq 4(%rsp), %rax
movslq (%rsp), %rdx
imulq %rax, %rdx
shlq $2, %rdx
movq 24(%rsp), %rsi # 8-byte Reload
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_23
# %bb.22:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 32(%rsp), %rdx
movl 4(%rsp), %esi
movl (%rsp), %edi
movq %rax, 168(%rsp)
movq %rcx, 160(%rsp)
movq %rdx, 152(%rsp)
movl %esi, 44(%rsp)
movl %edi, 40(%rsp)
leaq 168(%rsp), %rax
movq %rax, 176(%rsp)
leaq 160(%rsp), %rax
movq %rax, 184(%rsp)
leaq 152(%rsp), %rax
movq %rax, 192(%rsp)
leaq 44(%rsp), %rax
movq %rax, 200(%rsp)
leaq 40(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rdi
leaq 120(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq 136(%rsp), %rsi
movl 144(%rsp), %edx
movq 120(%rsp), %rcx
movl 128(%rsp), %r8d
leaq 176(%rsp), %r9
movl $_Z22calcolaProdPuntualeGPUPiS_S_ii, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_23:
movslq (%rsp), %rax
movslq 4(%rsp), %r14
imulq %rax, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
movq 32(%rsp), %rsi
movq %rax, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $45, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB4_28
# %bb.24: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB4_26
# %bb.25:
movzbl 67(%r14), %eax
jmp .LBB4_27
.LBB4_26:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_27: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl 4(%rsp), %esi
movl (%rsp), %edx
movq %rbx, %rdi
callq _Z13stampaMatricePiii
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_28:
.cfi_def_cfa_offset 272
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22calcolaProdPuntualeGPUPiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z22calcolaProdPuntualeGPUPiS_S_ii,@object # @_Z22calcolaProdPuntualeGPUPiS_S_ii
.section .rodata,"a",@progbits
.globl _Z22calcolaProdPuntualeGPUPiS_S_ii
.p2align 3, 0x0
_Z22calcolaProdPuntualeGPUPiS_S_ii:
.quad _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii
.size _Z22calcolaProdPuntualeGPUPiS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "---------------------------------------------"
.size .L.str.2, 46
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z22calcolaProdPuntualeGPUPiS_S_ii"
.size .L__unnamed_1, 35
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z37__device_stub__calcolaProdPuntualeGPUPiS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z22calcolaProdPuntualeGPUPiS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <math.h>
#include <ctime>
#include <cmath>
#include <stdlib.h>
#include <fstream>
#include <vector>
#include <sstream>
#include <iomanip>
#include <algorithm>
#include <cuda.h>
#include <curand.h>
#include <curand_kernel.h>
#define PI 3.14159265358979323846
//this function initialises the kernel which constructs the mesh according to the independent path construction.
void mesh_generation(int b, int num_assets, double m, double X0[], double sigma[], double delta[], double asset_amount[], double* X, double strike, double r, double delta_t, curandState_t* States, curandState_t* statesi, int threads);
//this function initialises all the mesh weights kernels
void meshweights(double* W, double m, int b, double sigma[], double delta[], double r, double delta_t, double* X, int num_assets, double* weight_denominator);
//this function converts one dim vectors to one dim arrays
void one_dim_array(std::vector< double > &vals, double array[], int N);
//this function provides an indexing interface for 3-d matrices stored in 1 dim arrays
double* three_dim_index(double* matrix, int i, int j, int k, double m, int b, int num_assets);
//this function provides an indexing interface for 2-d matrices stored in 1 dim arrays
double* two_dim_index(double* vector, int i, int j, double m, int b);
//this function initialises the mesh estimator kernel
double MeshEstimator(double strike, double r, double delta_t, int b, double m, double* X, double* W, double* V, double asset_amount[], int num_assets);
//this function initialises the pathestimator kernel.
double PathEstimator(double strike, double r, double delta_t, int b, double m, double sigma[], double delta[], double X0[], double* X, double* weight_denominator, double* V, double asset_amount[], int num_assets, int Path_estimator_iterations, int iterator, int Final_iteration, curandState_t* States, curandState_t* states, int threads);
//this function prints results for 1-dim options to 'OneDimHighPayoff.txt'. These results can be plotted using the program 'OneDimPayoff.py'
void print_high_payoff(int b, double m, double* X, double* V, double asset_amount[], double* W );
//this function prints results for 1-dim options to 'stocksimulation.txt'. These results can be plotted using the program 'simulation.py'
void SimulationPaths(int b, double m, double* X, double* V, double asset_amount[], double* W, double x );
//this kernel initialises the random seeds on each thread
__global__ void initialise(unsigned int seed, curandState_t* states) {
int idx=blockDim.x*blockIdx.x + threadIdx.x;
// we have to initialize the state
curand_init(seed, idx, 0, &states[idx]);
}
int main(){
srand((unsigned)time(NULL));
//begin timer
clock_t begin=clock();
//read in parameters from setting.txt
std::ifstream setting( "settings.txt" );
std::string line;
std::vector<std::string> settings;
int linenumber=0;
while(std::getline( setting, line))
{
if(linenumber%2==1)
settings.push_back(line);
linenumber++;
}
setting.close();
int integer;
std::vector < double > X0V;
std::vector < double > deltaV;
std::vector <double> sigmaV;
std::vector <double> asset_amountV;
std::istringstream ss(settings[0]);
std::string token;
while(std::getline(ss, token, ','))
{
X0V.push_back(atof(token.c_str()));
}
double T = atof(settings[1].c_str());
double m = atof(settings[2].c_str());
double delta_t=T/m;
double v_0, V_0, vtotal_sum=0, Vtotal_sum=0;
double r= atof(settings[3].c_str());
std::istringstream ss2(settings[4]);
while(std::getline(ss2, token, ','))
{
deltaV.push_back(atof(token.c_str()));
}
std::istringstream ss3(settings[5]);
while(std::getline(ss3, token, ','))
{
sigmaV.push_back(atof(token.c_str()));
}
int Path_estimator_iterations=atof(settings[6].c_str());
double strike=atof(settings[7].c_str());
int b=atoi(settings[8].c_str());
int N=atoi(settings[9].c_str());
double quantile=atof(settings[10].c_str());
int num_assets=atof(settings[11].c_str());
std::istringstream ss4(settings[12]);
while(std::getline(ss4, token, ','))
{
asset_amountV.push_back(atof(token.c_str()));
}
if(X0V.size() != num_assets || sigmaV.size() != num_assets || deltaV.size() !=num_assets || asset_amountV.size() !=num_assets){
std::cout<<"Either the starting price, volatility, number of assets or dividend yield was not specified for all assets"<<std::endl;
exit (EXIT_FAILURE);
}
std::cout<<"The parameters of this simulation are:"<<std::endl;
//Print these values to screen
for(integer=0; integer<X0V.size(); integer++){
std::cout<<"Starting Price of Asset "<<integer<<" = "<<X0V[integer]<<std::endl;
}
std::cout<<"Time to Expiry="<<T<<"\n"<<"Number of Time Steps="<<m<<"\n"<<"Interest Rate="<<r<<std::endl;
for(integer=0; integer<sigmaV.size(); integer++){
std::cout<<"Volatility of Asset "<<integer<<" = "<<sigmaV[integer]<<std::endl;
}
for(integer=0; integer<deltaV.size(); integer++){
std::cout<<"Dividend Yield of Asset "<<integer<<" ="<<deltaV[integer]<<std::endl;
}
std::cout<<"Number of Iterations Over the Path Estimator="<<Path_estimator_iterations<<"\n"<<"Strike Price="<<strike<<"\n"<<"Nodes per Time Step="<<b<<"\n"<<"Number Mesh Replications="<<N<<"\n"<<"Number of Assets="<<num_assets<<std::endl;
for(integer=0; integer<asset_amountV.size(); integer++){
std::cout<<"Amount of Asset "<<integer<<" = "<<asset_amountV[integer]<<std::endl;
}
// CONVERT TO ARRAYS
double X0 [num_assets];
double delta [num_assets];
double sigma [num_assets];
double asset_amount [num_assets];
one_dim_array(X0V, X0, num_assets);
one_dim_array(deltaV, delta, num_assets);
one_dim_array(sigmaV, sigma, num_assets);
one_dim_array(asset_amountV, asset_amount, num_assets);
//V values from each iteration over meshes
std::vector< double > Vvector;
//v values from each iteration over meshes
std::vector< double > vvector;
//asset vector
std::vector< double > assets;
//1 d vector in Weightsgen for-loop
std:: vector<double> dim1temp;
std::vector<double> sortvector;
int m_int= (int)m;
//mesh matrix
double* X;
int X_dim = (m_int) * b * (num_assets);
X= new double[X_dim];
//weight matrix
double* W;
int W_dim = (m_int) * b * b;
W= new double[W_dim];
//high values matrix
double* V;
int V_dim = (m_int) * b;
V = new double[V_dim];
//weight denominator values
double* weight_denominator;
int denom_dim = (m_int-1) * b;
weight_denominator =new double[denom_dim];
//convert to log prices
for(int init=0; init<num_assets; init++){
X0[init]=log(X0[init]);
}
int threads=Path_estimator_iterations;
if(b>Path_estimator_iterations){
threads=b;
}
curandState_t* States;
States= new curandState_t[threads];
//for-loop over different meshes
for(int iterator=0; iterator<N; iterator++){
curandState_t* states;
cudaMalloc((void**) &states, threads * sizeof(curandState_t));
if(iterator==0){
dim3 gridDim((int)ceil(threads/512.0));
dim3 blockDim(512.0);
initialise<<<gridDim, blockDim>>>(time(0), states);
cudaDeviceSynchronize();
cudaMemcpy(States, states, sizeof(curandState_t)*threads, cudaMemcpyDeviceToHost);
}
else{cudaMemcpy(states, States, threads*sizeof(curandState_t), cudaMemcpyHostToDevice);}
mesh_generation(b, num_assets, m, X0, sigma, delta, asset_amount, X, strike, r, delta_t, States, states, threads);
meshweights(W, m, b, sigma, delta, r, delta_t, X, num_assets, weight_denominator);
double check=0;
//check all the weights from X0 are 1
for(int e=0; e<b; e++){
if(*three_dim_index(W, 0, e, 0, m, b, b)!=1){
std::cout<<"there is an error with the weights. check that W[0][k][0]'s =1"<<std::endl;
}
}
//check that the weights going into a node sum to 1
for(int q=1; q<m; q++){
for(int a=0; a<b; a++){
check=0;
for(int E=0; E<b; E++){
check+=*three_dim_index(W, (q), a, E, m, b, num_assets);
}
}
}
V_0=MeshEstimator(strike, r, delta_t, b, m, X, W, V, asset_amount, num_assets);
Vvector.push_back(V_0);//vector containing high bias option prices
Vtotal_sum+=V_0;
std::cout<<"High Bias price (V_0) for mesh iteration "<<iterator<<" is "<<V_0<<std::endl;
v_0=PathEstimator(strike, r, delta_t, b, m, sigma, delta, X0, X, weight_denominator, V, asset_amount, num_assets, Path_estimator_iterations, iterator, N, States, states, threads);
cudaDeviceReset();
vvector.push_back(v_0);
vtotal_sum+=v_0;
std::cout<<"Low Bias price (v_0) for mesh iteration "<<iterator<<" is "<<v_0<<std::endl;
}//this is the end of the loop over the whole process.
if(num_assets==1){
print_high_payoff(b, m, X, V, asset_amount,W);
SimulationPaths(b, m, X, V, asset_amount, W, X0[0] );
}
//Calculate V(N) and v(N)
V_0=(1/double(N))*Vtotal_sum;
v_0=(1/double(N))*vtotal_sum;
//calculate errors
double std_div_V=0, std_div_v=0, squaresumV=0, squaresumv=0, Verror=0, verror=0;
for(int h=0; h<N; h++){
squaresumV+=(Vvector[h]-V_0)*(Vvector[h]-V_0);
squaresumv+=(vvector[h]-v_0)*(vvector[h]-v_0);
}
std_div_V=sqrt((1/double(N))*squaresumV); //standard deviation of V
std_div_v=sqrt((1/double(N))*squaresumv); //standard deviation of v
double standardErrorV=std_div_V*(1/sqrt(double(N)));
double standardErrorv=std_div_v*(1/sqrt(double(N)));
Verror=quantile*standardErrorV;
verror=quantile*standardErrorv;
std::cout<<"V(N)_0="<<V_0<<std::endl;
std::cout<<"v(N)_0="<<v_0<<std::endl;
double pointEst=(V_0+v_0)/2;
double EstimatedError=((Verror+V_0)-(v_0-verror))/(2*pointEst);
clock_t end =clock();
double elapsedtime=double(end-begin) / CLOCKS_PER_SEC;
std::ofstream outFile("results.txt", std::ios_base::app | std::ios_base::out);
outFile << N <<"\t"<< b <<"\t"<< Path_estimator_iterations<<"\t"<<exp(X0[0])<<"\t" << v_0 <<"\t"<< standardErrorv <<"\t"<< V_0 <<"\t"<< standardErrorV <<"\t"<< v_0-verror<<"\t"<<Verror+V_0 <<"\t"<<pointEst<<"\t"<<EstimatedError<<"\t" <<elapsedtime<< std::endl;
outFile.close();
std::ofstream LoutFile("latexresults.txt", std::ios_base::app | std::ios_base::out);
LoutFile <<std::fixed<<std::setprecision(3) << N <<"&"<< b <<"&"<< Path_estimator_iterations<<"&"<<exp(X0[0])<<"&" << v_0 <<"&"<< standardErrorv <<"&"<< V_0 <<"&"<< standardErrorV <<"&"<< v_0-verror<<"&"<<Verror+V_0 <<"&"<<pointEst<<"&"<<EstimatedError<<"&" <<elapsedtime<< std::endl;
outFile.close();
delete[] X;
delete[] W;
delete[] V;
delete[] weight_denominator;
delete[] States;
return 0;
} | #include <iostream>
#include <math.h>
#include <ctime>
#include <cmath>
#include <stdlib.h>
#include <fstream>
#include <vector>
#include <sstream>
#include <iomanip>
#include <algorithm>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
#include <hiprand/hiprand_kernel.h>
#define PI 3.14159265358979323846
//this function initialises the kernel which constructs the mesh according to the independent path construction.
void mesh_generation(int b, int num_assets, double m, double X0[], double sigma[], double delta[], double asset_amount[], double* X, double strike, double r, double delta_t, hiprandState_t* States, hiprandState_t* statesi, int threads);
//this function initialises all the mesh weights kernels
void meshweights(double* W, double m, int b, double sigma[], double delta[], double r, double delta_t, double* X, int num_assets, double* weight_denominator);
//this function converts one dim vectors to one dim arrays
void one_dim_array(std::vector< double > &vals, double array[], int N);
//this function provides an indexing interface for 3-d matrices stored in 1 dim arrays
double* three_dim_index(double* matrix, int i, int j, int k, double m, int b, int num_assets);
//this function provides an indexing interface for 2-d matrices stored in 1 dim arrays
double* two_dim_index(double* vector, int i, int j, double m, int b);
//this function initialises the mesh estimator kernel
double MeshEstimator(double strike, double r, double delta_t, int b, double m, double* X, double* W, double* V, double asset_amount[], int num_assets);
//this function initialises the pathestimator kernel.
double PathEstimator(double strike, double r, double delta_t, int b, double m, double sigma[], double delta[], double X0[], double* X, double* weight_denominator, double* V, double asset_amount[], int num_assets, int Path_estimator_iterations, int iterator, int Final_iteration, hiprandState_t* States, hiprandState_t* states, int threads);
//this function prints results for 1-dim options to 'OneDimHighPayoff.txt'. These results can be plotted using the program 'OneDimPayoff.py'
void print_high_payoff(int b, double m, double* X, double* V, double asset_amount[], double* W );
//this function prints results for 1-dim options to 'stocksimulation.txt'. These results can be plotted using the program 'simulation.py'
void SimulationPaths(int b, double m, double* X, double* V, double asset_amount[], double* W, double x );
//this kernel initialises the random seeds on each thread
__global__ void initialise(unsigned int seed, hiprandState_t* states) {
int idx=blockDim.x*blockIdx.x + threadIdx.x;
// we have to initialize the state
hiprand_init(seed, idx, 0, &states[idx]);
}
int main(){
srand((unsigned)time(NULL));
//begin timer
clock_t begin=clock();
//read in parameters from setting.txt
std::ifstream setting( "settings.txt" );
std::string line;
std::vector<std::string> settings;
int linenumber=0;
while(std::getline( setting, line))
{
if(linenumber%2==1)
settings.push_back(line);
linenumber++;
}
setting.close();
int integer;
std::vector < double > X0V;
std::vector < double > deltaV;
std::vector <double> sigmaV;
std::vector <double> asset_amountV;
std::istringstream ss(settings[0]);
std::string token;
while(std::getline(ss, token, ','))
{
X0V.push_back(atof(token.c_str()));
}
double T = atof(settings[1].c_str());
double m = atof(settings[2].c_str());
double delta_t=T/m;
double v_0, V_0, vtotal_sum=0, Vtotal_sum=0;
double r= atof(settings[3].c_str());
std::istringstream ss2(settings[4]);
while(std::getline(ss2, token, ','))
{
deltaV.push_back(atof(token.c_str()));
}
std::istringstream ss3(settings[5]);
while(std::getline(ss3, token, ','))
{
sigmaV.push_back(atof(token.c_str()));
}
int Path_estimator_iterations=atof(settings[6].c_str());
double strike=atof(settings[7].c_str());
int b=atoi(settings[8].c_str());
int N=atoi(settings[9].c_str());
double quantile=atof(settings[10].c_str());
int num_assets=atof(settings[11].c_str());
std::istringstream ss4(settings[12]);
while(std::getline(ss4, token, ','))
{
asset_amountV.push_back(atof(token.c_str()));
}
if(X0V.size() != num_assets || sigmaV.size() != num_assets || deltaV.size() !=num_assets || asset_amountV.size() !=num_assets){
std::cout<<"Either the starting price, volatility, number of assets or dividend yield was not specified for all assets"<<std::endl;
exit (EXIT_FAILURE);
}
std::cout<<"The parameters of this simulation are:"<<std::endl;
//Print these values to screen
for(integer=0; integer<X0V.size(); integer++){
std::cout<<"Starting Price of Asset "<<integer<<" = "<<X0V[integer]<<std::endl;
}
std::cout<<"Time to Expiry="<<T<<"\n"<<"Number of Time Steps="<<m<<"\n"<<"Interest Rate="<<r<<std::endl;
for(integer=0; integer<sigmaV.size(); integer++){
std::cout<<"Volatility of Asset "<<integer<<" = "<<sigmaV[integer]<<std::endl;
}
for(integer=0; integer<deltaV.size(); integer++){
std::cout<<"Dividend Yield of Asset "<<integer<<" ="<<deltaV[integer]<<std::endl;
}
std::cout<<"Number of Iterations Over the Path Estimator="<<Path_estimator_iterations<<"\n"<<"Strike Price="<<strike<<"\n"<<"Nodes per Time Step="<<b<<"\n"<<"Number Mesh Replications="<<N<<"\n"<<"Number of Assets="<<num_assets<<std::endl;
for(integer=0; integer<asset_amountV.size(); integer++){
std::cout<<"Amount of Asset "<<integer<<" = "<<asset_amountV[integer]<<std::endl;
}
// CONVERT TO ARRAYS
double X0 [num_assets];
double delta [num_assets];
double sigma [num_assets];
double asset_amount [num_assets];
one_dim_array(X0V, X0, num_assets);
one_dim_array(deltaV, delta, num_assets);
one_dim_array(sigmaV, sigma, num_assets);
one_dim_array(asset_amountV, asset_amount, num_assets);
//V values from each iteration over meshes
std::vector< double > Vvector;
//v values from each iteration over meshes
std::vector< double > vvector;
//asset vector
std::vector< double > assets;
//1 d vector in Weightsgen for-loop
std:: vector<double> dim1temp;
std::vector<double> sortvector;
int m_int= (int)m;
//mesh matrix
double* X;
int X_dim = (m_int) * b * (num_assets);
X= new double[X_dim];
//weight matrix
double* W;
int W_dim = (m_int) * b * b;
W= new double[W_dim];
//high values matrix
double* V;
int V_dim = (m_int) * b;
V = new double[V_dim];
//weight denominator values
double* weight_denominator;
int denom_dim = (m_int-1) * b;
weight_denominator =new double[denom_dim];
//convert to log prices
for(int init=0; init<num_assets; init++){
X0[init]=log(X0[init]);
}
int threads=Path_estimator_iterations;
if(b>Path_estimator_iterations){
threads=b;
}
hiprandState_t* States;
States= new hiprandState_t[threads];
//for-loop over different meshes
for(int iterator=0; iterator<N; iterator++){
hiprandState_t* states;
hipMalloc((void**) &states, threads * sizeof(hiprandState_t));
if(iterator==0){
dim3 gridDim((int)ceil(threads/512.0));
dim3 blockDim(512.0);
initialise<<<gridDim, blockDim>>>(time(0), states);
hipDeviceSynchronize();
hipMemcpy(States, states, sizeof(hiprandState_t)*threads, hipMemcpyDeviceToHost);
}
else{hipMemcpy(states, States, threads*sizeof(hiprandState_t), hipMemcpyHostToDevice);}
mesh_generation(b, num_assets, m, X0, sigma, delta, asset_amount, X, strike, r, delta_t, States, states, threads);
meshweights(W, m, b, sigma, delta, r, delta_t, X, num_assets, weight_denominator);
double check=0;
//check all the weights from X0 are 1
for(int e=0; e<b; e++){
if(*three_dim_index(W, 0, e, 0, m, b, b)!=1){
std::cout<<"there is an error with the weights. check that W[0][k][0]'s =1"<<std::endl;
}
}
//check that the weights going into a node sum to 1
for(int q=1; q<m; q++){
for(int a=0; a<b; a++){
check=0;
for(int E=0; E<b; E++){
check+=*three_dim_index(W, (q), a, E, m, b, num_assets);
}
}
}
V_0=MeshEstimator(strike, r, delta_t, b, m, X, W, V, asset_amount, num_assets);
Vvector.push_back(V_0);//vector containing high bias option prices
Vtotal_sum+=V_0;
std::cout<<"High Bias price (V_0) for mesh iteration "<<iterator<<" is "<<V_0<<std::endl;
v_0=PathEstimator(strike, r, delta_t, b, m, sigma, delta, X0, X, weight_denominator, V, asset_amount, num_assets, Path_estimator_iterations, iterator, N, States, states, threads);
hipDeviceReset();
vvector.push_back(v_0);
vtotal_sum+=v_0;
std::cout<<"Low Bias price (v_0) for mesh iteration "<<iterator<<" is "<<v_0<<std::endl;
}//this is the end of the loop over the whole process.
if(num_assets==1){
print_high_payoff(b, m, X, V, asset_amount,W);
SimulationPaths(b, m, X, V, asset_amount, W, X0[0] );
}
//Calculate V(N) and v(N)
V_0=(1/double(N))*Vtotal_sum;
v_0=(1/double(N))*vtotal_sum;
//calculate errors
double std_div_V=0, std_div_v=0, squaresumV=0, squaresumv=0, Verror=0, verror=0;
for(int h=0; h<N; h++){
squaresumV+=(Vvector[h]-V_0)*(Vvector[h]-V_0);
squaresumv+=(vvector[h]-v_0)*(vvector[h]-v_0);
}
std_div_V=sqrt((1/double(N))*squaresumV); //standard deviation of V
std_div_v=sqrt((1/double(N))*squaresumv); //standard deviation of v
double standardErrorV=std_div_V*(1/sqrt(double(N)));
double standardErrorv=std_div_v*(1/sqrt(double(N)));
Verror=quantile*standardErrorV;
verror=quantile*standardErrorv;
std::cout<<"V(N)_0="<<V_0<<std::endl;
std::cout<<"v(N)_0="<<v_0<<std::endl;
double pointEst=(V_0+v_0)/2;
double EstimatedError=((Verror+V_0)-(v_0-verror))/(2*pointEst);
clock_t end =clock();
double elapsedtime=double(end-begin) / CLOCKS_PER_SEC;
std::ofstream outFile("results.txt", std::ios_base::app | std::ios_base::out);
outFile << N <<"\t"<< b <<"\t"<< Path_estimator_iterations<<"\t"<<exp(X0[0])<<"\t" << v_0 <<"\t"<< standardErrorv <<"\t"<< V_0 <<"\t"<< standardErrorV <<"\t"<< v_0-verror<<"\t"<<Verror+V_0 <<"\t"<<pointEst<<"\t"<<EstimatedError<<"\t" <<elapsedtime<< std::endl;
outFile.close();
std::ofstream LoutFile("latexresults.txt", std::ios_base::app | std::ios_base::out);
LoutFile <<std::fixed<<std::setprecision(3) << N <<"&"<< b <<"&"<< Path_estimator_iterations<<"&"<<exp(X0[0])<<"&" << v_0 <<"&"<< standardErrorv <<"&"<< V_0 <<"&"<< standardErrorV <<"&"<< v_0-verror<<"&"<<Verror+V_0 <<"&"<<pointEst<<"&"<<EstimatedError<<"&" <<elapsedtime<< std::endl;
outFile.close();
delete[] X;
delete[] W;
delete[] V;
delete[] weight_denominator;
delete[] States;
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define BLOCK_SIZE 16
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void transGPU(const float *inMatrix, float *outMatrix, const size_t row, const size_t column)
{
size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if ((xIndex < column) && (yIndex < row))
{
size_t inIndex = yIndex * column + xIndex;
size_t outIndex = xIndex * row + yIndex;
outMatrix[outIndex] = inMatrix[inIndex];
}
} | code for sm_80
Function : _Z8transGPUPKfPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0040*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f26070 */
/*0070*/ IMAD R6, R6, c[0x0][0x4], R7 ; /* 0x0000010006067a24 */
/* 0x002fc600078e0207 */
/*0080*/ ISETP.GE.U32.AND.EX P1, PT, RZ, c[0x0][0x17c], PT, P1 ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f26110 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ ISETP.GE.U32.OR.EX P0, PT, RZ, c[0x0][0x174], P1, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0000f06500 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE.U32 R2, R6, c[0x0][0x178], R4 ; /* 0x00005e0006027a25 */
/* 0x000fc800078e0004 */
/*00f0*/ IMAD R3, R6, c[0x0][0x17c], R3 ; /* 0x00005f0006037a24 */
/* 0x000fe200078e0203 */
/*0100*/ LEA R8, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002087a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R9, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002097a11 */
/* 0x000fcc00000f1403 */
/*0120*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.WIDE.U32 R2, R4, c[0x0][0x170], R6 ; /* 0x00005c0004027a25 */
/* 0x000fc800078e0006 */
/*0150*/ IMAD R5, R4, c[0x0][0x174], R3 ; /* 0x00005d0004057a24 */
/* 0x000fe200078e0203 */
/*0160*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*0170*/ LEA.HI.X R5, R2, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f1405 */
/*0180*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x004fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define BLOCK_SIZE 16
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void transGPU(const float *inMatrix, float *outMatrix, const size_t row, const size_t column)
{
size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if ((xIndex < column) && (yIndex < row))
{
size_t inIndex = yIndex * column + xIndex;
size_t outIndex = xIndex * row + yIndex;
outMatrix[outIndex] = inMatrix[inIndex];
}
} | .file "tmpxft_0007fa3c_00000000-6_transGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ff
.type _Z1ff, @function
_Z1ff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z1ff, .-_Z1ff
.globl _Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm
.type _Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm, @function
_Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8transGPUPKfPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm, .-_Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm
.globl _Z8transGPUPKfPfmm
.type _Z8transGPUPKfPfmm, @function
_Z8transGPUPKfPfmm:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8transGPUPKfPfmm, .-_Z8transGPUPKfPfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8transGPUPKfPfmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8transGPUPKfPfmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define BLOCK_SIZE 16
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void transGPU(const float *inMatrix, float *outMatrix, const size_t row, const size_t column)
{
size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if ((xIndex < column) && (yIndex < row))
{
size_t inIndex = yIndex * column + xIndex;
size_t outIndex = xIndex * row + yIndex;
outMatrix[outIndex] = inMatrix[inIndex];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 16
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void transGPU(const float *inMatrix, float *outMatrix, const size_t row, const size_t column)
{
size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if ((xIndex < column) && (yIndex < row))
{
size_t inIndex = yIndex * column + xIndex;
size_t outIndex = xIndex * row + yIndex;
outMatrix[outIndex] = inMatrix[inIndex];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 16
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void transGPU(const float *inMatrix, float *outMatrix, const size_t row, const size_t column)
{
size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if ((xIndex < column) && (yIndex < row))
{
size_t inIndex = yIndex * column + xIndex;
size_t outIndex = xIndex * row + yIndex;
outMatrix[outIndex] = inMatrix[inIndex];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8transGPUPKfPfmm
.globl _Z8transGPUPKfPfmm
.p2align 8
.type _Z8transGPUPKfPfmm,@function
_Z8transGPUPKfPfmm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mov_b32_e32 v3, 0
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v1, v3
v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s2, s[4:5], v[0:1]
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[4:5], null, v0, s6, 0
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v0, s7, v[5:6]
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v5, v6
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v7, vcc_lo
global_load_b32 v7, v[3:4], off
v_mad_u64_u32 v[3:4], null, v2, s4, 0
v_mad_u64_u32 v[5:6], null, v2, s5, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v4, v5
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8transGPUPKfPfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8transGPUPKfPfmm, .Lfunc_end0-_Z8transGPUPKfPfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8transGPUPKfPfmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8transGPUPKfPfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 16
__device__ float f(float x)
{
return 4.f / (1.f + x * x);
}
__global__ void transGPU(const float *inMatrix, float *outMatrix, const size_t row, const size_t column)
{
size_t xIndex = blockIdx.x * blockDim.x + threadIdx.x;
size_t yIndex = blockIdx.y * blockDim.y + threadIdx.y;
if ((xIndex < column) && (yIndex < row))
{
size_t inIndex = yIndex * column + xIndex;
size_t outIndex = xIndex * row + yIndex;
outMatrix[outIndex] = inMatrix[inIndex];
}
} | .text
.file "transGPU.hip"
.globl _Z23__device_stub__transGPUPKfPfmm # -- Begin function _Z23__device_stub__transGPUPKfPfmm
.p2align 4, 0x90
.type _Z23__device_stub__transGPUPKfPfmm,@function
_Z23__device_stub__transGPUPKfPfmm: # @_Z23__device_stub__transGPUPKfPfmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8transGPUPKfPfmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__transGPUPKfPfmm, .Lfunc_end0-_Z23__device_stub__transGPUPKfPfmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8transGPUPKfPfmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8transGPUPKfPfmm,@object # @_Z8transGPUPKfPfmm
.section .rodata,"a",@progbits
.globl _Z8transGPUPKfPfmm
.p2align 3, 0x0
_Z8transGPUPKfPfmm:
.quad _Z23__device_stub__transGPUPKfPfmm
.size _Z8transGPUPKfPfmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8transGPUPKfPfmm"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__transGPUPKfPfmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8transGPUPKfPfmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8transGPUPKfPfmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e680000002600 */
/*0040*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R4, R4, c[0x0][0x0], R5 ; /* 0x0000000004047a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.U32.AND P1, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fe20003f26070 */
/*0070*/ IMAD R6, R6, c[0x0][0x4], R7 ; /* 0x0000010006067a24 */
/* 0x002fc600078e0207 */
/*0080*/ ISETP.GE.U32.AND.EX P1, PT, RZ, c[0x0][0x17c], PT, P1 ; /* 0x00005f00ff007a0c */
/* 0x000fe40003f26110 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ ISETP.GE.U32.OR.EX P0, PT, RZ, c[0x0][0x174], P1, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0000f06500 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00e0*/ IMAD.WIDE.U32 R2, R6, c[0x0][0x178], R4 ; /* 0x00005e0006027a25 */
/* 0x000fc800078e0004 */
/*00f0*/ IMAD R3, R6, c[0x0][0x17c], R3 ; /* 0x00005f0006037a24 */
/* 0x000fe200078e0203 */
/*0100*/ LEA R8, P0, R2, c[0x0][0x160], 0x2 ; /* 0x0000580002087a11 */
/* 0x000fc800078010ff */
/*0110*/ LEA.HI.X R9, R2, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590002097a11 */
/* 0x000fcc00000f1403 */
/*0120*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0130*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.WIDE.U32 R2, R4, c[0x0][0x170], R6 ; /* 0x00005c0004027a25 */
/* 0x000fc800078e0006 */
/*0150*/ IMAD R5, R4, c[0x0][0x174], R3 ; /* 0x00005d0004057a24 */
/* 0x000fe200078e0203 */
/*0160*/ LEA R4, P0, R2, c[0x0][0x168], 0x2 ; /* 0x00005a0002047a11 */
/* 0x000fc800078010ff */
/*0170*/ LEA.HI.X R5, R2, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0002057a11 */
/* 0x000fca00000f1405 */
/*0180*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x004fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8transGPUPKfPfmm
.globl _Z8transGPUPKfPfmm
.p2align 8
.type _Z8transGPUPKfPfmm,@function
_Z8transGPUPKfPfmm:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b128 s[4:7], s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v4, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mov_b32_e32 v3, 0
v_mad_u64_u32 v[0:1], null, s15, s2, v[4:5]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mov_b32_e32 v1, v3
v_cmp_gt_u64_e32 vcc_lo, s[6:7], v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s2, s[4:5], v[0:1]
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mad_u64_u32 v[4:5], null, v0, s6, 0
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[6:7], null, v0, s7, v[5:6]
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_mov_b32_e32 v5, v6
v_lshlrev_b64 v[6:7], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v5, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v7, vcc_lo
global_load_b32 v7, v[3:4], off
v_mad_u64_u32 v[3:4], null, v2, s4, 0
v_mad_u64_u32 v[5:6], null, v2, s5, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mov_b32_e32 v4, v5
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, v3, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v7, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8transGPUPKfPfmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8transGPUPKfPfmm, .Lfunc_end0-_Z8transGPUPKfPfmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8transGPUPKfPfmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8transGPUPKfPfmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007fa3c_00000000-6_transGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ff
.type _Z1ff, @function
_Z1ff:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z1ff, .-_Z1ff
.globl _Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm
.type _Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm, @function
_Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8transGPUPKfPfmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm, .-_Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm
.globl _Z8transGPUPKfPfmm
.type _Z8transGPUPKfPfmm, @function
_Z8transGPUPKfPfmm:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8transGPUPKfPfmmPKfPfmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z8transGPUPKfPfmm, .-_Z8transGPUPKfPfmm
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8transGPUPKfPfmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8transGPUPKfPfmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "transGPU.hip"
.globl _Z23__device_stub__transGPUPKfPfmm # -- Begin function _Z23__device_stub__transGPUPKfPfmm
.p2align 4, 0x90
.type _Z23__device_stub__transGPUPKfPfmm,@function
_Z23__device_stub__transGPUPKfPfmm: # @_Z23__device_stub__transGPUPKfPfmm
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8transGPUPKfPfmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__transGPUPKfPfmm, .Lfunc_end0-_Z23__device_stub__transGPUPKfPfmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8transGPUPKfPfmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8transGPUPKfPfmm,@object # @_Z8transGPUPKfPfmm
.section .rodata,"a",@progbits
.globl _Z8transGPUPKfPfmm
.p2align 3, 0x0
_Z8transGPUPKfPfmm:
.quad _Z23__device_stub__transGPUPKfPfmm
.size _Z8transGPUPKfPfmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8transGPUPKfPfmm"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__transGPUPKfPfmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8transGPUPKfPfmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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