system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define BLOCK_SIZE 16
#define BLOCKSIZE_X 16
#define BLOCKSIZE_Y 16
// STD includes
// CUDA runtime
// Utilities and system includes
static // Print device properties
__global__ void averageKernel( unsigned char* inputChannel, unsigned char* outputChannel, int imageW, int imageH)
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numElements = ((2 * KERNEL_RADIUS) + 1) * ((2 * KERNEL_RADIUS) + 1);
unsigned int sum = 0;
for (int kY = -KERNEL_RADIUS; kY <= KERNEL_RADIUS; kY++) {
const int curY = y + kY;
if (curY < 0 || curY > imageH) {
continue;
}
for (int kX = -KERNEL_RADIUS; kX <= KERNEL_RADIUS; kX++) {
const int curX = x + kX;
if (curX < 0 || curX > imageW) {
continue;
}
const int curPosition = (curY * imageW + curX);
if (curPosition >= 0 && curPosition < (imageW * imageH)) {
sum += inputChannel[curPosition];
}
}
}
outputChannel[y * imageW + x] = (unsigned char)(sum / numElements);
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 16
#define BLOCKSIZE_X 16
#define BLOCKSIZE_Y 16
// STD includes
// CUDA runtime
// Utilities and system includes
static // Print device properties
__global__ void averageKernel( unsigned char* inputChannel, unsigned char* outputChannel, int imageW, int imageH)
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numElements = ((2 * KERNEL_RADIUS) + 1) * ((2 * KERNEL_RADIUS) + 1);
unsigned int sum = 0;
for (int kY = -KERNEL_RADIUS; kY <= KERNEL_RADIUS; kY++) {
const int curY = y + kY;
if (curY < 0 || curY > imageH) {
continue;
}
for (int kX = -KERNEL_RADIUS; kX <= KERNEL_RADIUS; kX++) {
const int curX = x + kX;
if (curX < 0 || curX > imageW) {
continue;
}
const int curPosition = (curY * imageW + curX);
if (curPosition >= 0 && curPosition < (imageW * imageH)) {
sum += inputChannel[curPosition];
}
}
}
outputChannel[y * imageW + x] = (unsigned char)(sum / numElements);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 16
#define BLOCKSIZE_X 16
#define BLOCKSIZE_Y 16
// STD includes
// CUDA runtime
// Utilities and system includes
static // Print device properties
__global__ void averageKernel( unsigned char* inputChannel, unsigned char* outputChannel, int imageW, int imageH)
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numElements = ((2 * KERNEL_RADIUS) + 1) * ((2 * KERNEL_RADIUS) + 1);
unsigned int sum = 0;
for (int kY = -KERNEL_RADIUS; kY <= KERNEL_RADIUS; kY++) {
const int curY = y + kY;
if (curY < 0 || curY > imageH) {
continue;
}
for (int kX = -KERNEL_RADIUS; kX <= KERNEL_RADIUS; kX++) {
const int curX = x + kX;
if (curX < 0 || curX > imageW) {
continue;
}
const int curPosition = (curY * imageW + curX);
if (curPosition >= 0 && curPosition < (imageW * imageH)) {
sum += inputChannel[curPosition];
}
}
}
outputChannel[y * imageW + x] = (unsigned char)(sum / numElements);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL13averageKernelPhS_ii,"axG",@progbits,_ZL13averageKernelPhS_ii,comdat
.globl _ZL13averageKernelPhS_ii
.p2align 8
.type _ZL13averageKernelPhS_ii,@function
_ZL13averageKernelPhS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
s_load_b64 s[6:7], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s8, -8
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mul_i32 s14, s14, s2
s_mul_i32 s3, s5, s4
v_add3_u32 v4, v0, s14, -8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, -8, v1
v_mul_lo_u32 v3, s4, v2
v_mov_b32_e32 v2, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v3, s4, v3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 9
s_cbranch_scc1 .LBB0_9
.LBB0_2:
v_add_nc_u32_e32 v5, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_ge_i32_e64 s2, s5, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s2
s_cbranch_execz .LBB0_1
v_mov_b32_e32 v5, v4
s_mov_b32 s10, 17
s_branch .LBB0_6
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s10, s10, -1
s_cmp_lg_u32 s10, 0
s_cbranch_scc0 .LBB0_1
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_ge_i32_e64 s2, s4, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s11, s2
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v6
v_cmp_gt_i32_e64 s2, s3, v6
s_and_b32 s12, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_4
global_load_u8 v6, v6, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v6
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_mul_lo_u32 v1, v1, s4
v_mul_hi_u32 v2, v2, 0xe2c4a689
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v0, s14, v0, v1
v_lshrrev_b32_e32 v2, 8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL13averageKernelPhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL13averageKernelPhS_ii,"axG",@progbits,_ZL13averageKernelPhS_ii,comdat
.Lfunc_end0:
.size _ZL13averageKernelPhS_ii, .Lfunc_end0-_ZL13averageKernelPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL13averageKernelPhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL13averageKernelPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define BLOCK_SIZE 16
#define BLOCKSIZE_X 16
#define BLOCKSIZE_Y 16
// STD includes
// CUDA runtime
// Utilities and system includes
static // Print device properties
__global__ void averageKernel( unsigned char* inputChannel, unsigned char* outputChannel, int imageW, int imageH)
{
int y = blockIdx.y * blockDim.y + threadIdx.y;
int x = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numElements = ((2 * KERNEL_RADIUS) + 1) * ((2 * KERNEL_RADIUS) + 1);
unsigned int sum = 0;
for (int kY = -KERNEL_RADIUS; kY <= KERNEL_RADIUS; kY++) {
const int curY = y + kY;
if (curY < 0 || curY > imageH) {
continue;
}
for (int kX = -KERNEL_RADIUS; kX <= KERNEL_RADIUS; kX++) {
const int curX = x + kX;
if (curX < 0 || curX > imageW) {
continue;
}
const int curPosition = (curY * imageW + curX);
if (curPosition >= 0 && curPosition < (imageW * imageH)) {
sum += inputChannel[curPosition];
}
}
}
outputChannel[y * imageW + x] = (unsigned char)(sum / numElements);
} | .text
.file "averageKernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13averageKernelPhS_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R18, RZ, RZ, -0x8 ; /* 0xfffffff8ff127424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff147224 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe4000f8e023f */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0080*/ S2R R19, SR_CTAID.Y ; /* 0x0000000000137919 */
/* 0x000e680000002600 */
/*0090*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*00a0*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*00b0*/ ISETP.GT.AND P6, PT, R0.reuse, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x040fe40003fc4270 */
/*00c0*/ IADD3 R3, R0.reuse, -0x8, RZ ; /* 0xfffffff800037810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ IMAD R19, R19, c[0x0][0x4], R2 ; /* 0x0000010013137a24 */
/* 0x002fe200078e0202 */
/*00e0*/ IADD3 R4, R0.reuse, -0x7, RZ ; /* 0xfffffff900047810 */
/* 0x040fe40007ffe0ff */
/*00f0*/ IADD3 R5, R0.reuse, -0x6, RZ ; /* 0xfffffffa00057810 */
/* 0x040fe40007ffe0ff */
/*0100*/ ISETP.LT.OR P6, PT, R0.reuse, RZ, P6 ; /* 0x000000ff0000720c */
/* 0x040fe400037c1670 */
/*0110*/ ISETP.GE.AND P5, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc40003fa6270 */
/*0120*/ IADD3 R6, R0.reuse, -0x5, RZ ; /* 0xfffffffb00067810 */
/* 0x040fe40007ffe0ff */
/*0130*/ ISETP.GT.AND P4, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe40003f84270 */
/*0140*/ IADD3 R7, R0, -0x4, RZ ; /* 0xfffffffc00077810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.GT.AND P3, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe40003f64270 */
/*0160*/ ISETP.GT.AND P2, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe40003f44270 */
/*0170*/ P2R R32, PR, RZ, 0x40 ; /* 0x00000040ff207803 */
/* 0x000fc40000000000 */
/*0180*/ ISETP.GT.AND P1, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fe40003f24270 */
/*0190*/ ISETP.LT.OR P6, PT, R0.reuse, -0x1, P5 ; /* 0xffffffff0000780c */
/* 0x040fe40002fc1670 */
/*01a0*/ ISETP.GT.AND P0, PT, R7, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x000fe40003f04270 */
/*01b0*/ ISETP.LT.OR P5, PT, R0.reuse, 0x8, P4 ; /* 0x000000080000780c */
/* 0x040fe400027a1670 */
/*01c0*/ IADD3 R8, R0.reuse, -0x3, RZ ; /* 0xfffffffd00087810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ ISETP.LT.OR P4, PT, R0, 0x7, P3 ; /* 0x000000070000780c */
/* 0x000fc40001f81670 */
/*01e0*/ ISETP.LT.OR P3, PT, R0.reuse, 0x6, P2 ; /* 0x000000060000780c */
/* 0x040fe40001761670 */
/*01f0*/ ISETP.LT.OR P2, PT, R0.reuse, 0x5, P1 ; /* 0x000000050000780c */
/* 0x040fe40000f41670 */
/*0200*/ ISETP.LT.OR P1, PT, R0, 0x4, P0 ; /* 0x000000040000780c */
/* 0x000fe40000721670 */
/*0210*/ ISETP.GT.AND P0, PT, R8, c[0x0][0x170], PT ; /* 0x00005c0008007a0c */
/* 0x000fe40003f04270 */
/*0220*/ IADD3 R9, R0, -0x2, RZ ; /* 0xfffffffe00097810 */
/* 0x000fe40007ffe0ff */
/*0230*/ P2R R27, PR, RZ, 0x4 ; /* 0x00000004ff1b7803 */
/* 0x000fc40000000000 */
/*0240*/ ISETP.LT.OR P2, PT, R0.reuse, 0x3, P0 ; /* 0x000000030000780c */
/* 0x040fe40000741670 */
/*0250*/ ISETP.GT.AND P0, PT, R9, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x000fe40003f04270 */
/*0260*/ IADD3 R10, R0.reuse, -0x1, RZ ; /* 0xffffffff000a7810 */
/* 0x040fe40007ffe0ff */
/*0270*/ P2R R28, PR, RZ, 0x2 ; /* 0x00000002ff1c7803 */
/* 0x000fe40000000000 */
/*0280*/ ISETP.LT.OR P1, PT, R0, 0x2, P0 ; /* 0x000000020000780c */
/* 0x000fe40000721670 */
/*0290*/ ISETP.GT.AND P0, PT, R10, c[0x0][0x170], PT ; /* 0x00005c000a007a0c */
/* 0x000fc40003f04270 */
/*02a0*/ IADD3 R11, R0.reuse, 0x2, RZ ; /* 0x00000002000b7810 */
/* 0x040fe40007ffe0ff */
/*02b0*/ P2R R29, PR, RZ, 0x4 ; /* 0x00000004ff1d7803 */
/* 0x000fe40000000000 */
/*02c0*/ ISETP.LT.OR P2, PT, R0.reuse, 0x1, P0 ; /* 0x000000010000780c */
/* 0x040fe40000741670 */
/*02d0*/ ISETP.GT.AND P0, PT, R11, c[0x0][0x170], PT ; /* 0x00005c000b007a0c */
/* 0x000fe40003f04270 */
/*02e0*/ P2R R30, PR, RZ, 0x2 ; /* 0x00000002ff1e7803 */
/* 0x000fe40000000000 */
/*02f0*/ ISETP.LT.OR P1, PT, R0, -0x2, P0 ; /* 0xfffffffe0000780c */
/* 0x000fc40000721670 */
/*0300*/ IADD3 R12, R0.reuse, 0x3, RZ ; /* 0x00000003000c7810 */
/* 0x040fe40007ffe0ff */
/*0310*/ IADD3 R13, R0.reuse, 0x4, RZ ; /* 0x00000004000d7810 */
/* 0x040fe40007ffe0ff */
/*0320*/ IADD3 R14, R0.reuse, 0x5, RZ ; /* 0x00000005000e7810 */
/* 0x040fe40007ffe0ff */
/*0330*/ IADD3 R15, R0.reuse, 0x6, RZ ; /* 0x00000006000f7810 */
/* 0x040fe40007ffe0ff */
/*0340*/ IADD3 R16, R0.reuse, 0x7, RZ ; /* 0x0000000700107810 */
/* 0x040fe40007ffe0ff */
/*0350*/ IADD3 R17, R0, 0x8, RZ ; /* 0x0000000800117810 */
/* 0x000fc40007ffe0ff */
/*0360*/ P2R R25, PR, RZ, 0x20 ; /* 0x00000020ff197803 */
/* 0x000fe40000000000 */
/*0370*/ P2R R26, PR, RZ, 0x10 ; /* 0x00000010ff1a7803 */
/* 0x000fe40000000000 */
/*0380*/ P2R R24, PR, RZ, 0x8 ; /* 0x00000008ff187803 */
/* 0x000fe40000000000 */
/*0390*/ P2R R31, PR, RZ, 0x4 ; /* 0x00000004ff1f7803 */
/* 0x000fe40000000000 */
/*03a0*/ P2R R34, PR, RZ, 0x2 ; /* 0x00000002ff227803 */
/* 0x000fe40000000000 */
/*03b0*/ ISETP.GT.AND P0, PT, R12, c[0x0][0x170], PT ; /* 0x00005c000c007a0c */
/* 0x000fc40003f04270 */
/*03c0*/ ISETP.GT.AND P1, PT, R13, c[0x0][0x170], PT ; /* 0x00005c000d007a0c */
/* 0x000fe40003f24270 */
/*03d0*/ ISETP.GT.AND P2, PT, R14, c[0x0][0x170], PT ; /* 0x00005c000e007a0c */
/* 0x000fe40003f44270 */
/*03e0*/ ISETP.GT.AND P3, PT, R15, c[0x0][0x170], PT ; /* 0x00005c000f007a0c */
/* 0x000fe40003f64270 */
/*03f0*/ ISETP.GT.AND P4, PT, R16, c[0x0][0x170], PT ; /* 0x00005c0010007a0c */
/* 0x000fe40003f84270 */
/*0400*/ ISETP.GT.AND P5, PT, R17, c[0x0][0x170], PT ; /* 0x00005c0011007a0c */
/* 0x000fe40003fa4270 */
/*0410*/ P2R R33, PR, RZ, 0x40 ; /* 0x00000040ff217803 */
/* 0x000fc40000000000 */
/*0420*/ ISETP.LT.OR P0, PT, R0.reuse, -0x3, P0 ; /* 0xfffffffd0000780c */
/* 0x040fe40000701670 */
/*0430*/ ISETP.LT.OR P1, PT, R0.reuse, -0x4, P1 ; /* 0xfffffffc0000780c */
/* 0x040fe40000f21670 */
/*0440*/ ISETP.LT.OR P2, PT, R0.reuse, -0x5, P2 ; /* 0xfffffffb0000780c */
/* 0x040fe40001741670 */
/*0450*/ ISETP.LT.OR P3, PT, R0.reuse, -0x6, P3 ; /* 0xfffffffa0000780c */
/* 0x040fe40001f61670 */
/*0460*/ ISETP.LT.OR P4, PT, R0.reuse, -0x7, P4 ; /* 0xfffffff90000780c */
/* 0x040fe40002781670 */
/*0470*/ ISETP.LT.OR P5, PT, R0, -0x8, P5 ; /* 0xfffffff80000780c */
/* 0x000fc40002fa1670 */
/*0480*/ IADD3 R21, R0, 0x1, RZ ; /* 0x0000000100157810 */
/* 0x000fe40007ffe0ff */
/*0490*/ IMAD.IADD R22, R19, 0x1, R18 ; /* 0x0000000113167824 */
/* 0x000fe200078e0212 */
/*04a0*/ BSSY B0, 0xca0 ; /* 0x000007f000007945 */
/* 0x000fe20003800000 */
/*04b0*/ IADD3 R18, R18, 0x1, RZ ; /* 0x0000000112127810 */
/* 0x000fc60007ffe0ff */
/*04c0*/ ISETP.GT.AND P6, PT, R22, c[0x0][0x174], PT ; /* 0x00005d0016007a0c */
/* 0x000fc80003fc4270 */
/*04d0*/ ISETP.LT.OR P6, PT, R22, RZ, P6 ; /* 0x000000ff1600720c */
/* 0x000fda00037c1670 */
/*04e0*/ @P6 BRA 0xc90 ; /* 0x000007a000006947 */
/* 0x000fea0003800000 */
/*04f0*/ IMAD R38, R22, c[0x0][0x170], R0 ; /* 0x00005c0016267a24 */
/* 0x000fe200078e0200 */
/*0500*/ IADD3 R23, R0, -0x8, RZ ; /* 0xfffffff800177810 */
/* 0x000fe40007ffe0ff */
/*0510*/ P2R R36, PR, RZ, 0x10 ; /* 0x00000010ff247803 */
/* 0x000fe40000000000 */
/*0520*/ IADD3 R2, P6, R38, c[0x0][0x160], RZ ; /* 0x0000580026027a10 */
/* 0x000fe20007fde0ff */
/*0530*/ IMAD R23, R22, c[0x0][0x170], R23 ; /* 0x00005c0016177a24 */
/* 0x000fe200078e0217 */
/*0540*/ ISETP.NE.AND P4, PT, R25, RZ, PT ; /* 0x000000ff1900720c */
/* 0x000fe40003f85270 */
/*0550*/ LEA.HI.X.SX32 R3, R38, c[0x0][0x164], 0x1, P6 ; /* 0x0000590026037a11 */
/* 0x000fe400030f0eff */
/*0560*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc4000bfc6270 */
/*0570*/ P2R R35, PR, RZ, 0x20 ; /* 0x00000020ff237803 */
/* 0x000fe40000000000 */
/*0580*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fe400037c1670 */
/*0590*/ ISETP.NE.AND P5, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003fa5270 */
/*05a0*/ PLOP3.LUT P6, PT, P4, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe400027cd570 */
/*05b0*/ P2R R37, PR, RZ, 0x8 ; /* 0x00000008ff257803 */
/* 0x000fe40000000000 */
/*05c0*/ ISETP.NE.AND P3, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fc40003f65270 */
/*05d0*/ ISETP.NE.AND P4, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fce0003f85270 */
/*05e0*/ @!P6 LDG.E.U8 R23, [R2.64+-0x8] ; /* 0xfffff8060217e981 */
/* 0x000ea4000c1e1100 */
/*05f0*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0600*/ IMAD R23, R22, c[0x0][0x170], R4 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e0204 */
/*0610*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0620*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*0630*/ PLOP3.LUT P6, PT, P5, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40002fcd570 */
/*0640*/ ISETP.NE.AND P5, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fd60003fa5270 */
/*0650*/ @!P6 LDG.E.U8 R23, [R2.64+-0x7] ; /* 0xfffff9060217e981 */
/* 0x000ea4000c1e1100 */
/*0660*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0670*/ IMAD R23, R22, c[0x0][0x170], R5 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e0205 */
/*0680*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0690*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*06a0*/ PLOP3.LUT P6, PT, P3, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40001fcd570 */
/*06b0*/ ISETP.NE.AND P3, PT, R29, RZ, PT ; /* 0x000000ff1d00720c */
/* 0x000fd60003f65270 */
/*06c0*/ @!P6 LDG.E.U8 R23, [R2.64+-0x6] ; /* 0xfffffa060217e981 */
/* 0x000ea4000c1e1100 */
/*06d0*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*06e0*/ IMAD R23, R22, c[0x0][0x170], R6 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e0206 */
/*06f0*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0700*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*0710*/ PLOP3.LUT P6, PT, P4, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe400027cd570 */
/*0720*/ ISETP.NE.AND P4, PT, R30, RZ, PT ; /* 0x000000ff1e00720c */
/* 0x000fd60003f85270 */
/*0730*/ @!P6 LDG.E.U8 R23, [R2.64+-0x5] ; /* 0xfffffb060217e981 */
/* 0x000ea4000c1e1100 */
/*0740*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0750*/ IMAD R23, R22, c[0x0][0x170], R7 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e0207 */
/*0760*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0770*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*0780*/ PLOP3.LUT P6, PT, P5, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40002fcd570 */
/*0790*/ ISETP.NE.AND P5, PT, R31, RZ, PT ; /* 0x000000ff1f00720c */
/* 0x000fd60003fa5270 */
/*07a0*/ @!P6 LDG.E.U8 R23, [R2.64+-0x4] ; /* 0xfffffc060217e981 */
/* 0x000ea4000c1e1100 */
/*07b0*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*07c0*/ IMAD R23, R22, c[0x0][0x170], R8 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e0208 */
/*07d0*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*07e0*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*07f0*/ PLOP3.LUT P6, PT, P3, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40001fcd570 */
/*0800*/ ISETP.NE.AND P3, PT, R32, RZ, PT ; /* 0x000000ff2000720c */
/* 0x000fd60003f65270 */
/*0810*/ @!P6 LDG.E.U8 R23, [R2.64+-0x3] ; /* 0xfffffd060217e981 */
/* 0x000ea4000c1e1100 */
/*0820*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0830*/ IMAD R23, R22, c[0x0][0x170], R9 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e0209 */
/*0840*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0850*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*0860*/ PLOP3.LUT P6, PT, P4, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe400027cd570 */
/*0870*/ ISETP.NE.AND P4, PT, R33, RZ, PT ; /* 0x000000ff2100720c */
/* 0x000fd60003f85270 */
/*0880*/ @!P6 LDG.E.U8 R23, [R2.64+-0x2] ; /* 0xfffffe060217e981 */
/* 0x000ea4000c1e1100 */
/*0890*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*08a0*/ IMAD R23, R22, c[0x0][0x170], R10 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e020a */
/*08b0*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*08c0*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*08d0*/ PLOP3.LUT P6, PT, P5, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40002fcd570 */
/*08e0*/ ISETP.NE.AND P5, PT, R34, RZ, PT ; /* 0x000000ff2200720c */
/* 0x000fd60003fa5270 */
/*08f0*/ @!P6 LDG.E.U8 R23, [R2.64+-0x1] ; /* 0xffffff060217e981 */
/* 0x000ea4000c1e1100 */
/*0900*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe200078e0217 */
/*0910*/ ISETP.GE.AND P6, PT, R38, UR4, PT ; /* 0x0000000426007c0c */
/* 0x000fc8000bfc6270 */
/*0920*/ ISETP.LT.OR P6, PT, R38, RZ, P6 ; /* 0x000000ff2600720c */
/* 0x000fc800037c1670 */
/*0930*/ PLOP3.LUT P6, PT, P3, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40001fcd570 */
/*0940*/ ISETP.NE.AND P3, PT, R37, RZ, PT ; /* 0x000000ff2500720c */
/* 0x000fd60003f65270 */
/*0950*/ @!P6 LDG.E.U8 R23, [R2.64] ; /* 0x000000060217e981 */
/* 0x000ea4000c1e1100 */
/*0960*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0970*/ IMAD R23, R22, c[0x0][0x170], R21 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e0215 */
/*0980*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0990*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*09a0*/ PLOP3.LUT P6, PT, P4, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe400027cd570 */
/*09b0*/ ISETP.NE.AND P4, PT, R36, RZ, PT ; /* 0x000000ff2400720c */
/* 0x000fd60003f85270 */
/*09c0*/ @!P6 LDG.E.U8 R23, [R2.64+0x1] ; /* 0x000001060217e981 */
/* 0x000ea4000c1e1100 */
/*09d0*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*09e0*/ IMAD R23, R22, c[0x0][0x170], R11 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e020b */
/*09f0*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0a00*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*0a10*/ PLOP3.LUT P6, PT, P5, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40002fcd570 */
/*0a20*/ ISETP.NE.AND P5, PT, R35, RZ, PT ; /* 0x000000ff2300720c */
/* 0x000fd60003fa5270 */
/*0a30*/ @!P6 LDG.E.U8 R23, [R2.64+0x2] ; /* 0x000002060217e981 */
/* 0x000ea4000c1e1100 */
/*0a40*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0a50*/ IMAD R23, R22, c[0x0][0x170], R12 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e020c */
/*0a60*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0a70*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*0a80*/ PLOP3.LUT P6, PT, P0, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00007cd570 */
/*0a90*/ @!P6 LDG.E.U8 R23, [R2.64+0x3] ; /* 0x000003060217e981 */
/* 0x000ea4000c1e1100 */
/*0aa0*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0ab0*/ IMAD R23, R22, c[0x0][0x170], R13 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e020d */
/*0ac0*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0ad0*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*0ae0*/ PLOP3.LUT P6, PT, P1, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000fcd570 */
/*0af0*/ @!P6 LDG.E.U8 R23, [R2.64+0x4] ; /* 0x000004060217e981 */
/* 0x000ea4000c1e1100 */
/*0b00*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0b10*/ IMAD R23, R22, c[0x0][0x170], R14 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e020e */
/*0b20*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0b30*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*0b40*/ PLOP3.LUT P6, PT, P2, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00017cd570 */
/*0b50*/ @!P6 LDG.E.U8 R23, [R2.64+0x5] ; /* 0x000005060217e981 */
/* 0x000ea4000c1e1100 */
/*0b60*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0b70*/ IMAD R23, R22, c[0x0][0x170], R15 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e020f */
/*0b80*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0b90*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*0ba0*/ PLOP3.LUT P6, PT, P3, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0001fcd570 */
/*0bb0*/ @!P6 LDG.E.U8 R23, [R2.64+0x6] ; /* 0x000006060217e981 */
/* 0x000ea4000c1e1100 */
/*0bc0*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0bd0*/ IMAD R23, R22, c[0x0][0x170], R16 ; /* 0x00005c0016177a24 */
/* 0x000fca00078e0210 */
/*0be0*/ ISETP.GE.AND P6, PT, R23, UR4, PT ; /* 0x0000000417007c0c */
/* 0x000fc8000bfc6270 */
/*0bf0*/ ISETP.LT.OR P6, PT, R23, RZ, P6 ; /* 0x000000ff1700720c */
/* 0x000fc800037c1670 */
/*0c00*/ PLOP3.LUT P6, PT, P4, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda00027cd570 */
/*0c10*/ @!P6 LDG.E.U8 R23, [R2.64+0x7] ; /* 0x000007060217e981 */
/* 0x000ea2000c1e1100 */
/*0c20*/ IMAD R22, R22, c[0x0][0x170], R17 ; /* 0x00005c0016167a24 */
/* 0x000fe400078e0211 */
/*0c30*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fc600078e0217 */
/*0c40*/ ISETP.GE.AND P6, PT, R22, UR4, PT ; /* 0x0000000416007c0c */
/* 0x000fc8000bfc6270 */
/*0c50*/ ISETP.LT.OR P6, PT, R22, RZ, P6 ; /* 0x000000ff1600720c */
/* 0x000fc800037c1670 */
/*0c60*/ PLOP3.LUT P6, PT, P5, P6, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0002fcd570 */
/*0c70*/ @!P6 LDG.E.U8 R23, [R2.64+0x8] ; /* 0x000008060217e981 */
/* 0x000ea4000c1e1100 */
/*0c80*/ @!P6 IMAD.IADD R20, R20, 0x1, R23 ; /* 0x000000011414e824 */
/* 0x004fe400078e0217 */
/*0c90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ca0*/ ISETP.NE.AND P6, PT, R18, 0x9, PT ; /* 0x000000091200780c */
/* 0x000fda0003fc5270 */
/*0cb0*/ @P6 BRA 0x490 ; /* 0xfffff7d000006947 */
/* 0x000fea000383ffff */
/*0cc0*/ IMAD R0, R19, c[0x0][0x170], R0 ; /* 0x00005c0013007a24 */
/* 0x000fe400078e0200 */
/*0cd0*/ IMAD.WIDE.U32 R20, R20, -0x1d3b5977, RZ ; /* 0xe2c4a68914147825 */
/* 0x000fc600078e00ff */
/*0ce0*/ IADD3 R2, P0, R0.reuse, c[0x0][0x168], RZ ; /* 0x00005a0000027a10 */
/* 0x040fe40007f1e0ff */
/*0cf0*/ SHF.R.U32.HI R21, RZ, 0x8, R21 ; /* 0x00000008ff157819 */
/* 0x000fe40000011615 */
/*0d00*/ LEA.HI.X.SX32 R3, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f0eff */
/*0d10*/ STG.E.U8 [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe2000c101106 */
/*0d20*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0d30*/ BRA 0xd30; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0da0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0db0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0dd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0de0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0df0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZL13averageKernelPhS_ii,"axG",@progbits,_ZL13averageKernelPhS_ii,comdat
.globl _ZL13averageKernelPhS_ii
.p2align 8
.type _ZL13averageKernelPhS_ii,@function
_ZL13averageKernelPhS_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
v_bfe_u32 v3, v0, 10, 10
s_load_b64 s[6:7], s[0:1], 0x0
v_and_b32_e32 v0, 0x3ff, v0
s_mov_b32 s8, -8
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mul_i32 s14, s14, s2
s_mul_i32 s3, s5, s4
v_add3_u32 v4, v0, s14, -8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v2, -8, v1
v_mul_lo_u32 v3, s4, v2
v_mov_b32_e32 v2, 0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_2
.p2align 6
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v3, s4, v3
s_add_i32 s8, s8, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s8, 9
s_cbranch_scc1 .LBB0_9
.LBB0_2:
v_add_nc_u32_e32 v5, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_ge_i32_e64 s2, s5, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s9, s2
s_cbranch_execz .LBB0_1
v_mov_b32_e32 v5, v4
s_mov_b32 s10, 17
s_branch .LBB0_6
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s11
v_add_nc_u32_e32 v5, 1, v5
s_add_i32 s10, s10, -1
s_cmp_lg_u32 s10, 0
s_cbranch_scc0 .LBB0_1
.LBB0_6:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_ge_i32_e64 s2, s4, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s11, s2
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v6
v_cmp_gt_i32_e64 s2, s3, v6
s_and_b32 s12, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s12
s_cbranch_execz .LBB0_4
global_load_u8 v6, v6, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v2, v6
s_branch .LBB0_4
.LBB0_9:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x8
v_mul_lo_u32 v1, v1, s4
v_mul_hi_u32 v2, v2, 0xe2c4a689
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add3_u32 v0, s14, v0, v1
v_lshrrev_b32_e32 v2, 8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZL13averageKernelPhS_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZL13averageKernelPhS_ii,"axG",@progbits,_ZL13averageKernelPhS_ii,comdat
.Lfunc_end0:
.size _ZL13averageKernelPhS_ii, .Lfunc_end0-_ZL13averageKernelPhS_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _ZL13averageKernelPhS_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZL13averageKernelPhS_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001454e7_00000000-6_averageKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL13averageKernelPhS_ii, @function
_ZL13averageKernelPhS_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
movq %rsi, 24(%rsp)
movl %edx, 8(%rsp)
movl %ecx, 12(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _ZL13averageKernelPhS_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _ZL13averageKernelPhS_ii, .-_ZL13averageKernelPhS_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13averageKernelPhS_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13averageKernelPhS_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "averageKernel.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <thrust/gather.h>
#include <thrust/sort.h>
#include <thrust/binary_search.h>
#include <thrust/device_vector.h>
//#include <cuda.h>
#include <thrust/copy.h>
#include <thrust/device_ptr.h>
#include <thrust/sequence.h>
#include <thrust/scan.h>
#include <thrust/transform.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <cmath>
#include "math.h"
extern "C" { //required to avoid name mangling in PyCUDA: https://devtalk.nvidia.com/default/topic/471412/pycuda-thrust-example-in-case-someone-is-curious/
void thrust_sort_double(double* input_ptr, int length)
{
thrust::device_ptr<double> thrust_ptr(input_ptr);
thrust::sort(thrust_ptr, thrust_ptr + length);
}
void thrust_sort_by_key_double(double* key_ptr, int length, double* val_ptr)
{
thrust::device_ptr<double> thrust_key_ptr(key_ptr);
thrust::device_ptr<double> thrust_val_ptr(val_ptr);
thrust::sort_by_key(thrust_key_ptr, thrust_key_ptr + length, thrust_val_ptr);
}
void thrust_get_sort_perm_double(double* input_ptr, int length, int* perm_ptr)
{
thrust::device_ptr<double> thrust_ptr(input_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::sequence(indices, indices + length);
thrust::sort_by_key(thrust_ptr, thrust_ptr + length, indices);
}
void thrust_get_sort_perm_long(long* input_ptr, int length, int* perm_ptr)
{
thrust::device_ptr<long> thrust_ptr(input_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::sequence(indices, indices + length);
thrust::sort_by_key(thrust_ptr, thrust_ptr + length, indices);
}
void thrust_get_sort_perm_int(int* input_ptr, int length, int* perm_ptr)
{
thrust::device_ptr<int> thrust_ptr(input_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::sequence(indices, indices + length);
thrust::sort_by_key(thrust_ptr, thrust_ptr + length, indices);
}
void thrust_apply_sort_perm_double(double* input_ptr, int length, double* output_ptr, int* perm_ptr)
{
thrust::device_ptr<double> thrust_input_ptr(input_ptr);
thrust::device_ptr<double> thrust_output_ptr(output_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::gather(indices, indices + length, thrust_input_ptr, thrust_output_ptr);
}
void thrust_apply_sort_perm_long(long* input_ptr, int length, long* output_ptr, int* perm_ptr)
{
thrust::device_ptr<long> thrust_input_ptr(input_ptr);
thrust::device_ptr<long> thrust_output_ptr(output_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::gather(indices, indices + length, thrust_input_ptr, thrust_output_ptr);
}
void thrust_apply_sort_perm_int(int* input_ptr, int length, int* output_ptr, int* perm_ptr)
{
thrust::device_ptr<int> thrust_input_ptr(input_ptr);
thrust::device_ptr<int> thrust_output_ptr(output_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::gather(indices, indices + length, thrust_input_ptr, thrust_output_ptr);
}
void thrust_lower_bound_int(int* sorted_ptr, int sorted_length, int* bounds_ptr, int bounds_length, int* output_ptr)
{
thrust::device_ptr<int> thrust_sorted_ptr(sorted_ptr);
thrust::device_ptr<int> thrust_bounds_ptr(bounds_ptr);
thrust::device_ptr<int> thrust_output_ptr(output_ptr);
thrust::lower_bound(thrust_sorted_ptr, thrust_sorted_ptr + sorted_length, thrust_bounds_ptr, thrust_bounds_ptr + bounds_length, thrust_output_ptr);
}
void thrust_upper_bound_int(int* sorted_ptr, int sorted_length, int* bounds_ptr, int bounds_length, int* output_ptr)
{
thrust::device_ptr<int> thrust_sorted_ptr(sorted_ptr);
thrust::device_ptr<int> thrust_bounds_ptr(bounds_ptr);
thrust::device_ptr<int> thrust_output_ptr(output_ptr);
thrust::upper_bound(thrust_sorted_ptr, thrust_sorted_ptr + sorted_length, thrust_bounds_ptr, thrust_bounds_ptr + bounds_length, thrust_output_ptr);
}
void thrust_cumsum_double(double* data_ptr, int length, double* sum_ptr)
{
thrust::device_ptr<double> thrust_data_ptr(data_ptr);
thrust::device_ptr<double> thrust_sum_ptr(sum_ptr);
thrust::inclusive_scan(thrust_data_ptr, thrust_data_ptr + length, thrust_sum_ptr);
}
void thrust_cumsum_int(int* data_ptr, int length, int* sum_ptr)
{
thrust::device_ptr<int> thrust_data_ptr(data_ptr);
thrust::device_ptr<int> thrust_sum_ptr(sum_ptr);
thrust::inclusive_scan(thrust_data_ptr, thrust_data_ptr + length, thrust_sum_ptr);
}
// ---------------- slice statistics using thrust ---------------- //
// StackOverflow inspired:
// http://stackoverflow.com/questions/12380966/standard-deviation-using-cuda
typedef double T;
// This example computes several statistical properties of a data
// series in a single reduction. The algorithm is described in detail here:
// http://en.wikipedia.org/wiki/Algorithms_for_calculating_variance#Parallel_algorithm
//
// Thanks to Joseph Rhoads for contributing this example
// structure used to accumulate the moments and other
// statistical properties encountered so far.
struct summary_stats_data
{
T n;
T mean;
T M2;
// initialize to the identity element
void initialize()
{
n = mean = M2 = 0;
}
__host__ __device__
T variance() { return M2 / (n - 1); }
__host__ __device__
T variance_n() { return M2 / n; }
};
// stats_unary_op is a functor that takes in a value x and
// returns a summary_stats_data whose mean value is initialized to x.
struct summary_stats_unary_op
{
__host__ __device__
summary_stats_data operator()(const T& x) const
{
summary_stats_data result;
result.n = 1;
result.mean = x;
result.M2 = 0;
return result;
}
};
// summary_stats_binary_op is a functor that accepts two summary_stats_data
// structs and returns a new summary_stats_data which are an
// approximation to the summary_stats for
// all values that have been agregated so far
struct summary_stats_binary_op
: public thrust::binary_function<const summary_stats_data&,
const summary_stats_data&,
summary_stats_data >
{
__host__ __device__
summary_stats_data operator()(const summary_stats_data& x,
const summary_stats_data& y) const
{
summary_stats_data result;
// precompute some common subexpressions
T n = x.n + y.n;
T delta = y.mean - x.mean;
T delta2 = delta * delta;
//Basic number of samples (n)
result.n = n;
result.mean = x.mean + delta * y.n / n;
result.M2 = x.M2 + y.M2;
result.M2 += delta2 * x.n * y.n / n;
return result;
}
};
struct extract_mean
{
__host__ __device__
T operator()(summary_stats_data& x)
{
return x.mean;
}
};
struct extract_std
{
__host__ __device__
T operator()(summary_stats_data& x)
{
if (x.n < 1.001) {
return 0.;
} else {
return std::sqrt(x.variance());
}
}
};
void thrust_stats_per_slice(
int* particle_slice_id_ptr, double* u, const int n_mp,
// int* n_macroparticles_per_slice, const int n_slices, // inputs end
int* slice_id_ptr, double* slice_mean_ptr,
double* slice_std_ptr, int* n_relevant_entries // outputs end
) {
// set up arguments
summary_stats_unary_op unary_op;
summary_stats_binary_op binary_op;
thrust::equal_to<int> binary_pred;
extract_mean unary_extract_mean;
extract_std unary_extract_std;
// input pointers
thrust::device_ptr<double> thrust_u(u);
thrust::device_ptr<int> thrust_p_sid(particle_slice_id_ptr);
// output pointers
thrust::device_ptr<int> thrust_sid(slice_id_ptr);
thrust::device_ptr<double> thrust_mean(slice_mean_ptr);
thrust::device_ptr<double> thrust_std(slice_std_ptr);
// intermediate summary_stats_data type arrays
thrust::device_vector<summary_stats_data> stats_vec(n_mp);
thrust::device_vector<summary_stats_data> stats_vec_out(n_mp);
// convert array to summary_stats_data type
thrust::transform(thrust_u, thrust_u + n_mp, stats_vec.begin(), unary_op);
// pointers to end of relevant reduced entries
typedef thrust::device_ptr<int> Iterator1;
typedef thrust::device_vector<summary_stats_data>::iterator Iterator2;
thrust::pair<Iterator1, Iterator2> new_end;
// compute statistics for each slice
new_end = thrust::reduce_by_key(
thrust_p_sid,
thrust_p_sid + n_mp,
stats_vec.begin(),
thrust_sid,
stats_vec_out.begin(),
binary_pred,
binary_op
);
// how many relevant reduced entries in the output arrays:
*n_relevant_entries = new_end.first - thrust_sid;
// extract results and write to output arrays
thrust::transform(stats_vec_out.begin(), new_end.second,
thrust_mean, unary_extract_mean);
thrust::transform(stats_vec_out.begin(), new_end.second,
thrust_std, unary_extract_std);
}
} // end extern "C" | #include <hip/hip_runtime.h>
#include <thrust/gather.h>
#include <thrust/sort.h>
#include <thrust/binary_search.h>
#include <thrust/device_vector.h>
//#include <cuda.h>
#include <thrust/copy.h>
#include <thrust/device_ptr.h>
#include <thrust/sequence.h>
#include <thrust/scan.h>
#include <thrust/transform.h>
#include <thrust/reduce.h>
#include <thrust/functional.h>
#include <cmath>
#include "math.h"
extern "C" { //required to avoid name mangling in PyCUDA: https://devtalk.nvidia.com/default/topic/471412/pycuda-thrust-example-in-case-someone-is-curious/
void thrust_sort_double(double* input_ptr, int length)
{
thrust::device_ptr<double> thrust_ptr(input_ptr);
thrust::sort(thrust_ptr, thrust_ptr + length);
}
void thrust_sort_by_key_double(double* key_ptr, int length, double* val_ptr)
{
thrust::device_ptr<double> thrust_key_ptr(key_ptr);
thrust::device_ptr<double> thrust_val_ptr(val_ptr);
thrust::sort_by_key(thrust_key_ptr, thrust_key_ptr + length, thrust_val_ptr);
}
void thrust_get_sort_perm_double(double* input_ptr, int length, int* perm_ptr)
{
thrust::device_ptr<double> thrust_ptr(input_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::sequence(indices, indices + length);
thrust::sort_by_key(thrust_ptr, thrust_ptr + length, indices);
}
void thrust_get_sort_perm_long(long* input_ptr, int length, int* perm_ptr)
{
thrust::device_ptr<long> thrust_ptr(input_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::sequence(indices, indices + length);
thrust::sort_by_key(thrust_ptr, thrust_ptr + length, indices);
}
void thrust_get_sort_perm_int(int* input_ptr, int length, int* perm_ptr)
{
thrust::device_ptr<int> thrust_ptr(input_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::sequence(indices, indices + length);
thrust::sort_by_key(thrust_ptr, thrust_ptr + length, indices);
}
void thrust_apply_sort_perm_double(double* input_ptr, int length, double* output_ptr, int* perm_ptr)
{
thrust::device_ptr<double> thrust_input_ptr(input_ptr);
thrust::device_ptr<double> thrust_output_ptr(output_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::gather(indices, indices + length, thrust_input_ptr, thrust_output_ptr);
}
void thrust_apply_sort_perm_long(long* input_ptr, int length, long* output_ptr, int* perm_ptr)
{
thrust::device_ptr<long> thrust_input_ptr(input_ptr);
thrust::device_ptr<long> thrust_output_ptr(output_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::gather(indices, indices + length, thrust_input_ptr, thrust_output_ptr);
}
void thrust_apply_sort_perm_int(int* input_ptr, int length, int* output_ptr, int* perm_ptr)
{
thrust::device_ptr<int> thrust_input_ptr(input_ptr);
thrust::device_ptr<int> thrust_output_ptr(output_ptr);
thrust::device_ptr<int> indices(perm_ptr);
thrust::gather(indices, indices + length, thrust_input_ptr, thrust_output_ptr);
}
void thrust_lower_bound_int(int* sorted_ptr, int sorted_length, int* bounds_ptr, int bounds_length, int* output_ptr)
{
thrust::device_ptr<int> thrust_sorted_ptr(sorted_ptr);
thrust::device_ptr<int> thrust_bounds_ptr(bounds_ptr);
thrust::device_ptr<int> thrust_output_ptr(output_ptr);
thrust::lower_bound(thrust_sorted_ptr, thrust_sorted_ptr + sorted_length, thrust_bounds_ptr, thrust_bounds_ptr + bounds_length, thrust_output_ptr);
}
void thrust_upper_bound_int(int* sorted_ptr, int sorted_length, int* bounds_ptr, int bounds_length, int* output_ptr)
{
thrust::device_ptr<int> thrust_sorted_ptr(sorted_ptr);
thrust::device_ptr<int> thrust_bounds_ptr(bounds_ptr);
thrust::device_ptr<int> thrust_output_ptr(output_ptr);
thrust::upper_bound(thrust_sorted_ptr, thrust_sorted_ptr + sorted_length, thrust_bounds_ptr, thrust_bounds_ptr + bounds_length, thrust_output_ptr);
}
void thrust_cumsum_double(double* data_ptr, int length, double* sum_ptr)
{
thrust::device_ptr<double> thrust_data_ptr(data_ptr);
thrust::device_ptr<double> thrust_sum_ptr(sum_ptr);
thrust::inclusive_scan(thrust_data_ptr, thrust_data_ptr + length, thrust_sum_ptr);
}
void thrust_cumsum_int(int* data_ptr, int length, int* sum_ptr)
{
thrust::device_ptr<int> thrust_data_ptr(data_ptr);
thrust::device_ptr<int> thrust_sum_ptr(sum_ptr);
thrust::inclusive_scan(thrust_data_ptr, thrust_data_ptr + length, thrust_sum_ptr);
}
// ---------------- slice statistics using thrust ---------------- //
// StackOverflow inspired:
// http://stackoverflow.com/questions/12380966/standard-deviation-using-cuda
typedef double T;
// This example computes several statistical properties of a data
// series in a single reduction. The algorithm is described in detail here:
// http://en.wikipedia.org/wiki/Algorithms_for_calculating_variance#Parallel_algorithm
//
// Thanks to Joseph Rhoads for contributing this example
// structure used to accumulate the moments and other
// statistical properties encountered so far.
struct summary_stats_data
{
T n;
T mean;
T M2;
// initialize to the identity element
void initialize()
{
n = mean = M2 = 0;
}
__host__ __device__
T variance() { return M2 / (n - 1); }
__host__ __device__
T variance_n() { return M2 / n; }
};
// stats_unary_op is a functor that takes in a value x and
// returns a summary_stats_data whose mean value is initialized to x.
struct summary_stats_unary_op
{
__host__ __device__
summary_stats_data operator()(const T& x) const
{
summary_stats_data result;
result.n = 1;
result.mean = x;
result.M2 = 0;
return result;
}
};
// summary_stats_binary_op is a functor that accepts two summary_stats_data
// structs and returns a new summary_stats_data which are an
// approximation to the summary_stats for
// all values that have been agregated so far
struct summary_stats_binary_op
: public thrust::binary_function<const summary_stats_data&,
const summary_stats_data&,
summary_stats_data >
{
__host__ __device__
summary_stats_data operator()(const summary_stats_data& x,
const summary_stats_data& y) const
{
summary_stats_data result;
// precompute some common subexpressions
T n = x.n + y.n;
T delta = y.mean - x.mean;
T delta2 = delta * delta;
//Basic number of samples (n)
result.n = n;
result.mean = x.mean + delta * y.n / n;
result.M2 = x.M2 + y.M2;
result.M2 += delta2 * x.n * y.n / n;
return result;
}
};
struct extract_mean
{
__host__ __device__
T operator()(summary_stats_data& x)
{
return x.mean;
}
};
struct extract_std
{
__host__ __device__
T operator()(summary_stats_data& x)
{
if (x.n < 1.001) {
return 0.;
} else {
return std::sqrt(x.variance());
}
}
};
void thrust_stats_per_slice(
int* particle_slice_id_ptr, double* u, const int n_mp,
// int* n_macroparticles_per_slice, const int n_slices, // inputs end
int* slice_id_ptr, double* slice_mean_ptr,
double* slice_std_ptr, int* n_relevant_entries // outputs end
) {
// set up arguments
summary_stats_unary_op unary_op;
summary_stats_binary_op binary_op;
thrust::equal_to<int> binary_pred;
extract_mean unary_extract_mean;
extract_std unary_extract_std;
// input pointers
thrust::device_ptr<double> thrust_u(u);
thrust::device_ptr<int> thrust_p_sid(particle_slice_id_ptr);
// output pointers
thrust::device_ptr<int> thrust_sid(slice_id_ptr);
thrust::device_ptr<double> thrust_mean(slice_mean_ptr);
thrust::device_ptr<double> thrust_std(slice_std_ptr);
// intermediate summary_stats_data type arrays
thrust::device_vector<summary_stats_data> stats_vec(n_mp);
thrust::device_vector<summary_stats_data> stats_vec_out(n_mp);
// convert array to summary_stats_data type
thrust::transform(thrust_u, thrust_u + n_mp, stats_vec.begin(), unary_op);
// pointers to end of relevant reduced entries
typedef thrust::device_ptr<int> Iterator1;
typedef thrust::device_vector<summary_stats_data>::iterator Iterator2;
thrust::pair<Iterator1, Iterator2> new_end;
// compute statistics for each slice
new_end = thrust::reduce_by_key(
thrust_p_sid,
thrust_p_sid + n_mp,
stats_vec.begin(),
thrust_sid,
stats_vec_out.begin(),
binary_pred,
binary_op
);
// how many relevant reduced entries in the output arrays:
*n_relevant_entries = new_end.first - thrust_sid;
// extract results and write to output arrays
thrust::transform(stats_vec_out.begin(), new_end.second,
thrust_mean, unary_extract_mean);
thrust::transform(stats_vec_out.begin(), new_end.second,
thrust_std, unary_extract_std);
}
} // end extern "C" |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
/*__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz, float* p_xyt_real, float* p_xyt_imag,
float* sensor_pos, float* origin, float* laser_pos, float dx, float dz, int NX, int NY, int NZ,
float c_dt, int N_pos, int Nt, float ReceiveDelay)
{
int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
float tao = 0.0;
float voxel_int_real = 0.0, voxel_int_imag =0.0;
float voxel_real = 0.0, voxel_imag =0.0;
int Index = 0, counter = 1;
float GPS_x = origin[0] - (nx-NX/2)*dx; // x-coordiante for the voxel
float GPS_y = origin[1] + (ny-NY/2)*dx; // y-coordiante for the voxel
float GPS_z = origin[2] + (nz)*dz; // z-coordiante for the voxel
// time delay from the laser spot to the voxel
float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
float x_pos,y_pos,z_pos, cos_theta;
float voxel_int_real_tp[NPOINT], voxel_int_imag_tp[NPOINT], voxel_sq_real_tp[NPOINT], voxel_sq_imag_tp[NPOINT];
for(int K = 0; K<NPOINT; K++)
{
voxel_int_real_tp[K] = 0.0;
voxel_int_imag_tp[K] = 0.0;
voxel_sq_real_tp[K] = 0.0;
voxel_sq_imag_tp[K] = 0.0;
}
for(int K_x = 0;K_x<N_pos; K_x++)
{
x_pos = sensor_pos[K_x];
y_pos = sensor_pos[K_x+N_pos];
z_pos = sensor_pos[K_x+2*N_pos];
tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
cos_theta = GPS_z/(tao + 1e-6);
Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
if((Index<Nt-NPOINT*STRIDE) && (Index>0))
{
for(int P = 0; P<NPOINT; P++)
{
voxel_real = p_xyt_real[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
voxel_imag = p_xyt_imag[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
voxel_int_real_tp[P] = voxel_int_real_tp[P] + voxel_real; //* sqrt(Index*1.0);
voxel_int_imag_tp[P] = voxel_int_imag_tp[P] + voxel_imag; //* sqrt(Index*1.0);
voxel_sq_real_tp[P] = voxel_sq_real_tp[P] + voxel_real * voxel_real;
voxel_sq_imag_tp[P] = voxel_sq_imag_tp[P] + voxel_imag * voxel_imag;
}
counter = counter+1;
}
}
voxel_int_real = voxel_int_real_tp[0];
voxel_int_imag = voxel_int_imag_tp[0];
for (int J=0;J<NPOINT;J++)
{
if((voxel_sq_real_tp[J]>1e-6) && (voxel_sq_imag_tp[J]>1e-6))
{
CF_real = CF_real + powf(voxel_int_real_tp[J],2)/voxel_sq_real_tp[J]/counter;
CF_imag = CF_imag + powf(voxel_int_imag_tp[J],2)/voxel_sq_imag_tp[J]/counter;
}
}
CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real + voxel_int_imag * voxel_int_imag ) * (CF);
}*/
// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz, float* p_xyt_real, float* p_xyt_imag,
float* sensor_pos, float* origin, float* laser_pos, float dx, float dz, int NX, int NY, int NZ,
float c_dt, int N_pos, int Nt, float ReceiveDelay)
{
int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
float tao = 0.0;
float voxel_int_real = 0.0, voxel_int_imag =0.0;
float voxel_real = 0.0, voxel_imag =0.0;
int Index = 0, counter = 1;
float GPS_x = origin[0] - (nx-NX/2)*dx; // x-coordiante for the voxel
float GPS_y = origin[1] + (ny-NY/2)*dx; // y-coordiante for the voxel
float GPS_z = origin[2] + (nz)*dz; // z-coordiante for the voxel
// time delay from the laser spot to the voxel
float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
float x_pos,y_pos,z_pos, cos_theta;
float voxel_sq_real, voxel_sq_imag;
for(int K_x = 0;K_x<N_pos; K_x++)
{
x_pos = sensor_pos[K_x];
y_pos = sensor_pos[K_x+N_pos];
z_pos = sensor_pos[K_x+2*N_pos];
tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
cos_theta = GPS_z/(tao + 1e-6);
Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
if((Index<Nt) && (Index>0))
{
voxel_real = p_xyt_real[Index+K_x*(Nt)] * cos_theta;
voxel_imag = p_xyt_imag[Index+K_x*(Nt)] * cos_theta;
voxel_int_real = voxel_int_real + voxel_real; //* sqrt(Index*1.0);
voxel_int_imag = voxel_int_imag + voxel_imag; //* sqrt(Index*1.0);
voxel_sq_real = voxel_sq_real + voxel_real * voxel_real;
voxel_sq_imag = voxel_sq_imag + voxel_imag * voxel_imag;
counter = counter+1;
}
}
if((voxel_sq_real>1e-6) && (voxel_sq_imag>1e-6))
{
CF_real = CF_real + powf(voxel_int_real,2)/voxel_sq_real/counter;
CF_imag = CF_imag + powf(voxel_int_imag,2)/voxel_sq_imag/counter;
}
CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real + voxel_int_imag * voxel_int_imag ) * (CF);
} | .file "tmpxft_0018d1be_00000000-6_PhasorField.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif
.type _Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif, @function
_Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movss %xmm3, (%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 4(%rsp), %rax
movq %rax, 216(%rsp)
leaq 296(%rsp), %rax
movq %rax, 224(%rsp)
leaq 304(%rsp), %rax
movq %rax, 232(%rsp)
movq %rsp, %rax
movq %rax, 240(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 280
pushq 72(%rsp)
.cfi_def_cfa_offset 288
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif, .-_Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif
.globl _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.type _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, @function
_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, .-_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
/*__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz, float* p_xyt_real, float* p_xyt_imag,
float* sensor_pos, float* origin, float* laser_pos, float dx, float dz, int NX, int NY, int NZ,
float c_dt, int N_pos, int Nt, float ReceiveDelay)
{
int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
float tao = 0.0;
float voxel_int_real = 0.0, voxel_int_imag =0.0;
float voxel_real = 0.0, voxel_imag =0.0;
int Index = 0, counter = 1;
float GPS_x = origin[0] - (nx-NX/2)*dx; // x-coordiante for the voxel
float GPS_y = origin[1] + (ny-NY/2)*dx; // y-coordiante for the voxel
float GPS_z = origin[2] + (nz)*dz; // z-coordiante for the voxel
// time delay from the laser spot to the voxel
float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
float x_pos,y_pos,z_pos, cos_theta;
float voxel_int_real_tp[NPOINT], voxel_int_imag_tp[NPOINT], voxel_sq_real_tp[NPOINT], voxel_sq_imag_tp[NPOINT];
for(int K = 0; K<NPOINT; K++)
{
voxel_int_real_tp[K] = 0.0;
voxel_int_imag_tp[K] = 0.0;
voxel_sq_real_tp[K] = 0.0;
voxel_sq_imag_tp[K] = 0.0;
}
for(int K_x = 0;K_x<N_pos; K_x++)
{
x_pos = sensor_pos[K_x];
y_pos = sensor_pos[K_x+N_pos];
z_pos = sensor_pos[K_x+2*N_pos];
tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
cos_theta = GPS_z/(tao + 1e-6);
Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
if((Index<Nt-NPOINT*STRIDE) && (Index>0))
{
for(int P = 0; P<NPOINT; P++)
{
voxel_real = p_xyt_real[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
voxel_imag = p_xyt_imag[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
voxel_int_real_tp[P] = voxel_int_real_tp[P] + voxel_real; //* sqrt(Index*1.0);
voxel_int_imag_tp[P] = voxel_int_imag_tp[P] + voxel_imag; //* sqrt(Index*1.0);
voxel_sq_real_tp[P] = voxel_sq_real_tp[P] + voxel_real * voxel_real;
voxel_sq_imag_tp[P] = voxel_sq_imag_tp[P] + voxel_imag * voxel_imag;
}
counter = counter+1;
}
}
voxel_int_real = voxel_int_real_tp[0];
voxel_int_imag = voxel_int_imag_tp[0];
for (int J=0;J<NPOINT;J++)
{
if((voxel_sq_real_tp[J]>1e-6) && (voxel_sq_imag_tp[J]>1e-6))
{
CF_real = CF_real + powf(voxel_int_real_tp[J],2)/voxel_sq_real_tp[J]/counter;
CF_imag = CF_imag + powf(voxel_int_imag_tp[J],2)/voxel_sq_imag_tp[J]/counter;
}
}
CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real + voxel_int_imag * voxel_int_imag ) * (CF);
}*/
// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz, float* p_xyt_real, float* p_xyt_imag,
float* sensor_pos, float* origin, float* laser_pos, float dx, float dz, int NX, int NY, int NZ,
float c_dt, int N_pos, int Nt, float ReceiveDelay)
{
int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
float tao = 0.0;
float voxel_int_real = 0.0, voxel_int_imag =0.0;
float voxel_real = 0.0, voxel_imag =0.0;
int Index = 0, counter = 1;
float GPS_x = origin[0] - (nx-NX/2)*dx; // x-coordiante for the voxel
float GPS_y = origin[1] + (ny-NY/2)*dx; // y-coordiante for the voxel
float GPS_z = origin[2] + (nz)*dz; // z-coordiante for the voxel
// time delay from the laser spot to the voxel
float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
float x_pos,y_pos,z_pos, cos_theta;
float voxel_sq_real, voxel_sq_imag;
for(int K_x = 0;K_x<N_pos; K_x++)
{
x_pos = sensor_pos[K_x];
y_pos = sensor_pos[K_x+N_pos];
z_pos = sensor_pos[K_x+2*N_pos];
tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
cos_theta = GPS_z/(tao + 1e-6);
Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
if((Index<Nt) && (Index>0))
{
voxel_real = p_xyt_real[Index+K_x*(Nt)] * cos_theta;
voxel_imag = p_xyt_imag[Index+K_x*(Nt)] * cos_theta;
voxel_int_real = voxel_int_real + voxel_real; //* sqrt(Index*1.0);
voxel_int_imag = voxel_int_imag + voxel_imag; //* sqrt(Index*1.0);
voxel_sq_real = voxel_sq_real + voxel_real * voxel_real;
voxel_sq_imag = voxel_sq_imag + voxel_imag * voxel_imag;
counter = counter+1;
}
}
if((voxel_sq_real>1e-6) && (voxel_sq_imag>1e-6))
{
CF_real = CF_real + powf(voxel_int_real,2)/voxel_sq_real/counter;
CF_imag = CF_imag + powf(voxel_int_imag,2)/voxel_sq_imag/counter;
}
CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real + voxel_int_imag * voxel_int_imag ) * (CF);
} | #include <hip/hip_runtime.h>
// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
/*__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz, float* p_xyt_real, float* p_xyt_imag,
float* sensor_pos, float* origin, float* laser_pos, float dx, float dz, int NX, int NY, int NZ,
float c_dt, int N_pos, int Nt, float ReceiveDelay)
{
int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
float tao = 0.0;
float voxel_int_real = 0.0, voxel_int_imag =0.0;
float voxel_real = 0.0, voxel_imag =0.0;
int Index = 0, counter = 1;
float GPS_x = origin[0] - (nx-NX/2)*dx; // x-coordiante for the voxel
float GPS_y = origin[1] + (ny-NY/2)*dx; // y-coordiante for the voxel
float GPS_z = origin[2] + (nz)*dz; // z-coordiante for the voxel
// time delay from the laser spot to the voxel
float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
float x_pos,y_pos,z_pos, cos_theta;
float voxel_int_real_tp[NPOINT], voxel_int_imag_tp[NPOINT], voxel_sq_real_tp[NPOINT], voxel_sq_imag_tp[NPOINT];
for(int K = 0; K<NPOINT; K++)
{
voxel_int_real_tp[K] = 0.0;
voxel_int_imag_tp[K] = 0.0;
voxel_sq_real_tp[K] = 0.0;
voxel_sq_imag_tp[K] = 0.0;
}
for(int K_x = 0;K_x<N_pos; K_x++)
{
x_pos = sensor_pos[K_x];
y_pos = sensor_pos[K_x+N_pos];
z_pos = sensor_pos[K_x+2*N_pos];
tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
cos_theta = GPS_z/(tao + 1e-6);
Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
if((Index<Nt-NPOINT*STRIDE) && (Index>0))
{
for(int P = 0; P<NPOINT; P++)
{
voxel_real = p_xyt_real[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
voxel_imag = p_xyt_imag[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
voxel_int_real_tp[P] = voxel_int_real_tp[P] + voxel_real; //* sqrt(Index*1.0);
voxel_int_imag_tp[P] = voxel_int_imag_tp[P] + voxel_imag; //* sqrt(Index*1.0);
voxel_sq_real_tp[P] = voxel_sq_real_tp[P] + voxel_real * voxel_real;
voxel_sq_imag_tp[P] = voxel_sq_imag_tp[P] + voxel_imag * voxel_imag;
}
counter = counter+1;
}
}
voxel_int_real = voxel_int_real_tp[0];
voxel_int_imag = voxel_int_imag_tp[0];
for (int J=0;J<NPOINT;J++)
{
if((voxel_sq_real_tp[J]>1e-6) && (voxel_sq_imag_tp[J]>1e-6))
{
CF_real = CF_real + powf(voxel_int_real_tp[J],2)/voxel_sq_real_tp[J]/counter;
CF_imag = CF_imag + powf(voxel_int_imag_tp[J],2)/voxel_sq_imag_tp[J]/counter;
}
}
CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real + voxel_int_imag * voxel_int_imag ) * (CF);
}*/
// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz, float* p_xyt_real, float* p_xyt_imag,
float* sensor_pos, float* origin, float* laser_pos, float dx, float dz, int NX, int NY, int NZ,
float c_dt, int N_pos, int Nt, float ReceiveDelay)
{
int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
float tao = 0.0;
float voxel_int_real = 0.0, voxel_int_imag =0.0;
float voxel_real = 0.0, voxel_imag =0.0;
int Index = 0, counter = 1;
float GPS_x = origin[0] - (nx-NX/2)*dx; // x-coordiante for the voxel
float GPS_y = origin[1] + (ny-NY/2)*dx; // y-coordiante for the voxel
float GPS_z = origin[2] + (nz)*dz; // z-coordiante for the voxel
// time delay from the laser spot to the voxel
float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
float x_pos,y_pos,z_pos, cos_theta;
float voxel_sq_real, voxel_sq_imag;
for(int K_x = 0;K_x<N_pos; K_x++)
{
x_pos = sensor_pos[K_x];
y_pos = sensor_pos[K_x+N_pos];
z_pos = sensor_pos[K_x+2*N_pos];
tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
cos_theta = GPS_z/(tao + 1e-6);
Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
if((Index<Nt) && (Index>0))
{
voxel_real = p_xyt_real[Index+K_x*(Nt)] * cos_theta;
voxel_imag = p_xyt_imag[Index+K_x*(Nt)] * cos_theta;
voxel_int_real = voxel_int_real + voxel_real; //* sqrt(Index*1.0);
voxel_int_imag = voxel_int_imag + voxel_imag; //* sqrt(Index*1.0);
voxel_sq_real = voxel_sq_real + voxel_real * voxel_real;
voxel_sq_imag = voxel_sq_imag + voxel_imag * voxel_imag;
counter = counter+1;
}
}
if((voxel_sq_real>1e-6) && (voxel_sq_imag>1e-6))
{
CF_real = CF_real + powf(voxel_int_real,2)/voxel_sq_real/counter;
CF_imag = CF_imag + powf(voxel_int_imag,2)/voxel_sq_imag/counter;
}
CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real + voxel_int_imag * voxel_int_imag ) * (CF);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
/*__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz, float* p_xyt_real, float* p_xyt_imag,
float* sensor_pos, float* origin, float* laser_pos, float dx, float dz, int NX, int NY, int NZ,
float c_dt, int N_pos, int Nt, float ReceiveDelay)
{
int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
float tao = 0.0;
float voxel_int_real = 0.0, voxel_int_imag =0.0;
float voxel_real = 0.0, voxel_imag =0.0;
int Index = 0, counter = 1;
float GPS_x = origin[0] - (nx-NX/2)*dx; // x-coordiante for the voxel
float GPS_y = origin[1] + (ny-NY/2)*dx; // y-coordiante for the voxel
float GPS_z = origin[2] + (nz)*dz; // z-coordiante for the voxel
// time delay from the laser spot to the voxel
float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
float x_pos,y_pos,z_pos, cos_theta;
float voxel_int_real_tp[NPOINT], voxel_int_imag_tp[NPOINT], voxel_sq_real_tp[NPOINT], voxel_sq_imag_tp[NPOINT];
for(int K = 0; K<NPOINT; K++)
{
voxel_int_real_tp[K] = 0.0;
voxel_int_imag_tp[K] = 0.0;
voxel_sq_real_tp[K] = 0.0;
voxel_sq_imag_tp[K] = 0.0;
}
for(int K_x = 0;K_x<N_pos; K_x++)
{
x_pos = sensor_pos[K_x];
y_pos = sensor_pos[K_x+N_pos];
z_pos = sensor_pos[K_x+2*N_pos];
tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
cos_theta = GPS_z/(tao + 1e-6);
Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
if((Index<Nt-NPOINT*STRIDE) && (Index>0))
{
for(int P = 0; P<NPOINT; P++)
{
voxel_real = p_xyt_real[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
voxel_imag = p_xyt_imag[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
voxel_int_real_tp[P] = voxel_int_real_tp[P] + voxel_real; //* sqrt(Index*1.0);
voxel_int_imag_tp[P] = voxel_int_imag_tp[P] + voxel_imag; //* sqrt(Index*1.0);
voxel_sq_real_tp[P] = voxel_sq_real_tp[P] + voxel_real * voxel_real;
voxel_sq_imag_tp[P] = voxel_sq_imag_tp[P] + voxel_imag * voxel_imag;
}
counter = counter+1;
}
}
voxel_int_real = voxel_int_real_tp[0];
voxel_int_imag = voxel_int_imag_tp[0];
for (int J=0;J<NPOINT;J++)
{
if((voxel_sq_real_tp[J]>1e-6) && (voxel_sq_imag_tp[J]>1e-6))
{
CF_real = CF_real + powf(voxel_int_real_tp[J],2)/voxel_sq_real_tp[J]/counter;
CF_imag = CF_imag + powf(voxel_int_imag_tp[J],2)/voxel_sq_imag_tp[J]/counter;
}
}
CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real + voxel_int_imag * voxel_int_imag ) * (CF);
}*/
// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz, float* p_xyt_real, float* p_xyt_imag,
float* sensor_pos, float* origin, float* laser_pos, float dx, float dz, int NX, int NY, int NZ,
float c_dt, int N_pos, int Nt, float ReceiveDelay)
{
int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
float tao = 0.0;
float voxel_int_real = 0.0, voxel_int_imag =0.0;
float voxel_real = 0.0, voxel_imag =0.0;
int Index = 0, counter = 1;
float GPS_x = origin[0] - (nx-NX/2)*dx; // x-coordiante for the voxel
float GPS_y = origin[1] + (ny-NY/2)*dx; // y-coordiante for the voxel
float GPS_z = origin[2] + (nz)*dz; // z-coordiante for the voxel
// time delay from the laser spot to the voxel
float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
float x_pos,y_pos,z_pos, cos_theta;
float voxel_sq_real, voxel_sq_imag;
for(int K_x = 0;K_x<N_pos; K_x++)
{
x_pos = sensor_pos[K_x];
y_pos = sensor_pos[K_x+N_pos];
z_pos = sensor_pos[K_x+2*N_pos];
tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
cos_theta = GPS_z/(tao + 1e-6);
Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
if((Index<Nt) && (Index>0))
{
voxel_real = p_xyt_real[Index+K_x*(Nt)] * cos_theta;
voxel_imag = p_xyt_imag[Index+K_x*(Nt)] * cos_theta;
voxel_int_real = voxel_int_real + voxel_real; //* sqrt(Index*1.0);
voxel_int_imag = voxel_int_imag + voxel_imag; //* sqrt(Index*1.0);
voxel_sq_real = voxel_sq_real + voxel_real * voxel_real;
voxel_sq_imag = voxel_sq_imag + voxel_imag * voxel_imag;
counter = counter+1;
}
}
if((voxel_sq_real>1e-6) && (voxel_sq_imag>1e-6))
{
CF_real = CF_real + powf(voxel_int_real,2)/voxel_sq_real/counter;
CF_imag = CF_imag + powf(voxel_int_imag,2)/voxel_sq_imag/counter;
}
CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real + voxel_int_imag * voxel_int_imag ) * (CF);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.globl _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.p2align 8
.type _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif,@function
_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x64
s_load_b32 s12, s[0:1], 0x48
s_load_b64 s[16:17], s[0:1], 0x38
v_bfe_u32 v1, v0, 20, 10
v_and_b32_e32 v6, 0x3ff, v0
v_bfe_u32 v5, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s13, s2, v[6:7]
v_mov_b32_e32 v1, 0
v_mad_u64_u32 v[3:4], null, s14, s4, v[5:6]
s_cmp_lt_i32 s12, 1
s_mov_b32 s3, 0
s_cbranch_scc1 .LBB0_6
s_clause 0x1
s_load_b256 s[4:11], s[0:1], 0x8
s_load_b128 s[24:27], s[0:1], 0x28
s_lshr_b32 s2, s16, 31
s_lshr_b32 s13, s17, 31
s_add_i32 s2, s16, s2
s_load_b32 s22, s[0:1], 0x44
s_ashr_i32 s2, s2, 1
s_mov_b32 s21, 0x3eb0c6f7
v_subrev_nc_u32_e32 v1, s2, v0
s_mov_b32 s20, 0xa0b5ed8d
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
s_waitcnt lgkmcnt(0)
s_load_b64 s[14:15], s[10:11], 0x0
s_load_b64 s[18:19], s[24:25], 0x0
s_load_b32 s10, s[10:11], 0x8
s_add_i32 s11, s17, s13
s_mov_b32 s13, s3
s_ashr_i32 s2, s11, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v4, s2, v3
s_load_b32 s2, s[24:25], 0x8
v_cvt_f32_i32_e32 v4, v4
s_waitcnt lgkmcnt(0)
v_fma_f32 v9, -v1, s26, s14
v_cvt_f32_i32_e32 v1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, v4, s26, s15
v_sub_f32_e32 v4, s18, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v11, v1, s27, s10
v_sub_f32_e32 v1, s19, v10
s_load_b64 s[10:11], s[0:1], 0x4c
s_lshl_b64 s[18:19], s[12:13], 2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v4, v4, v4 :: v_dual_sub_f32 v5, s2, v11
v_fmac_f32_e32 v4, v1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v5
v_mul_f32_e32 v1, 0x4f800000, v4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, v4, v1, vcc_lo
v_cvt_f64_f32_e32 v[4:5], v11
v_sqrt_f32_e32 v1, v6
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v1
v_add_nc_u32_e32 v8, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v12, -v7, v1, v6
v_fma_f32 v13, -v8, v1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e64 s2, 0, v12
v_mov_b32_e32 v12, 1
v_cndmask_b32_e64 v1, v1, v7, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v13
v_cndmask_b32_e64 v1, v1, v8, s2
s_lshl_b32 s2, s12, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[14:15], s[2:3], 2
v_mul_f32_e32 v7, 0x37800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v1, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x260
v_mov_b32_e32 v1, 0
v_dual_cndmask_b32 v13, v7, v6 :: v_dual_mov_b32 v6, 0
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_add_i32 s12, s12, -1
s_add_i32 s3, s3, s10
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_cmp_eq_u32 s12, 0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_add_u32 s24, s8, s18
s_addc_u32 s25, s9, s19
s_clause 0x1
s_load_b32 s2, s[24:25], 0x0
s_load_b32 s13, s[8:9], 0x0
s_add_u32 s24, s8, s14
s_addc_u32 s25, s9, s15
s_load_b32 s23, s[24:25], 0x0
s_waitcnt lgkmcnt(0)
v_dual_sub_f32 v14, s2, v10 :: v_dual_sub_f32 v15, s13, v9
v_sub_f32_e32 v16, s23, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v14, v14, v14
v_fmac_f32_e32 v14, v15, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v14, v16, v16
v_mul_f32_e32 v15, 0x4f800000, v14
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v14, v14, v15, vcc_lo
v_sqrt_f32_e32 v15, v14
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v16, -1, v15
v_add_nc_u32_e32 v17, 1, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v18, -v16, v15, v14
v_fma_f32 v19, -v17, v15, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s2, 0, v18
v_cndmask_b32_e64 v15, v15, v16, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s2, 0, v19
v_cndmask_b32_e64 v15, v15, v17, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v16, 0x37800000, v15
v_cndmask_b32_e32 v15, v15, v16, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v14, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v14, v15, v14, vcc_lo
v_add_f32_e32 v15, v13, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v16, null, s22, s22, v15
v_div_scale_f32 v19, vcc_lo, v15, s22, v15
v_rcp_f32_e32 v17, v16
s_waitcnt_depctr 0xfff
v_fma_f32 v18, -v16, v17, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v17, v18, v17
v_mul_f32_e32 v18, v19, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v20, -v16, v18, v19
v_fmac_f32_e32 v18, v20, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v16, -v16, v18, v19
v_div_fmas_f32 v16, v16, v17, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v15, v16, s22, v15
v_subrev_f32_e32 v15, s11, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v15, v15
v_cvt_i32_f32_e32 v15, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s10, v15
v_cmp_lt_i32_e64 s2, 0, v15
s_and_b32 s13, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s13
s_cbranch_execz .LBB0_2
v_cvt_f64_f32_e32 v[16:17], v14
v_add_nc_u32_e32 v14, s3, v15
v_add_nc_u32_e32 v12, 1, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v15, 31, v14
v_lshlrev_b64 v[14:15], 2, v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v24, vcc_lo, s4, v14
v_add_co_ci_u32_e32 v25, vcc_lo, s5, v15, vcc_lo
v_add_co_u32 v14, vcc_lo, s6, v14
v_add_co_ci_u32_e32 v15, vcc_lo, s7, v15, vcc_lo
global_load_b32 v24, v[24:25], off
global_load_b32 v25, v[14:15], off
v_add_f64 v[16:17], v[16:17], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f64 v[18:19], null, v[16:17], v[16:17], v[4:5]
v_rcp_f64_e32 v[20:21], v[18:19]
s_waitcnt_depctr 0xfff
v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[20:21], v[22:23], v[20:21]
v_div_scale_f64 v[22:23], vcc_lo, v[4:5], v[16:17], v[4:5]
v_fma_f64 v[20:21], -v[18:19], v[14:15], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[14:15], v[20:21], v[14:15]
v_mul_f64 v[20:21], v[22:23], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[18:19], -v[18:19], v[20:21], v[22:23]
v_div_fmas_f64 v[14:15], v[18:19], v[14:15], v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[14:15], v[14:15], v[16:17], v[4:5]
v_cvt_f32_f64_e32 v14, v[14:15]
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_mul_f32_e32 v15, v24, v14
s_waitcnt vmcnt(0)
v_mul_f32_e32 v16, v25, v14
v_fmac_f32_e32 v1, v24, v14
v_fmac_f32_e32 v6, v25, v14
v_dual_fmac_f32 v8, v15, v15 :: v_dual_fmac_f32 v7, v16, v16
s_branch .LBB0_2
.LBB0_5:
v_cvt_f32_i32_e32 v4, v12
s_branch .LBB0_7
.LBB0_6:
v_mov_b32_e32 v4, 1.0
v_mov_b32_e32 v6, 0
.LBB0_7:
v_cvt_f64_f32_e32 v[9:10], v8
v_cvt_f64_f32_e32 v[11:12], v7
s_mov_b32 s3, 0x3eb0c6f7
s_mov_b32 s2, 0xa0b5ed8d
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[9:10]
v_cmp_lt_f64_e64 s2, s[2:3], v[11:12]
v_mov_b32_e32 v9, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_9
v_frexp_mant_f32_e64 v5, |v1|
s_mov_b32 s3, 0x3e76c4e1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
v_cndmask_b32_e64 v9, 0, 1, vcc_lo
v_ldexp_f32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, -1.0, v5
v_add_f32_e32 v9, 1.0, v5
v_rcp_f32_e32 v10, v9
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v14, v9, v12 :: v_dual_add_f32 v13, -1.0, v9
v_fma_f32 v9, v12, v9, -v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v5, v13
v_frexp_mant_f32_e64 v13, |v6|
v_fmac_f32_e32 v9, v12, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_f32_e64 s2, 0x3f2aaaab, v13
v_add_f32_e32 v15, v14, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v5, 0, 1, s2
v_sub_f32_e32 v14, v15, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_ldexp_f32 v5, v13, v5
v_sub_f32_e32 v13, v11, v15
v_sub_f32_e32 v9, v14, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v16, 1.0, v5
v_sub_f32_e32 v11, v11, v13
v_add_f32_e32 v14, -1.0, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v17, v16
v_sub_f32_e32 v11, v11, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, v9, v11
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v11, v14, v17
v_add_f32_e32 v9, v13, v9
v_add_f32_e32 v13, -1.0, v16
v_mul_f32_e32 v9, v10, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v5, v13
v_add_f32_e32 v13, v12, v9
v_mul_f32_e32 v15, v16, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, v11, v16, -v15
v_mul_f32_e32 v16, v13, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v10, v11, v5 :: v_dual_sub_f32 v5, v13, v12
v_fma_f32 v18, v13, v13, -v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v12, v15, v10 :: v_dual_sub_f32 v5, v9, v5
v_sub_f32_e32 v9, v14, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v19, v5, v5
v_dual_sub_f32 v15, v12, v15 :: v_dual_sub_f32 v14, v14, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v18, v13, v19
v_sub_f32_e32 v10, v15, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v12, v14, v12
v_add_f32_e32 v14, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v10, v10, v12
v_fmaak_f32 v12, s3, v14, 0x3e91f4c4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v9, v9, v10 :: v_dual_fmaak_f32 v10, v14, v12, 0x3ecccdef
v_dual_sub_f32 v12, v14, v16 :: v_dual_mul_f32 v21, v13, v14
v_mul_f32_e32 v9, v17, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v15, v14, v10
v_sub_f32_e32 v12, v18, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v16, v11, v9
v_fma_f32 v17, v14, v10, -v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v17, v12, v10
v_mul_f32_e32 v10, v16, v16
v_sub_f32_e32 v11, v16, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v18, v16, v16, -v10
v_sub_f32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v19, v9, v9
v_fmac_f32_e32 v18, v16, v19
v_fma_f32 v19, v14, v13, -v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v22, v10, v18
v_fmac_f32_e32 v19, v14, v5
v_ldexp_f32 v5, v5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmaak_f32 v14, s3, v22, 0x3e91f4c4 :: v_dual_fmac_f32 v19, v12, v13
v_sub_f32_e32 v10, v22, v10
v_fmaak_f32 v12, v22, v14, 0x3ecccdef
v_frexp_exp_i32_f32_e32 v14, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v10, v18, v10
v_mul_f32_e32 v23, v22, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
v_fma_f32 v18, v22, v12, -v23
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v14, v14
v_dual_fmac_f32 v18, v10, v12 :: v_dual_add_f32 v11, v15, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v15, v11, v15
v_add_f32_e32 v20, 0x3f2aaaaa, v11
v_sub_f32_e32 v15, v17, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v17, 0xbf2aaaaa, v20
v_add_f32_e32 v15, 0x31739010, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v11, v17
v_add_f32_e32 v17, v21, v19
v_add_f32_e32 v11, v15, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v21, v17, v21
v_dual_add_f32 v15, v20, v11 :: v_dual_sub_f32 v12, v19, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v20, v20, v15
v_dual_mul_f32 v24, v17, v15 :: v_dual_add_f32 v11, v11, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v20, v17, v15, -v24
v_dual_fmac_f32 v20, v17, v11 :: v_dual_add_f32 v11, v23, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v20, v12, v15
v_ldexp_f32 v12, v13, 1
v_mul_f32_e32 v13, v16, v22
v_sub_f32_e32 v15, v11, v23
v_add_f32_e32 v19, 0x3f2aaaaa, v11
v_add_f32_e32 v21, v24, v20
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v23, v22, v16, -v13
v_sub_f32_e32 v15, v18, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v18, 0xbf2aaaaa, v19 :: v_dual_add_f32 v25, v12, v21
v_dual_sub_f32 v24, v21, v24 :: v_dual_fmac_f32 v23, v22, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v15, 0x31739010, v15
v_dual_sub_f32 v11, v11, v18 :: v_dual_sub_f32 v12, v25, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v18, v20, v24
v_fmac_f32_e32 v23, v10, v16
v_ldexp_f32 v9, v9, 1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_add_f32 v10, v15, v11 :: v_dual_sub_f32 v11, v21, v12
v_add_f32_e32 v5, v5, v18
v_frexp_exp_i32_f32_e32 v21, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v12, v19, v10 :: v_dual_add_f32 v5, v5, v11
v_subrev_co_ci_u32_e64 v21, vcc_lo, 0, v21, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_f32_e32 v15, v19, v12
v_cmp_eq_f32_e32 vcc_lo, 1.0, v1
v_add_f32_e32 v19, v25, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v17, 0x3f317218, v14 :: v_dual_add_f32 v10, v10, v15
v_fma_f32 v20, v14, 0x3f317218, -v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v20, 0xb102e308, v14
v_add_f32_e32 v14, v13, v23
v_mul_f32_e32 v18, v14, v12
v_sub_f32_e32 v13, v14, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, v14, v12, -v18
v_sub_f32_e32 v13, v23, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v15, v14, v10 :: v_dual_sub_f32 v14, v19, v25
v_add_f32_e32 v11, v17, v20
v_cvt_f32_i32_e32 v10, v21
v_fmac_f32_e32 v15, v13, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_dual_sub_f32 v5, v5, v14 :: v_dual_add_f32 v22, v11, v19
v_sub_f32_e32 v17, v11, v17
v_ldexp_f32 v12, v16, 1
v_add_f32_e32 v14, v18, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v16, 0x3f317218, v10 :: v_dual_sub_f32 v23, v22, v11
v_dual_sub_f32 v17, v20, v17 :: v_dual_sub_f32 v18, v14, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v20, v22, v23
v_sub_f32_e32 v13, v19, v23
v_add_f32_e32 v19, v17, v5
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v15, v15, v18
v_fma_f32 v18, v10, 0x3f317218, -v16
v_sub_f32_e32 v11, v11, v20
v_dual_sub_f32 v20, v19, v17 :: v_dual_add_f32 v9, v9, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v18, 0xb102e308, v10 :: v_dual_add_f32 v11, v13, v11
v_add_f32_e32 v13, v12, v14
v_sub_f32_e32 v5, v5, v20
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v11, v19, v11 :: v_dual_sub_f32 v12, v13, v12
v_sub_f32_e32 v19, v19, v20
v_add_f32_e32 v21, v22, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v12, v14, v12
v_sub_f32_e32 v14, v17, v19
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v15, v21, v22
v_add_f32_e32 v9, v9, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v5, v5, v14 :: v_dual_sub_f32 v10, v11, v15
v_dual_add_f32 v11, v16, v18 :: v_dual_add_f32 v12, v13, v9
v_cndmask_b32_e64 v15, 2.0, 1.0, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v5, v5, v10 :: v_dual_sub_f32 v16, v11, v16
v_dual_add_f32 v10, v11, v12 :: v_dual_sub_f32 v13, v12, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v14, v21, v5
v_sub_f32_e32 v16, v18, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v17, v10, v11
v_sub_f32_e32 v9, v9, v13
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_sub_f32 v19, v14, v21 :: v_dual_mul_f32 v20, v15, v14
v_sub_f32_e32 v18, v10, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_sub_f32 v12, v12, v17 :: v_dual_sub_f32 v5, v5, v19
v_fma_f32 v14, v15, v14, -v20
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v11, v11, v18
v_cmp_class_f32_e64 vcc_lo, v20, 0x204
v_dual_fmac_f32 v14, v15, v5 :: v_dual_add_f32 v11, v12, v11
v_add_f32_e32 v5, v16, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v12, v20, v14 :: v_dual_sub_f32 v13, v5, v16
v_add_f32_e32 v11, v5, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v17, v12, v20, vcc_lo
v_dual_sub_f32 v12, v12, v20 :: v_dual_sub_f32 v5, v5, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v18, v10, v11 :: v_dual_sub_f32 v9, v9, v13
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v17
v_cmp_neq_f32_e64 s2, 0x7f800000, |v17|
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_dual_sub_f32 v5, v16, v5 :: v_dual_sub_f32 v10, v18, v10
v_mul_f32_e32 v20, 0.5, v15
v_cndmask_b32_e64 v19, 0, 0x37000000, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 1.0, v6
v_add_f32_e32 v5, v9, v5
v_sub_f32_e32 v9, v11, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v13, v17, v19
v_cndmask_b32_e64 v21, 2.0, 1.0, vcc_lo
v_add_f32_e32 v5, v5, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v10, 0x3fb8aa3b, v13
v_add_f32_e32 v16, v18, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v9, v13, 0x3fb8aa3b, -v10
v_rndne_f32_e32 v11, v10
v_dual_sub_f32 v18, v16, v18 :: v_dual_fmac_f32 v9, 0x32a5705f, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v10, v10, v11
v_cvt_i32_f32_e32 v11, v11
v_sub_f32_e32 v5, v5, v18
v_trunc_f32_e32 v18, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v9, v10, v9 :: v_dual_mul_f32 v10, v21, v16
v_cmp_eq_f32_e32 vcc_lo, v18, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_exp_f32_e32 v9, v9
v_fma_f32 v16, v21, v16, -v10
s_delay_alu instid0(VALU_DEP_1)
v_dual_fmac_f32 v16, v21, v5 :: v_dual_sub_f32 v5, v14, v12
v_trunc_f32_e32 v12, v20
s_waitcnt_depctr 0xfff
v_ldexp_f32 v9, v9, v11
v_add_f32_e32 v11, v10, v16
v_cndmask_b32_e64 v5, 0, v5, s2
v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v19, v5
v_cndmask_b32_e64 v9, 0, v9, s2
v_cmp_class_f32_e64 s2, v10, 0x204
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v14, v11, v10, s2
v_cmp_nlt_f32_e64 s2, 0x42b17218, v13
v_sub_f32_e32 v10, v11, v10
v_cmp_eq_f32_e64 s3, 0x42b17218, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v9, 0x7f800000, v9, s2
v_cmp_neq_f32_e64 s2, v12, v20
v_sub_f32_e32 v10, v16, v10
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v12, 0, 0x37000000, s3
v_fma_f32 v5, v9, v5, v9
v_cmp_eq_f32_e64 s3, 0x7f800000, v9
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v13, 1.0, v1, s2
v_sub_f32_e32 v15, v14, v12
v_cndmask_b32_e64 v5, v5, v9, s3
v_cmp_eq_f32_e64 s3, 0, v1
v_cndmask_b32_e64 v17, 0, v1, s2
v_cmp_class_f32_e64 s2, v1, 0x204
v_mul_f32_e32 v9, 0x3fb8aa3b, v15
v_bfi_b32 v5, 0x7fffffff, v5, v13
v_cndmask_b32_e64 v13, 0x7f800000, 0, s3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v19, v15, 0x3fb8aa3b, -v9
v_cndmask_b32_e32 v18, 0x7fc00000, v5, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v1
v_rndne_f32_e32 v20, v9
v_bfi_b32 v13, 0x7fffffff, v13, v17
v_fmac_f32_e32 v19, 0x32a5705f, v15
v_cndmask_b32_e32 v5, v5, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_4)
v_sub_f32_e32 v9, v9, v20
s_or_b32 vcc_lo, s3, s2
v_cvt_i32_f32_e32 v17, v20
v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v15
v_cndmask_b32_e32 v5, v5, v13, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v1, v1
v_add_f32_e32 v9, v9, v19
v_mul_f32_e32 v13, 0.5, v21
v_cmp_nlt_f32_e64 s3, 0x42b17218, v15
v_trunc_f32_e32 v18, v21
v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
v_exp_f32_e32 v9, v9
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v14|
v_trunc_f32_e32 v19, v13
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_scale_f32 v11, null, v8, v8, v5
v_cndmask_b32_e32 v10, 0, v10, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, v18, v21
v_rcp_f32_e32 v16, v11
s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f32 v9, v9, v17
v_add_f32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v9, 0, v9, s2
v_cmp_neq_f32_e64 s2, v19, v13
s_waitcnt_depctr 0xfff
v_fma_f32 v12, -v11, v16, 1.0
v_cndmask_b32_e64 v9, 0x7f800000, v9, s3
v_div_scale_f32 v13, s3, v5, v8, v5
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v16, v12, v16
v_fma_f32 v10, v9, v10, v9
v_cmp_eq_f32_e64 s4, 0x7f800000, v9
v_cndmask_b32_e64 v12, 1.0, v6, s2
v_cndmask_b32_e64 v15, 0, v6, s2
v_mul_f32_e32 v14, v13, v16
v_cmp_class_f32_e64 s2, v6, 0x204
v_cndmask_b32_e64 v9, v10, v9, s4
v_cmp_eq_f32_e64 s4, 0, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v10, -v11, v14, v13
v_bfi_b32 v9, 0x7fffffff, v9, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v12, 0x7f800000, 0, s4
v_fmac_f32_e32 v14, v10, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v10, 0x7fc00000, v9, vcc_lo
v_cmp_gt_f32_e32 vcc_lo, 0, v6
v_bfi_b32 v12, 0x7fffffff, v12, v15
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v11, -v11, v14, v13
v_cndmask_b32_e32 v9, v9, v10, vcc_lo
s_mov_b32 vcc_lo, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v10, v11, v16, v14
s_or_b32 vcc_lo, s4, s2
v_cndmask_b32_e32 v9, v9, v12, vcc_lo
v_cmp_o_f32_e32 vcc_lo, v6, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f32 v5, v10, v8, v5
v_cndmask_b32_e32 v8, 0x7fc00000, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_div_scale_f32 v9, null, v4, v4, v5
v_div_scale_f32 v15, vcc_lo, v5, v4, v5
v_div_scale_f32 v10, null, v7, v7, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v11, v9
v_rcp_f32_e32 v12, v10
s_waitcnt_depctr 0xfff
v_fma_f32 v13, -v9, v11, 1.0
v_fma_f32 v14, -v10, v12, 1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v11, v13, v11
v_div_scale_f32 v13, s2, v8, v7, v8
v_fmac_f32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v14, v15, v11
v_mul_f32_e32 v16, v13, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v17, -v9, v14, v15
v_fma_f32 v18, -v10, v16, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v14, v17, v11
v_fmac_f32_e32 v16, v18, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v9, v14, v15
v_fma_f32 v10, -v10, v16, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v9, v9, v11, v14
s_mov_b32 vcc_lo, s2
v_div_fmas_f32 v10, v10, v12, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v5, v9, v4, v5
v_div_fixup_f32 v7, v10, v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, 0, v5
v_div_scale_f32 v8, null, v4, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v8, v10, 1.0
v_fmac_f32_e32 v10, v11, v10
v_div_scale_f32 v11, vcc_lo, v7, v4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v12, v11, v10
v_fma_f32 v13, -v8, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v13, v10
v_fma_f32 v8, -v8, v12, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v8, v8, v10, v12
v_div_fixup_f32 v4, v8, v4, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, 0, v4
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s5
v_mul_f32_e32 v1, v1, v1
v_mul_f32_e32 v4, v9, v9
s_load_b64 s[4:5], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v1, v6, v6
v_mul_f32_e32 v6, 0x4f800000, v1
v_cmp_gt_f32_e64 s2, 0xf800000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v6, v1, v6, s2
v_sqrt_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_dual_fmac_f32 v4, v5, v5 :: v_dual_add_nc_u32 v11, -1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v5, 0x4f800000, v4
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
v_dual_cndmask_b32 v7, v4, v5 :: v_dual_add_nc_u32 v12, 1, v8
v_mad_u64_u32 v[4:5], null, v2, s17, v[3:4]
v_fma_f32 v2, -v11, v8, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fma_f32 v5, -v12, v8, v6
v_sqrt_f32_e32 v1, v7
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v9, -1, v1
v_add_nc_u32_e32 v10, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v13, -v9, v1, v7
v_fma_f32 v3, -v10, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_ge_f32_e64 s3, 0, v13
v_cmp_lt_f32_e64 s0, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v1, v1, v9, s3
v_cmp_ge_f32_e64 s3, 0, v2
v_cndmask_b32_e64 v3, v1, v10, s0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v8, v11, s3
v_cmp_lt_f32_e64 s0, 0, v5
v_cndmask_b32_e64 v5, v2, v12, s0
v_mad_u64_u32 v[1:2], null, v4, s16, v[0:1]
v_mul_f32_e32 v0, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, v3, v0, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v7, 0x260
v_cndmask_b32_e32 v4, v0, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v6, 0x260
v_mul_f32_e32 v2, 0x37800000, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v3, v5, v2, s2
v_ashrrev_i32_e32 v2, 31, v1
v_cndmask_b32_e32 v3, v3, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mul_f32_e32 v2, v3, v4
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 344
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 26
.amdhsa_next_free_sgpr 28
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, .Lfunc_end0-_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 60
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: by_value
- .offset: 68
.size: 4
.value_kind: by_value
- .offset: 72
.size: 4
.value_kind: by_value
- .offset: 76
.size: 4
.value_kind: by_value
- .offset: 80
.size: 4
.value_kind: by_value
- .offset: 88
.size: 4
.value_kind: hidden_block_count_x
- .offset: 92
.size: 4
.value_kind: hidden_block_count_y
- .offset: 96
.size: 4
.value_kind: hidden_block_count_z
- .offset: 100
.size: 2
.value_kind: hidden_group_size_x
- .offset: 102
.size: 2
.value_kind: hidden_group_size_y
- .offset: 104
.size: 2
.value_kind: hidden_group_size_z
- .offset: 106
.size: 2
.value_kind: hidden_remainder_x
- .offset: 108
.size: 2
.value_kind: hidden_remainder_y
- .offset: 110
.size: 2
.value_kind: hidden_remainder_z
- .offset: 128
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 136
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 144
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 152
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 344
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.private_segment_fixed_size: 0
.sgpr_count: 30
.sgpr_spill_count: 0
.symbol: _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 26
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
/*__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz, float* p_xyt_real, float* p_xyt_imag,
float* sensor_pos, float* origin, float* laser_pos, float dx, float dz, int NX, int NY, int NZ,
float c_dt, int N_pos, int Nt, float ReceiveDelay)
{
int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
float tao = 0.0;
float voxel_int_real = 0.0, voxel_int_imag =0.0;
float voxel_real = 0.0, voxel_imag =0.0;
int Index = 0, counter = 1;
float GPS_x = origin[0] - (nx-NX/2)*dx; // x-coordiante for the voxel
float GPS_y = origin[1] + (ny-NY/2)*dx; // y-coordiante for the voxel
float GPS_z = origin[2] + (nz)*dz; // z-coordiante for the voxel
// time delay from the laser spot to the voxel
float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
float x_pos,y_pos,z_pos, cos_theta;
float voxel_int_real_tp[NPOINT], voxel_int_imag_tp[NPOINT], voxel_sq_real_tp[NPOINT], voxel_sq_imag_tp[NPOINT];
for(int K = 0; K<NPOINT; K++)
{
voxel_int_real_tp[K] = 0.0;
voxel_int_imag_tp[K] = 0.0;
voxel_sq_real_tp[K] = 0.0;
voxel_sq_imag_tp[K] = 0.0;
}
for(int K_x = 0;K_x<N_pos; K_x++)
{
x_pos = sensor_pos[K_x];
y_pos = sensor_pos[K_x+N_pos];
z_pos = sensor_pos[K_x+2*N_pos];
tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
cos_theta = GPS_z/(tao + 1e-6);
Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
if((Index<Nt-NPOINT*STRIDE) && (Index>0))
{
for(int P = 0; P<NPOINT; P++)
{
voxel_real = p_xyt_real[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
voxel_imag = p_xyt_imag[Index+K_x*(Nt)+P*STRIDE] * cos_theta;
voxel_int_real_tp[P] = voxel_int_real_tp[P] + voxel_real; //* sqrt(Index*1.0);
voxel_int_imag_tp[P] = voxel_int_imag_tp[P] + voxel_imag; //* sqrt(Index*1.0);
voxel_sq_real_tp[P] = voxel_sq_real_tp[P] + voxel_real * voxel_real;
voxel_sq_imag_tp[P] = voxel_sq_imag_tp[P] + voxel_imag * voxel_imag;
}
counter = counter+1;
}
}
voxel_int_real = voxel_int_real_tp[0];
voxel_int_imag = voxel_int_imag_tp[0];
for (int J=0;J<NPOINT;J++)
{
if((voxel_sq_real_tp[J]>1e-6) && (voxel_sq_imag_tp[J]>1e-6))
{
CF_real = CF_real + powf(voxel_int_real_tp[J],2)/voxel_sq_real_tp[J]/counter;
CF_imag = CF_imag + powf(voxel_int_imag_tp[J],2)/voxel_sq_imag_tp[J]/counter;
}
}
CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real + voxel_int_imag * voxel_int_imag ) * (CF);
}*/
// ****
// Implement the phasor method using complex data rather than two times reconstruction
// ****
#define NPOINT 1
#define STRIDE 1
__global__ void ThreeD_NLOS_Phasor_General( float* p_xyz, float* p_xyt_real, float* p_xyt_imag,
float* sensor_pos, float* origin, float* laser_pos, float dx, float dz, int NX, int NY, int NZ,
float c_dt, int N_pos, int Nt, float ReceiveDelay)
{
int nz = blockIdx.z * blockDim.z + threadIdx.z; // the nz-column, which is the time direction
int ny = blockIdx.y * blockDim.y + threadIdx.y; // the ny-col
int nx = blockIdx.x * blockDim.x + threadIdx.x; // the nx-row
float CF_real = 0.0, CF_imag = 0.0, CF = 0.0;
float tao = 0.0;
float voxel_int_real = 0.0, voxel_int_imag =0.0;
float voxel_real = 0.0, voxel_imag =0.0;
int Index = 0, counter = 1;
float GPS_x = origin[0] - (nx-NX/2)*dx; // x-coordiante for the voxel
float GPS_y = origin[1] + (ny-NY/2)*dx; // y-coordiante for the voxel
float GPS_z = origin[2] + (nz)*dz; // z-coordiante for the voxel
// time delay from the laser spot to the voxel
float tao_trans = sqrtf( (laser_pos[0]-GPS_x)*(laser_pos[0]-GPS_x) + (laser_pos[1]-GPS_y)*(laser_pos[1]-GPS_y) + (laser_pos[2]-GPS_z)*(laser_pos[2]-GPS_z) );
float x_pos,y_pos,z_pos, cos_theta;
float voxel_sq_real, voxel_sq_imag;
for(int K_x = 0;K_x<N_pos; K_x++)
{
x_pos = sensor_pos[K_x];
y_pos = sensor_pos[K_x+N_pos];
z_pos = sensor_pos[K_x+2*N_pos];
tao = sqrtf( (x_pos-GPS_x) * (x_pos-GPS_x) + (y_pos-GPS_y)*(y_pos-GPS_y) + (z_pos-GPS_z)*(z_pos-GPS_z) );
cos_theta = GPS_z/(tao + 1e-6);
Index = int( floorf((tao + tao_trans)/c_dt-ReceiveDelay) );
if((Index<Nt) && (Index>0))
{
voxel_real = p_xyt_real[Index+K_x*(Nt)] * cos_theta;
voxel_imag = p_xyt_imag[Index+K_x*(Nt)] * cos_theta;
voxel_int_real = voxel_int_real + voxel_real; //* sqrt(Index*1.0);
voxel_int_imag = voxel_int_imag + voxel_imag; //* sqrt(Index*1.0);
voxel_sq_real = voxel_sq_real + voxel_real * voxel_real;
voxel_sq_imag = voxel_sq_imag + voxel_imag * voxel_imag;
counter = counter+1;
}
}
if((voxel_sq_real>1e-6) && (voxel_sq_imag>1e-6))
{
CF_real = CF_real + powf(voxel_int_real,2)/voxel_sq_real/counter;
CF_imag = CF_imag + powf(voxel_int_imag,2)/voxel_sq_imag/counter;
}
CF = sqrtf( CF_real*CF_real + CF_imag*CF_imag );
p_xyz[nx+NX*ny+nz*(NX*NY)] = sqrtf( voxel_int_real * voxel_int_real + voxel_int_imag * voxel_int_imag ) * (CF);
} | .text
.file "PhasorField.hip"
.globl _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif # -- Begin function _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.p2align 4, 0x90
.type _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif,@function
_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif: # @_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movss %xmm3, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, .Lfunc_end0-_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif,@object # @_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.section .rodata,"a",@progbits
.globl _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.p2align 3, 0x0
_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif:
.quad _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.size _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018d1be_00000000-6_PhasorField.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif
.type _Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif, @function
_Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif:
.LFB2051:
.cfi_startproc
endbr64
subq $264, %rsp
.cfi_def_cfa_offset 272
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movq %r9, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movss %xmm3, (%rsp)
movq %fs:40, %rax
movq %rax, 248(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 272(%rsp), %rax
movq %rax, 192(%rsp)
leaq 280(%rsp), %rax
movq %rax, 200(%rsp)
leaq 288(%rsp), %rax
movq %rax, 208(%rsp)
leaq 4(%rsp), %rax
movq %rax, 216(%rsp)
leaq 296(%rsp), %rax
movq %rax, 224(%rsp)
leaq 304(%rsp), %rax
movq %rax, 232(%rsp)
movq %rsp, %rax
movq %rax, 240(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 248(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 280
pushq 72(%rsp)
.cfi_def_cfa_offset 288
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 272
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif, .-_Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif
.globl _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.type _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, @function
_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 56
movl 56(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 64
call _Z65__device_stub__Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiifPfS_S_S_S_S_ffiiifiif
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, .-_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "PhasorField.hip"
.globl _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif # -- Begin function _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.p2align 4, 0x90
.type _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif,@function
_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif: # @_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.cfi_startproc
# %bb.0:
subq $232, %rsp
.cfi_def_cfa_offset 240
movq %rdi, 104(%rsp)
movq %rsi, 96(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movss %xmm3, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 80(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
leaq 256(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
leaq 264(%rsp), %rax
movq %rax, 208(%rsp)
leaq 272(%rsp), %rax
movq %rax, 216(%rsp)
movq %rsp, %rax
movq %rax, 224(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $248, %rsp
.cfi_adjust_cfa_offset -248
retq
.Lfunc_end0:
.size _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, .Lfunc_end0-_Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif,@object # @_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.section .rodata,"a",@progbits
.globl _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.p2align 3, 0x0
_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif:
.quad _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.size _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif"
.size .L__unnamed_1, 52
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26ThreeD_NLOS_Phasor_GeneralPfS_S_S_S_S_ffiiifiif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void
mat_hadamard(float *a, float *b, float *c, int rows, int columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < rows && j < columns)
{
int k = i * columns + j;
c[k] = a[k] * b[k];
}
} | code for sm_80
Function : _Z12mat_hadamardPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void
mat_hadamard(float *a, float *b, float *c, int rows, int columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < rows && j < columns)
{
int k = i * columns + j;
c[k] = a[k] * b[k];
}
} | .file "tmpxft_001aebef_00000000-6_mat_hadamard.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii
.type _Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii, @function
_Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12mat_hadamardPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii, .-_Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii
.globl _Z12mat_hadamardPfS_S_ii
.type _Z12mat_hadamardPfS_S_ii, @function
_Z12mat_hadamardPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12mat_hadamardPfS_S_ii, .-_Z12mat_hadamardPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mat_hadamardPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mat_hadamardPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void
mat_hadamard(float *a, float *b, float *c, int rows, int columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < rows && j < columns)
{
int k = i * columns + j;
c[k] = a[k] * b[k];
}
} | #include <hip/hip_runtime.h>
__global__ void
mat_hadamard(float *a, float *b, float *c, int rows, int columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < rows && j < columns)
{
int k = i * columns + j;
c[k] = a[k] * b[k];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void
mat_hadamard(float *a, float *b, float *c, int rows, int columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < rows && j < columns)
{
int k = i * columns + j;
c[k] = a[k] * b[k];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mat_hadamardPfS_S_ii
.globl _Z12mat_hadamardPfS_S_ii
.p2align 8
.type _Z12mat_hadamardPfS_S_ii,@function
_Z12mat_hadamardPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mat_hadamardPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mat_hadamardPfS_S_ii, .Lfunc_end0-_Z12mat_hadamardPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mat_hadamardPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mat_hadamardPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void
mat_hadamard(float *a, float *b, float *c, int rows, int columns)
{
const int i = blockDim.y * blockIdx.y + threadIdx.y,
j = blockDim.x * blockIdx.x + threadIdx.x;
if (i < rows && j < columns)
{
int k = i * columns + j;
c[k] = a[k] * b[k];
}
} | .text
.file "mat_hadamard.hip"
.globl _Z27__device_stub__mat_hadamardPfS_S_ii # -- Begin function _Z27__device_stub__mat_hadamardPfS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__mat_hadamardPfS_S_ii,@function
_Z27__device_stub__mat_hadamardPfS_S_ii: # @_Z27__device_stub__mat_hadamardPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12mat_hadamardPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__mat_hadamardPfS_S_ii, .Lfunc_end0-_Z27__device_stub__mat_hadamardPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mat_hadamardPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mat_hadamardPfS_S_ii,@object # @_Z12mat_hadamardPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z12mat_hadamardPfS_S_ii
.p2align 3, 0x0
_Z12mat_hadamardPfS_S_ii:
.quad _Z27__device_stub__mat_hadamardPfS_S_ii
.size _Z12mat_hadamardPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mat_hadamardPfS_S_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mat_hadamardPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mat_hadamardPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12mat_hadamardPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x17c], PT ; /* 0x00005f0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FMUL R9, R4, R3 ; /* 0x0000000304097220 */
/* 0x004fca0000400000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12mat_hadamardPfS_S_ii
.globl _Z12mat_hadamardPfS_S_ii
.p2align 8
.type _Z12mat_hadamardPfS_S_ii,@function
_Z12mat_hadamardPfS_S_ii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s4, 16
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12mat_hadamardPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12mat_hadamardPfS_S_ii, .Lfunc_end0-_Z12mat_hadamardPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12mat_hadamardPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12mat_hadamardPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aebef_00000000-6_mat_hadamard.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii
.type _Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii, @function
_Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12mat_hadamardPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii, .-_Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii
.globl _Z12mat_hadamardPfS_S_ii
.type _Z12mat_hadamardPfS_S_ii, @function
_Z12mat_hadamardPfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z12mat_hadamardPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12mat_hadamardPfS_S_ii, .-_Z12mat_hadamardPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mat_hadamardPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mat_hadamardPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_hadamard.hip"
.globl _Z27__device_stub__mat_hadamardPfS_S_ii # -- Begin function _Z27__device_stub__mat_hadamardPfS_S_ii
.p2align 4, 0x90
.type _Z27__device_stub__mat_hadamardPfS_S_ii,@function
_Z27__device_stub__mat_hadamardPfS_S_ii: # @_Z27__device_stub__mat_hadamardPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12mat_hadamardPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z27__device_stub__mat_hadamardPfS_S_ii, .Lfunc_end0-_Z27__device_stub__mat_hadamardPfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mat_hadamardPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mat_hadamardPfS_S_ii,@object # @_Z12mat_hadamardPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z12mat_hadamardPfS_S_ii
.p2align 3, 0x0
_Z12mat_hadamardPfS_S_ii:
.quad _Z27__device_stub__mat_hadamardPfS_S_ii
.size _Z12mat_hadamardPfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mat_hadamardPfS_S_ii"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mat_hadamardPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mat_hadamardPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <cuda.h>
//#include <cuda_runtime_api.h>
#include <cuda_runtime.h>
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
void add_vector_gpu( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
cudaMalloc( (void**)&dev_A, data_size );
cudaMalloc( (void**)&dev_B, data_size );
cudaMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
cudaMemcpy( dev_A, a, data_size, cudaMemcpyHostToDevice );
cudaMemcpy( dev_B, b, data_size, cudaMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
cudaMemcpy( c, dev_C, data_size, cudaMemcpyDeviceToHost );
// part5, release data
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
} | code for sm_80
Function : _Z9VectorAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <cuda.h>
//#include <cuda_runtime_api.h>
#include <cuda_runtime.h>
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
void add_vector_gpu( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
cudaMalloc( (void**)&dev_A, data_size );
cudaMalloc( (void**)&dev_B, data_size );
cudaMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
cudaMemcpy( dev_A, a, data_size, cudaMemcpyHostToDevice );
cudaMemcpy( dev_B, b, data_size, cudaMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
cudaMemcpy( c, dev_C, data_size, cudaMemcpyDeviceToHost );
// part5, release data
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
} | .file "tmpxft_0006a992_00000000-6_test1_cu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
.type _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_, @function
_Z32__device_stub__Z9VectorAddPfS_S_PfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_, .-_Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
.globl _Z9VectorAddPfS_S_
.type _Z9VectorAddPfS_S_, @function
_Z9VectorAddPfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z9VectorAddPfS_S_, .-_Z9VectorAddPfS_S_
.globl add_vector_gpu
.type add_vector_gpu, @function
add_vector_gpu:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size add_vector_gpu, .-add_vector_gpu
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9VectorAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <cuda.h>
//#include <cuda_runtime_api.h>
#include <cuda_runtime.h>
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
void add_vector_gpu( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
cudaMalloc( (void**)&dev_A, data_size );
cudaMalloc( (void**)&dev_B, data_size );
cudaMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
cudaMemcpy( dev_A, a, data_size, cudaMemcpyHostToDevice );
cudaMemcpy( dev_B, b, data_size, cudaMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
cudaMemcpy( c, dev_C, data_size, cudaMemcpyDeviceToHost );
// part5, release data
cudaFree(dev_A);
cudaFree(dev_B);
cudaFree(dev_C);
} | #include <stdlib.h>
#include <hip/hip_runtime.h>
//#include <cuda_runtime_api.h>
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
void add_vector_gpu( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
hipMalloc( (void**)&dev_A, data_size );
hipMalloc( (void**)&dev_B, data_size );
hipMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
hipMemcpy( dev_A, a, data_size, hipMemcpyHostToDevice );
hipMemcpy( dev_B, b, data_size, hipMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
hipMemcpy( c, dev_C, data_size, hipMemcpyDeviceToHost );
// part5, release data
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdlib.h>
#include <hip/hip_runtime.h>
//#include <cuda_runtime_api.h>
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
void add_vector_gpu( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
hipMalloc( (void**)&dev_A, data_size );
hipMalloc( (void**)&dev_B, data_size );
hipMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
hipMemcpy( dev_A, a, data_size, hipMemcpyHostToDevice );
hipMemcpy( dev_B, b, data_size, hipMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
hipMemcpy( c, dev_C, data_size, hipMemcpyDeviceToHost );
// part5, release data
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPfS_S_
.globl _Z9VectorAddPfS_S_
.p2align 8
.type _Z9VectorAddPfS_S_,@function
_Z9VectorAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPfS_S_, .Lfunc_end0-_Z9VectorAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdlib.h>
#include <hip/hip_runtime.h>
//#include <cuda_runtime_api.h>
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
__global__ void VectorAdd( float* arrayA, float* arrayB, float* output )
{
int idx = threadIdx.x;
output[idx] = arrayA[idx] + arrayB[idx];
}
extern "C" void add_vector_gpu( float* a, float* b, float *c, int size );
void add_vector_gpu( float* a, float* b, float *c, int size )
{
int data_size = size * sizeof(float);
// part1, allocate data on device
float *dev_A, *dev_B, *dev_C;
hipMalloc( (void**)&dev_A, data_size );
hipMalloc( (void**)&dev_B, data_size );
hipMalloc( (void**)&dev_C, data_size );
// part2, copy memory to device
hipMemcpy( dev_A, a, data_size, hipMemcpyHostToDevice );
hipMemcpy( dev_B, b, data_size, hipMemcpyHostToDevice );
// part3, run kernel
VectorAdd<<< 1, size >>>( dev_A, dev_B, dev_C );
// part4, copy data from device
hipMemcpy( c, dev_C, data_size, hipMemcpyDeviceToHost );
// part5, release data
hipFree(dev_A);
hipFree(dev_B);
hipFree(dev_C);
} | .text
.file "test1_cu.hip"
.globl _Z24__device_stub__VectorAddPfS_S_ # -- Begin function _Z24__device_stub__VectorAddPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPfS_S_,@function
_Z24__device_stub__VectorAddPfS_S_: # @_Z24__device_stub__VectorAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPfS_S_, .Lfunc_end0-_Z24__device_stub__VectorAddPfS_S_
.cfi_endproc
# -- End function
.globl add_vector_gpu # -- Begin function add_vector_gpu
.p2align 4, 0x90
.type add_vector_gpu,@function
add_vector_gpu: # @add_vector_gpu
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9VectorAddPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size add_vector_gpu, .Lfunc_end1-add_vector_gpu
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPfS_S_,@object # @_Z9VectorAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z9VectorAddPfS_S_
.p2align 3, 0x0
_Z9VectorAddPfS_S_:
.quad _Z24__device_stub__VectorAddPfS_S_
.size _Z9VectorAddPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9VectorAddPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9VectorAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9VectorAddPfS_S_
.globl _Z9VectorAddPfS_S_
.p2align 8
.type _Z9VectorAddPfS_S_,@function
_Z9VectorAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9VectorAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9VectorAddPfS_S_, .Lfunc_end0-_Z9VectorAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9VectorAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z9VectorAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006a992_00000000-6_test1_cu.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
.type _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_, @function
_Z32__device_stub__Z9VectorAddPfS_S_PfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9VectorAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_, .-_Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
.globl _Z9VectorAddPfS_S_
.type _Z9VectorAddPfS_S_, @function
_Z9VectorAddPfS_S_:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z9VectorAddPfS_S_, .-_Z9VectorAddPfS_S_
.globl add_vector_gpu
.type add_vector_gpu, @function
add_vector_gpu:
.LFB2027:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl %ecx, %ebp
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leal 0(,%rcx,4), %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z9VectorAddPfS_S_PfS_S_
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size add_vector_gpu, .-add_vector_gpu
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9VectorAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9VectorAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test1_cu.hip"
.globl _Z24__device_stub__VectorAddPfS_S_ # -- Begin function _Z24__device_stub__VectorAddPfS_S_
.p2align 4, 0x90
.type _Z24__device_stub__VectorAddPfS_S_,@function
_Z24__device_stub__VectorAddPfS_S_: # @_Z24__device_stub__VectorAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9VectorAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z24__device_stub__VectorAddPfS_S_, .Lfunc_end0-_Z24__device_stub__VectorAddPfS_S_
.cfi_endproc
# -- End function
.globl add_vector_gpu # -- Begin function add_vector_gpu
.p2align 4, 0x90
.type add_vector_gpu,@function
add_vector_gpu: # @add_vector_gpu
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $128, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %rbx
movq %rsi, %r12
movq %rdi, %r13
leal (,%r15,4), %eax
movslq %eax, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r14, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movq %r13, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9VectorAddPfS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq (%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
addq $128, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size add_vector_gpu, .Lfunc_end1-add_vector_gpu
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9VectorAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9VectorAddPfS_S_,@object # @_Z9VectorAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z9VectorAddPfS_S_
.p2align 3, 0x0
_Z9VectorAddPfS_S_:
.quad _Z24__device_stub__VectorAddPfS_S_
.size _Z9VectorAddPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9VectorAddPfS_S_"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__VectorAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9VectorAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <cmath>
#include <iomanip>
#include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
using namespace std;
#define ROOT 0
__device__ double eval_func1(double);
__global__ void calc_chunk(double, double*, int);
int main(int argc, char* argv[]){
double integral = 0.0;
int n, numBlocks, numThreads; // n = number of points, numBlocks = blocks on the device, numThreads = threads per block
double step; // step size when computing the integral; as n increases, step decreases and the integral's precision increases
int parts; // number of parts of the integral to compute for each thread
double* deviceGlobalSum;
cout<<"Enter number of points: ";
cin >> n;
cout<<"Enter number of blocks (up to 28): "; // GTX1080 on Pitt's CRC only allows up to 28 processors
cin >> numBlocks;
cout<<"Enter number of threads per block (up to 1024): "; // GTX1080 on Pitt's CRC only allows up to 1024 threads/block
cin >> numThreads;
if(n % (numBlocks*numThreads) != 0){ // can't split n up evenly by the number of threads
cout<<"N is not evenly divisible by # of Blocks! Exiting..."<<endl;
return 1;
} else if(numBlocks > 28 || numThreads > 1024){
cout<<"Too many requested blocks or threads! Exiting..."<<endl;
return 1;
}
step = 1.0 / (double) n; // step value of the integral, this is delta x for the trapezoidal rule
parts = (n / numBlocks) / numThreads; // number of parts per thread
// begin the timer for the multi-threaded portion of the code
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
// copy the global sum, or future integral value, from the host to the device
cudaMalloc((void**) &deviceGlobalSum, sizeof(double));
cudaMemcpy(deviceGlobalSum, &integral, sizeof(double), cudaMemcpyHostToDevice);
// call a function with specified number of blocks (i.e. address spaces, similar to processors) and number of threads (i.e. threads for each block)
calc_chunk<<<numBlocks, numThreads>>>(step, deviceGlobalSum, parts);
// barrier for all devices to complete
cudaDeviceSynchronize();
// copy the global sum of the device to the integral variable on the host
cudaMemcpy(&integral, deviceGlobalSum, sizeof(double), cudaMemcpyDeviceToHost);
// compute the total computation time
cudaEventRecord(end);
float timeDiff;
cudaEventElapsedTime(&timeDiff, start, end);
cudaEventSynchronize(end);
cudaEventDestroy(start);
cudaEventDestroy(end);
// free memory malloc'd on the device
cudaFree(deviceGlobalSum);
// print out the time and integral value
cout<<setprecision(9)<<"Final value of the integral is "<<integral<<"!"<<endl;
cout<<setprecision(9)<<"Execution time: "<<timeDiff<<endl;
return 0;
}
// Integral function we want to evaluate; increases modularity of the program
__device__ double eval_func1(double x){
return 4.0 / (1.0 + pow(x, 2));
}
// Calculate the chunk of the integral assigned to each thread (which belongs to a block)
__global__ void calc_chunk(double step, double* globalSum, int parts){
__shared__ double blockSum; // sum of all the parts in this block's chunk
if(threadIdx.x == 0) blockSum = 0.0; // let thread 0 initilize the shared variable since you can't declare and initialize on the same line
__syncthreads(); // barrier so no thread writes to the shared variable before it's initialized
int chunkNum = blockIdx.x * blockDim.x + threadIdx.x; // the chunk of the integral this thread is working on
double threadSum = 0.0;
double x = chunkNum * step * parts; // current x value we're evaluating the 'part' of the 'chunk' at
for(int i = 0; i < parts; i++){
double leftVal = eval_func1(x); // f(x_{i-1})
double rightVal = eval_func1(x + step); // f(x_{i})
threadSum += ((leftVal + rightVal)/2.0) * step; // trapezoidal rule
x += step;
}
atomicAdd(&blockSum, threadSum); // all thread write to the shared variable of the block
__syncthreads();
if(threadIdx.x == ROOT){
atomicAdd(globalSum, blockSum); // all blocks write to the 'shared' variable, global sum, of the device
}
} | .file "tmpxft_0015b2b9_00000000-6_integration.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10eval_func1d
.type _Z10eval_func1d, @function
_Z10eval_func1d:
.LFB3950:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3950:
.size _Z10eval_func1d, .-_Z10eval_func1d
.globl _Z32__device_stub__Z10calc_chunkdPdidPdi
.type _Z32__device_stub__Z10calc_chunkdPdidPdi, @function
_Z32__device_stub__Z10calc_chunkdPdidPdi:
.LFB3975:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movsd %xmm0, 24(%rsp)
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10calc_chunkdPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z32__device_stub__Z10calc_chunkdPdidPdi, .-_Z32__device_stub__Z10calc_chunkdPdidPdi
.globl _Z10calc_chunkdPdi
.type _Z10calc_chunkdPdi, @function
_Z10calc_chunkdPdi:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10calc_chunkdPdidPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z10calc_chunkdPdi, .-_Z10calc_chunkdPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Enter number of points: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Enter number of blocks (up to 28): "
.align 8
.LC3:
.string "Enter number of threads per block (up to 1024): "
.align 8
.LC4:
.string "N is not evenly divisible by # of Blocks! Exiting..."
.align 8
.LC5:
.string "Too many requested blocks or threads! Exiting..."
.align 8
.LC7:
.string "Final value of the integral is "
.section .rodata.str1.1
.LC8:
.string "!"
.LC9:
.string "Execution time: "
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0x000000000, 16(%rsp)
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 4(%rsp), %rsi
leaq _ZSt3cin(%rip), %rbx
movq %rbx, %rdi
call _ZNSirsERi@PLT
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 8(%rsp), %rsi
movq %rbx, %rdi
call _ZNSirsERi@PLT
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %ebx
movl 8(%rsp), %r12d
movl 12(%rsp), %ebp
movl %r12d, %ecx
imull %ebp, %ecx
movl %ebx, %eax
cltd
idivl %ecx
testl %edx, %edx
jne .L22
movl %edx, %r13d
cmpl $1024, %ebp
jg .L20
cmpl $28, %r12d
jg .L20
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl 8(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L18:
call cudaDeviceSynchronize@PLT
leaq 16(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq _ZSt4cout(%rip), %rbx
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $9, 8(%rbx,%rax)
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $9, 8(%rbx,%rax)
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L13
.L22:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %r13d
jmp .L13
.L20:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %r13d
.L13:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl %r13d, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %ebx, %eax
cltd
idivl %r12d
cltd
idivl %ebp
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
movsd .LC6(%rip), %xmm0
divsd %xmm1, %xmm0
movl %eax, %esi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z10calc_chunkdPdidPdi
jmp .L18
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10calc_chunkdPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10calc_chunkdPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cmath>
#include <iomanip>
#include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
using namespace std;
#define ROOT 0
__device__ double eval_func1(double);
__global__ void calc_chunk(double, double*, int);
int main(int argc, char* argv[]){
double integral = 0.0;
int n, numBlocks, numThreads; // n = number of points, numBlocks = blocks on the device, numThreads = threads per block
double step; // step size when computing the integral; as n increases, step decreases and the integral's precision increases
int parts; // number of parts of the integral to compute for each thread
double* deviceGlobalSum;
cout<<"Enter number of points: ";
cin >> n;
cout<<"Enter number of blocks (up to 28): "; // GTX1080 on Pitt's CRC only allows up to 28 processors
cin >> numBlocks;
cout<<"Enter number of threads per block (up to 1024): "; // GTX1080 on Pitt's CRC only allows up to 1024 threads/block
cin >> numThreads;
if(n % (numBlocks*numThreads) != 0){ // can't split n up evenly by the number of threads
cout<<"N is not evenly divisible by # of Blocks! Exiting..."<<endl;
return 1;
} else if(numBlocks > 28 || numThreads > 1024){
cout<<"Too many requested blocks or threads! Exiting..."<<endl;
return 1;
}
step = 1.0 / (double) n; // step value of the integral, this is delta x for the trapezoidal rule
parts = (n / numBlocks) / numThreads; // number of parts per thread
// begin the timer for the multi-threaded portion of the code
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
// copy the global sum, or future integral value, from the host to the device
cudaMalloc((void**) &deviceGlobalSum, sizeof(double));
cudaMemcpy(deviceGlobalSum, &integral, sizeof(double), cudaMemcpyHostToDevice);
// call a function with specified number of blocks (i.e. address spaces, similar to processors) and number of threads (i.e. threads for each block)
calc_chunk<<<numBlocks, numThreads>>>(step, deviceGlobalSum, parts);
// barrier for all devices to complete
cudaDeviceSynchronize();
// copy the global sum of the device to the integral variable on the host
cudaMemcpy(&integral, deviceGlobalSum, sizeof(double), cudaMemcpyDeviceToHost);
// compute the total computation time
cudaEventRecord(end);
float timeDiff;
cudaEventElapsedTime(&timeDiff, start, end);
cudaEventSynchronize(end);
cudaEventDestroy(start);
cudaEventDestroy(end);
// free memory malloc'd on the device
cudaFree(deviceGlobalSum);
// print out the time and integral value
cout<<setprecision(9)<<"Final value of the integral is "<<integral<<"!"<<endl;
cout<<setprecision(9)<<"Execution time: "<<timeDiff<<endl;
return 0;
}
// Integral function we want to evaluate; increases modularity of the program
__device__ double eval_func1(double x){
return 4.0 / (1.0 + pow(x, 2));
}
// Calculate the chunk of the integral assigned to each thread (which belongs to a block)
__global__ void calc_chunk(double step, double* globalSum, int parts){
__shared__ double blockSum; // sum of all the parts in this block's chunk
if(threadIdx.x == 0) blockSum = 0.0; // let thread 0 initilize the shared variable since you can't declare and initialize on the same line
__syncthreads(); // barrier so no thread writes to the shared variable before it's initialized
int chunkNum = blockIdx.x * blockDim.x + threadIdx.x; // the chunk of the integral this thread is working on
double threadSum = 0.0;
double x = chunkNum * step * parts; // current x value we're evaluating the 'part' of the 'chunk' at
for(int i = 0; i < parts; i++){
double leftVal = eval_func1(x); // f(x_{i-1})
double rightVal = eval_func1(x + step); // f(x_{i})
threadSum += ((leftVal + rightVal)/2.0) * step; // trapezoidal rule
x += step;
}
atomicAdd(&blockSum, threadSum); // all thread write to the shared variable of the block
__syncthreads();
if(threadIdx.x == ROOT){
atomicAdd(globalSum, blockSum); // all blocks write to the 'shared' variable, global sum, of the device
}
} | #include <iostream>
#include <cmath>
#include <iomanip>
#include <hip/hip_runtime.h>
#include <stdio.h>
using namespace std;
#define ROOT 0
__device__ double eval_func1(double);
__global__ void calc_chunk(double, double*, int);
int main(int argc, char* argv[]){
double integral = 0.0;
int n, numBlocks, numThreads; // n = number of points, numBlocks = blocks on the device, numThreads = threads per block
double step; // step size when computing the integral; as n increases, step decreases and the integral's precision increases
int parts; // number of parts of the integral to compute for each thread
double* deviceGlobalSum;
cout<<"Enter number of points: ";
cin >> n;
cout<<"Enter number of blocks (up to 28): "; // GTX1080 on Pitt's CRC only allows up to 28 processors
cin >> numBlocks;
cout<<"Enter number of threads per block (up to 1024): "; // GTX1080 on Pitt's CRC only allows up to 1024 threads/block
cin >> numThreads;
if(n % (numBlocks*numThreads) != 0){ // can't split n up evenly by the number of threads
cout<<"N is not evenly divisible by # of Blocks! Exiting..."<<endl;
return 1;
} else if(numBlocks > 28 || numThreads > 1024){
cout<<"Too many requested blocks or threads! Exiting..."<<endl;
return 1;
}
step = 1.0 / (double) n; // step value of the integral, this is delta x for the trapezoidal rule
parts = (n / numBlocks) / numThreads; // number of parts per thread
// begin the timer for the multi-threaded portion of the code
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
// copy the global sum, or future integral value, from the host to the device
hipMalloc((void**) &deviceGlobalSum, sizeof(double));
hipMemcpy(deviceGlobalSum, &integral, sizeof(double), hipMemcpyHostToDevice);
// call a function with specified number of blocks (i.e. address spaces, similar to processors) and number of threads (i.e. threads for each block)
calc_chunk<<<numBlocks, numThreads>>>(step, deviceGlobalSum, parts);
// barrier for all devices to complete
hipDeviceSynchronize();
// copy the global sum of the device to the integral variable on the host
hipMemcpy(&integral, deviceGlobalSum, sizeof(double), hipMemcpyDeviceToHost);
// compute the total computation time
hipEventRecord(end);
float timeDiff;
hipEventElapsedTime(&timeDiff, start, end);
hipEventSynchronize(end);
hipEventDestroy(start);
hipEventDestroy(end);
// free memory malloc'd on the device
hipFree(deviceGlobalSum);
// print out the time and integral value
cout<<setprecision(9)<<"Final value of the integral is "<<integral<<"!"<<endl;
cout<<setprecision(9)<<"Execution time: "<<timeDiff<<endl;
return 0;
}
// Integral function we want to evaluate; increases modularity of the program
__device__ double eval_func1(double x){
return 4.0 / (1.0 + pow(x, 2));
}
// Calculate the chunk of the integral assigned to each thread (which belongs to a block)
__global__ void calc_chunk(double step, double* globalSum, int parts){
__shared__ double blockSum; // sum of all the parts in this block's chunk
if(threadIdx.x == 0) blockSum = 0.0; // let thread 0 initilize the shared variable since you can't declare and initialize on the same line
__syncthreads(); // barrier so no thread writes to the shared variable before it's initialized
int chunkNum = blockIdx.x * blockDim.x + threadIdx.x; // the chunk of the integral this thread is working on
double threadSum = 0.0;
double x = chunkNum * step * parts; // current x value we're evaluating the 'part' of the 'chunk' at
for(int i = 0; i < parts; i++){
double leftVal = eval_func1(x); // f(x_{i-1})
double rightVal = eval_func1(x + step); // f(x_{i})
threadSum += ((leftVal + rightVal)/2.0) * step; // trapezoidal rule
x += step;
}
atomicAdd(&blockSum, threadSum); // all thread write to the shared variable of the block
__syncthreads();
if(threadIdx.x == ROOT){
atomicAdd(globalSum, blockSum); // all blocks write to the 'shared' variable, global sum, of the device
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <cmath>
#include <iomanip>
#include <hip/hip_runtime.h>
#include <stdio.h>
using namespace std;
#define ROOT 0
__device__ double eval_func1(double);
__global__ void calc_chunk(double, double*, int);
int main(int argc, char* argv[]){
double integral = 0.0;
int n, numBlocks, numThreads; // n = number of points, numBlocks = blocks on the device, numThreads = threads per block
double step; // step size when computing the integral; as n increases, step decreases and the integral's precision increases
int parts; // number of parts of the integral to compute for each thread
double* deviceGlobalSum;
cout<<"Enter number of points: ";
cin >> n;
cout<<"Enter number of blocks (up to 28): "; // GTX1080 on Pitt's CRC only allows up to 28 processors
cin >> numBlocks;
cout<<"Enter number of threads per block (up to 1024): "; // GTX1080 on Pitt's CRC only allows up to 1024 threads/block
cin >> numThreads;
if(n % (numBlocks*numThreads) != 0){ // can't split n up evenly by the number of threads
cout<<"N is not evenly divisible by # of Blocks! Exiting..."<<endl;
return 1;
} else if(numBlocks > 28 || numThreads > 1024){
cout<<"Too many requested blocks or threads! Exiting..."<<endl;
return 1;
}
step = 1.0 / (double) n; // step value of the integral, this is delta x for the trapezoidal rule
parts = (n / numBlocks) / numThreads; // number of parts per thread
// begin the timer for the multi-threaded portion of the code
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
// copy the global sum, or future integral value, from the host to the device
hipMalloc((void**) &deviceGlobalSum, sizeof(double));
hipMemcpy(deviceGlobalSum, &integral, sizeof(double), hipMemcpyHostToDevice);
// call a function with specified number of blocks (i.e. address spaces, similar to processors) and number of threads (i.e. threads for each block)
calc_chunk<<<numBlocks, numThreads>>>(step, deviceGlobalSum, parts);
// barrier for all devices to complete
hipDeviceSynchronize();
// copy the global sum of the device to the integral variable on the host
hipMemcpy(&integral, deviceGlobalSum, sizeof(double), hipMemcpyDeviceToHost);
// compute the total computation time
hipEventRecord(end);
float timeDiff;
hipEventElapsedTime(&timeDiff, start, end);
hipEventSynchronize(end);
hipEventDestroy(start);
hipEventDestroy(end);
// free memory malloc'd on the device
hipFree(deviceGlobalSum);
// print out the time and integral value
cout<<setprecision(9)<<"Final value of the integral is "<<integral<<"!"<<endl;
cout<<setprecision(9)<<"Execution time: "<<timeDiff<<endl;
return 0;
}
// Integral function we want to evaluate; increases modularity of the program
__device__ double eval_func1(double x){
return 4.0 / (1.0 + pow(x, 2));
}
// Calculate the chunk of the integral assigned to each thread (which belongs to a block)
__global__ void calc_chunk(double step, double* globalSum, int parts){
__shared__ double blockSum; // sum of all the parts in this block's chunk
if(threadIdx.x == 0) blockSum = 0.0; // let thread 0 initilize the shared variable since you can't declare and initialize on the same line
__syncthreads(); // barrier so no thread writes to the shared variable before it's initialized
int chunkNum = blockIdx.x * blockDim.x + threadIdx.x; // the chunk of the integral this thread is working on
double threadSum = 0.0;
double x = chunkNum * step * parts; // current x value we're evaluating the 'part' of the 'chunk' at
for(int i = 0; i < parts; i++){
double leftVal = eval_func1(x); // f(x_{i-1})
double rightVal = eval_func1(x + step); // f(x_{i})
threadSum += ((leftVal + rightVal)/2.0) * step; // trapezoidal rule
x += step;
}
atomicAdd(&blockSum, threadSum); // all thread write to the shared variable of the block
__syncthreads();
if(threadIdx.x == ROOT){
atomicAdd(globalSum, blockSum); // all blocks write to the 'shared' variable, global sum, of the device
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10calc_chunkdPdi
.globl _Z10calc_chunkdPdi
.p2align 8
.type _Z10calc_chunkdPdi,@function
_Z10calc_chunkdPdi:
v_cmp_eq_u32_e64 s2, 0, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_2
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, v1
ds_store_b64 v3, v[1:2]
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s33, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cmp_lt_i32 s33, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b64 s[8:9], s[0:1], 0x0
s_mov_b32 s11, 0x3fe55555
s_mov_b32 s10, 0x55555555
s_mov_b32 s13, 0x3fba6564
s_mov_b32 s12, 0x968915a9
s_mov_b32 s14, 0x4222de17
s_mov_b32 s17, 0x3fbe25e4
s_mov_b32 s16, 0x3abe935a
s_mov_b32 s19, 0x3fc110ef
s_mov_b32 s18, 0x47e6c9c2
s_mov_b32 s21, 0x3fc3b13b
s_mov_b32 s20, 0xcfa74449
s_mov_b32 s23, 0x3fc745d1
s_mov_b32 s22, 0x71bf3c30
s_mov_b32 s25, 0x3fcc71c7
s_mov_b32 s24, 0x1c7792ce
s_mov_b32 s27, 0x3fd24924
s_mov_b32 s26, 0x924920da
s_mov_b32 s29, 0x3fd99999
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_mov_b32 s28, 0x9999999c
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_cvt_f64_i32_e32 v[2:3], s33
s_mov_b32 s15, 0x3fbdee67
s_mov_b32 s31, 0x3fe62e42
s_mov_b32 s30, 0xfefa39ef
s_mov_b32 s35, 0x3c7abc9e
s_mov_b32 s34, 0x3b39803f
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f64_i32_e32 v[0:1], v1
s_mov_b32 s7, 0xbfe55555
s_mov_b32 s37, 0x3c8543b0
s_mov_b32 s36, 0xd5df274d
s_mov_b32 s39, 0x3ff71547
s_mov_b32 s38, 0x652b82fe
s_mov_b32 s41, 0xbfe62e42
s_mov_b32 s43, 0xbc7abc9e
s_mov_b32 s45, 0x3e928af3
s_mov_b32 s44, 0xfca7ab0c
s_mov_b32 s47, 0x3e5ade15
s_mov_b32 s46, 0x6a5dcb37
s_mov_b32 s49, 0x3ec71dee
s_mov_b32 s48, 0x623fde64
s_mov_b32 s51, 0x3efa0199
s_mov_b32 s50, 0x7c89e6b0
s_mov_b32 s53, 0x3f2a01a0
s_mov_b32 s52, 0x14761f6e
s_mov_b32 s55, 0x3f56c16c
s_mov_b32 s54, 0x1852b7b0
s_mov_b32 s57, 0x3f811111
s_mov_b32 s56, 0x11122322
s_mov_b32 s59, 0x3fa55555
s_mov_b32 s58, 0x555502a1
s_mov_b32 s61, 0x3fc55555
s_mov_b32 s60, 0x55555511
s_mov_b32 s63, 0x3fe00000
s_mov_b32 s62, 11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_mul_f64 v[4:5], v[0:1], s[8:9]
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
v_mul_f64 v[2:3], v[4:5], v[2:3]
.LBB0_4:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e64 v[4:5], |v[2:3]|
s_mov_b32 s6, s10
s_mov_b32 s40, s30
s_mov_b32 s42, s34
s_add_i32 s33, s33, -1
v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[4:5]
v_cndmask_b32_e64 v6, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[4:5], v[4:5], v6
v_add_f64 v[6:7], v[4:5], 1.0
v_add_f64 v[12:13], v[4:5], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[8:9], v[6:7]
v_add_f64 v[14:15], v[6:7], -1.0
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[10:11], v[8:9], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[6:7], v[10:11]
v_fma_f64 v[6:7], v[10:11], v[6:7], -v[16:17]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[4:5], v[10:11], v[4:5], v[6:7]
v_add_f64 v[6:7], v[16:17], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[12:13], -v[6:7]
v_add_f64 v[16:17], v[6:7], -v[16:17]
v_add_f64 v[12:13], v[12:13], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[16:17], -v[4:5]
v_add_f64 v[6:7], v[12:13], -v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[4:5], v[14:15], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[4:5], v[8:9], v[4:5]
v_add_f64 v[6:7], v[10:11], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[6:7], -v[10:11]
v_mul_f64 v[10:11], v[6:7], v[6:7]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[8:9], v[6:7], v[6:7], -v[10:11]
v_add_f64 v[12:13], v[4:5], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[6:7], v[12:13], v[8:9]
v_add_f64 v[12:13], v[10:11], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[14:15], v[12:13], s[14:15], s[12:13]
v_add_f64 v[10:11], v[12:13], -v[10:11]
v_mul_f64 v[18:19], v[6:7], v[12:13]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[8:9], -v[10:11]
v_fma_f64 v[22:23], v[12:13], v[6:7], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[18:19]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[22:23]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[14:15], v[12:13], v[14:15], s[26:27]
v_fma_f64 v[14:15], v[12:13], v[14:15], s[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[16:17], v[12:13], v[14:15]
v_fma_f64 v[10:11], v[12:13], v[14:15], -v[16:17]
v_fma_f64 v[12:13], v[12:13], v[4:5], v[22:23]
v_ldexp_f64 v[4:5], v[4:5], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[10:11], v[8:9], v[14:15], v[10:11]
v_fma_f64 v[8:9], v[8:9], v[6:7], v[12:13]
v_ldexp_f64 v[6:7], v[6:7], 1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[16:17], v[10:11]
v_add_f64 v[12:13], v[18:19], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[14:15], s[10:11]
v_add_f64 v[16:17], v[14:15], -v[16:17]
v_add_f64 v[18:19], v[12:13], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[24:25], v[20:21], s[6:7]
v_add_f64 v[10:11], v[10:11], -v[16:17]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[8:9], -v[18:19]
v_add_f64 v[14:15], v[14:15], -v[24:25]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[10:11], v[10:11], s[36:37]
v_add_f64 v[10:11], v[10:11], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[14:15], v[20:21], v[10:11]
v_add_f64 v[16:17], v[20:21], -v[14:15]
v_mul_f64 v[20:21], v[12:13], v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[10:11], v[16:17]
v_fma_f64 v[16:17], v[12:13], v[14:15], -v[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[10:11], v[12:13], v[10:11], v[16:17]
v_frexp_exp_i32_f64_e32 v12, v[2:3]
v_fma_f64 v[8:9], v[8:9], v[14:15], v[10:11]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_cvt_f64_i32_e32 v[12:13], v12
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[20:21], v[8:9]
v_mul_f64 v[18:19], v[12:13], s[30:31]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[14:15], v[6:7], v[10:11]
v_add_f64 v[16:17], v[10:11], -v[20:21]
v_add_f64 v[6:7], v[14:15], -v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[8:9], v[8:9], -v[16:17]
v_fma_f64 v[16:17], v[12:13], s[30:31], -v[18:19]
v_add_f64 v[6:7], v[10:11], -v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[4:5], v[4:5], v[8:9]
v_fma_f64 v[8:9], v[12:13], s[34:35], v[16:17]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[6:7], v[18:19], v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[14:15], v[4:5]
v_add_f64 v[18:19], v[6:7], -v[18:19]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[12:13], v[6:7], v[10:11]
v_add_f64 v[14:15], v[10:11], -v[14:15]
v_add_f64 v[8:9], v[8:9], -v[18:19]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[16:17], v[12:13], -v[6:7]
v_add_f64 v[4:5], v[4:5], -v[14:15]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[20:21], v[12:13], -v[16:17]
v_add_f64 v[10:11], v[10:11], -v[16:17]
v_add_f64 v[14:15], v[8:9], v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[6:7], -v[20:21]
v_add_f64 v[6:7], v[10:11], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[10:11], v[14:15], -v[8:9]
v_add_f64 v[6:7], v[14:15], v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_f64 v[14:15], v[14:15], -v[10:11]
v_add_f64 v[4:5], v[4:5], -v[10:11]
v_add_f64 v[16:17], v[12:13], v[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[8:9], -v[14:15]
v_add_f64 v[10:11], v[16:17], -v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[4:5], v[4:5], v[8:9]
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[4:5], v[6:7]
v_add_f64 v[6:7], v[16:17], v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[8:9], v[6:7], -v[16:17]
v_add_f64 v[10:11], v[6:7], v[6:7]
v_add_f64 v[4:5], v[4:5], -v[8:9]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[6:7], v[6:7], 2.0, -v[10:11]
v_cmp_class_f64_e64 vcc_lo, v[10:11], 0x204
v_fma_f64 v[4:5], v[4:5], 2.0, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[6:7], v[10:11], v[4:5]
v_dual_cndmask_b32 v9, v7, v11 :: v_dual_cndmask_b32 v8, v6, v10
v_add_f64 v[6:7], v[6:7], -v[10:11]
s_delay_alu instid0(VALU_DEP_2)
v_mul_f64 v[12:13], v[8:9], s[38:39]
v_cmp_nlt_f64_e64 s3, 0x40900000, v[8:9]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[8:9]|
v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[8:9]
v_add_f64 v[4:5], v[4:5], -v[6:7]
v_rndne_f64_e32 v[12:13], v[12:13]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v5, 0, v5 :: v_dual_cndmask_b32 v4, 0, v4
s_and_b32 vcc_lo, s4, s3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[14:15], v[12:13], s[40:41], v[8:9]
v_cvt_i32_f64_e32 v18, v[12:13]
v_fma_f64 v[14:15], v[12:13], s[42:43], v[14:15]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], s[46:47], s[44:45]
v_fma_f64 v[16:17], v[14:15], v[16:17], s[48:49]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[50:51]
v_fma_f64 v[16:17], v[14:15], v[16:17], s[52:53]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[54:55]
v_fma_f64 v[16:17], v[14:15], v[16:17], s[56:57]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[58:59]
v_fma_f64 v[16:17], v[14:15], v[16:17], s[60:61]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[16:17], v[14:15], v[16:17], s[62:63]
v_fma_f64 v[16:17], v[14:15], v[16:17], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], v[14:15], v[16:17], 1.0
v_ldexp_f64 v[10:11], v[12:13], v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v6, 0x7ff00000, v11, s3
v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[2:3]|
v_cndmask_b32_e64 v7, 0, v6, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, 0, v10, vcc_lo
v_cmp_neq_f64_e64 s4, 0, v[2:3]
v_add_f64 v[2:3], v[2:3], s[8:9]
v_fma_f64 v[4:5], v[6:7], v[4:5], v[6:7]
v_cmp_class_f64_e64 vcc_lo, v[6:7], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v4, v6
v_add_f64 v[4:5], |v[4:5]|, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[6:7], null, v[4:5], v[4:5], 4.0
v_div_scale_f64 v[12:13], vcc_lo, 4.0, v[4:5], 4.0
v_rcp_f64_e32 v[8:9], v[6:7]
s_waitcnt_depctr 0xfff
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
v_mul_f64 v[10:11], v[12:13], v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f64 v[4:5], v[6:7], v[4:5], 4.0
v_cndmask_b32_e64 v27, 0, v5, s3
v_frexp_mant_f64_e64 v[5:6], |v[2:3]|
s_and_b32 s3, s4, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[5:6]
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
v_ldexp_f64 v[5:6], v[5:6], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[5:6], 1.0
v_add_f64 v[13:14], v[5:6], -1.0
v_rcp_f64_e32 v[9:10], v[7:8]
v_add_f64 v[15:16], v[7:8], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], -v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[13:14], v[9:10]
v_mul_f64 v[17:18], v[7:8], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[11:12], v[7:8], -v[17:18]
v_fma_f64 v[5:6], v[11:12], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[17:18], v[5:6]
v_add_f64 v[15:16], v[13:14], -v[7:8]
v_add_f64 v[17:18], v[7:8], -v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[13:14], -v[15:16]
v_add_f64 v[5:6], v[17:18], -v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[13:14], -v[7:8]
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[15:16], v[5:6]
v_mul_f64 v[5:6], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[11:12], v[5:6]
v_add_f64 v[9:10], v[7:8], -v[11:12]
v_mul_f64 v[11:12], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[9:10]
v_fma_f64 v[9:10], v[7:8], v[7:8], -v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[13:14], v[5:6], v[5:6]
v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[13:14], v[11:12], v[9:10]
v_fma_f64 v[15:16], v[13:14], s[14:15], s[12:13]
v_add_f64 v[11:12], v[13:14], -v[11:12]
v_mul_f64 v[19:20], v[7:8], v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[16:17]
v_add_f64 v[9:10], v[9:10], -v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[23:24], v[13:14], v[7:8], -v[19:20]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[18:19]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[20:21]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[22:23]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[24:25]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[26:27]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[28:29]
v_mul_f64 v[17:18], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[13:14], v[15:16], -v[17:18]
v_fma_f64 v[13:14], v[13:14], v[5:6], v[23:24]
v_ldexp_f64 v[5:6], v[5:6], 1
v_fma_f64 v[11:12], v[9:10], v[15:16], v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[9:10], v[9:10], v[7:8], v[13:14]
v_ldexp_f64 v[7:8], v[7:8], 1
v_add_f64 v[15:16], v[17:18], v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[19:20], v[9:10]
v_add_f64 v[21:22], v[15:16], s[10:11]
v_add_f64 v[17:18], v[15:16], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[19:20], v[13:14], -v[19:20]
v_add_f64 v[25:26], v[21:22], s[6:7]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], -v[17:18]
v_add_f64 v[9:10], v[9:10], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[15:16], v[15:16], -v[25:26]
v_add_f64 v[11:12], v[11:12], s[36:37]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[11:12], v[11:12], v[15:16]
v_add_f64 v[15:16], v[21:22], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[17:18], v[21:22], -v[15:16]
v_mul_f64 v[21:22], v[13:14], v[15:16]
v_add_f64 v[11:12], v[11:12], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[13:14], v[15:16], -v[21:22]
v_fma_f64 v[11:12], v[13:14], v[11:12], v[17:18]
v_frexp_exp_i32_f64_e32 v13, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], v[9:10], v[15:16], v[11:12]
v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[13:14], v13
v_add_f64 v[11:12], v[21:22], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[19:20], v[13:14], s[30:31]
v_add_f64 v[15:16], v[7:8], v[11:12]
v_add_f64 v[17:18], v[11:12], -v[21:22]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[15:16], -v[7:8]
v_add_f64 v[9:10], v[9:10], -v[17:18]
v_fma_f64 v[17:18], v[13:14], s[30:31], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[11:12], -v[7:8]
v_add_f64 v[5:6], v[5:6], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], v[13:14], s[34:35], v[17:18]
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[19:20], v[9:10]
v_add_f64 v[11:12], v[15:16], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[19:20], v[7:8], -v[19:20]
v_add_f64 v[13:14], v[7:8], v[11:12]
v_add_f64 v[15:16], v[11:12], -v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[9:10], -v[19:20]
v_add_f64 v[17:18], v[13:14], -v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[15:16]
v_add_f64 v[21:22], v[13:14], -v[17:18]
v_add_f64 v[11:12], v[11:12], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[15:16], v[9:10], v[5:6]
v_add_f64 v[7:8], v[7:8], -v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[11:12], v[7:8]
v_add_f64 v[11:12], v[15:16], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[15:16], v[7:8]
v_add_f64 v[15:16], v[15:16], -v[11:12]
v_add_f64 v[5:6], v[5:6], -v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[17:18], v[13:14], v[7:8]
v_add_f64 v[9:10], v[9:10], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[17:18], -v[13:14]
v_add_f64 v[5:6], v[5:6], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], -v[11:12]
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[17:18], v[5:6]
v_add_f64 v[9:10], v[7:8], -v[17:18]
v_add_f64 v[11:12], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[9:10]
v_fma_f64 v[7:8], v[7:8], 2.0, -v[11:12]
v_cmp_class_f64_e64 vcc_lo, v[11:12], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], 2.0, v[7:8]
v_add_f64 v[7:8], v[11:12], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v9, v7, v11 :: v_dual_cndmask_b32 v10, v8, v12
v_add_f64 v[7:8], v[7:8], -v[11:12]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[9:10]|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], -v[7:8]
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_mul_f64 v[13:14], v[9:10], s[38:39]
v_cmp_nlt_f64_e64 s5, 0x40900000, v[9:10]
v_cmp_ngt_f64_e64 s6, 0xc090cc00, v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f64_e32 v[13:14], v[13:14]
v_fma_f64 v[15:16], v[13:14], s[40:41], v[9:10]
v_cvt_i32_f64_e32 v19, v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], s[42:43], v[15:16]
v_fma_f64 v[17:18], v[15:16], s[46:47], s[44:45]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[48:49]
v_fma_f64 v[17:18], v[15:16], v[17:18], s[50:51]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[52:53]
v_fma_f64 v[17:18], v[15:16], v[17:18], s[54:55]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[56:57]
v_fma_f64 v[17:18], v[15:16], v[17:18], s[58:59]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[60:61]
v_fma_f64 v[17:18], v[15:16], v[17:18], s[62:63]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], 1.0
v_fma_f64 v[13:14], v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ldexp_f64 v[11:12], v[13:14], v19
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
s_and_b32 vcc_lo, s6, s5
v_cndmask_b32_e64 v7, 0x7ff00000, v12, s5
v_cmp_neq_f64_e64 s5, 0, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v8, 0, v7, s6
v_cndmask_b32_e32 v7, 0, v11, vcc_lo
v_fma_f64 v[5:6], v[7:8], v[5:6], v[7:8]
v_cmp_class_f64_e64 vcc_lo, v[7:8], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v5, v5, v7
v_add_f64 v[5:6], |v[5:6]|, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f64 v[7:8], null, v[5:6], v[5:6], 4.0
v_div_scale_f64 v[13:14], vcc_lo, 4.0, v[5:6], 4.0
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_mul_f64 v[11:12], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[7:8], v[11:12], v[13:14]
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[11:12]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[2:3]|
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fixup_f64 v[5:6], v[7:8], v[5:6], 4.0
v_cndmask_b32_e64 v7, 0x40100000, v27, s4
v_cndmask_b32_e32 v8, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
s_and_b32 vcc_lo, s5, vcc_lo
v_cndmask_b32_e64 v6, 0, v4, s3
s_cmp_eq_u32 s33, 0
v_cndmask_b32_e64 v9, 0x40100000, v8, s5
v_cndmask_b32_e32 v8, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[4:5], v[6:7], v[8:9]
v_mul_f64 v[4:5], v[4:5], 0.5
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[0:1], v[4:5], s[8:9], v[0:1]
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_6
.LBB0_5:
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v1, 0
.LBB0_6:
v_mov_b32_e32 v2, 0
v_bfrev_b32_e32 v3, 1
s_mov_b32 s3, exec_lo
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_ctz_i32_b32 s6, s3
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_readlane_b32 s5, v1, s6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readlane_b32 s4, v0, s6
v_add_f64 v[2:3], v[2:3], s[4:5]
s_lshl_b32 s4, 1, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s3, s3, s4
s_cmp_lg_u32 s3, 0
s_cbranch_scc1 .LBB0_7
v_mbcnt_lo_u32_b32 v0, exec_lo, 0
s_mov_b32 s4, 0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_12
v_mov_b32_e32 v4, 0
ds_load_b64 v[0:1], v4
.LBB0_10:
s_waitcnt lgkmcnt(0)
v_add_f64 v[5:6], v[0:1], v[2:3]
ds_cmpstore_rtn_b64 v[5:6], v4, v[5:6], v[0:1]
s_waitcnt lgkmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[5:6], v[0:1]
v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_10
s_or_b32 exec_lo, exec_lo, s4
.LBB0_12:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_16
s_mov_b32 s3, exec_lo
s_mov_b32 s2, 0
v_mbcnt_lo_u32_b32 v0, s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 s4, exec_lo, vcc_lo
s_mov_b32 exec_lo, s4
s_cbranch_execz .LBB0_16
s_load_b64 s[0:1], s[0:1], 0x8
s_bcnt1_i32_b32 s3, s3
s_delay_alu instid0(SALU_CYCLE_1)
v_cvt_f64_u32_e32 v[0:1], s3
s_waitcnt lgkmcnt(0)
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v6, 0
ds_load_b64 v[2:3], v6
s_waitcnt lgkmcnt(0)
v_mul_f64 v[4:5], v[2:3], v[0:1]
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
.LBB0_15:
s_delay_alu instid0(VALU_DEP_1)
v_add_f64 v[0:1], v[2:3], v[4:5]
global_atomic_cmpswap_b64 v[0:1], v6, v[0:3], s[0:1] glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_15
.LBB0_16:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10calc_chunkdPdi
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 64
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10calc_chunkdPdi, .Lfunc_end0-_Z10calc_chunkdPdi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10calc_chunkdPdi
.private_segment_fixed_size: 0
.sgpr_count: 66
.sgpr_spill_count: 0
.symbol: _Z10calc_chunkdPdi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <cmath>
#include <iomanip>
#include <hip/hip_runtime.h>
#include <stdio.h>
using namespace std;
#define ROOT 0
__device__ double eval_func1(double);
__global__ void calc_chunk(double, double*, int);
int main(int argc, char* argv[]){
double integral = 0.0;
int n, numBlocks, numThreads; // n = number of points, numBlocks = blocks on the device, numThreads = threads per block
double step; // step size when computing the integral; as n increases, step decreases and the integral's precision increases
int parts; // number of parts of the integral to compute for each thread
double* deviceGlobalSum;
cout<<"Enter number of points: ";
cin >> n;
cout<<"Enter number of blocks (up to 28): "; // GTX1080 on Pitt's CRC only allows up to 28 processors
cin >> numBlocks;
cout<<"Enter number of threads per block (up to 1024): "; // GTX1080 on Pitt's CRC only allows up to 1024 threads/block
cin >> numThreads;
if(n % (numBlocks*numThreads) != 0){ // can't split n up evenly by the number of threads
cout<<"N is not evenly divisible by # of Blocks! Exiting..."<<endl;
return 1;
} else if(numBlocks > 28 || numThreads > 1024){
cout<<"Too many requested blocks or threads! Exiting..."<<endl;
return 1;
}
step = 1.0 / (double) n; // step value of the integral, this is delta x for the trapezoidal rule
parts = (n / numBlocks) / numThreads; // number of parts per thread
// begin the timer for the multi-threaded portion of the code
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
// copy the global sum, or future integral value, from the host to the device
hipMalloc((void**) &deviceGlobalSum, sizeof(double));
hipMemcpy(deviceGlobalSum, &integral, sizeof(double), hipMemcpyHostToDevice);
// call a function with specified number of blocks (i.e. address spaces, similar to processors) and number of threads (i.e. threads for each block)
calc_chunk<<<numBlocks, numThreads>>>(step, deviceGlobalSum, parts);
// barrier for all devices to complete
hipDeviceSynchronize();
// copy the global sum of the device to the integral variable on the host
hipMemcpy(&integral, deviceGlobalSum, sizeof(double), hipMemcpyDeviceToHost);
// compute the total computation time
hipEventRecord(end);
float timeDiff;
hipEventElapsedTime(&timeDiff, start, end);
hipEventSynchronize(end);
hipEventDestroy(start);
hipEventDestroy(end);
// free memory malloc'd on the device
hipFree(deviceGlobalSum);
// print out the time and integral value
cout<<setprecision(9)<<"Final value of the integral is "<<integral<<"!"<<endl;
cout<<setprecision(9)<<"Execution time: "<<timeDiff<<endl;
return 0;
}
// Integral function we want to evaluate; increases modularity of the program
__device__ double eval_func1(double x){
return 4.0 / (1.0 + pow(x, 2));
}
// Calculate the chunk of the integral assigned to each thread (which belongs to a block)
__global__ void calc_chunk(double step, double* globalSum, int parts){
__shared__ double blockSum; // sum of all the parts in this block's chunk
if(threadIdx.x == 0) blockSum = 0.0; // let thread 0 initilize the shared variable since you can't declare and initialize on the same line
__syncthreads(); // barrier so no thread writes to the shared variable before it's initialized
int chunkNum = blockIdx.x * blockDim.x + threadIdx.x; // the chunk of the integral this thread is working on
double threadSum = 0.0;
double x = chunkNum * step * parts; // current x value we're evaluating the 'part' of the 'chunk' at
for(int i = 0; i < parts; i++){
double leftVal = eval_func1(x); // f(x_{i-1})
double rightVal = eval_func1(x + step); // f(x_{i})
threadSum += ((leftVal + rightVal)/2.0) * step; // trapezoidal rule
x += step;
}
atomicAdd(&blockSum, threadSum); // all thread write to the shared variable of the block
__syncthreads();
if(threadIdx.x == ROOT){
atomicAdd(globalSum, blockSum); // all blocks write to the 'shared' variable, global sum, of the device
}
} | .text
.file "integration.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq $0, 32(%rsp)
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 40(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rsp, %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 40(%rsp), %ebx
movl 4(%rsp), %r14d
movl (%rsp), %ebp
movl %ebp, %ecx
imull %r14d, %ecx
movl %ebx, %eax
cltd
idivl %ecx
testl %edx, %edx
je .LBB0_4
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $52, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_23
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_14
.LBB0_3:
movzbl 67(%rbx), %eax
jmp .LBB0_15
.LBB0_4:
cmpl $28, %r14d
jg .LBB0_11
# %bb.5:
cmpl $1025, %ebp # imm = 0x401
jge .LBB0_11
# %bb.6:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %edi
movl (%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movl %ebx, %eax
cltd
idivl %r14d
cltd
idivl %ebp
cvtsi2sd %ebx, %xmm0
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movq 16(%rsp), %rcx
movsd %xmm1, 136(%rsp)
movq %rcx, 128(%rsp)
movl %eax, 44(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10calc_chunkdPdi, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipFree
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $9, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 32(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_23
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%r14)
je .LBB0_17
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB0_18
.LBB0_11:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_23
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%rbx)
jne .LBB0_3
.LBB0_14:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1, %eax
.LBB0_16:
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_17:
.cfi_def_cfa_offset 176
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $9, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
cmpb $0, 56(%rbx)
je .LBB0_21
# %bb.20:
movzbl 67(%rbx), %ecx
jmp .LBB0_22
.LBB0_21:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
jmp .LBB0_16
.LBB0_23:
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z25__device_stub__calc_chunkdPdi # -- Begin function _Z25__device_stub__calc_chunkdPdi
.p2align 4, 0x90
.type _Z25__device_stub__calc_chunkdPdi,@function
_Z25__device_stub__calc_chunkdPdi: # @_Z25__device_stub__calc_chunkdPdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movsd %xmm0, 72(%rsp)
movq %rdi, 64(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10calc_chunkdPdi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__calc_chunkdPdi, .Lfunc_end1-_Z25__device_stub__calc_chunkdPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10calc_chunkdPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter number of points: "
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Enter number of blocks (up to 28): "
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Enter number of threads per block (up to 1024): "
.size .L.str.2, 49
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "N is not evenly divisible by # of Blocks! Exiting..."
.size .L.str.3, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Too many requested blocks or threads! Exiting..."
.size .L.str.4, 49
.type _Z10calc_chunkdPdi,@object # @_Z10calc_chunkdPdi
.section .rodata,"a",@progbits
.globl _Z10calc_chunkdPdi
.p2align 3, 0x0
_Z10calc_chunkdPdi:
.quad _Z25__device_stub__calc_chunkdPdi
.size _Z10calc_chunkdPdi, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "Final value of the integral is "
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "!"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Execution time: "
.size .L.str.7, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10calc_chunkdPdi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__calc_chunkdPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym _Z10calc_chunkdPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0015b2b9_00000000-6_integration.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3953:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3953:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10eval_func1d
.type _Z10eval_func1d, @function
_Z10eval_func1d:
.LFB3950:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3950:
.size _Z10eval_func1d, .-_Z10eval_func1d
.globl _Z32__device_stub__Z10calc_chunkdPdidPdi
.type _Z32__device_stub__Z10calc_chunkdPdidPdi, @function
_Z32__device_stub__Z10calc_chunkdPdidPdi:
.LFB3975:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movsd %xmm0, 24(%rsp)
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10calc_chunkdPdi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3975:
.size _Z32__device_stub__Z10calc_chunkdPdidPdi, .-_Z32__device_stub__Z10calc_chunkdPdidPdi
.globl _Z10calc_chunkdPdi
.type _Z10calc_chunkdPdi, @function
_Z10calc_chunkdPdi:
.LFB3976:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10calc_chunkdPdidPdi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3976:
.size _Z10calc_chunkdPdi, .-_Z10calc_chunkdPdi
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Enter number of points: "
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Enter number of blocks (up to 28): "
.align 8
.LC3:
.string "Enter number of threads per block (up to 1024): "
.align 8
.LC4:
.string "N is not evenly divisible by # of Blocks! Exiting..."
.align 8
.LC5:
.string "Too many requested blocks or threads! Exiting..."
.align 8
.LC7:
.string "Final value of the integral is "
.section .rodata.str1.1
.LC8:
.string "!"
.LC9:
.string "Execution time: "
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0x000000000, 16(%rsp)
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 4(%rsp), %rsi
leaq _ZSt3cin(%rip), %rbx
movq %rbx, %rdi
call _ZNSirsERi@PLT
leaq .LC2(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 8(%rsp), %rsi
movq %rbx, %rdi
call _ZNSirsERi@PLT
leaq .LC3(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq 12(%rsp), %rsi
movq %rbx, %rdi
call _ZNSirsERi@PLT
movl 4(%rsp), %ebx
movl 8(%rsp), %r12d
movl 12(%rsp), %ebp
movl %r12d, %ecx
imull %ebp, %ecx
movl %ebx, %eax
cltd
idivl %ecx
testl %edx, %edx
jne .L22
movl %edx, %r13d
cmpl $1024, %ebp
jg .L20
cmpl $28, %r12d
jg .L20
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 40(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 24(%rsp), %rdi
movl $8, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rsi
movl $1, %ecx
movl $8, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %eax
movl %eax, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl 8(%rsp), %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L18:
call cudaDeviceSynchronize@PLT
leaq 16(%rsp), %rdi
movl $2, %ecx
movl $8, %edx
movq 24(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %esi
movq 40(%rsp), %rdi
call cudaEventRecord@PLT
leaq 60(%rsp), %rdi
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 40(%rsp), %rdi
call cudaEventSynchronize@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
movq 40(%rsp), %rdi
call cudaEventDestroy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq _ZSt4cout(%rip), %rbx
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $9, 8(%rbx,%rax)
leaq .LC7(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 16(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC8(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $9, 8(%rbx,%rax)
leaq .LC9(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 60(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L13
.L22:
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %r13d
jmp .L13
.L20:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %r13d
.L13:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl %r13d, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movl %ebx, %eax
cltd
idivl %r12d
cltd
idivl %ebp
pxor %xmm1, %xmm1
cvtsi2sdl %ebx, %xmm1
movsd .LC6(%rip), %xmm0
divsd %xmm1, %xmm0
movl %eax, %esi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z10calc_chunkdPdidPdi
jmp .L18
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z10calc_chunkdPdi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3978:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10calc_chunkdPdi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3978:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC6:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "integration.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI0_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq $0, 32(%rsp)
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $24, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 40(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
leaq 4(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rsp, %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movl 40(%rsp), %ebx
movl 4(%rsp), %r14d
movl (%rsp), %ebp
movl %ebp, %ecx
imull %r14d, %ecx
movl %ebx, %eax
cltd
idivl %ecx
testl %edx, %edx
je .LBB0_4
# %bb.1:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $52, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_23
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_14
.LBB0_3:
movzbl 67(%rbx), %eax
jmp .LBB0_15
.LBB0_4:
cmpl $28, %r14d
jg .LBB0_11
# %bb.5:
cmpl $1025, %ebp # imm = 0x401
jge .LBB0_11
# %bb.6:
leaq 24(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 16(%rsp), %rdi
movl $8, %esi
callq hipMalloc
movq 16(%rsp), %rdi
leaq 32(%rsp), %rsi
movl $8, %edx
movl $1, %ecx
callq hipMemcpy
movl 4(%rsp), %edi
movl (%rsp), %edx
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_8
# %bb.7:
movl %ebx, %eax
cltd
idivl %r14d
cltd
idivl %ebp
cvtsi2sd %ebx, %xmm0
movsd .LCPI0_0(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
movq 16(%rsp), %rcx
movsd %xmm1, 136(%rsp)
movq %rcx, 128(%rsp)
movl %eax, 44(%rsp)
leaq 136(%rsp), %rax
movq %rax, 48(%rsp)
leaq 128(%rsp), %rax
movq %rax, 56(%rsp)
leaq 44(%rsp), %rax
movq %rax, 64(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10calc_chunkdPdi, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_8:
callq hipDeviceSynchronize
movq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
movl $8, %edx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 24(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movq 16(%rsp), %rdi
callq hipFree
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $9, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd 32(%rsp), %xmm0 # xmm0 = mem[0],zero
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %rbx
movl $.L.str.6, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_23
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i16
cmpb $0, 56(%r14)
je .LBB0_17
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB0_18
.LBB0_11:
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $48, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_23
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i11
cmpb $0, 56(%rbx)
jne .LBB0_3
.LBB0_14:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $1, %eax
.LBB0_16:
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_17:
.cfi_def_cfa_offset 176
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit19
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $9, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_23
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i21
cmpb $0, 56(%rbx)
je .LBB0_21
# %bb.20:
movzbl 67(%rbx), %ecx
jmp .LBB0_22
.LBB0_21:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit24
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
jmp .LBB0_16
.LBB0_23:
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z25__device_stub__calc_chunkdPdi # -- Begin function _Z25__device_stub__calc_chunkdPdi
.p2align 4, 0x90
.type _Z25__device_stub__calc_chunkdPdi,@function
_Z25__device_stub__calc_chunkdPdi: # @_Z25__device_stub__calc_chunkdPdi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movsd %xmm0, 72(%rsp)
movq %rdi, 64(%rsp)
movl %esi, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10calc_chunkdPdi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__calc_chunkdPdi, .Lfunc_end1-_Z25__device_stub__calc_chunkdPdi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10calc_chunkdPdi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter number of points: "
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Enter number of blocks (up to 28): "
.size .L.str.1, 36
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Enter number of threads per block (up to 1024): "
.size .L.str.2, 49
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "N is not evenly divisible by # of Blocks! Exiting..."
.size .L.str.3, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Too many requested blocks or threads! Exiting..."
.size .L.str.4, 49
.type _Z10calc_chunkdPdi,@object # @_Z10calc_chunkdPdi
.section .rodata,"a",@progbits
.globl _Z10calc_chunkdPdi
.p2align 3, 0x0
_Z10calc_chunkdPdi:
.quad _Z25__device_stub__calc_chunkdPdi
.size _Z10calc_chunkdPdi, 8
.type .L.str.5,@object # @.str.5
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.5:
.asciz "Final value of the integral is "
.size .L.str.5, 32
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "!"
.size .L.str.6, 2
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Execution time: "
.size .L.str.7, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10calc_chunkdPdi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__calc_chunkdPdi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _ZSt3cin
.addrsig_sym _Z10calc_chunkdPdi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void InitArrays(float *ip, float *op, float *fp, int *kp, int ncols)
{
int i;
float *fppos, *oppos, *ippos;
int *kppos;
int blockOffset;
int rowStartPos;
int colsPerThread;
// Each block gets a row, each thread will fill part of a row
// Calculate the offset of the row
blockOffset = blockIdx.x * ncols;
// Calculate our offset into the row
rowStartPos = threadIdx.x * (ncols/blockDim.x);
// The number of cols per thread
colsPerThread = ncols/blockDim.x;
ippos = ip + blockOffset+ rowStartPos;
fppos = fp + blockOffset+ rowStartPos;
oppos = op + blockOffset+ rowStartPos;
kppos = kp + blockOffset+ rowStartPos;
for (i = 0; i < colsPerThread; i++) {
fppos[i] = NOTSETLOC; // Not Fixed
ippos[i] = 50;
oppos[i] = 50;
kppos[i] = 1; // Keep Going
}
if(rowStartPos == 0) {
fppos[0] = SETLOC;
ippos[0] = 0;
oppos[0] = 0;
kppos[0] = 0;
}
if(rowStartPos + colsPerThread >= ncols) {
fppos[colsPerThread-1] = SETLOC;
ippos[colsPerThread-1] = 0;
oppos[colsPerThread-1] = 0;
kppos[colsPerThread-1] = 0;
}
if(blockOffset == 0) {
for(i=0;i < colsPerThread; i++) {
fppos[i] = SETLOC;
ippos[i] = 0;
oppos[i] = 0;
kppos[i] = 0;
}
}
if(blockOffset == ncols - 1) {
for(i=0;i < colsPerThread; i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
if(blockOffset == 400 && rowStartPos < 330) {
if(rowStartPos + colsPerThread > 330) {
int end = 330 - rowStartPos;
for(i=0;i<end;i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
else {
for(i=0;i<colsPerThread;i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
}
if(blockOffset == 200 && rowStartPos <= 500 && rowStartPos + colsPerThread >=500) {
i=500-rowStartPos;
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
// Insert code to set the rest of the boundary and fixed positions
} | .file "tmpxft_0012669b_00000000-6_InitArrays.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii
.type _Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii, @function
_Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10InitArraysPfS_S_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii, .-_Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii
.globl _Z10InitArraysPfS_S_Pii
.type _Z10InitArraysPfS_S_Pii, @function
_Z10InitArraysPfS_S_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10InitArraysPfS_S_Pii, .-_Z10InitArraysPfS_S_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10InitArraysPfS_S_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10InitArraysPfS_S_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void InitArrays(float *ip, float *op, float *fp, int *kp, int ncols)
{
int i;
float *fppos, *oppos, *ippos;
int *kppos;
int blockOffset;
int rowStartPos;
int colsPerThread;
// Each block gets a row, each thread will fill part of a row
// Calculate the offset of the row
blockOffset = blockIdx.x * ncols;
// Calculate our offset into the row
rowStartPos = threadIdx.x * (ncols/blockDim.x);
// The number of cols per thread
colsPerThread = ncols/blockDim.x;
ippos = ip + blockOffset+ rowStartPos;
fppos = fp + blockOffset+ rowStartPos;
oppos = op + blockOffset+ rowStartPos;
kppos = kp + blockOffset+ rowStartPos;
for (i = 0; i < colsPerThread; i++) {
fppos[i] = NOTSETLOC; // Not Fixed
ippos[i] = 50;
oppos[i] = 50;
kppos[i] = 1; // Keep Going
}
if(rowStartPos == 0) {
fppos[0] = SETLOC;
ippos[0] = 0;
oppos[0] = 0;
kppos[0] = 0;
}
if(rowStartPos + colsPerThread >= ncols) {
fppos[colsPerThread-1] = SETLOC;
ippos[colsPerThread-1] = 0;
oppos[colsPerThread-1] = 0;
kppos[colsPerThread-1] = 0;
}
if(blockOffset == 0) {
for(i=0;i < colsPerThread; i++) {
fppos[i] = SETLOC;
ippos[i] = 0;
oppos[i] = 0;
kppos[i] = 0;
}
}
if(blockOffset == ncols - 1) {
for(i=0;i < colsPerThread; i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
if(blockOffset == 400 && rowStartPos < 330) {
if(rowStartPos + colsPerThread > 330) {
int end = 330 - rowStartPos;
for(i=0;i<end;i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
else {
for(i=0;i<colsPerThread;i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
}
if(blockOffset == 200 && rowStartPos <= 500 && rowStartPos + colsPerThread >=500) {
i=500-rowStartPos;
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
// Insert code to set the rest of the boundary and fixed positions
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InitArrays(float *ip, float *op, float *fp, int *kp, int ncols)
{
int i;
float *fppos, *oppos, *ippos;
int *kppos;
int blockOffset;
int rowStartPos;
int colsPerThread;
// Each block gets a row, each thread will fill part of a row
// Calculate the offset of the row
blockOffset = blockIdx.x * ncols;
// Calculate our offset into the row
rowStartPos = threadIdx.x * (ncols/blockDim.x);
// The number of cols per thread
colsPerThread = ncols/blockDim.x;
ippos = ip + blockOffset+ rowStartPos;
fppos = fp + blockOffset+ rowStartPos;
oppos = op + blockOffset+ rowStartPos;
kppos = kp + blockOffset+ rowStartPos;
for (i = 0; i < colsPerThread; i++) {
fppos[i] = NOTSETLOC; // Not Fixed
ippos[i] = 50;
oppos[i] = 50;
kppos[i] = 1; // Keep Going
}
if(rowStartPos == 0) {
fppos[0] = SETLOC;
ippos[0] = 0;
oppos[0] = 0;
kppos[0] = 0;
}
if(rowStartPos + colsPerThread >= ncols) {
fppos[colsPerThread-1] = SETLOC;
ippos[colsPerThread-1] = 0;
oppos[colsPerThread-1] = 0;
kppos[colsPerThread-1] = 0;
}
if(blockOffset == 0) {
for(i=0;i < colsPerThread; i++) {
fppos[i] = SETLOC;
ippos[i] = 0;
oppos[i] = 0;
kppos[i] = 0;
}
}
if(blockOffset == ncols - 1) {
for(i=0;i < colsPerThread; i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
if(blockOffset == 400 && rowStartPos < 330) {
if(rowStartPos + colsPerThread > 330) {
int end = 330 - rowStartPos;
for(i=0;i<end;i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
else {
for(i=0;i<colsPerThread;i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
}
if(blockOffset == 200 && rowStartPos <= 500 && rowStartPos + colsPerThread >=500) {
i=500-rowStartPos;
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
// Insert code to set the rest of the boundary and fixed positions
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InitArrays(float *ip, float *op, float *fp, int *kp, int ncols)
{
int i;
float *fppos, *oppos, *ippos;
int *kppos;
int blockOffset;
int rowStartPos;
int colsPerThread;
// Each block gets a row, each thread will fill part of a row
// Calculate the offset of the row
blockOffset = blockIdx.x * ncols;
// Calculate our offset into the row
rowStartPos = threadIdx.x * (ncols/blockDim.x);
// The number of cols per thread
colsPerThread = ncols/blockDim.x;
ippos = ip + blockOffset+ rowStartPos;
fppos = fp + blockOffset+ rowStartPos;
oppos = op + blockOffset+ rowStartPos;
kppos = kp + blockOffset+ rowStartPos;
for (i = 0; i < colsPerThread; i++) {
fppos[i] = NOTSETLOC; // Not Fixed
ippos[i] = 50;
oppos[i] = 50;
kppos[i] = 1; // Keep Going
}
if(rowStartPos == 0) {
fppos[0] = SETLOC;
ippos[0] = 0;
oppos[0] = 0;
kppos[0] = 0;
}
if(rowStartPos + colsPerThread >= ncols) {
fppos[colsPerThread-1] = SETLOC;
ippos[colsPerThread-1] = 0;
oppos[colsPerThread-1] = 0;
kppos[colsPerThread-1] = 0;
}
if(blockOffset == 0) {
for(i=0;i < colsPerThread; i++) {
fppos[i] = SETLOC;
ippos[i] = 0;
oppos[i] = 0;
kppos[i] = 0;
}
}
if(blockOffset == ncols - 1) {
for(i=0;i < colsPerThread; i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
if(blockOffset == 400 && rowStartPos < 330) {
if(rowStartPos + colsPerThread > 330) {
int end = 330 - rowStartPos;
for(i=0;i<end;i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
else {
for(i=0;i<colsPerThread;i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
}
if(blockOffset == 200 && rowStartPos <= 500 && rowStartPos + colsPerThread >=500) {
i=500-rowStartPos;
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
// Insert code to set the rest of the boundary and fixed positions
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10InitArraysPfS_S_Pii
.globl _Z10InitArraysPfS_S_Pii
.p2align 8
.type _Z10InitArraysPfS_S_Pii,@function
_Z10InitArraysPfS_S_Pii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s4, s[0:1], 0x20
s_load_b256 s[16:23], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v1, s2
s_sub_i32 s5, 0, s2
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_readfirstlane_b32 s3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s5, s3
s_mul_hi_u32 s5, s3, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s3, s3, s5
s_mul_hi_u32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s3, s2
s_add_i32 s1, s3, 1
s_sub_i32 s0, s4, s5
s_sub_i32 s5, s0, s2
s_cmp_ge_u32 s0, s2
s_cselect_b32 s1, s1, s3
s_cselect_b32 s0, s5, s0
s_add_i32 s3, s1, 1
s_cmp_ge_u32 s0, s2
s_mul_i32 s2, s15, s4
s_cselect_b32 s0, s3, s1
s_ashr_i32 s3, s2, 31
v_mul_lo_u32 v0, s0, v0
s_lshl_b64 s[6:7], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
s_add_u32 s1, s16, s6
s_addc_u32 s3, s17, s7
s_add_u32 s5, s20, s6
s_addc_u32 s8, s21, s7
s_add_u32 s9, s18, s6
v_ashrrev_i32_e32 v1, 31, v0
s_addc_u32 s10, s19, s7
s_add_u32 s6, s22, s6
s_addc_u32 s7, s23, s7
s_cmp_lt_i32 s0, 1
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v3, vcc_lo, s1, v1
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v7, vcc_lo, s5, v1
v_add_co_ci_u32_e32 v8, vcc_lo, s8, v2, vcc_lo
v_add_co_u32 v5, vcc_lo, s9, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s10, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_mov_b32 s1, 0
s_cbranch_scc1 .LBB0_3
s_delay_alu instid0(VALU_DEP_1)
v_dual_mov_b32 v19, 1 :: v_dual_mov_b32 v10, v2
v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v12, v6
v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v14, v4
v_dual_mov_b32 v13, v3 :: v_dual_mov_b32 v16, v8
v_dual_mov_b32 v17, -1.0 :: v_dual_mov_b32 v18, 0x42480000
v_mov_b32_e32 v15, v7
.p2align 6
.LBB0_2:
global_store_b32 v[15:16], v17, off
global_store_b32 v[13:14], v18, off
global_store_b32 v[11:12], v18, off
global_store_b32 v[9:10], v19, off
v_add_co_u32 v15, vcc_lo, v15, 4
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
v_add_co_u32 v13, vcc_lo, v13, 4
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s1, s0
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_mov_b32 s1, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_5
v_dual_mov_b32 v9, 1.0 :: v_dual_mov_b32 v10, 0
global_store_b32 v[7:8], v9, off
global_store_b32 v[3:4], v10, off
global_store_b32 v[5:6], v10, off
global_store_b32 v[1:2], v10, off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
v_add_nc_u32_e32 v17, s0, v0
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_le_i32_e64 s4, v17
s_cbranch_execz .LBB0_7
s_ashr_i32 s1, s0, 31
v_dual_mov_b32 v18, 1.0 :: v_dual_mov_b32 v19, 0
s_lshl_b64 s[6:7], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s1, s6, -4
s_addc_u32 s5, s7, -1
v_add_co_u32 v9, vcc_lo, v7, s1
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v8, vcc_lo
v_add_co_u32 v11, vcc_lo, v3, s1
v_add_co_ci_u32_e32 v12, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v13, vcc_lo, v5, s1
v_add_co_ci_u32_e32 v14, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v15, vcc_lo, v1, s1
v_add_co_ci_u32_e32 v16, vcc_lo, s5, v2, vcc_lo
global_store_b32 v[9:10], v18, off
global_store_b32 v[11:12], v19, off
global_store_b32 v[13:14], v19, off
global_store_b32 v[15:16], v19, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_cmp_lg_u32 s2, 0
s_cselect_b32 s1, -1, 0
s_cmp_lt_i32 s0, 1
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s1, s1, s3
s_and_b32 vcc_lo, exec_lo, s1
s_mov_b32 s1, 0
s_cbranch_vccnz .LBB0_10
v_dual_mov_b32 v18, 1.0 :: v_dual_mov_b32 v19, 0
v_dual_mov_b32 v10, v2 :: v_dual_mov_b32 v9, v1
v_dual_mov_b32 v12, v6 :: v_dual_mov_b32 v11, v5
v_dual_mov_b32 v14, v4 :: v_dual_mov_b32 v13, v3
v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
.p2align 6
.LBB0_9:
global_store_b32 v[15:16], v18, off
global_store_b32 v[13:14], v19, off
global_store_b32 v[11:12], v19, off
global_store_b32 v[9:10], v19, off
v_add_co_u32 v15, vcc_lo, v15, 4
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
v_add_co_u32 v13, vcc_lo, v13, 4
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s1, s0
s_cbranch_scc1 .LBB0_9
.LBB0_10:
s_add_i32 s4, s4, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s2, s4
s_cselect_b32 s1, -1, 0
s_cmp_lt_i32 s0, 1
s_cselect_b32 s3, -1, 0
s_or_b32 s1, s1, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_13
v_mov_b32_e32 v10, v2
v_mov_b32_e32 v12, v6
v_mov_b32_e32 v14, v4
v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
v_dual_mov_b32 v18, 1.0 :: v_dual_mov_b32 v19, 0x42c80000
v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v9, v1
v_mov_b32_e32 v11, v5
v_mov_b32_e32 v13, v3
s_mov_b32 s1, 0
.p2align 6
.LBB0_12:
global_store_b32 v[15:16], v18, off
global_store_b32 v[13:14], v19, off
global_store_b32 v[11:12], v19, off
global_store_b32 v[9:10], v20, off
v_add_co_u32 v15, vcc_lo, v15, 4
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
v_add_co_u32 v13, vcc_lo, v13, 4
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_add_i32 s1, s1, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s1, s0
s_cbranch_scc1 .LBB0_12
.LBB0_13:
v_cmp_gt_i32_e32 vcc_lo, 0x14a, v0
s_cmpk_eq_i32 s2, 0x190
s_cselect_b32 s1, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s1, vcc_lo
s_and_saveexec_b32 s1, s3
s_cbranch_execz .LBB0_22
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e32 0x14b, v17
s_xor_b32 s3, exec_lo, s3
s_cbranch_execz .LBB0_18
s_cmp_lt_i32 s0, 1
s_cbranch_scc1 .LBB0_18
v_mov_b32_e32 v10, v2
v_mov_b32_e32 v12, v6
v_mov_b32_e32 v14, v4
v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
v_dual_mov_b32 v18, 1.0 :: v_dual_mov_b32 v19, 0x42c80000
v_dual_mov_b32 v20, 0 :: v_dual_mov_b32 v9, v1
v_mov_b32_e32 v11, v5
v_mov_b32_e32 v13, v3
s_mov_b32 s4, 0
.p2align 6
.LBB0_17:
global_store_b32 v[15:16], v18, off
global_store_b32 v[13:14], v19, off
global_store_b32 v[11:12], v19, off
global_store_b32 v[9:10], v20, off
v_add_co_u32 v15, vcc_lo, v15, 4
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
v_add_co_u32 v13, vcc_lo, v13, 4
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_add_co_u32 v9, vcc_lo, v9, 4
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
s_add_i32 s4, s4, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s4, s0
s_cbranch_scc1 .LBB0_17
.LBB0_18:
s_and_not1_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_22
v_cmp_gt_i32_e32 vcc_lo, 0x14a, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_22
v_dual_mov_b32 v21, 0 :: v_dual_mov_b32 v10, v2
v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v12, v6
v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v14, v4
v_dual_mov_b32 v13, v3 :: v_dual_mov_b32 v16, v8
v_sub_nc_u32_e32 v18, 0x14a, v0
v_dual_mov_b32 v19, 1.0 :: v_dual_mov_b32 v20, 0x42c80000
v_mov_b32_e32 v15, v7
s_mov_b32 s3, 0
s_mov_b32 s4, 0
.p2align 6
.LBB0_21:
global_store_b32 v[15:16], v19, off
global_store_b32 v[13:14], v20, off
global_store_b32 v[11:12], v20, off
global_store_b32 v[9:10], v21, off
v_add_co_u32 v15, vcc_lo, v15, 4
v_add_co_ci_u32_e32 v16, vcc_lo, 0, v16, vcc_lo
v_add_co_u32 v13, vcc_lo, v13, 4
v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
v_add_co_u32 v11, vcc_lo, v11, 4
s_add_i32 s4, s4, 1
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v12, vcc_lo
v_cmp_ge_i32_e32 vcc_lo, s4, v18
v_add_co_u32 v9, s0, v9, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v10, s0, 0, v10, s0
s_or_b32 s3, vcc_lo, s3
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_21
.LBB0_22:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_i32_e32 vcc_lo, 0x1f5, v0
s_cmpk_eq_i32 s2, 0xc8
v_cmp_lt_i32_e64 s0, 0x1f3, v17
s_cselect_b32 s1, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s1, s1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_24
v_sub_nc_u32_e32 v9, 0x1f4, v0
v_dual_mov_b32 v11, 1.0 :: v_dual_mov_b32 v12, 0x42c80000
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, v7, v9
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v10, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, v9
v_add_co_ci_u32_e32 v4, vcc_lo, v4, v10, vcc_lo
v_add_co_u32 v5, vcc_lo, v5, v9
v_add_co_ci_u32_e32 v6, vcc_lo, v6, v10, vcc_lo
v_add_co_u32 v0, vcc_lo, v1, v9
v_add_co_ci_u32_e32 v1, vcc_lo, v2, v10, vcc_lo
v_mov_b32_e32 v2, 0
global_store_b32 v[7:8], v11, off
global_store_b32 v[3:4], v12, off
global_store_b32 v[5:6], v12, off
global_store_b32 v[0:1], v2, off
.LBB0_24:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10InitArraysPfS_S_Pii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 22
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10InitArraysPfS_S_Pii, .Lfunc_end0-_Z10InitArraysPfS_S_Pii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10InitArraysPfS_S_Pii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z10InitArraysPfS_S_Pii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 22
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void InitArrays(float *ip, float *op, float *fp, int *kp, int ncols)
{
int i;
float *fppos, *oppos, *ippos;
int *kppos;
int blockOffset;
int rowStartPos;
int colsPerThread;
// Each block gets a row, each thread will fill part of a row
// Calculate the offset of the row
blockOffset = blockIdx.x * ncols;
// Calculate our offset into the row
rowStartPos = threadIdx.x * (ncols/blockDim.x);
// The number of cols per thread
colsPerThread = ncols/blockDim.x;
ippos = ip + blockOffset+ rowStartPos;
fppos = fp + blockOffset+ rowStartPos;
oppos = op + blockOffset+ rowStartPos;
kppos = kp + blockOffset+ rowStartPos;
for (i = 0; i < colsPerThread; i++) {
fppos[i] = NOTSETLOC; // Not Fixed
ippos[i] = 50;
oppos[i] = 50;
kppos[i] = 1; // Keep Going
}
if(rowStartPos == 0) {
fppos[0] = SETLOC;
ippos[0] = 0;
oppos[0] = 0;
kppos[0] = 0;
}
if(rowStartPos + colsPerThread >= ncols) {
fppos[colsPerThread-1] = SETLOC;
ippos[colsPerThread-1] = 0;
oppos[colsPerThread-1] = 0;
kppos[colsPerThread-1] = 0;
}
if(blockOffset == 0) {
for(i=0;i < colsPerThread; i++) {
fppos[i] = SETLOC;
ippos[i] = 0;
oppos[i] = 0;
kppos[i] = 0;
}
}
if(blockOffset == ncols - 1) {
for(i=0;i < colsPerThread; i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
if(blockOffset == 400 && rowStartPos < 330) {
if(rowStartPos + colsPerThread > 330) {
int end = 330 - rowStartPos;
for(i=0;i<end;i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
else {
for(i=0;i<colsPerThread;i++) {
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
}
}
if(blockOffset == 200 && rowStartPos <= 500 && rowStartPos + colsPerThread >=500) {
i=500-rowStartPos;
fppos[i] = SETLOC;
ippos[i] = 100;
oppos[i] = 100;
kppos[i] = 0;
}
// Insert code to set the rest of the boundary and fixed positions
} | .text
.file "InitArrays.hip"
.globl _Z25__device_stub__InitArraysPfS_S_Pii # -- Begin function _Z25__device_stub__InitArraysPfS_S_Pii
.p2align 4, 0x90
.type _Z25__device_stub__InitArraysPfS_S_Pii,@function
_Z25__device_stub__InitArraysPfS_S_Pii: # @_Z25__device_stub__InitArraysPfS_S_Pii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10InitArraysPfS_S_Pii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z25__device_stub__InitArraysPfS_S_Pii, .Lfunc_end0-_Z25__device_stub__InitArraysPfS_S_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10InitArraysPfS_S_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10InitArraysPfS_S_Pii,@object # @_Z10InitArraysPfS_S_Pii
.section .rodata,"a",@progbits
.globl _Z10InitArraysPfS_S_Pii
.p2align 3, 0x0
_Z10InitArraysPfS_S_Pii:
.quad _Z25__device_stub__InitArraysPfS_S_Pii
.size _Z10InitArraysPfS_S_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10InitArraysPfS_S_Pii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__InitArraysPfS_S_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10InitArraysPfS_S_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012669b_00000000-6_InitArrays.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii
.type _Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii, @function
_Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 184
pushq 56(%rsp)
.cfi_def_cfa_offset 192
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10InitArraysPfS_S_Pii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii, .-_Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii
.globl _Z10InitArraysPfS_S_Pii
.type _Z10InitArraysPfS_S_Pii, @function
_Z10InitArraysPfS_S_Pii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10InitArraysPfS_S_PiiPfS_S_Pii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10InitArraysPfS_S_Pii, .-_Z10InitArraysPfS_S_Pii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10InitArraysPfS_S_Pii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10InitArraysPfS_S_Pii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "InitArrays.hip"
.globl _Z25__device_stub__InitArraysPfS_S_Pii # -- Begin function _Z25__device_stub__InitArraysPfS_S_Pii
.p2align 4, 0x90
.type _Z25__device_stub__InitArraysPfS_S_Pii,@function
_Z25__device_stub__InitArraysPfS_S_Pii: # @_Z25__device_stub__InitArraysPfS_S_Pii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10InitArraysPfS_S_Pii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z25__device_stub__InitArraysPfS_S_Pii, .Lfunc_end0-_Z25__device_stub__InitArraysPfS_S_Pii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10InitArraysPfS_S_Pii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10InitArraysPfS_S_Pii,@object # @_Z10InitArraysPfS_S_Pii
.section .rodata,"a",@progbits
.globl _Z10InitArraysPfS_S_Pii
.p2align 3, 0x0
_Z10InitArraysPfS_S_Pii:
.quad _Z25__device_stub__InitArraysPfS_S_Pii
.size _Z10InitArraysPfS_S_Pii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10InitArraysPfS_S_Pii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__InitArraysPfS_S_Pii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10InitArraysPfS_S_Pii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void octal(int *a,int *b)
{
int tid = threadIdx.x;
long int rem[50],i=0,length=0,x=0;
int num=a[tid];
while(num>7)
{
rem[i]=num%8;
num=num/8;
i++;
length++;
}
for(i=length-1;i>=0;i--)
{
x=x+(rem[i]*(10*i));
}
b[tid]=x;
}
int main(void)
{
int i,a[10000],b[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
int *d_a,*d_b;
int size = sizeof(int);
cudaMalloc((void **)&d_a,size*n);
cudaMalloc((void **)&d_b,size*n);
cudaMemcpy(d_a,a,size*n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size*n,cudaMemcpyHostToDevice);
octal<<<1,n>>>(d_a,d_b);
cudaMemcpy(b,d_b,size*n,cudaMemcpyDeviceToHost);
printf("Octal array is :");
for(i=0;i<n;i++)
{
printf("%d\t",b[i]);
}
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | code for sm_80
Function : _Z5octalPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x190, RZ ; /* 0xfffffe7001017810 */
/* 0x000fe40007ffe0ff */
/*0050*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fca00078e0203 */
/*0060*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea2000c1e1900 */
/*0070*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0080*/ BSSY B0, 0x500 ; /* 0x0000047000007945 */
/* 0x000fe20003800000 */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe40000011406 */
/*00b0*/ ISETP.GE.AND P0, PT, R4, 0x8, PT ; /* 0x000000080400780c */
/* 0x004fda0003f06270 */
/*00c0*/ @!P0 BRA 0x4f0 ; /* 0x0000042000008947 */
/* 0x000fea0003800000 */
/*00d0*/ LOP3.LUT R2, R4.reuse, 0x7, RZ, 0xc0, !PT ; /* 0x0000000704027812 */
/* 0x040fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R4, 0x40, PT ; /* 0x000000400400780c */
/* 0x000fe20003f06070 */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fc600078e00ff */
/*0110*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001f20000100a00 */
/*0120*/ @!P0 BRA 0x4f0 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*0130*/ SHF.R.U32.HI R2, RZ, 0x3, R4 ; /* 0x00000003ff027819 */
/* 0x001fe20000011604 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R4, 0x200, PT ; /* 0x000002000400780c */
/* 0x000fe20003f06070 */
/*0160*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; /* 0x00000002ff007424 */
/* 0x000fe200078e00ff */
/*0170*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*0180*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001ec0000100a00 */
/*0190*/ @!P0 BRA 0x4f0 ; /* 0x0000035000008947 */
/* 0x000fea0003800000 */
/*01a0*/ SHF.R.U32.HI R2, RZ, 0x6, R4 ; /* 0x00000006ff027819 */
/* 0x001fe20000011604 */
/*01b0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x1000, PT ; /* 0x000010000400780c */
/* 0x000fe20003f06070 */
/*01d0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3 ; /* 0x00000003ff007424 */
/* 0x000fe200078e00ff */
/*01e0*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*01f0*/ STL.64 [R1+0x10], R2 ; /* 0x0000100201007387 */
/* 0x0001ec0000100a00 */
/*0200*/ @!P0 BRA 0x4f0 ; /* 0x000002e000008947 */
/* 0x000fea0003800000 */
/*0210*/ SHF.R.U32.HI R2, RZ, 0x9, R4 ; /* 0x00000009ff027819 */
/* 0x001fe20000011604 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0230*/ ISETP.GE.U32.AND P0, PT, R4, 0x8000, PT ; /* 0x000080000400780c */
/* 0x000fe20003f06070 */
/*0240*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0250*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*0260*/ STL.64 [R1+0x18], R2 ; /* 0x0000180201007387 */
/* 0x0001ec0000100a00 */
/*0270*/ @!P0 BRA 0x4f0 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*0280*/ SHF.R.U32.HI R2, RZ, 0xc, R4 ; /* 0x0000000cff027819 */
/* 0x001fe20000011604 */
/*0290*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x40000, PT ; /* 0x000400000400780c */
/* 0x000fe20003f06070 */
/*02b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x5 ; /* 0x00000005ff007424 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*02d0*/ STL.64 [R1+0x20], R2 ; /* 0x0000200201007387 */
/* 0x0001ec0000100a00 */
/*02e0*/ @!P0 BRA 0x4f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*02f0*/ SHF.R.U32.HI R2, RZ, 0xf, R4 ; /* 0x0000000fff027819 */
/* 0x001fe20000011604 */
/*0300*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0310*/ ISETP.GE.U32.AND P0, PT, R4, 0x200000, PT ; /* 0x002000000400780c */
/* 0x000fe20003f06070 */
/*0320*/ IMAD.MOV.U32 R0, RZ, RZ, 0x6 ; /* 0x00000006ff007424 */
/* 0x000fe200078e00ff */
/*0330*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*0340*/ STL.64 [R1+0x28], R2 ; /* 0x0000280201007387 */
/* 0x0001ec0000100a00 */
/*0350*/ @!P0 BRA 0x4f0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0360*/ SHF.R.U32.HI R2, RZ, 0x12, R4 ; /* 0x00000012ff027819 */
/* 0x001fe20000011604 */
/*0370*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0380*/ ISETP.GE.U32.AND P0, PT, R4, 0x1000000, PT ; /* 0x010000000400780c */
/* 0x000fe20003f06070 */
/*0390*/ IMAD.MOV.U32 R0, RZ, RZ, 0x7 ; /* 0x00000007ff007424 */
/* 0x000fe200078e00ff */
/*03a0*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*03b0*/ STL.64 [R1+0x30], R2 ; /* 0x0000300201007387 */
/* 0x0001ec0000100a00 */
/*03c0*/ @!P0 BRA 0x4f0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*03d0*/ SHF.R.U32.HI R2, RZ, 0x15, R4 ; /* 0x00000015ff027819 */
/* 0x001fe20000011604 */
/*03e0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*03f0*/ ISETP.GE.U32.AND P0, PT, R4, 0x8000000, PT ; /* 0x080000000400780c */
/* 0x000fe20003f06070 */
/*0400*/ IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; /* 0x00000008ff007424 */
/* 0x000fe200078e00ff */
/*0410*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*0420*/ STL.64 [R1+0x38], R2 ; /* 0x0000380201007387 */
/* 0x0001ec0000100a00 */
/*0430*/ @!P0 BRA 0x4f0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R4, 0x40000000, PT ; /* 0x400000000400780c */
/* 0x000fe20003f06070 */
/*0450*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x001fe200078e00ff */
/*0460*/ SHF.R.U32.HI R2, RZ, 0x18, R4 ; /* 0x00000018ff027819 */
/* 0x000fe20000011604 */
/*0470*/ IMAD.MOV.U32 R0, RZ, RZ, 0x9 ; /* 0x00000009ff007424 */
/* 0x000fc600078e00ff */
/*0480*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*0490*/ STL.64 [R1+0x40], R2 ; /* 0x0000400201007387 */
/* 0x0001e40000100a00 */
/*04a0*/ @P0 SHF.R.U32.HI R4, RZ, 0x1b, R4 ; /* 0x0000001bff040819 */
/* 0x000fe20000011604 */
/*04b0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe400078e00ff */
/*04c0*/ @P0 IMAD.MOV.U32 R0, RZ, RZ, 0xa ; /* 0x0000000aff000424 */
/* 0x000fe200078e00ff */
/*04d0*/ @P0 LOP3.LUT R4, R4, 0x7, RZ, 0xc0, !PT ; /* 0x0000000704040812 */
/* 0x000fca00078ec0ff */
/*04e0*/ @P0 STL.64 [R1+0x48], R4 ; /* 0x0000480401000387 */
/* 0x0001e40000100a00 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0510*/ BSSY B0, 0x960 ; /* 0x0000044000007945 */
/* 0x000fe20003800000 */
/*0520*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x001fe400078e00ff */
/*0530*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05300 */
/*0540*/ @!P0 BRA 0x950 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD.U32 R4, R0, 0x8, R1 ; /* 0x0000000800047824 */
/* 0x000fca00078e0001 */
/*0560*/ LDL R2, [R4+-0x8] ; /* 0xfffff80004027983 */
/* 0x000ea20000100800 */
/*0570*/ ISETP.NE.U32.AND P0, PT, R0.reuse, 0x1, PT ; /* 0x000000010000780c */
/* 0x040fe20003f05070 */
/*0580*/ IMAD.MOV.U32 R3, RZ, RZ, 0xa ; /* 0x0000000aff037424 */
/* 0x000fe200078e00ff */
/*0590*/ BSSY B1, 0x950 ; /* 0x000003b000017945 */
/* 0x000fe40003800000 */
/*05a0*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05300 */
/*05b0*/ IMAD R9, R0, R3, c[0x2][0x0] ; /* 0x0080000000097624 */
/* 0x000fc800078e0203 */
/*05c0*/ IMAD R5, R9, R2, RZ ; /* 0x0000000209057224 */
/* 0x004fd000078e02ff */
/*05d0*/ @!P0 BRA 0x940 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*05e0*/ LDL R2, [R4+-0x10] ; /* 0xfffff00004027983 */
/* 0x000ea20000100800 */
/*05f0*/ ISETP.NE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe40003f05070 */
/*0600*/ IADD3 R3, R9, -0xa, RZ ; /* 0xfffffff609037810 */
/* 0x000fe40007ffe0ff */
/*0610*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05300 */
/*0620*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fd400078e0205 */
/*0630*/ @!P0 BRA 0x940 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*0640*/ LDL R2, [R4+-0x18] ; /* 0xffffe80004027983 */
/* 0x000ea20000100800 */
/*0650*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fe2000f8e00ff */
/*0660*/ ISETP.GE.U32.AND P0, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fc80003f06070 */
/*0670*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*0680*/ IADD3 R3, R9, -0x14, RZ ; /* 0xffffffec09037810 */
/* 0x000fca0007ffe0ff */
/*0690*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fcc00078e0205 */
/*06a0*/ @!P0 BRA 0x940 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*06b0*/ LDL R2, [R4+-0x20] ; /* 0xffffe00004027983 */
/* 0x000ea20000100800 */
/*06c0*/ ISETP.NE.U32.AND P0, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fe40003f05070 */
/*06d0*/ IADD3 R3, R9, -0x1e, RZ ; /* 0xffffffe209037810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05300 */
/*06f0*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fd400078e0205 */
/*0700*/ @!P0 BRA 0x940 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0710*/ LDL R2, [R4+-0x28] ; /* 0xffffd80004027983 */
/* 0x000ea20000100800 */
/*0720*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fe2000f8e00ff */
/*0730*/ ISETP.GE.U32.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x000fc80003f06070 */
/*0740*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*0750*/ IADD3 R3, R9, -0x28, RZ ; /* 0xffffffd809037810 */
/* 0x000fca0007ffe0ff */
/*0760*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fcc00078e0205 */
/*0770*/ @!P0 BRA 0x940 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0780*/ LDL R2, [R4+-0x30] ; /* 0xffffd00004027983 */
/* 0x000ea20000100800 */
/*0790*/ ISETP.NE.U32.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x000fe40003f05070 */
/*07a0*/ IADD3 R3, R9, -0x32, RZ ; /* 0xffffffce09037810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05300 */
/*07c0*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fd400078e0205 */
/*07d0*/ @!P0 BRA 0x940 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*07e0*/ LDL R2, [R4+-0x38] ; /* 0xffffc80004027983 */
/* 0x000ea20000100800 */
/*07f0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fe2000f8e00ff */
/*0800*/ ISETP.GE.U32.AND P0, PT, R0, 0x8, PT ; /* 0x000000080000780c */
/* 0x000fc80003f06070 */
/*0810*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*0820*/ IADD3 R3, R9, -0x3c, RZ ; /* 0xffffffc409037810 */
/* 0x000fca0007ffe0ff */
/*0830*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fcc00078e0205 */
/*0840*/ @!P0 BRA 0x940 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0850*/ LDL R2, [R4+-0x40] ; /* 0xffffc00004027983 */
/* 0x000ea20000100800 */
/*0860*/ ISETP.NE.U32.AND P0, PT, R0, 0x8, PT ; /* 0x000000080000780c */
/* 0x000fe40003f05070 */
/*0870*/ IADD3 R3, R9, -0x46, RZ ; /* 0xffffffba09037810 */
/* 0x000fe40007ffe0ff */
/*0880*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05300 */
/*0890*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fd400078e0205 */
/*08a0*/ @!P0 BRA 0x940 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*08b0*/ ISETP.GE.U32.AND P0, PT, R0, 0xa, PT ; /* 0x0000000a0000780c */
/* 0x000fe20003f06070 */
/*08c0*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fca000f8e00ff */
/*08d0*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe40003f06100 */
/*08e0*/ LDL R0, [R4+-0x48] ; /* 0xffffb80004007983 */
/* 0x000eb60000100800 */
/*08f0*/ @P0 LDL R2, [R4+-0x50] ; /* 0xffffb00004020983 */
/* 0x000ee20000100800 */
/*0900*/ IADD3 R3, R9, -0x50, RZ ; /* 0xffffffb009037810 */
/* 0x000fca0007ffe0ff */
/*0910*/ IMAD R5, R0, R3, R5 ; /* 0x0000000300057224 */
/* 0x004fe200078e0205 */
/*0920*/ @P0 IADD3 R3, R9, -0x5a, RZ ; /* 0xffffffa609030810 */
/* 0x000fca0007ffe0ff */
/*0930*/ @P0 IMAD R5, R2, R3, R5 ; /* 0x0000000302050224 */
/* 0x008fe400078e0205 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0960*/ LEA R2, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006027a11 */
/* 0x000fc800078010ff */
/*0970*/ LEA.HI.X R3, R6, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b0006037a11 */
/* 0x000fca00000f1407 */
/*0980*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0990*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09a0*/ BRA 0x9a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void octal(int *a,int *b)
{
int tid = threadIdx.x;
long int rem[50],i=0,length=0,x=0;
int num=a[tid];
while(num>7)
{
rem[i]=num%8;
num=num/8;
i++;
length++;
}
for(i=length-1;i>=0;i--)
{
x=x+(rem[i]*(10*i));
}
b[tid]=x;
}
int main(void)
{
int i,a[10000],b[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
int *d_a,*d_b;
int size = sizeof(int);
cudaMalloc((void **)&d_a,size*n);
cudaMalloc((void **)&d_b,size*n);
cudaMemcpy(d_a,a,size*n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size*n,cudaMemcpyHostToDevice);
octal<<<1,n>>>(d_a,d_b);
cudaMemcpy(b,d_b,size*n,cudaMemcpyDeviceToHost);
printf("Octal array is :");
for(i=0;i<n;i++)
{
printf("%d\t",b[i]);
}
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | .file "tmpxft_00163bd2_00000000-6_octal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5octalPiS_PiS_
.type _Z26__device_stub__Z5octalPiS_PiS_, @function
_Z26__device_stub__Z5octalPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5octalPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5octalPiS_PiS_, .-_Z26__device_stub__Z5octalPiS_PiS_
.globl _Z5octalPiS_
.type _Z5octalPiS_, @function
_Z5octalPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5octalPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5octalPiS_, .-_Z5octalPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter value of N:"
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Enter array elements of array A\n"
.section .rodata.str1.1
.LC3:
.string "Octal array is :"
.LC4:
.string "%d\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -77824(%rsp), %r11
.cfi_def_cfa 11, 77856
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2240, %rsp
.cfi_def_cfa_offset 80096
movq %fs:40, %rax
movq %rax, 80056(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %esi
testl %esi, %esi
jle .L12
leaq 48(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L13:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 4(%rsp), %esi
addq $4, %rbp
cmpl %ebx, %esi
jg .L13
.L12:
sall $2, %esi
movslq %esi, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 48(%rsp), %rsi
movl $1, %ecx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 40048(%rsp), %rsi
movl $1, %ecx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl 4(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 40048(%rsp), %rdi
movl $2, %ecx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
jle .L15
movl $0, %ebx
leaq .LC4(%rip), %rbp
.L16:
movl 40048(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L16
.L15:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 80056(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5octalPiS_PiS_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z5octalPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5octalPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
__global__ void octal(int *a,int *b)
{
int tid = threadIdx.x;
long int rem[50],i=0,length=0,x=0;
int num=a[tid];
while(num>7)
{
rem[i]=num%8;
num=num/8;
i++;
length++;
}
for(i=length-1;i>=0;i--)
{
x=x+(rem[i]*(10*i));
}
b[tid]=x;
}
int main(void)
{
int i,a[10000],b[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
int *d_a,*d_b;
int size = sizeof(int);
cudaMalloc((void **)&d_a,size*n);
cudaMalloc((void **)&d_b,size*n);
cudaMemcpy(d_a,a,size*n,cudaMemcpyHostToDevice);
cudaMemcpy(d_b,b,size*n,cudaMemcpyHostToDevice);
octal<<<1,n>>>(d_a,d_b);
cudaMemcpy(b,d_b,size*n,cudaMemcpyDeviceToHost);
printf("Octal array is :");
for(i=0;i<n;i++)
{
printf("%d\t",b[i]);
}
cudaFree(d_a);
cudaFree(d_b);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void octal(int *a,int *b)
{
int tid = threadIdx.x;
long int rem[50],i=0,length=0,x=0;
int num=a[tid];
while(num>7)
{
rem[i]=num%8;
num=num/8;
i++;
length++;
}
for(i=length-1;i>=0;i--)
{
x=x+(rem[i]*(10*i));
}
b[tid]=x;
}
int main(void)
{
int i,a[10000],b[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
int *d_a,*d_b;
int size = sizeof(int);
hipMalloc((void **)&d_a,size*n);
hipMalloc((void **)&d_b,size*n);
hipMemcpy(d_a,a,size*n,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size*n,hipMemcpyHostToDevice);
octal<<<1,n>>>(d_a,d_b);
hipMemcpy(b,d_b,size*n,hipMemcpyDeviceToHost);
printf("Octal array is :");
for(i=0;i<n;i++)
{
printf("%d\t",b[i]);
}
hipFree(d_a);
hipFree(d_b);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void octal(int *a,int *b)
{
int tid = threadIdx.x;
long int rem[50],i=0,length=0,x=0;
int num=a[tid];
while(num>7)
{
rem[i]=num%8;
num=num/8;
i++;
length++;
}
for(i=length-1;i>=0;i--)
{
x=x+(rem[i]*(10*i));
}
b[tid]=x;
}
int main(void)
{
int i,a[10000],b[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
int *d_a,*d_b;
int size = sizeof(int);
hipMalloc((void **)&d_a,size*n);
hipMalloc((void **)&d_b,size*n);
hipMemcpy(d_a,a,size*n,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size*n,hipMemcpyHostToDevice);
octal<<<1,n>>>(d_a,d_b);
hipMemcpy(b,d_b,size*n,hipMemcpyDeviceToHost);
printf("Octal array is :");
for(i=0;i<n;i++)
{
printf("%d\t",b[i]);
}
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5octalPiS_
.globl _Z5octalPiS_
.p2align 8
.type _Z5octalPiS_,@function
_Z5octalPiS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v1, s[2:3]
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 7, v5
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v6, 16
s_mov_b64 s[2:3], 0
s_mov_b32 s5, 0
.LBB0_2:
s_add_u32 s2, s2, 1
v_lshrrev_b32_e32 v7, 3, v5
s_addc_u32 s3, s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v4, s3 :: v_dual_and_b32 v1, 7, v5
v_cmp_gt_u32_e32 vcc_lo, 64, v5
v_mov_b32_e32 v3, s2
v_mov_b32_e32 v5, v7
scratch_store_b64 v6, v[1:2], off
v_add_nc_u32_e32 v6, 8, v6
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v5, 0
s_mov_b32 s3, exec_lo
v_cmpx_lt_i64_e32 0, v[3:4]
s_cbranch_execz .LBB0_8
v_mad_u64_u32 v[1:2], null, v3, 10, -10
s_mov_b32 s4, 0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, v4, 10, v[2:3]
v_lshlrev_b32_e32 v6, 3, v3
v_add_co_u32 v2, vcc_lo, v3, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
v_add3_u32 v4, v6, 16, -8
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, v5
.p2align 6
.LBB0_6:
scratch_load_b64 v[10:11], v4, off
v_add_co_u32 v2, vcc_lo, v2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, -1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, 2, v[2:3]
s_or_b32 s4, vcc_lo, s4
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v1, v10, v[7:8]
v_mul_lo_u32 v7, v1, v11
v_mul_lo_u32 v8, v9, v10
v_add_co_u32 v1, s2, v1, -10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v9, s2, -1, v9, s2
v_add3_u32 v6, v8, v6, v7
v_add_nc_u32_e32 v4, -8, v4
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s4
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v5, s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5octalPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 416
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5octalPiS_, .Lfunc_end0-_Z5octalPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5octalPiS_
.private_segment_fixed_size: 416
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z5octalPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
__global__ void octal(int *a,int *b)
{
int tid = threadIdx.x;
long int rem[50],i=0,length=0,x=0;
int num=a[tid];
while(num>7)
{
rem[i]=num%8;
num=num/8;
i++;
length++;
}
for(i=length-1;i>=0;i--)
{
x=x+(rem[i]*(10*i));
}
b[tid]=x;
}
int main(void)
{
int i,a[10000],b[10000],n;
printf("Enter value of N:");
scanf("%d",&n);
printf("Enter array elements of array A\n");
for(i=0;i<n;i++)
scanf("%d",&a[i]);
int *d_a,*d_b;
int size = sizeof(int);
hipMalloc((void **)&d_a,size*n);
hipMalloc((void **)&d_b,size*n);
hipMemcpy(d_a,a,size*n,hipMemcpyHostToDevice);
hipMemcpy(d_b,b,size*n,hipMemcpyHostToDevice);
octal<<<1,n>>>(d_a,d_b);
hipMemcpy(b,d_b,size*n,hipMemcpyDeviceToHost);
printf("Octal array is :");
for(i=0;i<n;i++)
{
printf("%d\t",b[i]);
}
hipFree(d_a);
hipFree(d_b);
return 0;
} | .text
.file "octal.hip"
.globl _Z20__device_stub__octalPiS_ # -- Begin function _Z20__device_stub__octalPiS_
.p2align 4, 0x90
.type _Z20__device_stub__octalPiS_,@function
_Z20__device_stub__octalPiS_: # @_Z20__device_stub__octalPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5octalPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__octalPiS_, .Lfunc_end0-_Z20__device_stub__octalPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $80120, %rsp # imm = 0x138F8
.cfi_def_cfa_offset 80144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 40112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
shll $2, %eax
movslq %eax, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 40112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5octalPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 112(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB1_8
# %bb.6: # %.lr.ph19.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # %.lr.ph19
# =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_7
.LBB1_8: # %._crit_edge20
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80120, %rsp # imm = 0x138F8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5octalPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5octalPiS_,@object # @_Z5octalPiS_
.section .rodata,"a",@progbits
.globl _Z5octalPiS_
.p2align 3, 0x0
_Z5octalPiS_:
.quad _Z20__device_stub__octalPiS_
.size _Z5octalPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter value of N:"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Octal array is :"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d\t"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5octalPiS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter array elements of array A"
.size .Lstr, 32
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__octalPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5octalPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5octalPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x190, RZ ; /* 0xfffffe7001017810 */
/* 0x000fe40007ffe0ff */
/*0050*/ IMAD.WIDE R2, R6, R3, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fca00078e0203 */
/*0060*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x000ea2000c1e1900 */
/*0070*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0080*/ BSSY B0, 0x500 ; /* 0x0000047000007945 */
/* 0x000fe20003800000 */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.S32.HI R7, RZ, 0x1f, R6 ; /* 0x0000001fff077819 */
/* 0x000fe40000011406 */
/*00b0*/ ISETP.GE.AND P0, PT, R4, 0x8, PT ; /* 0x000000080400780c */
/* 0x004fda0003f06270 */
/*00c0*/ @!P0 BRA 0x4f0 ; /* 0x0000042000008947 */
/* 0x000fea0003800000 */
/*00d0*/ LOP3.LUT R2, R4.reuse, 0x7, RZ, 0xc0, !PT ; /* 0x0000000704027812 */
/* 0x040fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R4, 0x40, PT ; /* 0x000000400400780c */
/* 0x000fe20003f06070 */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fc600078e00ff */
/*0110*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001f20000100a00 */
/*0120*/ @!P0 BRA 0x4f0 ; /* 0x000003c000008947 */
/* 0x000fea0003800000 */
/*0130*/ SHF.R.U32.HI R2, RZ, 0x3, R4 ; /* 0x00000003ff027819 */
/* 0x001fe20000011604 */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0150*/ ISETP.GE.U32.AND P0, PT, R4, 0x200, PT ; /* 0x000002000400780c */
/* 0x000fe20003f06070 */
/*0160*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; /* 0x00000002ff007424 */
/* 0x000fe200078e00ff */
/*0170*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*0180*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001ec0000100a00 */
/*0190*/ @!P0 BRA 0x4f0 ; /* 0x0000035000008947 */
/* 0x000fea0003800000 */
/*01a0*/ SHF.R.U32.HI R2, RZ, 0x6, R4 ; /* 0x00000006ff027819 */
/* 0x001fe20000011604 */
/*01b0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*01c0*/ ISETP.GE.U32.AND P0, PT, R4, 0x1000, PT ; /* 0x000010000400780c */
/* 0x000fe20003f06070 */
/*01d0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x3 ; /* 0x00000003ff007424 */
/* 0x000fe200078e00ff */
/*01e0*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*01f0*/ STL.64 [R1+0x10], R2 ; /* 0x0000100201007387 */
/* 0x0001ec0000100a00 */
/*0200*/ @!P0 BRA 0x4f0 ; /* 0x000002e000008947 */
/* 0x000fea0003800000 */
/*0210*/ SHF.R.U32.HI R2, RZ, 0x9, R4 ; /* 0x00000009ff027819 */
/* 0x001fe20000011604 */
/*0220*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0230*/ ISETP.GE.U32.AND P0, PT, R4, 0x8000, PT ; /* 0x000080000400780c */
/* 0x000fe20003f06070 */
/*0240*/ IMAD.MOV.U32 R0, RZ, RZ, 0x4 ; /* 0x00000004ff007424 */
/* 0x000fe200078e00ff */
/*0250*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*0260*/ STL.64 [R1+0x18], R2 ; /* 0x0000180201007387 */
/* 0x0001ec0000100a00 */
/*0270*/ @!P0 BRA 0x4f0 ; /* 0x0000027000008947 */
/* 0x000fea0003800000 */
/*0280*/ SHF.R.U32.HI R2, RZ, 0xc, R4 ; /* 0x0000000cff027819 */
/* 0x001fe20000011604 */
/*0290*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*02a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x40000, PT ; /* 0x000400000400780c */
/* 0x000fe20003f06070 */
/*02b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x5 ; /* 0x00000005ff007424 */
/* 0x000fe200078e00ff */
/*02c0*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*02d0*/ STL.64 [R1+0x20], R2 ; /* 0x0000200201007387 */
/* 0x0001ec0000100a00 */
/*02e0*/ @!P0 BRA 0x4f0 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*02f0*/ SHF.R.U32.HI R2, RZ, 0xf, R4 ; /* 0x0000000fff027819 */
/* 0x001fe20000011604 */
/*0300*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0310*/ ISETP.GE.U32.AND P0, PT, R4, 0x200000, PT ; /* 0x002000000400780c */
/* 0x000fe20003f06070 */
/*0320*/ IMAD.MOV.U32 R0, RZ, RZ, 0x6 ; /* 0x00000006ff007424 */
/* 0x000fe200078e00ff */
/*0330*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*0340*/ STL.64 [R1+0x28], R2 ; /* 0x0000280201007387 */
/* 0x0001ec0000100a00 */
/*0350*/ @!P0 BRA 0x4f0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0360*/ SHF.R.U32.HI R2, RZ, 0x12, R4 ; /* 0x00000012ff027819 */
/* 0x001fe20000011604 */
/*0370*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*0380*/ ISETP.GE.U32.AND P0, PT, R4, 0x1000000, PT ; /* 0x010000000400780c */
/* 0x000fe20003f06070 */
/*0390*/ IMAD.MOV.U32 R0, RZ, RZ, 0x7 ; /* 0x00000007ff007424 */
/* 0x000fe200078e00ff */
/*03a0*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*03b0*/ STL.64 [R1+0x30], R2 ; /* 0x0000300201007387 */
/* 0x0001ec0000100a00 */
/*03c0*/ @!P0 BRA 0x4f0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*03d0*/ SHF.R.U32.HI R2, RZ, 0x15, R4 ; /* 0x00000015ff027819 */
/* 0x001fe20000011604 */
/*03e0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*03f0*/ ISETP.GE.U32.AND P0, PT, R4, 0x8000000, PT ; /* 0x080000000400780c */
/* 0x000fe20003f06070 */
/*0400*/ IMAD.MOV.U32 R0, RZ, RZ, 0x8 ; /* 0x00000008ff007424 */
/* 0x000fe200078e00ff */
/*0410*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*0420*/ STL.64 [R1+0x38], R2 ; /* 0x0000380201007387 */
/* 0x0001ec0000100a00 */
/*0430*/ @!P0 BRA 0x4f0 ; /* 0x000000b000008947 */
/* 0x000fea0003800000 */
/*0440*/ ISETP.GE.U32.AND P0, PT, R4, 0x40000000, PT ; /* 0x400000000400780c */
/* 0x000fe20003f06070 */
/*0450*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x001fe200078e00ff */
/*0460*/ SHF.R.U32.HI R2, RZ, 0x18, R4 ; /* 0x00000018ff027819 */
/* 0x000fe20000011604 */
/*0470*/ IMAD.MOV.U32 R0, RZ, RZ, 0x9 ; /* 0x00000009ff007424 */
/* 0x000fc600078e00ff */
/*0480*/ LOP3.LUT R2, R2, 0x7, RZ, 0xc0, !PT ; /* 0x0000000702027812 */
/* 0x000fca00078ec0ff */
/*0490*/ STL.64 [R1+0x40], R2 ; /* 0x0000400201007387 */
/* 0x0001e40000100a00 */
/*04a0*/ @P0 SHF.R.U32.HI R4, RZ, 0x1b, R4 ; /* 0x0000001bff040819 */
/* 0x000fe20000011604 */
/*04b0*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff050224 */
/* 0x000fe400078e00ff */
/*04c0*/ @P0 IMAD.MOV.U32 R0, RZ, RZ, 0xa ; /* 0x0000000aff000424 */
/* 0x000fe200078e00ff */
/*04d0*/ @P0 LOP3.LUT R4, R4, 0x7, RZ, 0xc0, !PT ; /* 0x0000000704040812 */
/* 0x000fca00078ec0ff */
/*04e0*/ @P0 STL.64 [R1+0x48], R4 ; /* 0x0000480401000387 */
/* 0x0001e40000100a00 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0510*/ BSSY B0, 0x960 ; /* 0x0000044000007945 */
/* 0x000fe20003800000 */
/*0520*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x001fe400078e00ff */
/*0530*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda000bf05300 */
/*0540*/ @!P0 BRA 0x950 ; /* 0x0000040000008947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD.U32 R4, R0, 0x8, R1 ; /* 0x0000000800047824 */
/* 0x000fca00078e0001 */
/*0560*/ LDL R2, [R4+-0x8] ; /* 0xfffff80004027983 */
/* 0x000ea20000100800 */
/*0570*/ ISETP.NE.U32.AND P0, PT, R0.reuse, 0x1, PT ; /* 0x000000010000780c */
/* 0x040fe20003f05070 */
/*0580*/ IMAD.MOV.U32 R3, RZ, RZ, 0xa ; /* 0x0000000aff037424 */
/* 0x000fe200078e00ff */
/*0590*/ BSSY B1, 0x950 ; /* 0x000003b000017945 */
/* 0x000fe40003800000 */
/*05a0*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05300 */
/*05b0*/ IMAD R9, R0, R3, c[0x2][0x0] ; /* 0x0080000000097624 */
/* 0x000fc800078e0203 */
/*05c0*/ IMAD R5, R9, R2, RZ ; /* 0x0000000209057224 */
/* 0x004fd000078e02ff */
/*05d0*/ @!P0 BRA 0x940 ; /* 0x0000036000008947 */
/* 0x000fea0003800000 */
/*05e0*/ LDL R2, [R4+-0x10] ; /* 0xfffff00004027983 */
/* 0x000ea20000100800 */
/*05f0*/ ISETP.NE.U32.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fe40003f05070 */
/*0600*/ IADD3 R3, R9, -0xa, RZ ; /* 0xfffffff609037810 */
/* 0x000fe40007ffe0ff */
/*0610*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05300 */
/*0620*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fd400078e0205 */
/*0630*/ @!P0 BRA 0x940 ; /* 0x0000030000008947 */
/* 0x000fea0003800000 */
/*0640*/ LDL R2, [R4+-0x18] ; /* 0xffffe80004027983 */
/* 0x000ea20000100800 */
/*0650*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fe2000f8e00ff */
/*0660*/ ISETP.GE.U32.AND P0, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fc80003f06070 */
/*0670*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*0680*/ IADD3 R3, R9, -0x14, RZ ; /* 0xffffffec09037810 */
/* 0x000fca0007ffe0ff */
/*0690*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fcc00078e0205 */
/*06a0*/ @!P0 BRA 0x940 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*06b0*/ LDL R2, [R4+-0x20] ; /* 0xffffe00004027983 */
/* 0x000ea20000100800 */
/*06c0*/ ISETP.NE.U32.AND P0, PT, R0, 0x4, PT ; /* 0x000000040000780c */
/* 0x000fe40003f05070 */
/*06d0*/ IADD3 R3, R9, -0x1e, RZ ; /* 0xffffffe209037810 */
/* 0x000fe40007ffe0ff */
/*06e0*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05300 */
/*06f0*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fd400078e0205 */
/*0700*/ @!P0 BRA 0x940 ; /* 0x0000023000008947 */
/* 0x000fea0003800000 */
/*0710*/ LDL R2, [R4+-0x28] ; /* 0xffffd80004027983 */
/* 0x000ea20000100800 */
/*0720*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fe2000f8e00ff */
/*0730*/ ISETP.GE.U32.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x000fc80003f06070 */
/*0740*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*0750*/ IADD3 R3, R9, -0x28, RZ ; /* 0xffffffd809037810 */
/* 0x000fca0007ffe0ff */
/*0760*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fcc00078e0205 */
/*0770*/ @!P0 BRA 0x940 ; /* 0x000001c000008947 */
/* 0x000fea0003800000 */
/*0780*/ LDL R2, [R4+-0x30] ; /* 0xffffd00004027983 */
/* 0x000ea20000100800 */
/*0790*/ ISETP.NE.U32.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x000fe40003f05070 */
/*07a0*/ IADD3 R3, R9, -0x32, RZ ; /* 0xffffffce09037810 */
/* 0x000fe40007ffe0ff */
/*07b0*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05300 */
/*07c0*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fd400078e0205 */
/*07d0*/ @!P0 BRA 0x940 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*07e0*/ LDL R2, [R4+-0x38] ; /* 0xffffc80004027983 */
/* 0x000ea20000100800 */
/*07f0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fe2000f8e00ff */
/*0800*/ ISETP.GE.U32.AND P0, PT, R0, 0x8, PT ; /* 0x000000080000780c */
/* 0x000fc80003f06070 */
/*0810*/ ISETP.GE.U32.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f06100 */
/*0820*/ IADD3 R3, R9, -0x3c, RZ ; /* 0xffffffc409037810 */
/* 0x000fca0007ffe0ff */
/*0830*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fcc00078e0205 */
/*0840*/ @!P0 BRA 0x940 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0850*/ LDL R2, [R4+-0x40] ; /* 0xffffc00004027983 */
/* 0x000ea20000100800 */
/*0860*/ ISETP.NE.U32.AND P0, PT, R0, 0x8, PT ; /* 0x000000080000780c */
/* 0x000fe40003f05070 */
/*0870*/ IADD3 R3, R9, -0x46, RZ ; /* 0xffffffba09037810 */
/* 0x000fe40007ffe0ff */
/*0880*/ ISETP.NE.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fc6000bf05300 */
/*0890*/ IMAD R5, R2, R3, R5 ; /* 0x0000000302057224 */
/* 0x004fd400078e0205 */
/*08a0*/ @!P0 BRA 0x940 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*08b0*/ ISETP.GE.U32.AND P0, PT, R0, 0xa, PT ; /* 0x0000000a0000780c */
/* 0x000fe20003f06070 */
/*08c0*/ IMAD.U32 R0, RZ, RZ, UR4 ; /* 0x00000004ff007e24 */
/* 0x000fca000f8e00ff */
/*08d0*/ ISETP.GE.U32.AND.EX P0, PT, R0, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x000fe40003f06100 */
/*08e0*/ LDL R0, [R4+-0x48] ; /* 0xffffb80004007983 */
/* 0x000eb60000100800 */
/*08f0*/ @P0 LDL R2, [R4+-0x50] ; /* 0xffffb00004020983 */
/* 0x000ee20000100800 */
/*0900*/ IADD3 R3, R9, -0x50, RZ ; /* 0xffffffb009037810 */
/* 0x000fca0007ffe0ff */
/*0910*/ IMAD R5, R0, R3, R5 ; /* 0x0000000300057224 */
/* 0x004fe200078e0205 */
/*0920*/ @P0 IADD3 R3, R9, -0x5a, RZ ; /* 0xffffffa609030810 */
/* 0x000fca0007ffe0ff */
/*0930*/ @P0 IMAD R5, R2, R3, R5 ; /* 0x0000000302050224 */
/* 0x008fe400078e0205 */
/*0940*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0950*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0960*/ LEA R2, P0, R6, c[0x0][0x168], 0x2 ; /* 0x00005a0006027a11 */
/* 0x000fc800078010ff */
/*0970*/ LEA.HI.X R3, R6, c[0x0][0x16c], R7, 0x2, P0 ; /* 0x00005b0006037a11 */
/* 0x000fca00000f1407 */
/*0980*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101906 */
/*0990*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09a0*/ BRA 0x9a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5octalPiS_
.globl _Z5octalPiS_
.p2align 8
.type _Z5octalPiS_,@function
_Z5octalPiS_:
s_load_b64 s[2:3], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 2, v0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v4, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b32 v5, v1, s[2:3]
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e32 7, v5
s_cbranch_execz .LBB0_4
v_mov_b32_e32 v6, 16
s_mov_b64 s[2:3], 0
s_mov_b32 s5, 0
.LBB0_2:
s_add_u32 s2, s2, 1
v_lshrrev_b32_e32 v7, 3, v5
s_addc_u32 s3, s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v4, s3 :: v_dual_and_b32 v1, 7, v5
v_cmp_gt_u32_e32 vcc_lo, 64, v5
v_mov_b32_e32 v3, s2
v_mov_b32_e32 v5, v7
scratch_store_b64 v6, v[1:2], off
v_add_nc_u32_e32 v6, 8, v6
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_2
s_or_b32 exec_lo, exec_lo, s5
.LBB0_4:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
v_mov_b32_e32 v5, 0
s_mov_b32 s3, exec_lo
v_cmpx_lt_i64_e32 0, v[3:4]
s_cbranch_execz .LBB0_8
v_mad_u64_u32 v[1:2], null, v3, 10, -10
s_mov_b32 s4, 0
v_mov_b32_e32 v7, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[5:6], null, v4, 10, v[2:3]
v_lshlrev_b32_e32 v6, 3, v3
v_add_co_u32 v2, vcc_lo, v3, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v4, vcc_lo
v_add3_u32 v4, v6, 16, -8
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, v5
.p2align 6
.LBB0_6:
scratch_load_b64 v[10:11], v4, off
v_add_co_u32 v2, vcc_lo, v2, -1
v_add_co_ci_u32_e32 v3, vcc_lo, -1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i64_e32 vcc_lo, 2, v[2:3]
s_or_b32 s4, vcc_lo, s4
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[5:6], null, v1, v10, v[7:8]
v_mul_lo_u32 v7, v1, v11
v_mul_lo_u32 v8, v9, v10
v_add_co_u32 v1, s2, v1, -10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v9, s2, -1, v9, s2
v_add3_u32 v6, v8, v6, v7
v_add_nc_u32_e32 v4, -8, v4
s_delay_alu instid0(VALU_DEP_2)
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_6
s_or_b32 exec_lo, exec_lo, s4
.LBB0_8:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v5, s[0:1]
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5octalPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 416
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 1
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 6
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5octalPiS_, .Lfunc_end0-_Z5octalPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5octalPiS_
.private_segment_fixed_size: 416
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z5octalPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00163bd2_00000000-6_octal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z5octalPiS_PiS_
.type _Z26__device_stub__Z5octalPiS_PiS_, @function
_Z26__device_stub__Z5octalPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z5octalPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z5octalPiS_PiS_, .-_Z26__device_stub__Z5octalPiS_PiS_
.globl _Z5octalPiS_
.type _Z5octalPiS_, @function
_Z5octalPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z5octalPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z5octalPiS_, .-_Z5octalPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter value of N:"
.LC1:
.string "%d"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Enter array elements of array A\n"
.section .rodata.str1.1
.LC3:
.string "Octal array is :"
.LC4:
.string "%d\t"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
leaq -77824(%rsp), %r11
.cfi_def_cfa 11, 77856
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $2240, %rsp
.cfi_def_cfa_offset 80096
movq %fs:40, %rax
movq %rax, 80056(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 4(%rsp), %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 4(%rsp), %esi
testl %esi, %esi
jle .L12
leaq 48(%rsp), %rbp
movl $0, %ebx
leaq .LC1(%rip), %r12
.L13:
movq %rbp, %rsi
movq %r12, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
addl $1, %ebx
movl 4(%rsp), %esi
addq $4, %rbp
cmpl %ebx, %esi
jg .L13
.L12:
sall $2, %esi
movslq %esi, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
leal 0(,%rax,4), %esi
movslq %esi, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl 4(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 48(%rsp), %rsi
movl $1, %ecx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 40048(%rsp), %rsi
movl $1, %ecx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 4(%rsp), %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L14:
movl 4(%rsp), %eax
leal 0(,%rax,4), %edx
movslq %edx, %rdx
leaq 40048(%rsp), %rdi
movl $2, %ecx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 4(%rsp)
jle .L15
movl $0, %ebx
leaq .LC4(%rip), %rbp
.L16:
movl 40048(%rsp,%rbx,4), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, 4(%rsp)
jg .L16
.L15:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 80056(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $80064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z26__device_stub__Z5octalPiS_PiS_
jmp .L14
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z5octalPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z5octalPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "octal.hip"
.globl _Z20__device_stub__octalPiS_ # -- Begin function _Z20__device_stub__octalPiS_
.p2align 4, 0x90
.type _Z20__device_stub__octalPiS_,@function
_Z20__device_stub__octalPiS_: # @_Z20__device_stub__octalPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5octalPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z20__device_stub__octalPiS_, .Lfunc_end0-_Z20__device_stub__octalPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $80120, %rsp # imm = 0x138F8
.cfi_def_cfa_offset 80144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movl $.Lstr, %edi
callq puts@PLT
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
leaq 40112(%rsp), %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
incq %r14
movslq 12(%rsp), %rax
addq $4, %rbx
cmpq %rax, %r14
jl .LBB1_2
.LBB1_3: # %._crit_edge
shll $2, %eax
movslq %eax, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movslq 12(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
movq 24(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 40112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 112(%rsp), %rsi
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edx
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %rdx
orq $1, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z5octalPiS_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
leaq 112(%rsp), %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB1_8
# %bb.6: # %.lr.ph19.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # %.lr.ph19
# =>This Inner Loop Header: Depth=1
movl 112(%rsp,%rbx,4), %esi
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
incq %rbx
movslq 12(%rsp), %rax
cmpq %rax, %rbx
jl .LBB1_7
.LBB1_8: # %._crit_edge20
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $80120, %rsp # imm = 0x138F8
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5octalPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5octalPiS_,@object # @_Z5octalPiS_
.section .rodata,"a",@progbits
.globl _Z5octalPiS_
.p2align 3, 0x0
_Z5octalPiS_:
.quad _Z20__device_stub__octalPiS_
.size _Z5octalPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter value of N:"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Octal array is :"
.size .L.str.3, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "%d\t"
.size .L.str.4, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5octalPiS_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter array elements of array A"
.size .Lstr, 32
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__octalPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5octalPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void cuda_divide(float * dst, float *numerator, float *denominator, int width, int height)
{
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width)
{
int index = row * width + col;
if(denominator[index] > 0.0000001)
{
dst[index] = numerator[index] / denominator[index];
}
else
{
dst[index] = 0;
}
// printf("dst[%d] = %f\n", index, dst[index]);
}
} | code for sm_80
Function : _Z11cuda_dividePfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fc800078e0203 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0207 */
/*00e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x004e240000201800 */
/*0100*/ DSETP.GT.AND P0, PT, R2, c[0x2][0x0], PT ; /* 0x008000000200762a */
/* 0x0010640003f04000 */
/*0110*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fd800078e0207 */
/*0120*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0021e2000c101904 */
/*0130*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0140*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*0150*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0160*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fcc00000f1405 */
/*0170*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0180*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x000e620000001000 */
/*0190*/ BSSY B0, 0x240 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*01a0*/ FFMA R0, -R6, R7, 1 ; /* 0x3f80000006007423 */
/* 0x002fc80000000107 */
/*01b0*/ FFMA R0, R7, R0, R7 ; /* 0x0000000007007223 */
/* 0x000fe40000000007 */
/*01c0*/ FCHK P0, R5, R6 ; /* 0x0000000605007302 */
/* 0x004e640000000000 */
/*01d0*/ FFMA R7, R5, R0, RZ ; /* 0x0000000005077223 */
/* 0x000fc800000000ff */
/*01e0*/ FFMA R8, -R6, R7, R5 ; /* 0x0000000706087223 */
/* 0x000fc80000000105 */
/*01f0*/ FFMA R7, R0, R8, R7 ; /* 0x0000000800077223 */
/* 0x000fe20000000007 */
/*0200*/ @!P0 BRA 0x230 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0210*/ MOV R0, 0x230 ; /* 0x0000023000007802 */
/* 0x000fe40000000f00 */
/*0220*/ CALL.REL.NOINC 0x260 ; /* 0x0000003000007944 */
/* 0x001fea0003c00000 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ SHF.R.U32.HI R7, RZ, 0x17, R6.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011606 */
/*0270*/ BSSY B1, 0x8c0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0280*/ SHF.R.U32.HI R4, RZ, 0x17, R5.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011605 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*02a0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*02b0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0006 */
/*02c0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*02d0*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ IADD3 R11, R4, -0x1, RZ ; /* 0xffffffff040b7810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0300*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0310*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0320*/ @!P0 BRA 0x4a0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0330*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f1c200 */
/*0340*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*0350*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0360*/ @P0 BRA 0x8a0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0370*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0380*/ @!P0 BRA 0x880 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0390*/ FSETP.NEU.FTZ.AND P2, PT, |R5|.reuse, +INF , PT ; /* 0x7f8000000500780b */
/* 0x040fe40003f5d200 */
/*03a0*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*03b0*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*03c0*/ @!P1 BRA !P2, 0x880 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03d0*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*03e0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03f0*/ @P1 BRA 0x860 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0410*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0420*/ @P0 BRA 0x830 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0440*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0450*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0460*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0470*/ @!P0 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005088823 */
/* 0x000fe400000000ff */
/*0480*/ @!P1 FFMA R9, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006099823 */
/* 0x000fe200000000ff */
/*0490*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ LEA R6, R7, 0xc0800000, 0x17 ; /* 0xc080000007067811 */
/* 0x000fe200078eb8ff */
/*04b0*/ BSSY B2, 0x820 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*04c0*/ IADD3 R5, R4, -0x7f, RZ ; /* 0xffffff8104057810 */
/* 0x000fc60007ffe0ff */
/*04d0*/ IMAD.IADD R6, R9, 0x1, -R6 ; /* 0x0000000109067824 */
/* 0x000fe200078e0a06 */
/*04e0*/ IADD3 R7, R5.reuse, 0x7f, -R7 ; /* 0x0000007f05077810 */
/* 0x040fe20007ffe807 */
/*04f0*/ IMAD R8, R5, -0x800000, R8 ; /* 0xff80000005087824 */
/* 0x000fe400078e0208 */
/*0500*/ MUFU.RCP R9, R6 ; /* 0x0000000600097308 */
/* 0x000e220000001000 */
/*0510*/ FADD.FTZ R11, -R6, -RZ ; /* 0x800000ff060b7221 */
/* 0x000fe40000010100 */
/*0520*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0530*/ FFMA R4, R9, R11, 1 ; /* 0x3f80000009047423 */
/* 0x001fc8000000000b */
/*0540*/ FFMA R13, R9, R4, R9 ; /* 0x00000004090d7223 */
/* 0x000fc80000000009 */
/*0550*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*0560*/ FFMA R9, R11, R4, R8 ; /* 0x000000040b097223 */
/* 0x000fc80000000008 */
/*0570*/ FFMA R12, R13, R9, R4 ; /* 0x000000090d0c7223 */
/* 0x000fc80000000004 */
/*0580*/ FFMA R8, R11, R12, R8 ; /* 0x0000000c0b087223 */
/* 0x000fc80000000008 */
/*0590*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*05a0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*05b0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*05c0*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*05d0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*05e0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*05f0*/ @!P0 BRA 0x800 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0610*/ @P0 BRA 0x7d0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0630*/ @P0 BRA 0x810 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0650*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0660*/ @!P0 BRA 0x810 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0670*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0680*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0690*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*06a0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*06b0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*06c0*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*06d0*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*06f0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0700*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0710*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0720*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0730*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0740*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0750*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0760*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0770*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0780*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0790*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*07a0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*07b0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*07c0*/ BRA 0x810 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*07e0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07f0*/ BRA 0x810 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0800*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0810*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0820*/ BRA 0x8b0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*0840*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0850*/ BRA 0x8b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0860*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*0870*/ BRA 0x8b0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0880*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0890*/ BRA 0x8b0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08a0*/ FADD.FTZ R4, R5, R6 ; /* 0x0000000605047221 */
/* 0x000fe40000010000 */
/*08b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0004 */
/*08d0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*08e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08f0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff70004007950 */
/* 0x000fea0003c3ffff */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cuda_divide(float * dst, float *numerator, float *denominator, int width, int height)
{
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width)
{
int index = row * width + col;
if(denominator[index] > 0.0000001)
{
dst[index] = numerator[index] / denominator[index];
}
else
{
dst[index] = 0;
}
// printf("dst[%d] = %f\n", index, dst[index]);
}
} | .file "tmpxft_000cc991_00000000-6_cuda_divide.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii
.type _Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii, @function
_Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11cuda_dividePfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii, .-_Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii
.globl _Z11cuda_dividePfS_S_ii
.type _Z11cuda_dividePfS_S_ii, @function
_Z11cuda_dividePfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11cuda_dividePfS_S_ii, .-_Z11cuda_dividePfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11cuda_dividePfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11cuda_dividePfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cuda_divide(float * dst, float *numerator, float *denominator, int width, int height)
{
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width)
{
int index = row * width + col;
if(denominator[index] > 0.0000001)
{
dst[index] = numerator[index] / denominator[index];
}
else
{
dst[index] = 0;
}
// printf("dst[%d] = %f\n", index, dst[index]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_divide(float * dst, float *numerator, float *denominator, int width, int height)
{
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width)
{
int index = row * width + col;
if(denominator[index] > 0.0000001)
{
dst[index] = numerator[index] / denominator[index];
}
else
{
dst[index] = 0;
}
// printf("dst[%d] = %f\n", index, dst[index]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_divide(float * dst, float *numerator, float *denominator, int width, int height)
{
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width)
{
int index = row * width + col;
if(denominator[index] > 0.0000001)
{
dst[index] = numerator[index] / denominator[index];
}
else
{
dst[index] = 0;
}
// printf("dst[%d] = %f\n", index, dst[index]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11cuda_dividePfS_S_ii
.globl _Z11cuda_dividePfS_S_ii
.p2align 8
.type _Z11cuda_dividePfS_S_ii,@function
_Z11cuda_dividePfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s3, 0x3e7ad7f2
s_mov_b32 s2, 0x9abcaf48
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[3:4], v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[3:4]
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v3, v4, v2, v3
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11cuda_dividePfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11cuda_dividePfS_S_ii, .Lfunc_end0-_Z11cuda_dividePfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
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.value_kind: global_buffer
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.size: 4
.value_kind: by_value
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.size: 4
.value_kind: by_value
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.size: 4
.value_kind: hidden_block_count_x
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.size: 4
.value_kind: hidden_block_count_y
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.size: 4
.value_kind: hidden_block_count_z
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.size: 2
.value_kind: hidden_group_size_x
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.size: 2
.value_kind: hidden_group_size_y
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.size: 2
.value_kind: hidden_group_size_z
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.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11cuda_dividePfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11cuda_dividePfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cuda_divide(float * dst, float *numerator, float *denominator, int width, int height)
{
int row = threadIdx.y + blockIdx.y * blockDim.y;
int col = threadIdx.x + blockIdx.x * blockDim.x;
if(row < height && col < width)
{
int index = row * width + col;
if(denominator[index] > 0.0000001)
{
dst[index] = numerator[index] / denominator[index];
}
else
{
dst[index] = 0;
}
// printf("dst[%d] = %f\n", index, dst[index]);
}
} | .text
.file "cuda_divide.hip"
.globl _Z26__device_stub__cuda_dividePfS_S_ii # -- Begin function _Z26__device_stub__cuda_dividePfS_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__cuda_dividePfS_S_ii,@function
_Z26__device_stub__cuda_dividePfS_S_ii: # @_Z26__device_stub__cuda_dividePfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11cuda_dividePfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__cuda_dividePfS_S_ii, .Lfunc_end0-_Z26__device_stub__cuda_dividePfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11cuda_dividePfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11cuda_dividePfS_S_ii,@object # @_Z11cuda_dividePfS_S_ii
.section .rodata,"a",@progbits
.globl _Z11cuda_dividePfS_S_ii
.p2align 3, 0x0
_Z11cuda_dividePfS_S_ii:
.quad _Z26__device_stub__cuda_dividePfS_S_ii
.size _Z11cuda_dividePfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11cuda_dividePfS_S_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__cuda_dividePfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11cuda_dividePfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11cuda_dividePfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fc800078e0203 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0207 */
/*00e0*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ F2F.F64.F32 R2, R6 ; /* 0x0000000600027310 */
/* 0x004e240000201800 */
/*0100*/ DSETP.GT.AND P0, PT, R2, c[0x2][0x0], PT ; /* 0x008000000200762a */
/* 0x0010640003f04000 */
/*0110*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x001fd800078e0207 */
/*0120*/ @!P0 STG.E [R2.64], RZ ; /* 0x000000ff02008986 */
/* 0x0021e2000c101904 */
/*0130*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0140*/ SHF.R.S32.HI R5, RZ, 0x1f, R0 ; /* 0x0000001fff057819 */
/* 0x000fe40000011400 */
/*0150*/ LEA R4, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000047a11 */
/* 0x000fc800078010ff */
/*0160*/ LEA.HI.X R5, R0, c[0x0][0x16c], R5, 0x2, P0 ; /* 0x00005b0000057a11 */
/* 0x000fcc00000f1405 */
/*0170*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0180*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x000e620000001000 */
/*0190*/ BSSY B0, 0x240 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*01a0*/ FFMA R0, -R6, R7, 1 ; /* 0x3f80000006007423 */
/* 0x002fc80000000107 */
/*01b0*/ FFMA R0, R7, R0, R7 ; /* 0x0000000007007223 */
/* 0x000fe40000000007 */
/*01c0*/ FCHK P0, R5, R6 ; /* 0x0000000605007302 */
/* 0x004e640000000000 */
/*01d0*/ FFMA R7, R5, R0, RZ ; /* 0x0000000005077223 */
/* 0x000fc800000000ff */
/*01e0*/ FFMA R8, -R6, R7, R5 ; /* 0x0000000706087223 */
/* 0x000fc80000000105 */
/*01f0*/ FFMA R7, R0, R8, R7 ; /* 0x0000000800077223 */
/* 0x000fe20000000007 */
/*0200*/ @!P0 BRA 0x230 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0210*/ MOV R0, 0x230 ; /* 0x0000023000007802 */
/* 0x000fe40000000f00 */
/*0220*/ CALL.REL.NOINC 0x260 ; /* 0x0000003000007944 */
/* 0x001fea0003c00000 */
/*0230*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0240*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ SHF.R.U32.HI R7, RZ, 0x17, R6.reuse ; /* 0x00000017ff077819 */
/* 0x100fe20000011606 */
/*0270*/ BSSY B1, 0x8c0 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0280*/ SHF.R.U32.HI R4, RZ, 0x17, R5.reuse ; /* 0x00000017ff047819 */
/* 0x100fe20000011605 */
/*0290*/ IMAD.MOV.U32 R8, RZ, RZ, R5 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0005 */
/*02a0*/ LOP3.LUT R7, R7, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff07077812 */
/* 0x000fe200078ec0ff */
/*02b0*/ IMAD.MOV.U32 R9, RZ, RZ, R6 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0006 */
/*02c0*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fe400078ec0ff */
/*02d0*/ IADD3 R12, R7, -0x1, RZ ; /* 0xffffffff070c7810 */
/* 0x000fc40007ffe0ff */
/*02e0*/ IADD3 R11, R4, -0x1, RZ ; /* 0xffffffff040b7810 */
/* 0x000fe40007ffe0ff */
/*02f0*/ ISETP.GT.U32.AND P0, PT, R12, 0xfd, PT ; /* 0x000000fd0c00780c */
/* 0x000fc80003f04070 */
/*0300*/ ISETP.GT.U32.OR P0, PT, R11, 0xfd, P0 ; /* 0x000000fd0b00780c */
/* 0x000fda0000704470 */
/*0310*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a8224 */
/* 0x000fe200078e00ff */
/*0320*/ @!P0 BRA 0x4a0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0330*/ FSETP.GTU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fe40003f1c200 */
/*0340*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*0350*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0360*/ @P0 BRA 0x8a0 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0370*/ LOP3.LUT P0, RZ, R9, 0x7fffffff, R8, 0xc8, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fda000780c808 */
/*0380*/ @!P0 BRA 0x880 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0390*/ FSETP.NEU.FTZ.AND P2, PT, |R5|.reuse, +INF , PT ; /* 0x7f8000000500780b */
/* 0x040fe40003f5d200 */
/*03a0*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*03b0*/ FSETP.NEU.FTZ.AND P0, PT, |R5|, +INF , PT ; /* 0x7f8000000500780b */
/* 0x000fd60003f1d200 */
/*03c0*/ @!P1 BRA !P2, 0x880 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*03d0*/ LOP3.LUT P2, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000784c0ff */
/*03e0*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*03f0*/ @P1 BRA 0x860 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0400*/ LOP3.LUT P1, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000782c0ff */
/*0410*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0420*/ @P0 BRA 0x830 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0430*/ ISETP.GE.AND P0, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fe40003f06270 */
/*0440*/ ISETP.GE.AND P1, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fd60003f26270 */
/*0450*/ @P0 IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a0224 */
/* 0x000fe400078e00ff */
/*0460*/ @!P0 IMAD.MOV.U32 R10, RZ, RZ, -0x40 ; /* 0xffffffc0ff0a8424 */
/* 0x000fe400078e00ff */
/*0470*/ @!P0 FFMA R8, R5, 1.84467440737095516160e+19, RZ ; /* 0x5f80000005088823 */
/* 0x000fe400000000ff */
/*0480*/ @!P1 FFMA R9, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f80000006099823 */
/* 0x000fe200000000ff */
/*0490*/ @!P1 IADD3 R10, R10, 0x40, RZ ; /* 0x000000400a0a9810 */
/* 0x000fe40007ffe0ff */
/*04a0*/ LEA R6, R7, 0xc0800000, 0x17 ; /* 0xc080000007067811 */
/* 0x000fe200078eb8ff */
/*04b0*/ BSSY B2, 0x820 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*04c0*/ IADD3 R5, R4, -0x7f, RZ ; /* 0xffffff8104057810 */
/* 0x000fc60007ffe0ff */
/*04d0*/ IMAD.IADD R6, R9, 0x1, -R6 ; /* 0x0000000109067824 */
/* 0x000fe200078e0a06 */
/*04e0*/ IADD3 R7, R5.reuse, 0x7f, -R7 ; /* 0x0000007f05077810 */
/* 0x040fe20007ffe807 */
/*04f0*/ IMAD R8, R5, -0x800000, R8 ; /* 0xff80000005087824 */
/* 0x000fe400078e0208 */
/*0500*/ MUFU.RCP R9, R6 ; /* 0x0000000600097308 */
/* 0x000e220000001000 */
/*0510*/ FADD.FTZ R11, -R6, -RZ ; /* 0x800000ff060b7221 */
/* 0x000fe40000010100 */
/*0520*/ IMAD.IADD R7, R7, 0x1, R10 ; /* 0x0000000107077824 */
/* 0x000fe400078e020a */
/*0530*/ FFMA R4, R9, R11, 1 ; /* 0x3f80000009047423 */
/* 0x001fc8000000000b */
/*0540*/ FFMA R13, R9, R4, R9 ; /* 0x00000004090d7223 */
/* 0x000fc80000000009 */
/*0550*/ FFMA R4, R8, R13, RZ ; /* 0x0000000d08047223 */
/* 0x000fc800000000ff */
/*0560*/ FFMA R9, R11, R4, R8 ; /* 0x000000040b097223 */
/* 0x000fc80000000008 */
/*0570*/ FFMA R12, R13, R9, R4 ; /* 0x000000090d0c7223 */
/* 0x000fc80000000004 */
/*0580*/ FFMA R8, R11, R12, R8 ; /* 0x0000000c0b087223 */
/* 0x000fc80000000008 */
/*0590*/ FFMA R4, R13, R8, R12 ; /* 0x000000080d047223 */
/* 0x000fca000000000c */
/*05a0*/ SHF.R.U32.HI R5, RZ, 0x17, R4 ; /* 0x00000017ff057819 */
/* 0x000fc80000011604 */
/*05b0*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fca00078ec0ff */
/*05c0*/ IMAD.IADD R9, R5, 0x1, R7 ; /* 0x0000000105097824 */
/* 0x000fca00078e0207 */
/*05d0*/ IADD3 R5, R9, -0x1, RZ ; /* 0xffffffff09057810 */
/* 0x000fc80007ffe0ff */
/*05e0*/ ISETP.GE.U32.AND P0, PT, R5, 0xfe, PT ; /* 0x000000fe0500780c */
/* 0x000fda0003f06070 */
/*05f0*/ @!P0 BRA 0x800 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0600*/ ISETP.GT.AND P0, PT, R9, 0xfe, PT ; /* 0x000000fe0900780c */
/* 0x000fda0003f04270 */
/*0610*/ @P0 BRA 0x7d0 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0620*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x000fda0003f06270 */
/*0630*/ @P0 BRA 0x810 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0640*/ ISETP.GE.AND P0, PT, R9, -0x18, PT ; /* 0xffffffe80900780c */
/* 0x000fe40003f06270 */
/*0650*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fd600078ec0ff */
/*0660*/ @!P0 BRA 0x810 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0670*/ FFMA.RZ R5, R13, R8.reuse, R12.reuse ; /* 0x000000080d057223 */
/* 0x180fe2000000c00c */
/*0680*/ ISETP.NE.AND P2, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe20003f45270 */
/*0690*/ FFMA.RM R6, R13, R8.reuse, R12.reuse ; /* 0x000000080d067223 */
/* 0x180fe2000000400c */
/*06a0*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*06b0*/ LOP3.LUT R7, R5, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff05077812 */
/* 0x000fe200078ec0ff */
/*06c0*/ FFMA.RP R5, R13, R8, R12 ; /* 0x000000080d057223 */
/* 0x000fe2000000800c */
/*06d0*/ IADD3 R8, R9, 0x20, RZ ; /* 0x0000002009087810 */
/* 0x000fe20007ffe0ff */
/*06e0*/ IMAD.MOV R9, RZ, RZ, -R9 ; /* 0x000000ffff097224 */
/* 0x000fe200078e0a09 */
/*06f0*/ LOP3.LUT R7, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007077812 */
/* 0x000fe400078efcff */
/*0700*/ FSETP.NEU.FTZ.AND P0, PT, R5, R6, PT ; /* 0x000000060500720b */
/* 0x000fc40003f1d000 */
/*0710*/ SHF.L.U32 R8, R7, R8, RZ ; /* 0x0000000807087219 */
/* 0x000fe400000006ff */
/*0720*/ SEL R6, R9, RZ, P2 ; /* 0x000000ff09067207 */
/* 0x000fe40001000000 */
/*0730*/ ISETP.NE.AND P1, PT, R8, RZ, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40000f25270 */
/*0740*/ SHF.R.U32.HI R6, RZ, R6, R7 ; /* 0x00000006ff067219 */
/* 0x000fe40000011607 */
/*0750*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*0760*/ SHF.R.U32.HI R8, RZ, 0x1, R6 ; /* 0x00000001ff087819 */
/* 0x000fc40000011606 */
/*0770*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0780*/ LOP3.LUT R5, R5, 0x1, R8, 0xf8, !PT ; /* 0x0000000105057812 */
/* 0x000fc800078ef808 */
/*0790*/ LOP3.LUT R5, R5, R6, RZ, 0xc0, !PT ; /* 0x0000000605057212 */
/* 0x000fca00078ec0ff */
/*07a0*/ IMAD.IADD R5, R8, 0x1, R5 ; /* 0x0000000108057824 */
/* 0x000fca00078e0205 */
/*07b0*/ LOP3.LUT R4, R5, R4, RZ, 0xfc, !PT ; /* 0x0000000405047212 */
/* 0x000fe200078efcff */
/*07c0*/ BRA 0x810 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*07d0*/ LOP3.LUT R4, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004047812 */
/* 0x000fc800078ec0ff */
/*07e0*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*07f0*/ BRA 0x810 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0800*/ IMAD R4, R7, 0x800000, R4 ; /* 0x0080000007047824 */
/* 0x000fe400078e0204 */
/*0810*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0820*/ BRA 0x8b0 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0830*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fc800078e4808 */
/*0840*/ LOP3.LUT R4, R4, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000004047812 */
/* 0x000fe200078efcff */
/*0850*/ BRA 0x8b0 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0860*/ LOP3.LUT R4, R9, 0x80000000, R8, 0x48, !PT ; /* 0x8000000009047812 */
/* 0x000fe200078e4808 */
/*0870*/ BRA 0x8b0 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*0880*/ MUFU.RSQ R4, -QNAN ; /* 0xffc0000000047908 */
/* 0x000e220000001400 */
/*0890*/ BRA 0x8b0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*08a0*/ FADD.FTZ R4, R5, R6 ; /* 0x0000000605047221 */
/* 0x000fe40000010000 */
/*08b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*08c0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x001fe400078e0004 */
/*08d0*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*08e0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*08f0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff70004007950 */
/* 0x000fea0003c3ffff */
/*0900*/ BRA 0x900; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11cuda_dividePfS_S_ii
.globl _Z11cuda_dividePfS_S_ii
.p2align 8
.type _Z11cuda_dividePfS_S_ii,@function
_Z11cuda_dividePfS_S_ii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
s_mov_b32 s3, 0x3e7ad7f2
s_mov_b32 s2, 0x9abcaf48
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[3:4], v2
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_f64_e32 vcc_lo, s[2:3], v[3:4]
v_mov_b32_e32 v3, 0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[4:5], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v1, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v4, null, v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v3, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v3, v4, v2, v3
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v3, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11cuda_dividePfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11cuda_dividePfS_S_ii, .Lfunc_end0-_Z11cuda_dividePfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11cuda_dividePfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11cuda_dividePfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000cc991_00000000-6_cuda_divide.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii
.type _Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii, @function
_Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11cuda_dividePfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii, .-_Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii
.globl _Z11cuda_dividePfS_S_ii
.type _Z11cuda_dividePfS_S_ii, @function
_Z11cuda_dividePfS_S_ii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11cuda_dividePfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11cuda_dividePfS_S_ii, .-_Z11cuda_dividePfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11cuda_dividePfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11cuda_dividePfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_divide.hip"
.globl _Z26__device_stub__cuda_dividePfS_S_ii # -- Begin function _Z26__device_stub__cuda_dividePfS_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__cuda_dividePfS_S_ii,@function
_Z26__device_stub__cuda_dividePfS_S_ii: # @_Z26__device_stub__cuda_dividePfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11cuda_dividePfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__cuda_dividePfS_S_ii, .Lfunc_end0-_Z26__device_stub__cuda_dividePfS_S_ii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11cuda_dividePfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11cuda_dividePfS_S_ii,@object # @_Z11cuda_dividePfS_S_ii
.section .rodata,"a",@progbits
.globl _Z11cuda_dividePfS_S_ii
.p2align 3, 0x0
_Z11cuda_dividePfS_S_ii:
.quad _Z26__device_stub__cuda_dividePfS_S_ii
.size _Z11cuda_dividePfS_S_ii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11cuda_dividePfS_S_ii"
.size .L__unnamed_1, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__cuda_dividePfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11cuda_dividePfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,int var_6,int var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28) {
if (comp > +1.8298E-36f + (+0.0f * var_1)) {
if (comp < var_2 / var_3 + log10f((var_4 / (-1.6894E-4f / (-1.0921E36f + -1.3485E28f * -1.9564E-35f + var_5))))) {
comp = var_8 * fabsf(atanf((-1.8050E36f / (-1.5588E13f * var_9 / -1.3933E-8f))));
if (comp > (-1.8341E-43f + +1.5459E2f + cosf((+1.4057E-36f * +1.0774E-37f * (var_10 / -1.9005E-35f))))) {
float tmp_1 = -1.1918E24f;
comp += tmp_1 - var_11 + fmodf(ceilf((var_12 / (var_13 - (var_14 - -1.2298E-21f + var_15)))), var_16 / (+1.4845E-36f + (var_17 / (-1.4237E-17f * var_18))));
comp = (var_19 - (+1.6948E-37f * (var_20 - (var_21 * var_22))));
}
for (int i=0; i < var_6; ++i) {
comp = coshf(sqrtf(var_23 / -1.7772E-36f - var_24 * -1.7355E-37f));
comp += log10f(-1.1000E-36f);
float tmp_2 = -1.4713E-35f;
comp = tmp_2 * (var_25 + var_26);
}
for (int i=0; i < var_7; ++i) {
comp += (var_27 + var_28);
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
int tmp_7 = atoi(argv[7]);
int tmp_8 = atoi(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_001989a6_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff
.type _Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff, @function
_Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $360, %rsp
.cfi_def_cfa_offset 368
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movss %xmm4, 28(%rsp)
movss %xmm5, 24(%rsp)
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 368(%rsp), %rax
movq %rax, 192(%rsp)
leaq 376(%rsp), %rax
movq %rax, 200(%rsp)
leaq 384(%rsp), %rax
movq %rax, 208(%rsp)
leaq 392(%rsp), %rax
movq %rax, 216(%rsp)
leaq 400(%rsp), %rax
movq %rax, 224(%rsp)
leaq 408(%rsp), %rax
movq %rax, 232(%rsp)
leaq 416(%rsp), %rax
movq %rax, 240(%rsp)
leaq 424(%rsp), %rax
movq %rax, 248(%rsp)
leaq 432(%rsp), %rax
movq %rax, 256(%rsp)
leaq 440(%rsp), %rax
movq %rax, 264(%rsp)
leaq 448(%rsp), %rax
movq %rax, 272(%rsp)
leaq 456(%rsp), %rax
movq %rax, 280(%rsp)
leaq 464(%rsp), %rax
movq %rax, 288(%rsp)
leaq 472(%rsp), %rax
movq %rax, 296(%rsp)
leaq 480(%rsp), %rax
movq %rax, 304(%rsp)
leaq 488(%rsp), %rax
movq %rax, 312(%rsp)
leaq 496(%rsp), %rax
movq %rax, 320(%rsp)
leaq 504(%rsp), %rax
movq %rax, 328(%rsp)
leaq 512(%rsp), %rax
movq %rax, 336(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 376
pushq 56(%rsp)
.cfi_def_cfa_offset 384
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computeffffffiifffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 368
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff, .-_Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff
.globl _Z7computeffffffiifffffffffffffffffffff
.type _Z7computeffffffiifffffffffffffffffffff, @function
_Z7computeffffffiifffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movss 320(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computeffffffiifffffffffffffffffffff, .-_Z7computeffffffiifffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $256, %rsp
.cfi_def_cfa_offset 288
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 208(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 56(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 64(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 244(%rsp)
movl $1, 248(%rsp)
movl $1, 232(%rsp)
movl $1, 236(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 244(%rsp), %rdx
movl $1, %ecx
movq 232(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 216(%rsp), %xmm0
subq $160, %rsp
.cfi_def_cfa_offset 448
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 312(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 320(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 328(%rsp), %xmm6
movl %ebp, %esi
movl %r12d, %edi
pxor %xmm5, %xmm5
cvtsd2ss 336(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 344(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 352(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 360(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 368(%rsp), %xmm1
call _Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff
addq $160, %rsp
.cfi_def_cfa_offset 288
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computeffffffiifffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computeffffffiifffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,int var_6,int var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28) {
if (comp > +1.8298E-36f + (+0.0f * var_1)) {
if (comp < var_2 / var_3 + log10f((var_4 / (-1.6894E-4f / (-1.0921E36f + -1.3485E28f * -1.9564E-35f + var_5))))) {
comp = var_8 * fabsf(atanf((-1.8050E36f / (-1.5588E13f * var_9 / -1.3933E-8f))));
if (comp > (-1.8341E-43f + +1.5459E2f + cosf((+1.4057E-36f * +1.0774E-37f * (var_10 / -1.9005E-35f))))) {
float tmp_1 = -1.1918E24f;
comp += tmp_1 - var_11 + fmodf(ceilf((var_12 / (var_13 - (var_14 - -1.2298E-21f + var_15)))), var_16 / (+1.4845E-36f + (var_17 / (-1.4237E-17f * var_18))));
comp = (var_19 - (+1.6948E-37f * (var_20 - (var_21 * var_22))));
}
for (int i=0; i < var_6; ++i) {
comp = coshf(sqrtf(var_23 / -1.7772E-36f - var_24 * -1.7355E-37f));
comp += log10f(-1.1000E-36f);
float tmp_2 = -1.4713E-35f;
comp = tmp_2 * (var_25 + var_26);
}
for (int i=0; i < var_7; ++i) {
comp += (var_27 + var_28);
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
int tmp_7 = atoi(argv[7]);
int tmp_8 = atoi(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,int var_6,int var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28) {
if (comp > +1.8298E-36f + (+0.0f * var_1)) {
if (comp < var_2 / var_3 + log10f((var_4 / (-1.6894E-4f / (-1.0921E36f + -1.3485E28f * -1.9564E-35f + var_5))))) {
comp = var_8 * fabsf(atanf((-1.8050E36f / (-1.5588E13f * var_9 / -1.3933E-8f))));
if (comp > (-1.8341E-43f + +1.5459E2f + cosf((+1.4057E-36f * +1.0774E-37f * (var_10 / -1.9005E-35f))))) {
float tmp_1 = -1.1918E24f;
comp += tmp_1 - var_11 + fmodf(ceilf((var_12 / (var_13 - (var_14 - -1.2298E-21f + var_15)))), var_16 / (+1.4845E-36f + (var_17 / (-1.4237E-17f * var_18))));
comp = (var_19 - (+1.6948E-37f * (var_20 - (var_21 * var_22))));
}
for (int i=0; i < var_6; ++i) {
comp = coshf(sqrtf(var_23 / -1.7772E-36f - var_24 * -1.7355E-37f));
comp += log10f(-1.1000E-36f);
float tmp_2 = -1.4713E-35f;
comp = tmp_2 * (var_25 + var_26);
}
for (int i=0; i < var_7; ++i) {
comp += (var_27 + var_28);
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
int tmp_7 = atoi(argv[7]);
int tmp_8 = atoi(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, float var_1,float var_2,float var_3,float var_4,float var_5,int var_6,int var_7,float var_8,float var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28) {
if (comp > +1.8298E-36f + (+0.0f * var_1)) {
if (comp < var_2 / var_3 + log10f((var_4 / (-1.6894E-4f / (-1.0921E36f + -1.3485E28f * -1.9564E-35f + var_5))))) {
comp = var_8 * fabsf(atanf((-1.8050E36f / (-1.5588E13f * var_9 / -1.3933E-8f))));
if (comp > (-1.8341E-43f + +1.5459E2f + cosf((+1.4057E-36f * +1.0774E-37f * (var_10 / -1.9005E-35f))))) {
float tmp_1 = -1.1918E24f;
comp += tmp_1 - var_11 + fmodf(ceilf((var_12 / (var_13 - (var_14 - -1.2298E-21f + var_15)))), var_16 / (+1.4845E-36f + (var_17 / (-1.4237E-17f * var_18))));
comp = (var_19 - (+1.6948E-37f * (var_20 - (var_21 * var_22))));
}
for (int i=0; i < var_6; ++i) {
comp = coshf(sqrtf(var_23 / -1.7772E-36f - var_24 * -1.7355E-37f));
comp += log10f(-1.1000E-36f);
float tmp_2 = -1.4713E-35f;
comp = tmp_2 * (var_25 + var_26);
}
for (int i=0; i < var_7; ++i) {
comp += (var_27 + var_28);
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
float tmp_2 = atof(argv[2]);
float tmp_3 = atof(argv[3]);
float tmp_4 = atof(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
int tmp_7 = atoi(argv[7]);
int tmp_8 = atoi(argv[8]);
float tmp_9 = atof(argv[9]);
float tmp_10 = atof(argv[10]);
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computeffffffiifffffffffffffffffffff # -- Begin function _Z22__device_stub__computeffffffiifffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computeffffffiifffffffffffffffffffff,@function
_Z22__device_stub__computeffffffiifffffffffffffffffffff: # @_Z22__device_stub__computeffffffiifffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 336
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movss %xmm4, 28(%rsp)
movss %xmm5, 24(%rsp)
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 336(%rsp), %rax
movq %rax, 176(%rsp)
leaq 344(%rsp), %rax
movq %rax, 184(%rsp)
leaq 352(%rsp), %rax
movq %rax, 192(%rsp)
leaq 360(%rsp), %rax
movq %rax, 200(%rsp)
leaq 368(%rsp), %rax
movq %rax, 208(%rsp)
leaq 376(%rsp), %rax
movq %rax, 216(%rsp)
leaq 384(%rsp), %rax
movq %rax, 224(%rsp)
leaq 392(%rsp), %rax
movq %rax, 232(%rsp)
leaq 400(%rsp), %rax
movq %rax, 240(%rsp)
leaq 408(%rsp), %rax
movq %rax, 248(%rsp)
leaq 416(%rsp), %rax
movq %rax, 256(%rsp)
leaq 424(%rsp), %rax
movq %rax, 264(%rsp)
leaq 432(%rsp), %rax
movq %rax, 272(%rsp)
leaq 440(%rsp), %rax
movq %rax, 280(%rsp)
leaq 448(%rsp), %rax
movq %rax, 288(%rsp)
leaq 456(%rsp), %rax
movq %rax, 296(%rsp)
leaq 464(%rsp), %rax
movq %rax, 304(%rsp)
leaq 472(%rsp), %rax
movq %rax, 312(%rsp)
leaq 480(%rsp), %rax
movq %rax, 320(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computeffffffiifffffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $344, %rsp # imm = 0x158
.cfi_adjust_cfa_offset -344
retq
.Lfunc_end0:
.size _Z22__device_stub__computeffffffiifffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computeffffffiifffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $368, %rsp # imm = 0x170
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 24(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 64(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 192(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 200(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 208(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 216(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 224(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 232(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 152(%rsp) # 4-byte Spill
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp) # 4-byte Spill
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 144(%rsp)
movss %xmm9, 136(%rsp)
movss %xmm10, 128(%rsp)
movss %xmm11, 120(%rsp)
movss %xmm12, 112(%rsp)
movss %xmm13, 104(%rsp)
movss %xmm14, 96(%rsp)
movss %xmm15, 88(%rsp)
movss %xmm4, 80(%rsp)
movss %xmm5, 72(%rsp)
movss %xmm6, 64(%rsp)
movss %xmm7, 56(%rsp)
movss 152(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 48(%rsp)
movss 160(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 40(%rsp)
movss 168(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 32(%rsp)
movss 176(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 24(%rsp)
movss 184(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 16(%rsp)
movss 192(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 8(%rsp)
movss 200(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, (%rsp)
movss 232(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 224(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movl %ebx, %edi
movl %r14d, %esi
movss 216(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 208(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computeffffffiifffffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $368, %rsp # imm = 0x170
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computeffffffiifffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computeffffffiifffffffffffffffffffff,@object # @_Z7computeffffffiifffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computeffffffiifffffffffffffffffffff
.p2align 3, 0x0
_Z7computeffffffiifffffffffffffffffffff:
.quad _Z22__device_stub__computeffffffiifffffffffffffffffffff
.size _Z7computeffffffiifffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computeffffffiifffffffffffffffffffff"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computeffffffiifffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computeffffffiifffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001989a6_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff
.type _Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff, @function
_Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $360, %rsp
.cfi_def_cfa_offset 368
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movss %xmm4, 28(%rsp)
movss %xmm5, 24(%rsp)
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 12(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
leaq 368(%rsp), %rax
movq %rax, 192(%rsp)
leaq 376(%rsp), %rax
movq %rax, 200(%rsp)
leaq 384(%rsp), %rax
movq %rax, 208(%rsp)
leaq 392(%rsp), %rax
movq %rax, 216(%rsp)
leaq 400(%rsp), %rax
movq %rax, 224(%rsp)
leaq 408(%rsp), %rax
movq %rax, 232(%rsp)
leaq 416(%rsp), %rax
movq %rax, 240(%rsp)
leaq 424(%rsp), %rax
movq %rax, 248(%rsp)
leaq 432(%rsp), %rax
movq %rax, 256(%rsp)
leaq 440(%rsp), %rax
movq %rax, 264(%rsp)
leaq 448(%rsp), %rax
movq %rax, 272(%rsp)
leaq 456(%rsp), %rax
movq %rax, 280(%rsp)
leaq 464(%rsp), %rax
movq %rax, 288(%rsp)
leaq 472(%rsp), %rax
movq %rax, 296(%rsp)
leaq 480(%rsp), %rax
movq %rax, 304(%rsp)
leaq 488(%rsp), %rax
movq %rax, 312(%rsp)
leaq 496(%rsp), %rax
movq %rax, 320(%rsp)
leaq 504(%rsp), %rax
movq %rax, 328(%rsp)
leaq 512(%rsp), %rax
movq %rax, 336(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 376
pushq 56(%rsp)
.cfi_def_cfa_offset 384
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7computeffffffiifffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 368
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff, .-_Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff
.globl _Z7computeffffffiifffffffffffffffffffff
.type _Z7computeffffffiifffffffffffffffffffff, @function
_Z7computeffffffiifffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movss 320(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computeffffffiifffffffffffffffffffff, .-_Z7computeffffffiifffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $256, %rsp
.cfi_def_cfa_offset 288
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 16(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 208(%rsp)
movq 24(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 32(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 56(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 64(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movl $1, 244(%rsp)
movl $1, 248(%rsp)
movl $1, 232(%rsp)
movl $1, 236(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 244(%rsp), %rdx
movl $1, %ecx
movq 232(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $256, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 216(%rsp), %xmm0
subq $160, %rsp
.cfi_def_cfa_offset 448
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 312(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 320(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 328(%rsp), %xmm6
movl %ebp, %esi
movl %r12d, %edi
pxor %xmm5, %xmm5
cvtsd2ss 336(%rsp), %xmm5
pxor %xmm4, %xmm4
cvtsd2ss 344(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 352(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 360(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 368(%rsp), %xmm1
call _Z53__device_stub__Z7computeffffffiifffffffffffffffffffffffffffiifffffffffffffffffffff
addq $160, %rsp
.cfi_def_cfa_offset 288
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computeffffffiifffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computeffffffiifffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computeffffffiifffffffffffffffffffff # -- Begin function _Z22__device_stub__computeffffffiifffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computeffffffiifffffffffffffffffffff,@function
_Z22__device_stub__computeffffffiifffffffffffffffffffff: # @_Z22__device_stub__computeffffffiifffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $328, %rsp # imm = 0x148
.cfi_def_cfa_offset 336
movss %xmm0, 44(%rsp)
movss %xmm1, 40(%rsp)
movss %xmm2, 36(%rsp)
movss %xmm3, 32(%rsp)
movss %xmm4, 28(%rsp)
movss %xmm5, 24(%rsp)
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movss %xmm6, 12(%rsp)
movss %xmm7, 8(%rsp)
leaq 44(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rax
movq %rax, 104(%rsp)
leaq 36(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
leaq 336(%rsp), %rax
movq %rax, 176(%rsp)
leaq 344(%rsp), %rax
movq %rax, 184(%rsp)
leaq 352(%rsp), %rax
movq %rax, 192(%rsp)
leaq 360(%rsp), %rax
movq %rax, 200(%rsp)
leaq 368(%rsp), %rax
movq %rax, 208(%rsp)
leaq 376(%rsp), %rax
movq %rax, 216(%rsp)
leaq 384(%rsp), %rax
movq %rax, 224(%rsp)
leaq 392(%rsp), %rax
movq %rax, 232(%rsp)
leaq 400(%rsp), %rax
movq %rax, 240(%rsp)
leaq 408(%rsp), %rax
movq %rax, 248(%rsp)
leaq 416(%rsp), %rax
movq %rax, 256(%rsp)
leaq 424(%rsp), %rax
movq %rax, 264(%rsp)
leaq 432(%rsp), %rax
movq %rax, 272(%rsp)
leaq 440(%rsp), %rax
movq %rax, 280(%rsp)
leaq 448(%rsp), %rax
movq %rax, 288(%rsp)
leaq 456(%rsp), %rax
movq %rax, 296(%rsp)
leaq 464(%rsp), %rax
movq %rax, 304(%rsp)
leaq 472(%rsp), %rax
movq %rax, 312(%rsp)
leaq 480(%rsp), %rax
movq %rax, 320(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7computeffffffiifffffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $344, %rsp # imm = 0x158
.cfi_adjust_cfa_offset -344
retq
.Lfunc_end0:
.size _Z22__device_stub__computeffffffiifffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computeffffffiifffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $368, %rsp # imm = 0x170
.cfi_def_cfa_offset 400
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %r15
movq 8(%rsi), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 16(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 24(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 32(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 40(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 48(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 56(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 64(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 72(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 80(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 88(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 96(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 104(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 112(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 120(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 128(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 136(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 152(%rsp) # 8-byte Spill
movq 144(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 152(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 160(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 168(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 176(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 184(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 192(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 200(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 208(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 216(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movq 224(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 232(%r15), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 152(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 152(%rsp) # 4-byte Spill
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp) # 4-byte Spill
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 144(%rsp)
movss %xmm9, 136(%rsp)
movss %xmm10, 128(%rsp)
movss %xmm11, 120(%rsp)
movss %xmm12, 112(%rsp)
movss %xmm13, 104(%rsp)
movss %xmm14, 96(%rsp)
movss %xmm15, 88(%rsp)
movss %xmm4, 80(%rsp)
movss %xmm5, 72(%rsp)
movss %xmm6, 64(%rsp)
movss %xmm7, 56(%rsp)
movss 152(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 48(%rsp)
movss 160(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 40(%rsp)
movss 168(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 32(%rsp)
movss 176(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 24(%rsp)
movss 184(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 16(%rsp)
movss 192(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, 8(%rsp)
movss 200(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss %xmm4, (%rsp)
movss 232(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movss 224(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movl %ebx, %edi
movl %r14d, %esi
movss 216(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 208(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computeffffffiifffffffffffffffffffff
.LBB2_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $368, %rsp # imm = 0x170
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computeffffffiifffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computeffffffiifffffffffffffffffffff,@object # @_Z7computeffffffiifffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computeffffffiifffffffffffffffffffff
.p2align 3, 0x0
_Z7computeffffffiifffffffffffffffffffff:
.quad _Z22__device_stub__computeffffffiifffffffffffffffffffff
.size _Z7computeffffffiifffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computeffffffiifffffffffffffffffffff"
.size .L__unnamed_1, 40
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computeffffffiifffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computeffffffiifffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //imports
#include <stdio.h>
#include <math.h>
#include <cuda.h>
#include <stdlib.h>
__global__ void printSome(int i){
printf("%d",i);
}
int main(){
cudaStream_t streams[5];
int i;
for(i=0;i<5;i++){
cudaStreamCreate(&streams[i]);
}
for(i=0;i<5;i++){
printSome<<<1,1,0,streams[i]>>>(i);
}
for(i=0;i<5;i++){
cudaStreamDestroy(streams[i]);
}
return 0;
} | code for sm_80
Function : _Z9printSomei
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fca00078e00ff */
/*0010*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff087624 */
/* 0x000fe200078e00ff */
/*0030*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0040*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0050*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100800 */
/*0080*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000640000000a00 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fcc00000e06ff */
/*00a0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*00b0*/ MOV R11, 0x120 ; /* 0x00000120000b7802 */
/* 0x000fe40000000f00 */
/*00c0*/ MOV R20, 0xa0 ; /* 0x000000a000147802 */
/* 0x000fc40000000f00 */
/*00d0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*00f0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0100*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0110*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //imports
#include <stdio.h>
#include <math.h>
#include <cuda.h>
#include <stdlib.h>
__global__ void printSome(int i){
printf("%d",i);
}
int main(){
cudaStream_t streams[5];
int i;
for(i=0;i<5;i++){
cudaStreamCreate(&streams[i]);
}
for(i=0;i<5;i++){
printSome<<<1,1,0,streams[i]>>>(i);
}
for(i=0;i<5;i++){
cudaStreamDestroy(streams[i]);
}
return 0;
} | .file "tmpxft_00025f2b_00000000-6_handout.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9printSomeii
.type _Z27__device_stub__Z9printSomeii, @function
_Z27__device_stub__Z9printSomeii:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9printSomei(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9printSomeii, .-_Z27__device_stub__Z9printSomeii
.globl _Z9printSomei
.type _Z9printSomei, @function
_Z9printSomei:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9printSomeii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9printSomei, .-_Z9printSomei
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbp
leaq 72(%rsp), %r12
movq %rbp, %rbx
.L12:
movq %rbx, %rdi
call cudaStreamCreate@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L12
movl $0, %ebx
jmp .L14
.L13:
addq $1, %rbx
cmpq $5, %rbx
je .L15
.L14:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movq 32(%rsp,%rbx,8), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl %ebx, %edi
call _Z27__device_stub__Z9printSomeii
jmp .L13
.L15:
movq 0(%rbp), %rdi
call cudaStreamDestroy@PLT
addq $8, %rbp
cmpq %r12, %rbp
jne .L15
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9printSomei"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9printSomei(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //imports
#include <stdio.h>
#include <math.h>
#include <cuda.h>
#include <stdlib.h>
__global__ void printSome(int i){
printf("%d",i);
}
int main(){
cudaStream_t streams[5];
int i;
for(i=0;i<5;i++){
cudaStreamCreate(&streams[i]);
}
for(i=0;i<5;i++){
printSome<<<1,1,0,streams[i]>>>(i);
}
for(i=0;i<5;i++){
cudaStreamDestroy(streams[i]);
}
return 0;
} | //imports
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
__global__ void printSome(int i){
printf("%d",i);
}
int main(){
hipStream_t streams[5];
int i;
for(i=0;i<5;i++){
hipStreamCreate(&streams[i]);
}
for(i=0;i<5;i++){
printSome<<<1,1,0,streams[i]>>>(i);
}
for(i=0;i<5;i++){
hipStreamDestroy(streams[i]);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //imports
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
__global__ void printSome(int i){
printf("%d",i);
}
int main(){
hipStream_t streams[5];
int i;
for(i=0;i<5;i++){
hipStreamCreate(&streams[i]);
}
for(i=0;i<5;i++){
printSome<<<1,1,0,streams[i]>>>(i);
}
for(i=0;i<5;i++){
hipStreamDestroy(streams[i]);
}
return 0;
} | .text
.file "handout.hip"
.globl _Z24__device_stub__printSomei # -- Begin function _Z24__device_stub__printSomei
.p2align 4, 0x90
.type _Z24__device_stub__printSomei,@function
_Z24__device_stub__printSomei: # @_Z24__device_stub__printSomei
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9printSomei, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__printSomei, .Lfunc_end0-_Z24__device_stub__printSomei
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $80, %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $40, %rbx
jne .LBB1_1
# %bb.2: # %.preheader15
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %r14d, %r14d
leaq 48(%rsp), %r15
leaq 40(%rsp), %r12
leaq 32(%rsp), %r13
leaq 16(%rsp), %rbp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
incq %r14
cmpq $5, %r14
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 80(%rsp,%r14,8), %r9
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movl %r14d, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z9printSomei, %edi
movq %rbp, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 80(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $5, %rbx
jne .LBB1_7
# %bb.8:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9printSomei, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9printSomei,@object # @_Z9printSomei
.section .rodata,"a",@progbits
.globl _Z9printSomei
.p2align 3, 0x0
_Z9printSomei:
.quad _Z24__device_stub__printSomei
.size _Z9printSomei, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9printSomei"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__printSomei
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9printSomei
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00025f2b_00000000-6_handout.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z9printSomeii
.type _Z27__device_stub__Z9printSomeii, @function
_Z27__device_stub__Z9printSomeii:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movl %edi, 12(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9printSomei(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z27__device_stub__Z9printSomeii, .-_Z27__device_stub__Z9printSomeii
.globl _Z9printSomei
.type _Z9printSomei, @function
_Z9printSomei:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z9printSomeii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z9printSomei, .-_Z9printSomei
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rbp
leaq 72(%rsp), %r12
movq %rbp, %rbx
.L12:
movq %rbx, %rdi
call cudaStreamCreate@PLT
addq $8, %rbx
cmpq %r12, %rbx
jne .L12
movl $0, %ebx
jmp .L14
.L13:
addq $1, %rbx
cmpq $5, %rbx
je .L15
.L14:
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movq 32(%rsp,%rbx,8), %r9
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
movl %ebx, %edi
call _Z27__device_stub__Z9printSomeii
jmp .L13
.L15:
movq 0(%rbp), %rdi
call cudaStreamDestroy@PLT
addq $8, %rbp
cmpq %r12, %rbp
jne .L15
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9printSomei"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9printSomei(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "handout.hip"
.globl _Z24__device_stub__printSomei # -- Begin function _Z24__device_stub__printSomei
.p2align 4, 0x90
.type _Z24__device_stub__printSomei,@function
_Z24__device_stub__printSomei: # @_Z24__device_stub__printSomei
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movl %edi, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z9printSomei, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z24__device_stub__printSomei, .Lfunc_end0-_Z24__device_stub__printSomei
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $80, %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $40, %rbx
jne .LBB1_1
# %bb.2: # %.preheader15
movabsq $4294967297, %rbx # imm = 0x100000001
xorl %r14d, %r14d
leaq 48(%rsp), %r15
leaq 40(%rsp), %r12
leaq 32(%rsp), %r13
leaq 16(%rsp), %rbp
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
incq %r14
cmpq $5, %r14
je .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 80(%rsp,%r14,8), %r9
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movl %r14d, 12(%rsp)
leaq 12(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rdi
movq %r15, %rsi
movq %r12, %rdx
movq %r13, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z9printSomei, %edi
movq %rbp, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_7: # %.preheader
# =>This Inner Loop Header: Depth=1
movq 80(%rsp,%rbx,8), %rdi
callq hipStreamDestroy
incq %rbx
cmpq $5, %rbx
jne .LBB1_7
# %bb.8:
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9printSomei, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9printSomei,@object # @_Z9printSomei
.section .rodata,"a",@progbits
.globl _Z9printSomei
.p2align 3, 0x0
_Z9printSomei:
.quad _Z24__device_stub__printSomei
.size _Z9printSomei, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9printSomei"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__printSomei
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9printSomei
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // includes, system
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
// includes, project
#include <cuda_runtime.h>
#include <cufft.h>
#include <cufftXt.h>
// Complex data type
typedef float2 Complex;
static __host__ inline float ComplexAbs(Complex);
//This is the number of data points and stuff
#define N 50
constexpr double Pi = 3.14159265358979323846;
//this is the function we're transforming
float f(float t)
{
return sin(2*Pi*t);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
//memory for the function we're transforming
Complex* h_fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
for (unsigned int i = 0; i < N; i++) //initializing
{
h_fvalues[i].x = f(i * 1.0 / N);
h_fvalues[i].y = 0;
}
//device memory for the signal
Complex* d_fvalues;
cudaMalloc(reinterpret_cast<void**>(&d_fvalues), sizeof(Complex)*N);
//copy host memory to device
cudaMemcpy(d_fvalues, h_fvalues, sizeof(Complex)*N, cudaMemcpyHostToDevice);
//setting up the plan
cufftHandle plan;
cufftPlan1d(&plan, sizeof(Complex)*N, CUFFT_C2C,1);
//execute plan. This transforms the signal in place.
cufftExecC2C(plan, d_fvalues, d_fvalues, CUFFT_FORWARD);
//copying the results back onto the host
Complex* h_Fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
cudaMemcpy(h_Fvalues, d_fvalues, sizeof(Complex) * N, cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < N; i++)
{
std::cout << "i: " << i << " Re(F): " << h_Fvalues[i].x/N << " Im(F): " << h_Fvalues[i].y/100 << " |F|: " << ComplexAbs(h_Fvalues[i])/100 << std::endl;
}
free(h_fvalues);
cudaFree(d_fvalues);
free(h_Fvalues);
return 0;
}
//Complex absolute value
static __host__ inline float ComplexAbs(Complex a)
{
return sqrt(a.x * a.x + a.y * a.y);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // includes, system
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
// includes, project
#include <cuda_runtime.h>
#include <cufft.h>
#include <cufftXt.h>
// Complex data type
typedef float2 Complex;
static __host__ inline float ComplexAbs(Complex);
//This is the number of data points and stuff
#define N 50
constexpr double Pi = 3.14159265358979323846;
//this is the function we're transforming
float f(float t)
{
return sin(2*Pi*t);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
//memory for the function we're transforming
Complex* h_fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
for (unsigned int i = 0; i < N; i++) //initializing
{
h_fvalues[i].x = f(i * 1.0 / N);
h_fvalues[i].y = 0;
}
//device memory for the signal
Complex* d_fvalues;
cudaMalloc(reinterpret_cast<void**>(&d_fvalues), sizeof(Complex)*N);
//copy host memory to device
cudaMemcpy(d_fvalues, h_fvalues, sizeof(Complex)*N, cudaMemcpyHostToDevice);
//setting up the plan
cufftHandle plan;
cufftPlan1d(&plan, sizeof(Complex)*N, CUFFT_C2C,1);
//execute plan. This transforms the signal in place.
cufftExecC2C(plan, d_fvalues, d_fvalues, CUFFT_FORWARD);
//copying the results back onto the host
Complex* h_Fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
cudaMemcpy(h_Fvalues, d_fvalues, sizeof(Complex) * N, cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < N; i++)
{
std::cout << "i: " << i << " Re(F): " << h_Fvalues[i].x/N << " Im(F): " << h_Fvalues[i].y/100 << " |F|: " << ComplexAbs(h_Fvalues[i])/100 << std::endl;
}
free(h_fvalues);
cudaFree(d_fvalues);
free(h_Fvalues);
return 0;
}
//Complex absolute value
static __host__ inline float ComplexAbs(Complex a)
{
return sqrt(a.x * a.x + a.y * a.y);
} | .file "tmpxft_000fe0dc_00000000-6_CUFFT_Test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ff
.type _Z1ff, @function
_Z1ff:
.LFB3693:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
cvtss2sd %xmm0, %xmm0
mulsd .LC0(%rip), %xmm0
call sin@PLT
cvtsd2ss %xmm0, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3693:
.size _Z1ff, .-_Z1ff
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "i: "
.LC4:
.string " Re(F): "
.LC6:
.string " Im(F): "
.LC8:
.string " |F|: "
.text
.globl main
.type main, @function
main:
.LFB3694:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %ebx
.L8:
movl %ebx, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
call _Z1ff
movss %xmm0, (%r14,%rbx,8)
movl $0x00000000, 4(%r14,%rbx,8)
addq $1, %rbx
cmpq $50, %rbx
jne .L8
leaq 16(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rdi
movl $1, %ecx
movl $41, %edx
movl $400, %esi
call cufftPlan1d@PLT
movq 16(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 12(%rsp), %edi
call cufftExecC2C@PLT
movl $400, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movl $400, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r15
jmp .L13
.L20:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L18
call _ZSt16__throw_bad_castv@PLT
.L18:
call __stack_chk_fail@PLT
.L11:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L12:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $50, %rbx
je .L19
.L13:
movl $3, %edx
leaq .LC3(%rip), %rsi
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbx, %rsi
movq %r15, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movss 0(%r13,%rbx,8), %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movss 4(%r13,%rbx,8), %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $6, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movss 0(%r13,%rbx,8), %xmm0
movss 4(%r13,%rbx,8), %xmm1
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L20
cmpb $0, 56(%r12)
je .L11
movzbl 67(%r12), %esi
jmp .L12
.L19:
movq %r14, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3721:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3721:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1075388923
.align 8
.LC1:
.long 0
.long 1078525952
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1112014848
.align 4
.LC7:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // includes, system
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
// includes, project
#include <cuda_runtime.h>
#include <cufft.h>
#include <cufftXt.h>
// Complex data type
typedef float2 Complex;
static __host__ inline float ComplexAbs(Complex);
//This is the number of data points and stuff
#define N 50
constexpr double Pi = 3.14159265358979323846;
//this is the function we're transforming
float f(float t)
{
return sin(2*Pi*t);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
//memory for the function we're transforming
Complex* h_fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
for (unsigned int i = 0; i < N; i++) //initializing
{
h_fvalues[i].x = f(i * 1.0 / N);
h_fvalues[i].y = 0;
}
//device memory for the signal
Complex* d_fvalues;
cudaMalloc(reinterpret_cast<void**>(&d_fvalues), sizeof(Complex)*N);
//copy host memory to device
cudaMemcpy(d_fvalues, h_fvalues, sizeof(Complex)*N, cudaMemcpyHostToDevice);
//setting up the plan
cufftHandle plan;
cufftPlan1d(&plan, sizeof(Complex)*N, CUFFT_C2C,1);
//execute plan. This transforms the signal in place.
cufftExecC2C(plan, d_fvalues, d_fvalues, CUFFT_FORWARD);
//copying the results back onto the host
Complex* h_Fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
cudaMemcpy(h_Fvalues, d_fvalues, sizeof(Complex) * N, cudaMemcpyDeviceToHost);
for (unsigned int i = 0; i < N; i++)
{
std::cout << "i: " << i << " Re(F): " << h_Fvalues[i].x/N << " Im(F): " << h_Fvalues[i].y/100 << " |F|: " << ComplexAbs(h_Fvalues[i])/100 << std::endl;
}
free(h_fvalues);
cudaFree(d_fvalues);
free(h_Fvalues);
return 0;
}
//Complex absolute value
static __host__ inline float ComplexAbs(Complex a)
{
return sqrt(a.x * a.x + a.y * a.y);
} | // includes, system
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
// includes, project
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hipfft/hipfftXt.h>
// Complex data type
typedef float2 Complex;
static __host__ inline float ComplexAbs(Complex);
//This is the number of data points and stuff
#define N 50
constexpr double Pi = 3.14159265358979323846;
//this is the function we're transforming
float f(float t)
{
return sin(2*Pi*t);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
//memory for the function we're transforming
Complex* h_fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
for (unsigned int i = 0; i < N; i++) //initializing
{
h_fvalues[i].x = f(i * 1.0 / N);
h_fvalues[i].y = 0;
}
//device memory for the signal
Complex* d_fvalues;
hipMalloc(reinterpret_cast<void**>(&d_fvalues), sizeof(Complex)*N);
//copy host memory to device
hipMemcpy(d_fvalues, h_fvalues, sizeof(Complex)*N, hipMemcpyHostToDevice);
//setting up the plan
hipfftHandle plan;
hipfftPlan1d(&plan, sizeof(Complex)*N, HIPFFT_C2C,1);
//execute plan. This transforms the signal in place.
hipfftExecC2C(plan, d_fvalues, d_fvalues, HIPFFT_FORWARD);
//copying the results back onto the host
Complex* h_Fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
hipMemcpy(h_Fvalues, d_fvalues, sizeof(Complex) * N, hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < N; i++)
{
std::cout << "i: " << i << " Re(F): " << h_Fvalues[i].x/N << " Im(F): " << h_Fvalues[i].y/100 << " |F|: " << ComplexAbs(h_Fvalues[i])/100 << std::endl;
}
free(h_fvalues);
hipFree(d_fvalues);
free(h_Fvalues);
return 0;
}
//Complex absolute value
static __host__ inline float ComplexAbs(Complex a)
{
return sqrt(a.x * a.x + a.y * a.y);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // includes, system
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
// includes, project
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hipfft/hipfftXt.h>
// Complex data type
typedef float2 Complex;
static __host__ inline float ComplexAbs(Complex);
//This is the number of data points and stuff
#define N 50
constexpr double Pi = 3.14159265358979323846;
//this is the function we're transforming
float f(float t)
{
return sin(2*Pi*t);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
//memory for the function we're transforming
Complex* h_fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
for (unsigned int i = 0; i < N; i++) //initializing
{
h_fvalues[i].x = f(i * 1.0 / N);
h_fvalues[i].y = 0;
}
//device memory for the signal
Complex* d_fvalues;
hipMalloc(reinterpret_cast<void**>(&d_fvalues), sizeof(Complex)*N);
//copy host memory to device
hipMemcpy(d_fvalues, h_fvalues, sizeof(Complex)*N, hipMemcpyHostToDevice);
//setting up the plan
hipfftHandle plan;
hipfftPlan1d(&plan, sizeof(Complex)*N, HIPFFT_C2C,1);
//execute plan. This transforms the signal in place.
hipfftExecC2C(plan, d_fvalues, d_fvalues, HIPFFT_FORWARD);
//copying the results back onto the host
Complex* h_Fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
hipMemcpy(h_Fvalues, d_fvalues, sizeof(Complex) * N, hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < N; i++)
{
std::cout << "i: " << i << " Re(F): " << h_Fvalues[i].x/N << " Im(F): " << h_Fvalues[i].y/100 << " |F|: " << ComplexAbs(h_Fvalues[i])/100 << std::endl;
}
free(h_fvalues);
hipFree(d_fvalues);
free(h_Fvalues);
return 0;
}
//Complex absolute value
static __host__ inline float ComplexAbs(Complex a)
{
return sqrt(a.x * a.x + a.y * a.y);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // includes, system
#include <math.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <iostream>
// includes, project
#include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hipfft/hipfftXt.h>
// Complex data type
typedef float2 Complex;
static __host__ inline float ComplexAbs(Complex);
//This is the number of data points and stuff
#define N 50
constexpr double Pi = 3.14159265358979323846;
//this is the function we're transforming
float f(float t)
{
return sin(2*Pi*t);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv) {
//memory for the function we're transforming
Complex* h_fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
for (unsigned int i = 0; i < N; i++) //initializing
{
h_fvalues[i].x = f(i * 1.0 / N);
h_fvalues[i].y = 0;
}
//device memory for the signal
Complex* d_fvalues;
hipMalloc(reinterpret_cast<void**>(&d_fvalues), sizeof(Complex)*N);
//copy host memory to device
hipMemcpy(d_fvalues, h_fvalues, sizeof(Complex)*N, hipMemcpyHostToDevice);
//setting up the plan
hipfftHandle plan;
hipfftPlan1d(&plan, sizeof(Complex)*N, HIPFFT_C2C,1);
//execute plan. This transforms the signal in place.
hipfftExecC2C(plan, d_fvalues, d_fvalues, HIPFFT_FORWARD);
//copying the results back onto the host
Complex* h_Fvalues = reinterpret_cast<Complex*>(malloc(sizeof(Complex) * N));
hipMemcpy(h_Fvalues, d_fvalues, sizeof(Complex) * N, hipMemcpyDeviceToHost);
for (unsigned int i = 0; i < N; i++)
{
std::cout << "i: " << i << " Re(F): " << h_Fvalues[i].x/N << " Im(F): " << h_Fvalues[i].y/100 << " |F|: " << ComplexAbs(h_Fvalues[i])/100 << std::endl;
}
free(h_fvalues);
hipFree(d_fvalues);
free(h_Fvalues);
return 0;
}
//Complex absolute value
static __host__ inline float ComplexAbs(Complex a)
{
return sqrt(a.x * a.x + a.y * a.y);
} | .text
.file "CUFFT_Test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z1ff
.LCPI0_0:
.quad 0x401921fb54442d18 # double 6.2831853071795862
.text
.globl _Z1ff
.p2align 4, 0x90
.type _Z1ff,@function
_Z1ff: # @_Z1ff
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cvtss2sd %xmm0, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
callq sin
cvtsd2ss %xmm0, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z1ff, .Lfunc_end0-_Z1ff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4049000000000000 # double 50
.LCPI1_1:
.quad 0x401921fb54442d18 # double 6.2831853071795862
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_2:
.long 0x42480000 # float 50
.LCPI1_3:
.long 0x42c80000 # float 100
.LCPI1_4:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r14d, %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
callq sin
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r14,8)
movl $0, 4(%rbx,%r14,8)
incq %r14
cmpq $50, %r14
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
movl $41, %edx
movl $1, %ecx
callq hipfftPlan1d
movq 24(%rsp), %rdi
movq 8(%rsp), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_3 Depth=1
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_3 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $50, %r15
je .LBB1_11
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.2, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.3, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rsp)
movss 16(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
mulss %xmm0, %xmm0
addss %xmm1, %xmm0
ucomiss .LCPI1_4(%rip), %xmm0
jb .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_5: # %call.sqrt
# in Loop: Header=BB1_3 Depth=1
callq sqrtf
.LBB1_6: # %.split
# in Loop: Header=BB1_3 Depth=1
divss .LCPI1_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_12
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_3 Depth=1
cmpb $0, 56(%r12)
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_3 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_10
.LBB1_11:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i: "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Re(F): "
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Im(F): "
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " |F|: "
.size .L.str.3, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fe0dc_00000000-6_CUFFT_Test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z1ff
.type _Z1ff, @function
_Z1ff:
.LFB3693:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
cvtss2sd %xmm0, %xmm0
mulsd .LC0(%rip), %xmm0
call sin@PLT
cvtsd2ss %xmm0, %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3693:
.size _Z1ff, .-_Z1ff
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "i: "
.LC4:
.string " Re(F): "
.LC6:
.string " Im(F): "
.LC8:
.string " |F|: "
.text
.globl main
.type main, @function
main:
.LFB3694:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movl $400, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %ebx
.L8:
movl %ebx, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC1(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
call _Z1ff
movss %xmm0, (%r14,%rbx,8)
movl $0x00000000, 4(%r14,%rbx,8)
addq $1, %rbx
cmpq $50, %rbx
jne .L8
leaq 16(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $400, %edx
movq %r14, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 12(%rsp), %rdi
movl $1, %ecx
movl $41, %edx
movl $400, %esi
call cufftPlan1d@PLT
movq 16(%rsp), %rsi
movl $-1, %ecx
movq %rsi, %rdx
movl 12(%rsp), %edi
call cufftExecC2C@PLT
movl $400, %edi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movl $400, %edx
movq 16(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq _ZSt4cout(%rip), %r15
jmp .L13
.L20:
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L18
call _ZSt16__throw_bad_castv@PLT
.L18:
call __stack_chk_fail@PLT
.L11:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
.L12:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $1, %rbx
cmpq $50, %rbx
je .L19
.L13:
movl $3, %edx
leaq .LC3(%rip), %rsi
movq %r15, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rbx, %rsi
movq %r15, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC4(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movss 0(%r13,%rbx,8), %xmm0
divss .LC5(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $8, %edx
leaq .LC6(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movss 4(%r13,%rbx,8), %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $6, %edx
leaq .LC8(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movss 0(%r13,%rbx,8), %xmm0
movss 4(%r13,%rbx,8), %xmm1
mulss %xmm0, %xmm0
mulss %xmm1, %xmm1
addss %xmm1, %xmm0
sqrtss %xmm0, %xmm0
divss .LC7(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L20
cmpb $0, 56(%r12)
je .L11
movzbl 67(%r12), %esi
jmp .L12
.L19:
movq %r14, %rdi
call free@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq %r13, %rdi
call free@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3721:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3721:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 1413754136
.long 1075388923
.align 8
.LC1:
.long 0
.long 1078525952
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 1112014848
.align 4
.LC7:
.long 1120403456
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUFFT_Test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z1ff
.LCPI0_0:
.quad 0x401921fb54442d18 # double 6.2831853071795862
.text
.globl _Z1ff
.p2align 4, 0x90
.type _Z1ff,@function
_Z1ff: # @_Z1ff
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
cvtss2sd %xmm0, %xmm0
mulsd .LCPI0_0(%rip), %xmm0
callq sin
cvtsd2ss %xmm0, %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z1ff, .Lfunc_end0-_Z1ff
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x4049000000000000 # double 50
.LCPI1_1:
.quad 0x401921fb54442d18 # double 6.2831853071795862
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_2:
.long 0x42480000 # float 50
.LCPI1_3:
.long 0x42c80000 # float 100
.LCPI1_4:
.long 0x00000000 # float 0
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %r14d, %eax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
mulsd .LCPI1_1(%rip), %xmm0
callq sin
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%rbx,%r14,8)
movl $0, 4(%rbx,%r14,8)
incq %r14
cmpq $50, %r14
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
movq 8(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 24(%rsp), %rdi
movl $400, %esi # imm = 0x190
movl $41, %edx
movl $1, %ecx
callq hipfftPlan1d
movq 24(%rsp), %rdi
movq 8(%rsp), %rdx
movq %rdx, %rsi
movl $-1, %ecx
callq hipfftExecC2C
movl $400, %edi # imm = 0x190
callq malloc
movq %rax, %r14
movq 8(%rsp), %rsi
movl $400, %edx # imm = 0x190
movq %rax, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r15d, %r15d
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_9: # in Loop: Header=BB1_3 Depth=1
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB1_3 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
cmpq $50, %r15
je .LBB1_11
.LBB1_3: # =>This Inner Loop Header: Depth=1
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $3, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.2, %esi
movl $8, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 4(%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.3, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movsd (%r14,%r15,8), %xmm0 # xmm0 = mem[0],zero
movsd %xmm0, 16(%rsp)
movss 16(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
movss 20(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss %xmm1, %xmm1
mulss %xmm0, %xmm0
addss %xmm1, %xmm0
ucomiss .LCPI1_4(%rip), %xmm0
jb .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
sqrtss %xmm0, %xmm0
jmp .LBB1_6
.p2align 4, 0x90
.LBB1_5: # %call.sqrt
# in Loop: Header=BB1_3 Depth=1
callq sqrtf
.LBB1_6: # %.split
# in Loop: Header=BB1_3 Depth=1
divss .LCPI1_3(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_12
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB1_3 Depth=1
cmpb $0, 56(%r12)
je .LBB1_9
# %bb.8: # in Loop: Header=BB1_3 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_10
.LBB1_11:
movq %rbx, %rdi
callq free
movq 8(%rsp), %rdi
callq hipFree
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_12:
.cfi_def_cfa_offset 80
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "i: "
.size .L.str, 4
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Re(F): "
.size .L.str.1, 9
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Im(F): "
.size .L.str.2, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " |F|: "
.size .L.str.3, 7
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define NUMBER_OF_BLOCKS 256
#define NUMBER_OF_THREADS 64
// ==========
// Macro taken from:
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__device__ int getElementsPerUnit(int total, int number_of_units) {
int elements_per_unit = total / number_of_units;
double remains = total % number_of_units;
if(remains != 0) {
elements_per_unit += 1;
}
return elements_per_unit;
}
__global__ void normKernel(double *vectors, int size, double *results, int vector_size) {
int vectors_per_block = getElementsPerUnit(size, gridDim.x);
// Get range of vectors we will work with
int start = blockIdx.x * vectors_per_block;
int end = start + vectors_per_block;
if(end > size) {
end = size;
}
for(int vec_index = start; vec_index < end; vec_index++) {
for(int i = 0; i < vector_size; i++) {
results[vec_index] += pow(vectors[vec_index*vector_size + i], 2);
}
results[vec_index] = sqrt(results[vec_index]);
}
} | .file "tmpxft_0002b362_00000000-6_normKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18getElementsPerUnitii
.type _Z18getElementsPerUnitii, @function
_Z18getElementsPerUnitii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z18getElementsPerUnitii, .-_Z18getElementsPerUnitii
.globl _Z34__device_stub__Z10normKernelPdiS_iPdiS_i
.type _Z34__device_stub__Z10normKernelPdiS_iPdiS_i, @function
_Z34__device_stub__Z10normKernelPdiS_iPdiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10normKernelPdiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z34__device_stub__Z10normKernelPdiS_iPdiS_i, .-_Z34__device_stub__Z10normKernelPdiS_iPdiS_i
.globl _Z10normKernelPdiS_i
.type _Z10normKernelPdiS_i, @function
_Z10normKernelPdiS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10normKernelPdiS_iPdiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10normKernelPdiS_i, .-_Z10normKernelPdiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10normKernelPdiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10normKernelPdiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define NUMBER_OF_BLOCKS 256
#define NUMBER_OF_THREADS 64
// ==========
// Macro taken from:
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__device__ int getElementsPerUnit(int total, int number_of_units) {
int elements_per_unit = total / number_of_units;
double remains = total % number_of_units;
if(remains != 0) {
elements_per_unit += 1;
}
return elements_per_unit;
}
__global__ void normKernel(double *vectors, int size, double *results, int vector_size) {
int vectors_per_block = getElementsPerUnit(size, gridDim.x);
// Get range of vectors we will work with
int start = blockIdx.x * vectors_per_block;
int end = start + vectors_per_block;
if(end > size) {
end = size;
}
for(int vec_index = start; vec_index < end; vec_index++) {
for(int i = 0; i < vector_size; i++) {
results[vec_index] += pow(vectors[vec_index*vector_size + i], 2);
}
results[vec_index] = sqrt(results[vec_index]);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUMBER_OF_BLOCKS 256
#define NUMBER_OF_THREADS 64
// ==========
// Macro taken from:
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__device__ int getElementsPerUnit(int total, int number_of_units) {
int elements_per_unit = total / number_of_units;
double remains = total % number_of_units;
if(remains != 0) {
elements_per_unit += 1;
}
return elements_per_unit;
}
__global__ void normKernel(double *vectors, int size, double *results, int vector_size) {
int vectors_per_block = getElementsPerUnit(size, gridDim.x);
// Get range of vectors we will work with
int start = blockIdx.x * vectors_per_block;
int end = start + vectors_per_block;
if(end > size) {
end = size;
}
for(int vec_index = start; vec_index < end; vec_index++) {
for(int i = 0; i < vector_size; i++) {
results[vec_index] += pow(vectors[vec_index*vector_size + i], 2);
}
results[vec_index] = sqrt(results[vec_index]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUMBER_OF_BLOCKS 256
#define NUMBER_OF_THREADS 64
// ==========
// Macro taken from:
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__device__ int getElementsPerUnit(int total, int number_of_units) {
int elements_per_unit = total / number_of_units;
double remains = total % number_of_units;
if(remains != 0) {
elements_per_unit += 1;
}
return elements_per_unit;
}
__global__ void normKernel(double *vectors, int size, double *results, int vector_size) {
int vectors_per_block = getElementsPerUnit(size, gridDim.x);
// Get range of vectors we will work with
int start = blockIdx.x * vectors_per_block;
int end = start + vectors_per_block;
if(end > size) {
end = size;
}
for(int vec_index = start; vec_index < end; vec_index++) {
for(int i = 0; i < vector_size; i++) {
results[vec_index] += pow(vectors[vec_index*vector_size + i], 2);
}
results[vec_index] = sqrt(results[vec_index]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10normKernelPdiS_i
.globl _Z10normKernelPdiS_i
.p2align 8
.type _Z10normKernelPdiS_i,@function
_Z10normKernelPdiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x20
s_load_b32 s5, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
s_ashr_i32 s8, s5, 31
s_add_i32 s4, s2, s3
s_add_i32 s9, s5, s8
s_xor_b32 s4, s4, s3
s_xor_b32 s9, s9, s8
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s7, 0, s4
s_xor_b32 s3, s8, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s6, v0
s_mul_i32 s7, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s7, s6, s7
s_add_i32 s6, s6, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_hi_u32 s6, s9, s6
s_mul_i32 s7, s6, s4
s_add_i32 s8, s6, 1
s_sub_i32 s7, s9, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, s7, s4
s_cmp_ge_u32 s7, s4
s_cselect_b32 s6, s8, s6
s_cselect_b32 s7, s9, s7
s_add_i32 s8, s6, 1
s_cmp_ge_u32 s7, s4
s_cselect_b32 s4, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s4, s4, s3
s_sub_i32 s3, s4, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s3, s2
s_sub_i32 s2, s5, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_cmp_lg_u32 s2, 0
s_cselect_b32 s6, -1, 0
s_cmp_lg_u32 s6, 0
s_addc_u32 s2, s3, 0
s_cmp_lg_u32 s6, 0
s_mul_i32 s4, s2, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_addc_u32 s3, s4, s3
s_min_i32 s33, s3, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s4, s33
s_cbranch_scc1 .LBB0_6
s_clause 0x2
s_load_b32 s70, s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
v_mov_b32_e32 v2, 0
s_mov_b32 s11, 0x3fe55555
s_mov_b32 s10, 0x55555555
s_mov_b32 s13, 0x3fba6564
s_mov_b32 s12, 0x968915a9
s_mov_b32 s17, 0x3fbdee67
s_mov_b32 s16, 0x4222de17
s_mov_b32 s19, 0x3fbe25e4
s_mov_b32 s18, 0x3abe935a
s_mov_b32 s21, 0x3fc110ef
s_mov_b32 s20, 0x47e6c9c2
s_mov_b32 s23, 0x3fc3b13b
s_mov_b32 s22, 0xcfa74449
s_mov_b32 s25, 0x3fc745d1
s_mov_b32 s24, 0x71bf3c30
s_mov_b32 s27, 0x3fcc71c7
s_mov_b32 s26, 0x1c7792ce
s_waitcnt lgkmcnt(0)
s_cmp_gt_i32 s70, 0
s_mov_b32 s29, 0x3fd24924
s_cselect_b32 s0, -1, 0
s_mov_b32 s28, 0x924920da
v_cndmask_b32_e64 v0, 0, 1, s0
s_mul_i32 s0, s15, s70
s_mov_b32 s31, 0x3fd99999
s_mul_i32 s14, s0, s2
s_mov_b32 s30, 0x9999999c
v_cmp_ne_u32_e64 s0, 1, v0
s_mov_b32 s35, 0x3fe62e42
s_mov_b32 s34, 0xfefa39ef
s_mov_b32 s37, 0x3c7abc9e
s_mov_b32 s36, 0x3b39803f
s_mov_b32 s3, 0xbfe55555
s_mov_b32 s39, 0x3c8543b0
s_mov_b32 s38, 0xd5df274d
s_mov_b32 s41, 0x3ff71547
s_mov_b32 s40, 0x652b82fe
s_mov_b32 s43, 0xbfe62e42
s_mov_b32 s45, 0xbc7abc9e
s_mov_b32 s47, 0x3e928af3
s_mov_b32 s46, 0xfca7ab0c
s_mov_b32 s49, 0x3e5ade15
s_mov_b32 s48, 0x6a5dcb37
s_mov_b32 s51, 0x3ec71dee
s_mov_b32 s50, 0x623fde64
s_mov_b32 s53, 0x3efa0199
s_mov_b32 s52, 0x7c89e6b0
s_mov_b32 s55, 0x3f2a01a0
s_mov_b32 s54, 0x14761f6e
s_mov_b32 s57, 0x3f56c16c
s_mov_b32 s56, 0x1852b7b0
s_mov_b32 s59, 0x3f811111
s_mov_b32 s58, 0x11122322
s_mov_b32 s61, 0x3fa55555
s_mov_b32 s60, 0x555502a1
s_mov_b32 s63, 0x3fc55555
s_mov_b32 s62, 0x55555511
s_mov_b32 s65, 0x3fe00000
s_mov_b32 s64, 11
s_branch .LBB0_3
.LBB0_2:
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[66:67], s[4:5], 3
s_add_u32 s66, s8, s66
s_addc_u32 s67, s9, s67
global_load_b64 v[0:1], v2, s[66:67]
s_waitcnt vmcnt(0)
v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_and_b32 s1, vcc_lo, exec_lo
s_cselect_b32 s1, 0xffffff80, 0
s_add_i32 s4, s4, 1
s_add_i32 s14, s14, s70
v_lshlrev_b32_e32 v3, 8, v3
s_cmp_ge_i32 s4, s33
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[0:1], v[0:1], v3
v_rsq_f64_e32 v[3:4], v[0:1]
v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
s_waitcnt_depctr 0xfff
v_mul_f64 v[5:6], v[0:1], v[3:4]
v_mul_f64 v[3:4], v[3:4], 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[3:4], v[5:6], 0.5
v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
v_fma_f64 v[3:4], v[3:4], v[7:8], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[0:1]
v_fma_f64 v[5:6], v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], -v[5:6], v[5:6], v[0:1]
v_fma_f64 v[3:4], v[7:8], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], s1
v_dual_cndmask_b32 v1, v4, v1 :: v_dual_cndmask_b32 v0, v3, v0
global_store_b64 v2, v[0:1], s[66:67]
s_cbranch_scc1 .LBB0_6
.LBB0_3:
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
s_ashr_i32 s15, s14, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[66:67], s[14:15], 3
s_add_u32 s66, s6, s66
s_addc_u32 s67, s7, s67
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[68:69], s[4:5], 3
s_mov_b32 s5, s70
s_add_u32 s68, s8, s68
s_addc_u32 s69, s9, s69
global_load_b64 v[0:1], v2, s[68:69]
.LBB0_5:
global_load_b64 v[3:4], v2, s[66:67]
s_mov_b32 s2, s10
s_mov_b32 s42, s34
s_mov_b32 s44, s36
s_add_i32 s5, s5, -1
s_waitcnt vmcnt(0)
v_frexp_mant_f64_e64 v[5:6], |v[3:4]|
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_gt_f64_e32 vcc_lo, s[10:11], v[5:6]
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
v_ldexp_f64 v[5:6], v[5:6], v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[5:6], 1.0
v_add_f64 v[13:14], v[5:6], -1.0
v_rcp_f64_e32 v[9:10], v[7:8]
v_add_f64 v[15:16], v[7:8], -1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[5:6], -v[15:16]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[11:12], v[13:14], v[9:10]
v_mul_f64 v[17:18], v[7:8], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[11:12], v[7:8], -v[17:18]
v_fma_f64 v[5:6], v[11:12], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[17:18], v[5:6]
v_add_f64 v[15:16], v[13:14], -v[7:8]
v_add_f64 v[17:18], v[7:8], -v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[13:14], -v[15:16]
v_add_f64 v[5:6], v[17:18], -v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[13:14], -v[7:8]
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[15:16], v[5:6]
v_mul_f64 v[5:6], v[9:10], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[11:12], v[5:6]
v_add_f64 v[9:10], v[7:8], -v[11:12]
v_mul_f64 v[11:12], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[9:10]
v_fma_f64 v[9:10], v[7:8], v[7:8], -v[11:12]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[13:14], v[5:6], v[5:6]
v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[13:14], v[11:12], v[9:10]
v_fma_f64 v[15:16], v[13:14], s[16:17], s[12:13]
v_add_f64 v[11:12], v[13:14], -v[11:12]
v_mul_f64 v[19:20], v[7:8], v[13:14]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[18:19]
v_add_f64 v[9:10], v[9:10], -v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f64 v[23:24], v[13:14], v[7:8], -v[19:20]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[20:21]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[22:23]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[24:25]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[26:27]
v_fma_f64 v[15:16], v[13:14], v[15:16], s[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[15:16], v[13:14], v[15:16], s[30:31]
v_mul_f64 v[17:18], v[13:14], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f64 v[11:12], v[13:14], v[15:16], -v[17:18]
v_fma_f64 v[13:14], v[13:14], v[5:6], v[23:24]
v_ldexp_f64 v[5:6], v[5:6], 1
v_fma_f64 v[11:12], v[9:10], v[15:16], v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f64 v[9:10], v[9:10], v[7:8], v[13:14]
v_ldexp_f64 v[7:8], v[7:8], 1
v_add_f64 v[15:16], v[17:18], v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[19:20], v[9:10]
v_add_f64 v[21:22], v[15:16], s[10:11]
v_add_f64 v[17:18], v[15:16], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[19:20], v[13:14], -v[19:20]
v_add_f64 v[25:26], v[21:22], s[2:3]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[11:12], v[11:12], -v[17:18]
v_add_f64 v[9:10], v[9:10], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[15:16], v[15:16], -v[25:26]
v_add_f64 v[11:12], v[11:12], s[38:39]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[11:12], v[11:12], v[15:16]
v_add_f64 v[15:16], v[21:22], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[17:18], v[21:22], -v[15:16]
v_mul_f64 v[21:22], v[13:14], v[15:16]
v_add_f64 v[11:12], v[11:12], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[13:14], v[15:16], -v[21:22]
v_fma_f64 v[11:12], v[13:14], v[11:12], v[17:18]
v_frexp_exp_i32_f64_e32 v13, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], v[9:10], v[15:16], v[11:12]
v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_f64_i32_e32 v[13:14], v13
v_add_f64 v[11:12], v[21:22], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[19:20], v[13:14], s[34:35]
v_add_f64 v[15:16], v[7:8], v[11:12]
v_add_f64 v[17:18], v[11:12], -v[21:22]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[15:16], -v[7:8]
v_add_f64 v[9:10], v[9:10], -v[17:18]
v_fma_f64 v[17:18], v[13:14], s[34:35], -v[19:20]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[11:12], -v[7:8]
v_add_f64 v[5:6], v[5:6], v[9:10]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f64 v[9:10], v[13:14], s[36:37], v[17:18]
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[19:20], v[9:10]
v_add_f64 v[11:12], v[15:16], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[19:20], v[7:8], -v[19:20]
v_add_f64 v[13:14], v[7:8], v[11:12]
v_add_f64 v[15:16], v[11:12], -v[15:16]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[9:10], v[9:10], -v[19:20]
v_add_f64 v[17:18], v[13:14], -v[7:8]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[15:16]
v_add_f64 v[21:22], v[13:14], -v[17:18]
v_add_f64 v[11:12], v[11:12], -v[17:18]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[15:16], v[9:10], v[5:6]
v_add_f64 v[7:8], v[7:8], -v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[7:8], v[11:12], v[7:8]
v_add_f64 v[11:12], v[15:16], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[7:8], v[15:16], v[7:8]
v_add_f64 v[15:16], v[15:16], -v[11:12]
v_add_f64 v[5:6], v[5:6], -v[11:12]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f64 v[17:18], v[13:14], v[7:8]
v_add_f64 v[9:10], v[9:10], -v[15:16]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[17:18], -v[13:14]
v_add_f64 v[5:6], v[5:6], v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[7:8], -v[11:12]
v_add_f64 v[5:6], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[7:8], v[17:18], v[5:6]
v_add_f64 v[9:10], v[7:8], -v[17:18]
v_add_f64 v[11:12], v[7:8], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[5:6], v[5:6], -v[9:10]
v_fma_f64 v[7:8], v[7:8], 2.0, -v[11:12]
v_cmp_class_f64_e64 vcc_lo, v[11:12], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[5:6], v[5:6], 2.0, v[7:8]
v_add_f64 v[7:8], v[11:12], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v10, v8, v12 :: v_dual_cndmask_b32 v9, v7, v11
v_add_f64 v[7:8], v[7:8], -v[11:12]
v_mul_f64 v[13:14], v[9:10], s[40:41]
v_cmp_nlt_f64_e64 s1, 0x40900000, v[9:10]
v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[9:10]|
v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[9:10]
v_add_f64 v[5:6], v[5:6], -v[7:8]
v_rndne_f64_e32 v[13:14], v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v6, 0, v6 :: v_dual_cndmask_b32 v5, 0, v5
s_and_b32 vcc_lo, s2, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f64 v[15:16], v[13:14], s[42:43], v[9:10]
v_cvt_i32_f64_e32 v19, v[13:14]
v_fma_f64 v[15:16], v[13:14], s[44:45], v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[15:16], s[48:49], s[46:47]
v_fma_f64 v[17:18], v[15:16], v[17:18], s[50:51]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[52:53]
v_fma_f64 v[17:18], v[15:16], v[17:18], s[54:55]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[56:57]
v_fma_f64 v[17:18], v[15:16], v[17:18], s[58:59]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[60:61]
v_fma_f64 v[17:18], v[15:16], v[17:18], s[62:63]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[17:18], v[15:16], v[17:18], s[64:65]
v_fma_f64 v[17:18], v[15:16], v[17:18], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[13:14], v[15:16], v[17:18], 1.0
v_ldexp_f64 v[11:12], v[13:14], v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v7, 0x7ff00000, v12, s1
v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[3:4]|
v_cndmask_b32_e64 v8, 0, v7, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v7, 0, v11, vcc_lo
v_cmp_neq_f64_e64 s2, 0, v[3:4]
v_fma_f64 v[5:6], v[7:8], v[5:6], v[7:8]
v_cmp_class_f64_e64 vcc_lo, v[7:8], 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_dual_cndmask_b32 v6, v6, v8 :: v_dual_cndmask_b32 v3, v5, v7
s_and_b32 vcc_lo, s2, s1
s_add_u32 s66, s66, 8
s_addc_u32 s67, s67, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v3, 0, v3 :: v_dual_and_b32 v6, 0x7fffffff, v6
s_cmp_eq_u32 s5, 0
v_cndmask_b32_e64 v6, 0x7ff00000, v6, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, 0, v6, s2
v_add_f64 v[0:1], v[0:1], v[3:4]
global_store_b64 v2, v[0:1], s[68:69]
s_cbranch_scc0 .LBB0_5
s_branch .LBB0_2
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10normKernelPdiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 27
.amdhsa_next_free_sgpr 71
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10normKernelPdiS_i, .Lfunc_end0-_Z10normKernelPdiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10normKernelPdiS_i
.private_segment_fixed_size: 0
.sgpr_count: 73
.sgpr_spill_count: 0
.symbol: _Z10normKernelPdiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 27
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define NUMBER_OF_BLOCKS 256
#define NUMBER_OF_THREADS 64
// ==========
// Macro taken from:
// https://stackoverflow.com/questions/14038589/what-is-the-canonical-way-to-check-for-errors-using-the-cuda-runtime-api
__device__ int getElementsPerUnit(int total, int number_of_units) {
int elements_per_unit = total / number_of_units;
double remains = total % number_of_units;
if(remains != 0) {
elements_per_unit += 1;
}
return elements_per_unit;
}
__global__ void normKernel(double *vectors, int size, double *results, int vector_size) {
int vectors_per_block = getElementsPerUnit(size, gridDim.x);
// Get range of vectors we will work with
int start = blockIdx.x * vectors_per_block;
int end = start + vectors_per_block;
if(end > size) {
end = size;
}
for(int vec_index = start; vec_index < end; vec_index++) {
for(int i = 0; i < vector_size; i++) {
results[vec_index] += pow(vectors[vec_index*vector_size + i], 2);
}
results[vec_index] = sqrt(results[vec_index]);
}
} | .text
.file "normKernel.hip"
.globl _Z25__device_stub__normKernelPdiS_i # -- Begin function _Z25__device_stub__normKernelPdiS_i
.p2align 4, 0x90
.type _Z25__device_stub__normKernelPdiS_i,@function
_Z25__device_stub__normKernelPdiS_i: # @_Z25__device_stub__normKernelPdiS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10normKernelPdiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__normKernelPdiS_i, .Lfunc_end0-_Z25__device_stub__normKernelPdiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10normKernelPdiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10normKernelPdiS_i,@object # @_Z10normKernelPdiS_i
.section .rodata,"a",@progbits
.globl _Z10normKernelPdiS_i
.p2align 3, 0x0
_Z10normKernelPdiS_i:
.quad _Z25__device_stub__normKernelPdiS_i
.size _Z10normKernelPdiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10normKernelPdiS_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__normKernelPdiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10normKernelPdiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0002b362_00000000-6_normKernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z18getElementsPerUnitii
.type _Z18getElementsPerUnitii, @function
_Z18getElementsPerUnitii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z18getElementsPerUnitii, .-_Z18getElementsPerUnitii
.globl _Z34__device_stub__Z10normKernelPdiS_iPdiS_i
.type _Z34__device_stub__Z10normKernelPdiS_iPdiS_i, @function
_Z34__device_stub__Z10normKernelPdiS_iPdiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10normKernelPdiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z34__device_stub__Z10normKernelPdiS_iPdiS_i, .-_Z34__device_stub__Z10normKernelPdiS_iPdiS_i
.globl _Z10normKernelPdiS_i
.type _Z10normKernelPdiS_i, @function
_Z10normKernelPdiS_i:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10normKernelPdiS_iPdiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z10normKernelPdiS_i, .-_Z10normKernelPdiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10normKernelPdiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10normKernelPdiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "normKernel.hip"
.globl _Z25__device_stub__normKernelPdiS_i # -- Begin function _Z25__device_stub__normKernelPdiS_i
.p2align 4, 0x90
.type _Z25__device_stub__normKernelPdiS_i,@function
_Z25__device_stub__normKernelPdiS_i: # @_Z25__device_stub__normKernelPdiS_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10normKernelPdiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z25__device_stub__normKernelPdiS_i, .Lfunc_end0-_Z25__device_stub__normKernelPdiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10normKernelPdiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10normKernelPdiS_i,@object # @_Z10normKernelPdiS_i
.section .rodata,"a",@progbits
.globl _Z10normKernelPdiS_i
.p2align 3, 0x0
_Z10normKernelPdiS_i:
.quad _Z25__device_stub__normKernelPdiS_i
.size _Z10normKernelPdiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10normKernelPdiS_i"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__normKernelPdiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10normKernelPdiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <unistd.h>
#include <stdlib.h>
#include "cuda.h"
using namespace std;
__global__ void infinitekernel(float *dptr, int *dwait)
{
while(*dwait) *dptr += 1;
*dptr = 999;
}
int main(void)
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaStream_t stream[2];
for (int i=0; i < 2 ; i++)
cudaStreamCreate(&stream[i]);
float *hptr;
float *dptr;
int *hwait;
int *dwait;
hptr = (float*)malloc(sizeof(float));
hwait = (int*)malloc(sizeof(int));
cudaMalloc((void **)&dptr, sizeof(float));
cudaMalloc((void **)&dwait, sizeof(int));
*hptr = 9;
*hwait = 1;
cudaMemcpyAsync(dptr, hptr, sizeof(float), cudaMemcpyHostToDevice, stream[0]);
cudaMemcpyAsync(dwait, hwait, sizeof(float), cudaMemcpyHostToDevice, stream[0]);
cout << "Start to record kernel elapsed time" << endl;
cudaEventRecord(start, stream[1]);
infinitekernel<<<1, 1, 0, stream[1]>>>(dptr,dwait);
cudaEventRecord(stop, stream[1]);
for(int i=0; i<5; i++)
{
sleep(1);
cudaMemcpyAsync(hptr, dptr, sizeof(float), cudaMemcpyDeviceToHost, stream[0]);
cout << "["<< i << " seconds]" <<"value = " << *hptr << endl;
}
*hwait = 0;
cudaMemcpyAsync(dwait, hwait, sizeof(int), cudaMemcpyHostToDevice, stream[0]);
cudaMemcpyAsync(hptr, dptr, sizeof(float), cudaMemcpyDeviceToHost, stream[0]);
cout <<"[Finally]" << "value = "<< *hptr << endl;
cudaEventSynchronize(stop);
float elapsTime;
cudaEventElapsedTime(&elapsTime, start, stop);
cout << "Elapsed Time: " << elapsTime << endl;
} | code for sm_80
Function : _Z14infinitekernelPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4479c000 ; /* 0x4479c000ff097424 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe40000000f00 */
/*0070*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe40000000f00 */
/*0080*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*0090*/ @!P0 BRA 0x100 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*00a0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000164000c1e1900 */
/*00b0*/ FADD R7, R7, 1 ; /* 0x3f80000007077421 */
/* 0x020fca0000000000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0003e8000c101904 */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*00f0*/ @P0 BRA 0xb0 ; /* 0xffffffb000000947 */
/* 0x002fea000383ffff */
/*0100*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <unistd.h>
#include <stdlib.h>
#include "cuda.h"
using namespace std;
__global__ void infinitekernel(float *dptr, int *dwait)
{
while(*dwait) *dptr += 1;
*dptr = 999;
}
int main(void)
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaStream_t stream[2];
for (int i=0; i < 2 ; i++)
cudaStreamCreate(&stream[i]);
float *hptr;
float *dptr;
int *hwait;
int *dwait;
hptr = (float*)malloc(sizeof(float));
hwait = (int*)malloc(sizeof(int));
cudaMalloc((void **)&dptr, sizeof(float));
cudaMalloc((void **)&dwait, sizeof(int));
*hptr = 9;
*hwait = 1;
cudaMemcpyAsync(dptr, hptr, sizeof(float), cudaMemcpyHostToDevice, stream[0]);
cudaMemcpyAsync(dwait, hwait, sizeof(float), cudaMemcpyHostToDevice, stream[0]);
cout << "Start to record kernel elapsed time" << endl;
cudaEventRecord(start, stream[1]);
infinitekernel<<<1, 1, 0, stream[1]>>>(dptr,dwait);
cudaEventRecord(stop, stream[1]);
for(int i=0; i<5; i++)
{
sleep(1);
cudaMemcpyAsync(hptr, dptr, sizeof(float), cudaMemcpyDeviceToHost, stream[0]);
cout << "["<< i << " seconds]" <<"value = " << *hptr << endl;
}
*hwait = 0;
cudaMemcpyAsync(dwait, hwait, sizeof(int), cudaMemcpyHostToDevice, stream[0]);
cudaMemcpyAsync(hptr, dptr, sizeof(float), cudaMemcpyDeviceToHost, stream[0]);
cout <<"[Finally]" << "value = "<< *hptr << endl;
cudaEventSynchronize(stop);
float elapsTime;
cudaEventElapsedTime(&elapsTime, start, stop);
cout << "Elapsed Time: " << elapsTime << endl;
} | .file "tmpxft_00173832_00000000-6_events.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3685:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3685:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z14infinitekernelPfPiPfPi
.type _Z36__device_stub__Z14infinitekernelPfPiPfPi, @function
_Z36__device_stub__Z14infinitekernelPfPiPfPi:
.LFB3707:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14infinitekernelPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3707:
.size _Z36__device_stub__Z14infinitekernelPfPiPfPi, .-_Z36__device_stub__Z14infinitekernelPfPiPfPi
.globl _Z14infinitekernelPfPi
.type _Z14infinitekernelPfPi, @function
_Z14infinitekernelPfPi:
.LFB3708:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14infinitekernelPfPiPfPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _Z14infinitekernelPfPi, .-_Z14infinitekernelPfPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Start to record kernel elapsed time"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "["
.LC3:
.string " seconds]"
.LC4:
.string "value = "
.LC5:
.string "[Finally]"
.LC6:
.string "Elapsed Time: "
.text
.globl main
.type main, @function
main:
.LFB3682:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 88(%rsp), %rdi
call cudaStreamCreate@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0x41100000, 0(%r13)
movl $1, (%rbx)
movq 80(%rsp), %r8
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 80(%rsp), %r8
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 88(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movq 88(%rsp), %r9
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
movq 88(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %r12d
leaq .LC2(%rip), %r15
leaq _ZSt4cout(%rip), %r14
jmp .L17
.L21:
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z14infinitekernelPfPiPfPi
jmp .L12
.L24:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r12d
cmpl $5, %r12d
je .L23
.L17:
movl $1, %edi
call sleep@PLT
movq 80(%rsp), %r8
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpyAsync@PLT
movl $1, %edx
movq %r15, %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $9, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $8, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L24
cmpb $0, 56(%rbp)
je .L15
movzbl 67(%rbp), %esi
jmp .L16
.L23:
movq 8(%rsp), %rax
movl $0, (%rax)
movq 80(%rsp), %r8
movl $1, %ecx
movl $4, %edx
movq %rax, %rsi
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 80(%rsp), %r8
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpyAsync@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3682:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z14infinitekernelPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14infinitekernelPfPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3710:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <unistd.h>
#include <stdlib.h>
#include "cuda.h"
using namespace std;
__global__ void infinitekernel(float *dptr, int *dwait)
{
while(*dwait) *dptr += 1;
*dptr = 999;
}
int main(void)
{
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaStream_t stream[2];
for (int i=0; i < 2 ; i++)
cudaStreamCreate(&stream[i]);
float *hptr;
float *dptr;
int *hwait;
int *dwait;
hptr = (float*)malloc(sizeof(float));
hwait = (int*)malloc(sizeof(int));
cudaMalloc((void **)&dptr, sizeof(float));
cudaMalloc((void **)&dwait, sizeof(int));
*hptr = 9;
*hwait = 1;
cudaMemcpyAsync(dptr, hptr, sizeof(float), cudaMemcpyHostToDevice, stream[0]);
cudaMemcpyAsync(dwait, hwait, sizeof(float), cudaMemcpyHostToDevice, stream[0]);
cout << "Start to record kernel elapsed time" << endl;
cudaEventRecord(start, stream[1]);
infinitekernel<<<1, 1, 0, stream[1]>>>(dptr,dwait);
cudaEventRecord(stop, stream[1]);
for(int i=0; i<5; i++)
{
sleep(1);
cudaMemcpyAsync(hptr, dptr, sizeof(float), cudaMemcpyDeviceToHost, stream[0]);
cout << "["<< i << " seconds]" <<"value = " << *hptr << endl;
}
*hwait = 0;
cudaMemcpyAsync(dwait, hwait, sizeof(int), cudaMemcpyHostToDevice, stream[0]);
cudaMemcpyAsync(hptr, dptr, sizeof(float), cudaMemcpyDeviceToHost, stream[0]);
cout <<"[Finally]" << "value = "<< *hptr << endl;
cudaEventSynchronize(stop);
float elapsTime;
cudaEventElapsedTime(&elapsTime, start, stop);
cout << "Elapsed Time: " << elapsTime << endl;
} | #include <iostream>
#include <unistd.h>
#include <stdlib.h>
#include "hip/hip_runtime.h"
using namespace std;
__global__ void infinitekernel(float *dptr, int *dwait)
{
while(*dwait) *dptr += 1;
*dptr = 999;
}
int main(void)
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipStream_t stream[2];
for (int i=0; i < 2 ; i++)
hipStreamCreate(&stream[i]);
float *hptr;
float *dptr;
int *hwait;
int *dwait;
hptr = (float*)malloc(sizeof(float));
hwait = (int*)malloc(sizeof(int));
hipMalloc((void **)&dptr, sizeof(float));
hipMalloc((void **)&dwait, sizeof(int));
*hptr = 9;
*hwait = 1;
hipMemcpyAsync(dptr, hptr, sizeof(float), hipMemcpyHostToDevice, stream[0]);
hipMemcpyAsync(dwait, hwait, sizeof(float), hipMemcpyHostToDevice, stream[0]);
cout << "Start to record kernel elapsed time" << endl;
hipEventRecord(start, stream[1]);
infinitekernel<<<1, 1, 0, stream[1]>>>(dptr,dwait);
hipEventRecord(stop, stream[1]);
for(int i=0; i<5; i++)
{
sleep(1);
hipMemcpyAsync(hptr, dptr, sizeof(float), hipMemcpyDeviceToHost, stream[0]);
cout << "["<< i << " seconds]" <<"value = " << *hptr << endl;
}
*hwait = 0;
hipMemcpyAsync(dwait, hwait, sizeof(int), hipMemcpyHostToDevice, stream[0]);
hipMemcpyAsync(hptr, dptr, sizeof(float), hipMemcpyDeviceToHost, stream[0]);
cout <<"[Finally]" << "value = "<< *hptr << endl;
hipEventSynchronize(stop);
float elapsTime;
hipEventElapsedTime(&elapsTime, start, stop);
cout << "Elapsed Time: " << elapsTime << endl;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <unistd.h>
#include <stdlib.h>
#include "hip/hip_runtime.h"
using namespace std;
__global__ void infinitekernel(float *dptr, int *dwait)
{
while(*dwait) *dptr += 1;
*dptr = 999;
}
int main(void)
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipStream_t stream[2];
for (int i=0; i < 2 ; i++)
hipStreamCreate(&stream[i]);
float *hptr;
float *dptr;
int *hwait;
int *dwait;
hptr = (float*)malloc(sizeof(float));
hwait = (int*)malloc(sizeof(int));
hipMalloc((void **)&dptr, sizeof(float));
hipMalloc((void **)&dwait, sizeof(int));
*hptr = 9;
*hwait = 1;
hipMemcpyAsync(dptr, hptr, sizeof(float), hipMemcpyHostToDevice, stream[0]);
hipMemcpyAsync(dwait, hwait, sizeof(float), hipMemcpyHostToDevice, stream[0]);
cout << "Start to record kernel elapsed time" << endl;
hipEventRecord(start, stream[1]);
infinitekernel<<<1, 1, 0, stream[1]>>>(dptr,dwait);
hipEventRecord(stop, stream[1]);
for(int i=0; i<5; i++)
{
sleep(1);
hipMemcpyAsync(hptr, dptr, sizeof(float), hipMemcpyDeviceToHost, stream[0]);
cout << "["<< i << " seconds]" <<"value = " << *hptr << endl;
}
*hwait = 0;
hipMemcpyAsync(dwait, hwait, sizeof(int), hipMemcpyHostToDevice, stream[0]);
hipMemcpyAsync(hptr, dptr, sizeof(float), hipMemcpyDeviceToHost, stream[0]);
cout <<"[Finally]" << "value = "<< *hptr << endl;
hipEventSynchronize(stop);
float elapsTime;
hipEventElapsedTime(&elapsTime, start, stop);
cout << "Elapsed Time: " << elapsTime << endl;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14infinitekernelPfPi
.globl _Z14infinitekernelPfPi
.p2align 8
.type _Z14infinitekernelPfPi,@function
_Z14infinitekernelPfPi:
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s0, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_4
s_load_b32 s1, s[4:5], 0x0
v_cndmask_b32_e64 v1, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v1
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s1
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v0, 1.0, v0
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[4:5]
.LBB0_4:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x4479c000
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14infinitekernelPfPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14infinitekernelPfPi, .Lfunc_end0-_Z14infinitekernelPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14infinitekernelPfPi
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z14infinitekernelPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <unistd.h>
#include <stdlib.h>
#include "hip/hip_runtime.h"
using namespace std;
__global__ void infinitekernel(float *dptr, int *dwait)
{
while(*dwait) *dptr += 1;
*dptr = 999;
}
int main(void)
{
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
hipStream_t stream[2];
for (int i=0; i < 2 ; i++)
hipStreamCreate(&stream[i]);
float *hptr;
float *dptr;
int *hwait;
int *dwait;
hptr = (float*)malloc(sizeof(float));
hwait = (int*)malloc(sizeof(int));
hipMalloc((void **)&dptr, sizeof(float));
hipMalloc((void **)&dwait, sizeof(int));
*hptr = 9;
*hwait = 1;
hipMemcpyAsync(dptr, hptr, sizeof(float), hipMemcpyHostToDevice, stream[0]);
hipMemcpyAsync(dwait, hwait, sizeof(float), hipMemcpyHostToDevice, stream[0]);
cout << "Start to record kernel elapsed time" << endl;
hipEventRecord(start, stream[1]);
infinitekernel<<<1, 1, 0, stream[1]>>>(dptr,dwait);
hipEventRecord(stop, stream[1]);
for(int i=0; i<5; i++)
{
sleep(1);
hipMemcpyAsync(hptr, dptr, sizeof(float), hipMemcpyDeviceToHost, stream[0]);
cout << "["<< i << " seconds]" <<"value = " << *hptr << endl;
}
*hwait = 0;
hipMemcpyAsync(dwait, hwait, sizeof(int), hipMemcpyHostToDevice, stream[0]);
hipMemcpyAsync(hptr, dptr, sizeof(float), hipMemcpyDeviceToHost, stream[0]);
cout <<"[Finally]" << "value = "<< *hptr << endl;
hipEventSynchronize(stop);
float elapsTime;
hipEventElapsedTime(&elapsTime, start, stop);
cout << "Elapsed Time: " << elapsTime << endl;
} | .text
.file "events.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__infinitekernelPfPi # -- Begin function _Z29__device_stub__infinitekernelPfPi
.p2align 4, 0x90
.type _Z29__device_stub__infinitekernelPfPi,@function
_Z29__device_stub__infinitekernelPfPi: # @_Z29__device_stub__infinitekernelPfPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14infinitekernelPfPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__infinitekernelPfPi, .Lfunc_end0-_Z29__device_stub__infinitekernelPfPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $16, %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $8, %rbx
je .LBB1_1
# %bb.2:
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $1091567616, (%rbx) # imm = 0x41100000
movl $1, (%r14)
movq 8(%rsp), %rdi
movq 16(%rsp), %r8
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpyAsync
movq 40(%rsp), %rdi
movq 16(%rsp), %r8
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpyAsync
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_23
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_5
# %bb.4:
movzbl 67(%r15), %eax
jmp .LBB1_6
.LBB1_5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 56(%rsp), %rdi
movq 24(%rsp), %rsi
callq hipEventRecord
movq 24(%rsp), %r9
xorl %r15d, %r15d
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14infinitekernelPfPi, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi
callq hipEventRecord
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_9 Depth=1
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
# in Loop: Header=BB1_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %r15d
cmpl $5, %r15d
je .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl $1, %edi
callq sleep
movq 8(%rsp), %rsi
movq 16(%rsp), %r8
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpyAsync
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.2, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.3, %esi
movl $8, %edx
movq %r12, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_23
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r12)
je .LBB1_21
# %bb.11: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_22
.LBB1_12:
movl $0, (%r14)
movq 40(%rsp), %rdi
movq 16(%rsp), %r8
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rsi
movq 16(%rsp), %r8
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpyAsync
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 48(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
cmpb $0, 56(%rbx)
je .LBB1_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB1_20
.LBB1_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14infinitekernelPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14infinitekernelPfPi,@object # @_Z14infinitekernelPfPi
.section .rodata,"a",@progbits
.globl _Z14infinitekernelPfPi
.p2align 3, 0x0
_Z14infinitekernelPfPi:
.quad _Z29__device_stub__infinitekernelPfPi
.size _Z14infinitekernelPfPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Start to record kernel elapsed time"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "["
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " seconds]"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "value = "
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[Finally]"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Elapsed Time: "
.size .L.str.5, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14infinitekernelPfPi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__infinitekernelPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14infinitekernelPfPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14infinitekernelPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*0050*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4479c000 ; /* 0x4479c000ff097424 */
/* 0x000fe200078e00ff */
/*0060*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe40000000f00 */
/*0070*/ MOV R5, c[0x0][0x164] ; /* 0x0000590000057a02 */
/* 0x000fe40000000f00 */
/*0080*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*0090*/ @!P0 BRA 0x100 ; /* 0x0000006000008947 */
/* 0x000fea0003800000 */
/*00a0*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000164000c1e1900 */
/*00b0*/ FADD R7, R7, 1 ; /* 0x3f80000007077421 */
/* 0x020fca0000000000 */
/*00c0*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0003e8000c101904 */
/*00d0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00e0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x004fda0003f05270 */
/*00f0*/ @P0 BRA 0xb0 ; /* 0xffffffb000000947 */
/* 0x002fea000383ffff */
/*0100*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0110*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0120*/ BRA 0x120; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14infinitekernelPfPi
.globl _Z14infinitekernelPfPi
.p2align 8
.type _Z14infinitekernelPfPi,@function
_Z14infinitekernelPfPi:
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s0, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s0, 0
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_4
s_load_b32 s1, s[4:5], 0x0
v_cndmask_b32_e64 v1, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 1, v1
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s1
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v0, 1.0, v0
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccnz .LBB0_2
v_mov_b32_e32 v1, 0
global_store_b32 v1, v0, s[4:5]
.LBB0_4:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x4479c000
global_store_b32 v0, v1, s[4:5]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14infinitekernelPfPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14infinitekernelPfPi, .Lfunc_end0-_Z14infinitekernelPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14infinitekernelPfPi
.private_segment_fixed_size: 0
.sgpr_count: 10
.sgpr_spill_count: 0
.symbol: _Z14infinitekernelPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00173832_00000000-6_events.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3685:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3685:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z14infinitekernelPfPiPfPi
.type _Z36__device_stub__Z14infinitekernelPfPiPfPi, @function
_Z36__device_stub__Z14infinitekernelPfPiPfPi:
.LFB3707:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14infinitekernelPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3707:
.size _Z36__device_stub__Z14infinitekernelPfPiPfPi, .-_Z36__device_stub__Z14infinitekernelPfPiPfPi
.globl _Z14infinitekernelPfPi
.type _Z14infinitekernelPfPi, @function
_Z14infinitekernelPfPi:
.LFB3708:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14infinitekernelPfPiPfPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _Z14infinitekernelPfPi, .-_Z14infinitekernelPfPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "Start to record kernel elapsed time"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "["
.LC3:
.string " seconds]"
.LC4:
.string "value = "
.LC5:
.string "[Finally]"
.LC6:
.string "Elapsed Time: "
.text
.globl main
.type main, @function
main:
.LFB3682:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $120, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
leaq 80(%rsp), %rdi
call cudaStreamCreate@PLT
leaq 88(%rsp), %rdi
call cudaStreamCreate@PLT
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movl $4, %edi
call malloc@PLT
movq %rax, %rbx
movq %rax, 8(%rsp)
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $0x41100000, 0(%r13)
movl $1, (%rbx)
movq 80(%rsp), %r8
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 80(%rsp), %r8
movl $1, %ecx
movl $4, %edx
movq %rbx, %rsi
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 88(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movq 88(%rsp), %r9
movl $0, %r8d
movq 68(%rsp), %rdx
movl $1, %ecx
movq 56(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L12:
movq 88(%rsp), %rsi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movl $0, %r12d
leaq .LC2(%rip), %r15
leaq _ZSt4cout(%rip), %r14
jmp .L17
.L21:
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z14infinitekernelPfPiPfPi
jmp .L12
.L24:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L22
call _ZSt16__throw_bad_castv@PLT
.L22:
call __stack_chk_fail@PLT
.L15:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
.L16:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addl $1, %r12d
cmpl $5, %r12d
je .L23
.L17:
movl $1, %edi
call sleep@PLT
movq 80(%rsp), %r8
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpyAsync@PLT
movl $1, %edx
movq %r15, %rsi
movq %r14, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r12d, %esi
movq %r14, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movl $9, %edx
leaq .LC3(%rip), %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl $8, %edx
leaq .LC4(%rip), %rsi
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
movq %rbx, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L24
cmpb $0, 56(%rbp)
je .L15
movzbl 67(%rbp), %esi
jmp .L16
.L23:
movq 8(%rsp), %rax
movl $0, (%rax)
movq 80(%rsp), %r8
movl $1, %ecx
movl $4, %edx
movq %rax, %rsi
movq 48(%rsp), %rdi
call cudaMemcpyAsync@PLT
movq 80(%rsp), %r8
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpyAsync@PLT
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 0(%r13), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 68(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC6(%rip), %rsi
movq %rbx, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 68(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3682:
.size main, .-main
.section .rodata.str1.1
.LC7:
.string "_Z14infinitekernelPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z14infinitekernelPfPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3710:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "events.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z29__device_stub__infinitekernelPfPi # -- Begin function _Z29__device_stub__infinitekernelPfPi
.p2align 4, 0x90
.type _Z29__device_stub__infinitekernelPfPi,@function
_Z29__device_stub__infinitekernelPfPi: # @_Z29__device_stub__infinitekernelPfPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14infinitekernelPfPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__infinitekernelPfPi, .Lfunc_end0-_Z29__device_stub__infinitekernelPfPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq (%rsp,%rbx), %rdi
addq $16, %rdi
callq hipStreamCreate
addq $8, %rbx
cmpq $8, %rbx
je .LBB1_1
# %bb.2:
movl $4, %edi
callq malloc
movq %rax, %rbx
movl $4, %edi
callq malloc
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
leaq 40(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $1091567616, (%rbx) # imm = 0x41100000
movl $1, (%r14)
movq 8(%rsp), %rdi
movq 16(%rsp), %r8
movl $4, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpyAsync
movq 40(%rsp), %rdi
movq 16(%rsp), %r8
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpyAsync
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $35, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_23
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_5
# %bb.4:
movzbl 67(%r15), %eax
jmp .LBB1_6
.LBB1_5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 56(%rsp), %rdi
movq 24(%rsp), %rsi
callq hipEventRecord
movq 24(%rsp), %r9
xorl %r15d, %r15d
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 8(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
leaq 136(%rsp), %rax
movq %rax, 64(%rsp)
leaq 128(%rsp), %rax
movq %rax, 72(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14infinitekernelPfPi, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 48(%rsp), %rdi
movq 24(%rsp), %rsi
callq hipEventRecord
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_21: # in Loop: Header=BB1_9 Depth=1
movq %r12, %rdi
movq %rax, %r13
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r13, %rax
.LBB1_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit33
# in Loop: Header=BB1_9 Depth=1
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incl %r15d
cmpl $5, %r15d
je .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movl $1, %edi
callq sleep
movq 8(%rsp), %rsi
movq 16(%rsp), %r8
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpyAsync
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %r15d, %esi
callq _ZNSolsEi
movq %rax, %r12
movl $.L.str.2, %esi
movl $9, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $.L.str.3, %esi
movl $8, %edx
movq %r12, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq %r12, %rdi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB1_23
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i30
# in Loop: Header=BB1_9 Depth=1
cmpb $0, 56(%r12)
je .LBB1_21
# %bb.11: # in Loop: Header=BB1_9 Depth=1
movzbl 67(%r12), %ecx
jmp .LBB1_22
.LBB1_12:
movl $0, (%r14)
movq 40(%rsp), %rdi
movq 16(%rsp), %r8
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpyAsync
movq 8(%rsp), %rsi
movq 16(%rsp), %r8
movl $4, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpyAsync
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $9, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%rbx), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%rbx)
je .LBB1_15
# %bb.14:
movzbl 67(%rbx), %ecx
jmp .LBB1_16
.LBB1_15:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 48(%rsp), %rdi
callq hipEventSynchronize
movq 56(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 64(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $14, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 64(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_23
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i25
cmpb $0, 56(%rbx)
je .LBB1_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB1_20
.LBB1_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit28
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_23:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14infinitekernelPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14infinitekernelPfPi,@object # @_Z14infinitekernelPfPi
.section .rodata,"a",@progbits
.globl _Z14infinitekernelPfPi
.p2align 3, 0x0
_Z14infinitekernelPfPi:
.quad _Z29__device_stub__infinitekernelPfPi
.size _Z14infinitekernelPfPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Start to record kernel elapsed time"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "["
.size .L.str.1, 2
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " seconds]"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "value = "
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "[Finally]"
.size .L.str.4, 10
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Elapsed Time: "
.size .L.str.5, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14infinitekernelPfPi"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__infinitekernelPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14infinitekernelPfPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
__global__ void findSubstr(char *str, char *substr, int *len)
{
int subStrLen = *len;
int k = threadIdx.x;
for (int j = 0, i = k; j < subStrLen; j++, i++)
{
if(str[i] != substr[j])
{
return;
}
}
printf("Substring present at index %i\n", k);
}
int main()
{
cudaError_t err;
char *str = (char *) calloc(BUFSIZ, sizeof(char));
printf("Enter the String\n");
scanf("%[^\n]%*c", str);
int strLen = strlen(str);
char *substr = (char *) calloc(BUFSIZ, sizeof(char));
printf("Enter the substring\n");
scanf("%[^\n]%*c", substr);
int subStrLen = strlen(substr);
char *dStr, *dSubStr;
int *dLen;
cudaMalloc(&dStr,strLen);
cudaMalloc(&dSubStr, subStrLen);
cudaMalloc(&dLen, sizeof(int));
cudaMemcpy(dStr, str, strLen, cudaMemcpyHostToDevice);
cudaMemcpy(dSubStr, substr, subStrLen, cudaMemcpyHostToDevice);
cudaMemcpy(dLen, &subStrLen, sizeof(int), cudaMemcpyHostToDevice);
findSubstr<<<1, strLen - subStrLen + 1>>>(dStr, dSubStr, dLen);
err = cudaGetLastError();
if(err != cudaSuccess)
{
printf("The error string: %s\n", cudaGetErrorString(err));
}
cudaFree(dStr);
cudaFree(dSubStr);
cudaFree(dLen);
} | code for sm_80
Function : _Z10findSubstrPcS_Pi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc80007ffe0ff */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000802007981 */
/* 0x000ea2000c1e1900 */
/*0060*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fc60007f3e0ff */
/*0070*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fe200008e06ff */
/*0090*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x004fda0003f06270 */
/*00a0*/ @!P0 BRA 0x1c0 ; /* 0x0000011000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R9, RZ, RZ, R8 ; /* 0x000000ffff097224 */
/* 0x001fe200078e0008 */
/*00c0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fc60008000000 */
/*00d0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ IADD3 R4, P0, R9, c[0x0][0x160], RZ ; /* 0x0000580009047a10 */
/* 0x000fe20007f1e0ff */
/*00f0*/ UIADD3 UR5, UP0, UR4, UR6, URZ ; /* 0x0000000604057290 */
/* 0x000fc6000ff1e03f */
/*0100*/ LEA.HI.X.SX32 R5, R9, c[0x0][0x164], 0x1, P0 ; /* 0x0000590009057a11 */
/* 0x000fe200000f0eff */
/*0110*/ ULEA.HI.X.SX32 UR6, UR4, UR7, 0x1, UP0 ; /* 0x0000000704067291 */
/* 0x000fe400080f0e3f */
/*0120*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fc6000f8e00ff */
/*0130*/ LDG.E.U8 R5, [R4.64] ; /* 0x0000000804057981 */
/* 0x000ea2000c1e1100 */
/*0140*/ IMAD.U32 R3, RZ, RZ, UR6 ; /* 0x00000006ff037e24 */
/* 0x000fca000f8e00ff */
/*0150*/ LDG.E.U8 R2, [R2.64] ; /* 0x0000000802027981 */
/* 0x000ea2000c1e1100 */
/*0160*/ UIADD3 UR4, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000fffe03f */
/*0170*/ ISETP.NE.AND P0, PT, R5, R2, PT ; /* 0x000000020500720c */
/* 0x004fda0003f05270 */
/*0180*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0190*/ ISETP.LE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fe4000bf03270 */
/*01a0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fd60007ffe0ff */
/*01b0*/ @!P0 BRA 0xd0 ; /* 0xffffff1000008947 */
/* 0x000fea000383ffff */
/*01c0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe20000000f00 */
/*01d0*/ STL [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100800 */
/*01e0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*01f0*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x0000620000000a00 */
/*0200*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fce00078e00ff */
/*0210*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x001fe40000000000 */
/*0220*/ MOV R11, 0x290 ; /* 0x00000290000b7802 */
/* 0x000fe40000000f00 */
/*0230*/ MOV R20, 0x210 ; /* 0x0000021000147802 */
/* 0x000fe40000000f00 */
/*0240*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0250*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0260*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0270*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0280*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
__global__ void findSubstr(char *str, char *substr, int *len)
{
int subStrLen = *len;
int k = threadIdx.x;
for (int j = 0, i = k; j < subStrLen; j++, i++)
{
if(str[i] != substr[j])
{
return;
}
}
printf("Substring present at index %i\n", k);
}
int main()
{
cudaError_t err;
char *str = (char *) calloc(BUFSIZ, sizeof(char));
printf("Enter the String\n");
scanf("%[^\n]%*c", str);
int strLen = strlen(str);
char *substr = (char *) calloc(BUFSIZ, sizeof(char));
printf("Enter the substring\n");
scanf("%[^\n]%*c", substr);
int subStrLen = strlen(substr);
char *dStr, *dSubStr;
int *dLen;
cudaMalloc(&dStr,strLen);
cudaMalloc(&dSubStr, subStrLen);
cudaMalloc(&dLen, sizeof(int));
cudaMemcpy(dStr, str, strLen, cudaMemcpyHostToDevice);
cudaMemcpy(dSubStr, substr, subStrLen, cudaMemcpyHostToDevice);
cudaMemcpy(dLen, &subStrLen, sizeof(int), cudaMemcpyHostToDevice);
findSubstr<<<1, strLen - subStrLen + 1>>>(dStr, dSubStr, dLen);
err = cudaGetLastError();
if(err != cudaSuccess)
{
printf("The error string: %s\n", cudaGetErrorString(err));
}
cudaFree(dStr);
cudaFree(dSubStr);
cudaFree(dLen);
} | .file "tmpxft_000e4727_00000000-6_findSubstr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi
.type _Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi, @function
_Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10findSubstrPcS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi, .-_Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi
.globl _Z10findSubstrPcS_Pi
.type _Z10findSubstrPcS_Pi, @function
_Z10findSubstrPcS_Pi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10findSubstrPcS_Pi, .-_Z10findSubstrPcS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the String\n"
.LC1:
.string "%[^\n]%*c"
.LC2:
.string "Enter the substring\n"
.LC3:
.string "The error string: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, %esi
movl $8192, %edi
call calloc@PLT
movq %rax, %r12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
leaq .LC1(%rip), %r13
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %r12, %rdi
call strlen@PLT
movq %rax, %rbx
movl $1, %esi
movl $8192, %edi
call calloc@PLT
movq %rax, %rbp
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbp, %rdi
call strlen@PLT
movl %eax, 4(%rsp)
movslq %ebx, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
subl 4(%rsp), %ebx
addl $1, %ebx
movl %ebx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L17
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi
jmp .L12
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z10findSubstrPcS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10findSubstrPcS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
__global__ void findSubstr(char *str, char *substr, int *len)
{
int subStrLen = *len;
int k = threadIdx.x;
for (int j = 0, i = k; j < subStrLen; j++, i++)
{
if(str[i] != substr[j])
{
return;
}
}
printf("Substring present at index %i\n", k);
}
int main()
{
cudaError_t err;
char *str = (char *) calloc(BUFSIZ, sizeof(char));
printf("Enter the String\n");
scanf("%[^\n]%*c", str);
int strLen = strlen(str);
char *substr = (char *) calloc(BUFSIZ, sizeof(char));
printf("Enter the substring\n");
scanf("%[^\n]%*c", substr);
int subStrLen = strlen(substr);
char *dStr, *dSubStr;
int *dLen;
cudaMalloc(&dStr,strLen);
cudaMalloc(&dSubStr, subStrLen);
cudaMalloc(&dLen, sizeof(int));
cudaMemcpy(dStr, str, strLen, cudaMemcpyHostToDevice);
cudaMemcpy(dSubStr, substr, subStrLen, cudaMemcpyHostToDevice);
cudaMemcpy(dLen, &subStrLen, sizeof(int), cudaMemcpyHostToDevice);
findSubstr<<<1, strLen - subStrLen + 1>>>(dStr, dSubStr, dLen);
err = cudaGetLastError();
if(err != cudaSuccess)
{
printf("The error string: %s\n", cudaGetErrorString(err));
}
cudaFree(dStr);
cudaFree(dSubStr);
cudaFree(dLen);
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
__global__ void findSubstr(char *str, char *substr, int *len)
{
int subStrLen = *len;
int k = threadIdx.x;
for (int j = 0, i = k; j < subStrLen; j++, i++)
{
if(str[i] != substr[j])
{
return;
}
}
printf("Substring present at index %i\n", k);
}
int main()
{
hipError_t err;
char *str = (char *) calloc(BUFSIZ, sizeof(char));
printf("Enter the String\n");
scanf("%[^\n]%*c", str);
int strLen = strlen(str);
char *substr = (char *) calloc(BUFSIZ, sizeof(char));
printf("Enter the substring\n");
scanf("%[^\n]%*c", substr);
int subStrLen = strlen(substr);
char *dStr, *dSubStr;
int *dLen;
hipMalloc(&dStr,strLen);
hipMalloc(&dSubStr, subStrLen);
hipMalloc(&dLen, sizeof(int));
hipMemcpy(dStr, str, strLen, hipMemcpyHostToDevice);
hipMemcpy(dSubStr, substr, subStrLen, hipMemcpyHostToDevice);
hipMemcpy(dLen, &subStrLen, sizeof(int), hipMemcpyHostToDevice);
findSubstr<<<1, strLen - subStrLen + 1>>>(dStr, dSubStr, dLen);
err = hipGetLastError();
if(err != hipSuccess)
{
printf("The error string: %s\n", hipGetErrorString(err));
}
hipFree(dStr);
hipFree(dSubStr);
hipFree(dLen);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
__global__ void findSubstr(char *str, char *substr, int *len)
{
int subStrLen = *len;
int k = threadIdx.x;
for (int j = 0, i = k; j < subStrLen; j++, i++)
{
if(str[i] != substr[j])
{
return;
}
}
printf("Substring present at index %i\n", k);
}
int main()
{
hipError_t err;
char *str = (char *) calloc(BUFSIZ, sizeof(char));
printf("Enter the String\n");
scanf("%[^\n]%*c", str);
int strLen = strlen(str);
char *substr = (char *) calloc(BUFSIZ, sizeof(char));
printf("Enter the substring\n");
scanf("%[^\n]%*c", substr);
int subStrLen = strlen(substr);
char *dStr, *dSubStr;
int *dLen;
hipMalloc(&dStr,strLen);
hipMalloc(&dSubStr, subStrLen);
hipMalloc(&dLen, sizeof(int));
hipMemcpy(dStr, str, strLen, hipMemcpyHostToDevice);
hipMemcpy(dSubStr, substr, subStrLen, hipMemcpyHostToDevice);
hipMemcpy(dLen, &subStrLen, sizeof(int), hipMemcpyHostToDevice);
findSubstr<<<1, strLen - subStrLen + 1>>>(dStr, dSubStr, dLen);
err = hipGetLastError();
if(err != hipSuccess)
{
printf("The error string: %s\n", hipGetErrorString(err));
}
hipFree(dStr);
hipFree(dSubStr);
hipFree(dLen);
} | .text
.file "findSubstr.hip"
.globl _Z25__device_stub__findSubstrPcS_Pi # -- Begin function _Z25__device_stub__findSubstrPcS_Pi
.p2align 4, 0x90
.type _Z25__device_stub__findSubstrPcS_Pi,@function
_Z25__device_stub__findSubstrPcS_Pi: # @_Z25__device_stub__findSubstrPcS_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10findSubstrPcS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__findSubstrPcS_Pi, .Lfunc_end0-_Z25__device_stub__findSubstrPcS_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8192, %edi # imm = 0x2000
movl $1, %esi
callq calloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
callq strlen
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
movl $1, %esi
callq calloc
movq %rax, %r15
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %r15, %rdi
callq strlen
movl %eax, 12(%rsp)
movslq %r14d, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq 12(%rsp), %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq 12(%rsp), %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
subl 12(%rsp), %r14d
incl %r14d
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r14
orq $1, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10findSubstrPcS_Pi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_4:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10findSubstrPcS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10findSubstrPcS_Pi,@object # @_Z10findSubstrPcS_Pi
.section .rodata,"a",@progbits
.globl _Z10findSubstrPcS_Pi
.p2align 3, 0x0
_Z10findSubstrPcS_Pi:
.quad _Z25__device_stub__findSubstrPcS_Pi
.size _Z10findSubstrPcS_Pi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%[^\n]%*c"
.size .L.str.1, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The error string: %s\n"
.size .L.str.3, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10findSubstrPcS_Pi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter the String"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter the substring"
.size .Lstr.1, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__findSubstrPcS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10findSubstrPcS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e4727_00000000-6_findSubstr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi
.type _Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi, @function
_Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10findSubstrPcS_Pi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi, .-_Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi
.globl _Z10findSubstrPcS_Pi
.type _Z10findSubstrPcS_Pi, @function
_Z10findSubstrPcS_Pi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10findSubstrPcS_Pi, .-_Z10findSubstrPcS_Pi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the String\n"
.LC1:
.string "%[^\n]%*c"
.LC2:
.string "Enter the substring\n"
.LC3:
.string "The error string: %s\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $1, %esi
movl $8192, %edi
call calloc@PLT
movq %rax, %r12
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
leaq .LC1(%rip), %r13
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %r12, %rdi
call strlen@PLT
movq %rax, %rbx
movl $1, %esi
movl $8192, %edi
call calloc@PLT
movq %rax, %rbp
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rsi
movq %r13, %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbp, %rdi
call strlen@PLT
movl %eax, 4(%rsp)
movslq %ebx, %r13
leaq 8(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movslq 4(%rsp), %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movslq 4(%rsp), %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
subl 4(%rsp), %ebx
addl $1, %ebx
movl %ebx, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L17
.L13:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z10findSubstrPcS_PiPcS_Pi
jmp .L12
.L17:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z10findSubstrPcS_Pi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z10findSubstrPcS_Pi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "findSubstr.hip"
.globl _Z25__device_stub__findSubstrPcS_Pi # -- Begin function _Z25__device_stub__findSubstrPcS_Pi
.p2align 4, 0x90
.type _Z25__device_stub__findSubstrPcS_Pi,@function
_Z25__device_stub__findSubstrPcS_Pi: # @_Z25__device_stub__findSubstrPcS_Pi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10findSubstrPcS_Pi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__findSubstrPcS_Pi, .Lfunc_end0-_Z25__device_stub__findSubstrPcS_Pi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $8192, %edi # imm = 0x2000
movl $1, %esi
callq calloc
movq %rax, %rbx
movl $.Lstr, %edi
callq puts@PLT
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
callq strlen
movq %rax, %r14
movl $8192, %edi # imm = 0x2000
movl $1, %esi
callq calloc
movq %rax, %r15
movl $.Lstr.1, %edi
callq puts@PLT
movl $.L.str.1, %edi
movq %r15, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %r15, %rdi
callq strlen
movl %eax, 12(%rsp)
movslq %r14d, %r14
leaq 32(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movslq 12(%rsp), %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 32(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movslq 12(%rsp), %rdx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
subl 12(%rsp), %r14d
incl %r14d
movabsq $4294967296, %rdi # imm = 0x100000000
orq %rdi, %r14
orq $1, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z10findSubstrPcS_Pi, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipGetLastError
testl %eax, %eax
je .LBB1_4
# %bb.3:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movq %rax, %rsi
xorl %eax, %eax
callq printf
.LBB1_4:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10findSubstrPcS_Pi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10findSubstrPcS_Pi,@object # @_Z10findSubstrPcS_Pi
.section .rodata,"a",@progbits
.globl _Z10findSubstrPcS_Pi
.p2align 3, 0x0
_Z10findSubstrPcS_Pi:
.quad _Z25__device_stub__findSubstrPcS_Pi
.size _Z10findSubstrPcS_Pi, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%[^\n]%*c"
.size .L.str.1, 9
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "The error string: %s\n"
.size .L.str.3, 22
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10findSubstrPcS_Pi"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Enter the String"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "Enter the substring"
.size .Lstr.1, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__findSubstrPcS_Pi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10findSubstrPcS_Pi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | void is_a_thrust_bug();
int main(int argc, char** argv) {
is_a_thrust_bug();
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | void is_a_thrust_bug();
int main(int argc, char** argv) {
is_a_thrust_bug();
return 0;
} | .file "tmpxft_0016d7e0_00000000-6_repro.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z15is_a_thrust_bugv@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | void is_a_thrust_bug();
int main(int argc, char** argv) {
is_a_thrust_bug();
return 0;
} | #include <hip/hip_runtime.h>
void is_a_thrust_bug();
int main(int argc, char** argv) {
is_a_thrust_bug();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
void is_a_thrust_bug();
int main(int argc, char** argv) {
is_a_thrust_bug();
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
void is_a_thrust_bug();
int main(int argc, char** argv) {
is_a_thrust_bug();
return 0;
} | .text
.file "repro.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z15is_a_thrust_bugv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016d7e0_00000000-6_repro.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z15is_a_thrust_bugv@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "repro.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
callq _Z15is_a_thrust_bugv
xorl %eax, %eax
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <unistd.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
#define N 50000
#define CORES 50000
/* run the collatz conjecture and return the number of steps */
__global__ void collatz(unsigned int* step) {
//Set x to the initial value of step
unsigned int x = step[blockIdx.x];
//Reset step to 0
step[blockIdx.x] = 0;
/* do the iterative process */
while (x != 1) {
if ((x % 2) == 0) {
x = x / 2;
} else {
x = 3 * x + 1;
}
step[blockIdx.x]++;
}
}
int main( ) {
/* store the number of steps for each number up to N */
unsigned int cpu_steps[N];
unsigned int* gpu_steps;
/* allocate space on the GPU */
cudaMalloc((void**) &gpu_steps, N * sizeof(unsigned int));
for(int i=0; i < N; i++) {
cpu_steps[i] = i+1;
}
/* send gpu_steps to the GPU */
cudaMemcpy(gpu_steps, cpu_steps, N * sizeof(unsigned int), cudaMemcpyHostToDevice);
/* run the collatz conjecture on all N items */
collatz<<<CORES, 1>>>(gpu_steps);
/* send gpu_steps back to the CPU */
cudaMemcpy(cpu_steps, gpu_steps, N * sizeof(unsigned int), cudaMemcpyDeviceToHost);
/* free the memory on the GPU */
cudaFree(gpu_steps);
/* find the largest */
unsigned int largest = cpu_steps[0], largest_i = 0;
for (int i = 1; i < N; i++) {
if (cpu_steps[i] > largest) {
largest = cpu_steps[i];
largest_i = i;
}
}
/* report results */
printf("The longest collatz chain up to %d is %d with %d steps.\n",
N, largest_i + 1, largest);
return 0;
} | code for sm_80
Function : _Z7collatzPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0060*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0070*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x004fda0003f05270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fce00078e00ff */
/*00b0*/ LOP3.LUT R5, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100057812 */
/* 0x000fe400078ec0ff */
/*00c0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f05070 */
/*00e0*/ IMAD R5, R0, 0x3, R7 ; /* 0x0000000300057824 */
/* 0x000fd800078e0207 */
/*00f0*/ @P0 SHF.R.U32.HI R5, RZ, 0x1, R0 ; /* 0x00000001ff050819 */
/* 0x000fc80000011600 */
/*0100*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f05270 */
/*0110*/ MOV R0, R5 ; /* 0x0000000500007202 */
/* 0x000fd60000000f00 */
/*0120*/ @P0 BRA 0xb0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0130*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <unistd.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
#define N 50000
#define CORES 50000
/* run the collatz conjecture and return the number of steps */
__global__ void collatz(unsigned int* step) {
//Set x to the initial value of step
unsigned int x = step[blockIdx.x];
//Reset step to 0
step[blockIdx.x] = 0;
/* do the iterative process */
while (x != 1) {
if ((x % 2) == 0) {
x = x / 2;
} else {
x = 3 * x + 1;
}
step[blockIdx.x]++;
}
}
int main( ) {
/* store the number of steps for each number up to N */
unsigned int cpu_steps[N];
unsigned int* gpu_steps;
/* allocate space on the GPU */
cudaMalloc((void**) &gpu_steps, N * sizeof(unsigned int));
for(int i=0; i < N; i++) {
cpu_steps[i] = i+1;
}
/* send gpu_steps to the GPU */
cudaMemcpy(gpu_steps, cpu_steps, N * sizeof(unsigned int), cudaMemcpyHostToDevice);
/* run the collatz conjecture on all N items */
collatz<<<CORES, 1>>>(gpu_steps);
/* send gpu_steps back to the CPU */
cudaMemcpy(cpu_steps, gpu_steps, N * sizeof(unsigned int), cudaMemcpyDeviceToHost);
/* free the memory on the GPU */
cudaFree(gpu_steps);
/* find the largest */
unsigned int largest = cpu_steps[0], largest_i = 0;
for (int i = 1; i < N; i++) {
if (cpu_steps[i] > largest) {
largest = cpu_steps[i];
largest_i = i;
}
}
/* report results */
printf("The longest collatz chain up to %d is %d with %d steps.\n",
N, largest_i + 1, largest);
return 0;
} | .file "tmpxft_0012524a_00000000-6_collatz.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7collatzPjPj
.type _Z26__device_stub__Z7collatzPjPj, @function
_Z26__device_stub__Z7collatzPjPj:
.LFB2095:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7collatzPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z26__device_stub__Z7collatzPjPj, .-_Z26__device_stub__Z7collatzPjPj
.globl _Z7collatzPj
.type _Z7collatzPj, @function
_Z7collatzPj:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7collatzPjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z7collatzPj, .-_Z7collatzPj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "The longest collatz chain up to %d is %d with %d steps.\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
leaq -196608(%rsp), %r11
.cfi_def_cfa 11, 196616
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3448, %rsp
.cfi_def_cfa_offset 200064
movq %fs:40, %rax
movq %rax, 200040(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $200000, %esi
call cudaMalloc@PLT
movl $1, %eax
.L12:
movl %eax, 28(%rsp,%rax,4)
addq $1, %rax
cmpq $50001, %rax
jne .L12
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $200000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $50000, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $200000, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl 32(%rsp), %r8d
movl $1, %eax
movl $0, %ecx
.L15:
movl 32(%rsp,%rax,4), %edx
cmpl %edx, %r8d
cmovb %eax, %ecx
cmovb %edx, %r8d
addq $1, %rax
cmpq $50000, %rax
jne .L15
addl $1, %ecx
movl $50000, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 200040(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $200056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq (%rsp), %rdi
call _Z26__device_stub__Z7collatzPjPj
jmp .L13
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z7collatzPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7collatzPj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <unistd.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
#define N 50000
#define CORES 50000
/* run the collatz conjecture and return the number of steps */
__global__ void collatz(unsigned int* step) {
//Set x to the initial value of step
unsigned int x = step[blockIdx.x];
//Reset step to 0
step[blockIdx.x] = 0;
/* do the iterative process */
while (x != 1) {
if ((x % 2) == 0) {
x = x / 2;
} else {
x = 3 * x + 1;
}
step[blockIdx.x]++;
}
}
int main( ) {
/* store the number of steps for each number up to N */
unsigned int cpu_steps[N];
unsigned int* gpu_steps;
/* allocate space on the GPU */
cudaMalloc((void**) &gpu_steps, N * sizeof(unsigned int));
for(int i=0; i < N; i++) {
cpu_steps[i] = i+1;
}
/* send gpu_steps to the GPU */
cudaMemcpy(gpu_steps, cpu_steps, N * sizeof(unsigned int), cudaMemcpyHostToDevice);
/* run the collatz conjecture on all N items */
collatz<<<CORES, 1>>>(gpu_steps);
/* send gpu_steps back to the CPU */
cudaMemcpy(cpu_steps, gpu_steps, N * sizeof(unsigned int), cudaMemcpyDeviceToHost);
/* free the memory on the GPU */
cudaFree(gpu_steps);
/* find the largest */
unsigned int largest = cpu_steps[0], largest_i = 0;
for (int i = 1; i < N; i++) {
if (cpu_steps[i] > largest) {
largest = cpu_steps[i];
largest_i = i;
}
}
/* report results */
printf("The longest collatz chain up to %d is %d with %d steps.\n",
N, largest_i + 1, largest);
return 0;
} | #include <hip/hip_runtime.h>
#include <unistd.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
#define N 50000
#define CORES 50000
/* run the collatz conjecture and return the number of steps */
__global__ void collatz(unsigned int* step) {
//Set x to the initial value of step
unsigned int x = step[blockIdx.x];
//Reset step to 0
step[blockIdx.x] = 0;
/* do the iterative process */
while (x != 1) {
if ((x % 2) == 0) {
x = x / 2;
} else {
x = 3 * x + 1;
}
step[blockIdx.x]++;
}
}
int main( ) {
/* store the number of steps for each number up to N */
unsigned int cpu_steps[N];
unsigned int* gpu_steps;
/* allocate space on the GPU */
hipMalloc((void**) &gpu_steps, N * sizeof(unsigned int));
for(int i=0; i < N; i++) {
cpu_steps[i] = i+1;
}
/* send gpu_steps to the GPU */
hipMemcpy(gpu_steps, cpu_steps, N * sizeof(unsigned int), hipMemcpyHostToDevice);
/* run the collatz conjecture on all N items */
collatz<<<CORES, 1>>>(gpu_steps);
/* send gpu_steps back to the CPU */
hipMemcpy(cpu_steps, gpu_steps, N * sizeof(unsigned int), hipMemcpyDeviceToHost);
/* free the memory on the GPU */
hipFree(gpu_steps);
/* find the largest */
unsigned int largest = cpu_steps[0], largest_i = 0;
for (int i = 1; i < N; i++) {
if (cpu_steps[i] > largest) {
largest = cpu_steps[i];
largest_i = i;
}
}
/* report results */
printf("The longest collatz chain up to %d is %d with %d steps.\n",
N, largest_i + 1, largest);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <unistd.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
#define N 50000
#define CORES 50000
/* run the collatz conjecture and return the number of steps */
__global__ void collatz(unsigned int* step) {
//Set x to the initial value of step
unsigned int x = step[blockIdx.x];
//Reset step to 0
step[blockIdx.x] = 0;
/* do the iterative process */
while (x != 1) {
if ((x % 2) == 0) {
x = x / 2;
} else {
x = 3 * x + 1;
}
step[blockIdx.x]++;
}
}
int main( ) {
/* store the number of steps for each number up to N */
unsigned int cpu_steps[N];
unsigned int* gpu_steps;
/* allocate space on the GPU */
hipMalloc((void**) &gpu_steps, N * sizeof(unsigned int));
for(int i=0; i < N; i++) {
cpu_steps[i] = i+1;
}
/* send gpu_steps to the GPU */
hipMemcpy(gpu_steps, cpu_steps, N * sizeof(unsigned int), hipMemcpyHostToDevice);
/* run the collatz conjecture on all N items */
collatz<<<CORES, 1>>>(gpu_steps);
/* send gpu_steps back to the CPU */
hipMemcpy(cpu_steps, gpu_steps, N * sizeof(unsigned int), hipMemcpyDeviceToHost);
/* free the memory on the GPU */
hipFree(gpu_steps);
/* find the largest */
unsigned int largest = cpu_steps[0], largest_i = 0;
for (int i = 1; i < N; i++) {
if (cpu_steps[i] > largest) {
largest = cpu_steps[i];
largest_i = i;
}
}
/* report results */
printf("The longest collatz chain up to %d is %d with %d steps.\n",
N, largest_i + 1, largest);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7collatzPj
.globl _Z7collatzPj
.p2align 8
.type _Z7collatzPj,@function
_Z7collatzPj:
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 1
s_cbranch_scc1 .LBB0_7
.LBB0_1:
s_bitcmp1_b32 s2, 0
s_mov_b32 s5, -1
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_3
s_mul_i32 s4, s2, 3
s_mov_b32 s5, 0
s_add_i32 s4, s4, 1
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_5
s_lshr_b32 s4, s2, 1
.LBB0_5:
s_add_i32 s3, s3, 1
s_cmp_lg_u32 s4, 1
s_cbranch_scc0 .LBB0_7
s_mov_b32 s2, s4
s_branch .LBB0_1
.LBB0_7:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7collatzPj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7collatzPj, .Lfunc_end0-_Z7collatzPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7collatzPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7collatzPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <unistd.h>
#include <ctype.h>
#include <stdio.h>
#include <stdlib.h>
#define N 50000
#define CORES 50000
/* run the collatz conjecture and return the number of steps */
__global__ void collatz(unsigned int* step) {
//Set x to the initial value of step
unsigned int x = step[blockIdx.x];
//Reset step to 0
step[blockIdx.x] = 0;
/* do the iterative process */
while (x != 1) {
if ((x % 2) == 0) {
x = x / 2;
} else {
x = 3 * x + 1;
}
step[blockIdx.x]++;
}
}
int main( ) {
/* store the number of steps for each number up to N */
unsigned int cpu_steps[N];
unsigned int* gpu_steps;
/* allocate space on the GPU */
hipMalloc((void**) &gpu_steps, N * sizeof(unsigned int));
for(int i=0; i < N; i++) {
cpu_steps[i] = i+1;
}
/* send gpu_steps to the GPU */
hipMemcpy(gpu_steps, cpu_steps, N * sizeof(unsigned int), hipMemcpyHostToDevice);
/* run the collatz conjecture on all N items */
collatz<<<CORES, 1>>>(gpu_steps);
/* send gpu_steps back to the CPU */
hipMemcpy(cpu_steps, gpu_steps, N * sizeof(unsigned int), hipMemcpyDeviceToHost);
/* free the memory on the GPU */
hipFree(gpu_steps);
/* find the largest */
unsigned int largest = cpu_steps[0], largest_i = 0;
for (int i = 1; i < N; i++) {
if (cpu_steps[i] > largest) {
largest = cpu_steps[i];
largest_i = i;
}
}
/* report results */
printf("The longest collatz chain up to %d is %d with %d steps.\n",
N, largest_i + 1, largest);
return 0;
} | .text
.file "collatz.hip"
.globl _Z22__device_stub__collatzPj # -- Begin function _Z22__device_stub__collatzPj
.p2align 4, 0x90
.type _Z22__device_stub__collatzPj,@function
_Z22__device_stub__collatzPj: # @_Z22__device_stub__collatzPj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7collatzPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__collatzPj, .Lfunc_end0-_Z22__device_stub__collatzPj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $200080, %rsp # imm = 0x30D90
.cfi_def_cfa_offset 200096
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, 80(%rsp,%rax,4)
movq %rcx, %rax
cmpq $50000, %rcx # imm = 0xC350
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $200000, %edx # imm = 0x30D40
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 49999(%rdx), %rdi
xorl %ebx, %ebx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7collatzPj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $200000, %edx # imm = 0x30D40
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $1, %eax
movl 80(%rsp), %ecx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rax,4), %edx
cmpl %ecx, %edx
cmoval %edx, %ecx
cmoval %eax, %ebx
incq %rax
cmpq $50000, %rax # imm = 0xC350
jne .LBB1_5
# %bb.6:
incl %ebx
movl $.L.str, %edi
movl $50000, %esi # imm = 0xC350
movl %ebx, %edx
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $200080, %rsp # imm = 0x30D90
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7collatzPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7collatzPj,@object # @_Z7collatzPj
.section .rodata,"a",@progbits
.globl _Z7collatzPj
.p2align 3, 0x0
_Z7collatzPj:
.quad _Z22__device_stub__collatzPj
.size _Z7collatzPj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The longest collatz chain up to %d is %d with %d steps.\n"
.size .L.str, 57
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7collatzPj"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__collatzPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7collatzPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7collatzPj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x001fca00078e0003 */
/*0050*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0060*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0070*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x004fda0003f05270 */
/*0080*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0090*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fce00078e00ff */
/*00b0*/ LOP3.LUT R5, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100057812 */
/* 0x000fe400078ec0ff */
/*00c0*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*00d0*/ ISETP.NE.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f05070 */
/*00e0*/ IMAD R5, R0, 0x3, R7 ; /* 0x0000000300057824 */
/* 0x000fd800078e0207 */
/*00f0*/ @P0 SHF.R.U32.HI R5, RZ, 0x1, R0 ; /* 0x00000001ff050819 */
/* 0x000fc80000011600 */
/*0100*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f05270 */
/*0110*/ MOV R0, R5 ; /* 0x0000000500007202 */
/* 0x000fd60000000f00 */
/*0120*/ @P0 BRA 0xb0 ; /* 0xffffff8000000947 */
/* 0x000fea000383ffff */
/*0130*/ STG.E [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7collatzPj
.globl _Z7collatzPj
.p2align 8
.type _Z7collatzPj,@function
_Z7collatzPj:
s_load_b64 s[0:1], s[0:1], 0x0
s_mov_b32 s2, s15
s_mov_b32 s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_load_b32 s2, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 1
s_cbranch_scc1 .LBB0_7
.LBB0_1:
s_bitcmp1_b32 s2, 0
s_mov_b32 s5, -1
s_cselect_b32 s4, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_3
s_mul_i32 s4, s2, 3
s_mov_b32 s5, 0
s_add_i32 s4, s4, 1
.LBB0_3:
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_5
s_lshr_b32 s4, s2, 1
.LBB0_5:
s_add_i32 s3, s3, 1
s_cmp_lg_u32 s4, 1
s_cbranch_scc0 .LBB0_7
s_mov_b32 s2, s4
s_branch .LBB0_1
.LBB0_7:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s3
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7collatzPj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7collatzPj, .Lfunc_end0-_Z7collatzPj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7collatzPj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7collatzPj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012524a_00000000-6_collatz.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2073:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2073:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z7collatzPjPj
.type _Z26__device_stub__Z7collatzPjPj, @function
_Z26__device_stub__Z7collatzPjPj:
.LFB2095:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7collatzPj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2095:
.size _Z26__device_stub__Z7collatzPjPj, .-_Z26__device_stub__Z7collatzPjPj
.globl _Z7collatzPj
.type _Z7collatzPj, @function
_Z7collatzPj:
.LFB2096:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z7collatzPjPj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2096:
.size _Z7collatzPj, .-_Z7collatzPj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "The longest collatz chain up to %d is %d with %d steps.\n"
.text
.globl main
.type main, @function
main:
.LFB2070:
.cfi_startproc
endbr64
leaq -196608(%rsp), %r11
.cfi_def_cfa 11, 196616
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $3448, %rsp
.cfi_def_cfa_offset 200064
movq %fs:40, %rax
movq %rax, 200040(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $200000, %esi
call cudaMalloc@PLT
movl $1, %eax
.L12:
movl %eax, 28(%rsp,%rax,4)
addq $1, %rax
cmpq $50001, %rax
jne .L12
leaq 32(%rsp), %rsi
movl $1, %ecx
movl $200000, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $50000, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L20
.L13:
leaq 32(%rsp), %rdi
movl $2, %ecx
movl $200000, %edx
movq (%rsp), %rsi
call cudaMemcpy@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movl 32(%rsp), %r8d
movl $1, %eax
movl $0, %ecx
.L15:
movl 32(%rsp,%rax,4), %edx
cmpl %edx, %r8d
cmovb %eax, %ecx
cmovb %edx, %r8d
addq $1, %rax
cmpq $50000, %rax
jne .L15
addl $1, %ecx
movl $50000, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 200040(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $200056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
movq (%rsp), %rdi
call _Z26__device_stub__Z7collatzPjPj
jmp .L13
.L21:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "_Z7collatzPj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2098:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7collatzPj(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2098:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "collatz.hip"
.globl _Z22__device_stub__collatzPj # -- Begin function _Z22__device_stub__collatzPj
.p2align 4, 0x90
.type _Z22__device_stub__collatzPj,@function
_Z22__device_stub__collatzPj: # @_Z22__device_stub__collatzPj
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z7collatzPj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z22__device_stub__collatzPj, .Lfunc_end0-_Z22__device_stub__collatzPj
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $200080, %rsp # imm = 0x30D90
.cfi_def_cfa_offset 200096
.cfi_offset %rbx, -16
leaq 8(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
leaq 1(%rax), %rcx
movl %ecx, 80(%rsp,%rax,4)
movq %rcx, %rax
cmpq $50000, %rcx # imm = 0xC350
jne .LBB1_1
# %bb.2:
movq 8(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $200000, %edx # imm = 0x30D40
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdx # imm = 0x100000001
leaq 49999(%rdx), %rdi
xorl %ebx, %ebx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z7collatzPj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq 8(%rsp), %rsi
leaq 80(%rsp), %rdi
movl $200000, %edx # imm = 0x30D40
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movl $1, %eax
movl 80(%rsp), %ecx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rax,4), %edx
cmpl %ecx, %edx
cmoval %edx, %ecx
cmoval %eax, %ebx
incq %rax
cmpq $50000, %rax # imm = 0xC350
jne .LBB1_5
# %bb.6:
incl %ebx
movl $.L.str, %edi
movl $50000, %esi # imm = 0xC350
movl %ebx, %edx
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $200080, %rsp # imm = 0x30D90
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7collatzPj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7collatzPj,@object # @_Z7collatzPj
.section .rodata,"a",@progbits
.globl _Z7collatzPj
.p2align 3, 0x0
_Z7collatzPj:
.quad _Z22__device_stub__collatzPj
.size _Z7collatzPj, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "The longest collatz chain up to %d is %d with %d steps.\n"
.size .L.str, 57
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7collatzPj"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__collatzPj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7collatzPj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = (blockIdx.x * blockDim.x) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if (global_index_1d < num_coordinates)
{
unsigned int image_index_1d = d_coordinates[imgSize - global_index_1d - 1];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for (int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++)
{
for (int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++)
{
int2 image_offset_index_2d = make_int2(x, y);
int2 image_offset_index_2d_clamped = make_int2(min(nx - 1, max(0, image_offset_index_2d.x)), min(ny - 1, max(0, image_offset_index_2d.y)));
int image_offset_index_1d_clamped = (nx * image_offset_index_2d_clamped.y) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[image_offset_index_1d_clamped];
unsigned char b_value = d_b[image_offset_index_1d_clamped];
unsigned int gb_average = (g_value + b_value) / 2;
//printf("heya\t");
d_r_output[image_offset_index_1d_clamped] = (unsigned char)gb_average;
}
}
}
} | code for sm_80
Function : _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x188], PT ; /* 0x0000620000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ LOP3.LUT R3, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff037212 */
/* 0x000fe200078e33ff */
/*0070*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff047624 */
/* 0x000fe200078e00ff */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD R3, R4, c[0x0][0x18c], R3 ; /* 0x0000630004037a24 */
/* 0x000fc800078e0203 */
/*00b0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0202 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ I2F.U32.RP R0, c[0x0][0x190] ; /* 0x0000640000007b06 */
/* 0x000e300000209000 */
/*00e0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00f0*/ IADD3 R6, R0, 0xffffffe, RZ ; /* 0x0ffffffe00067810 */
/* 0x001fcc0007ffe0ff */
/*0100*/ F2I.FTZ.U32.TRUNC.NTZ R7, R6 ; /* 0x0000000600077305 */
/* 0x000064000021f000 */
/*0110*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x001fe400078e00ff */
/*0120*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x002fc800078e0a07 */
/*0130*/ IMAD R5, R5, c[0x0][0x190], RZ ; /* 0x0000640005057a24 */
/* 0x000fc800078e02ff */
/*0140*/ IMAD.HI.U32 R7, R7, R5, R6 ; /* 0x0000000507077227 */
/* 0x000fe200078e0006 */
/*0150*/ LOP3.LUT R6, RZ, c[0x0][0x190], RZ, 0x33, !PT ; /* 0x00006400ff067a12 */
/* 0x000fca00078e33ff */
/*0160*/ IMAD.HI.U32 R7, R7, R2, RZ ; /* 0x0000000207077227 */
/* 0x004fc800078e00ff */
/*0170*/ IMAD.MOV R3, RZ, RZ, -R7 ; /* 0x000000ffff037224 */
/* 0x000fc800078e0a07 */
/*0180*/ IMAD R2, R3, c[0x0][0x190], R2 ; /* 0x0000640003027a24 */
/* 0x000fca00078e0202 */
/*0190*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fda0003f06070 */
/*01a0*/ @P0 IADD3 R2, R2, -c[0x0][0x190], RZ ; /* 0x8000640002020a10 */
/* 0x000fe40007ffe0ff */
/*01b0*/ @P0 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107070810 */
/* 0x000fe40007ffe0ff */
/*01c0*/ ISETP.GE.U32.AND P1, PT, R2, c[0x0][0x190], PT ; /* 0x0000640002007a0c */
/* 0x000fe40003f26070 */
/*01d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x190], PT ; /* 0x00006400ff007a0c */
/* 0x000fd60003f05070 */
/*01e0*/ @P1 IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107071810 */
/* 0x000fc80007ffe0ff */
/*01f0*/ SEL R7, R6, R7, !P0 ; /* 0x0000000706077207 */
/* 0x000fc80004000000 */
/*0200*/ LOP3.LUT R7, R7, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff07077812 */
/* 0x000fc800078ec0ff */
/*0210*/ IADD3 R5, R7.reuse, -c[0x0][0x194], RZ ; /* 0x8000650007057a10 */
/* 0x040fe40007ffe0ff */
/*0220*/ IADD3 R0, R7, c[0x0][0x194], RZ ; /* 0x0000650007007a10 */
/* 0x000fc80007ffe0ff */
/*0230*/ ISETP.GT.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44270 */
/*0240*/ @P2 EXIT ; /* 0x000000000000294d */
/* 0x000fea0003800000 */
/*0250*/ IADD3 R3, R2, -c[0x0][0x190], RZ ; /* 0x8000640002037a10 */
/* 0x000fe20007ffe0ff */
/*0260*/ ULDC UR4, c[0x0][0x18c] ; /* 0x0000630000047ab9 */
/* 0x000fe20000000800 */
/*0270*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe20007ffe0ff */
/*0280*/ UIADD3 UR4, UR4, -0x1, URZ ; /* 0xffffffff04047890 */
/* 0x000fe2000fffe03f */
/*0290*/ @P0 SEL R6, R3, R2, P1 ; /* 0x0000000203060207 */
/* 0x000fc80000800000 */
/*02a0*/ LOP3.LUT R7, R6, 0xffff, RZ, 0xc0, !PT ; /* 0x0000ffff06077812 */
/* 0x000fc800078ec0ff */
/*02b0*/ IADD3 R2, R7.reuse, -c[0x0][0x198], RZ ; /* 0x8000660007027a10 */
/* 0x040fe40007ffe0ff */
/*02c0*/ IADD3 R3, R7, c[0x0][0x198], RZ ; /* 0x0000660007037a10 */
/* 0x000fe40007ffe0ff */
/*02d0*/ IMNMX R9, RZ, R2, !PT ; /* 0x00000002ff097217 */
/* 0x000fe40007800200 */
/*02e0*/ IMNMX R8, R2, R3, !PT ; /* 0x0000000302087217 */
/* 0x000fe40007800200 */
/*02f0*/ IMNMX R9, R9, R4, PT ; /* 0x0000000409097217 */
/* 0x000fe40003800200 */
/*0300*/ IADD3 R8, R8, c[0x0][0x198], RZ ; /* 0x0000660008087a10 */
/* 0x000fc80007ffe0ff */
/*0310*/ IADD3 R24, -R6, 0x1, R8 ; /* 0x0000000106187810 */
/* 0x000fe20007ffe108 */
/*0320*/ IMAD.IADD R7, R8, 0x1, -R7 ; /* 0x0000000108077824 */
/* 0x000fe200078e0a07 */
/*0330*/ IADD3 R6, R2.reuse, 0x1, RZ ; /* 0x0000000102067810 */
/* 0x040fe40007ffe0ff */
/*0340*/ IADD3 R8, R2.reuse, 0x3, RZ ; /* 0x0000000302087810 */
/* 0x040fe40007ffe0ff */
/*0350*/ ISETP.GE.U32.AND P0, PT, R7, 0x3, PT ; /* 0x000000030700780c */
/* 0x000fe40003f06070 */
/*0360*/ IADD3 R7, R2, 0x2, RZ ; /* 0x0000000202077810 */
/* 0x000fe40007ffe0ff */
/*0370*/ IMNMX R11, RZ, R6, !PT ; /* 0x00000006ff0b7217 */
/* 0x000fc40007800200 */
/*0380*/ IMNMX R13, RZ, R7, !PT ; /* 0x00000007ff0d7217 */
/* 0x000fe40007800200 */
/*0390*/ IMNMX R10, R4.reuse, R11, PT ; /* 0x0000000b040a7217 */
/* 0x040fe40003800200 */
/*03a0*/ IMNMX R11, R4, R13, PT ; /* 0x0000000d040b7217 */
/* 0x000fe40003800200 */
/*03b0*/ LOP3.LUT R24, R24, 0x3, RZ, 0xc0, !PT ; /* 0x0000000318187812 */
/* 0x000fe400078ec0ff */
/*03c0*/ ISETP.GT.AND P1, PT, R2, R3, PT ; /* 0x000000030200720c */
/* 0x000fe20003f24270 */
/*03d0*/ BSSY B0, 0xb90 ; /* 0x000007b000007945 */
/* 0x000fd80003800000 */
/*03e0*/ @P1 BRA 0xb80 ; /* 0x0000079000001947 */
/* 0x001fea0003800000 */
/*03f0*/ ISETP.NE.AND P1, PT, R24, RZ, PT ; /* 0x000000ff1800720c */
/* 0x000fe20003f25270 */
/*0400*/ BSSY B1, 0x740 ; /* 0x0000033000017945 */
/* 0x000fe20003800000 */
/*0410*/ IMNMX R26, RZ, R5, !PT ; /* 0x00000005ff1a7217 */
/* 0x000fe20007800200 */
/*0420*/ IMAD.MOV.U32 R18, RZ, RZ, R2 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0002 */
/*0430*/ IMNMX R26, R26, UR4, PT ; /* 0x000000041a1a7c17 */
/* 0x000fce000b800200 */
/*0440*/ @!P1 BRA 0x730 ; /* 0x000002e000009947 */
/* 0x000fea0003800000 */
/*0450*/ IMAD R16, R26, c[0x0][0x190], R9 ; /* 0x000064001a107a24 */
/* 0x000fca00078e0209 */
/*0460*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0470*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0480*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0490*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*04a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*04b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*04c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*04d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*04e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe40000ffe4ff */
/*04f0*/ ISETP.NE.AND P1, PT, R24, 0x1, PT ; /* 0x000000011800780c */
/* 0x000fe20003f25270 */
/*0500*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0510*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0520*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0530*/ IMAD.MOV.U32 R18, RZ, RZ, R6 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0006 */
/*0540*/ @!P1 BRA 0x730 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0550*/ IMAD R16, R26, c[0x0][0x190], R10 ; /* 0x000064001a107a24 */
/* 0x001fca00078e020a */
/*0560*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0570*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0580*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0590*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*05a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*05b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*05c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*05d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*05e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe40000ffe4ff */
/*05f0*/ ISETP.NE.AND P1, PT, R24, 0x2, PT ; /* 0x000000021800780c */
/* 0x000fe20003f25270 */
/*0600*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0610*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0620*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0630*/ IMAD.MOV.U32 R18, RZ, RZ, R7 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0007 */
/*0640*/ @!P1 BRA 0x730 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*0650*/ IMAD R16, R26, c[0x0][0x190], R11 ; /* 0x000064001a107a24 */
/* 0x001fca00078e020b */
/*0660*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0670*/ IADD3 R12, P2, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c00100c7a10 */
/* 0x040fe40007f5e0ff */
/*0680*/ IADD3 R14, P1, R16, c[0x0][0x178], RZ ; /* 0x00005e00100e7a10 */
/* 0x000fe40007f3e0ff */
/*0690*/ IADD3.X R13, R17.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00110d7a10 */
/* 0x040fe400017fe4ff */
/*06a0*/ IADD3.X R15, R17, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00110f7a10 */
/* 0x000fc80000ffe4ff */
/*06b0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*06c0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*06d0*/ IADD3 R16, P1, R16, c[0x0][0x180], RZ ; /* 0x0000600010107a10 */
/* 0x000fc80007f3e0ff */
/*06e0*/ IADD3.X R17, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610011117a10 */
/* 0x000fe20000ffe4ff */
/*06f0*/ IMAD.IADD R18, R14, 0x1, R13 ; /* 0x000000010e127824 */
/* 0x004fca00078e020d */
/*0700*/ SHF.R.U32.HI R19, RZ, 0x1, R18 ; /* 0x00000001ff137819 */
/* 0x000fca0000011612 */
/*0710*/ STG.E.U8 [R16.64], R19 ; /* 0x0000001310007986 */
/* 0x0001e2000c101106 */
/*0720*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x000fc600078e0008 */
/*0730*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0740*/ @!P0 BRA 0xb80 ; /* 0x0000043000008947 */
/* 0x000fea0003800000 */
/*0750*/ IADD3 R28, R18, 0x3, RZ ; /* 0x00000003121c7810 */
/* 0x000fc80007ffe0ff */
/*0760*/ IADD3 R12, R28, -0x3, RZ ; /* 0xfffffffd1c0c7810 */
/* 0x001fc80007ffe0ff */
/*0770*/ IMNMX R13, RZ, R12, !PT ; /* 0x0000000cff0d7217 */
/* 0x000fc80007800200 */
/*0780*/ IMNMX R13, R4, R13, PT ; /* 0x0000000d040d7217 */
/* 0x000fca0003800200 */
/*0790*/ IMAD R22, R26, c[0x0][0x190], R13 ; /* 0x000064001a167a24 */
/* 0x000fca00078e020d */
/*07a0*/ SHF.R.S32.HI R19, RZ, 0x1f, R22 ; /* 0x0000001fff137819 */
/* 0x001fe40000011416 */
/*07b0*/ IADD3 R12, P2, R22.reuse, c[0x0][0x170], RZ ; /* 0x00005c00160c7a10 */
/* 0x040fe40007f5e0ff */
/*07c0*/ IADD3 R14, P1, R22, c[0x0][0x178], RZ ; /* 0x00005e00160e7a10 */
/* 0x000fe40007f3e0ff */
/*07d0*/ IADD3.X R13, R19.reuse, c[0x0][0x174], RZ, P2, !PT ; /* 0x00005d00130d7a10 */
/* 0x040fe400017fe4ff */
/*07e0*/ IADD3.X R15, R19, c[0x0][0x17c], RZ, P1, !PT ; /* 0x00005f00130f7a10 */
/* 0x000fc80000ffe4ff */
/*07f0*/ LDG.E.U8 R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000ea8000c1e1100 */
/*0800*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000ea2000c1e1100 */
/*0810*/ IADD3 R16, R28, -0x2, RZ ; /* 0xfffffffe1c107810 */
/* 0x000fc80007ffe0ff */
/*0820*/ IMNMX R17, RZ, R16, !PT ; /* 0x00000010ff117217 */
/* 0x000fc80007800200 */
/*0830*/ IMNMX R17, R4, R17, PT ; /* 0x0000001104117217 */
/* 0x000fca0003800200 */
/*0840*/ IMAD R16, R26, c[0x0][0x190], R17 ; /* 0x000064001a107a24 */
/* 0x000fe200078e0211 */
/*0850*/ IADD3 R22, P1, R22, c[0x0][0x180], RZ ; /* 0x0000600016167a10 */
/* 0x000fc80007f3e0ff */
/*0860*/ SHF.R.S32.HI R17, RZ, 0x1f, R16 ; /* 0x0000001fff117819 */
/* 0x000fe40000011410 */
/*0870*/ IADD3 R18, P3, R16.reuse, c[0x0][0x170], RZ ; /* 0x00005c0010127a10 */
/* 0x040fe40007f7e0ff */
/*0880*/ IADD3 R20, P2, R16, c[0x0][0x178], RZ ; /* 0x00005e0010147a10 */
/* 0x000fe40007f5e0ff */
/*0890*/ IADD3.X R23, R19, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610013177a10 */
/* 0x000fe40000ffe4ff */
/*08a0*/ IADD3.X R19, R17.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0011137a10 */
/* 0x040fe40001ffe4ff */
/*08b0*/ IADD3.X R21, R17, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f0011157a10 */
/* 0x000fe200017fe4ff */
/*08c0*/ IMAD.IADD R25, R14, 0x1, R13 ; /* 0x000000010e197824 */
/* 0x004fca00078e020d */
/*08d0*/ SHF.R.U32.HI R29, RZ, 0x1, R25 ; /* 0x00000001ff1d7819 */
/* 0x000fca0000011619 */
/*08e0*/ STG.E.U8 [R22.64], R29 ; /* 0x0000001d16007986 */
/* 0x0001e8000c101106 */
/*08f0*/ LDG.E.U8 R20, [R20.64] ; /* 0x0000000614147981 */
/* 0x000e28000c1e1100 */
/*0900*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000612137981 */
/* 0x000e22000c1e1100 */
/*0910*/ IADD3 R12, R28, -0x1, RZ ; /* 0xffffffff1c0c7810 */
/* 0x000fc80007ffe0ff */
/*0920*/ IMNMX R13, RZ, R12, !PT ; /* 0x0000000cff0d7217 */
/* 0x000fc80007800200 */
/*0930*/ IMNMX R13, R4, R13, PT ; /* 0x0000000d040d7217 */
/* 0x000fca0003800200 */
/*0940*/ IMAD R27, R26, c[0x0][0x190], R13 ; /* 0x000064001a1b7a24 */
/* 0x000fe200078e020d */
/*0950*/ IADD3 R12, P1, R16, c[0x0][0x180], RZ ; /* 0x00006000100c7a10 */
/* 0x000fc80007f3e0ff */
/*0960*/ SHF.R.S32.HI R25, RZ, 0x1f, R27 ; /* 0x0000001fff197819 */
/* 0x000fe4000001141b */
/*0970*/ IADD3 R16, P3, R27.reuse, c[0x0][0x170], RZ ; /* 0x00005c001b107a10 */
/* 0x040fe40007f7e0ff */
/*0980*/ IADD3 R14, P2, R27, c[0x0][0x178], RZ ; /* 0x00005e001b0e7a10 */
/* 0x000fe40007f5e0ff */
/*0990*/ IADD3.X R13, R17, c[0x0][0x184], RZ, P1, !PT ; /* 0x00006100110d7a10 */
/* 0x000fe40000ffe4ff */
/*09a0*/ IADD3.X R17, R25.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d0019117a10 */
/* 0x040fe40001ffe4ff */
/*09b0*/ IADD3.X R15, R25, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f00190f7a10 */
/* 0x000fe200017fe4ff */
/*09c0*/ IMAD.IADD R22, R20, 0x1, R19 ; /* 0x0000000114167824 */
/* 0x001fca00078e0213 */
/*09d0*/ SHF.R.U32.HI R19, RZ, 0x1, R22 ; /* 0x00000001ff137819 */
/* 0x000fca0000011616 */
/*09e0*/ STG.E.U8 [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0001e8000c101106 */
/*09f0*/ LDG.E.U8 R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x0002a8000c1e1100 */
/*0a00*/ LDG.E.U8 R17, [R16.64] ; /* 0x0000000610117981 */
/* 0x000ea2000c1e1100 */
/*0a10*/ IMNMX R21, RZ, R28, !PT ; /* 0x0000001cff157217 */
/* 0x000fc80007800200 */
/*0a20*/ IMNMX R21, R4, R21, PT ; /* 0x0000001504157217 */
/* 0x000fe40003800200 */
/*0a30*/ IADD3 R22, P1, R27, c[0x0][0x180], RZ ; /* 0x000060001b167a10 */
/* 0x000fc60007f3e0ff */
/*0a40*/ IMAD R15, R26, c[0x0][0x190], R21 ; /* 0x000064001a0f7a24 */
/* 0x002fe200078e0215 */
/*0a50*/ IADD3.X R23, R25, c[0x0][0x184], RZ, P1, !PT ; /* 0x0000610019177a10 */
/* 0x000fc80000ffe4ff */
/*0a60*/ SHF.R.S32.HI R29, RZ, 0x1f, R15 ; /* 0x0000001fff1d7819 */
/* 0x000fe4000001140f */
/*0a70*/ IADD3 R20, P3, R15.reuse, c[0x0][0x170], RZ ; /* 0x00005c000f147a10 */
/* 0x040fe40007f7e0ff */
/*0a80*/ IADD3 R18, P2, R15, c[0x0][0x178], RZ ; /* 0x00005e000f127a10 */
/* 0x000fe40007f5e0ff */
/*0a90*/ IADD3.X R21, R29.reuse, c[0x0][0x174], RZ, P3, !PT ; /* 0x00005d001d157a10 */
/* 0x040fe40001ffe4ff */
/*0aa0*/ IADD3.X R19, R29, c[0x0][0x17c], RZ, P2, !PT ; /* 0x00005f001d137a10 */
/* 0x001fe200017fe4ff */
/*0ab0*/ IMAD.IADD R27, R14, 0x1, R17 ; /* 0x000000010e1b7824 */
/* 0x004fca00078e0211 */
/*0ac0*/ SHF.R.U32.HI R27, RZ, 0x1, R27 ; /* 0x00000001ff1b7819 */
/* 0x000fca000001161b */
/*0ad0*/ STG.E.U8 [R22.64], R27 ; /* 0x0000001b16007986 */
/* 0x0001e8000c101106 */
/*0ae0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000612127981 */
/* 0x000ea8000c1e1100 */
/*0af0*/ LDG.E.U8 R21, [R20.64] ; /* 0x0000000614157981 */
/* 0x000ea2000c1e1100 */
/*0b00*/ IADD3 R12, P1, R15, c[0x0][0x180], RZ ; /* 0x000060000f0c7a10 */
/* 0x000fc80007f3e0ff */
/*0b10*/ IADD3.X R13, R29, c[0x0][0x184], RZ, P1, !PT ; /* 0x000061001d0d7a10 */
/* 0x000fe40000ffe4ff */
/*0b20*/ ISETP.GE.AND P1, PT, R28.reuse, R3, PT ; /* 0x000000031c00720c */
/* 0x040fe40003f26270 */
/*0b30*/ IADD3 R28, R28, 0x4, RZ ; /* 0x000000041c1c7810 */
/* 0x000fe20007ffe0ff */
/*0b40*/ IMAD.IADD R14, R18, 0x1, R21 ; /* 0x00000001120e7824 */
/* 0x004fca00078e0215 */
/*0b50*/ SHF.R.U32.HI R15, RZ, 0x1, R14 ; /* 0x00000001ff0f7819 */
/* 0x000fca000001160e */
/*0b60*/ STG.E.U8 [R12.64], R15 ; /* 0x0000000f0c007986 */
/* 0x0001e2000c101106 */
/*0b70*/ @!P1 BRA 0x760 ; /* 0xfffffbe000009947 */
/* 0x000fea000383ffff */
/*0b80*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b90*/ ISETP.GE.AND P1, PT, R5.reuse, R0, PT ; /* 0x000000000500720c */
/* 0x040fe40003f26270 */
/*0ba0*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fd60007ffe0ff */
/*0bb0*/ @!P1 BRA 0x3c0 ; /* 0xfffff80000009947 */
/* 0x000fea000383ffff */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ BRA 0xbd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = (blockIdx.x * blockDim.x) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if (global_index_1d < num_coordinates)
{
unsigned int image_index_1d = d_coordinates[imgSize - global_index_1d - 1];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for (int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++)
{
for (int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++)
{
int2 image_offset_index_2d = make_int2(x, y);
int2 image_offset_index_2d_clamped = make_int2(min(nx - 1, max(0, image_offset_index_2d.x)), min(ny - 1, max(0, image_offset_index_2d.y)));
int image_offset_index_1d_clamped = (nx * image_offset_index_2d_clamped.y) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[image_offset_index_1d_clamped];
unsigned char b_value = d_b[image_offset_index_1d_clamped];
unsigned int gb_average = (g_value + b_value) / 2;
//printf("heya\t");
d_r_output[image_offset_index_1d_clamped] = (unsigned char)gb_average;
}
}
}
} | .file "tmpxft_00041cdf_00000000-6_remove_redness_from_coordinates.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
.type _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii, @function
_Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
leaq 224(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 240(%rsp), %rax
movq %rax, 176(%rsp)
leaq 248(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii, .-_Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, @function
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 40
movl 40(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 48
call _Z68__device_stub__Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiiiPKjPhS1_S1_S1_iiiii
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .-_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = (blockIdx.x * blockDim.x) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if (global_index_1d < num_coordinates)
{
unsigned int image_index_1d = d_coordinates[imgSize - global_index_1d - 1];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for (int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++)
{
for (int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++)
{
int2 image_offset_index_2d = make_int2(x, y);
int2 image_offset_index_2d_clamped = make_int2(min(nx - 1, max(0, image_offset_index_2d.x)), min(ny - 1, max(0, image_offset_index_2d.y)));
int image_offset_index_1d_clamped = (nx * image_offset_index_2d_clamped.y) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[image_offset_index_1d_clamped];
unsigned char b_value = d_b[image_offset_index_1d_clamped];
unsigned int gb_average = (g_value + b_value) / 2;
//printf("heya\t");
d_r_output[image_offset_index_1d_clamped] = (unsigned char)gb_average;
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = (blockIdx.x * blockDim.x) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if (global_index_1d < num_coordinates)
{
unsigned int image_index_1d = d_coordinates[imgSize - global_index_1d - 1];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for (int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++)
{
for (int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++)
{
int2 image_offset_index_2d = make_int2(x, y);
int2 image_offset_index_2d_clamped = make_int2(min(nx - 1, max(0, image_offset_index_2d.x)), min(ny - 1, max(0, image_offset_index_2d.y)));
int image_offset_index_1d_clamped = (nx * image_offset_index_2d_clamped.y) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[image_offset_index_1d_clamped];
unsigned char b_value = d_b[image_offset_index_1d_clamped];
unsigned int gb_average = (g_value + b_value) / 2;
//printf("heya\t");
d_r_output[image_offset_index_1d_clamped] = (unsigned char)gb_average;
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void remove_redness_from_coordinates( const unsigned int* d_coordinates, unsigned char* d_r, unsigned char* d_b, unsigned char* d_g, unsigned char* d_r_output, int num_coordinates, int num_pixels_y, int num_pixels_x, int template_half_height, int template_half_width )
{
int ny = num_pixels_y;
int nx = num_pixels_x;
int global_index_1d = (blockIdx.x * blockDim.x) + threadIdx.x;
int imgSize = num_pixels_x * num_pixels_y;
if (global_index_1d < num_coordinates)
{
unsigned int image_index_1d = d_coordinates[imgSize - global_index_1d - 1];
ushort2 image_index_2d = make_ushort2(image_index_1d % num_pixels_x, image_index_1d / num_pixels_x);
for (int y = image_index_2d.y - template_half_height; y <= image_index_2d.y + template_half_height; y++)
{
for (int x = image_index_2d.x - template_half_width; x <= image_index_2d.x + template_half_width; x++)
{
int2 image_offset_index_2d = make_int2(x, y);
int2 image_offset_index_2d_clamped = make_int2(min(nx - 1, max(0, image_offset_index_2d.x)), min(ny - 1, max(0, image_offset_index_2d.y)));
int image_offset_index_1d_clamped = (nx * image_offset_index_2d_clamped.y) + image_offset_index_2d_clamped.x;
unsigned char g_value = d_g[image_offset_index_1d_clamped];
unsigned char b_value = d_b[image_offset_index_1d_clamped];
unsigned int gb_average = (g_value + b_value) / 2;
//printf("heya\t");
d_r_output[image_offset_index_1d_clamped] = (unsigned char)gb_average;
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.globl _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.p2align 8
.type _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii,@function
_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x4c
s_load_b32 s3, s[0:1], 0x28
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x34
s_mov_b32 s10, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s7, s3, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xad_u32 v0, v1, -1, s7
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
s_sub_i32 s4, 0, s3
global_load_b32 v0, v[0:1], off
v_cvt_f32_u32_e32 v1, s3
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v1, v1
v_mul_lo_u32 v2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_add_nc_u32_e32 v1, v1, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v2, v1, s3
v_add_nc_u32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_subrev_nc_u32_e32 v4, s3, v2
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v1, v1, v3
v_cmp_le_u32_e32 vcc_lo, s3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v3, 1, v1
v_cndmask_b32_e32 v1, v1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, s3
v_sub_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_perm_b32 v2, v1, v0, 0x5040100
v_lshrrev_b32_e32 v0, 16, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_nc_u32_e32 v1, s6, v0
v_add_nc_u32_e32 v0, s6, v0
v_cmp_le_i32_e32 vcc_lo, v1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_clause 0x2
s_load_b32 s12, s[0:1], 0x38
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b64 s[8:9], s[0:1], 0x20
v_and_b32_e32 v3, 0xffff, v2
s_add_i32 s11, s3, -1
s_add_i32 s2, s2, -1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_subrev_nc_u32_e32 v2, s12, v3
v_add_nc_u32_e32 v3, s12, v3
s_lshl_b32 s0, s12, 1
s_or_b32 s12, s0, 1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_le_i32_e32 vcc_lo, v2, v3
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_4
.p2align 6
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s13
v_add_nc_u32_e32 v3, 1, v1
v_cmp_eq_u32_e64 s0, v1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mov_b32_e32 v1, v3
s_or_b32 s10, s0, s10
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s10
s_cbranch_execz .LBB0_7
.LBB0_4:
s_and_saveexec_b32 s13, vcc_lo
s_cbranch_execz .LBB0_3
v_maxmin_i32 v3, v1, 0, s2
v_mov_b32_e32 v4, v2
s_mov_b32 s14, s12
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v3, v3, s3
.p2align 6
.LBB0_6:
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_maxmin_i32 v5, v4, 0, s11
v_add_nc_u32_e32 v4, 1, v4
s_add_i32 s14, s14, -1
s_cmp_eq_u32 s14, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v9, v5, v3
v_ashrrev_i32_e32 v10, 31, v9
v_add_co_u32 v7, s1, s6, v9
v_add_co_u32 v5, s0, s4, v9
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e64 v8, s1, s7, v10, s1
v_add_co_ci_u32_e64 v6, s0, s5, v10, s0
global_load_u8 v7, v[7:8], off
global_load_u8 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_add_nc_u16 v7, v5, v7
v_add_co_u32 v5, s0, s8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v6, s0, s9, v10, s0
v_lshrrev_b16 v7, 1, v7
global_store_b8 v[5:6], v7, off
s_cbranch_scc0 .LBB0_6
s_branch .LBB0_3
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 320
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii, .Lfunc_end0-_Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 52
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: by_value
- .offset: 64
.size: 4
.value_kind: hidden_block_count_x
- .offset: 68
.size: 4
.value_kind: hidden_block_count_y
- .offset: 72
.size: 4
.value_kind: hidden_block_count_z
- .offset: 76
.size: 2
.value_kind: hidden_group_size_x
- .offset: 78
.size: 2
.value_kind: hidden_group_size_y
- .offset: 80
.size: 2
.value_kind: hidden_group_size_z
- .offset: 82
.size: 2
.value_kind: hidden_remainder_x
- .offset: 84
.size: 2
.value_kind: hidden_remainder_y
- .offset: 86
.size: 2
.value_kind: hidden_remainder_z
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 120
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 128
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 320
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31remove_redness_from_coordinatesPKjPhS1_S1_S1_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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