system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <sys/time.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 1000
#define CUDA_SAFE_CALL(call) \
{ \
cudaError err = call; \
if (cudaSuccess != err) \
{ \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, cudaGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
double timestamp()
{
struct timeval tv;
gettimeofday(&tv, 0);
return tv.tv_sec + 1e-6 * tv.tv_usec;
}
void Floyd_sequential(unsigned int *mat, const size_t N)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
void Floyd_count(unsigned int *ref, const size_t N, unsigned int *reference_cnt)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
if(k == 0) {
reference_cnt[i0] += 2;
reference_cnt[i1] += 1;
reference_cnt[i2] += 1;
}
//mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
__global__ void gpu_Floyd(unsigned int *result, int N, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
//printf("row: %d, col: %d\n", row, col);
if (row < N && col < N)
{
int i0 = row * N + col;
int i1 = row * N + k;
int i2 = k * N + col;
//printf("result[%d][%d]: %d, result[%d][%d]: %d, result[%d][%d]: %d\n", row, col,result[i0], row, k, result[i1],k, col, result[i2]);
result[i0] = (result[i0] < result[i1] + result[i2]) ? result[i0] : (result[i1] + result[i2]);
}
}
void GenMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
mat[i] = rand() % 32;
if (mat[i] == 0)
{
mat[i] = INT_MAX / 2;
}
if (i % N == i / N)
{
mat[i] = 0;
}
}
}
void showMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
printf("mat[%d] = %d, ", i, mat[i]);
}
printf("done\n");
}
bool CmpArray(const unsigned int *l, const unsigned int *r, const size_t eleNum)
{
for (int i = 0; i < eleNum; i++)
if (l[i] != r[i])
{
printf("ERROR: l[%d] = %d, r[%d] = %d\n", i, l[i], i, r[i]);
return false;
}
return true;
}
int main(int argc, char **argv)
{
// generate a random matrix.
size_t N = MATRIX_SIZE;
unsigned int *mat = (unsigned int *)malloc(sizeof(int) * N * N);
unsigned int *reference_cnt = (unsigned int *)malloc(sizeof(int) * N * N);
memset(reference_cnt, 0, sizeof(int) * N * N);
GenMatrix(mat, N);
// compute the reference result.
unsigned int *ref = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(ref, mat, sizeof(int) * N * N);
//printf("mat\n");
//showMatrix(mat, N);
double time1 = timestamp();
Floyd_sequential(ref, N);
double time2 = timestamp();
//Floyd_count(ref, N, reference_cnt);
//showMatrix(reference_cnt, N);
//printf("ref\n");
//showMatrix(ref, N);
//CUDA Portion
unsigned int *result = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(result, mat, sizeof(int) * N * N);
unsigned int *d_result;
// compute your results
CUDA_SAFE_CALL(cudaMalloc((void **)&d_result, sizeof(int) * N * N));
CUDA_SAFE_CALL(cudaMemcpy(d_result, result, sizeof(int) * N * N, cudaMemcpyHostToDevice));
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid((size_t)ceil(((float)N) / ((float)block.x)), (size_t)ceil(((float)N) / ((float)block.y)));
double time3 = timestamp();
for (int k = 0; k < N; k++)
{
gpu_Floyd<<<grid, block>>>(d_result, N, k);
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err)
{
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n",
__FILE__, __LINE__, cudaGetErrorString(err));
}
}
double time4 = timestamp();
CUDA_SAFE_CALL(cudaMemcpy(result, d_result, sizeof(int) * N * N, cudaMemcpyDeviceToHost));
//printf("result\n");
//showMatrix(result, N);
printf("sequential time use: %f, cuda time use: %f\nspeedup-rate: %f\n", time2 - time1, time4 - time3, (time2 - time1) / (time4 - time3));
// compare your result with reference result
if (CmpArray(result, ref, N * N))
printf("The matrix matches.\n");
else
printf("The matrix do not match.\n");
free(ref);
free(mat);
free(result);
cudaFree(d_result);
} | code for sm_80
Function : _Z9gpu_FloydPjii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R4, R0, R6, c[0x0][0x16c] ; /* 0x00005b0000047624 */
/* 0x000fe400078e0206 */
/*00e0*/ IMAD R6, R6, c[0x0][0x16c], R3.reuse ; /* 0x00005b0006067a24 */
/* 0x100fe400078e0203 */
/*00f0*/ IMAD R3, R0, c[0x0][0x168], R3 ; /* 0x00005a0000037a24 */
/* 0x000fe400078e0203 */
/*0100*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0209 */
/*0110*/ IMAD.WIDE R6, R6, R9.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe400078e0209 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0130*/ IMAD.WIDE R2, R3, R9, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe400078e0209 */
/*0140*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ee2000c1e1900 */
/*0160*/ IADD3 R0, R6, R5, RZ ; /* 0x0000000506007210 */
/* 0x004fc80007ffe0ff */
/*0170*/ IMNMX.U32 R9, R0, R9, PT ; /* 0x0000000900097217 */
/* 0x008fca0003800000 */
/*0180*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <sys/time.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 1000
#define CUDA_SAFE_CALL(call) \
{ \
cudaError err = call; \
if (cudaSuccess != err) \
{ \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, cudaGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
double timestamp()
{
struct timeval tv;
gettimeofday(&tv, 0);
return tv.tv_sec + 1e-6 * tv.tv_usec;
}
void Floyd_sequential(unsigned int *mat, const size_t N)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
void Floyd_count(unsigned int *ref, const size_t N, unsigned int *reference_cnt)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
if(k == 0) {
reference_cnt[i0] += 2;
reference_cnt[i1] += 1;
reference_cnt[i2] += 1;
}
//mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
__global__ void gpu_Floyd(unsigned int *result, int N, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
//printf("row: %d, col: %d\n", row, col);
if (row < N && col < N)
{
int i0 = row * N + col;
int i1 = row * N + k;
int i2 = k * N + col;
//printf("result[%d][%d]: %d, result[%d][%d]: %d, result[%d][%d]: %d\n", row, col,result[i0], row, k, result[i1],k, col, result[i2]);
result[i0] = (result[i0] < result[i1] + result[i2]) ? result[i0] : (result[i1] + result[i2]);
}
}
void GenMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
mat[i] = rand() % 32;
if (mat[i] == 0)
{
mat[i] = INT_MAX / 2;
}
if (i % N == i / N)
{
mat[i] = 0;
}
}
}
void showMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
printf("mat[%d] = %d, ", i, mat[i]);
}
printf("done\n");
}
bool CmpArray(const unsigned int *l, const unsigned int *r, const size_t eleNum)
{
for (int i = 0; i < eleNum; i++)
if (l[i] != r[i])
{
printf("ERROR: l[%d] = %d, r[%d] = %d\n", i, l[i], i, r[i]);
return false;
}
return true;
}
int main(int argc, char **argv)
{
// generate a random matrix.
size_t N = MATRIX_SIZE;
unsigned int *mat = (unsigned int *)malloc(sizeof(int) * N * N);
unsigned int *reference_cnt = (unsigned int *)malloc(sizeof(int) * N * N);
memset(reference_cnt, 0, sizeof(int) * N * N);
GenMatrix(mat, N);
// compute the reference result.
unsigned int *ref = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(ref, mat, sizeof(int) * N * N);
//printf("mat\n");
//showMatrix(mat, N);
double time1 = timestamp();
Floyd_sequential(ref, N);
double time2 = timestamp();
//Floyd_count(ref, N, reference_cnt);
//showMatrix(reference_cnt, N);
//printf("ref\n");
//showMatrix(ref, N);
//CUDA Portion
unsigned int *result = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(result, mat, sizeof(int) * N * N);
unsigned int *d_result;
// compute your results
CUDA_SAFE_CALL(cudaMalloc((void **)&d_result, sizeof(int) * N * N));
CUDA_SAFE_CALL(cudaMemcpy(d_result, result, sizeof(int) * N * N, cudaMemcpyHostToDevice));
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid((size_t)ceil(((float)N) / ((float)block.x)), (size_t)ceil(((float)N) / ((float)block.y)));
double time3 = timestamp();
for (int k = 0; k < N; k++)
{
gpu_Floyd<<<grid, block>>>(d_result, N, k);
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err)
{
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n",
__FILE__, __LINE__, cudaGetErrorString(err));
}
}
double time4 = timestamp();
CUDA_SAFE_CALL(cudaMemcpy(result, d_result, sizeof(int) * N * N, cudaMemcpyDeviceToHost));
//printf("result\n");
//showMatrix(result, N);
printf("sequential time use: %f, cuda time use: %f\nspeedup-rate: %f\n", time2 - time1, time4 - time3, (time2 - time1) / (time4 - time3));
// compare your result with reference result
if (CmpArray(result, ref, N * N))
printf("The matrix matches.\n");
else
printf("The matrix do not match.\n");
free(ref);
free(mat);
free(result);
cudaFree(d_result);
} | .file "tmpxft_000fda23_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9timestampv
.type _Z9timestampv, @function
_Z9timestampv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9timestampv, .-_Z9timestampv
.globl _Z16Floyd_sequentialPjm
.type _Z16Floyd_sequentialPjm, @function
_Z16Floyd_sequentialPjm:
.LFB2058:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L15
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, %r9
movl %esi, %r11d
leal 1(%rsi), %r13d
movl %esi, %r12d
movl $0, %ebp
movl $0, %r8d
movl $0, %ebx
movl $0, %ecx
movl %ecx, %esi
.L9:
movl %r8d, %r10d
movl $0, %ecx
movl %esi, -4(%rsp)
.L12:
leal (%r10,%rbp), %eax
cltq
leaq (%rdi,%rax,4), %r14
movl %ebx, %edx
.L10:
leal (%r10,%rdx), %eax
cltq
leaq (%rdi,%rax,4), %rsi
movslq %edx, %r15
movl (%r14), %eax
addl (%rdi,%r15,4), %eax
movl (%rsi), %r15d
cmpl %r15d, %eax
cmova %r15d, %eax
movl %eax, (%rsi)
addl $1, %edx
cmpl %r9d, %edx
jne .L10
addl $1, %ecx
addl %r11d, %r10d
cmpl %r12d, %ecx
jne .L12
movl -4(%rsp), %esi
addl $1, %esi
addl %r11d, %ebx
addl %r11d, %r9d
subl %r11d, %r8d
addl %r13d, %ebp
cmpl %r12d, %esi
jne .L9
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2058:
.size _Z16Floyd_sequentialPjm, .-_Z16Floyd_sequentialPjm
.globl _Z11Floyd_countPjmS_
.type _Z11Floyd_countPjmS_, @function
_Z11Floyd_countPjmS_:
.LFB2059:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L27
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbp
movq %rdx, %rcx
movl %esi, %r11d
movl $0, %r12d
movl $0, %edi
jmp .L20
.L21:
addl $1, %eax
cmpl %eax, %esi
je .L30
.L22:
testl %edi, %edi
jne .L21
movslq %eax, %rdx
addl $2, (%rcx,%rdx,4)
addl $1, (%r8)
leal (%rax,%r9), %edx
movslq %edx, %rdx
addl $1, (%rcx,%rdx,4)
jmp .L21
.L30:
addl $1, %ebx
addl %r11d, %esi
addl %r11d, %r10d
subl %r11d, %r9d
cmpl %ebp, %ebx
je .L23
.L24:
leal (%rdi,%r10), %eax
cltq
leaq (%rcx,%rax,4), %r8
movl %r10d, %eax
jmp .L22
.L23:
addl $1, %edi
addl %r11d, %r12d
cmpl %ebp, %edi
je .L18
.L20:
movl %r12d, %r9d
movl %r11d, %esi
movl $0, %r10d
movl $0, %ebx
jmp .L24
.L18:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2059:
.size _Z11Floyd_countPjmS_, .-_Z11Floyd_countPjmS_
.globl _Z9GenMatrixPjm
.type _Z9GenMatrixPjm, @function
_Z9GenMatrixPjm:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r13
imulq %rsi, %r13
testq %r13, %r13
je .L31
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
movl $1073741823, %r14d
.L35:
call rand@PLT
cltd
shrl $27, %edx
leal (%rax,%rdx), %ecx
andl $31, %ecx
subl %edx, %ecx
cmove %r14d, %ecx
movq %rbx, %rax
movl $0, %edx
divq %rbp
cmpq %rax, %rdx
movl $0, %eax
cmove %eax, %ecx
movl %ecx, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r13
jne .L35
.L31:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9GenMatrixPjm, .-_Z9GenMatrixPjm
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "mat[%d] = %d, "
.LC2:
.string "done\n"
.text
.globl _Z10showMatrixPjm
.type _Z10showMatrixPjm, @function
_Z10showMatrixPjm:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbp
imulq %rsi, %rbp
testq %rbp, %rbp
je .L39
movq %rdi, %r12
movl $0, %ebx
leaq .LC1(%rip), %r13
.L40:
movl (%r12,%rbx,4), %ecx
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %rbp
jne .L40
.L39:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z10showMatrixPjm, .-_Z10showMatrixPjm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "ERROR: l[%d] = %d, r[%d] = %d\n"
.text
.globl _Z8CmpArrayPKjS0_m
.type _Z8CmpArrayPKjS0_m, @function
_Z8CmpArrayPKjS0_m:
.LFB2062:
.cfi_startproc
endbr64
testq %rdx, %rdx
je .L47
movl $0, %r8d
.L46:
movl (%rdi,%r8,4), %ecx
movl (%rsi,%r8,4), %r9d
cmpl %r9d, %ecx
jne .L53
addq $1, %r8
cmpq %r8, %rdx
jne .L46
movl $1, %eax
ret
.L53:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %r8d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L47:
movl $1, %eax
ret
.cfi_endproc
.LFE2062:
.size _Z8CmpArrayPKjS0_m, .-_Z8CmpArrayPKjS0_m
.globl _Z30__device_stub__Z9gpu_FloydPjiiPjii
.type _Z30__device_stub__Z9gpu_FloydPjiiPjii, @function
_Z30__device_stub__Z9gpu_FloydPjiiPjii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L58
.L54:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9gpu_FloydPjii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L54
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z30__device_stub__Z9gpu_FloydPjiiPjii, .-_Z30__device_stub__Z9gpu_FloydPjiiPjii
.globl _Z9gpu_FloydPjii
.type _Z9gpu_FloydPjii, @function
_Z9gpu_FloydPjii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9gpu_FloydPjiiPjii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z9gpu_FloydPjii, .-_Z9gpu_FloydPjii
.section .rodata.str1.8
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/yifanliuu/Paralleled-All-pairs-shortest-paths-blocked-Floyd-algorithm/master/src/simple.cu"
.align 8
.LC5:
.string "Cuda error in file '%s' in line %i : %s.\n"
.align 8
.LC6:
.string "sequential time use: %f, cuda time use: %f\nspeedup-rate: %f\n"
.section .rodata.str1.1
.LC7:
.string "The matrix matches.\n"
.LC8:
.string "The matrix do not match.\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call malloc@PLT
movq %rax, %r14
movl $4000000, %edi
call malloc@PLT
movq %rax, %rdi
movl $4000000, %edx
movl $0, %esi
call memset@PLT
movl $1000, %esi
movq %r14, %rdi
call _Z9GenMatrixPjm
movl $4000000, %edi
call malloc@PLT
movq %rax, %r15
movl $4000000, %edx
movq %r14, %rsi
movq %rax, %rdi
call memcpy@PLT
call _Z9timestampv
movsd %xmm0, (%rsp)
movl $1000, %esi
movq %r15, %rdi
call _Z16Floyd_sequentialPjm
call _Z9timestampv
movsd %xmm0, 8(%rsp)
movl $4000000, %edi
call malloc@PLT
movq %rax, %r13
movl $4000000, %edx
movq %r14, %rsi
movq %rax, %rdi
call memcpy@PLT
leaq 40(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L74
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L75
movl $1, 56(%rsp)
movl $125, 60(%rsp)
movl $125, 64(%rsp)
movl $1, 68(%rsp)
call _Z9timestampv
movsd %xmm0, 16(%rsp)
movl $0, %ebx
leaq .LC4(%rip), %r12
leaq .LC5(%rip), %rbp
jmp .L67
.L74:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $142, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $144, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L76
.L66:
addl $1, %ebx
cmpl $1000, %ebx
je .L77
.L67:
movl $8, 48(%rsp)
movl $8, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L65
movl %ebx, %edx
movl $1000, %esi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z9gpu_FloydPjiiPjii
jmp .L65
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $155, %r8d
movq %r12, %rcx
movq %rbp, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L66
.L77:
call _Z9timestampv
movsd %xmm0, 24(%rsp)
movl $2, %ecx
movl $4000000, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L78
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
movsd 24(%rsp), %xmm1
subsd 16(%rsp), %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $1000000, %edx
movq %r15, %rsi
movq %r13, %rdi
call _Z8CmpArrayPKjS0_m
testb %al, %al
je .L69
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L70:
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L79
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $159, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L70
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9gpu_FloydPjii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpu_FloydPjii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#include <sys/time.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 1000
#define CUDA_SAFE_CALL(call) \
{ \
cudaError err = call; \
if (cudaSuccess != err) \
{ \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, cudaGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
double timestamp()
{
struct timeval tv;
gettimeofday(&tv, 0);
return tv.tv_sec + 1e-6 * tv.tv_usec;
}
void Floyd_sequential(unsigned int *mat, const size_t N)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
void Floyd_count(unsigned int *ref, const size_t N, unsigned int *reference_cnt)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
if(k == 0) {
reference_cnt[i0] += 2;
reference_cnt[i1] += 1;
reference_cnt[i2] += 1;
}
//mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
__global__ void gpu_Floyd(unsigned int *result, int N, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
//printf("row: %d, col: %d\n", row, col);
if (row < N && col < N)
{
int i0 = row * N + col;
int i1 = row * N + k;
int i2 = k * N + col;
//printf("result[%d][%d]: %d, result[%d][%d]: %d, result[%d][%d]: %d\n", row, col,result[i0], row, k, result[i1],k, col, result[i2]);
result[i0] = (result[i0] < result[i1] + result[i2]) ? result[i0] : (result[i1] + result[i2]);
}
}
void GenMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
mat[i] = rand() % 32;
if (mat[i] == 0)
{
mat[i] = INT_MAX / 2;
}
if (i % N == i / N)
{
mat[i] = 0;
}
}
}
void showMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
printf("mat[%d] = %d, ", i, mat[i]);
}
printf("done\n");
}
bool CmpArray(const unsigned int *l, const unsigned int *r, const size_t eleNum)
{
for (int i = 0; i < eleNum; i++)
if (l[i] != r[i])
{
printf("ERROR: l[%d] = %d, r[%d] = %d\n", i, l[i], i, r[i]);
return false;
}
return true;
}
int main(int argc, char **argv)
{
// generate a random matrix.
size_t N = MATRIX_SIZE;
unsigned int *mat = (unsigned int *)malloc(sizeof(int) * N * N);
unsigned int *reference_cnt = (unsigned int *)malloc(sizeof(int) * N * N);
memset(reference_cnt, 0, sizeof(int) * N * N);
GenMatrix(mat, N);
// compute the reference result.
unsigned int *ref = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(ref, mat, sizeof(int) * N * N);
//printf("mat\n");
//showMatrix(mat, N);
double time1 = timestamp();
Floyd_sequential(ref, N);
double time2 = timestamp();
//Floyd_count(ref, N, reference_cnt);
//showMatrix(reference_cnt, N);
//printf("ref\n");
//showMatrix(ref, N);
//CUDA Portion
unsigned int *result = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(result, mat, sizeof(int) * N * N);
unsigned int *d_result;
// compute your results
CUDA_SAFE_CALL(cudaMalloc((void **)&d_result, sizeof(int) * N * N));
CUDA_SAFE_CALL(cudaMemcpy(d_result, result, sizeof(int) * N * N, cudaMemcpyHostToDevice));
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid((size_t)ceil(((float)N) / ((float)block.x)), (size_t)ceil(((float)N) / ((float)block.y)));
double time3 = timestamp();
for (int k = 0; k < N; k++)
{
gpu_Floyd<<<grid, block>>>(d_result, N, k);
cudaError_t err = cudaGetLastError();
if (cudaSuccess != err)
{
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n",
__FILE__, __LINE__, cudaGetErrorString(err));
}
}
double time4 = timestamp();
CUDA_SAFE_CALL(cudaMemcpy(result, d_result, sizeof(int) * N * N, cudaMemcpyDeviceToHost));
//printf("result\n");
//showMatrix(result, N);
printf("sequential time use: %f, cuda time use: %f\nspeedup-rate: %f\n", time2 - time1, time4 - time3, (time2 - time1) / (time4 - time3));
// compare your result with reference result
if (CmpArray(result, ref, N * N))
printf("The matrix matches.\n");
else
printf("The matrix do not match.\n");
free(ref);
free(mat);
free(result);
cudaFree(d_result);
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <sys/time.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 1000
#define CUDA_SAFE_CALL(call) \
{ \
hipError_t err = call; \
if (hipSuccess != err) \
{ \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, hipGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
double timestamp()
{
struct timeval tv;
gettimeofday(&tv, 0);
return tv.tv_sec + 1e-6 * tv.tv_usec;
}
void Floyd_sequential(unsigned int *mat, const size_t N)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
void Floyd_count(unsigned int *ref, const size_t N, unsigned int *reference_cnt)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
if(k == 0) {
reference_cnt[i0] += 2;
reference_cnt[i1] += 1;
reference_cnt[i2] += 1;
}
//mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
__global__ void gpu_Floyd(unsigned int *result, int N, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
//printf("row: %d, col: %d\n", row, col);
if (row < N && col < N)
{
int i0 = row * N + col;
int i1 = row * N + k;
int i2 = k * N + col;
//printf("result[%d][%d]: %d, result[%d][%d]: %d, result[%d][%d]: %d\n", row, col,result[i0], row, k, result[i1],k, col, result[i2]);
result[i0] = (result[i0] < result[i1] + result[i2]) ? result[i0] : (result[i1] + result[i2]);
}
}
void GenMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
mat[i] = rand() % 32;
if (mat[i] == 0)
{
mat[i] = INT_MAX / 2;
}
if (i % N == i / N)
{
mat[i] = 0;
}
}
}
void showMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
printf("mat[%d] = %d, ", i, mat[i]);
}
printf("done\n");
}
bool CmpArray(const unsigned int *l, const unsigned int *r, const size_t eleNum)
{
for (int i = 0; i < eleNum; i++)
if (l[i] != r[i])
{
printf("ERROR: l[%d] = %d, r[%d] = %d\n", i, l[i], i, r[i]);
return false;
}
return true;
}
int main(int argc, char **argv)
{
// generate a random matrix.
size_t N = MATRIX_SIZE;
unsigned int *mat = (unsigned int *)malloc(sizeof(int) * N * N);
unsigned int *reference_cnt = (unsigned int *)malloc(sizeof(int) * N * N);
memset(reference_cnt, 0, sizeof(int) * N * N);
GenMatrix(mat, N);
// compute the reference result.
unsigned int *ref = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(ref, mat, sizeof(int) * N * N);
//printf("mat\n");
//showMatrix(mat, N);
double time1 = timestamp();
Floyd_sequential(ref, N);
double time2 = timestamp();
//Floyd_count(ref, N, reference_cnt);
//showMatrix(reference_cnt, N);
//printf("ref\n");
//showMatrix(ref, N);
//CUDA Portion
unsigned int *result = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(result, mat, sizeof(int) * N * N);
unsigned int *d_result;
// compute your results
CUDA_SAFE_CALL(hipMalloc((void **)&d_result, sizeof(int) * N * N));
CUDA_SAFE_CALL(hipMemcpy(d_result, result, sizeof(int) * N * N, hipMemcpyHostToDevice));
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid((size_t)ceil(((float)N) / ((float)block.x)), (size_t)ceil(((float)N) / ((float)block.y)));
double time3 = timestamp();
for (int k = 0; k < N; k++)
{
gpu_Floyd<<<grid, block>>>(d_result, N, k);
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n",
__FILE__, __LINE__, hipGetErrorString(err));
}
}
double time4 = timestamp();
CUDA_SAFE_CALL(hipMemcpy(result, d_result, sizeof(int) * N * N, hipMemcpyDeviceToHost));
//printf("result\n");
//showMatrix(result, N);
printf("sequential time use: %f, cuda time use: %f\nspeedup-rate: %f\n", time2 - time1, time4 - time3, (time2 - time1) / (time4 - time3));
// compare your result with reference result
if (CmpArray(result, ref, N * N))
printf("The matrix matches.\n");
else
printf("The matrix do not match.\n");
free(ref);
free(mat);
free(result);
hipFree(d_result);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <sys/time.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 1000
#define CUDA_SAFE_CALL(call) \
{ \
hipError_t err = call; \
if (hipSuccess != err) \
{ \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, hipGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
double timestamp()
{
struct timeval tv;
gettimeofday(&tv, 0);
return tv.tv_sec + 1e-6 * tv.tv_usec;
}
void Floyd_sequential(unsigned int *mat, const size_t N)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
void Floyd_count(unsigned int *ref, const size_t N, unsigned int *reference_cnt)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
if(k == 0) {
reference_cnt[i0] += 2;
reference_cnt[i1] += 1;
reference_cnt[i2] += 1;
}
//mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
__global__ void gpu_Floyd(unsigned int *result, int N, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
//printf("row: %d, col: %d\n", row, col);
if (row < N && col < N)
{
int i0 = row * N + col;
int i1 = row * N + k;
int i2 = k * N + col;
//printf("result[%d][%d]: %d, result[%d][%d]: %d, result[%d][%d]: %d\n", row, col,result[i0], row, k, result[i1],k, col, result[i2]);
result[i0] = (result[i0] < result[i1] + result[i2]) ? result[i0] : (result[i1] + result[i2]);
}
}
void GenMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
mat[i] = rand() % 32;
if (mat[i] == 0)
{
mat[i] = INT_MAX / 2;
}
if (i % N == i / N)
{
mat[i] = 0;
}
}
}
void showMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
printf("mat[%d] = %d, ", i, mat[i]);
}
printf("done\n");
}
bool CmpArray(const unsigned int *l, const unsigned int *r, const size_t eleNum)
{
for (int i = 0; i < eleNum; i++)
if (l[i] != r[i])
{
printf("ERROR: l[%d] = %d, r[%d] = %d\n", i, l[i], i, r[i]);
return false;
}
return true;
}
int main(int argc, char **argv)
{
// generate a random matrix.
size_t N = MATRIX_SIZE;
unsigned int *mat = (unsigned int *)malloc(sizeof(int) * N * N);
unsigned int *reference_cnt = (unsigned int *)malloc(sizeof(int) * N * N);
memset(reference_cnt, 0, sizeof(int) * N * N);
GenMatrix(mat, N);
// compute the reference result.
unsigned int *ref = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(ref, mat, sizeof(int) * N * N);
//printf("mat\n");
//showMatrix(mat, N);
double time1 = timestamp();
Floyd_sequential(ref, N);
double time2 = timestamp();
//Floyd_count(ref, N, reference_cnt);
//showMatrix(reference_cnt, N);
//printf("ref\n");
//showMatrix(ref, N);
//CUDA Portion
unsigned int *result = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(result, mat, sizeof(int) * N * N);
unsigned int *d_result;
// compute your results
CUDA_SAFE_CALL(hipMalloc((void **)&d_result, sizeof(int) * N * N));
CUDA_SAFE_CALL(hipMemcpy(d_result, result, sizeof(int) * N * N, hipMemcpyHostToDevice));
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid((size_t)ceil(((float)N) / ((float)block.x)), (size_t)ceil(((float)N) / ((float)block.y)));
double time3 = timestamp();
for (int k = 0; k < N; k++)
{
gpu_Floyd<<<grid, block>>>(d_result, N, k);
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n",
__FILE__, __LINE__, hipGetErrorString(err));
}
}
double time4 = timestamp();
CUDA_SAFE_CALL(hipMemcpy(result, d_result, sizeof(int) * N * N, hipMemcpyDeviceToHost));
//printf("result\n");
//showMatrix(result, N);
printf("sequential time use: %f, cuda time use: %f\nspeedup-rate: %f\n", time2 - time1, time4 - time3, (time2 - time1) / (time4 - time3));
// compare your result with reference result
if (CmpArray(result, ref, N * N))
printf("The matrix matches.\n");
else
printf("The matrix do not match.\n");
free(ref);
free(mat);
free(result);
hipFree(d_result);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9gpu_FloydPjii
.globl _Z9gpu_FloydPjii
.p2align 8
.type _Z9gpu_FloydPjii,@function
_Z9gpu_FloydPjii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b32 s3, s[0:1], 0xc
v_mul_lo_u32 v2, v2, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v2, v0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s3, v2
v_mad_u64_u32 v[3:4], null, s3, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
s_clause 0x2
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v0, v1, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_u32_e32 v0, v2, v0
global_store_b32 v[4:5], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9gpu_FloydPjii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9gpu_FloydPjii, .Lfunc_end0-_Z9gpu_FloydPjii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9gpu_FloydPjii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9gpu_FloydPjii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <sys/time.h>
#define BLOCK_SIZE 8
#define MATRIX_SIZE 1000
#define CUDA_SAFE_CALL(call) \
{ \
hipError_t err = call; \
if (hipSuccess != err) \
{ \
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n", \
__FILE__, __LINE__, hipGetErrorString(err)); \
exit(EXIT_FAILURE); \
} \
}
double timestamp()
{
struct timeval tv;
gettimeofday(&tv, 0);
return tv.tv_sec + 1e-6 * tv.tv_usec;
}
void Floyd_sequential(unsigned int *mat, const size_t N)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
void Floyd_count(unsigned int *ref, const size_t N, unsigned int *reference_cnt)
{
for (int k = 0; k < N; k++)
for (int i = 0; i < N; i++)
for (int j = 0; j < N; j++)
{
int i0 = i * N + j;
int i1 = i * N + k;
int i2 = k * N + j;
if(k == 0) {
reference_cnt[i0] += 2;
reference_cnt[i1] += 1;
reference_cnt[i2] += 1;
}
//mat[i0] = (mat[i0] < mat[i1] + mat[i2]) ? mat[i0] : (mat[i1] + mat[i2]);
}
}
__global__ void gpu_Floyd(unsigned int *result, int N, int k)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
//printf("row: %d, col: %d\n", row, col);
if (row < N && col < N)
{
int i0 = row * N + col;
int i1 = row * N + k;
int i2 = k * N + col;
//printf("result[%d][%d]: %d, result[%d][%d]: %d, result[%d][%d]: %d\n", row, col,result[i0], row, k, result[i1],k, col, result[i2]);
result[i0] = (result[i0] < result[i1] + result[i2]) ? result[i0] : (result[i1] + result[i2]);
}
}
void GenMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
mat[i] = rand() % 32;
if (mat[i] == 0)
{
mat[i] = INT_MAX / 2;
}
if (i % N == i / N)
{
mat[i] = 0;
}
}
}
void showMatrix(unsigned int *mat, const size_t N)
{
for (int i = 0; i < N * N; i++)
{
printf("mat[%d] = %d, ", i, mat[i]);
}
printf("done\n");
}
bool CmpArray(const unsigned int *l, const unsigned int *r, const size_t eleNum)
{
for (int i = 0; i < eleNum; i++)
if (l[i] != r[i])
{
printf("ERROR: l[%d] = %d, r[%d] = %d\n", i, l[i], i, r[i]);
return false;
}
return true;
}
int main(int argc, char **argv)
{
// generate a random matrix.
size_t N = MATRIX_SIZE;
unsigned int *mat = (unsigned int *)malloc(sizeof(int) * N * N);
unsigned int *reference_cnt = (unsigned int *)malloc(sizeof(int) * N * N);
memset(reference_cnt, 0, sizeof(int) * N * N);
GenMatrix(mat, N);
// compute the reference result.
unsigned int *ref = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(ref, mat, sizeof(int) * N * N);
//printf("mat\n");
//showMatrix(mat, N);
double time1 = timestamp();
Floyd_sequential(ref, N);
double time2 = timestamp();
//Floyd_count(ref, N, reference_cnt);
//showMatrix(reference_cnt, N);
//printf("ref\n");
//showMatrix(ref, N);
//CUDA Portion
unsigned int *result = (unsigned int *)malloc(sizeof(int) * N * N);
memcpy(result, mat, sizeof(int) * N * N);
unsigned int *d_result;
// compute your results
CUDA_SAFE_CALL(hipMalloc((void **)&d_result, sizeof(int) * N * N));
CUDA_SAFE_CALL(hipMemcpy(d_result, result, sizeof(int) * N * N, hipMemcpyHostToDevice));
dim3 block(BLOCK_SIZE, BLOCK_SIZE);
dim3 grid((size_t)ceil(((float)N) / ((float)block.x)), (size_t)ceil(((float)N) / ((float)block.y)));
double time3 = timestamp();
for (int k = 0; k < N; k++)
{
gpu_Floyd<<<grid, block>>>(d_result, N, k);
hipError_t err = hipGetLastError();
if (hipSuccess != err)
{
fprintf(stderr, "Cuda error in file '%s' in line %i : %s.\n",
__FILE__, __LINE__, hipGetErrorString(err));
}
}
double time4 = timestamp();
CUDA_SAFE_CALL(hipMemcpy(result, d_result, sizeof(int) * N * N, hipMemcpyDeviceToHost));
//printf("result\n");
//showMatrix(result, N);
printf("sequential time use: %f, cuda time use: %f\nspeedup-rate: %f\n", time2 - time1, time4 - time3, (time2 - time1) / (time4 - time3));
// compare your result with reference result
if (CmpArray(result, ref, N * N))
printf("The matrix matches.\n");
else
printf("The matrix do not match.\n");
free(ref);
free(mat);
free(result);
hipFree(d_result);
} | .text
.file "simple.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9timestampv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9timestampv
.p2align 4, 0x90
.type _Z9timestampv,@function
_Z9timestampv: # @_Z9timestampv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9timestampv, .Lfunc_end0-_Z9timestampv
.cfi_endproc
# -- End function
.globl _Z16Floyd_sequentialPjm # -- Begin function _Z16Floyd_sequentialPjm
.p2align 4, 0x90
.type _Z16Floyd_sequentialPjm,@function
_Z16Floyd_sequentialPjm: # @_Z16Floyd_sequentialPjm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB1_8
# %bb.1: # %.preheader39.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rax
shlq $32, %rax
xorl %ecx, %ecx
movabsq $4294967296, %rdx # imm = 0x100000000
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_2: # %.preheader39
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
# Child Loop BB1_4 Depth 3
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
movl %r10d, %r11d
imull %esi, %r11d
addl %r8d, %r11d
movslq %r11d, %r11
movq %rcx, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
leal (%r9,%r14), %ebp
movslq %ebp, %r15
movq %rbx, %r12
sarq $30, %r12
movl (%rdi,%r12), %ebp
addl (%rdi,%r11,4), %ebp
movl (%rdi,%r15,4), %r12d
cmpl %ebp, %r12d
cmovbl %r12d, %ebp
movl %ebp, (%rdi,%r15,4)
incq %r14
addq %rdx, %rbx
cmpq %r14, %rsi
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=2
incq %r10
addq %rsi, %r9
cmpq %rsi, %r10
jne .LBB1_3
# %bb.6: # in Loop: Header=BB1_2 Depth=1
incq %r8
addq %rax, %rcx
cmpq %rsi, %r8
jne .LBB1_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_8: # %._crit_edge
retq
.Lfunc_end1:
.size _Z16Floyd_sequentialPjm, .Lfunc_end1-_Z16Floyd_sequentialPjm
.cfi_endproc
# -- End function
.globl _Z11Floyd_countPjmS_ # -- Begin function _Z11Floyd_countPjmS_
.p2align 4, 0x90
.type _Z11Floyd_countPjmS_,@function
_Z11Floyd_countPjmS_: # @_Z11Floyd_countPjmS_
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB2_9
# %bb.1: # %.preheader30.lr.ph
xorl %eax, %eax
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_2 Depth=1
incq %rax
cmpq %rsi, %rax
je .LBB2_9
.LBB2_2: # %.preheader30
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
xorl %ecx, %ecx
xorl %edi, %edi
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_3 Depth=2
incq %rdi
addq %rsi, %rcx
cmpq %rsi, %rdi
je .LBB2_8
.LBB2_3: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
movl %edi, %r8d
imull %esi, %r8d
movslq %r8d, %r8
xorl %r9d, %r9d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=3
incq %r9
cmpq %r9, %rsi
je .LBB2_7
.LBB2_4: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
testq %rax, %rax
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=3
leal (%rcx,%r9), %r10d
movslq %r10d, %r10
addl $2, (%rdx,%r10,4)
incl (%rdx,%r8,4)
incl (%rdx,%r9,4)
jmp .LBB2_6
.LBB2_9: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11Floyd_countPjmS_, .Lfunc_end2-_Z11Floyd_countPjmS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__gpu_FloydPjii # -- Begin function _Z24__device_stub__gpu_FloydPjii
.p2align 4, 0x90
.type _Z24__device_stub__gpu_FloydPjii,@function
_Z24__device_stub__gpu_FloydPjii: # @_Z24__device_stub__gpu_FloydPjii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9gpu_FloydPjii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z24__device_stub__gpu_FloydPjii, .Lfunc_end3-_Z24__device_stub__gpu_FloydPjii
.cfi_endproc
# -- End function
.globl _Z9GenMatrixPjm # -- Begin function _Z9GenMatrixPjm
.p2align 4, 0x90
.type _Z9GenMatrixPjm,@function
_Z9GenMatrixPjm: # @_Z9GenMatrixPjm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
imulq %rsi, %r12
testq %r12, %r12
je .LBB4_3
# %bb.1: # %.lr.ph.preheader
movq %rsi, %rbx
movq %rdi, %r14
xorl %r13d, %r13d
movl $1073741823, %ebp # imm = 0x3FFFFFFF
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
leal 31(%rcx), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
andl $-32, %eax
subl %eax, %ecx
cmovel %ebp, %ecx
movq %r15, %rax
xorl %edx, %edx
divq %rbx
cmpq %rax, %rdx
cmovel %r13d, %ecx
movl %ecx, (%r14,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB4_2
.LBB4_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z9GenMatrixPjm, .Lfunc_end4-_Z9GenMatrixPjm
.cfi_endproc
# -- End function
.globl _Z10showMatrixPjm # -- Begin function _Z10showMatrixPjm
.p2align 4, 0x90
.type _Z10showMatrixPjm,@function
_Z10showMatrixPjm: # @_Z10showMatrixPjm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
imulq %rsi, %rbx
testq %rbx, %rbx
je .LBB5_3
# %bb.1: # %.lr.ph.preheader
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %edx
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %rbx
jne .LBB5_2
.LBB5_3: # %._crit_edge
movl $.Lstr, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end5:
.size _Z10showMatrixPjm, .Lfunc_end5-_Z10showMatrixPjm
.cfi_endproc
# -- End function
.globl _Z8CmpArrayPKjS0_m # -- Begin function _Z8CmpArrayPKjS0_m
.p2align 4, 0x90
.type _Z8CmpArrayPKjS0_m,@function
_Z8CmpArrayPKjS0_m: # @_Z8CmpArrayPKjS0_m
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
testq %rdx, %rdx
sete %bl
je .LBB6_8
# %bb.1: # %.lr.ph.preheader
movl (%rdi), %eax
movl (%rsi), %r8d
xorl %ecx, %ecx
cmpl %r8d, %eax
jne .LBB6_6
# %bb.2: # %.lr.ph40.preheader
leaq -1(%rdx), %r9
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_3: # %.lr.ph40
# =>This Inner Loop Header: Depth=1
cmpq %rcx, %r9
je .LBB6_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB6_3 Depth=1
movl 4(%rdi,%rcx,4), %eax
movl 4(%rsi,%rcx,4), %r8d
incq %rcx
cmpl %r8d, %eax
je .LBB6_3
# %bb.5: # %.lr.ph._crit_edge
cmpq %rdx, %rcx
setae %bl
.LBB6_6:
movl $.L.str.2, %edi
movl %ecx, %esi
movl %eax, %edx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
jmp .LBB6_8
.LBB6_7:
movb $1, %bl
.LBB6_8: # %.loopexit
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z8CmpArrayPKjS0_m, .Lfunc_end6-_Z8CmpArrayPKjS0_m
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
movl $1073741823, %ebp # imm = 0x3FFFFFFF
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB7_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r13, %rax
shrq $3, %rax
mulq %r12
movq %rdx, %r14
shrq $4, %r14
movq %rbx, %r15
imulq $-1000, %r14, %rbx # imm = 0xFC18
callq rand
# kill: def $eax killed $eax def $rax
leal 31(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-32, %ecx
subl %ecx, %eax
cmovel %ebp, %eax
addq %r13, %rbx
cmpq %r14, %rbx
movq %r15, %rbx
movl $0, %ecx
cmovel %ecx, %eax
movl %eax, (%r15,%r13,4)
incq %r13
cmpq $1000000, %r13 # imm = 0xF4240
jne .LBB7_1
# %bb.2: # %_Z9GenMatrixPjm.exit
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movl $4000000, %edx # imm = 0x3D0900
movq %rax, %rdi
movq %rbx, %rsi
callq memcpy@PLT
xorl %r12d, %r12d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm0
movq (%rsp), %r15
mulsd .LCPI7_0(%rip), %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
movq %r14, %rax
.p2align 4, 0x90
.LBB7_3: # %.preheader39.i
# =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
# Child Loop BB7_5 Depth 3
movq %r14, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_4: # %.preheader.i
# Parent Loop BB7_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_5 Depth 3
imull $1000, %edx, %esi # imm = 0x3E8
addl %r12d, %esi
movslq %esi, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB7_5: # Parent Loop BB7_3 Depth=1
# Parent Loop BB7_4 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rax,%rdi,4), %r8d
addl (%r14,%rsi,4), %r8d
movl (%rcx,%rdi,4), %r9d
cmpl %r8d, %r9d
cmovbl %r9d, %r8d
movl %r8d, (%rcx,%rdi,4)
incq %rdi
cmpq $1000, %rdi # imm = 0x3E8
jne .LBB7_5
# %bb.6: # in Loop: Header=BB7_4 Depth=2
incq %rdx
addq $4000, %rcx # imm = 0xFA0
cmpq $1000, %rdx # imm = 0x3E8
jne .LBB7_4
# %bb.7: # in Loop: Header=BB7_3 Depth=1
incq %r12
addq $4000, %rax # imm = 0xFA0
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB7_3
# %bb.8: # %_Z16Floyd_sequentialPjm.exit
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r12
movl $4000000, %edx # imm = 0x3D0900
movq %rax, %rdi
movq %rbx, %rsi
callq memcpy@PLT
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB7_9
# %bb.11:
movq 24(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r12, 72(%rsp) # 8-byte Spill
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_12
# %bb.13:
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
movsd 48(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 48(%rsp) # 8-byte Spill
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI7_0(%rip), %xmm0
addsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 40(%rsp) # 8-byte Spill
movq %rsp, %r15
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI7_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movabsq $536870912125, %r13 # imm = 0x7D0000007D
movabsq $34359738376, %rbp # imm = 0x800000008
xorl %r12d, %r12d
jmp .LBB7_14
.p2align 4, 0x90
.LBB7_16: # in Loop: Header=BB7_14 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB7_17
.LBB7_18: # in Loop: Header=BB7_14 Depth=1
incl %r12d
cmpl $1000, %r12d # imm = 0x3E8
je .LBB7_19
.LBB7_14: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_16
# %bb.15: # in Loop: Header=BB7_14 Depth=1
movq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1000, 60(%rsp) # imm = 0x3E8
movl %r12d, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 60(%rsp), %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z9gpu_FloydPjii, %edi
movq %r15, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_16
.LBB7_17: # in Loop: Header=BB7_14 Depth=1
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %r15, %rdi
movq %rsp, %r15
movl $155, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB7_18
.LBB7_19:
xorl %r12d, %r12d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r15
movq 8(%rsp), %r13
movq 24(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 72(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_20
# %bb.21:
xorps %xmm0, %xmm0
cvtsi2sdq 64(%rsp), %xmm0 # 8-byte Folded Reload
cvtsi2sd %r13, %xmm2
mulsd .LCPI7_0(%rip), %xmm2
movsd 32(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
addsd %xmm0, %xmm3
xorps %xmm1, %xmm1
cvtsi2sd %r15, %xmm1
addsd %xmm2, %xmm1
subsd %xmm3, %xmm1
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 48(%rsp), %xmm0 # 8-byte Folded Reload
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
movl $.L.str.5, %edi
movb $3, %al
callq printf
movl (%rbp), %edx
movl (%r14), %r8d
movl $0, %r15d
cmpl %r8d, %edx
jne .LBB7_26
# %bb.22: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_23: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $999999, %r12 # imm = 0xF423F
je .LBB7_27
# %bb.24: # %.lr.ph.i79
# in Loop: Header=BB7_23 Depth=1
movl 4(%rbp,%r12,4), %edx
movl 4(%r14,%r12,4), %r8d
incq %r12
cmpl %r8d, %edx
je .LBB7_23
# %bb.25: # %.lr.ph.i79._crit_edge.loopexit
leaq -1(%r12), %rax
cmpq $999999, %rax # imm = 0xF423F
setae %r15b
.LBB7_26: # %.lr.ph.i79._crit_edge
movl $.L.str.2, %edi
movl %r12d, %esi
movl %r12d, %ecx
xorl %eax, %eax
callq printf
jmp .LBB7_28
.LBB7_27: # %_Z8CmpArrayPKjS0_m.exit.loopexit
setae %r15b
.LBB7_28: # %_Z8CmpArrayPKjS0_m.exit
movl $.Lstr.2, %eax
movl $.Lstr.1, %edi
testb %r15b, %r15b
cmovneq %rax, %rdi
callq puts@PLT
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq %rbp, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_9:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $142, %ecx
jmp .LBB7_10
.LBB7_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $144, %ecx
jmp .LBB7_10
.LBB7_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $159, %ecx
.LBB7_10:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpu_FloydPjii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9gpu_FloydPjii,@object # @_Z9gpu_FloydPjii
.section .rodata,"a",@progbits
.globl _Z9gpu_FloydPjii
.p2align 3, 0x0
_Z9gpu_FloydPjii:
.quad _Z24__device_stub__gpu_FloydPjii
.size _Z9gpu_FloydPjii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "mat[%d] = %d, "
.size .L.str, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: l[%d] = %d, r[%d] = %d\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda error in file '%s' in line %i : %s.\n"
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/yifanliuu/Paralleled-All-pairs-shortest-paths-blocked-Floyd-algorithm/master/src/simple.hip"
.size .L.str.4, 149
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "sequential time use: %f, cuda time use: %f\nspeedup-rate: %f\n"
.size .L.str.5, 61
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9gpu_FloydPjii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "done"
.size .Lstr, 5
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "The matrix do not match."
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "The matrix matches."
.size .Lstr.2, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__gpu_FloydPjii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9gpu_FloydPjii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9gpu_FloydPjii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x168], PT ; /* 0x00005a0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R6, c[0x0][0x168] ; /* 0x00005a0000067a02 */
/* 0x000fe20000000f00 */
/*00b0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00d0*/ IMAD R4, R0, R6, c[0x0][0x16c] ; /* 0x00005b0000047624 */
/* 0x000fe400078e0206 */
/*00e0*/ IMAD R6, R6, c[0x0][0x16c], R3.reuse ; /* 0x00005b0006067a24 */
/* 0x100fe400078e0203 */
/*00f0*/ IMAD R3, R0, c[0x0][0x168], R3 ; /* 0x00005a0000037a24 */
/* 0x000fe400078e0203 */
/*0100*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0209 */
/*0110*/ IMAD.WIDE R6, R6, R9.reuse, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x080fe400078e0209 */
/*0120*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0130*/ IMAD.WIDE R2, R3, R9, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fe400078e0209 */
/*0140*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0150*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ee2000c1e1900 */
/*0160*/ IADD3 R0, R6, R5, RZ ; /* 0x0000000506007210 */
/* 0x004fc80007ffe0ff */
/*0170*/ IMNMX.U32 R9, R0, R9, PT ; /* 0x0000000900097217 */
/* 0x008fca0003800000 */
/*0180*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9gpu_FloydPjii
.globl _Z9gpu_FloydPjii
.p2align 8
.type _Z9gpu_FloydPjii,@function
_Z9gpu_FloydPjii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s3, v[4:5]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_2
s_load_b32 s3, s[0:1], 0xc
v_mul_lo_u32 v2, v2, s2
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v2, v0
v_ashrrev_i32_e32 v6, 31, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[5:6]
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, s3, v2
v_mad_u64_u32 v[3:4], null, s3, s2, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_lshlrev_b64 v[2:3], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v6, vcc_lo
s_clause 0x2
global_load_b32 v0, v[0:1], off
global_load_b32 v1, v[2:3], off
global_load_b32 v2, v[4:5], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v0, v1, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_min_u32_e32 v0, v2, v0
global_store_b32 v[4:5], v0, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9gpu_FloydPjii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9gpu_FloydPjii, .Lfunc_end0-_Z9gpu_FloydPjii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9gpu_FloydPjii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9gpu_FloydPjii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fda23_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9timestampv
.type _Z9timestampv, @function
_Z9timestampv:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z9timestampv, .-_Z9timestampv
.globl _Z16Floyd_sequentialPjm
.type _Z16Floyd_sequentialPjm, @function
_Z16Floyd_sequentialPjm:
.LFB2058:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L15
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, %r9
movl %esi, %r11d
leal 1(%rsi), %r13d
movl %esi, %r12d
movl $0, %ebp
movl $0, %r8d
movl $0, %ebx
movl $0, %ecx
movl %ecx, %esi
.L9:
movl %r8d, %r10d
movl $0, %ecx
movl %esi, -4(%rsp)
.L12:
leal (%r10,%rbp), %eax
cltq
leaq (%rdi,%rax,4), %r14
movl %ebx, %edx
.L10:
leal (%r10,%rdx), %eax
cltq
leaq (%rdi,%rax,4), %rsi
movslq %edx, %r15
movl (%r14), %eax
addl (%rdi,%r15,4), %eax
movl (%rsi), %r15d
cmpl %r15d, %eax
cmova %r15d, %eax
movl %eax, (%rsi)
addl $1, %edx
cmpl %r9d, %edx
jne .L10
addl $1, %ecx
addl %r11d, %r10d
cmpl %r12d, %ecx
jne .L12
movl -4(%rsp), %esi
addl $1, %esi
addl %r11d, %ebx
addl %r11d, %r9d
subl %r11d, %r8d
addl %r13d, %ebp
cmpl %r12d, %esi
jne .L9
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2058:
.size _Z16Floyd_sequentialPjm, .-_Z16Floyd_sequentialPjm
.globl _Z11Floyd_countPjmS_
.type _Z11Floyd_countPjmS_, @function
_Z11Floyd_countPjmS_:
.LFB2059:
.cfi_startproc
endbr64
testq %rsi, %rsi
je .L27
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rsi, %rbp
movq %rdx, %rcx
movl %esi, %r11d
movl $0, %r12d
movl $0, %edi
jmp .L20
.L21:
addl $1, %eax
cmpl %eax, %esi
je .L30
.L22:
testl %edi, %edi
jne .L21
movslq %eax, %rdx
addl $2, (%rcx,%rdx,4)
addl $1, (%r8)
leal (%rax,%r9), %edx
movslq %edx, %rdx
addl $1, (%rcx,%rdx,4)
jmp .L21
.L30:
addl $1, %ebx
addl %r11d, %esi
addl %r11d, %r10d
subl %r11d, %r9d
cmpl %ebp, %ebx
je .L23
.L24:
leal (%rdi,%r10), %eax
cltq
leaq (%rcx,%rax,4), %r8
movl %r10d, %eax
jmp .L22
.L23:
addl $1, %edi
addl %r11d, %r12d
cmpl %ebp, %edi
je .L18
.L20:
movl %r12d, %r9d
movl %r11d, %esi
movl $0, %r10d
movl $0, %ebx
jmp .L24
.L18:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
ret
.cfi_endproc
.LFE2059:
.size _Z11Floyd_countPjmS_, .-_Z11Floyd_countPjmS_
.globl _Z9GenMatrixPjm
.type _Z9GenMatrixPjm, @function
_Z9GenMatrixPjm:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rsi, %r13
imulq %rsi, %r13
testq %r13, %r13
je .L31
movq %rdi, %r12
movq %rsi, %rbp
movl $0, %ebx
movl $1073741823, %r14d
.L35:
call rand@PLT
cltd
shrl $27, %edx
leal (%rax,%rdx), %ecx
andl $31, %ecx
subl %edx, %ecx
cmove %r14d, %ecx
movq %rbx, %rax
movl $0, %edx
divq %rbp
cmpq %rax, %rdx
movl $0, %eax
cmove %eax, %ecx
movl %ecx, (%r12,%rbx,4)
addq $1, %rbx
cmpq %rbx, %r13
jne .L35
.L31:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z9GenMatrixPjm, .-_Z9GenMatrixPjm
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "mat[%d] = %d, "
.LC2:
.string "done\n"
.text
.globl _Z10showMatrixPjm
.type _Z10showMatrixPjm, @function
_Z10showMatrixPjm:
.LFB2061:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movq %rsi, %rbp
imulq %rsi, %rbp
testq %rbp, %rbp
je .L39
movq %rdi, %r12
movl $0, %ebx
leaq .LC1(%rip), %r13
.L40:
movl (%r12,%rbx,4), %ecx
movl %ebx, %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %rbp
jne .L40
.L39:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z10showMatrixPjm, .-_Z10showMatrixPjm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "ERROR: l[%d] = %d, r[%d] = %d\n"
.text
.globl _Z8CmpArrayPKjS0_m
.type _Z8CmpArrayPKjS0_m, @function
_Z8CmpArrayPKjS0_m:
.LFB2062:
.cfi_startproc
endbr64
testq %rdx, %rdx
je .L47
movl $0, %r8d
.L46:
movl (%rdi,%r8,4), %ecx
movl (%rsi,%r8,4), %r9d
cmpl %r9d, %ecx
jne .L53
addq $1, %r8
cmpq %r8, %rdx
jne .L46
movl $1, %eax
ret
.L53:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %r8d, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L47:
movl $1, %eax
ret
.cfi_endproc
.LFE2062:
.size _Z8CmpArrayPKjS0_m, .-_Z8CmpArrayPKjS0_m
.globl _Z30__device_stub__Z9gpu_FloydPjiiPjii
.type _Z30__device_stub__Z9gpu_FloydPjiiPjii, @function
_Z30__device_stub__Z9gpu_FloydPjiiPjii:
.LFB2088:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L58
.L54:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L59
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9gpu_FloydPjii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L54
.L59:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z30__device_stub__Z9gpu_FloydPjiiPjii, .-_Z30__device_stub__Z9gpu_FloydPjiiPjii
.globl _Z9gpu_FloydPjii
.type _Z9gpu_FloydPjii, @function
_Z9gpu_FloydPjii:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9gpu_FloydPjiiPjii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z9gpu_FloydPjii, .-_Z9gpu_FloydPjii
.section .rodata.str1.8
.align 8
.LC4:
.string "/home/ubuntu/Datasets/stackv2/train-structured/yifanliuu/Paralleled-All-pairs-shortest-paths-blocked-Floyd-algorithm/master/src/simple.cu"
.align 8
.LC5:
.string "Cuda error in file '%s' in line %i : %s.\n"
.align 8
.LC6:
.string "sequential time use: %f, cuda time use: %f\nspeedup-rate: %f\n"
.section .rodata.str1.1
.LC7:
.string "The matrix matches.\n"
.LC8:
.string "The matrix do not match.\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call malloc@PLT
movq %rax, %r14
movl $4000000, %edi
call malloc@PLT
movq %rax, %rdi
movl $4000000, %edx
movl $0, %esi
call memset@PLT
movl $1000, %esi
movq %r14, %rdi
call _Z9GenMatrixPjm
movl $4000000, %edi
call malloc@PLT
movq %rax, %r15
movl $4000000, %edx
movq %r14, %rsi
movq %rax, %rdi
call memcpy@PLT
call _Z9timestampv
movsd %xmm0, (%rsp)
movl $1000, %esi
movq %r15, %rdi
call _Z16Floyd_sequentialPjm
call _Z9timestampv
movsd %xmm0, 8(%rsp)
movl $4000000, %edi
call malloc@PLT
movq %rax, %r13
movl $4000000, %edx
movq %r14, %rsi
movq %rax, %rdi
call memcpy@PLT
leaq 40(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L74
movl $1, %ecx
movl $4000000, %edx
movq %r13, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L75
movl $1, 56(%rsp)
movl $125, 60(%rsp)
movl $125, 64(%rsp)
movl $1, 68(%rsp)
call _Z9timestampv
movsd %xmm0, 16(%rsp)
movl $0, %ebx
leaq .LC4(%rip), %r12
leaq .LC5(%rip), %rbp
jmp .L67
.L74:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $142, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L75:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $144, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L65:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L76
.L66:
addl $1, %ebx
cmpl $1000, %ebx
je .L77
.L67:
movl $8, 48(%rsp)
movl $8, 52(%rsp)
movl 56(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movq 60(%rsp), %rdi
movl 68(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L65
movl %ebx, %edx
movl $1000, %esi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z9gpu_FloydPjiiPjii
jmp .L65
.L76:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $155, %r8d
movq %r12, %rcx
movq %rbp, %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
jmp .L66
.L77:
call _Z9timestampv
movsd %xmm0, 24(%rsp)
movl $2, %ecx
movl $4000000, %edx
movq 40(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L78
movsd 8(%rsp), %xmm0
subsd (%rsp), %xmm0
movsd 24(%rsp), %xmm1
subsd 16(%rsp), %xmm1
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $1000000, %edx
movq %r15, %rsi
movq %r13, %rdi
call _Z8CmpArrayPKjS0_m
testb %al, %al
je .L69
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L70:
movq %r15, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L79
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L78:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r9
movl $159, %r8d
leaq .LC4(%rip), %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L69:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L70
.L79:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z9gpu_FloydPjii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9gpu_FloydPjii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z9timestampv
.LCPI0_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z9timestampv
.p2align 4, 0x90
.type _Z9timestampv,@function
_Z9timestampv: # @_Z9timestampv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm1
cvtsi2sdq 16(%rsp), %xmm0
mulsd .LCPI0_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9timestampv, .Lfunc_end0-_Z9timestampv
.cfi_endproc
# -- End function
.globl _Z16Floyd_sequentialPjm # -- Begin function _Z16Floyd_sequentialPjm
.p2align 4, 0x90
.type _Z16Floyd_sequentialPjm,@function
_Z16Floyd_sequentialPjm: # @_Z16Floyd_sequentialPjm
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB1_8
# %bb.1: # %.preheader39.lr.ph
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rax
shlq $32, %rax
xorl %ecx, %ecx
movabsq $4294967296, %rdx # imm = 0x100000000
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_2: # %.preheader39
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
# Child Loop BB1_4 Depth 3
xorl %r9d, %r9d
xorl %r10d, %r10d
.p2align 4, 0x90
.LBB1_3: # %.preheader
# Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_4 Depth 3
movl %r10d, %r11d
imull %esi, %r11d
addl %r8d, %r11d
movslq %r11d, %r11
movq %rcx, %rbx
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_3 Depth=2
# => This Inner Loop Header: Depth=3
leal (%r9,%r14), %ebp
movslq %ebp, %r15
movq %rbx, %r12
sarq $30, %r12
movl (%rdi,%r12), %ebp
addl (%rdi,%r11,4), %ebp
movl (%rdi,%r15,4), %r12d
cmpl %ebp, %r12d
cmovbl %r12d, %ebp
movl %ebp, (%rdi,%r15,4)
incq %r14
addq %rdx, %rbx
cmpq %r14, %rsi
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=2
incq %r10
addq %rsi, %r9
cmpq %rsi, %r10
jne .LBB1_3
# %bb.6: # in Loop: Header=BB1_2 Depth=1
incq %r8
addq %rax, %rcx
cmpq %rsi, %r8
jne .LBB1_2
# %bb.7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_8: # %._crit_edge
retq
.Lfunc_end1:
.size _Z16Floyd_sequentialPjm, .Lfunc_end1-_Z16Floyd_sequentialPjm
.cfi_endproc
# -- End function
.globl _Z11Floyd_countPjmS_ # -- Begin function _Z11Floyd_countPjmS_
.p2align 4, 0x90
.type _Z11Floyd_countPjmS_,@function
_Z11Floyd_countPjmS_: # @_Z11Floyd_countPjmS_
.cfi_startproc
# %bb.0:
testq %rsi, %rsi
je .LBB2_9
# %bb.1: # %.preheader30.lr.ph
xorl %eax, %eax
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_8: # in Loop: Header=BB2_2 Depth=1
incq %rax
cmpq %rsi, %rax
je .LBB2_9
.LBB2_2: # %.preheader30
# =>This Loop Header: Depth=1
# Child Loop BB2_3 Depth 2
# Child Loop BB2_4 Depth 3
xorl %ecx, %ecx
xorl %edi, %edi
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_3 Depth=2
incq %rdi
addq %rsi, %rcx
cmpq %rsi, %rdi
je .LBB2_8
.LBB2_3: # %.preheader
# Parent Loop BB2_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_4 Depth 3
movl %edi, %r8d
imull %esi, %r8d
movslq %r8d, %r8
xorl %r9d, %r9d
jmp .LBB2_4
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_4 Depth=3
incq %r9
cmpq %r9, %rsi
je .LBB2_7
.LBB2_4: # Parent Loop BB2_2 Depth=1
# Parent Loop BB2_3 Depth=2
# => This Inner Loop Header: Depth=3
testq %rax, %rax
jne .LBB2_6
# %bb.5: # in Loop: Header=BB2_4 Depth=3
leal (%rcx,%r9), %r10d
movslq %r10d, %r10
addl $2, (%rdx,%r10,4)
incl (%rdx,%r8,4)
incl (%rdx,%r9,4)
jmp .LBB2_6
.LBB2_9: # %._crit_edge
retq
.Lfunc_end2:
.size _Z11Floyd_countPjmS_, .Lfunc_end2-_Z11Floyd_countPjmS_
.cfi_endproc
# -- End function
.globl _Z24__device_stub__gpu_FloydPjii # -- Begin function _Z24__device_stub__gpu_FloydPjii
.p2align 4, 0x90
.type _Z24__device_stub__gpu_FloydPjii,@function
_Z24__device_stub__gpu_FloydPjii: # @_Z24__device_stub__gpu_FloydPjii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9gpu_FloydPjii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end3:
.size _Z24__device_stub__gpu_FloydPjii, .Lfunc_end3-_Z24__device_stub__gpu_FloydPjii
.cfi_endproc
# -- End function
.globl _Z9GenMatrixPjm # -- Begin function _Z9GenMatrixPjm
.p2align 4, 0x90
.type _Z9GenMatrixPjm,@function
_Z9GenMatrixPjm: # @_Z9GenMatrixPjm
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r12
imulq %rsi, %r12
testq %r12, %r12
je .LBB4_3
# %bb.1: # %.lr.ph.preheader
movq %rsi, %rbx
movq %rdi, %r14
xorl %r13d, %r13d
movl $1073741823, %ebp # imm = 0x3FFFFFFF
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
movl %eax, %ecx
leal 31(%rcx), %eax
testl %ecx, %ecx
cmovnsl %ecx, %eax
andl $-32, %eax
subl %eax, %ecx
cmovel %ebp, %ecx
movq %r15, %rax
xorl %edx, %edx
divq %rbx
cmpq %rax, %rdx
cmovel %r13d, %ecx
movl %ecx, (%r14,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB4_2
.LBB4_3: # %._crit_edge
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z9GenMatrixPjm, .Lfunc_end4-_Z9GenMatrixPjm
.cfi_endproc
# -- End function
.globl _Z10showMatrixPjm # -- Begin function _Z10showMatrixPjm
.p2align 4, 0x90
.type _Z10showMatrixPjm,@function
_Z10showMatrixPjm: # @_Z10showMatrixPjm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
imulq %rsi, %rbx
testq %rbx, %rbx
je .LBB5_3
# %bb.1: # %.lr.ph.preheader
movq %rdi, %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB5_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%r14,%r15,4), %edx
movl $.L.str, %edi
movl %r15d, %esi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %rbx
jne .LBB5_2
.LBB5_3: # %._crit_edge
movl $.Lstr, %edi
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end5:
.size _Z10showMatrixPjm, .Lfunc_end5-_Z10showMatrixPjm
.cfi_endproc
# -- End function
.globl _Z8CmpArrayPKjS0_m # -- Begin function _Z8CmpArrayPKjS0_m
.p2align 4, 0x90
.type _Z8CmpArrayPKjS0_m,@function
_Z8CmpArrayPKjS0_m: # @_Z8CmpArrayPKjS0_m
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
testq %rdx, %rdx
sete %bl
je .LBB6_8
# %bb.1: # %.lr.ph.preheader
movl (%rdi), %eax
movl (%rsi), %r8d
xorl %ecx, %ecx
cmpl %r8d, %eax
jne .LBB6_6
# %bb.2: # %.lr.ph40.preheader
leaq -1(%rdx), %r9
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB6_3: # %.lr.ph40
# =>This Inner Loop Header: Depth=1
cmpq %rcx, %r9
je .LBB6_7
# %bb.4: # %.lr.ph
# in Loop: Header=BB6_3 Depth=1
movl 4(%rdi,%rcx,4), %eax
movl 4(%rsi,%rcx,4), %r8d
incq %rcx
cmpl %r8d, %eax
je .LBB6_3
# %bb.5: # %.lr.ph._crit_edge
cmpq %rdx, %rcx
setae %bl
.LBB6_6:
movl $.L.str.2, %edi
movl %ecx, %esi
movl %eax, %edx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq printf
jmp .LBB6_8
.LBB6_7:
movb $1, %bl
.LBB6_8: # %.loopexit
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z8CmpArrayPKjS0_m, .Lfunc_end6-_Z8CmpArrayPKjS0_m
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI7_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movabsq $2361183241434822607, %r12 # imm = 0x20C49BA5E353F7CF
movl $1073741823, %ebp # imm = 0x3FFFFFFF
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB7_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movq %r13, %rax
shrq $3, %rax
mulq %r12
movq %rdx, %r14
shrq $4, %r14
movq %rbx, %r15
imulq $-1000, %r14, %rbx # imm = 0xFC18
callq rand
# kill: def $eax killed $eax def $rax
leal 31(%rax), %ecx
testl %eax, %eax
cmovnsl %eax, %ecx
andl $-32, %ecx
subl %ecx, %eax
cmovel %ebp, %eax
addq %r13, %rbx
cmpq %r14, %rbx
movq %r15, %rbx
movl $0, %ecx
cmovel %ecx, %eax
movl %eax, (%r15,%r13,4)
incq %r13
cmpq $1000000, %r13 # imm = 0xF4240
jne .LBB7_1
# %bb.2: # %_Z9GenMatrixPjm.exit
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movl $4000000, %edx # imm = 0x3D0900
movq %rax, %rdi
movq %rbx, %rsi
callq memcpy@PLT
xorl %r12d, %r12d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 8(%rsp), %xmm0
movq (%rsp), %r15
mulsd .LCPI7_0(%rip), %xmm0
movsd %xmm0, 48(%rsp) # 8-byte Spill
movq %r14, %rax
.p2align 4, 0x90
.LBB7_3: # %.preheader39.i
# =>This Loop Header: Depth=1
# Child Loop BB7_4 Depth 2
# Child Loop BB7_5 Depth 3
movq %r14, %rcx
xorl %edx, %edx
.p2align 4, 0x90
.LBB7_4: # %.preheader.i
# Parent Loop BB7_3 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB7_5 Depth 3
imull $1000, %edx, %esi # imm = 0x3E8
addl %r12d, %esi
movslq %esi, %rsi
xorl %edi, %edi
.p2align 4, 0x90
.LBB7_5: # Parent Loop BB7_3 Depth=1
# Parent Loop BB7_4 Depth=2
# => This Inner Loop Header: Depth=3
movl (%rax,%rdi,4), %r8d
addl (%r14,%rsi,4), %r8d
movl (%rcx,%rdi,4), %r9d
cmpl %r8d, %r9d
cmovbl %r9d, %r8d
movl %r8d, (%rcx,%rdi,4)
incq %rdi
cmpq $1000, %rdi # imm = 0x3E8
jne .LBB7_5
# %bb.6: # in Loop: Header=BB7_4 Depth=2
incq %rdx
addq $4000, %rcx # imm = 0xFA0
cmpq $1000, %rdx # imm = 0x3E8
jne .LBB7_4
# %bb.7: # in Loop: Header=BB7_3 Depth=1
incq %r12
addq $4000, %rax # imm = 0xFA0
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB7_3
# %bb.8: # %_Z16Floyd_sequentialPjm.exit
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq (%rsp), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
movsd %xmm0, 40(%rsp) # 8-byte Spill
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r12
movl $4000000, %edx # imm = 0x3D0900
movq %rax, %rdi
movq %rbx, %rsi
callq memcpy@PLT
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
testl %eax, %eax
jne .LBB7_9
# %bb.11:
movq 24(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r12, 72(%rsp) # 8-byte Spill
movq %r12, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_12
# %bb.13:
xorps %xmm0, %xmm0
cvtsi2sd %r15, %xmm0
movsd 48(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
addsd %xmm0, %xmm1
movsd %xmm1, 48(%rsp) # 8-byte Spill
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
mulsd .LCPI7_0(%rip), %xmm0
addsd 32(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 40(%rsp) # 8-byte Spill
movq %rsp, %r15
movq %r15, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rax
movq %rax, 64(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI7_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movabsq $536870912125, %r13 # imm = 0x7D0000007D
movabsq $34359738376, %rbp # imm = 0x800000008
xorl %r12d, %r12d
jmp .LBB7_14
.p2align 4, 0x90
.LBB7_16: # in Loop: Header=BB7_14 Depth=1
callq hipGetLastError
testl %eax, %eax
jne .LBB7_17
.LBB7_18: # in Loop: Header=BB7_14 Depth=1
incl %r12d
cmpl $1000, %r12d # imm = 0x3E8
je .LBB7_19
.LBB7_14: # =>This Inner Loop Header: Depth=1
movq %r13, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB7_16
# %bb.15: # in Loop: Header=BB7_14 Depth=1
movq 24(%rsp), %rax
movq %rax, 128(%rsp)
movl $1000, 60(%rsp) # imm = 0x3E8
movl %r12d, 56(%rsp)
leaq 128(%rsp), %rax
movq %rax, (%rsp)
leaq 60(%rsp), %rax
movq %rax, 8(%rsp)
leaq 56(%rsp), %rax
movq %rax, 16(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
movl $_Z9gpu_FloydPjii, %edi
movq %r15, %r9
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB7_16
.LBB7_17: # in Loop: Header=BB7_14 Depth=1
movq stderr(%rip), %r15
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %r15, %rdi
movq %rsp, %r15
movl $155, %ecx
movq %rax, %r8
xorl %eax, %eax
callq fprintf
jmp .LBB7_18
.LBB7_19:
xorl %r12d, %r12d
movq %rsp, %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %r15
movq 8(%rsp), %r13
movq 24(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 72(%rsp), %rbp # 8-byte Reload
movq %rbp, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB7_20
# %bb.21:
xorps %xmm0, %xmm0
cvtsi2sdq 64(%rsp), %xmm0 # 8-byte Folded Reload
cvtsi2sd %r13, %xmm2
mulsd .LCPI7_0(%rip), %xmm2
movsd 32(%rsp), %xmm3 # 8-byte Reload
# xmm3 = mem[0],zero
addsd %xmm0, %xmm3
xorps %xmm1, %xmm1
cvtsi2sd %r15, %xmm1
addsd %xmm2, %xmm1
subsd %xmm3, %xmm1
movsd 40(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 48(%rsp), %xmm0 # 8-byte Folded Reload
movapd %xmm0, %xmm2
divsd %xmm1, %xmm2
movl $.L.str.5, %edi
movb $3, %al
callq printf
movl (%rbp), %edx
movl (%r14), %r8d
movl $0, %r15d
cmpl %r8d, %edx
jne .LBB7_26
# %bb.22: # %.lr.ph.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB7_23: # %.lr.ph
# =>This Inner Loop Header: Depth=1
cmpq $999999, %r12 # imm = 0xF423F
je .LBB7_27
# %bb.24: # %.lr.ph.i79
# in Loop: Header=BB7_23 Depth=1
movl 4(%rbp,%r12,4), %edx
movl 4(%r14,%r12,4), %r8d
incq %r12
cmpl %r8d, %edx
je .LBB7_23
# %bb.25: # %.lr.ph.i79._crit_edge.loopexit
leaq -1(%r12), %rax
cmpq $999999, %rax # imm = 0xF423F
setae %r15b
.LBB7_26: # %.lr.ph.i79._crit_edge
movl $.L.str.2, %edi
movl %r12d, %esi
movl %r12d, %ecx
xorl %eax, %eax
callq printf
jmp .LBB7_28
.LBB7_27: # %_Z8CmpArrayPKjS0_m.exit.loopexit
setae %r15b
.LBB7_28: # %_Z8CmpArrayPKjS0_m.exit
movl $.Lstr.2, %eax
movl $.Lstr.1, %edi
testb %r15b, %r15b
cmovneq %rax, %rdi
callq puts@PLT
movq %r14, %rdi
callq free
movq %rbx, %rdi
callq free
movq %rbp, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB7_9:
.cfi_def_cfa_offset 192
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $142, %ecx
jmp .LBB7_10
.LBB7_12:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $144, %ecx
jmp .LBB7_10
.LBB7_20:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
movl $.L.str.4, %edx
movq %rbx, %rdi
movl $159, %ecx
.LBB7_10:
movq %rax, %r8
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end7:
.size main, .Lfunc_end7-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB8_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB8_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9gpu_FloydPjii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end8:
.size __hip_module_ctor, .Lfunc_end8-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB9_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB9_2:
retq
.Lfunc_end9:
.size __hip_module_dtor, .Lfunc_end9-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9gpu_FloydPjii,@object # @_Z9gpu_FloydPjii
.section .rodata,"a",@progbits
.globl _Z9gpu_FloydPjii
.p2align 3, 0x0
_Z9gpu_FloydPjii:
.quad _Z24__device_stub__gpu_FloydPjii
.size _Z9gpu_FloydPjii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "mat[%d] = %d, "
.size .L.str, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ERROR: l[%d] = %d, r[%d] = %d\n"
.size .L.str.2, 31
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Cuda error in file '%s' in line %i : %s.\n"
.size .L.str.3, 42
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/yifanliuu/Paralleled-All-pairs-shortest-paths-blocked-Floyd-algorithm/master/src/simple.hip"
.size .L.str.4, 149
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "sequential time use: %f, cuda time use: %f\nspeedup-rate: %f\n"
.size .L.str.5, 61
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9gpu_FloydPjii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "done"
.size .Lstr, 5
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "The matrix do not match."
.size .Lstr.1, 25
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "The matrix matches."
.size .Lstr.2, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__gpu_FloydPjii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9gpu_FloydPjii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
struct MyStruct
{
int a;
int b;
int c;
};
int main(void)
{
int *ptr;
char *ptr1;
int **ptr2;
int(*ptr3)[3];
int *(*ptr4)[4];
int temp = sizeof(*ptr);
printf("result is :%d\n",temp);
int array[20];
int *ptr5 = array;
for (int i = 0; i < 20; i++)
{
array[i] = i;
}
for (int i = 0; i < 20; i++)
{
(*ptr5)++;
ptr5++;
}
for (int i = 0; i < 20; i++)
{
printf("number %d: value %d\n", i, array[i]);
}
int a1 = 12;
int b1;
int *p1;
int **ptr6;
p1 = &a1;
*p1 = 24;
ptr6 = &p1;
*ptr6 = &b1;
**ptr6 = 34;
printf("a1 is %d,b1 is %d,*p1 is %d,**ptr6 is %d\n", a1, b1, *p1, **ptr6);
char *str1[3] = {
"Hello,this is a sample!\n",
"Hi,good morning\n",
"Hello world\n"
};
char s[80];
strcpy(s, str1[0]);
printf(s);
cout << **str1 << endl;
strcpy(s, str1[1]);
printf(s);
strcpy(s, str1[2]);
printf(s);
MyStruct ss = { 20,30,40 };
MyStruct *ptr7 = &ss;
int *pstr = (int*)&ss;
cout << sizeof(ptr7) << " and " << sizeof(pstr) << endl;
cout << ptr7->a << " " << ptr7->b << " " << ptr7->c << endl;
cout << *pstr << " " << *(pstr + 1) << " " << *(pstr + 2) << endl;
int fun1(char*, int);
int(*pfun1)(char*, int);
pfun1 = fun1;
int res = (*pfun1)("abcdefg", 7);
}
int fun1(char* x1, int x2){
cout << x1 << " " << x2 << endl;
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
struct MyStruct
{
int a;
int b;
int c;
};
int main(void)
{
int *ptr;
char *ptr1;
int **ptr2;
int(*ptr3)[3];
int *(*ptr4)[4];
int temp = sizeof(*ptr);
printf("result is :%d\n",temp);
int array[20];
int *ptr5 = array;
for (int i = 0; i < 20; i++)
{
array[i] = i;
}
for (int i = 0; i < 20; i++)
{
(*ptr5)++;
ptr5++;
}
for (int i = 0; i < 20; i++)
{
printf("number %d: value %d\n", i, array[i]);
}
int a1 = 12;
int b1;
int *p1;
int **ptr6;
p1 = &a1;
*p1 = 24;
ptr6 = &p1;
*ptr6 = &b1;
**ptr6 = 34;
printf("a1 is %d,b1 is %d,*p1 is %d,**ptr6 is %d\n", a1, b1, *p1, **ptr6);
char *str1[3] = {
"Hello,this is a sample!\n",
"Hi,good morning\n",
"Hello world\n"
};
char s[80];
strcpy(s, str1[0]);
printf(s);
cout << **str1 << endl;
strcpy(s, str1[1]);
printf(s);
strcpy(s, str1[2]);
printf(s);
MyStruct ss = { 20,30,40 };
MyStruct *ptr7 = &ss;
int *pstr = (int*)&ss;
cout << sizeof(ptr7) << " and " << sizeof(pstr) << endl;
cout << ptr7->a << " " << ptr7->b << " " << ptr7->c << endl;
cout << *pstr << " " << *(pstr + 1) << " " << *(pstr + 2) << endl;
int fun1(char*, int);
int(*pfun1)(char*, int);
pfun1 = fun1;
int res = (*pfun1)("abcdefg", 7);
}
int fun1(char* x1, int x2){
cout << x1 << " " << x2 << endl;
return 0;
} | .file "tmpxft_0012394d_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z4fun1Pci
.type _Z4fun1Pci, @function
_Z4fun1Pci:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %esi, %ebp
testq %rdi, %rdi
je .L10
movq %rdi, %rbx
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L5:
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L11
cmpb $0, 56(%rbp)
je .L7
movzbl 67(%rbp), %esi
.L8:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L5
.L11:
call _ZSt16__throw_bad_castv@PLT
.L7:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.cfi_endproc
.LFE3670:
.size _Z4fun1Pci, .-_Z4fun1Pci
.section .rodata.str1.1
.LC1:
.string "result is :%d\n"
.LC2:
.string "number %d: value %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "a1 is %d,b1 is %d,*p1 is %d,**ptr6 is %d\n"
.section .rodata.str1.1
.LC4:
.string " and "
.LC5:
.string "abcdefg"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $184, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl $4, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %eax
.L13:
movl %eax, (%rsp,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L13
movq %rsp, %rax
leaq 80(%rsp), %rdx
.L14:
addl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L14
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L15:
movl (%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $20, %rbx
jne .L15
movl $34, %r9d
movl $34, %r8d
movl $34, %ecx
movl $24, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rbx
movabsq $7526689734314976584, %rax
movabsq $2333181762011689833, %rdx
movq %rax, 80(%rsp)
movq %rdx, 88(%rsp)
movabsq $8295737305619570803, %rax
movabsq $2851469261827425, %rdx
movq %rax, 89(%rsp)
movq %rdx, 97(%rsp)
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $72, %esi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movabsq $2334113031147776328, %rax
movabsq $749689262084091757, %rdx
movq %rax, 80(%rsp)
movq %rdx, 88(%rsp)
movb $0, 96(%rsp)
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movabsq $8031924123371070792, %rax
movq %rax, 80(%rsp)
movabsq $2925166706259744, %rax
movq %rax, 85(%rsp)
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, %esi
movq %rbp, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $20, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $30, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $40, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $20, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $30, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $40, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $7, %esi
leaq .LC5(%rip), %rdi
call _Z4fun1Pci
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <iostream>
using namespace std;
struct MyStruct
{
int a;
int b;
int c;
};
int main(void)
{
int *ptr;
char *ptr1;
int **ptr2;
int(*ptr3)[3];
int *(*ptr4)[4];
int temp = sizeof(*ptr);
printf("result is :%d\n",temp);
int array[20];
int *ptr5 = array;
for (int i = 0; i < 20; i++)
{
array[i] = i;
}
for (int i = 0; i < 20; i++)
{
(*ptr5)++;
ptr5++;
}
for (int i = 0; i < 20; i++)
{
printf("number %d: value %d\n", i, array[i]);
}
int a1 = 12;
int b1;
int *p1;
int **ptr6;
p1 = &a1;
*p1 = 24;
ptr6 = &p1;
*ptr6 = &b1;
**ptr6 = 34;
printf("a1 is %d,b1 is %d,*p1 is %d,**ptr6 is %d\n", a1, b1, *p1, **ptr6);
char *str1[3] = {
"Hello,this is a sample!\n",
"Hi,good morning\n",
"Hello world\n"
};
char s[80];
strcpy(s, str1[0]);
printf(s);
cout << **str1 << endl;
strcpy(s, str1[1]);
printf(s);
strcpy(s, str1[2]);
printf(s);
MyStruct ss = { 20,30,40 };
MyStruct *ptr7 = &ss;
int *pstr = (int*)&ss;
cout << sizeof(ptr7) << " and " << sizeof(pstr) << endl;
cout << ptr7->a << " " << ptr7->b << " " << ptr7->c << endl;
cout << *pstr << " " << *(pstr + 1) << " " << *(pstr + 2) << endl;
int fun1(char*, int);
int(*pfun1)(char*, int);
pfun1 = fun1;
int res = (*pfun1)("abcdefg", 7);
}
int fun1(char* x1, int x2){
cout << x1 << " " << x2 << endl;
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
struct MyStruct
{
int a;
int b;
int c;
};
int main(void)
{
int *ptr;
char *ptr1;
int **ptr2;
int(*ptr3)[3];
int *(*ptr4)[4];
int temp = sizeof(*ptr);
printf("result is :%d\n",temp);
int array[20];
int *ptr5 = array;
for (int i = 0; i < 20; i++)
{
array[i] = i;
}
for (int i = 0; i < 20; i++)
{
(*ptr5)++;
ptr5++;
}
for (int i = 0; i < 20; i++)
{
printf("number %d: value %d\n", i, array[i]);
}
int a1 = 12;
int b1;
int *p1;
int **ptr6;
p1 = &a1;
*p1 = 24;
ptr6 = &p1;
*ptr6 = &b1;
**ptr6 = 34;
printf("a1 is %d,b1 is %d,*p1 is %d,**ptr6 is %d\n", a1, b1, *p1, **ptr6);
char *str1[3] = {
"Hello,this is a sample!\n",
"Hi,good morning\n",
"Hello world\n"
};
char s[80];
strcpy(s, str1[0]);
printf(s);
cout << **str1 << endl;
strcpy(s, str1[1]);
printf(s);
strcpy(s, str1[2]);
printf(s);
MyStruct ss = { 20,30,40 };
MyStruct *ptr7 = &ss;
int *pstr = (int*)&ss;
cout << sizeof(ptr7) << " and " << sizeof(pstr) << endl;
cout << ptr7->a << " " << ptr7->b << " " << ptr7->c << endl;
cout << *pstr << " " << *(pstr + 1) << " " << *(pstr + 2) << endl;
int fun1(char*, int);
int(*pfun1)(char*, int);
pfun1 = fun1;
int res = (*pfun1)("abcdefg", 7);
}
int fun1(char* x1, int x2){
cout << x1 << " " << x2 << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
struct MyStruct
{
int a;
int b;
int c;
};
int main(void)
{
int *ptr;
char *ptr1;
int **ptr2;
int(*ptr3)[3];
int *(*ptr4)[4];
int temp = sizeof(*ptr);
printf("result is :%d\n",temp);
int array[20];
int *ptr5 = array;
for (int i = 0; i < 20; i++)
{
array[i] = i;
}
for (int i = 0; i < 20; i++)
{
(*ptr5)++;
ptr5++;
}
for (int i = 0; i < 20; i++)
{
printf("number %d: value %d\n", i, array[i]);
}
int a1 = 12;
int b1;
int *p1;
int **ptr6;
p1 = &a1;
*p1 = 24;
ptr6 = &p1;
*ptr6 = &b1;
**ptr6 = 34;
printf("a1 is %d,b1 is %d,*p1 is %d,**ptr6 is %d\n", a1, b1, *p1, **ptr6);
char *str1[3] = {
"Hello,this is a sample!\n",
"Hi,good morning\n",
"Hello world\n"
};
char s[80];
strcpy(s, str1[0]);
printf(s);
cout << **str1 << endl;
strcpy(s, str1[1]);
printf(s);
strcpy(s, str1[2]);
printf(s);
MyStruct ss = { 20,30,40 };
MyStruct *ptr7 = &ss;
int *pstr = (int*)&ss;
cout << sizeof(ptr7) << " and " << sizeof(pstr) << endl;
cout << ptr7->a << " " << ptr7->b << " " << ptr7->c << endl;
cout << *pstr << " " << *(pstr + 1) << " " << *(pstr + 2) << endl;
int fun1(char*, int);
int(*pfun1)(char*, int);
pfun1 = fun1;
int res = (*pfun1)("abcdefg", 7);
}
int fun1(char* x1, int x2){
cout << x1 << " " << x2 << endl;
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <iostream>
using namespace std;
struct MyStruct
{
int a;
int b;
int c;
};
int main(void)
{
int *ptr;
char *ptr1;
int **ptr2;
int(*ptr3)[3];
int *(*ptr4)[4];
int temp = sizeof(*ptr);
printf("result is :%d\n",temp);
int array[20];
int *ptr5 = array;
for (int i = 0; i < 20; i++)
{
array[i] = i;
}
for (int i = 0; i < 20; i++)
{
(*ptr5)++;
ptr5++;
}
for (int i = 0; i < 20; i++)
{
printf("number %d: value %d\n", i, array[i]);
}
int a1 = 12;
int b1;
int *p1;
int **ptr6;
p1 = &a1;
*p1 = 24;
ptr6 = &p1;
*ptr6 = &b1;
**ptr6 = 34;
printf("a1 is %d,b1 is %d,*p1 is %d,**ptr6 is %d\n", a1, b1, *p1, **ptr6);
char *str1[3] = {
"Hello,this is a sample!\n",
"Hi,good morning\n",
"Hello world\n"
};
char s[80];
strcpy(s, str1[0]);
printf(s);
cout << **str1 << endl;
strcpy(s, str1[1]);
printf(s);
strcpy(s, str1[2]);
printf(s);
MyStruct ss = { 20,30,40 };
MyStruct *ptr7 = &ss;
int *pstr = (int*)&ss;
cout << sizeof(ptr7) << " and " << sizeof(pstr) << endl;
cout << ptr7->a << " " << ptr7->b << " " << ptr7->c << endl;
cout << *pstr << " " << *(pstr + 1) << " " << *(pstr + 2) << endl;
int fun1(char*, int);
int(*pfun1)(char*, int);
pfun1 = fun1;
int res = (*pfun1)("abcdefg", 7);
}
int fun1(char* x1, int x2){
cout << x1 << " " << x2 << endl;
return 0;
} | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $184, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %ebx, %ebx
movl $.L.str, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 96(%rsp,%rbx,4)
incq %rbx
cmpq $20, %rbx
jne .LBB0_1
# %bb.2: # %.preheader51.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.preheader51
# =>This Inner Loop Header: Depth=1
incl 96(%rsp,%rax,4)
incq %rax
cmpl $20, %eax
jne .LBB0_3
# %bb.4: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %edx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $20, %rbx
jne .LBB0_5
# %bb.6:
movl $.L.str.2, %edi
movl $24, %esi
movl $34, %edx
movl $34, %ecx
movl $34, %r8d
xorl %eax, %eax
callq printf
movups .L.str.3+9(%rip), %xmm0
movups %xmm0, 25(%rsp)
movups .L.str.3(%rip), %xmm0
movaps %xmm0, 16(%rsp)
leaq 16(%rsp), %rdi
xorl %eax, %eax
callq printf
movb $72, 15(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB0_8
# %bb.7:
leaq 15(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
jmp .LBB0_9
.LBB0_8:
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $72, %esi
callq _ZNSo3putEc
.LBB0_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_26
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_12
# %bb.11:
movzbl 67(%r14), %eax
jmp .LBB0_13
.LBB0_12:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movups .L.str.4(%rip), %xmm0
movaps %xmm0, 16(%rsp)
movb $0, 32(%rsp)
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %eax, %eax
callq printf
movabsq $8031924123371070792, %rax # imm = 0x6F77206F6C6C6548
movq %rax, 16(%rsp)
movabsq $2925166706259744, %rax # imm = 0xA646C726F7720
movq %rax, 21(%rsp)
movq %rbx, %rdi
xorl %eax, %eax
callq printf
movl $_ZSt4cout, %edi
movl $8, %esi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.6, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $8, %esi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_26
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
je .LBB0_16
# %bb.15:
movzbl 67(%rbx), %ecx
jmp .LBB0_17
.LBB0_16:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $20, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $30, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $40, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_26
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%rbx)
je .LBB0_20
# %bb.19:
movzbl 67(%rbx), %ecx
jmp .LBB0_21
.LBB0_20:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $20, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $30, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $40, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_26
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%rbx)
je .LBB0_24
# %bb.23:
movzbl 67(%rbx), %ecx
jmp .LBB0_25
.LBB0_24:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.8, %edi
movl $7, %esi
callq _Z4fun1Pci
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_26:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z4fun1Pci # -- Begin function _Z4fun1Pci
.p2align 4, 0x90
.type _Z4fun1Pci,@function
_Z4fun1Pci: # @_Z4fun1Pci
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
testq %rdi, %rdi
je .LBB1_1
# %bb.2:
movq %rdi, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_3
.LBB1_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_6
# %bb.5:
movzbl 67(%rbx), %ecx
jmp .LBB1_7
.LBB1_6:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z4fun1Pci, .Lfunc_end1-_Z4fun1Pci
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "result is :%d\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "number %d: value %d\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "a1 is %d,b1 is %d,*p1 is %d,**ptr6 is %d\n"
.size .L.str.2, 42
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Hello,this is a sample!\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Hi,good morning\n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Hello world\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " and "
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " "
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "abcdefg"
.size .L.str.8, 8
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012394d_00000000-6_kernel.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " "
.text
.globl _Z4fun1Pci
.type _Z4fun1Pci, @function
_Z4fun1Pci:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %esi, %ebp
testq %rdi, %rdi
je .L10
movq %rdi, %rbx
call strlen@PLT
movq %rax, %rdx
movq %rbx, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L5:
movl $1, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebp, %esi
movq %rbx, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbx
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbp
testq %rbp, %rbp
je .L11
cmpb $0, 56(%rbp)
je .L7
movzbl 67(%rbp), %esi
.L8:
movsbl %sil, %esi
movq %rbx, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %eax
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
leaq _ZSt4cout(%rip), %rdi
movq _ZSt4cout(%rip), %rax
addq -24(%rax), %rdi
movl 32(%rdi), %esi
orl $1, %esi
call _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate@PLT
jmp .L5
.L11:
call _ZSt16__throw_bad_castv@PLT
.L7:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L8
.cfi_endproc
.LFE3670:
.size _Z4fun1Pci, .-_Z4fun1Pci
.section .rodata.str1.1
.LC1:
.string "result is :%d\n"
.LC2:
.string "number %d: value %d\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "a1 is %d,b1 is %d,*p1 is %d,**ptr6 is %d\n"
.section .rodata.str1.1
.LC4:
.string " and "
.LC5:
.string "abcdefg"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $184, %rsp
.cfi_def_cfa_offset 208
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movl $4, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %eax
.L13:
movl %eax, (%rsp,%rax,4)
addq $1, %rax
cmpq $20, %rax
jne .L13
movq %rsp, %rax
leaq 80(%rsp), %rdx
.L14:
addl $1, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L14
movl $0, %ebx
leaq .LC2(%rip), %rbp
.L15:
movl (%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $20, %rbx
jne .L15
movl $34, %r9d
movl $34, %r8d
movl $34, %ecx
movl $24, %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 80(%rsp), %rbx
movabsq $7526689734314976584, %rax
movabsq $2333181762011689833, %rdx
movq %rax, 80(%rsp)
movq %rdx, 88(%rsp)
movabsq $8295737305619570803, %rax
movabsq $2851469261827425, %rdx
movq %rax, 89(%rsp)
movq %rdx, 97(%rsp)
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $72, %esi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movabsq $2334113031147776328, %rax
movabsq $749689262084091757, %rdx
movq %rax, 80(%rsp)
movq %rdx, 88(%rsp)
movb $0, 96(%rsp)
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movabsq $8031924123371070792, %rax
movq %rax, 80(%rsp)
movabsq $2925166706259744, %rax
movq %rax, 85(%rsp)
movq %rbx, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $8, %esi
movq %rbp, %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $8, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $20, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
leaq .LC0(%rip), %rbx
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $30, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $40, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $20, %esi
movq %rbp, %rdi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $30, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
movq %rbx, %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $40, %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $7, %esi
leaq .LC5(%rip), %rdi
call _Z4fun1Pci
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L21
movl $0, %eax
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $184, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
xorl %ebx, %ebx
movl $.L.str, %edi
movl $4, %esi
xorl %eax, %eax
callq printf
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 96(%rsp,%rbx,4)
incq %rbx
cmpq $20, %rbx
jne .LBB0_1
# %bb.2: # %.preheader51.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_3: # %.preheader51
# =>This Inner Loop Header: Depth=1
incl 96(%rsp,%rax,4)
incq %rax
cmpl $20, %eax
jne .LBB0_3
# %bb.4: # %.preheader.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # %.preheader
# =>This Inner Loop Header: Depth=1
movl 96(%rsp,%rbx,4), %edx
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $20, %rbx
jne .LBB0_5
# %bb.6:
movl $.L.str.2, %edi
movl $24, %esi
movl $34, %edx
movl $34, %ecx
movl $34, %r8d
xorl %eax, %eax
callq printf
movups .L.str.3+9(%rip), %xmm0
movups %xmm0, 25(%rsp)
movups .L.str.3(%rip), %xmm0
movaps %xmm0, 16(%rsp)
leaq 16(%rsp), %rdi
xorl %eax, %eax
callq printf
movb $72, 15(%rsp)
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
cmpq $0, _ZSt4cout+16(%rax)
je .LBB0_8
# %bb.7:
leaq 15(%rsp), %rsi
movl $_ZSt4cout, %edi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rax, %rbx
jmp .LBB0_9
.LBB0_8:
movl $_ZSt4cout, %ebx
movl $_ZSt4cout, %edi
movl $72, %esi
callq _ZNSo3putEc
.LBB0_9: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_c.exit
movq (%rbx), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %r14
testq %r14, %r14
je .LBB0_26
# %bb.10: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB0_12
# %bb.11:
movzbl 67(%r14), %eax
jmp .LBB0_13
.LBB0_12:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_13: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %rbx, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movups .L.str.4(%rip), %xmm0
movaps %xmm0, 16(%rsp)
movb $0, 32(%rsp)
leaq 16(%rsp), %rbx
movq %rbx, %rdi
xorl %eax, %eax
callq printf
movabsq $8031924123371070792, %rax # imm = 0x6F77206F6C6C6548
movq %rax, 16(%rsp)
movabsq $2925166706259744, %rax # imm = 0xA646C726F7720
movq %rax, 21(%rsp)
movq %rbx, %rdi
xorl %eax, %eax
callq printf
movl $_ZSt4cout, %edi
movl $8, %esi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.6, %esi
movl $5, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $8, %esi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_26
# %bb.14: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i37
cmpb $0, 56(%rbx)
je .LBB0_16
# %bb.15:
movzbl 67(%rbx), %ecx
jmp .LBB0_17
.LBB0_16:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_17: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit40
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $20, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $30, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $40, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_26
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i42
cmpb $0, 56(%rbx)
je .LBB0_20
# %bb.19:
movzbl 67(%rbx), %ecx
jmp .LBB0_21
.LBB0_20:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_21: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit45
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $20, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $30, %esi
callq _ZNSolsEi
movq %rax, %rbx
movl $.L.str.7, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
movl $40, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_26
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i47
cmpb $0, 56(%rbx)
je .LBB0_24
# %bb.23:
movzbl 67(%rbx), %ecx
jmp .LBB0_25
.LBB0_24:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit50
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $.L.str.8, %edi
movl $7, %esi
callq _Z4fun1Pci
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_26:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z4fun1Pci # -- Begin function _Z4fun1Pci
.p2align 4, 0x90
.type _Z4fun1Pci,@function
_Z4fun1Pci: # @_Z4fun1Pci
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
testq %rdi, %rdi
je .LBB1_1
# %bb.2:
movq %rdi, %r14
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_3
.LBB1_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebx, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_8
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_6
# %bb.5:
movzbl 67(%rbx), %ecx
jmp .LBB1_7
.LBB1_6:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_8:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z4fun1Pci, .Lfunc_end1-_Z4fun1Pci
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "result is :%d\n"
.size .L.str, 15
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "number %d: value %d\n"
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "a1 is %d,b1 is %d,*p1 is %d,**ptr6 is %d\n"
.size .L.str.2, 42
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Hello,this is a sample!\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Hi,good morning\n"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Hello world\n"
.size .L.str.5, 13
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz " and "
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz " "
.size .L.str.7, 2
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "abcdefg"
.size .L.str.8, 8
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
__global__ void matrixMul(int *a, int *b, int *c, int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int temp_sum = 0;
if((row < n) && (col < n)){
for (int k = 0; k < n; k++){
temp_sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = temp_sum;
}
}
void matrix_init(int *a, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
a[i * n + j] = rand() % 100;
}
}
}
void check_answer(int *a, int *b, int *c, int n){
int *verify_c;
verify_c = (int*)malloc(n*n*sizeof(int));
int temp_sum;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
temp_sum = 0;
for (int k = 0; k < n; k++){
temp_sum += a[i * n + k] * b[k * n + j];
}
verify_c[i * n + j] = temp_sum;
}
}
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
assert(c[i * n + j] == verify_c[i * n + j]);
}
}
}
int main(){
int n = 1 << 10;
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
matrix_init(h_a, n);
matrix_init(h_b, n);
cudaMemcpy(d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, bytes, cudaMemcpyHostToDevice);
int BLOCK_SIZE = 16;
int GRID_SIZE = n / BLOCK_SIZE;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
matrixMul<<<grid, threads>>>(d_a, d_b, d_c, n);
cudaMemcpy(h_c, d_c, bytes, cudaMemcpyDeviceToHost);
check_answer(h_a, h_b, h_c, n);
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf("Completed.\n");
return 0;
} | code for sm_80
Function : _Z9matrixMulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
__global__ void matrixMul(int *a, int *b, int *c, int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int temp_sum = 0;
if((row < n) && (col < n)){
for (int k = 0; k < n; k++){
temp_sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = temp_sum;
}
}
void matrix_init(int *a, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
a[i * n + j] = rand() % 100;
}
}
}
void check_answer(int *a, int *b, int *c, int n){
int *verify_c;
verify_c = (int*)malloc(n*n*sizeof(int));
int temp_sum;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
temp_sum = 0;
for (int k = 0; k < n; k++){
temp_sum += a[i * n + k] * b[k * n + j];
}
verify_c[i * n + j] = temp_sum;
}
}
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
assert(c[i * n + j] == verify_c[i * n + j]);
}
}
}
int main(){
int n = 1 << 10;
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
matrix_init(h_a, n);
matrix_init(h_b, n);
cudaMemcpy(d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, bytes, cudaMemcpyHostToDevice);
int BLOCK_SIZE = 16;
int GRID_SIZE = n / BLOCK_SIZE;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
matrixMul<<<grid, threads>>>(d_a, d_b, d_c, n);
cudaMemcpy(h_c, d_c, bytes, cudaMemcpyDeviceToHost);
check_answer(h_a, h_b, h_c, n);
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf("Completed.\n");
return 0;
} | .file "tmpxft_00130063_00000000-6_matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11matrix_initPii
.type _Z11matrix_initPii, @function
_Z11matrix_initPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L9
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r14d
movslq %esi, %r13
leaq 0(,%r13,4), %r15
leaq (%rdi,%r15), %rbp
negq %r13
salq $2, %r13
movl $0, %r12d
.L5:
leaq 0(%rbp,%r13), %rbx
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
addl $1, %r12d
addq %r15, %rbp
cmpl %r12d, %r14d
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z11matrix_initPii, .-_Z11matrix_initPii
.globl _Z12check_answerPiS_S_i
.type _Z12check_answerPiS_S_i, @function
_Z12check_answerPiS_S_i:
.LFB2058:
.cfi_startproc
endbr64
movl $0, %edi
movl $0, %r8d
testl %ecx, %ecx
jg .L13
ret
.L16:
leal 1(%rdi), %eax
cmpl %edx, %edi
je .L21
movl %eax, %edi
.L13:
movl %r8d, %esi
.L18:
movl $0, %eax
.L15:
movl %eax, %edx
addl $1, %eax
cmpl %eax, %ecx
jne .L15
leal 1(%rsi), %eax
cmpl %edx, %esi
je .L16
movl %eax, %esi
jmp .L18
.L21:
movl $0, %esi
.L17:
movl $0, %eax
.L19:
movl %eax, %ecx
addl $1, %eax
cmpl %ecx, %edx
jne .L19
leal 1(%rsi), %eax
cmpl %esi, %edx
je .L12
movl %eax, %esi
jmp .L17
.L12:
ret
.cfi_endproc
.LFE2058:
.size _Z12check_answerPiS_S_i, .-_Z12check_answerPiS_S_i
.globl _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixMulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.globl _Z9matrixMulPiS_S_i
.type _Z9matrixMulPiS_S_i, @function
_Z9matrixMulPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9matrixMulPiS_S_i, .-_Z9matrixMulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Completed.\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1024, %esi
movq %rbp, %rdi
call _Z11matrix_initPii
movl $1024, %esi
movq %rbx, %rdi
call _Z11matrix_initPii
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 32(%rsp)
movl $64, 36(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L34:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
jmp .L34
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9matrixMulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include <device_launch_parameters.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
__global__ void matrixMul(int *a, int *b, int *c, int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int temp_sum = 0;
if((row < n) && (col < n)){
for (int k = 0; k < n; k++){
temp_sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = temp_sum;
}
}
void matrix_init(int *a, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
a[i * n + j] = rand() % 100;
}
}
}
void check_answer(int *a, int *b, int *c, int n){
int *verify_c;
verify_c = (int*)malloc(n*n*sizeof(int));
int temp_sum;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
temp_sum = 0;
for (int k = 0; k < n; k++){
temp_sum += a[i * n + k] * b[k * n + j];
}
verify_c[i * n + j] = temp_sum;
}
}
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
assert(c[i * n + j] == verify_c[i * n + j]);
}
}
}
int main(){
int n = 1 << 10;
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
int *d_a, *d_b, *d_c;
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
matrix_init(h_a, n);
matrix_init(h_b, n);
cudaMemcpy(d_a, h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, bytes, cudaMemcpyHostToDevice);
int BLOCK_SIZE = 16;
int GRID_SIZE = n / BLOCK_SIZE;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
matrixMul<<<grid, threads>>>(d_a, d_b, d_c, n);
cudaMemcpy(h_c, d_c, bytes, cudaMemcpyDeviceToHost);
check_answer(h_a, h_b, h_c, n);
free(h_a);
free(h_b);
free(h_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf("Completed.\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
__global__ void matrixMul(int *a, int *b, int *c, int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int temp_sum = 0;
if((row < n) && (col < n)){
for (int k = 0; k < n; k++){
temp_sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = temp_sum;
}
}
void matrix_init(int *a, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
a[i * n + j] = rand() % 100;
}
}
}
void check_answer(int *a, int *b, int *c, int n){
int *verify_c;
verify_c = (int*)malloc(n*n*sizeof(int));
int temp_sum;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
temp_sum = 0;
for (int k = 0; k < n; k++){
temp_sum += a[i * n + k] * b[k * n + j];
}
verify_c[i * n + j] = temp_sum;
}
}
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
assert(c[i * n + j] == verify_c[i * n + j]);
}
}
}
int main(){
int n = 1 << 10;
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
matrix_init(h_a, n);
matrix_init(h_b, n);
hipMemcpy(d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, bytes, hipMemcpyHostToDevice);
int BLOCK_SIZE = 16;
int GRID_SIZE = n / BLOCK_SIZE;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
matrixMul<<<grid, threads>>>(d_a, d_b, d_c, n);
hipMemcpy(h_c, d_c, bytes, hipMemcpyDeviceToHost);
check_answer(h_a, h_b, h_c, n);
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf("Completed.\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
__global__ void matrixMul(int *a, int *b, int *c, int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int temp_sum = 0;
if((row < n) && (col < n)){
for (int k = 0; k < n; k++){
temp_sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = temp_sum;
}
}
void matrix_init(int *a, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
a[i * n + j] = rand() % 100;
}
}
}
void check_answer(int *a, int *b, int *c, int n){
int *verify_c;
verify_c = (int*)malloc(n*n*sizeof(int));
int temp_sum;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
temp_sum = 0;
for (int k = 0; k < n; k++){
temp_sum += a[i * n + k] * b[k * n + j];
}
verify_c[i * n + j] = temp_sum;
}
}
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
assert(c[i * n + j] == verify_c[i * n + j]);
}
}
}
int main(){
int n = 1 << 10;
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
matrix_init(h_a, n);
matrix_init(h_b, n);
hipMemcpy(d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, bytes, hipMemcpyHostToDevice);
int BLOCK_SIZE = 16;
int GRID_SIZE = n / BLOCK_SIZE;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
matrixMul<<<grid, threads>>>(d_a, d_b, d_c, n);
hipMemcpy(h_c, d_c, bytes, hipMemcpyDeviceToHost);
check_answer(h_a, h_b, h_c, n);
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf("Completed.\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPiS_S_i
.globl _Z9matrixMulPiS_S_i
.p2align 8
.type _Z9matrixMulPiS_S_i,@function
_Z9matrixMulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPiS_S_i, .Lfunc_end0-_Z9matrixMulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
__global__ void matrixMul(int *a, int *b, int *c, int n){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int temp_sum = 0;
if((row < n) && (col < n)){
for (int k = 0; k < n; k++){
temp_sum += a[row * n + k] * b[k * n + col];
}
c[row * n + col] = temp_sum;
}
}
void matrix_init(int *a, int n){
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
a[i * n + j] = rand() % 100;
}
}
}
void check_answer(int *a, int *b, int *c, int n){
int *verify_c;
verify_c = (int*)malloc(n*n*sizeof(int));
int temp_sum;
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
temp_sum = 0;
for (int k = 0; k < n; k++){
temp_sum += a[i * n + k] * b[k * n + j];
}
verify_c[i * n + j] = temp_sum;
}
}
for (int i = 0; i < n; i++){
for (int j = 0; j < n; j++){
assert(c[i * n + j] == verify_c[i * n + j]);
}
}
}
int main(){
int n = 1 << 10;
size_t bytes = n*n*sizeof(int);
int *h_a, *h_b, *h_c;
h_a = (int*)malloc(bytes);
h_b = (int*)malloc(bytes);
h_c = (int*)malloc(bytes);
int *d_a, *d_b, *d_c;
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
matrix_init(h_a, n);
matrix_init(h_b, n);
hipMemcpy(d_a, h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, bytes, hipMemcpyHostToDevice);
int BLOCK_SIZE = 16;
int GRID_SIZE = n / BLOCK_SIZE;
dim3 grid(GRID_SIZE, GRID_SIZE);
dim3 threads(BLOCK_SIZE, BLOCK_SIZE);
matrixMul<<<grid, threads>>>(d_a, d_b, d_c, n);
hipMemcpy(h_c, d_c, bytes, hipMemcpyDeviceToHost);
check_answer(h_a, h_b, h_c, n);
free(h_a);
free(h_b);
free(h_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf("Completed.\n");
return 0;
} | .text
.file "matrix_mult.hip"
.globl _Z24__device_stub__matrixMulPiS_S_i # -- Begin function _Z24__device_stub__matrixMulPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPiS_S_i,@function
_Z24__device_stub__matrixMulPiS_S_i: # @_Z24__device_stub__matrixMulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixMulPiS_S_i, .Lfunc_end0-_Z24__device_stub__matrixMulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z11matrix_initPii # -- Begin function _Z11matrix_initPii
.p2align 4, 0x90
.type _Z11matrix_initPii,@function
_Z11matrix_initPii: # @_Z11matrix_initPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbp,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11matrix_initPii, .Lfunc_end1-_Z11matrix_initPii
.cfi_endproc
# -- End function
.globl _Z12check_answerPiS_S_i # -- Begin function _Z12check_answerPiS_S_i
.p2align 4, 0x90
.type _Z12check_answerPiS_S_i,@function
_Z12check_answerPiS_S_i: # @_Z12check_answerPiS_S_i
.cfi_startproc
# %bb.0: # %.preheader36
retq
.Lfunc_end2:
.size _Z12check_answerPiS_S_i, .Lfunc_end2-_Z12check_answerPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %r12d, %r12d
movq %rbx, %r13
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbp,4)
incq %rbp
cmpq $1024, %rbp # imm = 0x400
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %r12
addq $4096, %r13 # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB3_1
# %bb.4: # %.preheader.i37.preheader
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB3_5: # %.preheader.i37
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbp,4)
incq %rbp
cmpq $1024, %rbp # imm = 0x400
jne .LBB3_6
# %bb.7: # %._crit_edge.i42
# in Loop: Header=BB3_5 Depth=1
incq %r12
addq $4096, %r13 # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB3_5
# %bb.8: # %_Z11matrix_initPii.exit45
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPiS_S_i,@object # @_Z9matrixMulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixMulPiS_S_i
.p2align 3, 0x0
_Z9matrixMulPiS_S_i:
.quad _Z24__device_stub__matrixMulPiS_S_i
.size _Z9matrixMulPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9matrixMulPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Completed."
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixMulPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0030*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0205 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x178], P0 ; /* 0x00005e0003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R28, -RZ, RZ, 0, 0 ; /* 0x00000000ff1c7435 */
/* 0x000fe200000001ff */
/*00d0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbf0 ; /* 0x00000af000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe40007ffe0ff */
/*0110*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*0140*/ MOV R28, RZ ; /* 0x000000ff001c7202 */
/* 0x000fd20000000f00 */
/*0150*/ @!P0 BRA 0xaf0 ; /* 0x0000099000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R6, -R5, c[0x0][0x178], RZ ; /* 0x00005e0005067a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R25, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff197435 */
/* 0x000fe200000001ff */
/*0180*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0190*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe40000000f00 */
/*01a0*/ ISETP.GT.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fcc0003f04270 */
/*01b0*/ IMAD.WIDE R24, R0, R25, c[0x0][0x168] ; /* 0x00005a0000187625 */
/* 0x000fce00078e0219 */
/*01c0*/ @!P0 BRA 0x960 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x6a0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0000a2000c1e1900 */
/*0230*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R12, R3, 0x4, R12 ; /* 0x00000004030c7825 */
/* 0x000fca00078e020c */
/*0250*/ LDG.E R27, [R12.64] ; /* 0x000000040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ IMAD.WIDE R10, R2, 0x4, R24 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0218 */
/*0270*/ LDG.E R17, [R12.64+0x4] ; /* 0x000004040c117981 */
/* 0x000ee6000c1e1900 */
/*0280*/ IMAD.WIDE R18, R2.reuse, 0x4, R10 ; /* 0x0000000402127825 */
/* 0x040fe200078e020a */
/*0290*/ LDG.E R16, [R10.64] ; /* 0x000000040a107981 */
/* 0x0002e8000c1e1900 */
/*02a0*/ LDG.E R7, [R12.64+0xc] ; /* 0x00000c040c077981 */
/* 0x000f22000c1e1900 */
/*02b0*/ IMAD.WIDE R14, R2, 0x4, R18 ; /* 0x00000004020e7825 */
/* 0x000fc600078e0212 */
/*02c0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000b26000c1e1900 */
/*02d0*/ IMAD.WIDE R20, R2.reuse, 0x4, R14 ; /* 0x0000000402147825 */
/* 0x040fe200078e020e */
/*02e0*/ LDG.E R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000128000c1e1900 */
/*02f0*/ LDG.E R9, [R12.64+0x10] ; /* 0x000010040c097981 */
/* 0x000f28000c1e1900 */
/*0300*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x020f22000c1e1900 */
/*0310*/ IMAD.WIDE R14, R2, 0x4, R20 ; /* 0x00000004020e7825 */
/* 0x001fc600078e0214 */
/*0320*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000166000c1e1900 */
/*0330*/ IMAD.WIDE R22, R2.reuse, 0x4, R14 ; /* 0x0000000402167825 */
/* 0x040fe200078e020e */
/*0340*/ LDG.E R8, [R14.64] ; /* 0x000000040e087981 */
/* 0x000168000c1e1900 */
/*0350*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x002f62000c1e1900 */
/*0360*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x000fc600078e0216 */
/*0370*/ LDG.E R10, [R22.64] ; /* 0x00000004160a7981 */
/* 0x000368000c1e1900 */
/*0380*/ LDG.E R21, [R12.64+0x18] ; /* 0x000018040c157981 */
/* 0x001f62000c1e1900 */
/*0390*/ IMAD R29, R29, R27, R28 ; /* 0x0000001b1d1d7224 */
/* 0x004fc600078e021c */
/*03a0*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x0000a2000c1e1900 */
/*03c0*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fc800078e0218 */
/*03d0*/ IMAD R29, R16, R17, R29 ; /* 0x00000011101d7224 */
/* 0x008fe400078e021d */
/*03e0*/ IMAD.WIDE R16, R2, 0x4, R14 ; /* 0x0000000402107825 */
/* 0x000fe400078e020e */
/*03f0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a4000c1e1900 */
/*0400*/ IMAD R29, R18, R19, R29 ; /* 0x00000013121d7224 */
/* 0x010fe400078e021d */
/*0410*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fe400078e0210 */
/*0420*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008a4000c1e1900 */
/*0430*/ IMAD R26, R26, R7, R29 ; /* 0x000000071a1a7224 */
/* 0x000fc400078e021d */
/*0440*/ IMAD.WIDE R22, R2.reuse, 0x4, R18 ; /* 0x0000000402167825 */
/* 0x042fe200078e0212 */
/*0450*/ LDG.E R7, [R12.64+0x20] ; /* 0x000020040c077981 */
/* 0x000ea8000c1e1900 */
/*0460*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ea2000c1e1900 */
/*0470*/ IMAD.WIDE R24, R2, 0x4, R22 ; /* 0x0000000402187825 */
/* 0x001fc600078e0216 */
/*0480*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000a2000c1e1900 */
/*0490*/ IMAD R9, R20, R9, R26 ; /* 0x0000000914097224 */
/* 0x020fc600078e021a */
/*04a0*/ LDG.E R26, [R12.64+0x28] ; /* 0x000028040c1a7981 */
/* 0x000f62000c1e1900 */
/*04b0*/ IMAD R11, R8, R11, R9 ; /* 0x0000000b080b7224 */
/* 0x000fe400078e0209 */
/*04c0*/ IMAD.WIDE R8, R2, 0x4, R24 ; /* 0x0000000402087825 */
/* 0x000fe200078e0218 */
/*04d0*/ LDG.E R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000368000c1e1900 */
/*04e0*/ LDG.E R17, [R12.64+0x2c] ; /* 0x00002c040c117981 */
/* 0x010f22000c1e1900 */
/*04f0*/ IMAD R21, R10, R21, R11 ; /* 0x000000150a157224 */
/* 0x000fc600078e020b */
/*0500*/ LDG.E R15, [R24.64] ; /* 0x00000004180f7981 */
/* 0x008722000c1e1900 */
/*0510*/ IMAD.WIDE R10, R2, 0x4, R8 ; /* 0x00000004020a7825 */
/* 0x000fc600078e0208 */
/*0520*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x001128000c1e1900 */
/*0530*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x002f28000c1e1900 */
/*0540*/ LDG.E R24, [R12.64+0x30] ; /* 0x000030040c187981 */
/* 0x008ee8000c1e1900 */
/*0550*/ LDG.E R25, [R12.64+0x38] ; /* 0x000038040c197981 */
/* 0x000ee8000c1e1900 */
/*0560*/ LDG.E R8, [R12.64+0x3c] ; /* 0x00003c040c087981 */
/* 0x001ee2000c1e1900 */
/*0570*/ IMAD R9, R28, R27, R21 ; /* 0x0000001b1c097224 */
/* 0x004fc600078e0215 */
/*0580*/ LDG.E R28, [R12.64+0x34] ; /* 0x000034040c1c7981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IMAD.WIDE R20, R2, 0x4, R10 ; /* 0x0000000402147825 */
/* 0x000fca00078e020a */
/*05a0*/ LDG.E R27, [R20.64] ; /* 0x00000004141b7981 */
/* 0x000ea2000c1e1900 */
/*05b0*/ IADD3 R6, R6, -0x10, RZ ; /* 0xfffffff006067810 */
/* 0x000fc80007ffe0ff */
/*05c0*/ ISETP.GT.AND P1, PT, R6, 0xc, PT ; /* 0x0000000c0600780c */
/* 0x000fe20003f24270 */
/*05d0*/ IMAD R7, R14, R7, R9 ; /* 0x000000070e077224 */
/* 0x000fc800078e0209 */
/*05e0*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x000fc800078e0207 */
/*05f0*/ IMAD R7, R18, R26, R7 ; /* 0x0000001a12077224 */
/* 0x020fc800078e0207 */
/*0600*/ IMAD R7, R22, R17, R7 ; /* 0x0000001116077224 */
/* 0x010fe200078e0207 */
/*0610*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0620*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0630*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0640*/ IMAD R7, R15, R24, R7 ; /* 0x000000180f077224 */
/* 0x008fc800078e0207 */
/*0650*/ IMAD R28, R19, R28, R7 ; /* 0x0000001c131c7224 */
/* 0x004fc800078e0207 */
/*0660*/ IMAD R28, R23, R25, R28 ; /* 0x00000019171c7224 */
/* 0x000fe400078e021c */
/*0670*/ IMAD.WIDE R24, R2, 0x4, R20 ; /* 0x0000000402187825 */
/* 0x000fc800078e0214 */
/*0680*/ IMAD R28, R27, R8, R28 ; /* 0x000000081b1c7224 */
/* 0x000fe200078e021c */
/*0690*/ @P1 BRA 0x210 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06a0*/ ISETP.GT.AND P1, PT, R6, 0x4, PT ; /* 0x000000040600780c */
/* 0x000fda0003f24270 */
/*06b0*/ @!P1 BRA 0x940 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06c0*/ IMAD.WIDE R16, R2, 0x4, R24 ; /* 0x0000000402107825 */
/* 0x000fe200078e0218 */
/*06d0*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E R7, [R24.64] ; /* 0x0000000418077981 */
/* 0x0000a2000c1e1900 */
/*06f0*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fc60008000f00 */
/*0700*/ IMAD.WIDE R12, R2.reuse, 0x4, R16 ; /* 0x00000004020c7825 */
/* 0x040fe200078e0210 */
/*0710*/ LDG.E R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0002e6000c1e1900 */
/*0720*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fe200078e0208 */
/*0730*/ LDG.E R23, [R12.64] ; /* 0x000000040c177981 */
/* 0x000966000c1e1900 */
/*0740*/ IMAD.WIDE R14, R2.reuse, 0x4, R12 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020c */
/*0750*/ LDG.E R20, [R8.64] ; /* 0x0000000408147981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R22, [R8.64+0x4] ; /* 0x0000040408167981 */
/* 0x000ee2000c1e1900 */
/*0770*/ IMAD.WIDE R10, R2, 0x4, R14 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020e */
/*0780*/ LDG.E R26, [R8.64+0x8] ; /* 0x00000804081a7981 */
/* 0x000f66000c1e1900 */
/*0790*/ IMAD.WIDE R16, R2.reuse, 0x4, R10 ; /* 0x0000000402107825 */
/* 0x042fe200078e020a */
/*07a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07b0*/ LDG.E R27, [R8.64+0xc] ; /* 0x00000c04081b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R18, R2, 0x4, R16 ; /* 0x0000000402127825 */
/* 0x000fc600078e0210 */
/*07d0*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R25, [R8.64+0x10] ; /* 0x0000100408197981 */
/* 0x001f62000c1e1900 */
/*07f0*/ IMAD.WIDE R12, R2, 0x4, R18 ; /* 0x00000004020c7825 */
/* 0x010fc600078e0212 */
/*0800*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R29, [R8.64+0x14] ; /* 0x00001404081d7981 */
/* 0x000f28000c1e1900 */
/*0820*/ LDG.E R24, [R18.64] ; /* 0x0000000412187981 */
/* 0x000128000c1e1900 */
/*0830*/ LDG.E R11, [R8.64+0x18] ; /* 0x00001804080b7981 */
/* 0x002f28000c1e1900 */
/*0840*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000f28000c1e1900 */
/*0850*/ LDG.E R18, [R8.64+0x1c] ; /* 0x00001c0408127981 */
/* 0x001f22000c1e1900 */
/*0860*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0880*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R6, R6, -0x8, RZ ; /* 0xfffffff806067810 */
/* 0x000fe20007ffe0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IMAD R7, R7, R20, R28 ; /* 0x0000001407077224 */
/* 0x004fc800078e021c */
/*08c0*/ IMAD R7, R21, R22, R7 ; /* 0x0000001615077224 */
/* 0x008fc800078e0207 */
/*08d0*/ IMAD R7, R23, R26, R7 ; /* 0x0000001a17077224 */
/* 0x020fc800078e0207 */
/*08e0*/ IMAD R7, R14, R27, R7 ; /* 0x0000001b0e077224 */
/* 0x000fc800078e0207 */
/*08f0*/ IMAD R7, R10, R25, R7 ; /* 0x000000190a077224 */
/* 0x000fc800078e0207 */
/*0900*/ IMAD R7, R16, R29, R7 ; /* 0x0000001d10077224 */
/* 0x010fc800078e0207 */
/*0910*/ IMAD R7, R24, R11, R7 ; /* 0x0000000b18077224 */
/* 0x000fe400078e0207 */
/*0920*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fc800078e020c */
/*0930*/ IMAD R28, R15, R18, R7 ; /* 0x000000120f1c7224 */
/* 0x000fe400078e0207 */
/*0940*/ ISETP.NE.OR P0, PT, R6, RZ, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0000705670 */
/*0950*/ @!P0 BRA 0xaf0 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0960*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*0970*/ IMAD.WIDE R14, R2, 0x4, R24 ; /* 0x00000004020e7825 */
/* 0x000fe200078e0218 */
/*0980*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0990*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ea8000c1e1900 */
/*09a0*/ IMAD.WIDE R8, R3, 0x4, R8 ; /* 0x0000000403087825 */
/* 0x000fc800078e0208 */
/*09b0*/ IMAD.WIDE R12, R2.reuse, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x040fe200078e020e */
/*09c0*/ LDG.E R7, [R8.64] ; /* 0x0000000408077981 */
/* 0x000ea8000c1e1900 */
/*09d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000ee2000c1e1900 */
/*09e0*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x000fc600078e020c */
/*09f0*/ LDG.E R16, [R8.64+0x4] ; /* 0x0000040408107981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R17, [R8.64+0x8] ; /* 0x0000080408117981 */
/* 0x000f28000c1e1900 */
/*0a20*/ LDG.E R19, [R8.64+0xc] ; /* 0x00000c0408137981 */
/* 0x000f68000c1e1900 */
/*0a30*/ LDG.E R20, [R10.64] ; /* 0x000000040a147981 */
/* 0x000f62000c1e1900 */
/*0a40*/ IADD3 R6, R6, -0x4, RZ ; /* 0xfffffffc06067810 */
/* 0x000fc80007ffe0ff */
/*0a50*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0a60*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a70*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a80*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a90*/ IMAD R7, R25, R7, R28 ; /* 0x0000000719077224 */
/* 0x004fc800078e021c */
/*0aa0*/ IMAD R7, R14, R16, R7 ; /* 0x000000100e077224 */
/* 0x008fe400078e0207 */
/*0ab0*/ IMAD.WIDE R24, R2, 0x4, R10 ; /* 0x0000000402187825 */
/* 0x000fc800078e020a */
/*0ac0*/ IMAD R7, R18, R17, R7 ; /* 0x0000001112077224 */
/* 0x010fc800078e0207 */
/*0ad0*/ IMAD R28, R20, R19, R7 ; /* 0x00000013141c7224 */
/* 0x020fe200078e0207 */
/*0ae0*/ @P0 BRA 0x960 ; /* 0xfffffe7000000947 */
/* 0x000fea000383ffff */
/*0af0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b00*/ @!P0 BRA 0xbf0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0b10*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x000fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fd000078e0200 */
/*0b40*/ IMAD.WIDE R6, R6, R9, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0209 */
/*0b50*/ IMAD.WIDE R8, R4, R9, c[0x0][0x168] ; /* 0x00005a0004087625 */
/* 0x000fca00078e0209 */
/*0b60*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0000a8000c1e1900 */
/*0b70*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x0002a2000c1e1900 */
/*0b80*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc80007ffe0ff */
/*0b90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0ba0*/ IMAD.WIDE R8, R2, 0x4, R8 ; /* 0x0000000402087825 */
/* 0x001fe200078e0208 */
/*0bb0*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0bc0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bd0*/ IMAD R28, R11, R4, R28 ; /* 0x000000040b1c7224 */
/* 0x004fcc00078e021c */
/*0be0*/ @P0 BRA 0xb60 ; /* 0xffffff7000000947 */
/* 0x000fea000383ffff */
/*0bf0*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c00*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fca0000000f00 */
/*0c10*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c20*/ STG.E [R2.64], R28 ; /* 0x0000001c02007986 */
/* 0x000fe2000c101904 */
/*0c30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c40*/ BRA 0xc40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPiS_S_i
.globl _Z9matrixMulPiS_S_i
.p2align 8
.type _Z9matrixMulPiS_S_i,@function
_Z9matrixMulPiS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[3:4], 2, v[2:3]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
.p2align 6
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v6, 31, v5
s_add_i32 s3, s3, -1
s_cmp_eq_u32 s3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
global_load_b32 v8, v[3:4], off
global_load_b32 v9, v[6:7], off
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[6:7], null, v9, v8, v[2:3]
v_add_co_u32 v3, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_dual_mov_b32 v2, v6 :: v_dual_add_nc_u32 v5, s2, v5
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v0, s2, v[1:2]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPiS_S_i, .Lfunc_end0-_Z9matrixMulPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00130063_00000000-6_matrix_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11matrix_initPii
.type _Z11matrix_initPii, @function
_Z11matrix_initPii:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L9
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
movl %esi, %r14d
movslq %esi, %r13
leaq 0(,%r13,4), %r15
leaq (%rdi,%r15), %rbp
negq %r13
salq $2, %r13
movl $0, %r12d
.L5:
leaq 0(%rbp,%r13), %rbx
.L6:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
addl $1, %r12d
addq %r15, %rbp
cmpl %r12d, %r14d
jne .L5
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore 3
.cfi_restore 6
.cfi_restore 12
.cfi_restore 13
.cfi_restore 14
.cfi_restore 15
ret
.cfi_endproc
.LFE2057:
.size _Z11matrix_initPii, .-_Z11matrix_initPii
.globl _Z12check_answerPiS_S_i
.type _Z12check_answerPiS_S_i, @function
_Z12check_answerPiS_S_i:
.LFB2058:
.cfi_startproc
endbr64
movl $0, %edi
movl $0, %r8d
testl %ecx, %ecx
jg .L13
ret
.L16:
leal 1(%rdi), %eax
cmpl %edx, %edi
je .L21
movl %eax, %edi
.L13:
movl %r8d, %esi
.L18:
movl $0, %eax
.L15:
movl %eax, %edx
addl $1, %eax
cmpl %eax, %ecx
jne .L15
leal 1(%rsi), %eax
cmpl %edx, %esi
je .L16
movl %eax, %esi
jmp .L18
.L21:
movl $0, %esi
.L17:
movl $0, %eax
.L19:
movl %eax, %ecx
addl $1, %eax
cmpl %ecx, %edx
jne .L19
leal 1(%rsi), %eax
cmpl %esi, %edx
je .L12
movl %eax, %esi
jmp .L17
.L12:
ret
.cfi_endproc
.LFE2058:
.size _Z12check_answerPiS_S_i, .-_Z12check_answerPiS_S_i
.globl _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.type _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixMulPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
.globl _Z9matrixMulPiS_S_i
.type _Z9matrixMulPiS_S_i, @function
_Z9matrixMulPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9matrixMulPiS_S_i, .-_Z9matrixMulPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Completed.\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbp
movl $4194304, %edi
call malloc@PLT
movq %rax, %rbx
movl $4194304, %edi
call malloc@PLT
movq %rax, %r12
leaq 8(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4194304, %esi
call cudaMalloc@PLT
movl $1024, %esi
movq %rbp, %rdi
call _Z11matrix_initPii
movl $1024, %esi
movq %rbx, %rdi
call _Z11matrix_initPii
movl $1, %ecx
movl $4194304, %edx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4194304, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 32(%rsp)
movl $64, 36(%rsp)
movl $16, 44(%rsp)
movl $16, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L34:
movl $2, %ecx
movl $4194304, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
movl $1024, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9matrixMulPiS_S_iPiS_S_i
jmp .L34
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9matrixMulPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mult.hip"
.globl _Z24__device_stub__matrixMulPiS_S_i # -- Begin function _Z24__device_stub__matrixMulPiS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPiS_S_i,@function
_Z24__device_stub__matrixMulPiS_S_i: # @_Z24__device_stub__matrixMulPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixMulPiS_S_i, .Lfunc_end0-_Z24__device_stub__matrixMulPiS_S_i
.cfi_endproc
# -- End function
.globl _Z11matrix_initPii # -- Begin function _Z11matrix_initPii
.p2align 4, 0x90
.type _Z11matrix_initPii,@function
_Z11matrix_initPii: # @_Z11matrix_initPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, (%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %esi, %ebx
movl %esi, %r15d
xorl %r12d, %r12d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r12d, %eax
movq (%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbp
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%rbp,%r14,4)
incq %r14
cmpq %r14, %r15
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %r13
addl %ebx, %r12d
cmpq %r15, %r13
jne .LBB1_2
.LBB1_5: # %._crit_edge13
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11matrix_initPii, .Lfunc_end1-_Z11matrix_initPii
.cfi_endproc
# -- End function
.globl _Z12check_answerPiS_S_i # -- Begin function _Z12check_answerPiS_S_i
.p2align 4, 0x90
.type _Z12check_answerPiS_S_i,@function
_Z12check_answerPiS_S_i: # @_Z12check_answerPiS_S_i
.cfi_startproc
# %bb.0: # %.preheader36
retq
.Lfunc_end2:
.size _Z12check_answerPiS_S_i, .Lfunc_end2-_Z12check_answerPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %rbx
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r14
movl $4194304, %edi # imm = 0x400000
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4194304, %esi # imm = 0x400000
callq hipMalloc
xorl %r12d, %r12d
movq %rbx, %r13
.p2align 4, 0x90
.LBB3_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_2 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_2: # Parent Loop BB3_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbp,4)
incq %rbp
cmpq $1024, %rbp # imm = 0x400
jne .LBB3_2
# %bb.3: # %._crit_edge.i
# in Loop: Header=BB3_1 Depth=1
incq %r12
addq $4096, %r13 # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB3_1
# %bb.4: # %.preheader.i37.preheader
xorl %r12d, %r12d
movq %r14, %r13
.p2align 4, 0x90
.LBB3_5: # %.preheader.i37
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r13,%rbp,4)
incq %rbp
cmpq $1024, %rbp # imm = 0x400
jne .LBB3_6
# %bb.7: # %._crit_edge.i42
# in Loop: Header=BB3_5 Depth=1
incq %r12
addq $4096, %r13 # imm = 0x1000
cmpq $1024, %r12 # imm = 0x400
jne .LBB3_5
# %bb.8: # %_Z11matrix_initPii.exit45
movq 24(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4194304, %edx # imm = 0x400000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $274877907008, %rdi # imm = 0x4000000040
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $1024, 36(%rsp) # imm = 0x400
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9matrixMulPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_10:
movq 8(%rsp), %rsi
movl $4194304, %edx # imm = 0x400000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr, %edi
callq puts@PLT
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPiS_S_i,@object # @_Z9matrixMulPiS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixMulPiS_S_i
.p2align 3, 0x0
_Z9matrixMulPiS_S_i:
.quad _Z24__device_stub__matrixMulPiS_S_i
.size _Z9matrixMulPiS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9matrixMulPiS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Completed."
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPiS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <stdlib.h>
#include <time.h>
#include <cfloat>
#define min(a, b) (a < b ? a : b)
#define max(a, b) (a > b ? a : b)
#define abs(a) (a > 0 ? a : -1 * a)
#define MAX_BLOCKS 50000
__global__ void kMeansStep2(int *d_counts, float *d_new_clusters, float *d_prev_clusters, int *converged, int n_clusters, int d){
int cluster = threadIdx.x;
int dim = threadIdx.y;
if (dim == 0){
printf("cluster number %d, count %d\n", cluster, d_counts[cluster]);
}
int count = max(1, d_counts[cluster]);
d_new_clusters[cluster * d + dim] /= (float)count;
if (abs(d_new_clusters[cluster * d + dim] - d_prev_clusters[cluster * d + dim]) > 0.01)
atomicAnd(&converged[0], 0);
}
__global__ void kMeansStep1(float *d_data, float *d_prev_clusters, float *d_new_clusters, int *d_counts, int n_data, int n_clusters, int d){
int data = blockIdx.x;
int cluster = threadIdx.x;
int dim = threadIdx.y;
// if (blockIdx.x > 5000)
// printf("data number %d\n", blockIdx.x);
while(data < n_data){
extern __shared__ float s[];
float *shared_dist = s;
float *shared_data = (float*)&shared_dist[n_clusters];
float *shared_prev_clusters = (float*)&shared_data[d];
shared_dist[cluster] = 0.0;
shared_prev_clusters[cluster * d + dim] = d_prev_clusters[cluster * d + dim];
if (cluster == 0)
shared_data[dim] = d_data[data * d + dim];
__syncthreads();
float tmp_dist = shared_prev_clusters[cluster * d + dim] - shared_data[dim];
float dist_data_cluster_dim = tmp_dist * tmp_dist;
atomicAdd(&shared_dist[cluster], dist_data_cluster_dim);
__syncthreads();
__shared__ int best_cluster;
if (cluster == 0 && dim == 0){
float best_distance = FLT_MAX;
best_cluster = -1;
for (int j=0; j<n_clusters; j++)
if (shared_dist[j] < best_distance){
best_distance = shared_dist[j];
best_cluster = j;
}
printf("data point number %d assigned to cluster %d\n", data, best_cluster);
atomicAdd(&d_counts[best_cluster], 1);
}
__syncthreads();
if (cluster == 0){
atomicAdd(&d_new_clusters[best_cluster * d + dim], shared_data[dim]);
// printf("%f is added to new clusters %d , %d\n", shared_data[dim], best_cluster, dim);
}
data += MAX_BLOCKS;
__syncthreads();
}
}
int main(){
srand((unsigned int)time(NULL));
int n_data = 30;
int n_clusters = 4;
int d = 2;
int size_data = sizeof(float) * n_data * d;
int size_clusters = sizeof(float) * n_clusters * d;
int *h_converged = (int *)malloc(1 * sizeof(int));
float *h_data = (float *)malloc(size_data);
float *h_clusters = (float *)malloc(size_clusters);
int data_x[30] = {25,34,22,27,33,33,31,22,35,34,67,54,57,43,50,57,59,52,65,47,49,48,35,33,44,45,38,43,51,46};
int data_y[30] = {79,51,53,78,59,74,73,57,69,75,51,32,40,47,53,36,35,58,59,50,25,20,14,12,20,5,29,27,8,7};
for (int i=0; i<n_data*d; i++){
// h_data[i] = ((float)rand()/(float)(RAND_MAX)) * 100.0;
if (i % 2 == 0)
h_data[i] = data_x[i / 2];
else
h_data[i] = data_y[i / 2];
printf("%f ", h_data[i]);
if ((i+1) % d == 0)
printf("\n");
}
printf("\ninitial clusters:\n");
for (int i=0; i<n_clusters*d; i++){
h_clusters[i] = ((float)rand()/(float)(RAND_MAX)) * 100.0;
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
float *d_data, *d_new_clusters, *d_prev_clusters;
int *d_converged, *d_counts;
cudaMalloc((void **)&d_data, size_data);
cudaMalloc((void **)&d_new_clusters, size_clusters);
cudaMalloc((void **)&d_prev_clusters, size_clusters);
cudaMalloc((void **)&d_counts, n_clusters * sizeof(int));
cudaMalloc((void **)&d_converged, sizeof(int));
cudaMemcpy(d_data, h_data, size_data, cudaMemcpyHostToDevice);
cudaMemcpy(d_prev_clusters, h_clusters, size_clusters, cudaMemcpyHostToDevice);
float *d1 = d_prev_clusters;
float *d2 = d_new_clusters;
dim3 bd(n_clusters, d);
int n_data_blocks = min(n_data, MAX_BLOCKS);
int sharedMemSize1 = (n_clusters + d + n_clusters * d) * sizeof(float);
int iteration = 1;
clock_t start_time = clock();
while(1){
cudaMemset(d2, 0.0, size_clusters);
cudaMemset(d_counts, 0, n_clusters * sizeof(int));
kMeansStep1 <<<n_data_blocks, bd, sharedMemSize1>>> (d_data, d1, d2, d_counts, n_data, n_clusters, d);
cudaThreadSynchronize();
h_converged[0] = 1;
cudaMemcpy(d_converged, h_converged, sizeof(int), cudaMemcpyHostToDevice);
kMeansStep2 <<<1, bd>>> (d_counts, d2, d1, d_converged, n_clusters, d);
cudaThreadSynchronize();
cudaMemcpy(h_clusters, d1, size_clusters, cudaMemcpyDeviceToHost);
printf("\niteration %d prev cluster:\n", iteration);
for(int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
cudaMemcpy(h_clusters, d2, size_clusters, cudaMemcpyDeviceToHost);
printf("\niteration %d new cluster:\n", iteration);
for(int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
cudaMemcpy(h_converged, d_converged, sizeof(int), cudaMemcpyDeviceToHost);
if (h_converged[0] == 1){
cudaMemcpy(h_clusters, d2, size_clusters, cudaMemcpyDeviceToHost);
break;
}
d1 = d1 == d_prev_clusters ? d_new_clusters : d_prev_clusters;
d2 = d2 == d_prev_clusters ? d_new_clusters : d_prev_clusters;
iteration += 1;
if (iteration > 10)
break;
}
clock_t end_time = clock();
printf("\nFinished!!\n");
printf("Final clusters:\n");
for (int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
printf("number of iterations is %d \n", iteration);
double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
printf("total time: %f\n", total_time);
return 0;
} | .file "tmpxft_0016415f_00000000-6_kmeans_v2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii
.type _Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii, @function
_Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11kMeansStep2PiPfS0_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii, .-_Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii
.globl _Z11kMeansStep2PiPfS0_S_ii
.type _Z11kMeansStep2PiPfS0_S_ii, @function
_Z11kMeansStep2PiPfS0_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11kMeansStep2PiPfS0_S_ii, .-_Z11kMeansStep2PiPfS0_S_ii
.globl _Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii
.type _Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii, @function
_Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11kMeansStep1PfS_S_Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii, .-_Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii
.globl _Z11kMeansStep1PfS_S_Piiii
.type _Z11kMeansStep1PfS_S_Piiii, @function
_Z11kMeansStep1PfS_S_Piiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11kMeansStep1PfS_S_Piiii, .-_Z11kMeansStep1PfS_S_Piiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "\n"
.LC2:
.string "\ninitial clusters:\n"
.LC5:
.string "\niteration %d prev cluster:\n"
.LC6:
.string "\niteration %d new cluster:\n"
.LC7:
.string "\nFinished!!\n"
.LC8:
.string "Final clusters:\n"
.LC9:
.string "number of iterations is %d \n"
.LC11:
.string "total time: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $360, %rsp
.cfi_def_cfa_offset 416
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $4, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $240, %edi
call malloc@PLT
movq %rax, %r15
movl $32, %edi
call malloc@PLT
movq %rax, %rbp
movl $25, 96(%rsp)
movl $34, 100(%rsp)
movl $22, 104(%rsp)
movl $27, 108(%rsp)
movl $33, 112(%rsp)
movl $33, 116(%rsp)
movl $31, 120(%rsp)
movl $22, 124(%rsp)
movl $35, 128(%rsp)
movl $34, 132(%rsp)
movl $67, 136(%rsp)
movl $54, 140(%rsp)
movl $57, 144(%rsp)
movl $43, 148(%rsp)
movl $50, 152(%rsp)
movl $57, 156(%rsp)
movl $59, 160(%rsp)
movl $52, 164(%rsp)
movl $65, 168(%rsp)
movl $47, 172(%rsp)
movl $49, 176(%rsp)
movl $48, 180(%rsp)
movl $35, 184(%rsp)
movl $33, 188(%rsp)
movl $44, 192(%rsp)
movl $45, 196(%rsp)
movl $38, 200(%rsp)
movl $43, 204(%rsp)
movl $51, 208(%rsp)
movl $46, 212(%rsp)
movl $79, 224(%rsp)
movl $51, 228(%rsp)
movl $53, 232(%rsp)
movl $78, 236(%rsp)
movl $59, 240(%rsp)
movl $74, 244(%rsp)
movl $73, 248(%rsp)
movl $57, 252(%rsp)
movl $69, 256(%rsp)
movl $75, 260(%rsp)
movl $51, 264(%rsp)
movl $32, 268(%rsp)
movl $40, 272(%rsp)
movl $47, 276(%rsp)
movl $53, 280(%rsp)
movl $36, 284(%rsp)
movl $35, 288(%rsp)
movl $58, 292(%rsp)
movl $59, 296(%rsp)
movl $50, 300(%rsp)
movl $25, 304(%rsp)
movl $20, 308(%rsp)
movl $14, 312(%rsp)
movl $12, 316(%rsp)
movl $20, 320(%rsp)
movl $5, 324(%rsp)
movl $29, 328(%rsp)
movl $27, 332(%rsp)
movl $8, 336(%rsp)
movl $7, 340(%rsp)
movq %r15, %r12
movl $0, %ebx
leaq .LC0(%rip), %r13
leaq .LC1(%rip), %r14
jmp .L23
.L20:
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
cltq
pxor %xmm0, %xmm0
cvtsi2ssl 224(%rsp,%rax,4), %xmm0
movss %xmm0, (%r12)
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
testb $1, %bl
je .L49
.L22:
addq $4, %r12
cmpl $60, %ebx
je .L50
.L23:
testb $1, %bl
jne .L20
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
cltq
pxor %xmm0, %xmm0
cvtsi2ssl 96(%rsp,%rax,4), %xmm0
movss %xmm0, (%r12)
jmp .L21
.L49:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L50:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L25
.L24:
addq $1, %rbx
cmpq $9, %rbx
je .L51
.L25:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC3(%rip), %xmm0
mulss .LC4(%rip), %xmm0
movss %xmm0, -4(%rbp,%rbx,4)
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $1, %bl
jne .L24
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L51:
leaq 32(%rsp), %rdi
movl $240, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $240, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $32, %edx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rax
movq %rax, 8(%rsp)
movq 40(%rsp), %r15
movl $4, 72(%rsp)
movl $2, 76(%rsp)
movl $1, 80(%rsp)
call clock@PLT
movq %rax, 24(%rsp)
movl $1, %r14d
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L36
.L57:
subq $8, %rsp
.cfi_def_cfa_offset 424
pushq $2
.cfi_def_cfa_offset 432
movl $4, %r9d
movl $30, %r8d
movq 80(%rsp), %rcx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L26
.L58:
movl $2, %r9d
movl $4, %r8d
movq 56(%rsp), %rcx
movq 8(%rsp), %rdx
movq %r15, %rsi
movq 64(%rsp), %rdi
call _Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii
jmp .L27
.L28:
addq $1, %rbx
cmpq $9, %rbx
je .L52
.L29:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $1, %bl
jne .L28
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L52:
movl $2, %ecx
movl $32, %edx
movq %r15, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %r14d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
jmp .L31
.L30:
addq $1, %rbx
cmpq $9, %rbx
je .L53
.L31:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $1, %bl
jne .L30
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L30
.L53:
movl $2, %ecx
movl $4, %edx
movq 56(%rsp), %rsi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
cmpl $1, (%rbx)
je .L54
movq 48(%rsp), %rax
movq 8(%rsp), %rcx
cmpq %rcx, %rax
je .L55
movq %rax, 8(%rsp)
.L34:
cmpq %r15, %rax
je .L56
movq %rax, %r15
.L35:
addl $1, %r14d
cmpl $11, %r14d
je .L33
.L36:
movl $32, %edx
movl $0, %esi
movq %r15, %rdi
call cudaMemset@PLT
movl $16, %edx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaMemset@PLT
movl $30, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl 80(%rsp), %ecx
movl $0, %r9d
movl $56, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L26:
call cudaThreadSynchronize@PLT
movq 16(%rsp), %rax
movl $1, (%rax)
movl $1, %ecx
movl $4, %edx
movq %rax, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L27:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $32, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %r14d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
jmp .L29
.L54:
movl $2, %ecx
movl $32, %edx
movq %r15, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
.L33:
call clock@PLT
movq %rax, %r15
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L38
.L55:
movq 40(%rsp), %rdx
movq %rdx, 8(%rsp)
jmp .L34
.L56:
movq 40(%rsp), %r15
jmp .L35
.L37:
addq $1, %rbx
cmpq $9, %rbx
je .L59
.L38:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $1, %bl
jne .L37
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L37
.L59:
movl %r14d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %rax, %r15
pxor %xmm0, %xmm0
cvtsi2sdq %r15, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z11kMeansStep1PfS_S_Piiii"
.LC13:
.string "_Z11kMeansStep2PiPfS0_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kMeansStep1PfS_S_Piiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kMeansStep2PiPfS0_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 805306368
.align 4
.LC4:
.long 1120403456
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime_api.h>
#include <device_launch_parameters.h>
#include <stdlib.h>
#include <time.h>
#include <cfloat>
#define min(a, b) (a < b ? a : b)
#define max(a, b) (a > b ? a : b)
#define abs(a) (a > 0 ? a : -1 * a)
#define MAX_BLOCKS 50000
__global__ void kMeansStep2(int *d_counts, float *d_new_clusters, float *d_prev_clusters, int *converged, int n_clusters, int d){
int cluster = threadIdx.x;
int dim = threadIdx.y;
if (dim == 0){
printf("cluster number %d, count %d\n", cluster, d_counts[cluster]);
}
int count = max(1, d_counts[cluster]);
d_new_clusters[cluster * d + dim] /= (float)count;
if (abs(d_new_clusters[cluster * d + dim] - d_prev_clusters[cluster * d + dim]) > 0.01)
atomicAnd(&converged[0], 0);
}
__global__ void kMeansStep1(float *d_data, float *d_prev_clusters, float *d_new_clusters, int *d_counts, int n_data, int n_clusters, int d){
int data = blockIdx.x;
int cluster = threadIdx.x;
int dim = threadIdx.y;
// if (blockIdx.x > 5000)
// printf("data number %d\n", blockIdx.x);
while(data < n_data){
extern __shared__ float s[];
float *shared_dist = s;
float *shared_data = (float*)&shared_dist[n_clusters];
float *shared_prev_clusters = (float*)&shared_data[d];
shared_dist[cluster] = 0.0;
shared_prev_clusters[cluster * d + dim] = d_prev_clusters[cluster * d + dim];
if (cluster == 0)
shared_data[dim] = d_data[data * d + dim];
__syncthreads();
float tmp_dist = shared_prev_clusters[cluster * d + dim] - shared_data[dim];
float dist_data_cluster_dim = tmp_dist * tmp_dist;
atomicAdd(&shared_dist[cluster], dist_data_cluster_dim);
__syncthreads();
__shared__ int best_cluster;
if (cluster == 0 && dim == 0){
float best_distance = FLT_MAX;
best_cluster = -1;
for (int j=0; j<n_clusters; j++)
if (shared_dist[j] < best_distance){
best_distance = shared_dist[j];
best_cluster = j;
}
printf("data point number %d assigned to cluster %d\n", data, best_cluster);
atomicAdd(&d_counts[best_cluster], 1);
}
__syncthreads();
if (cluster == 0){
atomicAdd(&d_new_clusters[best_cluster * d + dim], shared_data[dim]);
// printf("%f is added to new clusters %d , %d\n", shared_data[dim], best_cluster, dim);
}
data += MAX_BLOCKS;
__syncthreads();
}
}
int main(){
srand((unsigned int)time(NULL));
int n_data = 30;
int n_clusters = 4;
int d = 2;
int size_data = sizeof(float) * n_data * d;
int size_clusters = sizeof(float) * n_clusters * d;
int *h_converged = (int *)malloc(1 * sizeof(int));
float *h_data = (float *)malloc(size_data);
float *h_clusters = (float *)malloc(size_clusters);
int data_x[30] = {25,34,22,27,33,33,31,22,35,34,67,54,57,43,50,57,59,52,65,47,49,48,35,33,44,45,38,43,51,46};
int data_y[30] = {79,51,53,78,59,74,73,57,69,75,51,32,40,47,53,36,35,58,59,50,25,20,14,12,20,5,29,27,8,7};
for (int i=0; i<n_data*d; i++){
// h_data[i] = ((float)rand()/(float)(RAND_MAX)) * 100.0;
if (i % 2 == 0)
h_data[i] = data_x[i / 2];
else
h_data[i] = data_y[i / 2];
printf("%f ", h_data[i]);
if ((i+1) % d == 0)
printf("\n");
}
printf("\ninitial clusters:\n");
for (int i=0; i<n_clusters*d; i++){
h_clusters[i] = ((float)rand()/(float)(RAND_MAX)) * 100.0;
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
float *d_data, *d_new_clusters, *d_prev_clusters;
int *d_converged, *d_counts;
cudaMalloc((void **)&d_data, size_data);
cudaMalloc((void **)&d_new_clusters, size_clusters);
cudaMalloc((void **)&d_prev_clusters, size_clusters);
cudaMalloc((void **)&d_counts, n_clusters * sizeof(int));
cudaMalloc((void **)&d_converged, sizeof(int));
cudaMemcpy(d_data, h_data, size_data, cudaMemcpyHostToDevice);
cudaMemcpy(d_prev_clusters, h_clusters, size_clusters, cudaMemcpyHostToDevice);
float *d1 = d_prev_clusters;
float *d2 = d_new_clusters;
dim3 bd(n_clusters, d);
int n_data_blocks = min(n_data, MAX_BLOCKS);
int sharedMemSize1 = (n_clusters + d + n_clusters * d) * sizeof(float);
int iteration = 1;
clock_t start_time = clock();
while(1){
cudaMemset(d2, 0.0, size_clusters);
cudaMemset(d_counts, 0, n_clusters * sizeof(int));
kMeansStep1 <<<n_data_blocks, bd, sharedMemSize1>>> (d_data, d1, d2, d_counts, n_data, n_clusters, d);
cudaThreadSynchronize();
h_converged[0] = 1;
cudaMemcpy(d_converged, h_converged, sizeof(int), cudaMemcpyHostToDevice);
kMeansStep2 <<<1, bd>>> (d_counts, d2, d1, d_converged, n_clusters, d);
cudaThreadSynchronize();
cudaMemcpy(h_clusters, d1, size_clusters, cudaMemcpyDeviceToHost);
printf("\niteration %d prev cluster:\n", iteration);
for(int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
cudaMemcpy(h_clusters, d2, size_clusters, cudaMemcpyDeviceToHost);
printf("\niteration %d new cluster:\n", iteration);
for(int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
cudaMemcpy(h_converged, d_converged, sizeof(int), cudaMemcpyDeviceToHost);
if (h_converged[0] == 1){
cudaMemcpy(h_clusters, d2, size_clusters, cudaMemcpyDeviceToHost);
break;
}
d1 = d1 == d_prev_clusters ? d_new_clusters : d_prev_clusters;
d2 = d2 == d_prev_clusters ? d_new_clusters : d_prev_clusters;
iteration += 1;
if (iteration > 10)
break;
}
clock_t end_time = clock();
printf("\nFinished!!\n");
printf("Final clusters:\n");
for (int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
printf("number of iterations is %d \n", iteration);
double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
printf("total time: %f\n", total_time);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdlib.h>
#include <time.h>
#include <cfloat>
#define min(a, b) (a < b ? a : b)
#define max(a, b) (a > b ? a : b)
#define abs(a) (a > 0 ? a : -1 * a)
#define MAX_BLOCKS 50000
__global__ void kMeansStep2(int *d_counts, float *d_new_clusters, float *d_prev_clusters, int *converged, int n_clusters, int d){
int cluster = threadIdx.x;
int dim = threadIdx.y;
if (dim == 0){
printf("cluster number %d, count %d\n", cluster, d_counts[cluster]);
}
int count = max(1, d_counts[cluster]);
d_new_clusters[cluster * d + dim] /= (float)count;
if (abs(d_new_clusters[cluster * d + dim] - d_prev_clusters[cluster * d + dim]) > 0.01)
atomicAnd(&converged[0], 0);
}
__global__ void kMeansStep1(float *d_data, float *d_prev_clusters, float *d_new_clusters, int *d_counts, int n_data, int n_clusters, int d){
int data = blockIdx.x;
int cluster = threadIdx.x;
int dim = threadIdx.y;
// if (blockIdx.x > 5000)
// printf("data number %d\n", blockIdx.x);
while(data < n_data){
extern __shared__ float s[];
float *shared_dist = s;
float *shared_data = (float*)&shared_dist[n_clusters];
float *shared_prev_clusters = (float*)&shared_data[d];
shared_dist[cluster] = 0.0;
shared_prev_clusters[cluster * d + dim] = d_prev_clusters[cluster * d + dim];
if (cluster == 0)
shared_data[dim] = d_data[data * d + dim];
__syncthreads();
float tmp_dist = shared_prev_clusters[cluster * d + dim] - shared_data[dim];
float dist_data_cluster_dim = tmp_dist * tmp_dist;
atomicAdd(&shared_dist[cluster], dist_data_cluster_dim);
__syncthreads();
__shared__ int best_cluster;
if (cluster == 0 && dim == 0){
float best_distance = FLT_MAX;
best_cluster = -1;
for (int j=0; j<n_clusters; j++)
if (shared_dist[j] < best_distance){
best_distance = shared_dist[j];
best_cluster = j;
}
printf("data point number %d assigned to cluster %d\n", data, best_cluster);
atomicAdd(&d_counts[best_cluster], 1);
}
__syncthreads();
if (cluster == 0){
atomicAdd(&d_new_clusters[best_cluster * d + dim], shared_data[dim]);
// printf("%f is added to new clusters %d , %d\n", shared_data[dim], best_cluster, dim);
}
data += MAX_BLOCKS;
__syncthreads();
}
}
int main(){
srand((unsigned int)time(NULL));
int n_data = 30;
int n_clusters = 4;
int d = 2;
int size_data = sizeof(float) * n_data * d;
int size_clusters = sizeof(float) * n_clusters * d;
int *h_converged = (int *)malloc(1 * sizeof(int));
float *h_data = (float *)malloc(size_data);
float *h_clusters = (float *)malloc(size_clusters);
int data_x[30] = {25,34,22,27,33,33,31,22,35,34,67,54,57,43,50,57,59,52,65,47,49,48,35,33,44,45,38,43,51,46};
int data_y[30] = {79,51,53,78,59,74,73,57,69,75,51,32,40,47,53,36,35,58,59,50,25,20,14,12,20,5,29,27,8,7};
for (int i=0; i<n_data*d; i++){
// h_data[i] = ((float)rand()/(float)(RAND_MAX)) * 100.0;
if (i % 2 == 0)
h_data[i] = data_x[i / 2];
else
h_data[i] = data_y[i / 2];
printf("%f ", h_data[i]);
if ((i+1) % d == 0)
printf("\n");
}
printf("\ninitial clusters:\n");
for (int i=0; i<n_clusters*d; i++){
h_clusters[i] = ((float)rand()/(float)(RAND_MAX)) * 100.0;
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
float *d_data, *d_new_clusters, *d_prev_clusters;
int *d_converged, *d_counts;
hipMalloc((void **)&d_data, size_data);
hipMalloc((void **)&d_new_clusters, size_clusters);
hipMalloc((void **)&d_prev_clusters, size_clusters);
hipMalloc((void **)&d_counts, n_clusters * sizeof(int));
hipMalloc((void **)&d_converged, sizeof(int));
hipMemcpy(d_data, h_data, size_data, hipMemcpyHostToDevice);
hipMemcpy(d_prev_clusters, h_clusters, size_clusters, hipMemcpyHostToDevice);
float *d1 = d_prev_clusters;
float *d2 = d_new_clusters;
dim3 bd(n_clusters, d);
int n_data_blocks = min(n_data, MAX_BLOCKS);
int sharedMemSize1 = (n_clusters + d + n_clusters * d) * sizeof(float);
int iteration = 1;
clock_t start_time = clock();
while(1){
hipMemset(d2, 0.0, size_clusters);
hipMemset(d_counts, 0, n_clusters * sizeof(int));
kMeansStep1 <<<n_data_blocks, bd, sharedMemSize1>>> (d_data, d1, d2, d_counts, n_data, n_clusters, d);
hipDeviceSynchronize();
h_converged[0] = 1;
hipMemcpy(d_converged, h_converged, sizeof(int), hipMemcpyHostToDevice);
kMeansStep2 <<<1, bd>>> (d_counts, d2, d1, d_converged, n_clusters, d);
hipDeviceSynchronize();
hipMemcpy(h_clusters, d1, size_clusters, hipMemcpyDeviceToHost);
printf("\niteration %d prev cluster:\n", iteration);
for(int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
hipMemcpy(h_clusters, d2, size_clusters, hipMemcpyDeviceToHost);
printf("\niteration %d new cluster:\n", iteration);
for(int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
hipMemcpy(h_converged, d_converged, sizeof(int), hipMemcpyDeviceToHost);
if (h_converged[0] == 1){
hipMemcpy(h_clusters, d2, size_clusters, hipMemcpyDeviceToHost);
break;
}
d1 = d1 == d_prev_clusters ? d_new_clusters : d_prev_clusters;
d2 = d2 == d_prev_clusters ? d_new_clusters : d_prev_clusters;
iteration += 1;
if (iteration > 10)
break;
}
clock_t end_time = clock();
printf("\nFinished!!\n");
printf("Final clusters:\n");
for (int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
printf("number of iterations is %d \n", iteration);
double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
printf("total time: %f\n", total_time);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdlib.h>
#include <time.h>
#include <cfloat>
#define min(a, b) (a < b ? a : b)
#define max(a, b) (a > b ? a : b)
#define abs(a) (a > 0 ? a : -1 * a)
#define MAX_BLOCKS 50000
__global__ void kMeansStep2(int *d_counts, float *d_new_clusters, float *d_prev_clusters, int *converged, int n_clusters, int d){
int cluster = threadIdx.x;
int dim = threadIdx.y;
if (dim == 0){
printf("cluster number %d, count %d\n", cluster, d_counts[cluster]);
}
int count = max(1, d_counts[cluster]);
d_new_clusters[cluster * d + dim] /= (float)count;
if (abs(d_new_clusters[cluster * d + dim] - d_prev_clusters[cluster * d + dim]) > 0.01)
atomicAnd(&converged[0], 0);
}
__global__ void kMeansStep1(float *d_data, float *d_prev_clusters, float *d_new_clusters, int *d_counts, int n_data, int n_clusters, int d){
int data = blockIdx.x;
int cluster = threadIdx.x;
int dim = threadIdx.y;
// if (blockIdx.x > 5000)
// printf("data number %d\n", blockIdx.x);
while(data < n_data){
extern __shared__ float s[];
float *shared_dist = s;
float *shared_data = (float*)&shared_dist[n_clusters];
float *shared_prev_clusters = (float*)&shared_data[d];
shared_dist[cluster] = 0.0;
shared_prev_clusters[cluster * d + dim] = d_prev_clusters[cluster * d + dim];
if (cluster == 0)
shared_data[dim] = d_data[data * d + dim];
__syncthreads();
float tmp_dist = shared_prev_clusters[cluster * d + dim] - shared_data[dim];
float dist_data_cluster_dim = tmp_dist * tmp_dist;
atomicAdd(&shared_dist[cluster], dist_data_cluster_dim);
__syncthreads();
__shared__ int best_cluster;
if (cluster == 0 && dim == 0){
float best_distance = FLT_MAX;
best_cluster = -1;
for (int j=0; j<n_clusters; j++)
if (shared_dist[j] < best_distance){
best_distance = shared_dist[j];
best_cluster = j;
}
printf("data point number %d assigned to cluster %d\n", data, best_cluster);
atomicAdd(&d_counts[best_cluster], 1);
}
__syncthreads();
if (cluster == 0){
atomicAdd(&d_new_clusters[best_cluster * d + dim], shared_data[dim]);
// printf("%f is added to new clusters %d , %d\n", shared_data[dim], best_cluster, dim);
}
data += MAX_BLOCKS;
__syncthreads();
}
}
int main(){
srand((unsigned int)time(NULL));
int n_data = 30;
int n_clusters = 4;
int d = 2;
int size_data = sizeof(float) * n_data * d;
int size_clusters = sizeof(float) * n_clusters * d;
int *h_converged = (int *)malloc(1 * sizeof(int));
float *h_data = (float *)malloc(size_data);
float *h_clusters = (float *)malloc(size_clusters);
int data_x[30] = {25,34,22,27,33,33,31,22,35,34,67,54,57,43,50,57,59,52,65,47,49,48,35,33,44,45,38,43,51,46};
int data_y[30] = {79,51,53,78,59,74,73,57,69,75,51,32,40,47,53,36,35,58,59,50,25,20,14,12,20,5,29,27,8,7};
for (int i=0; i<n_data*d; i++){
// h_data[i] = ((float)rand()/(float)(RAND_MAX)) * 100.0;
if (i % 2 == 0)
h_data[i] = data_x[i / 2];
else
h_data[i] = data_y[i / 2];
printf("%f ", h_data[i]);
if ((i+1) % d == 0)
printf("\n");
}
printf("\ninitial clusters:\n");
for (int i=0; i<n_clusters*d; i++){
h_clusters[i] = ((float)rand()/(float)(RAND_MAX)) * 100.0;
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
float *d_data, *d_new_clusters, *d_prev_clusters;
int *d_converged, *d_counts;
hipMalloc((void **)&d_data, size_data);
hipMalloc((void **)&d_new_clusters, size_clusters);
hipMalloc((void **)&d_prev_clusters, size_clusters);
hipMalloc((void **)&d_counts, n_clusters * sizeof(int));
hipMalloc((void **)&d_converged, sizeof(int));
hipMemcpy(d_data, h_data, size_data, hipMemcpyHostToDevice);
hipMemcpy(d_prev_clusters, h_clusters, size_clusters, hipMemcpyHostToDevice);
float *d1 = d_prev_clusters;
float *d2 = d_new_clusters;
dim3 bd(n_clusters, d);
int n_data_blocks = min(n_data, MAX_BLOCKS);
int sharedMemSize1 = (n_clusters + d + n_clusters * d) * sizeof(float);
int iteration = 1;
clock_t start_time = clock();
while(1){
hipMemset(d2, 0.0, size_clusters);
hipMemset(d_counts, 0, n_clusters * sizeof(int));
kMeansStep1 <<<n_data_blocks, bd, sharedMemSize1>>> (d_data, d1, d2, d_counts, n_data, n_clusters, d);
hipDeviceSynchronize();
h_converged[0] = 1;
hipMemcpy(d_converged, h_converged, sizeof(int), hipMemcpyHostToDevice);
kMeansStep2 <<<1, bd>>> (d_counts, d2, d1, d_converged, n_clusters, d);
hipDeviceSynchronize();
hipMemcpy(h_clusters, d1, size_clusters, hipMemcpyDeviceToHost);
printf("\niteration %d prev cluster:\n", iteration);
for(int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
hipMemcpy(h_clusters, d2, size_clusters, hipMemcpyDeviceToHost);
printf("\niteration %d new cluster:\n", iteration);
for(int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
hipMemcpy(h_converged, d_converged, sizeof(int), hipMemcpyDeviceToHost);
if (h_converged[0] == 1){
hipMemcpy(h_clusters, d2, size_clusters, hipMemcpyDeviceToHost);
break;
}
d1 = d1 == d_prev_clusters ? d_new_clusters : d_prev_clusters;
d2 = d2 == d_prev_clusters ? d_new_clusters : d_prev_clusters;
iteration += 1;
if (iteration > 10)
break;
}
clock_t end_time = clock();
printf("\nFinished!!\n");
printf("Final clusters:\n");
for (int i=0; i<n_clusters*d; i++){
printf("%f ", h_clusters[i]);
if ((i+1) % d == 0)
printf("\n");
}
printf("number of iterations is %d \n", iteration);
double total_time = ((double) (end_time - start_time)) / CLOCKS_PER_SEC;
printf("total time: %f\n", total_time);
return 0;
} | .text
.file "kmeans_v2.hip"
.globl _Z26__device_stub__kMeansStep2PiPfS0_S_ii # -- Begin function _Z26__device_stub__kMeansStep2PiPfS0_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__kMeansStep2PiPfS0_S_ii,@function
_Z26__device_stub__kMeansStep2PiPfS0_S_ii: # @_Z26__device_stub__kMeansStep2PiPfS0_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11kMeansStep2PiPfS0_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__kMeansStep2PiPfS0_S_ii, .Lfunc_end0-_Z26__device_stub__kMeansStep2PiPfS0_S_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__kMeansStep1PfS_S_Piiii # -- Begin function _Z26__device_stub__kMeansStep1PfS_S_Piiii
.p2align 4, 0x90
.type _Z26__device_stub__kMeansStep1PfS_S_Piiii,@function
_Z26__device_stub__kMeansStep1PfS_S_Piiii: # @_Z26__device_stub__kMeansStep1PfS_S_Piiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11kMeansStep1PfS_S_Piiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z26__device_stub__kMeansStep1PfS_S_Piiii, .Lfunc_end1-_Z26__device_stub__kMeansStep1PfS_S_Piiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_1:
.long 0x42c80000 # float 100
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $4, %edi
callq malloc
movq %rax, 120(%rsp) # 8-byte Spill
movl $240, %edi
callq malloc
movq %rax, %r15
movl $32, %edi
callq malloc
movq %rax, %rbx
movl $.L__const.main.data_x, %r13d
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_3: # in Loop: Header=BB2_1 Depth=1
incq %r12
cmpq $60, %r12
je .LBB2_4
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %r12d, %eax
shrl %eax
testb $1, %r12b
movl $.L__const.main.data_y, %ecx
cmoveq %r13, %rcx
xorps %xmm0, %xmm0
cvtsi2ssl (%rcx,%rax,4), %xmm0
movss %xmm0, (%r15,%r12,4)
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r12b
je .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_3
.LBB2_4:
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_5 Depth=1
incq %r12
cmpq $8, %r12
je .LBB2_8
.LBB2_5: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
mulss .LCPI2_1(%rip), %xmm0
movss %xmm0, (%rbx,%r12,4)
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r12b
je .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_7
.LBB2_8:
movabsq $8589934596, %r12 # imm = 0x200000004
movabsq $4294967297, %r14 # imm = 0x100000001
leaq 136(%rsp), %rdi
movl $240, %esi
callq hipMalloc
leaq 128(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 136(%rsp), %rdi
movl $1, %ebp
movl $240, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $32, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %r13
movq 128(%rsp), %r15
callq clock
movq %rax, 200(%rsp) # 8-byte Spill
leaq 29(%r14), %rax
movq %rax, 208(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_9: # =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
# Child Loop BB2_18 Depth 2
movl $32, %edx
movq %r15, %rdi
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
movl $16, %edx
xorl %esi, %esi
callq hipMemset
movl $56, %r8d
movq 208(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movq 136(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %r13, 96(%rsp)
movq %r15, 88(%rsp)
movq %rcx, 80(%rsp)
movl $30, 4(%rsp)
movl $4, (%rsp)
movl $2, 116(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 116(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z11kMeansStep1PfS_S_Piiii, %edi
leaq 144(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
callq hipDeviceSynchronize
movq 120(%rsp), %rsi # 8-byte Reload
movl $1, (%rsi)
movq 16(%rsp), %rdi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r12, %r14
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12: # in Loop: Header=BB2_9 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %r15, 96(%rsp)
movq %r13, 88(%rsp)
movq %rcx, 80(%rsp)
movl $4, 4(%rsp)
movl $2, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z11kMeansStep2PiPfS0_S_ii, %edi
leaq 144(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13: # in Loop: Header=BB2_9 Depth=1
callq hipDeviceSynchronize
movl $32, %edx
movq %rbx, %rdi
movq %r13, %rsi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
jmp .LBB2_14
.p2align 4, 0x90
.LBB2_16: # in Loop: Header=BB2_14 Depth=2
incq %r12
cmpq $8, %r12
je .LBB2_17
.LBB2_14: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r12b
je .LBB2_16
# %bb.15: # in Loop: Header=BB2_14 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB2_16
.p2align 4, 0x90
.LBB2_17: # in Loop: Header=BB2_9 Depth=1
movl $32, %edx
movq %rbx, %rdi
movq %r15, %rsi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
jmp .LBB2_18
.p2align 4, 0x90
.LBB2_20: # in Loop: Header=BB2_18 Depth=2
incq %r12
cmpq $8, %r12
je .LBB2_21
.LBB2_18: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r12b
je .LBB2_20
# %bb.19: # in Loop: Header=BB2_18 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB2_20
.p2align 4, 0x90
.LBB2_21: # in Loop: Header=BB2_9 Depth=1
movq 16(%rsp), %rsi
movl $4, %edx
movq 120(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $1, (%r12)
je .LBB2_22
# %bb.23: # in Loop: Header=BB2_9 Depth=1
movq 24(%rsp), %rax
cmpq %rax, %r13
movq 128(%rsp), %rcx
movq %rax, %r13
cmoveq %rcx, %r13
cmpq %rax, %r15
cmoveq %rcx, %rax
incl %ebp
movq %rax, %r15
cmpl $11, %ebp
movq %r14, %r12
jne .LBB2_9
# %bb.24:
movl $11, %ebp
jmp .LBB2_25
.LBB2_22:
movl $32, %edx
movq %rbx, %rdi
movq %r15, %rsi
movl $2, %ecx
callq hipMemcpy
.LBB2_25: # %.loopexit
callq clock
movq %rax, %r14
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r15d, %r15d
jmp .LBB2_26
.p2align 4, 0x90
.LBB2_28: # in Loop: Header=BB2_26 Depth=1
incq %r15
cmpq $8, %r15
je .LBB2_29
.LBB2_26: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r15b
je .LBB2_28
# %bb.27: # in Loop: Header=BB2_26 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_28
.LBB2_29:
movl $.L.str.7, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
subq 200(%rsp), %r14 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
divsd .LCPI2_2(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kMeansStep2PiPfS0_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kMeansStep1PfS_S_Piiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kMeansStep2PiPfS0_S_ii,@object # @_Z11kMeansStep2PiPfS0_S_ii
.section .rodata,"a",@progbits
.globl _Z11kMeansStep2PiPfS0_S_ii
.p2align 3, 0x0
_Z11kMeansStep2PiPfS0_S_ii:
.quad _Z26__device_stub__kMeansStep2PiPfS0_S_ii
.size _Z11kMeansStep2PiPfS0_S_ii, 8
.type _Z11kMeansStep1PfS_S_Piiii,@object # @_Z11kMeansStep1PfS_S_Piiii
.globl _Z11kMeansStep1PfS_S_Piiii
.p2align 3, 0x0
_Z11kMeansStep1PfS_S_Piiii:
.quad _Z26__device_stub__kMeansStep1PfS_S_Piiii
.size _Z11kMeansStep1PfS_S_Piiii, 8
.type .L__const.main.data_x,@object # @__const.main.data_x
.p2align 4, 0x0
.L__const.main.data_x:
.long 25 # 0x19
.long 34 # 0x22
.long 22 # 0x16
.long 27 # 0x1b
.long 33 # 0x21
.long 33 # 0x21
.long 31 # 0x1f
.long 22 # 0x16
.long 35 # 0x23
.long 34 # 0x22
.long 67 # 0x43
.long 54 # 0x36
.long 57 # 0x39
.long 43 # 0x2b
.long 50 # 0x32
.long 57 # 0x39
.long 59 # 0x3b
.long 52 # 0x34
.long 65 # 0x41
.long 47 # 0x2f
.long 49 # 0x31
.long 48 # 0x30
.long 35 # 0x23
.long 33 # 0x21
.long 44 # 0x2c
.long 45 # 0x2d
.long 38 # 0x26
.long 43 # 0x2b
.long 51 # 0x33
.long 46 # 0x2e
.size .L__const.main.data_x, 120
.type .L__const.main.data_y,@object # @__const.main.data_y
.p2align 4, 0x0
.L__const.main.data_y:
.long 79 # 0x4f
.long 51 # 0x33
.long 53 # 0x35
.long 78 # 0x4e
.long 59 # 0x3b
.long 74 # 0x4a
.long 73 # 0x49
.long 57 # 0x39
.long 69 # 0x45
.long 75 # 0x4b
.long 51 # 0x33
.long 32 # 0x20
.long 40 # 0x28
.long 47 # 0x2f
.long 53 # 0x35
.long 36 # 0x24
.long 35 # 0x23
.long 58 # 0x3a
.long 59 # 0x3b
.long 50 # 0x32
.long 25 # 0x19
.long 20 # 0x14
.long 14 # 0xe
.long 12 # 0xc
.long 20 # 0x14
.long 5 # 0x5
.long 29 # 0x1d
.long 27 # 0x1b
.long 8 # 0x8
.long 7 # 0x7
.size .L__const.main.data_y, 120
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\niteration %d prev cluster:\n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\niteration %d new cluster:\n"
.size .L.str.4, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "number of iterations is %d \n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "total time: %f\n"
.size .L.str.8, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11kMeansStep2PiPfS0_S_ii"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11kMeansStep1PfS_S_Piiii"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\ninitial clusters:"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nFinished!!"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Final clusters:"
.size .Lstr.2, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kMeansStep2PiPfS0_S_ii
.addrsig_sym _Z26__device_stub__kMeansStep1PfS_S_Piiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kMeansStep2PiPfS0_S_ii
.addrsig_sym _Z11kMeansStep1PfS_S_Piiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016415f_00000000-6_kmeans_v2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii
.type _Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii, @function
_Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11kMeansStep2PiPfS0_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii, .-_Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii
.globl _Z11kMeansStep2PiPfS0_S_ii
.type _Z11kMeansStep2PiPfS0_S_ii, @function
_Z11kMeansStep2PiPfS0_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11kMeansStep2PiPfS0_S_ii, .-_Z11kMeansStep2PiPfS0_S_ii
.globl _Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii
.type _Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii, @function
_Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11kMeansStep1PfS_S_Piiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii, .-_Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii
.globl _Z11kMeansStep1PfS_S_Piiii
.type _Z11kMeansStep1PfS_S_Piiii, @function
_Z11kMeansStep1PfS_S_Piiii:
.LFB2085:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z11kMeansStep1PfS_S_Piiii, .-_Z11kMeansStep1PfS_S_Piiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%f "
.LC1:
.string "\n"
.LC2:
.string "\ninitial clusters:\n"
.LC5:
.string "\niteration %d prev cluster:\n"
.LC6:
.string "\niteration %d new cluster:\n"
.LC7:
.string "\nFinished!!\n"
.LC8:
.string "Final clusters:\n"
.LC9:
.string "number of iterations is %d \n"
.LC11:
.string "total time: %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $360, %rsp
.cfi_def_cfa_offset 416
movq %fs:40, %rax
movq %rax, 344(%rsp)
xorl %eax, %eax
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl $4, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $240, %edi
call malloc@PLT
movq %rax, %r15
movl $32, %edi
call malloc@PLT
movq %rax, %rbp
movl $25, 96(%rsp)
movl $34, 100(%rsp)
movl $22, 104(%rsp)
movl $27, 108(%rsp)
movl $33, 112(%rsp)
movl $33, 116(%rsp)
movl $31, 120(%rsp)
movl $22, 124(%rsp)
movl $35, 128(%rsp)
movl $34, 132(%rsp)
movl $67, 136(%rsp)
movl $54, 140(%rsp)
movl $57, 144(%rsp)
movl $43, 148(%rsp)
movl $50, 152(%rsp)
movl $57, 156(%rsp)
movl $59, 160(%rsp)
movl $52, 164(%rsp)
movl $65, 168(%rsp)
movl $47, 172(%rsp)
movl $49, 176(%rsp)
movl $48, 180(%rsp)
movl $35, 184(%rsp)
movl $33, 188(%rsp)
movl $44, 192(%rsp)
movl $45, 196(%rsp)
movl $38, 200(%rsp)
movl $43, 204(%rsp)
movl $51, 208(%rsp)
movl $46, 212(%rsp)
movl $79, 224(%rsp)
movl $51, 228(%rsp)
movl $53, 232(%rsp)
movl $78, 236(%rsp)
movl $59, 240(%rsp)
movl $74, 244(%rsp)
movl $73, 248(%rsp)
movl $57, 252(%rsp)
movl $69, 256(%rsp)
movl $75, 260(%rsp)
movl $51, 264(%rsp)
movl $32, 268(%rsp)
movl $40, 272(%rsp)
movl $47, 276(%rsp)
movl $53, 280(%rsp)
movl $36, 284(%rsp)
movl $35, 288(%rsp)
movl $58, 292(%rsp)
movl $59, 296(%rsp)
movl $50, 300(%rsp)
movl $25, 304(%rsp)
movl $20, 308(%rsp)
movl $14, 312(%rsp)
movl $12, 316(%rsp)
movl $20, 320(%rsp)
movl $5, 324(%rsp)
movl $29, 328(%rsp)
movl $27, 332(%rsp)
movl $8, 336(%rsp)
movl $7, 340(%rsp)
movq %r15, %r12
movl $0, %ebx
leaq .LC0(%rip), %r13
leaq .LC1(%rip), %r14
jmp .L23
.L20:
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
cltq
pxor %xmm0, %xmm0
cvtsi2ssl 224(%rsp,%rax,4), %xmm0
movss %xmm0, (%r12)
.L21:
pxor %xmm0, %xmm0
cvtss2sd (%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
testb $1, %bl
je .L49
.L22:
addq $4, %r12
cmpl $60, %ebx
je .L50
.L23:
testb $1, %bl
jne .L20
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
cltq
pxor %xmm0, %xmm0
cvtsi2ssl 96(%rsp,%rax,4), %xmm0
movss %xmm0, (%r12)
jmp .L21
.L49:
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L50:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L25
.L24:
addq $1, %rbx
cmpq $9, %rbx
je .L51
.L25:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC3(%rip), %xmm0
mulss .LC4(%rip), %xmm0
movss %xmm0, -4(%rbp,%rbx,4)
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $1, %bl
jne .L24
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L24
.L51:
leaq 32(%rsp), %rdi
movl $240, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $240, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $32, %edx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movq 48(%rsp), %rax
movq %rax, 8(%rsp)
movq 40(%rsp), %r15
movl $4, 72(%rsp)
movl $2, 76(%rsp)
movl $1, 80(%rsp)
call clock@PLT
movq %rax, 24(%rsp)
movl $1, %r14d
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L36
.L57:
subq $8, %rsp
.cfi_def_cfa_offset 424
pushq $2
.cfi_def_cfa_offset 432
movl $4, %r9d
movl $30, %r8d
movq 80(%rsp), %rcx
movq %r15, %rdx
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z40__device_stub__Z11kMeansStep1PfS_S_PiiiiPfS_S_Piiii
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L26
.L58:
movl $2, %r9d
movl $4, %r8d
movq 56(%rsp), %rcx
movq 8(%rsp), %rdx
movq %r15, %rsi
movq 64(%rsp), %rdi
call _Z40__device_stub__Z11kMeansStep2PiPfS0_S_iiPiPfS0_S_ii
jmp .L27
.L28:
addq $1, %rbx
cmpq $9, %rbx
je .L52
.L29:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $1, %bl
jne .L28
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L28
.L52:
movl $2, %ecx
movl $32, %edx
movq %r15, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %r14d, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
jmp .L31
.L30:
addq $1, %rbx
cmpq $9, %rbx
je .L53
.L31:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $1, %bl
jne .L30
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L30
.L53:
movl $2, %ecx
movl $4, %edx
movq 56(%rsp), %rsi
movq 16(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
cmpl $1, (%rbx)
je .L54
movq 48(%rsp), %rax
movq 8(%rsp), %rcx
cmpq %rcx, %rax
je .L55
movq %rax, 8(%rsp)
.L34:
cmpq %r15, %rax
je .L56
movq %rax, %r15
.L35:
addl $1, %r14d
cmpl $11, %r14d
je .L33
.L36:
movl $32, %edx
movl $0, %esi
movq %r15, %rdi
call cudaMemset@PLT
movl $16, %edx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaMemset@PLT
movl $30, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl 80(%rsp), %ecx
movl $0, %r9d
movl $56, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L57
.L26:
call cudaThreadSynchronize@PLT
movq 16(%rsp), %rax
movl $1, (%rax)
movl $1, %ecx
movl $4, %edx
movq %rax, %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl 80(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 72(%rsp), %rdx
movq 84(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L58
.L27:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $32, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl %r14d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
jmp .L29
.L54:
movl $2, %ecx
movl $32, %edx
movq %r15, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
.L33:
call clock@PLT
movq %rax, %r15
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC0(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L38
.L55:
movq 40(%rsp), %rdx
movq %rdx, 8(%rsp)
jmp .L34
.L56:
movq 40(%rsp), %r15
jmp .L35
.L37:
addq $1, %rbx
cmpq $9, %rbx
je .L59
.L38:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%rbx,4), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
testb $1, %bl
jne .L37
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L37
.L59:
movl %r14d, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 24(%rsp), %rax
subq %rax, %r15
pxor %xmm0, %xmm0
cvtsi2sdq %r15, %xmm0
divsd .LC10(%rip), %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 344(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $360, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z11kMeansStep1PfS_S_Piiii"
.LC13:
.string "_Z11kMeansStep2PiPfS0_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kMeansStep1PfS_S_Piiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z11kMeansStep2PiPfS0_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 805306368
.align 4
.LC4:
.long 1120403456
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kmeans_v2.hip"
.globl _Z26__device_stub__kMeansStep2PiPfS0_S_ii # -- Begin function _Z26__device_stub__kMeansStep2PiPfS0_S_ii
.p2align 4, 0x90
.type _Z26__device_stub__kMeansStep2PiPfS0_S_ii,@function
_Z26__device_stub__kMeansStep2PiPfS0_S_ii: # @_Z26__device_stub__kMeansStep2PiPfS0_S_ii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11kMeansStep2PiPfS0_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__kMeansStep2PiPfS0_S_ii, .Lfunc_end0-_Z26__device_stub__kMeansStep2PiPfS0_S_ii
.cfi_endproc
# -- End function
.globl _Z26__device_stub__kMeansStep1PfS_S_Piiii # -- Begin function _Z26__device_stub__kMeansStep1PfS_S_Piiii
.p2align 4, 0x90
.type _Z26__device_stub__kMeansStep1PfS_S_Piiii,@function
_Z26__device_stub__kMeansStep1PfS_S_Piiii: # @_Z26__device_stub__kMeansStep1PfS_S_Piiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 12(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11kMeansStep1PfS_S_Piiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z26__device_stub__kMeansStep1PfS_S_Piiii, .Lfunc_end1-_Z26__device_stub__kMeansStep1PfS_S_Piiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI2_1:
.long 0x42c80000 # float 100
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI2_2:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $216, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
xorl %r12d, %r12d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl $4, %edi
callq malloc
movq %rax, 120(%rsp) # 8-byte Spill
movl $240, %edi
callq malloc
movq %rax, %r15
movl $32, %edi
callq malloc
movq %rax, %rbx
movl $.L__const.main.data_x, %r13d
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_3: # in Loop: Header=BB2_1 Depth=1
incq %r12
cmpq $60, %r12
je .LBB2_4
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %r12d, %eax
shrl %eax
testb $1, %r12b
movl $.L__const.main.data_y, %ecx
cmoveq %r13, %rcx
xorps %xmm0, %xmm0
cvtsi2ssl (%rcx,%rax,4), %xmm0
movss %xmm0, (%r15,%r12,4)
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r12b
je .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_3
.LBB2_4:
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_5 Depth=1
incq %r12
cmpq $8, %r12
je .LBB2_8
.LBB2_5: # =>This Inner Loop Header: Depth=1
callq rand
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss .LCPI2_0(%rip), %xmm0
mulss .LCPI2_1(%rip), %xmm0
movss %xmm0, (%rbx,%r12,4)
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r12b
je .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_7
.LBB2_8:
movabsq $8589934596, %r12 # imm = 0x200000004
movabsq $4294967297, %r14 # imm = 0x100000001
leaq 136(%rsp), %rdi
movl $240, %esi
callq hipMalloc
leaq 128(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $32, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $16, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 136(%rsp), %rdi
movl $1, %ebp
movl $240, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $32, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %r13
movq 128(%rsp), %r15
callq clock
movq %rax, 200(%rsp) # 8-byte Spill
leaq 29(%r14), %rax
movq %rax, 208(%rsp) # 8-byte Spill
.p2align 4, 0x90
.LBB2_9: # =>This Loop Header: Depth=1
# Child Loop BB2_14 Depth 2
# Child Loop BB2_18 Depth 2
movl $32, %edx
movq %r15, %rdi
xorl %esi, %esi
callq hipMemset
movq 8(%rsp), %rdi
movl $16, %edx
xorl %esi, %esi
callq hipMemset
movl $56, %r8d
movq 208(%rsp), %rdi # 8-byte Reload
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movq 136(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 104(%rsp)
movq %r13, 96(%rsp)
movq %r15, 88(%rsp)
movq %rcx, 80(%rsp)
movl $30, 4(%rsp)
movl $4, (%rsp)
movl $2, 116(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 116(%rsp), %rax
movq %rax, 192(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z11kMeansStep1PfS_S_Piiii, %edi
leaq 144(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
callq hipDeviceSynchronize
movq 120(%rsp), %rsi # 8-byte Reload
movl $1, (%rsi)
movq 16(%rsp), %rdi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %r12, %r14
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12: # in Loop: Header=BB2_9 Depth=1
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 104(%rsp)
movq %r15, 96(%rsp)
movq %r13, 88(%rsp)
movq %rcx, 80(%rsp)
movl $4, 4(%rsp)
movl $2, (%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 96(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rax
movq %rax, 160(%rsp)
leaq 80(%rsp), %rax
movq %rax, 168(%rsp)
leaq 4(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z11kMeansStep2PiPfS0_S_ii, %edi
leaq 144(%rsp), %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13: # in Loop: Header=BB2_9 Depth=1
callq hipDeviceSynchronize
movl $32, %edx
movq %rbx, %rdi
movq %r13, %rsi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.3, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
jmp .LBB2_14
.p2align 4, 0x90
.LBB2_16: # in Loop: Header=BB2_14 Depth=2
incq %r12
cmpq $8, %r12
je .LBB2_17
.LBB2_14: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r12b
je .LBB2_16
# %bb.15: # in Loop: Header=BB2_14 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB2_16
.p2align 4, 0x90
.LBB2_17: # in Loop: Header=BB2_9 Depth=1
movl $32, %edx
movq %rbx, %rdi
movq %r15, %rsi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
xorl %r12d, %r12d
jmp .LBB2_18
.p2align 4, 0x90
.LBB2_20: # in Loop: Header=BB2_18 Depth=2
incq %r12
cmpq $8, %r12
je .LBB2_21
.LBB2_18: # Parent Loop BB2_9 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r12b
je .LBB2_20
# %bb.19: # in Loop: Header=BB2_18 Depth=2
movl $10, %edi
callq putchar@PLT
jmp .LBB2_20
.p2align 4, 0x90
.LBB2_21: # in Loop: Header=BB2_9 Depth=1
movq 16(%rsp), %rsi
movl $4, %edx
movq 120(%rsp), %r12 # 8-byte Reload
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
cmpl $1, (%r12)
je .LBB2_22
# %bb.23: # in Loop: Header=BB2_9 Depth=1
movq 24(%rsp), %rax
cmpq %rax, %r13
movq 128(%rsp), %rcx
movq %rax, %r13
cmoveq %rcx, %r13
cmpq %rax, %r15
cmoveq %rcx, %rax
incl %ebp
movq %rax, %r15
cmpl $11, %ebp
movq %r14, %r12
jne .LBB2_9
# %bb.24:
movl $11, %ebp
jmp .LBB2_25
.LBB2_22:
movl $32, %edx
movq %rbx, %rdi
movq %r15, %rsi
movl $2, %ecx
callq hipMemcpy
.LBB2_25: # %.loopexit
callq clock
movq %rax, %r14
movl $.Lstr.1, %edi
callq puts@PLT
movl $.Lstr.2, %edi
callq puts@PLT
xorl %r15d, %r15d
jmp .LBB2_26
.p2align 4, 0x90
.LBB2_28: # in Loop: Header=BB2_26 Depth=1
incq %r15
cmpq $8, %r15
je .LBB2_29
.LBB2_26: # =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
testb $1, %r15b
je .LBB2_28
# %bb.27: # in Loop: Header=BB2_26 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_28
.LBB2_29:
movl $.L.str.7, %edi
movl %ebp, %esi
xorl %eax, %eax
callq printf
subq 200(%rsp), %r14 # 8-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %r14, %xmm0
divsd .LCPI2_2(%rip), %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kMeansStep2PiPfS0_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11kMeansStep1PfS_S_Piiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11kMeansStep2PiPfS0_S_ii,@object # @_Z11kMeansStep2PiPfS0_S_ii
.section .rodata,"a",@progbits
.globl _Z11kMeansStep2PiPfS0_S_ii
.p2align 3, 0x0
_Z11kMeansStep2PiPfS0_S_ii:
.quad _Z26__device_stub__kMeansStep2PiPfS0_S_ii
.size _Z11kMeansStep2PiPfS0_S_ii, 8
.type _Z11kMeansStep1PfS_S_Piiii,@object # @_Z11kMeansStep1PfS_S_Piiii
.globl _Z11kMeansStep1PfS_S_Piiii
.p2align 3, 0x0
_Z11kMeansStep1PfS_S_Piiii:
.quad _Z26__device_stub__kMeansStep1PfS_S_Piiii
.size _Z11kMeansStep1PfS_S_Piiii, 8
.type .L__const.main.data_x,@object # @__const.main.data_x
.p2align 4, 0x0
.L__const.main.data_x:
.long 25 # 0x19
.long 34 # 0x22
.long 22 # 0x16
.long 27 # 0x1b
.long 33 # 0x21
.long 33 # 0x21
.long 31 # 0x1f
.long 22 # 0x16
.long 35 # 0x23
.long 34 # 0x22
.long 67 # 0x43
.long 54 # 0x36
.long 57 # 0x39
.long 43 # 0x2b
.long 50 # 0x32
.long 57 # 0x39
.long 59 # 0x3b
.long 52 # 0x34
.long 65 # 0x41
.long 47 # 0x2f
.long 49 # 0x31
.long 48 # 0x30
.long 35 # 0x23
.long 33 # 0x21
.long 44 # 0x2c
.long 45 # 0x2d
.long 38 # 0x26
.long 43 # 0x2b
.long 51 # 0x33
.long 46 # 0x2e
.size .L__const.main.data_x, 120
.type .L__const.main.data_y,@object # @__const.main.data_y
.p2align 4, 0x0
.L__const.main.data_y:
.long 79 # 0x4f
.long 51 # 0x33
.long 53 # 0x35
.long 78 # 0x4e
.long 59 # 0x3b
.long 74 # 0x4a
.long 73 # 0x49
.long 57 # 0x39
.long 69 # 0x45
.long 75 # 0x4b
.long 51 # 0x33
.long 32 # 0x20
.long 40 # 0x28
.long 47 # 0x2f
.long 53 # 0x35
.long 36 # 0x24
.long 35 # 0x23
.long 58 # 0x3a
.long 59 # 0x3b
.long 50 # 0x32
.long 25 # 0x19
.long 20 # 0x14
.long 14 # 0xe
.long 12 # 0xc
.long 20 # 0x14
.long 5 # 0x5
.long 29 # 0x1d
.long 27 # 0x1b
.long 8 # 0x8
.long 7 # 0x7
.size .L__const.main.data_y, 120
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%f "
.size .L.str, 4
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\niteration %d prev cluster:\n"
.size .L.str.3, 29
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\niteration %d new cluster:\n"
.size .L.str.4, 28
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "number of iterations is %d \n"
.size .L.str.7, 29
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "total time: %f\n"
.size .L.str.8, 16
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11kMeansStep2PiPfS0_S_ii"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z11kMeansStep1PfS_S_Piiii"
.size .L__unnamed_2, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\ninitial clusters:"
.size .Lstr, 19
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nFinished!!"
.size .Lstr.1, 12
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Final clusters:"
.size .Lstr.2, 16
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__kMeansStep2PiPfS0_S_ii
.addrsig_sym _Z26__device_stub__kMeansStep1PfS_S_Piiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11kMeansStep2PiPfS0_S_ii
.addrsig_sym _Z11kMeansStep1PfS_S_Piiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define BLOCK_SIZE 3
#define WA 3
#define HA 3
#define WB 3
#define HB WA
#define WC WB
#define HC HA
void randomInit(float * data ,int size)
{
for(int i = 0; i < size; ++i)
data[i] = i;
}
__global__ void matrixMul(float* C,float* A,float* B,int wA,int wB)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float value = 0;
for(int i = 0; i < wA; ++i)
{
float elementA = A[ty * wA + i];
float elementB = B[i * wB + tx];
value += elementA * elementB;
}
C[ty * wA + tx] = value;
}
int main(int argc ,char** argv)
{
srand(2006);
unsigned int size_A = WA * HA;
unsigned int mem_size_A =sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B =sizeof(float) * size_B;
float * h_B = (float*) malloc(mem_size_B);
randomInit(h_A, size_A);
randomInit(h_B, size_B);
printf("\n\nMatrix A\n");
for(int i = 0; i < size_A; i++)
{
printf("%f ", h_A[i]);
if(((i + 1) % WA) == 0)
printf("\n");
}
printf("\n\nMatrix B\n");
for(int i = 0; i < size_B; i++)
{
printf
("%f ", h_B[i]);
if(((i + 1) % WB) == 0)
printf("\n");
}
unsigned int size_C = WC * HC;
unsigned int mem_size_C =sizeof(float) * size_C;
float * h_C = (float *) malloc(mem_size_C);
float* d_A;
float* d_B;
cudaMalloc((void**) &d_A, mem_size_A);
cudaMalloc((void**) &d_B, mem_size_B);
cudaMemcpy(d_A, h_A,mem_size_A ,cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B,mem_size_B ,cudaMemcpyHostToDevice);
float* d_C;
cudaMalloc((void**) &d_C, mem_size_C);
dim3 threads(BLOCK_SIZE , BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
matrixMul<<< grid , threads >>>(d_C, d_A,d_B, WA, WB);
cudaMemcpy(h_C, d_C, mem_size_C ,cudaMemcpyDeviceToHost);
printf("\n\n Matrix C ( Results ) \n ");
for(int i = 0;i<size_C; i ++){
printf("%f",h_C[i]);
if(((i+ 1) % WC) == 0)
printf("\n");
}
printf("\n");
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} | code for sm_80
Function : _Z9matrixMulPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R2, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a24 */
/* 0x001fd800078e02ff */
/*0080*/ @!P0 BRA 0xbd0 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R4.reuse, -0x1, RZ ; /* 0xffffffff04037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*00e0*/ @!P0 BRA 0xac0 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ HFMA2.MMA R29, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1d7435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0130*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*0140*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE R28, R0, R29, c[0x0][0x170] ; /* 0x00005c00001c7625 */
/* 0x002fcc00078e021d */
/*0160*/ @!P0 BRA 0x920 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x650 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01c0*/ LDG.E R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*01e0*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x000fca00078e020c */
/*01f0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ MOV R8, c[0x0][0x17c] ; /* 0x00005f0000087a02 */
/* 0x000fc60000000f00 */
/*0210*/ LDG.E R16, [R12.64+0x4] ; /* 0x000004040c107981 */
/* 0x000ee4000c1e1900 */
/*0220*/ IMAD.WIDE R6, R8.reuse, 0x4, R28 ; /* 0x0000000408067825 */
/* 0x040fe400078e021c */
/*0230*/ LDG.E R10, [R12.64+0xc] ; /* 0x00000c040c0a7981 */
/* 0x000f28000c1e1900 */
/*0240*/ IMAD.WIDE R18, R8.reuse, 0x4, R6 ; /* 0x0000000408127825 */
/* 0x040fe200078e0206 */
/*0250*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x0002e8000c1e1900 */
/*0260*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x000f62000c1e1900 */
/*0270*/ IMAD.WIDE R24, R8, 0x4, R18 ; /* 0x0000000408187825 */
/* 0x000fc600078e0212 */
/*0280*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000326000c1e1900 */
/*0290*/ IMAD.WIDE R28, R8.reuse, 0x4, R24 ; /* 0x00000004081c7825 */
/* 0x041fe200078e0218 */
/*02a0*/ LDG.E R21, [R24.64] ; /* 0x0000000418157981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R7, [R28.64] ; /* 0x000000041c077981 */
/* 0x002368000c1e1900 */
/*02c0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x000f22000c1e1900 */
/*02d0*/ IMAD.WIDE R22, R8, 0x4, R28 ; /* 0x0000000408167825 */
/* 0x000fc600078e021c */
/*02e0*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000f62000c1e1900 */
/*0310*/ IMAD.WIDE R22, R8, 0x4, R22 ; /* 0x0000000408167825 */
/* 0x001fca00078e0216 */
/*0320*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x000162000c1e1900 */
/*0330*/ IMAD.WIDE R24, R8, 0x4, R22 ; /* 0x0000000408187825 */
/* 0x000fca00078e0216 */
/*0340*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x002362000c1e1900 */
/*0350*/ FFMA R29, R14, R15, R27 ; /* 0x0000000f0e1d7223 */
/* 0x004fc6000000001b */
/*0360*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE R14, R8, 0x4, R24 ; /* 0x00000004080e7825 */
/* 0x000fc800078e0218 */
/*0380*/ FFMA R29, R17, R16, R29 ; /* 0x00000010111d7223 */
/* 0x008fe4000000001d */
/*0390*/ IMAD.WIDE R16, R8, 0x4, R14 ; /* 0x0000000408107825 */
/* 0x000fe400078e020e */
/*03a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a8000c1e1900 */
/*03b0*/ LDG.E R15, [R12.64+0x28] ; /* 0x000028040c0f7981 */
/* 0x008ee2000c1e1900 */
/*03c0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03d0*/ IMAD.WIDE R18, R8, 0x4, R16 ; /* 0x0000000408127825 */
/* 0x000fc400078e0210 */
/*03e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008e4000c1e1900 */
/*03f0*/ FFMA R10, R21, R10, R29 ; /* 0x0000000a150a7223 */
/* 0x000fe4000000001d */
/*0400*/ IMAD.WIDE R22, R8.reuse, 0x4, R18 ; /* 0x0000000408167825 */
/* 0x041fe200078e0212 */
/*0410*/ LDG.E R21, [R12.64+0x20] ; /* 0x000020040c157981 */
/* 0x000ee8000c1e1900 */
/*0420*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ee2000c1e1900 */
/*0430*/ IMAD.WIDE R24, R8, 0x4, R22 ; /* 0x0000000408187825 */
/* 0x002fc600078e0216 */
/*0440*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R7, R7, R26, R10 ; /* 0x0000001a07077223 */
/* 0x020fc6000000000a */
/*0460*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000362000c1e1900 */
/*0470*/ FFMA R11, R6, R11, R7 ; /* 0x0000000b060b7223 */
/* 0x000fe40000000007 */
/*0480*/ IMAD.WIDE R6, R8, 0x4, R24 ; /* 0x0000000408067825 */
/* 0x000fe200078e0218 */
/*0490*/ LDG.E R17, [R24.64] ; /* 0x0000000418117981 */
/* 0x010968000c1e1900 */
/*04a0*/ LDG.E R19, [R12.64+0x2c] ; /* 0x00002c040c137981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R22, R9, R20, R11 ; /* 0x0000001409167223 */
/* 0x002fc6000000000b */
/*04c0*/ LDG.E R20, [R12.64+0x30] ; /* 0x000030040c147981 */
/* 0x000f62000c1e1900 */
/*04d0*/ IMAD.WIDE R10, R8, 0x4, R6 ; /* 0x00000004080a7825 */
/* 0x000fc600078e0206 */
/*04e0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000168000c1e1900 */
/*04f0*/ LDG.E R25, [R12.64+0x3c] ; /* 0x00003c040c197981 */
/* 0x010f28000c1e1900 */
/*0500*/ LDG.E R6, [R12.64+0x34] ; /* 0x000034040c067981 */
/* 0x001f22000c1e1900 */
/*0510*/ FFMA R7, R28, R27, R22 ; /* 0x0000001b1c077223 */
/* 0x004fe40000000016 */
/*0520*/ IMAD.WIDE R22, R8, 0x4, R10 ; /* 0x0000000408167825 */
/* 0x000fe200078e020a */
/*0530*/ LDG.E R28, [R12.64+0x38] ; /* 0x000038040c1c7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*0570*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0580*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0590*/ FFMA R14, R14, R21, R7 ; /* 0x000000150e0e7223 */
/* 0x008fc80000000007 */
/*05a0*/ FFMA R14, R16, R29, R14 ; /* 0x0000001d100e7223 */
/* 0x000fc8000000000e */
/*05b0*/ FFMA R14, R18, R15, R14 ; /* 0x0000000f120e7223 */
/* 0x000fc8000000000e */
/*05c0*/ FFMA R14, R26, R19, R14 ; /* 0x000000131a0e7223 */
/* 0x020fc8000000000e */
/*05d0*/ FFMA R14, R17, R20, R14 ; /* 0x00000014110e7223 */
/* 0x000fe2000000000e */
/*05e0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0600*/ FFMA R6, R9, R6, R14 ; /* 0x0000000609067223 */
/* 0x010fc8000000000e */
/*0610*/ FFMA R27, R27, R28, R6 ; /* 0x0000001c1b1b7223 */
/* 0x004fe40000000006 */
/*0620*/ IMAD.WIDE R28, R8, 0x4, R22 ; /* 0x00000004081c7825 */
/* 0x000fc800078e0216 */
/*0630*/ FFMA R27, R24, R25, R27 ; /* 0x00000019181b7223 */
/* 0x000fe2000000001b */
/*0640*/ @P1 BRA 0x1b0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0650*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0660*/ @!P1 BRA 0x900 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*0670*/ MOV R19, c[0x0][0x17c] ; /* 0x00005f0000137a02 */
/* 0x000fe20000000f00 */
/*0680*/ LDG.E R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x0000a2000c1e1900 */
/*0690*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe40008000f00 */
/*06a0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*06b0*/ IMAD.WIDE R14, R19, 0x4, R28 ; /* 0x00000004130e7825 */
/* 0x000fc800078e021c */
/*06c0*/ IMAD.WIDE R6, R2, 0x4, R6 ; /* 0x0000000402067825 */
/* 0x000fe200078e0206 */
/*06d0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x0002e6000c1e1900 */
/*06e0*/ IMAD.WIDE R10, R19.reuse, 0x4, R14 ; /* 0x00000004130a7825 */
/* 0x040fe200078e020e */
/*06f0*/ LDG.E R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R22, [R6.64+0x4] ; /* 0x0000040406167981 */
/* 0x000ee2000c1e1900 */
/*0710*/ IMAD.WIDE R12, R19, 0x4, R10 ; /* 0x00000004130c7825 */
/* 0x000fc600078e020a */
/*0720*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x000966000c1e1900 */
/*0730*/ IMAD.WIDE R8, R19.reuse, 0x4, R12 ; /* 0x0000000413087825 */
/* 0x040fe200078e020c */
/*0740*/ LDG.E R24, [R6.64+0x8] ; /* 0x0000080406187981 */
/* 0x000f68000c1e1900 */
/*0750*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000162000c1e1900 */
/*0760*/ IMAD.WIDE R14, R19, 0x4, R8 ; /* 0x00000004130e7825 */
/* 0x002fc600078e0208 */
/*0770*/ LDG.E R25, [R6.64+0xc] ; /* 0x00000c0406197981 */
/* 0x000f66000c1e1900 */
/*0780*/ IMAD.WIDE R16, R19.reuse, 0x4, R14 ; /* 0x0000000413107825 */
/* 0x040fe200078e020e */
/*0790*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000368000c1e1900 */
/*07a0*/ LDG.E R29, [R6.64+0x10] ; /* 0x00001004061d7981 */
/* 0x001f62000c1e1900 */
/*07b0*/ IMAD.WIDE R10, R19, 0x4, R16 ; /* 0x00000004130a7825 */
/* 0x010fc600078e0210 */
/*07c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*07d0*/ LDG.E R28, [R6.64+0x14] ; /* 0x00001404061c7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000128000c1e1900 */
/*07f0*/ LDG.E R9, [R6.64+0x18] ; /* 0x0000180406097981 */
/* 0x002f28000c1e1900 */
/*0800*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R16, [R6.64+0x1c] ; /* 0x00001c0406107981 */
/* 0x001f22000c1e1900 */
/*0820*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0830*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0840*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0850*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0860*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0870*/ FFMA R18, R18, R20, R27 ; /* 0x0000001412127223 */
/* 0x004fc8000000001b */
/*0880*/ FFMA R18, R21, R22, R18 ; /* 0x0000001615127223 */
/* 0x008fc80000000012 */
/*0890*/ FFMA R18, R23, R24, R18 ; /* 0x0000001817127223 */
/* 0x020fc80000000012 */
/*08a0*/ FFMA R12, R12, R25, R18 ; /* 0x000000190c0c7223 */
/* 0x000fc80000000012 */
/*08b0*/ FFMA R29, R8, R29, R12 ; /* 0x0000001d081d7223 */
/* 0x000fc8000000000c */
/*08c0*/ FFMA R14, R14, R28, R29 ; /* 0x0000001c0e0e7223 */
/* 0x010fe4000000001d */
/*08d0*/ IMAD.WIDE R28, R19, 0x4, R10 ; /* 0x00000004131c7825 */
/* 0x000fc800078e020a */
/*08e0*/ FFMA R9, R26, R9, R14 ; /* 0x000000091a097223 */
/* 0x000fc8000000000e */
/*08f0*/ FFMA R27, R13, R16, R9 ; /* 0x000000100d1b7223 */
/* 0x000fe40000000009 */
/*0900*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0910*/ @!P0 BRA 0xac0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0920*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe40008000f00 */
/*0930*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe40008000f00 */
/*0940*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fc60000000f00 */
/*0950*/ IMAD.WIDE R6, R2, 0x4, R6 ; /* 0x0000000402067825 */
/* 0x000fc800078e0206 */
/*0960*/ IMAD.WIDE R14, R13.reuse, 0x4, R28 ; /* 0x000000040d0e7825 */
/* 0x040fe200078e021c */
/*0970*/ LDG.E R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea8000c1e1900 */
/*0980*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IMAD.WIDE R10, R13, 0x4, R14 ; /* 0x000000040d0a7825 */
/* 0x000fc600078e020e */
/*09a0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee8000c1e1900 */
/*09b0*/ LDG.E R16, [R6.64+0x4] ; /* 0x0000040406107981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R8, R13, 0x4, R10 ; /* 0x000000040d087825 */
/* 0x000fc600078e020a */
/*09d0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R18, [R6.64+0x8] ; /* 0x0000080406127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0406147981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ FFMA R12, R28, R12, R27 ; /* 0x0000000c1c0c7223 */
/* 0x004fc8000000001b */
/*0a70*/ FFMA R12, R15, R16, R12 ; /* 0x000000100f0c7223 */
/* 0x008fe4000000000c */
/*0a80*/ IMAD.WIDE R28, R13, 0x4, R8 ; /* 0x000000040d1c7825 */
/* 0x000fc800078e0208 */
/*0a90*/ FFMA R12, R17, R18, R12 ; /* 0x00000012110c7223 */
/* 0x010fc8000000000c */
/*0aa0*/ FFMA R27, R19, R20, R12 ; /* 0x00000014131b7223 */
/* 0x020fe2000000000c */
/*0ab0*/ @P0 BRA 0x920 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbd0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R2, R3, RZ ; /* 0x0000000302067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x002fd000078e0200 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fca00078e0208 */
/*0b30*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a8000c1e1900 */
/*0b40*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0002a2000c1e1900 */
/*0b50*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0b60*/ MOV R5, c[0x0][0x17c] ; /* 0x00005f0000057a02 */
/* 0x000fe40000000f00 */
/*0b70*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0b80*/ IMAD.WIDE R8, R5, 0x4, R8 ; /* 0x0000000405087825 */
/* 0x001fe200078e0208 */
/*0b90*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0ba0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bb0*/ FFMA R27, R10, R3, R27 ; /* 0x000000030a1b7223 */
/* 0x004fc8000000001b */
/*0bc0*/ @P0 BRA 0xb30 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bd0*/ IADD3 R2, R2, R0, RZ ; /* 0x0000000002027210 */
/* 0x002fe40007ffe0ff */
/*0be0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0bf0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0c00*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x000fe2000c101904 */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ BRA 0xc20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define BLOCK_SIZE 3
#define WA 3
#define HA 3
#define WB 3
#define HB WA
#define WC WB
#define HC HA
void randomInit(float * data ,int size)
{
for(int i = 0; i < size; ++i)
data[i] = i;
}
__global__ void matrixMul(float* C,float* A,float* B,int wA,int wB)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float value = 0;
for(int i = 0; i < wA; ++i)
{
float elementA = A[ty * wA + i];
float elementB = B[i * wB + tx];
value += elementA * elementB;
}
C[ty * wA + tx] = value;
}
int main(int argc ,char** argv)
{
srand(2006);
unsigned int size_A = WA * HA;
unsigned int mem_size_A =sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B =sizeof(float) * size_B;
float * h_B = (float*) malloc(mem_size_B);
randomInit(h_A, size_A);
randomInit(h_B, size_B);
printf("\n\nMatrix A\n");
for(int i = 0; i < size_A; i++)
{
printf("%f ", h_A[i]);
if(((i + 1) % WA) == 0)
printf("\n");
}
printf("\n\nMatrix B\n");
for(int i = 0; i < size_B; i++)
{
printf
("%f ", h_B[i]);
if(((i + 1) % WB) == 0)
printf("\n");
}
unsigned int size_C = WC * HC;
unsigned int mem_size_C =sizeof(float) * size_C;
float * h_C = (float *) malloc(mem_size_C);
float* d_A;
float* d_B;
cudaMalloc((void**) &d_A, mem_size_A);
cudaMalloc((void**) &d_B, mem_size_B);
cudaMemcpy(d_A, h_A,mem_size_A ,cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B,mem_size_B ,cudaMemcpyHostToDevice);
float* d_C;
cudaMalloc((void**) &d_C, mem_size_C);
dim3 threads(BLOCK_SIZE , BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
matrixMul<<< grid , threads >>>(d_C, d_A,d_B, WA, WB);
cudaMemcpy(h_C, d_C, mem_size_C ,cudaMemcpyDeviceToHost);
printf("\n\n Matrix C ( Results ) \n ");
for(int i = 0;i<size_C; i ++){
printf("%f",h_C[i]);
if(((i+ 1) % WC) == 0)
printf("\n");
}
printf("\n");
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} | .file "tmpxft_0017597d_00000000-6_cuda_p4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.globl _Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii
.type _Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii, @function
_Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixMulPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii, .-_Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii
.globl _Z9matrixMulPfS_S_ii
.type _Z9matrixMulPfS_S_ii, @function
_Z9matrixMulPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9matrixMulPfS_S_ii, .-_Z9matrixMulPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n\nMatrix A\n"
.LC1:
.string "%f "
.LC2:
.string "\n"
.LC3:
.string "\n\nMatrix B\n"
.LC4:
.string "\n\n Matrix C ( Results ) \n "
.LC5:
.string "%f"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $2006, %edi
call srand@PLT
movl $36, %edi
call malloc@PLT
movq %rax, %r12
movl $36, %edi
call malloc@PLT
movq %rax, %rbp
movl $9, %esi
movq %r12, %rdi
call _Z10randomInitPfi
movl $9, %esi
movq %rbp, %rdi
call _Z10randomInitPfi
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r14
jmp .L17
.L16:
addq $1, %rbx
cmpq $10, %rbx
je .L28
.L17:
pxor %xmm0, %xmm0
cvtss2sd -4(%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
cmpl %ebx, %eax
jne .L16
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L28:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r14
jmp .L19
.L18:
addq $1, %rbx
cmpq $10, %rbx
je .L29
.L19:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
cmpl %ebx, %eax
jne .L18
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L29:
movl $36, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $36, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $36, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $3, 32(%rsp)
movl $3, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L20:
movl $2, %ecx
movl $36, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC5(%rip), %r14
leaq .LC2(%rip), %r15
jmp .L22
.L30:
movl $3, %r8d
movl $3, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii
jmp .L20
.L32:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
addq $1, %rbx
cmpq $10, %rbx
je .L31
.L22:
pxor %xmm0, %xmm0
cvtss2sd -4(%r13,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
cmpl %ebx, %eax
jne .L21
jmp .L32
.L31:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9matrixMulPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define BLOCK_SIZE 3
#define WA 3
#define HA 3
#define WB 3
#define HB WA
#define WC WB
#define HC HA
void randomInit(float * data ,int size)
{
for(int i = 0; i < size; ++i)
data[i] = i;
}
__global__ void matrixMul(float* C,float* A,float* B,int wA,int wB)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float value = 0;
for(int i = 0; i < wA; ++i)
{
float elementA = A[ty * wA + i];
float elementB = B[i * wB + tx];
value += elementA * elementB;
}
C[ty * wA + tx] = value;
}
int main(int argc ,char** argv)
{
srand(2006);
unsigned int size_A = WA * HA;
unsigned int mem_size_A =sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B =sizeof(float) * size_B;
float * h_B = (float*) malloc(mem_size_B);
randomInit(h_A, size_A);
randomInit(h_B, size_B);
printf("\n\nMatrix A\n");
for(int i = 0; i < size_A; i++)
{
printf("%f ", h_A[i]);
if(((i + 1) % WA) == 0)
printf("\n");
}
printf("\n\nMatrix B\n");
for(int i = 0; i < size_B; i++)
{
printf
("%f ", h_B[i]);
if(((i + 1) % WB) == 0)
printf("\n");
}
unsigned int size_C = WC * HC;
unsigned int mem_size_C =sizeof(float) * size_C;
float * h_C = (float *) malloc(mem_size_C);
float* d_A;
float* d_B;
cudaMalloc((void**) &d_A, mem_size_A);
cudaMalloc((void**) &d_B, mem_size_B);
cudaMemcpy(d_A, h_A,mem_size_A ,cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_B,mem_size_B ,cudaMemcpyHostToDevice);
float* d_C;
cudaMalloc((void**) &d_C, mem_size_C);
dim3 threads(BLOCK_SIZE , BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
matrixMul<<< grid , threads >>>(d_C, d_A,d_B, WA, WB);
cudaMemcpy(h_C, d_C, mem_size_C ,cudaMemcpyDeviceToHost);
printf("\n\n Matrix C ( Results ) \n ");
for(int i = 0;i<size_C; i ++){
printf("%f",h_C[i]);
if(((i+ 1) % WC) == 0)
printf("\n");
}
printf("\n");
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define BLOCK_SIZE 3
#define WA 3
#define HA 3
#define WB 3
#define HB WA
#define WC WB
#define HC HA
void randomInit(float * data ,int size)
{
for(int i = 0; i < size; ++i)
data[i] = i;
}
__global__ void matrixMul(float* C,float* A,float* B,int wA,int wB)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float value = 0;
for(int i = 0; i < wA; ++i)
{
float elementA = A[ty * wA + i];
float elementB = B[i * wB + tx];
value += elementA * elementB;
}
C[ty * wA + tx] = value;
}
int main(int argc ,char** argv)
{
srand(2006);
unsigned int size_A = WA * HA;
unsigned int mem_size_A =sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B =sizeof(float) * size_B;
float * h_B = (float*) malloc(mem_size_B);
randomInit(h_A, size_A);
randomInit(h_B, size_B);
printf("\n\nMatrix A\n");
for(int i = 0; i < size_A; i++)
{
printf("%f ", h_A[i]);
if(((i + 1) % WA) == 0)
printf("\n");
}
printf("\n\nMatrix B\n");
for(int i = 0; i < size_B; i++)
{
printf
("%f ", h_B[i]);
if(((i + 1) % WB) == 0)
printf("\n");
}
unsigned int size_C = WC * HC;
unsigned int mem_size_C =sizeof(float) * size_C;
float * h_C = (float *) malloc(mem_size_C);
float* d_A;
float* d_B;
hipMalloc((void**) &d_A, mem_size_A);
hipMalloc((void**) &d_B, mem_size_B);
hipMemcpy(d_A, h_A,mem_size_A ,hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B,mem_size_B ,hipMemcpyHostToDevice);
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
dim3 threads(BLOCK_SIZE , BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
matrixMul<<< grid , threads >>>(d_C, d_A,d_B, WA, WB);
hipMemcpy(h_C, d_C, mem_size_C ,hipMemcpyDeviceToHost);
printf("\n\n Matrix C ( Results ) \n ");
for(int i = 0;i<size_C; i ++){
printf("%f",h_C[i]);
if(((i+ 1) % WC) == 0)
printf("\n");
}
printf("\n");
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define BLOCK_SIZE 3
#define WA 3
#define HA 3
#define WB 3
#define HB WA
#define WC WB
#define HC HA
void randomInit(float * data ,int size)
{
for(int i = 0; i < size; ++i)
data[i] = i;
}
__global__ void matrixMul(float* C,float* A,float* B,int wA,int wB)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float value = 0;
for(int i = 0; i < wA; ++i)
{
float elementA = A[ty * wA + i];
float elementB = B[i * wB + tx];
value += elementA * elementB;
}
C[ty * wA + tx] = value;
}
int main(int argc ,char** argv)
{
srand(2006);
unsigned int size_A = WA * HA;
unsigned int mem_size_A =sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B =sizeof(float) * size_B;
float * h_B = (float*) malloc(mem_size_B);
randomInit(h_A, size_A);
randomInit(h_B, size_B);
printf("\n\nMatrix A\n");
for(int i = 0; i < size_A; i++)
{
printf("%f ", h_A[i]);
if(((i + 1) % WA) == 0)
printf("\n");
}
printf("\n\nMatrix B\n");
for(int i = 0; i < size_B; i++)
{
printf
("%f ", h_B[i]);
if(((i + 1) % WB) == 0)
printf("\n");
}
unsigned int size_C = WC * HC;
unsigned int mem_size_C =sizeof(float) * size_C;
float * h_C = (float *) malloc(mem_size_C);
float* d_A;
float* d_B;
hipMalloc((void**) &d_A, mem_size_A);
hipMalloc((void**) &d_B, mem_size_B);
hipMemcpy(d_A, h_A,mem_size_A ,hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B,mem_size_B ,hipMemcpyHostToDevice);
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
dim3 threads(BLOCK_SIZE , BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
matrixMul<<< grid , threads >>>(d_C, d_A,d_B, WA, WB);
hipMemcpy(h_C, d_C, mem_size_C ,hipMemcpyDeviceToHost);
printf("\n\n Matrix C ( Results ) \n ");
for(int i = 0;i<size_C; i ++){
printf("%f",h_C[i]);
if(((i+ 1) % WC) == 0)
printf("\n");
}
printf("\n");
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPfS_S_ii
.globl _Z9matrixMulPfS_S_ii
.p2align 8
.type _Z9matrixMulPfS_S_ii,@function
_Z9matrixMulPfS_S_ii:
s_load_b32 s4, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[8:11], s[0:1], 0x8
v_mul_lo_u32 v2, v0, s4
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v6, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
v_add_co_u32 v2, s5, s10, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e64 v3, null, s11, 0, s5
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_mov_b32_e32 v6, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_mov_b32 s5, s4
.LBB0_2:
global_load_b32 v7, v[4:5], off
global_load_b32 v8, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v7, v8
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPfS_S_ii, .Lfunc_end0-_Z9matrixMulPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <math.h>
#define BLOCK_SIZE 3
#define WA 3
#define HA 3
#define WB 3
#define HB WA
#define WC WB
#define HC HA
void randomInit(float * data ,int size)
{
for(int i = 0; i < size; ++i)
data[i] = i;
}
__global__ void matrixMul(float* C,float* A,float* B,int wA,int wB)
{
int tx = threadIdx.x;
int ty = threadIdx.y;
float value = 0;
for(int i = 0; i < wA; ++i)
{
float elementA = A[ty * wA + i];
float elementB = B[i * wB + tx];
value += elementA * elementB;
}
C[ty * wA + tx] = value;
}
int main(int argc ,char** argv)
{
srand(2006);
unsigned int size_A = WA * HA;
unsigned int mem_size_A =sizeof(float) * size_A;
float* h_A = (float*) malloc(mem_size_A);
unsigned int size_B = WB * HB;
unsigned int mem_size_B =sizeof(float) * size_B;
float * h_B = (float*) malloc(mem_size_B);
randomInit(h_A, size_A);
randomInit(h_B, size_B);
printf("\n\nMatrix A\n");
for(int i = 0; i < size_A; i++)
{
printf("%f ", h_A[i]);
if(((i + 1) % WA) == 0)
printf("\n");
}
printf("\n\nMatrix B\n");
for(int i = 0; i < size_B; i++)
{
printf
("%f ", h_B[i]);
if(((i + 1) % WB) == 0)
printf("\n");
}
unsigned int size_C = WC * HC;
unsigned int mem_size_C =sizeof(float) * size_C;
float * h_C = (float *) malloc(mem_size_C);
float* d_A;
float* d_B;
hipMalloc((void**) &d_A, mem_size_A);
hipMalloc((void**) &d_B, mem_size_B);
hipMemcpy(d_A, h_A,mem_size_A ,hipMemcpyHostToDevice);
hipMemcpy(d_B, h_B,mem_size_B ,hipMemcpyHostToDevice);
float* d_C;
hipMalloc((void**) &d_C, mem_size_C);
dim3 threads(BLOCK_SIZE , BLOCK_SIZE);
dim3 grid(WC / threads.x, HC / threads.y);
matrixMul<<< grid , threads >>>(d_C, d_A,d_B, WA, WB);
hipMemcpy(h_C, d_C, mem_size_C ,hipMemcpyDeviceToHost);
printf("\n\n Matrix C ( Results ) \n ");
for(int i = 0;i<size_C; i ++){
printf("%f",h_C[i]);
if(((i+ 1) % WC) == 0)
printf("\n");
}
printf("\n");
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
free(h_A);
free(h_B);
free(h_C);
} | .text
.file "cuda_p4.hip"
.globl _Z10randomInitPfi # -- Begin function _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10randomInitPfi, .Lfunc_end0-_Z10randomInitPfi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__matrixMulPfS_S_ii # -- Begin function _Z24__device_stub__matrixMulPfS_S_ii
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPfS_S_ii,@function
_Z24__device_stub__matrixMulPfS_S_ii: # @_Z24__device_stub__matrixMulPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixMulPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__matrixMulPfS_S_ii, .Lfunc_end1-_Z24__device_stub__matrixMulPfS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $2006, %edi # imm = 0x7D6
callq srand
movl $36, %edi
callq malloc
movq %rax, %rbx
movl $36, %edi
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $9, %rax
jne .LBB2_1
# %bb.2: # %.lr.ph.i52.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i52
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $9, %rax
jne .LBB2_3
# %bb.4: # %_Z10randomInitPfi.exit56
movl $.Lstr, %edi
callq puts@PLT
movl $1, %r15d
xorl %r12d, %r12d
movabsq $-6148914691236517205, %r13 # imm = 0xAAAAAAAAAAAAAAAB
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_5 Depth=1
incq %r12
incq %r15
cmpq $9, %r12
je .LBB2_8
.LBB2_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rax
mulq %r13
shrq %rdx
leal (%rdx,%rdx,2), %ebp
decl %ebp
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
cmpl %r12d, %ebp
jne .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_7
.LBB2_8:
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %r15d
xorl %r12d, %r12d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
incq %r12
incq %r15
cmpq $9, %r12
je .LBB2_12
.LBB2_9: # =>This Inner Loop Header: Depth=1
movq %r15, %rax
mulq %r13
shrq %rdx
leal (%rdx,%rdx,2), %ebp
decl %ebp
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
cmpl %r12d, %ebp
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_11
.LBB2_12:
movl $36, %edi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $36, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $36, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $12884901891, %rdx # imm = 0x300000003
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $3, 36(%rsp)
movl $3, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9matrixMulPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
movq 8(%rsp), %rsi
movl $36, %edx
movq %r15, %r13
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %ebp, %ebp
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $1, %r12d
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_17: # in Loop: Header=BB2_15 Depth=1
incq %rbp
incq %r12
cmpq $9, %rbp
je .LBB2_18
.LBB2_15: # =>This Inner Loop Header: Depth=1
movq %r12, %rax
movabsq $-6148914691236517205, %rcx # imm = 0xAAAAAAAAAAAAAAAB
mulq %rcx
shrq %rdx
leal (%rdx,%rdx,2), %r15d
decl %r15d
movss (%r13,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
cmpl %ebp, %r15d
jne .LBB2_17
# %bb.16: # in Loop: Header=BB2_15 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_17
.LBB2_18:
movl $10, %edi
callq putchar@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPfS_S_ii,@object # @_Z9matrixMulPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z9matrixMulPfS_S_ii
.p2align 3, 0x0
_Z9matrixMulPfS_S_ii:
.quad _Z24__device_stub__matrixMulPfS_S_ii
.size _Z9matrixMulPfS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n\n Matrix C ( Results ) \n "
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f"
.size .L.str.5, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPfS_S_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\nMatrix A"
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nMatrix B"
.size .Lstr.1, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixMulPfS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e220000002200 */
/*0020*/ MOV R4, c[0x0][0x178] ; /* 0x00005e0000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R27, -RZ, RZ, 0, 0 ; /* 0x00000000ff1b7435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0060*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R2, R2, c[0x0][0x178], RZ ; /* 0x00005e0002027a24 */
/* 0x001fd800078e02ff */
/*0080*/ @!P0 BRA 0xbd0 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0090*/ IADD3 R3, R4.reuse, -0x1, RZ ; /* 0xffffffff04037810 */
/* 0x040fe40007ffe0ff */
/*00a0*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*00b0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*00c0*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fe40000000f00 */
/*00d0*/ MOV R3, RZ ; /* 0x000000ff00037202 */
/* 0x000fd20000000f00 */
/*00e0*/ @!P0 BRA 0xac0 ; /* 0x000009d000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0100*/ HFMA2.MMA R29, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff1d7435 */
/* 0x000fe200000001ff */
/*0110*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0120*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0130*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f04270 */
/*0140*/ MOV R27, RZ ; /* 0x000000ff001b7202 */
/* 0x000fca0000000f00 */
/*0150*/ IMAD.WIDE R28, R0, R29, c[0x0][0x170] ; /* 0x00005c00001c7625 */
/* 0x002fcc00078e021d */
/*0160*/ @!P0 BRA 0x920 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0190*/ @!P1 BRA 0x650 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01b0*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*01c0*/ LDG.E R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x0000a2000c1e1900 */
/*01d0*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*01e0*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x000fca00078e020c */
/*01f0*/ LDG.E R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x000ea2000c1e1900 */
/*0200*/ MOV R8, c[0x0][0x17c] ; /* 0x00005f0000087a02 */
/* 0x000fc60000000f00 */
/*0210*/ LDG.E R16, [R12.64+0x4] ; /* 0x000004040c107981 */
/* 0x000ee4000c1e1900 */
/*0220*/ IMAD.WIDE R6, R8.reuse, 0x4, R28 ; /* 0x0000000408067825 */
/* 0x040fe400078e021c */
/*0230*/ LDG.E R10, [R12.64+0xc] ; /* 0x00000c040c0a7981 */
/* 0x000f28000c1e1900 */
/*0240*/ IMAD.WIDE R18, R8.reuse, 0x4, R6 ; /* 0x0000000408127825 */
/* 0x040fe200078e0206 */
/*0250*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x0002e8000c1e1900 */
/*0260*/ LDG.E R26, [R12.64+0x10] ; /* 0x000010040c1a7981 */
/* 0x000f62000c1e1900 */
/*0270*/ IMAD.WIDE R24, R8, 0x4, R18 ; /* 0x0000000408187825 */
/* 0x000fc600078e0212 */
/*0280*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000326000c1e1900 */
/*0290*/ IMAD.WIDE R28, R8.reuse, 0x4, R24 ; /* 0x00000004081c7825 */
/* 0x041fe200078e0218 */
/*02a0*/ LDG.E R21, [R24.64] ; /* 0x0000000418157981 */
/* 0x000128000c1e1900 */
/*02b0*/ LDG.E R7, [R28.64] ; /* 0x000000041c077981 */
/* 0x002368000c1e1900 */
/*02c0*/ LDG.E R19, [R12.64+0x8] ; /* 0x000008040c137981 */
/* 0x000f22000c1e1900 */
/*02d0*/ IMAD.WIDE R22, R8, 0x4, R28 ; /* 0x0000000408167825 */
/* 0x000fc600078e021c */
/*02e0*/ LDG.E R11, [R12.64+0x14] ; /* 0x000014040c0b7981 */
/* 0x000f68000c1e1900 */
/*02f0*/ LDG.E R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x000168000c1e1900 */
/*0300*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000f62000c1e1900 */
/*0310*/ IMAD.WIDE R22, R8, 0x4, R22 ; /* 0x0000000408167825 */
/* 0x001fca00078e0216 */
/*0320*/ LDG.E R9, [R22.64] ; /* 0x0000000416097981 */
/* 0x000162000c1e1900 */
/*0330*/ IMAD.WIDE R24, R8, 0x4, R22 ; /* 0x0000000408187825 */
/* 0x000fca00078e0216 */
/*0340*/ LDG.E R28, [R24.64] ; /* 0x00000004181c7981 */
/* 0x002362000c1e1900 */
/*0350*/ FFMA R29, R14, R15, R27 ; /* 0x0000000f0e1d7223 */
/* 0x004fc6000000001b */
/*0360*/ LDG.E R27, [R12.64+0x1c] ; /* 0x00001c040c1b7981 */
/* 0x000ea2000c1e1900 */
/*0370*/ IMAD.WIDE R14, R8, 0x4, R24 ; /* 0x00000004080e7825 */
/* 0x000fc800078e0218 */
/*0380*/ FFMA R29, R17, R16, R29 ; /* 0x00000010111d7223 */
/* 0x008fe4000000001d */
/*0390*/ IMAD.WIDE R16, R8, 0x4, R14 ; /* 0x0000000408107825 */
/* 0x000fe400078e020e */
/*03a0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0006a8000c1e1900 */
/*03b0*/ LDG.E R15, [R12.64+0x28] ; /* 0x000028040c0f7981 */
/* 0x008ee2000c1e1900 */
/*03c0*/ FFMA R29, R18, R19, R29 ; /* 0x00000013121d7223 */
/* 0x010fe4000000001d */
/*03d0*/ IMAD.WIDE R18, R8, 0x4, R16 ; /* 0x0000000408127825 */
/* 0x000fc400078e0210 */
/*03e0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0008e4000c1e1900 */
/*03f0*/ FFMA R10, R21, R10, R29 ; /* 0x0000000a150a7223 */
/* 0x000fe4000000001d */
/*0400*/ IMAD.WIDE R22, R8.reuse, 0x4, R18 ; /* 0x0000000408167825 */
/* 0x041fe200078e0212 */
/*0410*/ LDG.E R21, [R12.64+0x20] ; /* 0x000020040c157981 */
/* 0x000ee8000c1e1900 */
/*0420*/ LDG.E R29, [R12.64+0x24] ; /* 0x000024040c1d7981 */
/* 0x000ee2000c1e1900 */
/*0430*/ IMAD.WIDE R24, R8, 0x4, R22 ; /* 0x0000000408187825 */
/* 0x002fc600078e0216 */
/*0440*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R7, R7, R26, R10 ; /* 0x0000001a07077223 */
/* 0x020fc6000000000a */
/*0460*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000362000c1e1900 */
/*0470*/ FFMA R11, R6, R11, R7 ; /* 0x0000000b060b7223 */
/* 0x000fe40000000007 */
/*0480*/ IMAD.WIDE R6, R8, 0x4, R24 ; /* 0x0000000408067825 */
/* 0x000fe200078e0218 */
/*0490*/ LDG.E R17, [R24.64] ; /* 0x0000000418117981 */
/* 0x010968000c1e1900 */
/*04a0*/ LDG.E R19, [R12.64+0x2c] ; /* 0x00002c040c137981 */
/* 0x001f62000c1e1900 */
/*04b0*/ FFMA R22, R9, R20, R11 ; /* 0x0000001409167223 */
/* 0x002fc6000000000b */
/*04c0*/ LDG.E R20, [R12.64+0x30] ; /* 0x000030040c147981 */
/* 0x000f62000c1e1900 */
/*04d0*/ IMAD.WIDE R10, R8, 0x4, R6 ; /* 0x00000004080a7825 */
/* 0x000fc600078e0206 */
/*04e0*/ LDG.E R9, [R6.64] ; /* 0x0000000406097981 */
/* 0x000168000c1e1900 */
/*04f0*/ LDG.E R25, [R12.64+0x3c] ; /* 0x00003c040c197981 */
/* 0x010f28000c1e1900 */
/*0500*/ LDG.E R6, [R12.64+0x34] ; /* 0x000034040c067981 */
/* 0x001f22000c1e1900 */
/*0510*/ FFMA R7, R28, R27, R22 ; /* 0x0000001b1c077223 */
/* 0x004fe40000000016 */
/*0520*/ IMAD.WIDE R22, R8, 0x4, R10 ; /* 0x0000000408167825 */
/* 0x000fe200078e020a */
/*0530*/ LDG.E R28, [R12.64+0x38] ; /* 0x000038040c1c7981 */
/* 0x000ea8000c1e1900 */
/*0540*/ LDG.E R27, [R10.64] ; /* 0x000000040a1b7981 */
/* 0x000ea8000c1e1900 */
/*0550*/ LDG.E R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x000ea2000c1e1900 */
/*0560*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc80007ffe0ff */
/*0570*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe20003f24270 */
/*0580*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0590*/ FFMA R14, R14, R21, R7 ; /* 0x000000150e0e7223 */
/* 0x008fc80000000007 */
/*05a0*/ FFMA R14, R16, R29, R14 ; /* 0x0000001d100e7223 */
/* 0x000fc8000000000e */
/*05b0*/ FFMA R14, R18, R15, R14 ; /* 0x0000000f120e7223 */
/* 0x000fc8000000000e */
/*05c0*/ FFMA R14, R26, R19, R14 ; /* 0x000000131a0e7223 */
/* 0x020fc8000000000e */
/*05d0*/ FFMA R14, R17, R20, R14 ; /* 0x00000014110e7223 */
/* 0x000fe2000000000e */
/*05e0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05f0*/ IADD3 R3, R3, 0x10, RZ ; /* 0x0000001003037810 */
/* 0x000fe40007ffe0ff */
/*0600*/ FFMA R6, R9, R6, R14 ; /* 0x0000000609067223 */
/* 0x010fc8000000000e */
/*0610*/ FFMA R27, R27, R28, R6 ; /* 0x0000001c1b1b7223 */
/* 0x004fe40000000006 */
/*0620*/ IMAD.WIDE R28, R8, 0x4, R22 ; /* 0x00000004081c7825 */
/* 0x000fc800078e0216 */
/*0630*/ FFMA R27, R24, R25, R27 ; /* 0x00000019181b7223 */
/* 0x000fe2000000001b */
/*0640*/ @P1 BRA 0x1b0 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*0650*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0660*/ @!P1 BRA 0x900 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*0670*/ MOV R19, c[0x0][0x17c] ; /* 0x00005f0000137a02 */
/* 0x000fe20000000f00 */
/*0680*/ LDG.E R18, [R28.64] ; /* 0x000000041c127981 */
/* 0x0000a2000c1e1900 */
/*0690*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe40008000f00 */
/*06a0*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe20008000f00 */
/*06b0*/ IMAD.WIDE R14, R19, 0x4, R28 ; /* 0x00000004130e7825 */
/* 0x000fc800078e021c */
/*06c0*/ IMAD.WIDE R6, R2, 0x4, R6 ; /* 0x0000000402067825 */
/* 0x000fe200078e0206 */
/*06d0*/ LDG.E R21, [R14.64] ; /* 0x000000040e157981 */
/* 0x0002e6000c1e1900 */
/*06e0*/ IMAD.WIDE R10, R19.reuse, 0x4, R14 ; /* 0x00000004130a7825 */
/* 0x040fe200078e020e */
/*06f0*/ LDG.E R20, [R6.64] ; /* 0x0000000406147981 */
/* 0x000ea8000c1e1900 */
/*0700*/ LDG.E R22, [R6.64+0x4] ; /* 0x0000040406167981 */
/* 0x000ee2000c1e1900 */
/*0710*/ IMAD.WIDE R12, R19, 0x4, R10 ; /* 0x00000004130c7825 */
/* 0x000fc600078e020a */
/*0720*/ LDG.E R23, [R10.64] ; /* 0x000000040a177981 */
/* 0x000966000c1e1900 */
/*0730*/ IMAD.WIDE R8, R19.reuse, 0x4, R12 ; /* 0x0000000413087825 */
/* 0x040fe200078e020c */
/*0740*/ LDG.E R24, [R6.64+0x8] ; /* 0x0000080406187981 */
/* 0x000f68000c1e1900 */
/*0750*/ LDG.E R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000162000c1e1900 */
/*0760*/ IMAD.WIDE R14, R19, 0x4, R8 ; /* 0x00000004130e7825 */
/* 0x002fc600078e0208 */
/*0770*/ LDG.E R25, [R6.64+0xc] ; /* 0x00000c0406197981 */
/* 0x000f66000c1e1900 */
/*0780*/ IMAD.WIDE R16, R19.reuse, 0x4, R14 ; /* 0x0000000413107825 */
/* 0x040fe200078e020e */
/*0790*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000368000c1e1900 */
/*07a0*/ LDG.E R29, [R6.64+0x10] ; /* 0x00001004061d7981 */
/* 0x001f62000c1e1900 */
/*07b0*/ IMAD.WIDE R10, R19, 0x4, R16 ; /* 0x00000004130a7825 */
/* 0x010fc600078e0210 */
/*07c0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000f28000c1e1900 */
/*07d0*/ LDG.E R28, [R6.64+0x14] ; /* 0x00001404061c7981 */
/* 0x000f28000c1e1900 */
/*07e0*/ LDG.E R26, [R16.64] ; /* 0x00000004101a7981 */
/* 0x000128000c1e1900 */
/*07f0*/ LDG.E R9, [R6.64+0x18] ; /* 0x0000180406097981 */
/* 0x002f28000c1e1900 */
/*0800*/ LDG.E R13, [R10.64] ; /* 0x000000040a0d7981 */
/* 0x000f28000c1e1900 */
/*0810*/ LDG.E R16, [R6.64+0x1c] ; /* 0x00001c0406107981 */
/* 0x001f22000c1e1900 */
/*0820*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0830*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*0840*/ IADD3 R3, R3, 0x8, RZ ; /* 0x0000000803037810 */
/* 0x000fe40007ffe0ff */
/*0850*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0860*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0870*/ FFMA R18, R18, R20, R27 ; /* 0x0000001412127223 */
/* 0x004fc8000000001b */
/*0880*/ FFMA R18, R21, R22, R18 ; /* 0x0000001615127223 */
/* 0x008fc80000000012 */
/*0890*/ FFMA R18, R23, R24, R18 ; /* 0x0000001817127223 */
/* 0x020fc80000000012 */
/*08a0*/ FFMA R12, R12, R25, R18 ; /* 0x000000190c0c7223 */
/* 0x000fc80000000012 */
/*08b0*/ FFMA R29, R8, R29, R12 ; /* 0x0000001d081d7223 */
/* 0x000fc8000000000c */
/*08c0*/ FFMA R14, R14, R28, R29 ; /* 0x0000001c0e0e7223 */
/* 0x010fe4000000001d */
/*08d0*/ IMAD.WIDE R28, R19, 0x4, R10 ; /* 0x00000004131c7825 */
/* 0x000fc800078e020a */
/*08e0*/ FFMA R9, R26, R9, R14 ; /* 0x000000091a097223 */
/* 0x000fc8000000000e */
/*08f0*/ FFMA R27, R13, R16, R9 ; /* 0x000000100d1b7223 */
/* 0x000fe40000000009 */
/*0900*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0910*/ @!P0 BRA 0xac0 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0920*/ MOV R6, UR6 ; /* 0x0000000600067c02 */
/* 0x000fe40008000f00 */
/*0930*/ MOV R7, UR7 ; /* 0x0000000700077c02 */
/* 0x000fe40008000f00 */
/*0940*/ MOV R13, c[0x0][0x17c] ; /* 0x00005f00000d7a02 */
/* 0x000fc60000000f00 */
/*0950*/ IMAD.WIDE R6, R2, 0x4, R6 ; /* 0x0000000402067825 */
/* 0x000fc800078e0206 */
/*0960*/ IMAD.WIDE R14, R13.reuse, 0x4, R28 ; /* 0x000000040d0e7825 */
/* 0x040fe200078e021c */
/*0970*/ LDG.E R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea8000c1e1900 */
/*0980*/ LDG.E R28, [R28.64] ; /* 0x000000041c1c7981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IMAD.WIDE R10, R13, 0x4, R14 ; /* 0x000000040d0a7825 */
/* 0x000fc600078e020e */
/*09a0*/ LDG.E R15, [R14.64] ; /* 0x000000040e0f7981 */
/* 0x000ee8000c1e1900 */
/*09b0*/ LDG.E R16, [R6.64+0x4] ; /* 0x0000040406107981 */
/* 0x000ee2000c1e1900 */
/*09c0*/ IMAD.WIDE R8, R13, 0x4, R10 ; /* 0x000000040d087825 */
/* 0x000fc600078e020a */
/*09d0*/ LDG.E R17, [R10.64] ; /* 0x000000040a117981 */
/* 0x000f28000c1e1900 */
/*09e0*/ LDG.E R18, [R6.64+0x8] ; /* 0x0000080406127981 */
/* 0x000f28000c1e1900 */
/*09f0*/ LDG.E R20, [R6.64+0xc] ; /* 0x00000c0406147981 */
/* 0x000f68000c1e1900 */
/*0a00*/ LDG.E R19, [R8.64] ; /* 0x0000000408137981 */
/* 0x000f62000c1e1900 */
/*0a10*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a20*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0a30*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0a40*/ IADD3 R3, R3, 0x4, RZ ; /* 0x0000000403037810 */
/* 0x000fc60007ffe0ff */
/*0a50*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0a60*/ FFMA R12, R28, R12, R27 ; /* 0x0000000c1c0c7223 */
/* 0x004fc8000000001b */
/*0a70*/ FFMA R12, R15, R16, R12 ; /* 0x000000100f0c7223 */
/* 0x008fe4000000000c */
/*0a80*/ IMAD.WIDE R28, R13, 0x4, R8 ; /* 0x000000040d1c7825 */
/* 0x000fc800078e0208 */
/*0a90*/ FFMA R12, R17, R18, R12 ; /* 0x00000012110c7223 */
/* 0x010fc8000000000c */
/*0aa0*/ FFMA R27, R19, R20, R12 ; /* 0x00000014131b7223 */
/* 0x020fe2000000000c */
/*0ab0*/ @P0 BRA 0x920 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 BRA 0xbd0 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0af0*/ IADD3 R6, R2, R3, RZ ; /* 0x0000000302067210 */
/* 0x000fe20007ffe0ff */
/*0b00*/ IMAD R3, R3, c[0x0][0x17c], R0 ; /* 0x00005f0003037a24 */
/* 0x002fd000078e0200 */
/*0b10*/ IMAD.WIDE R6, R6, R8, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0208 */
/*0b20*/ IMAD.WIDE R8, R3, R8, c[0x0][0x170] ; /* 0x00005c0003087625 */
/* 0x000fca00078e0208 */
/*0b30*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x0000a8000c1e1900 */
/*0b40*/ LDG.E R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0002a2000c1e1900 */
/*0b50*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0b60*/ MOV R5, c[0x0][0x17c] ; /* 0x00005f0000057a02 */
/* 0x000fe40000000f00 */
/*0b70*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0b80*/ IMAD.WIDE R8, R5, 0x4, R8 ; /* 0x0000000405087825 */
/* 0x001fe200078e0208 */
/*0b90*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0ba0*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0bb0*/ FFMA R27, R10, R3, R27 ; /* 0x000000030a1b7223 */
/* 0x004fc8000000001b */
/*0bc0*/ @P0 BRA 0xb30 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0bd0*/ IADD3 R2, R2, R0, RZ ; /* 0x0000000002027210 */
/* 0x002fe40007ffe0ff */
/*0be0*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0bf0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0c00*/ STG.E [R2.64], R27 ; /* 0x0000001b02007986 */
/* 0x000fe2000c101904 */
/*0c10*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c20*/ BRA 0xc20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixMulPfS_S_ii
.globl _Z9matrixMulPfS_S_ii
.p2align 8
.type _Z9matrixMulPfS_S_ii,@function
_Z9matrixMulPfS_S_ii:
s_load_b32 s4, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_3
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b128 s[8:11], s[0:1], 0x8
v_mul_lo_u32 v2, v0, s4
v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v6, 2, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_ashr_i32 s3, s2, 31
v_add_co_u32 v2, s5, s10, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s8, v4
v_add_co_ci_u32_e64 v3, null, s11, 0, s5
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
v_mov_b32_e32 v6, 0
s_lshl_b64 s[2:3], s[2:3], 2
s_mov_b32 s5, s4
.LBB0_2:
global_load_b32 v7, v[4:5], off
global_load_b32 v8, v[2:3], off
v_add_co_u32 v2, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v7, v8
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v6, 0
.LBB0_4:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v6, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixMulPfS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 12
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixMulPfS_S_ii, .Lfunc_end0-_Z9matrixMulPfS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixMulPfS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 14
.sgpr_spill_count: 0
.symbol: _Z9matrixMulPfS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017597d_00000000-6_cuda_p4.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10randomInitPfi
.type _Z10randomInitPfi, @function
_Z10randomInitPfi:
.LFB2057:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L3
movslq %esi, %rsi
movl $0, %eax
.L5:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rdi,%rax,4)
addq $1, %rax
cmpq %rsi, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z10randomInitPfi, .-_Z10randomInitPfi
.globl _Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii
.type _Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii, @function
_Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixMulPfS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii, .-_Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii
.globl _Z9matrixMulPfS_S_ii
.type _Z9matrixMulPfS_S_ii, @function
_Z9matrixMulPfS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9matrixMulPfS_S_ii, .-_Z9matrixMulPfS_S_ii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "\n\nMatrix A\n"
.LC1:
.string "%f "
.LC2:
.string "\n"
.LC3:
.string "\n\nMatrix B\n"
.LC4:
.string "\n\n Matrix C ( Results ) \n "
.LC5:
.string "%f"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $2006, %edi
call srand@PLT
movl $36, %edi
call malloc@PLT
movq %rax, %r12
movl $36, %edi
call malloc@PLT
movq %rax, %rbp
movl $9, %esi
movq %r12, %rdi
call _Z10randomInitPfi
movl $9, %esi
movq %rbp, %rdi
call _Z10randomInitPfi
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r14
jmp .L17
.L16:
addq $1, %rbx
cmpq $10, %rbx
je .L28
.L17:
pxor %xmm0, %xmm0
cvtss2sd -4(%r12,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
cmpl %ebx, %eax
jne .L16
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L28:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC1(%rip), %r13
leaq .LC2(%rip), %r14
jmp .L19
.L18:
addq $1, %rbx
cmpq $10, %rbx
je .L29
.L19:
pxor %xmm0, %xmm0
cvtss2sd -4(%rbp,%rbx,4), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
cmpl %ebx, %eax
jne .L18
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L29:
movl $36, %edi
call malloc@PLT
movq %rax, %r13
leaq 8(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $36, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $36, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
movl $36, %esi
call cudaMalloc@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $3, 32(%rsp)
movl $3, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L20:
movl $2, %ecx
movl $36, %edx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ebx
leaq .LC5(%rip), %r14
leaq .LC2(%rip), %r15
jmp .L22
.L30:
movl $3, %r8d
movl $3, %ecx
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z34__device_stub__Z9matrixMulPfS_S_iiPfS_S_ii
jmp .L20
.L32:
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L21:
addq $1, %rbx
cmpq $10, %rbx
je .L31
.L22:
pxor %xmm0, %xmm0
cvtss2sd -4(%r13,%rbx,4), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1431655766, %rax, %rax
shrq $32, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,2), %eax
cmpl %ebx, %eax
jne .L21
jmp .L32
.L31:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L33
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z9matrixMulPfS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixMulPfS_S_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_p4.hip"
.globl _Z10randomInitPfi # -- Begin function _Z10randomInitPfi
.p2align 4, 0x90
.type _Z10randomInitPfi,@function
_Z10randomInitPfi: # @_Z10randomInitPfi
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %esi, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rdi,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z10randomInitPfi, .Lfunc_end0-_Z10randomInitPfi
.cfi_endproc
# -- End function
.globl _Z24__device_stub__matrixMulPfS_S_ii # -- Begin function _Z24__device_stub__matrixMulPfS_S_ii
.p2align 4, 0x90
.type _Z24__device_stub__matrixMulPfS_S_ii,@function
_Z24__device_stub__matrixMulPfS_S_ii: # @_Z24__device_stub__matrixMulPfS_S_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixMulPfS_S_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z24__device_stub__matrixMulPfS_S_ii, .Lfunc_end1-_Z24__device_stub__matrixMulPfS_S_ii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $2006, %edi # imm = 0x7D6
callq srand
movl $36, %edi
callq malloc
movq %rax, %rbx
movl $36, %edi
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
incq %rax
cmpq $9, %rax
jne .LBB2_1
# %bb.2: # %.lr.ph.i52.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i52
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $9, %rax
jne .LBB2_3
# %bb.4: # %_Z10randomInitPfi.exit56
movl $.Lstr, %edi
callq puts@PLT
movl $1, %r15d
xorl %r12d, %r12d
movabsq $-6148914691236517205, %r13 # imm = 0xAAAAAAAAAAAAAAAB
jmp .LBB2_5
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_5 Depth=1
incq %r12
incq %r15
cmpq $9, %r12
je .LBB2_8
.LBB2_5: # =>This Inner Loop Header: Depth=1
movq %r15, %rax
mulq %r13
shrq %rdx
leal (%rdx,%rdx,2), %ebp
decl %ebp
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
cmpl %r12d, %ebp
jne .LBB2_7
# %bb.6: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_7
.LBB2_8:
movl $.Lstr.1, %edi
callq puts@PLT
movl $1, %r15d
xorl %r12d, %r12d
jmp .LBB2_9
.p2align 4, 0x90
.LBB2_11: # in Loop: Header=BB2_9 Depth=1
incq %r12
incq %r15
cmpq $9, %r12
je .LBB2_12
.LBB2_9: # =>This Inner Loop Header: Depth=1
movq %r15, %rax
mulq %r13
shrq %rdx
leal (%rdx,%rdx,2), %ebp
decl %ebp
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.1, %edi
movb $1, %al
callq printf
cmpl %r12d, %ebp
jne .LBB2_11
# %bb.10: # in Loop: Header=BB2_9 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_11
.LBB2_12:
movl $36, %edi
callq malloc
movq %rax, %r15
leaq 24(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $36, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $36, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 8(%rsp), %rdi
movl $36, %esi
callq hipMalloc
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $12884901891, %rdx # imm = 0x300000003
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_14
# %bb.13:
movq 8(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $3, 36(%rsp)
movl $3, 32(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9matrixMulPfS_S_ii, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_14:
movq 8(%rsp), %rsi
movl $36, %edx
movq %r15, %r13
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %ebp, %ebp
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movl $1, %r12d
jmp .LBB2_15
.p2align 4, 0x90
.LBB2_17: # in Loop: Header=BB2_15 Depth=1
incq %rbp
incq %r12
cmpq $9, %rbp
je .LBB2_18
.LBB2_15: # =>This Inner Loop Header: Depth=1
movq %r12, %rax
movabsq $-6148914691236517205, %rcx # imm = 0xAAAAAAAAAAAAAAAB
mulq %rcx
shrq %rdx
leal (%rdx,%rdx,2), %r15d
decl %r15d
movss (%r13,%rbp,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str.5, %edi
movb $1, %al
callq printf
cmpl %ebp, %r15d
jne .LBB2_17
# %bb.16: # in Loop: Header=BB2_15 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB2_17
.LBB2_18:
movl $10, %edi
callq putchar@PLT
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r13, %rdi
callq free
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixMulPfS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixMulPfS_S_ii,@object # @_Z9matrixMulPfS_S_ii
.section .rodata,"a",@progbits
.globl _Z9matrixMulPfS_S_ii
.p2align 3, 0x0
_Z9matrixMulPfS_S_ii:
.quad _Z24__device_stub__matrixMulPfS_S_ii
.size _Z9matrixMulPfS_S_ii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f "
.size .L.str.1, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "\n\n Matrix C ( Results ) \n "
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f"
.size .L.str.5, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matrixMulPfS_S_ii"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\nMatrix A"
.size .Lstr, 11
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\n\nMatrix B"
.size .Lstr.1, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixMulPfS_S_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixMulPfS_S_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 100
__global__ void CUDAStrCopy(char *str, int *len)
{
int i = blockIdx.x;
char temp = str[i];
str[i] = str[*len - i - 1];
str[*len - i - 1] = temp;
}
int main()
{
char str[N];
printf("Enter the string: ");
scanf("%s", str);
char *pstr;
int len = strlen(str);
int *plen;
char str2[len];
cudaMalloc((void**)&pstr, len * sizeof(char));
cudaMalloc((void**)&plen, sizeof(int));
cudaMemcpy(pstr, str, len * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(plen, &len, sizeof(int), cudaMemcpyHostToDevice);
CUDAStrCopy<<<len, 1>>>(pstr, plen);
cudaMemcpy(str, pstr, len * sizeof(char), cudaMemcpyDeviceToHost);
printf("Reversed String is: %s\n", str);
cudaFree(pstr);
cudaFree(plen);
printf("\n");
return 0;
} | code for sm_80
Function : _Z11CUDAStrCopyPcPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0040*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0050*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R0, [R4.64] ; /* 0x0000000a04007981 */
/* 0x000ea2000c1e1900 */
/*0070*/ ULOP3.LUT UR8, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f087292 */
/* 0x001fcc000f8e333f */
/*0080*/ IADD3 R0, R0, UR8, RZ ; /* 0x0000000800007c10 */
/* 0x004fc8000fffe0ff */
/*0090*/ IADD3 R6, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x000fc80007f1e0ff */
/*00a0*/ LEA.HI.X.SX32 R7, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000077a11 */
/* 0x000fcc00000f0eff */
/*00b0*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000a06077981 */
/* 0x000ea2000c1e1100 */
/*00c0*/ UIADD3 UR5, UP0, UR4, UR6, URZ ; /* 0x0000000604057290 */
/* 0x000fc8000ff1e03f */
/*00d0*/ ULEA.HI.X.SX32 UR4, UR4, UR7, 0x1, UP0 ; /* 0x0000000704047291 */
/* 0x000fe400080f0e3f */
/*00e0*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fc8000f8e00ff */
/*00f0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0100*/ LDG.E.U8 R11, [R2.64] ; /* 0x0000000a020b7981 */
/* 0x000ee8000c1e1100 */
/*0110*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x004fe8000c10110a */
/*0120*/ LDG.E R4, [R4.64] ; /* 0x0000000a04047981 */
/* 0x000ea4000c1e1900 */
/*0130*/ IADD3 R0, R4, UR8, RZ ; /* 0x0000000804007c10 */
/* 0x004fc8000fffe0ff */
/*0140*/ IADD3 R8, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x000fc80007f1e0ff */
/*0150*/ LEA.HI.X.SX32 R9, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000097a11 */
/* 0x000fca00000f0eff */
/*0160*/ STG.E.U8 [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x008fe2000c10110a */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 100
__global__ void CUDAStrCopy(char *str, int *len)
{
int i = blockIdx.x;
char temp = str[i];
str[i] = str[*len - i - 1];
str[*len - i - 1] = temp;
}
int main()
{
char str[N];
printf("Enter the string: ");
scanf("%s", str);
char *pstr;
int len = strlen(str);
int *plen;
char str2[len];
cudaMalloc((void**)&pstr, len * sizeof(char));
cudaMalloc((void**)&plen, sizeof(int));
cudaMemcpy(pstr, str, len * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(plen, &len, sizeof(int), cudaMemcpyHostToDevice);
CUDAStrCopy<<<len, 1>>>(pstr, plen);
cudaMemcpy(str, pstr, len * sizeof(char), cudaMemcpyDeviceToHost);
printf("Reversed String is: %s\n", str);
cudaFree(pstr);
cudaFree(plen);
printf("\n");
return 0;
} | .file "tmpxft_0006e5d9_00000000-6_reverse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11CUDAStrCopyPcPiPcPi
.type _Z33__device_stub__Z11CUDAStrCopyPcPiPcPi, @function
_Z33__device_stub__Z11CUDAStrCopyPcPiPcPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11CUDAStrCopyPcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z11CUDAStrCopyPcPiPcPi, .-_Z33__device_stub__Z11CUDAStrCopyPcPiPcPi
.globl _Z11CUDAStrCopyPcPi
.type _Z11CUDAStrCopyPcPi, @function
_Z11CUDAStrCopyPcPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11CUDAStrCopyPcPiPcPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11CUDAStrCopyPcPi, .-_Z11CUDAStrCopyPcPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the string: "
.LC1:
.string "%s"
.LC2:
.string "Reversed String is: %s\n"
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $160, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %rbx
movq %rbx, %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbx, %rdi
call strlen@PLT
movl %eax, 4(%rsp)
movslq %eax, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movslq 4(%rsp), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl 4(%rsp), %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movslq 4(%rsp), %rdx
leaq 48(%rsp), %rbx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z11CUDAStrCopyPcPiPcPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11CUDAStrCopyPcPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11CUDAStrCopyPcPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 100
__global__ void CUDAStrCopy(char *str, int *len)
{
int i = blockIdx.x;
char temp = str[i];
str[i] = str[*len - i - 1];
str[*len - i - 1] = temp;
}
int main()
{
char str[N];
printf("Enter the string: ");
scanf("%s", str);
char *pstr;
int len = strlen(str);
int *plen;
char str2[len];
cudaMalloc((void**)&pstr, len * sizeof(char));
cudaMalloc((void**)&plen, sizeof(int));
cudaMemcpy(pstr, str, len * sizeof(char), cudaMemcpyHostToDevice);
cudaMemcpy(plen, &len, sizeof(int), cudaMemcpyHostToDevice);
CUDAStrCopy<<<len, 1>>>(pstr, plen);
cudaMemcpy(str, pstr, len * sizeof(char), cudaMemcpyDeviceToHost);
printf("Reversed String is: %s\n", str);
cudaFree(pstr);
cudaFree(plen);
printf("\n");
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 100
__global__ void CUDAStrCopy(char *str, int *len)
{
int i = blockIdx.x;
char temp = str[i];
str[i] = str[*len - i - 1];
str[*len - i - 1] = temp;
}
int main()
{
char str[N];
printf("Enter the string: ");
scanf("%s", str);
char *pstr;
int len = strlen(str);
int *plen;
char str2[len];
hipMalloc((void**)&pstr, len * sizeof(char));
hipMalloc((void**)&plen, sizeof(int));
hipMemcpy(pstr, str, len * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(plen, &len, sizeof(int), hipMemcpyHostToDevice);
CUDAStrCopy<<<len, 1>>>(pstr, plen);
hipMemcpy(str, pstr, len * sizeof(char), hipMemcpyDeviceToHost);
printf("Reversed String is: %s\n", str);
hipFree(pstr);
hipFree(plen);
printf("\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 100
__global__ void CUDAStrCopy(char *str, int *len)
{
int i = blockIdx.x;
char temp = str[i];
str[i] = str[*len - i - 1];
str[*len - i - 1] = temp;
}
int main()
{
char str[N];
printf("Enter the string: ");
scanf("%s", str);
char *pstr;
int len = strlen(str);
int *plen;
char str2[len];
hipMalloc((void**)&pstr, len * sizeof(char));
hipMalloc((void**)&plen, sizeof(int));
hipMemcpy(pstr, str, len * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(plen, &len, sizeof(int), hipMemcpyHostToDevice);
CUDAStrCopy<<<len, 1>>>(pstr, plen);
hipMemcpy(str, pstr, len * sizeof(char), hipMemcpyDeviceToHost);
printf("Reversed String is: %s\n", str);
hipFree(pstr);
hipFree(plen);
printf("\n");
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11CUDAStrCopyPcPi
.globl _Z11CUDAStrCopyPcPi
.p2align 8
.type _Z11CUDAStrCopyPcPi,@function
_Z11CUDAStrCopyPcPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_ashr_i32 s5, s15, 31
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s6, s[2:3], 0x0
s_add_u32 s4, s0, s15
s_addc_u32 s5, s1, s5
s_not_b32 s8, s15
s_waitcnt lgkmcnt(0)
s_add_i32 s6, s6, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_add_u32 s6, s0, s6
s_addc_u32 s7, s1, s7
s_clause 0x1
global_load_u8 v1, v0, s[6:7]
global_load_u8 v2, v0, s[4:5]
s_waitcnt vmcnt(1)
global_store_b8 v0, v1, s[4:5]
global_load_b32 v0, v0, s[2:3]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11CUDAStrCopyPcPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11CUDAStrCopyPcPi, .Lfunc_end0-_Z11CUDAStrCopyPcPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11CUDAStrCopyPcPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11CUDAStrCopyPcPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#define N 100
__global__ void CUDAStrCopy(char *str, int *len)
{
int i = blockIdx.x;
char temp = str[i];
str[i] = str[*len - i - 1];
str[*len - i - 1] = temp;
}
int main()
{
char str[N];
printf("Enter the string: ");
scanf("%s", str);
char *pstr;
int len = strlen(str);
int *plen;
char str2[len];
hipMalloc((void**)&pstr, len * sizeof(char));
hipMalloc((void**)&plen, sizeof(int));
hipMemcpy(pstr, str, len * sizeof(char), hipMemcpyHostToDevice);
hipMemcpy(plen, &len, sizeof(int), hipMemcpyHostToDevice);
CUDAStrCopy<<<len, 1>>>(pstr, plen);
hipMemcpy(str, pstr, len * sizeof(char), hipMemcpyDeviceToHost);
printf("Reversed String is: %s\n", str);
hipFree(pstr);
hipFree(plen);
printf("\n");
return 0;
} | .text
.file "reverse.hip"
.globl _Z26__device_stub__CUDAStrCopyPcPi # -- Begin function _Z26__device_stub__CUDAStrCopyPcPi
.p2align 4, 0x90
.type _Z26__device_stub__CUDAStrCopyPcPi,@function
_Z26__device_stub__CUDAStrCopyPcPi: # @_Z26__device_stub__CUDAStrCopyPcPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11CUDAStrCopyPcPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__CUDAStrCopyPcPi, .Lfunc_end0-_Z26__device_stub__CUDAStrCopyPcPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $216, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 112(%rsp), %rbx
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
callq strlen
movq %rsp, %r14
movl %eax, 12(%rsp)
movslq %eax, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movslq 12(%rsp), %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11CUDAStrCopyPcPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
leaq 112(%rsp), %rbx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $10, %edi
callq putchar@PLT
movq %r14, %rsp
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11CUDAStrCopyPcPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11CUDAStrCopyPcPi,@object # @_Z11CUDAStrCopyPcPi
.section .rodata,"a",@progbits
.globl _Z11CUDAStrCopyPcPi
.p2align 3, 0x0
_Z11CUDAStrCopyPcPi:
.quad _Z26__device_stub__CUDAStrCopyPcPi
.size _Z11CUDAStrCopyPcPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the string: "
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Reversed String is: %s\n"
.size .L.str.2, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11CUDAStrCopyPcPi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__CUDAStrCopyPcPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11CUDAStrCopyPcPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11CUDAStrCopyPcPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0040*/ S2UR UR4, SR_CTAID.X ; /* 0x00000000000479c3 */
/* 0x000e220000002500 */
/*0050*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fc60000000a00 */
/*0060*/ LDG.E R0, [R4.64] ; /* 0x0000000a04007981 */
/* 0x000ea2000c1e1900 */
/*0070*/ ULOP3.LUT UR8, URZ, UR4, URZ, 0x33, !UPT ; /* 0x000000043f087292 */
/* 0x001fcc000f8e333f */
/*0080*/ IADD3 R0, R0, UR8, RZ ; /* 0x0000000800007c10 */
/* 0x004fc8000fffe0ff */
/*0090*/ IADD3 R6, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a10 */
/* 0x000fc80007f1e0ff */
/*00a0*/ LEA.HI.X.SX32 R7, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000077a11 */
/* 0x000fcc00000f0eff */
/*00b0*/ LDG.E.U8 R7, [R6.64] ; /* 0x0000000a06077981 */
/* 0x000ea2000c1e1100 */
/*00c0*/ UIADD3 UR5, UP0, UR4, UR6, URZ ; /* 0x0000000604057290 */
/* 0x000fc8000ff1e03f */
/*00d0*/ ULEA.HI.X.SX32 UR4, UR4, UR7, 0x1, UP0 ; /* 0x0000000704047291 */
/* 0x000fe400080f0e3f */
/*00e0*/ IMAD.U32 R2, RZ, RZ, UR5 ; /* 0x00000005ff027e24 */
/* 0x000fc8000f8e00ff */
/*00f0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*0100*/ LDG.E.U8 R11, [R2.64] ; /* 0x0000000a020b7981 */
/* 0x000ee8000c1e1100 */
/*0110*/ STG.E.U8 [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x004fe8000c10110a */
/*0120*/ LDG.E R4, [R4.64] ; /* 0x0000000a04047981 */
/* 0x000ea4000c1e1900 */
/*0130*/ IADD3 R0, R4, UR8, RZ ; /* 0x0000000804007c10 */
/* 0x004fc8000fffe0ff */
/*0140*/ IADD3 R8, P0, R0, c[0x0][0x160], RZ ; /* 0x0000580000087a10 */
/* 0x000fc80007f1e0ff */
/*0150*/ LEA.HI.X.SX32 R9, R0, c[0x0][0x164], 0x1, P0 ; /* 0x0000590000097a11 */
/* 0x000fca00000f0eff */
/*0160*/ STG.E.U8 [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x008fe2000c10110a */
/*0170*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0180*/ BRA 0x180; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11CUDAStrCopyPcPi
.globl _Z11CUDAStrCopyPcPi
.p2align 8
.type _Z11CUDAStrCopyPcPi,@function
_Z11CUDAStrCopyPcPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_ashr_i32 s5, s15, 31
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_load_b32 s6, s[2:3], 0x0
s_add_u32 s4, s0, s15
s_addc_u32 s5, s1, s5
s_not_b32 s8, s15
s_waitcnt lgkmcnt(0)
s_add_i32 s6, s6, s8
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s7, s6, 31
s_add_u32 s6, s0, s6
s_addc_u32 s7, s1, s7
s_clause 0x1
global_load_u8 v1, v0, s[6:7]
global_load_u8 v2, v0, s[4:5]
s_waitcnt vmcnt(1)
global_store_b8 v0, v1, s[4:5]
global_load_b32 v0, v0, s[2:3]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, s8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v1, 31, v0
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b8 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11CUDAStrCopyPcPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11CUDAStrCopyPcPi, .Lfunc_end0-_Z11CUDAStrCopyPcPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11CUDAStrCopyPcPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11CUDAStrCopyPcPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006e5d9_00000000-6_reverse.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11CUDAStrCopyPcPiPcPi
.type _Z33__device_stub__Z11CUDAStrCopyPcPiPcPi, @function
_Z33__device_stub__Z11CUDAStrCopyPcPiPcPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11CUDAStrCopyPcPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z33__device_stub__Z11CUDAStrCopyPcPiPcPi, .-_Z33__device_stub__Z11CUDAStrCopyPcPiPcPi
.globl _Z11CUDAStrCopyPcPi
.type _Z11CUDAStrCopyPcPi, @function
_Z11CUDAStrCopyPcPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11CUDAStrCopyPcPiPcPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11CUDAStrCopyPcPi, .-_Z11CUDAStrCopyPcPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Enter the string: "
.LC1:
.string "%s"
.LC2:
.string "Reversed String is: %s\n"
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $160, %rsp
.cfi_def_cfa_offset 176
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 48(%rsp), %rbx
movq %rbx, %rsi
leaq .LC1(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movq %rbx, %rdi
call strlen@PLT
movl %eax, 4(%rsp)
movslq %eax, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movslq 4(%rsp), %rdx
movl $1, %ecx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 4(%rsp), %rsi
movl $1, %ecx
movl $4, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl 4(%rsp), %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movslq 4(%rsp), %rdx
leaq 48(%rsp), %rbx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq %rbx, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L16
movl $0, %eax
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z11CUDAStrCopyPcPiPcPi
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z11CUDAStrCopyPcPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11CUDAStrCopyPcPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reverse.hip"
.globl _Z26__device_stub__CUDAStrCopyPcPi # -- Begin function _Z26__device_stub__CUDAStrCopyPcPi
.p2align 4, 0x90
.type _Z26__device_stub__CUDAStrCopyPcPi,@function
_Z26__device_stub__CUDAStrCopyPcPi: # @_Z26__device_stub__CUDAStrCopyPcPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11CUDAStrCopyPcPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__CUDAStrCopyPcPi, .Lfunc_end0-_Z26__device_stub__CUDAStrCopyPcPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $216, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 112(%rsp), %rbx
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq __isoc23_scanf
movq %rbx, %rdi
callq strlen
movq %rsp, %r14
movl %eax, 12(%rsp)
movslq %eax, %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movslq 12(%rsp), %rdx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 12(%rsp), %rsi
movl $4, %edx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq 24(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11CUDAStrCopyPcPi, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movslq 12(%rsp), %rdx
leaq 112(%rsp), %rbx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 16(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movl $10, %edi
callq putchar@PLT
movq %r14, %rsp
xorl %eax, %eax
addq $216, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11CUDAStrCopyPcPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11CUDAStrCopyPcPi,@object # @_Z11CUDAStrCopyPcPi
.section .rodata,"a",@progbits
.globl _Z11CUDAStrCopyPcPi
.p2align 3, 0x0
_Z11CUDAStrCopyPcPi:
.quad _Z26__device_stub__CUDAStrCopyPcPi
.size _Z11CUDAStrCopyPcPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the string: "
.size .L.str, 19
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s"
.size .L.str.1, 3
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Reversed String is: %s\n"
.size .L.str.2, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11CUDAStrCopyPcPi"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__CUDAStrCopyPcPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11CUDAStrCopyPcPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "csr.cuh"
#include "cudaMacros.cuh"
#include <stdio.h>
template<unsigned int blockSize, unsigned int beh>
__device__ void warpReduce_mxn(volatile double *sdata, unsigned int tid_0) {
int i;
if (blockSize >= 64)
SUM_POSITIONS_H(beh, 32)
if (blockSize >= 32)
SUM_POSITIONS_H(beh, 16)
if (blockSize >= 16)
SUM_POSITIONS_H(beh, 8)
if (blockSize >= 8)
SUM_POSITIONS_H(beh, 4)
if (blockSize >= 4)
SUM_POSITIONS_H(beh, 2)
if (blockSize >= 2) {
SUM_POSITIONS_H(beh, 1)
}
}
template<unsigned int blockSize, unsigned int beh>
__device__ void warpReduce_multithread_simple_mxn(volatile double *sdata, unsigned int sdata_index, unsigned int tid) {
if (blockSize >= 64)
sdata[sdata_index] += sdata[sdata_index + 32 * beh];
if (blockSize >= 32)
sdata[sdata_index] += sdata[sdata_index + 16 * beh];
if (blockSize >= 16)
sdata[sdata_index] += sdata[sdata_index + 8 * beh];
if (blockSize >= 8)
sdata[sdata_index] += sdata[sdata_index + 4 * beh];
if (blockSize >= 4)
sdata[sdata_index] += sdata[sdata_index + 2 * beh];
if (blockSize >= 2)
sdata[sdata_index] += sdata[sdata_index + beh];
}
template<unsigned int blockSize, unsigned int beh, unsigned int bew>
__global__ void device_cuda_csr_matrixvector_multithread_simple_mxn(double* as, unsigned int *irp, unsigned int* ja, double* x, double* y) {
extern __shared__ double sdata[];
// printf("block size: x%d\ty%d\n", blockDim.x, blockDim.y);
unsigned int sdata_index = threadIdx.y + threadIdx.x * beh;
sdata[sdata_index] = 0;
unsigned int tid = threadIdx.x;
unsigned int bid = blockIdx.x;
unsigned int irp_off = irp[bid] + tid;
unsigned int irp_end = irp[bid + 1];
for (; irp_off < irp_end; irp_off += blockSize) {
for (int i = 0; i < bew; ++i) {
sdata[sdata_index] += x[ja[irp_off] + i] * as[irp_off * beh * bew + threadIdx.y * bew + i];
// if (x[ja[irp_off] + i] * as[irp_off * beh * bew + threadIdx.y * bew + i] > 0)
// printf("bid:%d\ttidX:%d\ttidY:%d\tvalue was: %f\n",bid,tid,threadIdx.y, x[ja[irp_off] + i] * as[irp_off * beh * bew + threadIdx.y * bew + i]);
}
}
__syncthreads();
if (blockSize >= 512) {
if (tid < 256) {
sdata[sdata_index] += sdata[sdata_index + 256 * beh];
}
__syncthreads();
}
if (blockSize >= 256) {
if (tid < 128)
sdata[sdata_index] += sdata[sdata_index + 128 * beh];
__syncthreads();
}
if (blockSize >= 128) {
if (tid < 64)
sdata[sdata_index] += sdata[sdata_index + 64 * beh];
__syncthreads();
}
if (tid < 32)
warpReduce_multithread_simple_mxn<blockSize, beh>(sdata, sdata_index, threadIdx.x);
if (tid == 0) {
y[threadIdx.y + bid * beh] = sdata[threadIdx.y];
}
}
template<unsigned int BlockSize, unsigned int beh, unsigned int bew>
__global__ void device_cuda_csr_matrixvector_simple_mxn(double* as, unsigned int *irp, unsigned int* ja, double* x, double* y) {
extern __shared__ double sdata[];
unsigned int i, j, irp_off;
unsigned int bes = beh * bew;
unsigned int bid = blockIdx.x;
unsigned int tid = threadIdx.x;
unsigned int tid_0 = threadIdx.x * beh;
for (i = 0; i < beh; ++i) {
sdata[tid_0 + i] = 0;
}
unsigned a;
unsigned int as_off;
for (irp_off = irp[bid] + tid; irp_off < irp[bid + 1]; irp_off += BlockSize) {
a = 0;
as_off = (irp_off) * bes;
for (i = 0; i < beh; ++i) {
for (j = 0; j < bew; ++j) {
sdata[tid_0 + i] += x[ja[irp_off] + j] * as[as_off + a++];
}
}
}
__syncthreads();
if (BlockSize >= 512) {
if (tid < 256)
SUM_POSITIONS_H(beh, 256)
__syncthreads();
}
if (BlockSize >= 256) {
if (tid < 128)
SUM_POSITIONS_H(beh, 128)
__syncthreads();
}
if (BlockSize >= 128) {
if (tid < 64)
SUM_POSITIONS_H(beh, 64)
__syncthreads();
}
if (tid < 32)
warpReduce_mxn<BlockSize, beh>(sdata, tid_0);
if (tid == 0) {
for (int var = 0; var < beh; ++var) {
y[blockIdx.x * beh + var] = sdata[var];
}
}
}
__host__ double cuda_csr_matrixvector(unsigned int *h_irp, unsigned int irp_size, unsigned int* h_ja, unsigned int ja_size, double* h_as, unsigned int as_size, unsigned int cols, unsigned int rows, unsigned int beh, unsigned int bew, unsigned int blockRows, double* h_x, double* h_y, unsigned int blockSize) {
if (blockSize * beh > 1024)
return 0;
double* x_off = (double*) calloc(cols + bew, sizeof(double));
memcpy(x_off, h_x, cols * sizeof(double));
unsigned int* d_irp;
unsigned int* d_ja;
double* d_as;
double* d_x;
double* d_y;
cudaError_t error;
cudaEvent_t start, stop;
float temp, milliseconds = 0;
CHECK_CUDA_ERROR(cudaEventCreate(&start))
CHECK_CUDA_ERROR(cudaEventCreate(&stop))
dim3 BS(blockSize, beh, 1);
cudaSetDevice(0);
CHECK_CUDA_ERROR(cudaMalloc((void** ) &d_irp, irp_size * sizeof(unsigned int)))
CHECK_CUDA_ERROR(cudaMalloc((void** ) &d_ja, ja_size * sizeof(unsigned int)))
CHECK_CUDA_ERROR(cudaMalloc((void** ) &d_as, as_size * sizeof(double)))
CHECK_CUDA_ERROR(cudaMalloc((void** ) &d_y, (rows + beh - rows % beh) * sizeof(double)))
CHECK_CUDA_ERROR(cudaMalloc((void** ) &d_x, (cols + bew) * sizeof(double)))
CHECK_CUDA_ERROR(cudaMemcpy(d_irp, h_irp, irp_size * sizeof(unsigned int), cudaMemcpyHostToDevice))
CHECK_CUDA_ERROR(cudaMemcpy(d_ja, h_ja, ja_size * sizeof(unsigned int), cudaMemcpyHostToDevice))
CHECK_CUDA_ERROR(cudaMemcpy(d_as, h_as, as_size * sizeof(double), cudaMemcpyHostToDevice))
CHECK_CUDA_ERROR(cudaMemcpy(d_x, x_off, (cols + bew) * sizeof(double), cudaMemcpyHostToDevice))
CHECK_CUDA_ERROR(cudaMemcpy(d_y, h_y, rows * sizeof(double), cudaMemcpyHostToDevice))
for (int run = 0; run < TRIES; run++) {
CHECK_CUDA_ERROR(cudaEventRecord(start))
SWITCH_BLOCKENTRY_SIZE_AND_CUDA_BLOCK_SIZE(blockSize, beh, bew, device_cuda_csr_matrixvector_multithread_simple_mxn, blockRows, BS, 2 * blockSize * beh * sizeof(double), (d_as, d_irp, d_ja, d_x, d_y))
CHECK_CUDA_ERROR(cudaEventRecord(stop))
error = cudaGetLastError();
if (error != cudaSuccess) {
exit(1);
}
CHECK_CUDA_ERROR(cudaEventRecord(stop))
CHECK_CUDA_ERROR(cudaEventSynchronize(stop))
CHECK_CUDA_ERROR(cudaEventElapsedTime(&temp, start, stop));
milliseconds += temp;
}
CHECK_CUDA_ERROR(cudaMemcpy(h_y, d_y, rows * sizeof(double), cudaMemcpyDeviceToHost))
CHECK_CUDA_ERROR(cudaFree(d_ja))
CHECK_CUDA_ERROR(cudaFree(d_as))
CHECK_CUDA_ERROR(cudaFree(d_irp))
CHECK_CUDA_ERROR(cudaFree(d_y))
CHECK_CUDA_ERROR(cudaFree(d_x))
return milliseconds * 1000.0 / (double) TRIES;
} | /*
* csr.cuh
*
* Created on: 22/05/2017
* Author: leonardo
*/
#ifndef CSR_CUH_
#define CSR_CUH_
#include <hip/hip_runtime.h>
__host__ double cuda_csr_matrixvector(
unsigned int *h_irp, unsigned int irp_size,
unsigned int* h_ja, unsigned int ja_size,
double* h_as, unsigned int as_size,
unsigned int cols, unsigned int rows,
unsigned int beh, unsigned int bew,
unsigned int blockRows,
double* h_x,
double* h_y,
unsigned int blockSize);
#endif /* CSR_CUH_ */ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* csr.cuh
*
* Created on: 22/05/2017
* Author: leonardo
*/
#ifndef CSR_CUH_
#define CSR_CUH_
#include <hip/hip_runtime.h>
__host__ double cuda_csr_matrixvector(
unsigned int *h_irp, unsigned int irp_size,
unsigned int* h_ja, unsigned int ja_size,
double* h_as, unsigned int as_size,
unsigned int cols, unsigned int rows,
unsigned int beh, unsigned int bew,
unsigned int blockRows,
double* h_x,
double* h_y,
unsigned int blockSize);
#endif /* CSR_CUH_ */ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* csr.cuh
*
* Created on: 22/05/2017
* Author: leonardo
*/
#ifndef CSR_CUH_
#define CSR_CUH_
#include <hip/hip_runtime.h>
__host__ double cuda_csr_matrixvector(
unsigned int *h_irp, unsigned int irp_size,
unsigned int* h_ja, unsigned int ja_size,
double* h_as, unsigned int as_size,
unsigned int cols, unsigned int rows,
unsigned int beh, unsigned int bew,
unsigned int blockRows,
double* h_x,
double* h_y,
unsigned int blockSize);
#endif /* CSR_CUH_ */ | .text
.file "csr.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#define N 256
#define T 256
__global__ void reverseArray(int *A ,int *B){
int i = threadIdx.x;
B[i] = A[(N - 1) - i];
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof (int);
int a[N], b[N], *devA, *devB;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = i;
printf("%d ",a[i]);
}
cudaMalloc( (void**)&devA,size);
cudaMalloc( (void**)&devB,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
reverseArray<<<1,T>>>(devA,devB);
cudaMemcpy( b, devB, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
cudaFree(devB);
printf("\nNew A array \n");
for (i = 0;i < N; i++){
printf("%d ",b[i]);
}
printf("\n");
} | code for sm_80
Function : _Z12reverseArrayPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R2, -R4, 0xff, RZ ; /* 0x000000ff04027810 */
/* 0x001fd00007ffe1ff */
/*0050*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0060*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#define N 256
#define T 256
__global__ void reverseArray(int *A ,int *B){
int i = threadIdx.x;
B[i] = A[(N - 1) - i];
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof (int);
int a[N], b[N], *devA, *devB;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = i;
printf("%d ",a[i]);
}
cudaMalloc( (void**)&devA,size);
cudaMalloc( (void**)&devB,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
reverseArray<<<1,T>>>(devA,devB);
cudaMemcpy( b, devB, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
cudaFree(devB);
printf("\nNew A array \n");
for (i = 0;i < N; i++){
printf("%d ",b[i]);
}
printf("\n");
} | .file "tmpxft_001876b7_00000000-6_Q3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12reverseArrayPiS_PiS_
.type _Z34__device_stub__Z12reverseArrayPiS_PiS_, @function
_Z34__device_stub__Z12reverseArrayPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12reverseArrayPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z12reverseArrayPiS_PiS_, .-_Z34__device_stub__Z12reverseArrayPiS_PiS_
.globl _Z12reverseArrayPiS_
.type _Z12reverseArrayPiS_, @function
_Z12reverseArrayPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12reverseArrayPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12reverseArrayPiS_, .-_Z12reverseArrayPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Original A array\n"
.LC1:
.string "%d "
.LC2:
.string "\nNew A array \n"
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $2112, %rsp
.cfi_def_cfa_offset 2144
movq %fs:40, %rax
movq %rax, 2104(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L12:
movl %ebx, %edx
movl %ebx, 48(%rsp,%rbx,4)
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L12
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 1072(%rsp), %rbx
movl $2, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 2096(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 2104(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $2112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z12reverseArrayPiS_PiS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12reverseArrayPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12reverseArrayPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#define N 256
#define T 256
__global__ void reverseArray(int *A ,int *B){
int i = threadIdx.x;
B[i] = A[(N - 1) - i];
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof (int);
int a[N], b[N], *devA, *devB;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = i;
printf("%d ",a[i]);
}
cudaMalloc( (void**)&devA,size);
cudaMalloc( (void**)&devB,size);
cudaMemcpy( devA, a, size, cudaMemcpyHostToDevice);
reverseArray<<<1,T>>>(devA,devB);
cudaMemcpy( b, devB, size, cudaMemcpyDeviceToHost);
cudaFree(devA);
cudaFree(devB);
printf("\nNew A array \n");
for (i = 0;i < N; i++){
printf("%d ",b[i]);
}
printf("\n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 256
#define T 256
__global__ void reverseArray(int *A ,int *B){
int i = threadIdx.x;
B[i] = A[(N - 1) - i];
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof (int);
int a[N], b[N], *devA, *devB;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = i;
printf("%d ",a[i]);
}
hipMalloc( (void**)&devA,size);
hipMalloc( (void**)&devB,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
reverseArray<<<1,T>>>(devA,devB);
hipMemcpy( b, devB, size, hipMemcpyDeviceToHost);
hipFree(devA);
hipFree(devB);
printf("\nNew A array \n");
for (i = 0;i < N; i++){
printf("%d ",b[i]);
}
printf("\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 256
#define T 256
__global__ void reverseArray(int *A ,int *B){
int i = threadIdx.x;
B[i] = A[(N - 1) - i];
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof (int);
int a[N], b[N], *devA, *devB;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = i;
printf("%d ",a[i]);
}
hipMalloc( (void**)&devA,size);
hipMalloc( (void**)&devB,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
reverseArray<<<1,T>>>(devA,devB);
hipMemcpy( b, devB, size, hipMemcpyDeviceToHost);
hipFree(devA);
hipFree(devB);
printf("\nNew A array \n");
for (i = 0;i < N; i++){
printf("%d ",b[i]);
}
printf("\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12reverseArrayPiS_
.globl _Z12reverseArrayPiS_
.p2align 8
.type _Z12reverseArrayPiS_,@function
_Z12reverseArrayPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_sub_nc_u32_e32 v1, 0xff, v0
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12reverseArrayPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12reverseArrayPiS_, .Lfunc_end0-_Z12reverseArrayPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12reverseArrayPiS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z12reverseArrayPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#define N 256
#define T 256
__global__ void reverseArray(int *A ,int *B){
int i = threadIdx.x;
B[i] = A[(N - 1) - i];
}
int main (int argc, char *argv[]){
int i;
int size = N * sizeof (int);
int a[N], b[N], *devA, *devB;
printf("Original A array\n");
for (i = 0; i < N; i++){
a[i] = i;
printf("%d ",a[i]);
}
hipMalloc( (void**)&devA,size);
hipMalloc( (void**)&devB,size);
hipMemcpy( devA, a, size, hipMemcpyHostToDevice);
reverseArray<<<1,T>>>(devA,devB);
hipMemcpy( b, devB, size, hipMemcpyDeviceToHost);
hipFree(devA);
hipFree(devB);
printf("\nNew A array \n");
for (i = 0;i < N; i++){
printf("%d ",b[i]);
}
printf("\n");
} | .text
.file "Q3.hip"
.globl _Z27__device_stub__reverseArrayPiS_ # -- Begin function _Z27__device_stub__reverseArrayPiS_
.p2align 4, 0x90
.type _Z27__device_stub__reverseArrayPiS_,@function
_Z27__device_stub__reverseArrayPiS_: # @_Z27__device_stub__reverseArrayPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12reverseArrayPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__reverseArrayPiS_, .Lfunc_end0-_Z27__device_stub__reverseArrayPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 2144
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 1104(%rsp,%rbx,4)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
leaq 1104(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12reverseArrayPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12reverseArrayPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12reverseArrayPiS_,@object # @_Z12reverseArrayPiS_
.section .rodata,"a",@progbits
.globl _Z12reverseArrayPiS_
.p2align 3, 0x0
_Z12reverseArrayPiS_:
.quad _Z27__device_stub__reverseArrayPiS_
.size _Z12reverseArrayPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12reverseArrayPiS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Original A array"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nNew A array "
.size .Lstr.1, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__reverseArrayPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12reverseArrayPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12reverseArrayPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R2, -R4, 0xff, RZ ; /* 0x000000ff04027810 */
/* 0x001fd00007ffe1ff */
/*0050*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0205 */
/*0060*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0070*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fca00078e0205 */
/*0080*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0090*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00a0*/ BRA 0xa0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12reverseArrayPiS_
.globl _Z12reverseArrayPiS_
.p2align 8
.type _Z12reverseArrayPiS_,@function
_Z12reverseArrayPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_sub_nc_u32_e32 v1, 0xff, v0
v_lshlrev_b32_e32 v0, 2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v1, v[1:2], off
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12reverseArrayPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12reverseArrayPiS_, .Lfunc_end0-_Z12reverseArrayPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12reverseArrayPiS_
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z12reverseArrayPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001876b7_00000000-6_Q3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z34__device_stub__Z12reverseArrayPiS_PiS_
.type _Z34__device_stub__Z12reverseArrayPiS_PiS_, @function
_Z34__device_stub__Z12reverseArrayPiS_PiS_:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12reverseArrayPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z34__device_stub__Z12reverseArrayPiS_PiS_, .-_Z34__device_stub__Z12reverseArrayPiS_PiS_
.globl _Z12reverseArrayPiS_
.type _Z12reverseArrayPiS_, @function
_Z12reverseArrayPiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z12reverseArrayPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12reverseArrayPiS_, .-_Z12reverseArrayPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Original A array\n"
.LC1:
.string "%d "
.LC2:
.string "\nNew A array \n"
.LC3:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $2112, %rsp
.cfi_def_cfa_offset 2144
movq %fs:40, %rax
movq %rax, 2104(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $0, %ebx
leaq .LC1(%rip), %rbp
.L12:
movl %ebx, %edx
movl %ebx, 48(%rsp,%rbx,4)
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $256, %rbx
jne .L12
leaq 8(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1024, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $1024, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
leaq 1072(%rsp), %rbx
movl $2, %ecx
movl $1024, %edx
movq 16(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 2096(%rsp), %r12
leaq .LC1(%rip), %rbp
.L14:
movl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L14
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 2104(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $2112, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z34__device_stub__Z12reverseArrayPiS_PiS_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z12reverseArrayPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z12reverseArrayPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Q3.hip"
.globl _Z27__device_stub__reverseArrayPiS_ # -- Begin function _Z27__device_stub__reverseArrayPiS_
.p2align 4, 0x90
.type _Z27__device_stub__reverseArrayPiS_,@function
_Z27__device_stub__reverseArrayPiS_: # @_Z27__device_stub__reverseArrayPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z12reverseArrayPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z27__device_stub__reverseArrayPiS_, .Lfunc_end0-_Z27__device_stub__reverseArrayPiS_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 2144
.cfi_offset %rbx, -16
movl $.Lstr, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %ebx, 1104(%rsp,%rbx,4)
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq %rsp, %rdi
movl $1024, %esi # imm = 0x400
callq hipMalloc
movq 8(%rsp), %rdi
leaq 1104(%rsp), %rsi
movl $1024, %edx # imm = 0x400
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12reverseArrayPiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rsi
leaq 80(%rsp), %rdi
movl $1024, %edx # imm = 0x400
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movl $.Lstr.1, %edi
callq puts@PLT
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 80(%rsp,%rbx,4), %esi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $256, %rbx # imm = 0x100
jne .LBB1_5
# %bb.6:
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
addq $2128, %rsp # imm = 0x850
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12reverseArrayPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12reverseArrayPiS_,@object # @_Z12reverseArrayPiS_
.section .rodata,"a",@progbits
.globl _Z12reverseArrayPiS_
.p2align 3, 0x0
_Z12reverseArrayPiS_:
.quad _Z27__device_stub__reverseArrayPiS_
.size _Z12reverseArrayPiS_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%d "
.size .L.str.1, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12reverseArrayPiS_"
.size .L__unnamed_1, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Original A array"
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nNew A array "
.size .Lstr.1, 14
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__reverseArrayPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12reverseArrayPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define N 2
__global__ void foo()
{
__shared__ int A[8];
A[0] = threadIdx.x;
} | code for sm_80
Function : _Z3foov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define N 2
__global__ void foo()
{
__shared__ int A[8];
A[0] = threadIdx.x;
} | .file "tmpxft_001a29d7_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21__device_stub__Z3foovv
.type _Z21__device_stub__Z3foovv, @function
_Z21__device_stub__Z3foovv:
.LFB2081:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z3foov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z21__device_stub__Z3foovv, .-_Z21__device_stub__Z3foovv
.globl _Z3foov
.type _Z3foov, @function
_Z3foov:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z3foovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z3foov, .-_Z3foov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3foov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3foov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
#define N 2
__global__ void foo()
{
__shared__ int A[8];
A[0] = threadIdx.x;
} | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 2
__global__ void foo()
{
__shared__ int A[8];
A[0] = threadIdx.x;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 2
__global__ void foo()
{
__shared__ int A[8];
A[0] = threadIdx.x;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3foov
.globl _Z3foov
.p2align 8
.type _Z3foov,@function
_Z3foov:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3foov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3foov, .Lfunc_end0-_Z3foov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3foov
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3foov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#define N 2
__global__ void foo()
{
__shared__ int A[8];
A[0] = threadIdx.x;
} | .text
.file "main.hip"
.globl _Z18__device_stub__foov # -- Begin function _Z18__device_stub__foov
.p2align 4, 0x90
.type _Z18__device_stub__foov,@function
_Z18__device_stub__foov: # @_Z18__device_stub__foov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3foov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z18__device_stub__foov, .Lfunc_end0-_Z18__device_stub__foov
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3foov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3foov,@object # @_Z3foov
.section .rodata,"a",@progbits
.globl _Z3foov
.p2align 3, 0x0
_Z3foov:
.quad _Z18__device_stub__foov
.size _Z3foov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3foov"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__foov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3foov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3foov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3foov
.globl _Z3foov
.p2align 8
.type _Z3foov,@function
_Z3foov:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3foov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 0
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 0
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3foov, .Lfunc_end0-_Z3foov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args: []
.group_segment_fixed_size: 0
.kernarg_segment_align: 4
.kernarg_segment_size: 0
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3foov
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z3foov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a29d7_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21__device_stub__Z3foovv
.type _Z21__device_stub__Z3foovv, @function
_Z21__device_stub__Z3foovv:
.LFB2081:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z3foov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z21__device_stub__Z3foovv, .-_Z21__device_stub__Z3foovv
.globl _Z3foov
.type _Z3foov, @function
_Z3foov:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z3foovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z3foov, .-_Z3foov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3foov"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3foov(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z18__device_stub__foov # -- Begin function _Z18__device_stub__foov
.p2align 4, 0x90
.type _Z18__device_stub__foov,@function
_Z18__device_stub__foov: # @_Z18__device_stub__foov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z3foov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z18__device_stub__foov, .Lfunc_end0-_Z18__device_stub__foov
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3foov, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3foov,@object # @_Z3foov
.section .rodata,"a",@progbits
.globl _Z3foov
.p2align 3, 0x0
_Z3foov:
.quad _Z18__device_stub__foov
.size _Z3foov, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3foov"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__foov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3foov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void rfi_gpu_kernel(unsigned short *d_input, int nchans, int nsamp)
{
int c = blockIdx.x * blockDim.x + threadIdx.x;
int count =0;
float stdev = 1000000.0f;
float mean = 0.0f;
float sum = 0.0f;
float sum_squares = 0.0f;
float cutoff = (4.0f * stdev);
for(int out=0; out<4; out++) {
sum = 0.0f;
sum_squares = 0.0f;
count = 0;
for(int t = 0; t < nsamp; t++) {
float data=(float)d_input[c*nsamp + t];
if(data < (mean + cutoff) && data > (mean - cutoff) ) {
sum+=data;
sum_squares+=(data*data);
count++;
}
}
mean = (sum/(float)count);
sum_squares = ((sum_squares / count) - (mean * mean));
stdev = sqrt(sum_squares);
cutoff = (4.0f * stdev);
}
for(int t = 0; t < nsamp-4; t++) {
float data=0.0f;
for(int x = 0; x<4; x++) data+=(float)d_input[c*nsamp + t + x];
data=data*0.25f;
//float data=(float)d_input[c*nsamp + t];
if(data > (mean + cutoff) || data < (mean - cutoff)) {
d_input[c*nsamp + t]=(unsigned short)mean;
}
}
} | .file "tmpxft_00027801_00000000-6_rfi_gpu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii
.type _Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii, @function
_Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14rfi_gpu_kernelPtii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii, .-_Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii
.globl _Z14rfi_gpu_kernelPtii
.type _Z14rfi_gpu_kernelPtii, @function
_Z14rfi_gpu_kernelPtii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14rfi_gpu_kernelPtii, .-_Z14rfi_gpu_kernelPtii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14rfi_gpu_kernelPtii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14rfi_gpu_kernelPtii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void rfi_gpu_kernel(unsigned short *d_input, int nchans, int nsamp)
{
int c = blockIdx.x * blockDim.x + threadIdx.x;
int count =0;
float stdev = 1000000.0f;
float mean = 0.0f;
float sum = 0.0f;
float sum_squares = 0.0f;
float cutoff = (4.0f * stdev);
for(int out=0; out<4; out++) {
sum = 0.0f;
sum_squares = 0.0f;
count = 0;
for(int t = 0; t < nsamp; t++) {
float data=(float)d_input[c*nsamp + t];
if(data < (mean + cutoff) && data > (mean - cutoff) ) {
sum+=data;
sum_squares+=(data*data);
count++;
}
}
mean = (sum/(float)count);
sum_squares = ((sum_squares / count) - (mean * mean));
stdev = sqrt(sum_squares);
cutoff = (4.0f * stdev);
}
for(int t = 0; t < nsamp-4; t++) {
float data=0.0f;
for(int x = 0; x<4; x++) data+=(float)d_input[c*nsamp + t + x];
data=data*0.25f;
//float data=(float)d_input[c*nsamp + t];
if(data > (mean + cutoff) || data < (mean - cutoff)) {
d_input[c*nsamp + t]=(unsigned short)mean;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rfi_gpu_kernel(unsigned short *d_input, int nchans, int nsamp)
{
int c = blockIdx.x * blockDim.x + threadIdx.x;
int count =0;
float stdev = 1000000.0f;
float mean = 0.0f;
float sum = 0.0f;
float sum_squares = 0.0f;
float cutoff = (4.0f * stdev);
for(int out=0; out<4; out++) {
sum = 0.0f;
sum_squares = 0.0f;
count = 0;
for(int t = 0; t < nsamp; t++) {
float data=(float)d_input[c*nsamp + t];
if(data < (mean + cutoff) && data > (mean - cutoff) ) {
sum+=data;
sum_squares+=(data*data);
count++;
}
}
mean = (sum/(float)count);
sum_squares = ((sum_squares / count) - (mean * mean));
stdev = sqrt(sum_squares);
cutoff = (4.0f * stdev);
}
for(int t = 0; t < nsamp-4; t++) {
float data=0.0f;
for(int x = 0; x<4; x++) data+=(float)d_input[c*nsamp + t + x];
data=data*0.25f;
//float data=(float)d_input[c*nsamp + t];
if(data > (mean + cutoff) || data < (mean - cutoff)) {
d_input[c*nsamp + t]=(unsigned short)mean;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rfi_gpu_kernel(unsigned short *d_input, int nchans, int nsamp)
{
int c = blockIdx.x * blockDim.x + threadIdx.x;
int count =0;
float stdev = 1000000.0f;
float mean = 0.0f;
float sum = 0.0f;
float sum_squares = 0.0f;
float cutoff = (4.0f * stdev);
for(int out=0; out<4; out++) {
sum = 0.0f;
sum_squares = 0.0f;
count = 0;
for(int t = 0; t < nsamp; t++) {
float data=(float)d_input[c*nsamp + t];
if(data < (mean + cutoff) && data > (mean - cutoff) ) {
sum+=data;
sum_squares+=(data*data);
count++;
}
}
mean = (sum/(float)count);
sum_squares = ((sum_squares / count) - (mean * mean));
stdev = sqrt(sum_squares);
cutoff = (4.0f * stdev);
}
for(int t = 0; t < nsamp-4; t++) {
float data=0.0f;
for(int x = 0; x<4; x++) data+=(float)d_input[c*nsamp + t + x];
data=data*0.25f;
//float data=(float)d_input[c*nsamp + t];
if(data > (mean + cutoff) || data < (mean - cutoff)) {
d_input[c*nsamp + t]=(unsigned short)mean;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14rfi_gpu_kernelPtii
.globl _Z14rfi_gpu_kernelPtii
.p2align 8
.type _Z14rfi_gpu_kernelPtii,@function
_Z14rfi_gpu_kernelPtii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s4, s[0:1], 0xc
v_dual_mov_b32 v5, 0x4a742400 :: v_dual_mov_b32 v4, 0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_cmp_gt_i32 s4, 0
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x0
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v1, s4
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 1, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_branch .LBB0_2
.LBB0_1:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v5, v8
s_add_i32 s6, s6, 1
s_cmp_eq_u32 s6, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_scale_f32 v4, null, v5, v5, v7
v_div_scale_f32 v8, null, v5, v5, v6
v_div_scale_f32 v13, vcc_lo, v7, v5, v7
v_rcp_f32_e32 v9, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v10, v8
s_waitcnt_depctr 0xfff
v_fma_f32 v11, -v4, v9, 1.0
v_fma_f32 v12, -v8, v10, 1.0
v_dual_fmac_f32 v9, v11, v9 :: v_dual_fmac_f32 v10, v12, v10
v_div_scale_f32 v11, s0, v6, v5, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v12, v13, v9
v_mul_f32_e32 v14, v11, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v15, -v4, v12, v13
v_fma_f32 v16, -v8, v14, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v15, v9
v_fmac_f32_e32 v14, v16, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v4, -v4, v12, v13
v_fma_f32 v8, -v8, v14, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_fmas_f32 v4, v4, v9, v12
s_mov_b32 vcc_lo, s0
v_div_fmas_f32 v8, v8, v10, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fixup_f32 v4, v4, v5, v7
v_div_fixup_f32 v5, v8, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v4, v4, v5
v_mul_f32_e32 v6, 0x4f800000, v5
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_sqrt_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v7, -1, v6
v_add_nc_u32_e32 v8, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v6, v5
v_fma_f32 v10, -v8, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v9
v_cndmask_b32_e64 v6, v6, v7, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v10
v_cndmask_b32_e64 v6, v6, v8, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, 0x37800000, v6
v_cndmask_b32_e32 v6, v6, v7, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v5, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v5, v6, v5, vcc_lo
v_mul_f32_e32 v5, 4.0, v5
s_cbranch_scc1 .LBB0_5
.LBB0_2:
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
v_mov_b32_e32 v8, 0
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_1
v_dual_add_f32 v9, v4, v5 :: v_dual_mov_b32 v8, 0
v_dual_sub_f32 v10, v4, v5 :: v_dual_mov_b32 v5, v3
v_dual_mov_b32 v6, 0 :: v_dual_mov_b32 v7, 0
v_mov_b32_e32 v4, v2
s_mov_b32 s7, s4
.p2align 6
.LBB0_4:
global_load_u16 v11, v[4:5], off
v_add_co_u32 v4, s1, v4, 2
s_add_i32 s7, s7, -1
s_waitcnt vmcnt(0)
v_cvt_f32_u32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_cmp_gt_f32_e32 vcc_lo, v9, v11
v_cmp_lt_f32_e64 s0, v10, v11
v_mul_f32_e32 v12, v11, v11
s_and_b32 vcc_lo, vcc_lo, s0
v_add_co_ci_u32_e64 v5, s0, 0, v5, s1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v12, 0x80000000, v12, vcc_lo
v_cndmask_b32_e32 v11, 0x80000000, v11, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
s_cmp_eq_u32 s7, 0
v_dual_add_f32 v6, v6, v12 :: v_dual_add_f32 v7, v7, v11
s_cbranch_scc0 .LBB0_4
s_branch .LBB0_1
.LBB0_5:
s_cmp_lt_i32 s4, 5
s_cbranch_scc1 .LBB0_12
v_lshlrev_b64 v[6:7], 1, v[0:1]
v_add_f32_e32 v1, v4, v5
v_sub_f32_e32 v2, v4, v5
v_cvt_u32_f32_e32 v3, v4
s_add_i32 s4, s4, -5
s_mov_b32 s5, 0
v_add_co_u32 v4, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v4, vcc_lo, v4, 2
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_add_i32 s0, s5, 1
s_cmp_eq_u32 s5, s4
s_mov_b32 s5, s0
s_cbranch_scc1 .LBB0_12
.LBB0_8:
v_mov_b32_e32 v6, 0
s_mov_b64 s[0:1], 0
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1)
v_add_co_u32 v7, vcc_lo, v4, s0
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v5, vcc_lo
s_add_u32 s0, s0, 2
s_addc_u32 s1, s1, 0
s_cmp_eq_u32 s0, 8
global_load_u16 v7, v[7:8], off
s_waitcnt vmcnt(0)
v_cvt_f32_u32_e32 v7, v7
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v6, v7
s_cbranch_scc0 .LBB0_9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, 0x3e800000, v6
v_cmp_gt_f32_e32 vcc_lo, v6, v1
v_cmp_lt_f32_e64 s0, v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s1, vcc_lo, s0
s_and_saveexec_b32 s0, s1
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v6, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v7, 31, v6
v_lshlrev_b64 v[6:7], 1, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_store_b16 v[6:7], v3, off
s_branch .LBB0_7
.LBB0_12:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14rfi_gpu_kernelPtii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14rfi_gpu_kernelPtii, .Lfunc_end0-_Z14rfi_gpu_kernelPtii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14rfi_gpu_kernelPtii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14rfi_gpu_kernelPtii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rfi_gpu_kernel(unsigned short *d_input, int nchans, int nsamp)
{
int c = blockIdx.x * blockDim.x + threadIdx.x;
int count =0;
float stdev = 1000000.0f;
float mean = 0.0f;
float sum = 0.0f;
float sum_squares = 0.0f;
float cutoff = (4.0f * stdev);
for(int out=0; out<4; out++) {
sum = 0.0f;
sum_squares = 0.0f;
count = 0;
for(int t = 0; t < nsamp; t++) {
float data=(float)d_input[c*nsamp + t];
if(data < (mean + cutoff) && data > (mean - cutoff) ) {
sum+=data;
sum_squares+=(data*data);
count++;
}
}
mean = (sum/(float)count);
sum_squares = ((sum_squares / count) - (mean * mean));
stdev = sqrt(sum_squares);
cutoff = (4.0f * stdev);
}
for(int t = 0; t < nsamp-4; t++) {
float data=0.0f;
for(int x = 0; x<4; x++) data+=(float)d_input[c*nsamp + t + x];
data=data*0.25f;
//float data=(float)d_input[c*nsamp + t];
if(data > (mean + cutoff) || data < (mean - cutoff)) {
d_input[c*nsamp + t]=(unsigned short)mean;
}
}
} | .text
.file "rfi_gpu_kernel.hip"
.globl _Z29__device_stub__rfi_gpu_kernelPtii # -- Begin function _Z29__device_stub__rfi_gpu_kernelPtii
.p2align 4, 0x90
.type _Z29__device_stub__rfi_gpu_kernelPtii,@function
_Z29__device_stub__rfi_gpu_kernelPtii: # @_Z29__device_stub__rfi_gpu_kernelPtii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14rfi_gpu_kernelPtii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__rfi_gpu_kernelPtii, .Lfunc_end0-_Z29__device_stub__rfi_gpu_kernelPtii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14rfi_gpu_kernelPtii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14rfi_gpu_kernelPtii,@object # @_Z14rfi_gpu_kernelPtii
.section .rodata,"a",@progbits
.globl _Z14rfi_gpu_kernelPtii
.p2align 3, 0x0
_Z14rfi_gpu_kernelPtii:
.quad _Z29__device_stub__rfi_gpu_kernelPtii
.size _Z14rfi_gpu_kernelPtii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14rfi_gpu_kernelPtii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__rfi_gpu_kernelPtii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14rfi_gpu_kernelPtii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00027801_00000000-6_rfi_gpu_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii
.type _Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii, @function
_Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z14rfi_gpu_kernelPtii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii, .-_Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii
.globl _Z14rfi_gpu_kernelPtii
.type _Z14rfi_gpu_kernelPtii, @function
_Z14rfi_gpu_kernelPtii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z14rfi_gpu_kernelPtiiPtii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14rfi_gpu_kernelPtii, .-_Z14rfi_gpu_kernelPtii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14rfi_gpu_kernelPtii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14rfi_gpu_kernelPtii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rfi_gpu_kernel.hip"
.globl _Z29__device_stub__rfi_gpu_kernelPtii # -- Begin function _Z29__device_stub__rfi_gpu_kernelPtii
.p2align 4, 0x90
.type _Z29__device_stub__rfi_gpu_kernelPtii,@function
_Z29__device_stub__rfi_gpu_kernelPtii: # @_Z29__device_stub__rfi_gpu_kernelPtii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z14rfi_gpu_kernelPtii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z29__device_stub__rfi_gpu_kernelPtii, .Lfunc_end0-_Z29__device_stub__rfi_gpu_kernelPtii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14rfi_gpu_kernelPtii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14rfi_gpu_kernelPtii,@object # @_Z14rfi_gpu_kernelPtii
.section .rodata,"a",@progbits
.globl _Z14rfi_gpu_kernelPtii
.p2align 3, 0x0
_Z14rfi_gpu_kernelPtii:
.quad _Z29__device_stub__rfi_gpu_kernelPtii
.size _Z14rfi_gpu_kernelPtii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14rfi_gpu_kernelPtii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__rfi_gpu_kernelPtii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14rfi_gpu_kernelPtii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#define N 10
#define THREADS 1
#define BLOCKS 1
// size of array
__global__ void add(int *a,int *b, int *c)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N)
{
c[tid] = a[tid]+b[tid];
}
}
int main(void)
{
int T = 100; // threads per block
int B = 2; // blocks per grid
// VS may not like defined constants in <<< >>>
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**)&dev_a,N * sizeof(int));
cudaMalloc((void**)&dev_b,N * sizeof(int));
cudaMalloc((void**)&dev_c,N * sizeof(int));
for(int i=0;i<N;i++)
{
a[i] = i;
b[i] = i*1;
}
cudaMemcpy(dev_a, a , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , N*sizeof(int),cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float elapsedTime;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
add<<<B,T>>>(dev_a,dev_b,dev_c);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventRecord(stop, 0);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(c, dev_c, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
// printf("Execution Time: %1.10f\n", elapsedTime);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#define N 10
#define THREADS 1
#define BLOCKS 1
// size of array
__global__ void add(int *a,int *b, int *c)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N)
{
c[tid] = a[tid]+b[tid];
}
}
int main(void)
{
int T = 100; // threads per block
int B = 2; // blocks per grid
// VS may not like defined constants in <<< >>>
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**)&dev_a,N * sizeof(int));
cudaMalloc((void**)&dev_b,N * sizeof(int));
cudaMalloc((void**)&dev_c,N * sizeof(int));
for(int i=0;i<N;i++)
{
a[i] = i;
b[i] = i*1;
}
cudaMemcpy(dev_a, a , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , N*sizeof(int),cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float elapsedTime;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
add<<<B,T>>>(dev_a,dev_b,dev_c);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventRecord(stop, 0);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(c, dev_c, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
// printf("Execution Time: %1.10f\n", elapsedTime);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | .file "tmpxft_001b07ea_00000000-6_VectorAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d+%d=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $216, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 64(%rsp,%rax,4)
movl %eax, 112(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 160(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
leaq 160(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 112(%rsp,%rbx), %ecx
movl 64(%rsp,%rbx), %edx
movl 160(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <stdlib.h>
#define N 10
#define THREADS 1
#define BLOCKS 1
// size of array
__global__ void add(int *a,int *b, int *c)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N)
{
c[tid] = a[tid]+b[tid];
}
}
int main(void)
{
int T = 100; // threads per block
int B = 2; // blocks per grid
// VS may not like defined constants in <<< >>>
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
cudaMalloc((void**)&dev_a,N * sizeof(int));
cudaMalloc((void**)&dev_b,N * sizeof(int));
cudaMalloc((void**)&dev_c,N * sizeof(int));
for(int i=0;i<N;i++)
{
a[i] = i;
b[i] = i*1;
}
cudaMemcpy(dev_a, a , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b , N*sizeof(int),cudaMemcpyHostToDevice);
cudaMemcpy(dev_c, c , N*sizeof(int),cudaMemcpyHostToDevice);
cudaEvent_t start, stop;
float elapsedTime;
cudaEventCreate(&start);
cudaEventCreate(&stop);
cudaEventRecord(start, 0);
add<<<B,T>>>(dev_a,dev_b,dev_c);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventRecord(stop, 0);
cudaEventElapsedTime(&elapsedTime, start, stop);
cudaEventDestroy(start);
cudaEventDestroy(stop);
cudaMemcpy(c, dev_c, N*sizeof(int), cudaMemcpyDeviceToHost);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
// printf("Execution Time: %1.10f\n", elapsedTime);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define N 10
#define THREADS 1
#define BLOCKS 1
// size of array
__global__ void add(int *a,int *b, int *c)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N)
{
c[tid] = a[tid]+b[tid];
}
}
int main(void)
{
int T = 100; // threads per block
int B = 2; // blocks per grid
// VS may not like defined constants in <<< >>>
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**)&dev_a,N * sizeof(int));
hipMalloc((void**)&dev_b,N * sizeof(int));
hipMalloc((void**)&dev_c,N * sizeof(int));
for(int i=0;i<N;i++)
{
a[i] = i;
b[i] = i*1;
}
hipMemcpy(dev_a, a , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , N*sizeof(int),hipMemcpyHostToDevice);
hipEvent_t start, stop;
float elapsedTime;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
add<<<B,T>>>(dev_a,dev_b,dev_c);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventRecord(stop, 0);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(c, dev_c, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
// printf("Execution Time: %1.10f\n", elapsedTime);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define N 10
#define THREADS 1
#define BLOCKS 1
// size of array
__global__ void add(int *a,int *b, int *c)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N)
{
c[tid] = a[tid]+b[tid];
}
}
int main(void)
{
int T = 100; // threads per block
int B = 2; // blocks per grid
// VS may not like defined constants in <<< >>>
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**)&dev_a,N * sizeof(int));
hipMalloc((void**)&dev_b,N * sizeof(int));
hipMalloc((void**)&dev_c,N * sizeof(int));
for(int i=0;i<N;i++)
{
a[i] = i;
b[i] = i*1;
}
hipMemcpy(dev_a, a , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , N*sizeof(int),hipMemcpyHostToDevice);
hipEvent_t start, stop;
float elapsedTime;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
add<<<B,T>>>(dev_a,dev_b,dev_c);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventRecord(stop, 0);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(c, dev_c, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
// printf("Execution Time: %1.10f\n", elapsedTime);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 10, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#define N 10
#define THREADS 1
#define BLOCKS 1
// size of array
__global__ void add(int *a,int *b, int *c)
{
int tid = blockIdx.x * blockDim.x + threadIdx.x;
if(tid < N)
{
c[tid] = a[tid]+b[tid];
}
}
int main(void)
{
int T = 100; // threads per block
int B = 2; // blocks per grid
// VS may not like defined constants in <<< >>>
int a[N],b[N],c[N];
int *dev_a, *dev_b, *dev_c;
hipMalloc((void**)&dev_a,N * sizeof(int));
hipMalloc((void**)&dev_b,N * sizeof(int));
hipMalloc((void**)&dev_c,N * sizeof(int));
for(int i=0;i<N;i++)
{
a[i] = i;
b[i] = i*1;
}
hipMemcpy(dev_a, a , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_b, b , N*sizeof(int),hipMemcpyHostToDevice);
hipMemcpy(dev_c, c , N*sizeof(int),hipMemcpyHostToDevice);
hipEvent_t start, stop;
float elapsedTime;
hipEventCreate(&start);
hipEventCreate(&stop);
hipEventRecord(start, 0);
add<<<B,T>>>(dev_a,dev_b,dev_c);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventRecord(stop, 0);
hipEventElapsedTime(&elapsedTime, start, stop);
hipEventDestroy(start);
hipEventDestroy(stop);
hipMemcpy(c, dev_c, N*sizeof(int), hipMemcpyDeviceToHost);
for(int i=0;i<N;i++)
{
printf("%d+%d=%d\n",a[i],b[i],c[i]);
}
// printf("Execution Time: %1.10f\n", elapsedTime);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
return 0;
} | .text
.file "VectorAddition.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -16
leaq 32(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 240(%rsp,%rax,4)
movl %eax, 192(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
movq 32(%rsp), %rdi
leaq 240(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 98(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 240(%rsp,%rbx,4), %esi
movl 192(%rsp,%rbx,4), %edx
movl 144(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d+%d=%d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GT.AND P0, PT, R6, 0x9, PT ; /* 0x000000090600780c */
/* 0x000fda0003f04270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addPiS_S_
.globl _Z3addPiS_S_
.p2align 8
.type _Z3addPiS_S_,@function
_Z3addPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 10, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addPiS_S_, .Lfunc_end0-_Z3addPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3addPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b07ea_00000000-6_VectorAddition.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z3addPiS_S_PiS_S_
.type _Z26__device_stub__Z3addPiS_S_PiS_S_, @function
_Z26__device_stub__Z3addPiS_S_PiS_S_:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3addPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z3addPiS_S_PiS_S_, .-_Z26__device_stub__Z3addPiS_S_PiS_S_
.globl _Z3addPiS_S_
.type _Z3addPiS_S_, @function
_Z3addPiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z3addPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addPiS_S_, .-_Z3addPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d+%d=%d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $216, %rsp
.cfi_def_cfa_offset 240
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $0, %eax
.L12:
movl %eax, 64(%rsp,%rax,4)
movl %eax, 112(%rsp,%rax,4)
addq $1, %rax
cmpq $10, %rax
jne .L12
leaq 64(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq (%rsp), %rdi
call cudaMemcpy@PLT
leaq 112(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 160(%rsp), %rsi
movl $1, %ecx
movl $40, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
leaq 32(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movl $100, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $2, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
movq 32(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0, %esi
movq 32(%rsp), %rdi
call cudaEventRecord@PLT
leaq 52(%rsp), %rdi
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
call cudaEventElapsedTime@PLT
movq 24(%rsp), %rdi
call cudaEventDestroy@PLT
movq 32(%rsp), %rdi
call cudaEventDestroy@PLT
leaq 160(%rsp), %rdi
movl $2, %ecx
movl $40, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %rbp
.L14:
movl 112(%rsp,%rbx), %ecx
movl 64(%rsp,%rbx), %edx
movl 160(%rsp,%rbx), %r8d
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L14
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z3addPiS_S_PiS_S_
jmp .L13
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3addPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "VectorAddition.hip"
.globl _Z18__device_stub__addPiS_S_ # -- Begin function _Z18__device_stub__addPiS_S_
.p2align 4, 0x90
.type _Z18__device_stub__addPiS_S_,@function
_Z18__device_stub__addPiS_S_: # @_Z18__device_stub__addPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z18__device_stub__addPiS_S_, .Lfunc_end0-_Z18__device_stub__addPiS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -16
leaq 32(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 24(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %eax, 240(%rsp,%rax,4)
movl %eax, 192(%rsp,%rax,4)
incq %rax
cmpq $10, %rax
jne .LBB1_1
# %bb.2:
movq 32(%rsp), %rdi
leaq 240(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
leaq 192(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 144(%rsp), %rsi
movl $40, %edx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
callq hipEventCreate
movq %rsp, %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 98(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z3addPiS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq (%rsp), %rdi
callq hipEventSynchronize
movq (%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 16(%rsp), %rsi
movq (%rsp), %rdx
leaq 112(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
callq hipEventDestroy
movq (%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rsi
leaq 144(%rsp), %rdi
movl $40, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_5: # =>This Inner Loop Header: Depth=1
movl 240(%rsp,%rbx,4), %esi
movl 192(%rsp,%rbx,4), %edx
movl 144(%rsp,%rbx,4), %ecx
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $10, %rbx
jne .LBB1_5
# %bb.6:
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $288, %rsp # imm = 0x120
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addPiS_S_,@object # @_Z3addPiS_S_
.section .rodata,"a",@progbits
.globl _Z3addPiS_S_
.p2align 3, 0x0
_Z3addPiS_S_:
.quad _Z18__device_stub__addPiS_S_
.size _Z3addPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d+%d=%d\n"
.size .L.str, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addPiS_S_"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#define SIZE 16
#define BLOCKSIZE 4
extern "C" void outer_compute(int *in_arr, int *out_arr);
__device__ int compare(int a, int b) {
if (a == b) return 1;
return 0;
}
__global__ void compute(int *d_in,int *d_out) {
int i;
d_out[threadIdx.x] = 0;
for (i=0; i<SIZE/BLOCKSIZE; i++) {
d_out[threadIdx.x] += compare(d_in[i*BLOCKSIZE+threadIdx.x],6);
}
}
void outer_compute(int *h_in_array, int *h_out_array) {
int *d_in_array, *d_out_array;
/* allocate memory for device copies, and copy input to device */
cudaMalloc((void **) &d_in_array,SIZE*sizeof(int));
cudaMalloc((void **) &d_out_array,BLOCKSIZE*sizeof(int));
cudaMemcpy(d_in_array,h_in_array,SIZE*sizeof(int),cudaMemcpyHostToDevice);
/* compute number of appearances of 8 for subset of data in each thread! */
compute<<<1,BLOCKSIZE,0>>>(d_in_array,d_out_array);
cudaThreadSynchronize();
cudaMemcpy(h_out_array,d_out_array,BLOCKSIZE*sizeof(int),cudaMemcpyDeviceToHost);
} | code for sm_80
Function : _Z7computePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fc800078e0005 */
/*0050*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0005 */
/*0060*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*0070*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.NE.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x004fc80003f05270 */
/*0090*/ SEL R7, RZ, 0x1, P0 ; /* 0x00000001ff077807 */
/* 0x000fca0000000000 */
/*00a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*00b0*/ LDG.E R0, [R4.64+0x10] ; /* 0x0000100404007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fe40007ffe0ff */
/*00d0*/ ISETP.NE.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 IMAD.MOV R9, RZ, RZ, R7 ; /* 0x000000ffff090224 */
/* 0x000fca00078e0207 */
/*00f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0100*/ LDG.E R0, [R4.64+0x20] ; /* 0x0000200404007981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x000fe40007ffe0ff */
/*0120*/ ISETP.NE.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x004fda0003f05270 */
/*0130*/ @P0 IMAD.MOV R11, RZ, RZ, R9 ; /* 0x000000ffff0b0224 */
/* 0x000fca00078e0209 */
/*0140*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0150*/ LDG.E R0, [R4.64+0x30] ; /* 0x0000300404007981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IADD3 R7, R11, 0x1, RZ ; /* 0x000000010b077810 */
/* 0x001fe40007ffe0ff */
/*0170*/ ISETP.NE.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x004fda0003f05270 */
/*0180*/ @P0 IMAD.MOV R7, RZ, RZ, R11 ; /* 0x000000ffff070224 */
/* 0x000fca00078e020b */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#define SIZE 16
#define BLOCKSIZE 4
extern "C" void outer_compute(int *in_arr, int *out_arr);
__device__ int compare(int a, int b) {
if (a == b) return 1;
return 0;
}
__global__ void compute(int *d_in,int *d_out) {
int i;
d_out[threadIdx.x] = 0;
for (i=0; i<SIZE/BLOCKSIZE; i++) {
d_out[threadIdx.x] += compare(d_in[i*BLOCKSIZE+threadIdx.x],6);
}
}
void outer_compute(int *h_in_array, int *h_out_array) {
int *d_in_array, *d_out_array;
/* allocate memory for device copies, and copy input to device */
cudaMalloc((void **) &d_in_array,SIZE*sizeof(int));
cudaMalloc((void **) &d_out_array,BLOCKSIZE*sizeof(int));
cudaMemcpy(d_in_array,h_in_array,SIZE*sizeof(int),cudaMemcpyHostToDevice);
/* compute number of appearances of 8 for subset of data in each thread! */
compute<<<1,BLOCKSIZE,0>>>(d_in_array,d_out_array);
cudaThreadSynchronize();
cudaMemcpy(h_out_array,d_out_array,BLOCKSIZE*sizeof(int),cudaMemcpyDeviceToHost);
} | .file "tmpxft_00156c1d_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7compareii
.type _Z7compareii, @function
_Z7compareii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7compareii, .-_Z7compareii
.globl _Z28__device_stub__Z7computePiS_PiS_
.type _Z28__device_stub__Z7computePiS_PiS_, @function
_Z28__device_stub__Z7computePiS_PiS_:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7computePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z28__device_stub__Z7computePiS_PiS_, .-_Z28__device_stub__Z7computePiS_PiS_
.globl _Z7computePiS_
.type _Z7computePiS_, @function
_Z7computePiS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7computePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z7computePiS_, .-_Z7computePiS_
.globl outer_compute
.type outer_compute, @function
outer_compute:
.LFB2028:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $16, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7computePiS_PiS_
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size outer_compute, .-outer_compute
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#define SIZE 16
#define BLOCKSIZE 4
extern "C" void outer_compute(int *in_arr, int *out_arr);
__device__ int compare(int a, int b) {
if (a == b) return 1;
return 0;
}
__global__ void compute(int *d_in,int *d_out) {
int i;
d_out[threadIdx.x] = 0;
for (i=0; i<SIZE/BLOCKSIZE; i++) {
d_out[threadIdx.x] += compare(d_in[i*BLOCKSIZE+threadIdx.x],6);
}
}
void outer_compute(int *h_in_array, int *h_out_array) {
int *d_in_array, *d_out_array;
/* allocate memory for device copies, and copy input to device */
cudaMalloc((void **) &d_in_array,SIZE*sizeof(int));
cudaMalloc((void **) &d_out_array,BLOCKSIZE*sizeof(int));
cudaMemcpy(d_in_array,h_in_array,SIZE*sizeof(int),cudaMemcpyHostToDevice);
/* compute number of appearances of 8 for subset of data in each thread! */
compute<<<1,BLOCKSIZE,0>>>(d_in_array,d_out_array);
cudaThreadSynchronize();
cudaMemcpy(h_out_array,d_out_array,BLOCKSIZE*sizeof(int),cudaMemcpyDeviceToHost);
} | #include <hip/hip_runtime.h>
#define SIZE 16
#define BLOCKSIZE 4
extern "C" void outer_compute(int *in_arr, int *out_arr);
__device__ int compare(int a, int b) {
if (a == b) return 1;
return 0;
}
__global__ void compute(int *d_in,int *d_out) {
int i;
d_out[threadIdx.x] = 0;
for (i=0; i<SIZE/BLOCKSIZE; i++) {
d_out[threadIdx.x] += compare(d_in[i*BLOCKSIZE+threadIdx.x],6);
}
}
void outer_compute(int *h_in_array, int *h_out_array) {
int *d_in_array, *d_out_array;
/* allocate memory for device copies, and copy input to device */
hipMalloc((void **) &d_in_array,SIZE*sizeof(int));
hipMalloc((void **) &d_out_array,BLOCKSIZE*sizeof(int));
hipMemcpy(d_in_array,h_in_array,SIZE*sizeof(int),hipMemcpyHostToDevice);
/* compute number of appearances of 8 for subset of data in each thread! */
compute<<<1,BLOCKSIZE,0>>>(d_in_array,d_out_array);
hipDeviceSynchronize();
hipMemcpy(h_out_array,d_out_array,BLOCKSIZE*sizeof(int),hipMemcpyDeviceToHost);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define SIZE 16
#define BLOCKSIZE 4
extern "C" void outer_compute(int *in_arr, int *out_arr);
__device__ int compare(int a, int b) {
if (a == b) return 1;
return 0;
}
__global__ void compute(int *d_in,int *d_out) {
int i;
d_out[threadIdx.x] = 0;
for (i=0; i<SIZE/BLOCKSIZE; i++) {
d_out[threadIdx.x] += compare(d_in[i*BLOCKSIZE+threadIdx.x],6);
}
}
void outer_compute(int *h_in_array, int *h_out_array) {
int *d_in_array, *d_out_array;
/* allocate memory for device copies, and copy input to device */
hipMalloc((void **) &d_in_array,SIZE*sizeof(int));
hipMalloc((void **) &d_out_array,BLOCKSIZE*sizeof(int));
hipMemcpy(d_in_array,h_in_array,SIZE*sizeof(int),hipMemcpyHostToDevice);
/* compute number of appearances of 8 for subset of data in each thread! */
compute<<<1,BLOCKSIZE,0>>>(d_in_array,d_out_array);
hipDeviceSynchronize();
hipMemcpy(h_out_array,d_out_array,BLOCKSIZE*sizeof(int),hipMemcpyDeviceToHost);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePiS_
.globl _Z7computePiS_
.p2align 8
.type _Z7computePiS_,@function
_Z7computePiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v0, s4, s2, v5
v_add_co_u32 v3, s0, s0, v5
v_add_co_ci_u32_e64 v1, null, s3, 0, s4
v_add_co_ci_u32_e64 v4, null, s1, 0, s0
s_mov_b64 s[0:1], 0
global_store_b32 v5, v2, s[2:3]
.LBB0_1:
v_add_co_u32 v5, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_add_u32 s0, s0, 16
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 64
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 6, v5
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
global_store_b32 v[0:1], v2, off
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePiS_, .Lfunc_end0-_Z7computePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePiS_
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z7computePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define SIZE 16
#define BLOCKSIZE 4
extern "C" void outer_compute(int *in_arr, int *out_arr);
__device__ int compare(int a, int b) {
if (a == b) return 1;
return 0;
}
__global__ void compute(int *d_in,int *d_out) {
int i;
d_out[threadIdx.x] = 0;
for (i=0; i<SIZE/BLOCKSIZE; i++) {
d_out[threadIdx.x] += compare(d_in[i*BLOCKSIZE+threadIdx.x],6);
}
}
void outer_compute(int *h_in_array, int *h_out_array) {
int *d_in_array, *d_out_array;
/* allocate memory for device copies, and copy input to device */
hipMalloc((void **) &d_in_array,SIZE*sizeof(int));
hipMalloc((void **) &d_out_array,BLOCKSIZE*sizeof(int));
hipMemcpy(d_in_array,h_in_array,SIZE*sizeof(int),hipMemcpyHostToDevice);
/* compute number of appearances of 8 for subset of data in each thread! */
compute<<<1,BLOCKSIZE,0>>>(d_in_array,d_out_array);
hipDeviceSynchronize();
hipMemcpy(h_out_array,d_out_array,BLOCKSIZE*sizeof(int),hipMemcpyDeviceToHost);
} | .text
.file "simple.hip"
.globl _Z22__device_stub__computePiS_ # -- Begin function _Z22__device_stub__computePiS_
.p2align 4, 0x90
.type _Z22__device_stub__computePiS_,@function
_Z22__device_stub__computePiS_: # @_Z22__device_stub__computePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7computePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__computePiS_, .Lfunc_end0-_Z22__device_stub__computePiS_
.cfi_endproc
# -- End function
.globl outer_compute # -- Begin function outer_compute
.p2align 4, 0x90
.type outer_compute,@function
outer_compute: # @outer_compute
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size outer_compute, .Lfunc_end1-outer_compute
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePiS_,@object # @_Z7computePiS_
.section .rodata,"a",@progbits
.globl _Z7computePiS_
.p2align 3, 0x0
_Z7computePiS_:
.quad _Z22__device_stub__computePiS_
.size _Z7computePiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computePiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7computePiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0040*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fc800078e0005 */
/*0050*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0005 */
/*0060*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe8000c101904 */
/*0070*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ ISETP.NE.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x004fc80003f05270 */
/*0090*/ SEL R7, RZ, 0x1, P0 ; /* 0x00000001ff077807 */
/* 0x000fca0000000000 */
/*00a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e8000c101904 */
/*00b0*/ LDG.E R0, [R4.64+0x10] ; /* 0x0000100404007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IADD3 R9, R7, 0x1, RZ ; /* 0x0000000107097810 */
/* 0x000fe40007ffe0ff */
/*00d0*/ ISETP.NE.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x004fda0003f05270 */
/*00e0*/ @P0 IMAD.MOV R9, RZ, RZ, R7 ; /* 0x000000ffff090224 */
/* 0x000fca00078e0207 */
/*00f0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*0100*/ LDG.E R0, [R4.64+0x20] ; /* 0x0000200404007981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x000fe40007ffe0ff */
/*0120*/ ISETP.NE.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x004fda0003f05270 */
/*0130*/ @P0 IMAD.MOV R11, RZ, RZ, R9 ; /* 0x000000ffff0b0224 */
/* 0x000fca00078e0209 */
/*0140*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x000fe8000c101904 */
/*0150*/ LDG.E R0, [R4.64+0x30] ; /* 0x0000300404007981 */
/* 0x000ea2000c1e1900 */
/*0160*/ IADD3 R7, R11, 0x1, RZ ; /* 0x000000010b077810 */
/* 0x001fe40007ffe0ff */
/*0170*/ ISETP.NE.AND P0, PT, R0, 0x6, PT ; /* 0x000000060000780c */
/* 0x004fda0003f05270 */
/*0180*/ @P0 IMAD.MOV R7, RZ, RZ, R11 ; /* 0x000000ffff070224 */
/* 0x000fca00078e020b */
/*0190*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7computePiS_
.globl _Z7computePiS_
.p2align 8
.type _Z7computePiS_,@function
_Z7computePiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v5, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_co_u32 v0, s4, s2, v5
v_add_co_u32 v3, s0, s0, v5
v_add_co_ci_u32_e64 v1, null, s3, 0, s4
v_add_co_ci_u32_e64 v4, null, s1, 0, s0
s_mov_b64 s[0:1], 0
global_store_b32 v5, v2, s[2:3]
.LBB0_1:
v_add_co_u32 v5, vcc_lo, v3, s0
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
s_add_u32 s0, s0, 16
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s0, 64
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 6, v5
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
global_store_b32 v[0:1], v2, off
s_cbranch_scc1 .LBB0_1
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7computePiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 5
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7computePiS_, .Lfunc_end0-_Z7computePiS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7computePiS_
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z7computePiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00156c1d_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2031:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7compareii
.type _Z7compareii, @function
_Z7compareii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z7compareii, .-_Z7compareii
.globl _Z28__device_stub__Z7computePiS_PiS_
.type _Z28__device_stub__Z7computePiS_PiS_, @function
_Z28__device_stub__Z7computePiS_PiS_:
.LFB2053:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7computePiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z28__device_stub__Z7computePiS_PiS_, .-_Z28__device_stub__Z7computePiS_PiS_
.globl _Z7computePiS_
.type _Z7computePiS_, @function
_Z7computePiS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z7computePiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z7computePiS_, .-_Z7computePiS_
.globl outer_compute
.type outer_compute, @function
outer_compute:
.LFB2028:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $56, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $64, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $16, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $64, %edx
movq %rbp, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L14:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $16, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z28__device_stub__Z7computePiS_PiS_
jmp .L14
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2028:
.size outer_compute, .-outer_compute
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7computePiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computePiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple.hip"
.globl _Z22__device_stub__computePiS_ # -- Begin function _Z22__device_stub__computePiS_
.p2align 4, 0x90
.type _Z22__device_stub__computePiS_,@function
_Z22__device_stub__computePiS_: # @_Z22__device_stub__computePiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7computePiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__computePiS_, .Lfunc_end0-_Z22__device_stub__computePiS_
.cfi_endproc
# -- End function
.globl outer_compute # -- Begin function outer_compute
.p2align 4, 0x90
.type outer_compute,@function
outer_compute: # @outer_compute
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq %rsi, %rbx
movq %rdi, %r14
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
movq %rsp, %rdi
movl $16, %esi
callq hipMalloc
movq 8(%rsp), %rdi
movl $64, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 3(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7computePiS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movl $16, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size outer_compute, .Lfunc_end1-outer_compute
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computePiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computePiS_,@object # @_Z7computePiS_
.section .rodata,"a",@progbits
.globl _Z7computePiS_
.p2align 3, 0x0
_Z7computePiS_:
.quad _Z22__device_stub__computePiS_
.size _Z7computePiS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computePiS_"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computePiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computePiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //headers
#include <stdio.h>
#include <cuda.h> //standard cuda header file
//global variables
int inputLength = 5;
float *hostInput1 = NULL;
float *hostInput2 = NULL;
float *hostOutput = NULL;
float *deviceInput1 = NULL;
float *deviceInput2 = NULL;
float *deviceOutput = NULL;
//global kernel function definition
__global__ void vecAdd(float *in1, float *in2, float *out, int len)
{
//variable declaration
//row * width + column
int i = blockIdx.x * blockDim.x + threadIdx.x;
//code
if(i < len)
{
out[i] = in1[i] + in2[i];
}
}
int main(int argc, char *argv[])
{
//function declaration
void cleanup(void);
//code
//allocate host memory
hostInput1 = (float *)malloc(inputLength * sizeof(float));
if(hostInput1 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 1.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostInput2 = (float *)malloc(inputLength * sizeof(float));
if(hostInput2 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 2.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostOutput = (float *)malloc(inputLength * sizeof(float));
if(hostOutput == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Output Array.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
//fill above input host vectors with arbitary but hard-coded data
hostInput1[0] = 101.0f;
hostInput1[1] = 102.0f;
hostInput1[2] = 103.0f;
hostInput1[3] = 104.0f;
hostInput1[4] = 105.0f;
hostInput2[0] = 201.0f;
hostInput2[1] = 202.0f;
hostInput2[2] = 203.0f;
hostInput2[3] = 204.0f;
hostInput2[4] = 205.0f;
//allocate the device memory
int size = inputLength * sizeof(float);
cudaError_t err = cudaSuccess;
err = cudaMalloc((void **)&deviceInput1, size);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&deviceInput2, size);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&deviceOutput, size);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//copy host memory contents to device memory
err = cudaMemcpy(deviceInput1, hostInput1, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMemcpy(deviceInput2, hostInput2, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//cuda kernel configuration
dim3 DimGrid = dim3(ceil(inputLength / 256.0), 1, 1);
dim3 DimBlock = dim3(256, 1, 1);
vecAdd<<<DimGrid, DimBlock>>>(deviceInput1, deviceInput2, deviceOutput, inputLength);
//copy device memory to host memory
err = cudaMemcpy(hostOutput, deviceOutput, size, cudaMemcpyDeviceToHost);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//result
int i;
for(i = 0; i < inputLength; i++)
{
printf("%f + %f = %f\n", hostInput1[i], hostInput2[i], hostOutput[i]);
}
//total cleanup
cleanup();
return (0);
}
void cleanup(void)
{
//code
//free allocated device memory
if(deviceOutput)
{
cudaFree(deviceOutput);
deviceOutput = NULL;
}
if(deviceInput2)
{
cudaFree(deviceInput2);
deviceInput2 = NULL;
}
if(deviceInput1)
{
cudaFree(deviceInput1);
deviceInput1 = NULL;
}
//free allocated host memory
if(hostOutput)
{
free(hostOutput);
hostOutput = NULL;
}
if(hostInput2)
{
free(hostInput2);
hostInput2 = NULL;
}
if(hostInput1)
{
free(hostInput1);
hostInput1 = NULL;
}
} | code for sm_80
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //headers
#include <stdio.h>
#include <cuda.h> //standard cuda header file
//global variables
int inputLength = 5;
float *hostInput1 = NULL;
float *hostInput2 = NULL;
float *hostOutput = NULL;
float *deviceInput1 = NULL;
float *deviceInput2 = NULL;
float *deviceOutput = NULL;
//global kernel function definition
__global__ void vecAdd(float *in1, float *in2, float *out, int len)
{
//variable declaration
//row * width + column
int i = blockIdx.x * blockDim.x + threadIdx.x;
//code
if(i < len)
{
out[i] = in1[i] + in2[i];
}
}
int main(int argc, char *argv[])
{
//function declaration
void cleanup(void);
//code
//allocate host memory
hostInput1 = (float *)malloc(inputLength * sizeof(float));
if(hostInput1 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 1.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostInput2 = (float *)malloc(inputLength * sizeof(float));
if(hostInput2 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 2.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostOutput = (float *)malloc(inputLength * sizeof(float));
if(hostOutput == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Output Array.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
//fill above input host vectors with arbitary but hard-coded data
hostInput1[0] = 101.0f;
hostInput1[1] = 102.0f;
hostInput1[2] = 103.0f;
hostInput1[3] = 104.0f;
hostInput1[4] = 105.0f;
hostInput2[0] = 201.0f;
hostInput2[1] = 202.0f;
hostInput2[2] = 203.0f;
hostInput2[3] = 204.0f;
hostInput2[4] = 205.0f;
//allocate the device memory
int size = inputLength * sizeof(float);
cudaError_t err = cudaSuccess;
err = cudaMalloc((void **)&deviceInput1, size);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&deviceInput2, size);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&deviceOutput, size);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//copy host memory contents to device memory
err = cudaMemcpy(deviceInput1, hostInput1, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMemcpy(deviceInput2, hostInput2, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//cuda kernel configuration
dim3 DimGrid = dim3(ceil(inputLength / 256.0), 1, 1);
dim3 DimBlock = dim3(256, 1, 1);
vecAdd<<<DimGrid, DimBlock>>>(deviceInput1, deviceInput2, deviceOutput, inputLength);
//copy device memory to host memory
err = cudaMemcpy(hostOutput, deviceOutput, size, cudaMemcpyDeviceToHost);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//result
int i;
for(i = 0; i < inputLength; i++)
{
printf("%f + %f = %f\n", hostInput1[i], hostInput2[i], hostOutput[i]);
}
//total cleanup
cleanup();
return (0);
}
void cleanup(void)
{
//code
//free allocated device memory
if(deviceOutput)
{
cudaFree(deviceOutput);
deviceOutput = NULL;
}
if(deviceInput2)
{
cudaFree(deviceInput2);
deviceInput2 = NULL;
}
if(deviceInput1)
{
cudaFree(deviceInput1);
deviceInput1 = NULL;
}
//free allocated host memory
if(hostOutput)
{
free(hostOutput);
hostOutput = NULL;
}
if(hostInput2)
{
free(hostInput2);
hostInput2 = NULL;
}
if(hostInput1)
{
free(hostInput1);
hostInput1 = NULL;
}
} | .file "tmpxft_0004d159_00000000-6_HelloCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7cleanupv
.type _Z7cleanupv, @function
_Z7cleanupv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq deviceOutput(%rip), %rdi
testq %rdi, %rdi
je .L4
call cudaFree@PLT
movq $0, deviceOutput(%rip)
.L4:
movq deviceInput2(%rip), %rdi
testq %rdi, %rdi
je .L5
call cudaFree@PLT
movq $0, deviceInput2(%rip)
.L5:
movq deviceInput1(%rip), %rdi
testq %rdi, %rdi
je .L6
call cudaFree@PLT
movq $0, deviceInput1(%rip)
.L6:
movq hostOutput(%rip), %rdi
testq %rdi, %rdi
je .L7
call free@PLT
movq $0, hostOutput(%rip)
.L7:
movq hostInput2(%rip), %rdi
testq %rdi, %rdi
je .L8
call free@PLT
movq $0, hostInput2(%rip)
.L8:
movq hostInput1(%rip), %rdi
testq %rdi, %rdi
je .L3
call free@PLT
movq $0, hostInput1(%rip)
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7cleanupv, .-_Z7cleanupv
.globl _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 1.\nExiting ...\n"
.align 8
.LC1:
.string "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 2.\nExiting ...\n"
.align 8
.LC2:
.string "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Output Array.\nExiting ...\n"
.align 8
.LC13:
.string "/home/ubuntu/Datasets/stackv2/train-structured/yashPat98/HPP/master/CUDA/CUDA-Seminar/01-HelloCUDA/HelloCUDA.cu"
.align 8
.LC14:
.string "GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC19:
.string "%f + %f = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl inputLength(%rip), %ebx
movslq %ebx, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, hostInput1(%rip)
testq %rax, %rax
je .L37
movq %rax, %r13
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, hostInput2(%rip)
testq %rax, %rax
je .L38
movq %r12, %rdi
call malloc@PLT
movq %rax, hostOutput(%rip)
testq %rax, %rax
je .L39
movl $0x42ca0000, 0(%r13)
movl $0x42cc0000, 4(%r13)
movl $0x42ce0000, 8(%r13)
movl $0x42d00000, 12(%r13)
movl $0x42d20000, 16(%r13)
movl $0x43490000, 0(%rbp)
movl $0x434a0000, 4(%rbp)
movl $0x434b0000, 8(%rbp)
movl $0x434c0000, 12(%rbp)
movl $0x434d0000, 16(%rbp)
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
leaq deviceInput1(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
movq %rbx, %rsi
leaq deviceInput2(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movq %rbx, %rsi
leaq deviceOutput(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl $1, %ecx
movq %rbx, %rdx
movq hostInput1(%rip), %rsi
movq deviceInput1(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L43
movl $1, %ecx
movq %rbx, %rdx
movq hostInput2(%rip), %rsi
movq deviceInput2(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L44
pxor %xmm0, %xmm0
cvtsi2sdl inputLength(%rip), %xmm0
mulsd .LC15(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC20(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC16(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L28
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC18(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L28:
cvttsd2siq %xmm3, %rax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L29:
movl $2, %ecx
movq %rbx, %rdx
movq deviceOutput(%rip), %rsi
movq hostOutput(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movl $0, %ebx
leaq .LC19(%rip), %rbp
cmpl $0, inputLength(%rip)
jle .L32
.L31:
movq hostInput1(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq hostOutput(%rip), %rax
pxor %xmm2, %xmm2
cvtss2sd (%rax,%rbx,4), %xmm2
movq hostInput2(%rip), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, inputLength(%rip)
jg .L31
.L32:
call _Z7cleanupv
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L38:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L39:
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $80, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $88, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $96, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $105, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $113, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L45:
movl inputLength(%rip), %ecx
movq deviceOutput(%rip), %rdx
movq deviceInput2(%rip), %rsi
movq deviceInput1(%rip), %rdi
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
jmp .L29
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $127, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z6vecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl deviceOutput
.bss
.align 8
.type deviceOutput, @object
.size deviceOutput, 8
deviceOutput:
.zero 8
.globl deviceInput2
.align 8
.type deviceInput2, @object
.size deviceInput2, 8
deviceInput2:
.zero 8
.globl deviceInput1
.align 8
.type deviceInput1, @object
.size deviceInput1, 8
deviceInput1:
.zero 8
.globl hostOutput
.align 8
.type hostOutput, @object
.size hostOutput, 8
hostOutput:
.zero 8
.globl hostInput2
.align 8
.type hostInput2, @object
.size hostInput2, 8
hostInput2:
.zero 8
.globl hostInput1
.align 8
.type hostInput1, @object
.size hostInput1, 8
hostInput1:
.zero 8
.globl inputLength
.data
.align 4
.type inputLength, @object
.size inputLength, 4
inputLength:
.long 5
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC15:
.long 0
.long 1064304640
.align 8
.LC16:
.long 0
.long 1127219200
.align 8
.LC18:
.long 0
.long 1072693248
.align 8
.LC20:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //headers
#include <stdio.h>
#include <cuda.h> //standard cuda header file
//global variables
int inputLength = 5;
float *hostInput1 = NULL;
float *hostInput2 = NULL;
float *hostOutput = NULL;
float *deviceInput1 = NULL;
float *deviceInput2 = NULL;
float *deviceOutput = NULL;
//global kernel function definition
__global__ void vecAdd(float *in1, float *in2, float *out, int len)
{
//variable declaration
//row * width + column
int i = blockIdx.x * blockDim.x + threadIdx.x;
//code
if(i < len)
{
out[i] = in1[i] + in2[i];
}
}
int main(int argc, char *argv[])
{
//function declaration
void cleanup(void);
//code
//allocate host memory
hostInput1 = (float *)malloc(inputLength * sizeof(float));
if(hostInput1 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 1.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostInput2 = (float *)malloc(inputLength * sizeof(float));
if(hostInput2 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 2.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostOutput = (float *)malloc(inputLength * sizeof(float));
if(hostOutput == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Output Array.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
//fill above input host vectors with arbitary but hard-coded data
hostInput1[0] = 101.0f;
hostInput1[1] = 102.0f;
hostInput1[2] = 103.0f;
hostInput1[3] = 104.0f;
hostInput1[4] = 105.0f;
hostInput2[0] = 201.0f;
hostInput2[1] = 202.0f;
hostInput2[2] = 203.0f;
hostInput2[3] = 204.0f;
hostInput2[4] = 205.0f;
//allocate the device memory
int size = inputLength * sizeof(float);
cudaError_t err = cudaSuccess;
err = cudaMalloc((void **)&deviceInput1, size);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&deviceInput2, size);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **)&deviceOutput, size);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//copy host memory contents to device memory
err = cudaMemcpy(deviceInput1, hostInput1, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = cudaMemcpy(deviceInput2, hostInput2, size, cudaMemcpyHostToDevice);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//cuda kernel configuration
dim3 DimGrid = dim3(ceil(inputLength / 256.0), 1, 1);
dim3 DimBlock = dim3(256, 1, 1);
vecAdd<<<DimGrid, DimBlock>>>(deviceInput1, deviceInput2, deviceOutput, inputLength);
//copy device memory to host memory
err = cudaMemcpy(hostOutput, deviceOutput, size, cudaMemcpyDeviceToHost);
if(err != cudaSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", cudaGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//result
int i;
for(i = 0; i < inputLength; i++)
{
printf("%f + %f = %f\n", hostInput1[i], hostInput2[i], hostOutput[i]);
}
//total cleanup
cleanup();
return (0);
}
void cleanup(void)
{
//code
//free allocated device memory
if(deviceOutput)
{
cudaFree(deviceOutput);
deviceOutput = NULL;
}
if(deviceInput2)
{
cudaFree(deviceInput2);
deviceInput2 = NULL;
}
if(deviceInput1)
{
cudaFree(deviceInput1);
deviceInput1 = NULL;
}
//free allocated host memory
if(hostOutput)
{
free(hostOutput);
hostOutput = NULL;
}
if(hostInput2)
{
free(hostInput2);
hostInput2 = NULL;
}
if(hostInput1)
{
free(hostInput1);
hostInput1 = NULL;
}
} | //headers
#include <stdio.h>
#include <hip/hip_runtime.h> //standard cuda header file
//global variables
int inputLength = 5;
float *hostInput1 = NULL;
float *hostInput2 = NULL;
float *hostOutput = NULL;
float *deviceInput1 = NULL;
float *deviceInput2 = NULL;
float *deviceOutput = NULL;
//global kernel function definition
__global__ void vecAdd(float *in1, float *in2, float *out, int len)
{
//variable declaration
//row * width + column
int i = blockIdx.x * blockDim.x + threadIdx.x;
//code
if(i < len)
{
out[i] = in1[i] + in2[i];
}
}
int main(int argc, char *argv[])
{
//function declaration
void cleanup(void);
//code
//allocate host memory
hostInput1 = (float *)malloc(inputLength * sizeof(float));
if(hostInput1 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 1.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostInput2 = (float *)malloc(inputLength * sizeof(float));
if(hostInput2 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 2.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostOutput = (float *)malloc(inputLength * sizeof(float));
if(hostOutput == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Output Array.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
//fill above input host vectors with arbitary but hard-coded data
hostInput1[0] = 101.0f;
hostInput1[1] = 102.0f;
hostInput1[2] = 103.0f;
hostInput1[3] = 104.0f;
hostInput1[4] = 105.0f;
hostInput2[0] = 201.0f;
hostInput2[1] = 202.0f;
hostInput2[2] = 203.0f;
hostInput2[3] = 204.0f;
hostInput2[4] = 205.0f;
//allocate the device memory
int size = inputLength * sizeof(float);
hipError_t err = hipSuccess;
err = hipMalloc((void **)&deviceInput1, size);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&deviceInput2, size);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&deviceOutput, size);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//copy host memory contents to device memory
err = hipMemcpy(deviceInput1, hostInput1, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMemcpy(deviceInput2, hostInput2, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//cuda kernel configuration
dim3 DimGrid = dim3(ceil(inputLength / 256.0), 1, 1);
dim3 DimBlock = dim3(256, 1, 1);
vecAdd<<<DimGrid, DimBlock>>>(deviceInput1, deviceInput2, deviceOutput, inputLength);
//copy device memory to host memory
err = hipMemcpy(hostOutput, deviceOutput, size, hipMemcpyDeviceToHost);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//result
int i;
for(i = 0; i < inputLength; i++)
{
printf("%f + %f = %f\n", hostInput1[i], hostInput2[i], hostOutput[i]);
}
//total cleanup
cleanup();
return (0);
}
void cleanup(void)
{
//code
//free allocated device memory
if(deviceOutput)
{
hipFree(deviceOutput);
deviceOutput = NULL;
}
if(deviceInput2)
{
hipFree(deviceInput2);
deviceInput2 = NULL;
}
if(deviceInput1)
{
hipFree(deviceInput1);
deviceInput1 = NULL;
}
//free allocated host memory
if(hostOutput)
{
free(hostOutput);
hostOutput = NULL;
}
if(hostInput2)
{
free(hostInput2);
hostInput2 = NULL;
}
if(hostInput1)
{
free(hostInput1);
hostInput1 = NULL;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //headers
#include <stdio.h>
#include <hip/hip_runtime.h> //standard cuda header file
//global variables
int inputLength = 5;
float *hostInput1 = NULL;
float *hostInput2 = NULL;
float *hostOutput = NULL;
float *deviceInput1 = NULL;
float *deviceInput2 = NULL;
float *deviceOutput = NULL;
//global kernel function definition
__global__ void vecAdd(float *in1, float *in2, float *out, int len)
{
//variable declaration
//row * width + column
int i = blockIdx.x * blockDim.x + threadIdx.x;
//code
if(i < len)
{
out[i] = in1[i] + in2[i];
}
}
int main(int argc, char *argv[])
{
//function declaration
void cleanup(void);
//code
//allocate host memory
hostInput1 = (float *)malloc(inputLength * sizeof(float));
if(hostInput1 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 1.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostInput2 = (float *)malloc(inputLength * sizeof(float));
if(hostInput2 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 2.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostOutput = (float *)malloc(inputLength * sizeof(float));
if(hostOutput == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Output Array.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
//fill above input host vectors with arbitary but hard-coded data
hostInput1[0] = 101.0f;
hostInput1[1] = 102.0f;
hostInput1[2] = 103.0f;
hostInput1[3] = 104.0f;
hostInput1[4] = 105.0f;
hostInput2[0] = 201.0f;
hostInput2[1] = 202.0f;
hostInput2[2] = 203.0f;
hostInput2[3] = 204.0f;
hostInput2[4] = 205.0f;
//allocate the device memory
int size = inputLength * sizeof(float);
hipError_t err = hipSuccess;
err = hipMalloc((void **)&deviceInput1, size);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&deviceInput2, size);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&deviceOutput, size);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//copy host memory contents to device memory
err = hipMemcpy(deviceInput1, hostInput1, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMemcpy(deviceInput2, hostInput2, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//cuda kernel configuration
dim3 DimGrid = dim3(ceil(inputLength / 256.0), 1, 1);
dim3 DimBlock = dim3(256, 1, 1);
vecAdd<<<DimGrid, DimBlock>>>(deviceInput1, deviceInput2, deviceOutput, inputLength);
//copy device memory to host memory
err = hipMemcpy(hostOutput, deviceOutput, size, hipMemcpyDeviceToHost);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//result
int i;
for(i = 0; i < inputLength; i++)
{
printf("%f + %f = %f\n", hostInput1[i], hostInput2[i], hostOutput[i]);
}
//total cleanup
cleanup();
return (0);
}
void cleanup(void)
{
//code
//free allocated device memory
if(deviceOutput)
{
hipFree(deviceOutput);
deviceOutput = NULL;
}
if(deviceInput2)
{
hipFree(deviceInput2);
deviceInput2 = NULL;
}
if(deviceInput1)
{
hipFree(deviceInput1);
deviceInput1 = NULL;
}
//free allocated host memory
if(hostOutput)
{
free(hostOutput);
hostOutput = NULL;
}
if(hostInput2)
{
free(hostInput2);
hostInput2 = NULL;
}
if(hostInput1)
{
free(hostInput1);
hostInput1 = NULL;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_i
.globl _Z6vecAddPfS_S_i
.p2align 8
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_i, .Lfunc_end0-_Z6vecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //headers
#include <stdio.h>
#include <hip/hip_runtime.h> //standard cuda header file
//global variables
int inputLength = 5;
float *hostInput1 = NULL;
float *hostInput2 = NULL;
float *hostOutput = NULL;
float *deviceInput1 = NULL;
float *deviceInput2 = NULL;
float *deviceOutput = NULL;
//global kernel function definition
__global__ void vecAdd(float *in1, float *in2, float *out, int len)
{
//variable declaration
//row * width + column
int i = blockIdx.x * blockDim.x + threadIdx.x;
//code
if(i < len)
{
out[i] = in1[i] + in2[i];
}
}
int main(int argc, char *argv[])
{
//function declaration
void cleanup(void);
//code
//allocate host memory
hostInput1 = (float *)malloc(inputLength * sizeof(float));
if(hostInput1 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 1.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostInput2 = (float *)malloc(inputLength * sizeof(float));
if(hostInput2 == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 2.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
hostOutput = (float *)malloc(inputLength * sizeof(float));
if(hostOutput == NULL)
{
printf("CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Output Array.\nExiting ...\n");
cleanup();
exit(EXIT_FAILURE);
}
//fill above input host vectors with arbitary but hard-coded data
hostInput1[0] = 101.0f;
hostInput1[1] = 102.0f;
hostInput1[2] = 103.0f;
hostInput1[3] = 104.0f;
hostInput1[4] = 105.0f;
hostInput2[0] = 201.0f;
hostInput2[1] = 202.0f;
hostInput2[2] = 203.0f;
hostInput2[3] = 204.0f;
hostInput2[4] = 205.0f;
//allocate the device memory
int size = inputLength * sizeof(float);
hipError_t err = hipSuccess;
err = hipMalloc((void **)&deviceInput1, size);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&deviceInput2, size);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMalloc((void **)&deviceOutput, size);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//copy host memory contents to device memory
err = hipMemcpy(deviceInput1, hostInput1, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
err = hipMemcpy(deviceInput2, hostInput2, size, hipMemcpyHostToDevice);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//cuda kernel configuration
dim3 DimGrid = dim3(ceil(inputLength / 256.0), 1, 1);
dim3 DimBlock = dim3(256, 1, 1);
vecAdd<<<DimGrid, DimBlock>>>(deviceInput1, deviceInput2, deviceOutput, inputLength);
//copy device memory to host memory
err = hipMemcpy(hostOutput, deviceOutput, size, hipMemcpyDeviceToHost);
if(err != hipSuccess)
{
printf("GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n", hipGetErrorString(err), __FILE__, __LINE__);
cleanup();
exit(EXIT_FAILURE);
}
//result
int i;
for(i = 0; i < inputLength; i++)
{
printf("%f + %f = %f\n", hostInput1[i], hostInput2[i], hostOutput[i]);
}
//total cleanup
cleanup();
return (0);
}
void cleanup(void)
{
//code
//free allocated device memory
if(deviceOutput)
{
hipFree(deviceOutput);
deviceOutput = NULL;
}
if(deviceInput2)
{
hipFree(deviceInput2);
deviceInput2 = NULL;
}
if(deviceInput1)
{
hipFree(deviceInput1);
deviceInput1 = NULL;
}
//free allocated host memory
if(hostOutput)
{
free(hostOutput);
hostOutput = NULL;
}
if(hostInput2)
{
free(hostInput2);
hostInput2 = NULL;
}
if(hostInput1)
{
free(hostInput1);
hostInput1 = NULL;
}
} | .text
.file "HelloCUDA.hip"
.globl _Z21__device_stub__vecAddPfS_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_i,@function
_Z21__device_stub__vecAddPfS_S_i: # @_Z21__device_stub__vecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x42ca0000 # float 101
.long 0x42cc0000 # float 102
.long 0x42ce0000 # float 103
.long 0x42d00000 # float 104
.LCPI1_1:
.long 0x43490000 # float 201
.long 0x434a0000 # float 202
.long 0x434b0000 # float 203
.long 0x434c0000 # float 204
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq inputLength(%rip), %r12
leaq (,%r12,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, hostInput1(%rip)
testq %rax, %rax
je .LBB1_1
# %bb.4:
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, hostInput2(%rip)
testq %rax, %rax
je .LBB1_5
# %bb.6:
movq %rax, %r14
movq %r15, %rdi
callq malloc
movq %rax, hostOutput(%rip)
testq %rax, %rax
je .LBB1_7
# %bb.8:
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1.01E+2,1.02E+2,1.03E+2,1.04E+2]
movups %xmm0, (%rbx)
movl $1121058816, 16(%rbx) # imm = 0x42D20000
movapd .LCPI1_1(%rip), %xmm0 # xmm0 = [2.01E+2,2.02E+2,2.03E+2,2.04E+2]
movupd %xmm0, (%r14)
movl $1129119744, 16(%r14) # imm = 0x434D0000
shll $2, %r12d
movslq %r12d, %rbx
movl $deviceInput1, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_9
# %bb.11:
movl $deviceInput2, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.13:
movl $deviceOutput, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movq deviceInput1(%rip), %rdi
movq hostInput1(%rip), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movq deviceInput2(%rip), %rdi
movq hostInput2(%rip), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.19:
xorps %xmm0, %xmm0
cvtsi2sdl inputLength(%rip), %xmm0
mulsd .LCPI1_2(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_21
# %bb.20:
movq deviceInput1(%rip), %rax
movq deviceInput2(%rip), %rcx
movq deviceOutput(%rip), %rdx
movl inputLength(%rip), %esi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl %esi, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_21:
movq hostOutput(%rip), %rdi
movq deviceOutput(%rip), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_26
# %bb.22: # %.preheader
cmpl $0, inputLength(%rip)
jle .LBB1_25
# %bb.23: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_24: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq hostInput1(%rip), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq hostInput2(%rip), %rax
movss (%rax,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movq hostOutput(%rip), %rax
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.5, %edi
movb $3, %al
callq printf
incq %rbx
movslq inputLength(%rip), %rax
cmpq %rax, %rbx
jl .LBB1_24
.LBB1_25: # %._crit_edge
callq _Z7cleanupv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 160
movl $.Lstr.2, %edi
jmp .LBB1_2
.LBB1_5:
movl $.Lstr.1, %edi
jmp .LBB1_2
.LBB1_7:
movl $.Lstr, %edi
.LBB1_2:
callq puts@PLT
jmp .LBB1_3
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $80, %ecx
jmp .LBB1_10
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $88, %ecx
jmp .LBB1_10
.LBB1_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $96, %ecx
jmp .LBB1_10
.LBB1_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $105, %ecx
jmp .LBB1_10
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $113, %ecx
jmp .LBB1_10
.LBB1_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $127, %ecx
.LBB1_10:
xorl %eax, %eax
callq printf
.LBB1_3:
callq _Z7cleanupv
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z7cleanupv # -- Begin function _Z7cleanupv
.p2align 4, 0x90
.type _Z7cleanupv,@function
_Z7cleanupv: # @_Z7cleanupv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq deviceOutput(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq hipFree
movq $0, deviceOutput(%rip)
.LBB2_2:
movq deviceInput2(%rip), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq hipFree
movq $0, deviceInput2(%rip)
.LBB2_4:
movq deviceInput1(%rip), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq hipFree
movq $0, deviceInput1(%rip)
.LBB2_6:
movq hostOutput(%rip), %rdi
testq %rdi, %rdi
je .LBB2_8
# %bb.7:
callq free
movq $0, hostOutput(%rip)
.LBB2_8:
movq hostInput2(%rip), %rdi
testq %rdi, %rdi
je .LBB2_10
# %bb.9:
callq free
movq $0, hostInput2(%rip)
.LBB2_10:
movq hostInput1(%rip), %rdi
testq %rdi, %rdi
je .LBB2_12
# %bb.11:
callq free
movq $0, hostInput1(%rip)
.LBB2_12:
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7cleanupv, .Lfunc_end2-_Z7cleanupv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type inputLength,@object # @inputLength
.data
.globl inputLength
.p2align 2, 0x0
inputLength:
.long 5 # 0x5
.size inputLength, 4
.type hostInput1,@object # @hostInput1
.bss
.globl hostInput1
.p2align 3, 0x0
hostInput1:
.quad 0
.size hostInput1, 8
.type hostInput2,@object # @hostInput2
.globl hostInput2
.p2align 3, 0x0
hostInput2:
.quad 0
.size hostInput2, 8
.type hostOutput,@object # @hostOutput
.globl hostOutput
.p2align 3, 0x0
hostOutput:
.quad 0
.size hostOutput, 8
.type deviceInput1,@object # @deviceInput1
.globl deviceInput1
.p2align 3, 0x0
deviceInput1:
.quad 0
.size deviceInput1, 8
.type deviceInput2,@object # @deviceInput2
.globl deviceInput2
.p2align 3, 0x0
deviceInput2:
.quad 0
.size deviceInput2, 8
.type deviceOutput,@object # @deviceOutput
.globl deviceOutput
.p2align 3, 0x0
deviceOutput:
.quad 0
.size deviceOutput, 8
.type _Z6vecAddPfS_S_i,@object # @_Z6vecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_i:
.quad _Z21__device_stub__vecAddPfS_S_i
.size _Z6vecAddPfS_S_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n"
.size .L.str.3, 72
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/yashPat98/HPP/master/CUDA/CUDA-Seminar/01-HelloCUDA/HelloCUDA.hip"
.size .L.str.4, 123
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f + %f = %f\n"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Output Array.\nExiting ..."
.size .Lstr, 91
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 2.\nExiting ..."
.size .Lstr.1, 92
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 1.\nExiting ..."
.size .Lstr.2, 92
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deviceInput1
.addrsig_sym deviceInput2
.addrsig_sym deviceOutput
.addrsig_sym _Z6vecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*00d0*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPfS_S_i
.globl _Z6vecAddPfS_S_i
.p2align 8
.type _Z6vecAddPfS_S_i,@function
_Z6vecAddPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPfS_S_i, .Lfunc_end0-_Z6vecAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004d159_00000000-6_HelloCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7cleanupv
.type _Z7cleanupv, @function
_Z7cleanupv:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq deviceOutput(%rip), %rdi
testq %rdi, %rdi
je .L4
call cudaFree@PLT
movq $0, deviceOutput(%rip)
.L4:
movq deviceInput2(%rip), %rdi
testq %rdi, %rdi
je .L5
call cudaFree@PLT
movq $0, deviceInput2(%rip)
.L5:
movq deviceInput1(%rip), %rdi
testq %rdi, %rdi
je .L6
call cudaFree@PLT
movq $0, deviceInput1(%rip)
.L6:
movq hostOutput(%rip), %rdi
testq %rdi, %rdi
je .L7
call free@PLT
movq $0, hostOutput(%rip)
.L7:
movq hostInput2(%rip), %rdi
testq %rdi, %rdi
je .L8
call free@PLT
movq $0, hostInput2(%rip)
.L8:
movq hostInput1(%rip), %rdi
testq %rdi, %rdi
je .L3
call free@PLT
movq $0, hostInput1(%rip)
.L3:
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7cleanupv, .-_Z7cleanupv
.globl _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.type _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
.globl _Z6vecAddPfS_S_i
.type _Z6vecAddPfS_S_i, @function
_Z6vecAddPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6vecAddPfS_S_i, .-_Z6vecAddPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 1.\nExiting ...\n"
.align 8
.LC1:
.string "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 2.\nExiting ...\n"
.align 8
.LC2:
.string "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Output Array.\nExiting ...\n"
.align 8
.LC13:
.string "/home/ubuntu/Datasets/stackv2/train-structured/yashPat98/HPP/master/CUDA/CUDA-Seminar/01-HelloCUDA/HelloCUDA.cu"
.align 8
.LC14:
.string "GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC19:
.string "%f + %f = %f\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movl inputLength(%rip), %ebx
movslq %ebx, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, hostInput1(%rip)
testq %rax, %rax
je .L37
movq %rax, %r13
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rax, hostInput2(%rip)
testq %rax, %rax
je .L38
movq %r12, %rdi
call malloc@PLT
movq %rax, hostOutput(%rip)
testq %rax, %rax
je .L39
movl $0x42ca0000, 0(%r13)
movl $0x42cc0000, 4(%r13)
movl $0x42ce0000, 8(%r13)
movl $0x42d00000, 12(%r13)
movl $0x42d20000, 16(%r13)
movl $0x43490000, 0(%rbp)
movl $0x434a0000, 4(%rbp)
movl $0x434b0000, 8(%rbp)
movl $0x434c0000, 12(%rbp)
movl $0x434d0000, 16(%rbp)
sall $2, %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
leaq deviceInput1(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L40
movq %rbx, %rsi
leaq deviceInput2(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L41
movq %rbx, %rsi
leaq deviceOutput(%rip), %rdi
call cudaMalloc@PLT
testl %eax, %eax
jne .L42
movl $1, %ecx
movq %rbx, %rdx
movq hostInput1(%rip), %rsi
movq deviceInput1(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L43
movl $1, %ecx
movq %rbx, %rdx
movq hostInput2(%rip), %rsi
movq deviceInput2(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L44
pxor %xmm0, %xmm0
cvtsi2sdl inputLength(%rip), %xmm0
mulsd .LC15(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC20(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC16(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L28
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC18(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L28:
cvttsd2siq %xmm3, %rax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L29:
movl $2, %ecx
movq %rbx, %rdx
movq deviceOutput(%rip), %rsi
movq hostOutput(%rip), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L30
movl $0, %ebx
leaq .LC19(%rip), %rbp
cmpl $0, inputLength(%rip)
jle .L32
.L31:
movq hostInput1(%rip), %rax
pxor %xmm0, %xmm0
cvtss2sd (%rax,%rbx,4), %xmm0
movq hostOutput(%rip), %rax
pxor %xmm2, %xmm2
cvtss2sd (%rax,%rbx,4), %xmm2
movq hostInput2(%rip), %rax
pxor %xmm1, %xmm1
cvtss2sd (%rax,%rbx,4), %xmm1
movq %rbp, %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, inputLength(%rip)
jg .L31
.L32:
call _Z7cleanupv
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L37:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L38:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L39:
leaq .LC2(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $80, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $88, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L42:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $96, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L43:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $105, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $113, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.L45:
movl inputLength(%rip), %ecx
movq deviceOutput(%rip), %rdx
movq deviceInput2(%rip), %rsi
movq deviceInput1(%rip), %rdi
call _Z30__device_stub__Z6vecAddPfS_S_iPfS_S_i
jmp .L29
.L30:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
movl $127, %r8d
leaq .LC13(%rip), %rcx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call _Z7cleanupv
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC21:
.string "_Z6vecAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl deviceOutput
.bss
.align 8
.type deviceOutput, @object
.size deviceOutput, 8
deviceOutput:
.zero 8
.globl deviceInput2
.align 8
.type deviceInput2, @object
.size deviceInput2, 8
deviceInput2:
.zero 8
.globl deviceInput1
.align 8
.type deviceInput1, @object
.size deviceInput1, 8
deviceInput1:
.zero 8
.globl hostOutput
.align 8
.type hostOutput, @object
.size hostOutput, 8
hostOutput:
.zero 8
.globl hostInput2
.align 8
.type hostInput2, @object
.size hostInput2, 8
hostInput2:
.zero 8
.globl hostInput1
.align 8
.type hostInput1, @object
.size hostInput1, 8
hostInput1:
.zero 8
.globl inputLength
.data
.align 4
.type inputLength, @object
.size inputLength, 4
inputLength:
.long 5
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC15:
.long 0
.long 1064304640
.align 8
.LC16:
.long 0
.long 1127219200
.align 8
.LC18:
.long 0
.long 1072693248
.align 8
.LC20:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "HelloCUDA.hip"
.globl _Z21__device_stub__vecAddPfS_S_i # -- Begin function _Z21__device_stub__vecAddPfS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPfS_S_i,@function
_Z21__device_stub__vecAddPfS_S_i: # @_Z21__device_stub__vecAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPfS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x42ca0000 # float 101
.long 0x42cc0000 # float 102
.long 0x42ce0000 # float 103
.long 0x42d00000 # float 104
.LCPI1_1:
.long 0x43490000 # float 201
.long 0x434a0000 # float 202
.long 0x434b0000 # float 203
.long 0x434c0000 # float 204
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3f70000000000000 # double 0.00390625
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movslq inputLength(%rip), %r12
leaq (,%r12,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, hostInput1(%rip)
testq %rax, %rax
je .LBB1_1
# %bb.4:
movq %rax, %rbx
movq %r15, %rdi
callq malloc
movq %rax, hostInput2(%rip)
testq %rax, %rax
je .LBB1_5
# %bb.6:
movq %rax, %r14
movq %r15, %rdi
callq malloc
movq %rax, hostOutput(%rip)
testq %rax, %rax
je .LBB1_7
# %bb.8:
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [1.01E+2,1.02E+2,1.03E+2,1.04E+2]
movups %xmm0, (%rbx)
movl $1121058816, 16(%rbx) # imm = 0x42D20000
movapd .LCPI1_1(%rip), %xmm0 # xmm0 = [2.01E+2,2.02E+2,2.03E+2,2.04E+2]
movupd %xmm0, (%r14)
movl $1129119744, 16(%r14) # imm = 0x434D0000
shll $2, %r12d
movslq %r12d, %rbx
movl $deviceInput1, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_9
# %bb.11:
movl $deviceInput2, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_12
# %bb.13:
movl $deviceOutput, %edi
movq %rbx, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB1_14
# %bb.15:
movq deviceInput1(%rip), %rdi
movq hostInput1(%rip), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_16
# %bb.17:
movq deviceInput2(%rip), %rdi
movq hostInput2(%rip), %rsi
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_18
# %bb.19:
xorps %xmm0, %xmm0
cvtsi2sdl inputLength(%rip), %xmm0
mulsd .LCPI1_2(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %rax
movl %eax, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_21
# %bb.20:
movq deviceInput1(%rip), %rax
movq deviceInput2(%rip), %rcx
movq deviceOutput(%rip), %rdx
movl inputLength(%rip), %esi
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 56(%rsp)
movl %esi, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_21:
movq hostOutput(%rip), %rdi
movq deviceOutput(%rip), %rsi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_26
# %bb.22: # %.preheader
cmpl $0, inputLength(%rip)
jle .LBB1_25
# %bb.23: # %.lr.ph.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_24: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq hostInput1(%rip), %rax
movss (%rax,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movq hostInput2(%rip), %rax
movss (%rax,%rbx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
cvtss2sd %xmm1, %xmm1
movq hostOutput(%rip), %rax
movss (%rax,%rbx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
cvtss2sd %xmm2, %xmm2
movl $.L.str.5, %edi
movb $3, %al
callq printf
incq %rbx
movslq inputLength(%rip), %rax
cmpq %rax, %rbx
jl .LBB1_24
.LBB1_25: # %._crit_edge
callq _Z7cleanupv
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_1:
.cfi_def_cfa_offset 160
movl $.Lstr.2, %edi
jmp .LBB1_2
.LBB1_5:
movl $.Lstr.1, %edi
jmp .LBB1_2
.LBB1_7:
movl $.Lstr, %edi
.LBB1_2:
callq puts@PLT
jmp .LBB1_3
.LBB1_9:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $80, %ecx
jmp .LBB1_10
.LBB1_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $88, %ecx
jmp .LBB1_10
.LBB1_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $96, %ecx
jmp .LBB1_10
.LBB1_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $105, %ecx
jmp .LBB1_10
.LBB1_18:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $113, %ecx
jmp .LBB1_10
.LBB1_26:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %edi
movl $.L.str.4, %edx
movq %rax, %rsi
movl $127, %ecx
.LBB1_10:
xorl %eax, %eax
callq printf
.LBB1_3:
callq _Z7cleanupv
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z7cleanupv # -- Begin function _Z7cleanupv
.p2align 4, 0x90
.type _Z7cleanupv,@function
_Z7cleanupv: # @_Z7cleanupv
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movq deviceOutput(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
callq hipFree
movq $0, deviceOutput(%rip)
.LBB2_2:
movq deviceInput2(%rip), %rdi
testq %rdi, %rdi
je .LBB2_4
# %bb.3:
callq hipFree
movq $0, deviceInput2(%rip)
.LBB2_4:
movq deviceInput1(%rip), %rdi
testq %rdi, %rdi
je .LBB2_6
# %bb.5:
callq hipFree
movq $0, deviceInput1(%rip)
.LBB2_6:
movq hostOutput(%rip), %rdi
testq %rdi, %rdi
je .LBB2_8
# %bb.7:
callq free
movq $0, hostOutput(%rip)
.LBB2_8:
movq hostInput2(%rip), %rdi
testq %rdi, %rdi
je .LBB2_10
# %bb.9:
callq free
movq $0, hostInput2(%rip)
.LBB2_10:
movq hostInput1(%rip), %rdi
testq %rdi, %rdi
je .LBB2_12
# %bb.11:
callq free
movq $0, hostInput1(%rip)
.LBB2_12:
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7cleanupv, .Lfunc_end2-_Z7cleanupv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type inputLength,@object # @inputLength
.data
.globl inputLength
.p2align 2, 0x0
inputLength:
.long 5 # 0x5
.size inputLength, 4
.type hostInput1,@object # @hostInput1
.bss
.globl hostInput1
.p2align 3, 0x0
hostInput1:
.quad 0
.size hostInput1, 8
.type hostInput2,@object # @hostInput2
.globl hostInput2
.p2align 3, 0x0
hostInput2:
.quad 0
.size hostInput2, 8
.type hostOutput,@object # @hostOutput
.globl hostOutput
.p2align 3, 0x0
hostOutput:
.quad 0
.size hostOutput, 8
.type deviceInput1,@object # @deviceInput1
.globl deviceInput1
.p2align 3, 0x0
deviceInput1:
.quad 0
.size deviceInput1, 8
.type deviceInput2,@object # @deviceInput2
.globl deviceInput2
.p2align 3, 0x0
deviceInput2:
.quad 0
.size deviceInput2, 8
.type deviceOutput,@object # @deviceOutput
.globl deviceOutput
.p2align 3, 0x0
deviceOutput:
.quad 0
.size deviceOutput, 8
.type _Z6vecAddPfS_S_i,@object # @_Z6vecAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPfS_S_i
.p2align 3, 0x0
_Z6vecAddPfS_S_i:
.quad _Z21__device_stub__vecAddPfS_S_i
.size _Z6vecAddPfS_S_i, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "GPU Memory Fatal Error = %s In File Name %s At Line No %d.\nExiting ...\n"
.size .L.str.3, 72
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/yashPat98/HPP/master/CUDA/CUDA-Seminar/01-HelloCUDA/HelloCUDA.hip"
.size .L.str.4, 123
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%f + %f = %f\n"
.size .L.str.5, 14
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPfS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Output Array.\nExiting ..."
.size .Lstr, 91
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 2.\nExiting ..."
.size .Lstr.1, 92
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "CPU Memory Fatal Error = Can Not Allocate Enough Memory For Host Input Array 1.\nExiting ..."
.size .Lstr.2, 92
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym deviceInput1
.addrsig_sym deviceInput2
.addrsig_sym deviceOutput
.addrsig_sym _Z6vecAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void cudaKernelTexture2D(unsigned char* surface, int width, int height, size_t pitch, float t)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned char* pixel;
// in the case where, due to quantization into grids, we have
// more threads than pixels, skip the threads which don't
// correspond to valid pixels
if (x >= width || y >= height) return;
// get a pointer to the pixel at (x,y)
pixel = (unsigned char*)(surface + y*pitch) + 4*x;
// populate it
float value_x = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*x)/width - 1.0f ) );
float value_y = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*y)/height - 1.0f ) );
// Color : DirectX BGRA, OpenGL RGBA
pixel[0] = 255*(0.5f + 0.5f*cos(t)); // blue
pixel[1] = 255*(0.5*pixel[1]/255.0 + 0.5*pow(value_y, 3.0f)); // green
pixel[2] = 255*(0.5*pixel[0]/255.0 + 0.5*pow(value_x, 3.0f)); // red
pixel[3] = 255; // alpha
} | .file "tmpxft_00062363_00000000-6_cudaKernelTexture2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf
.type _Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf, @function
_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19cudaKernelTexture2DPhiimf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf, .-_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf
.globl _Z19cudaKernelTexture2DPhiimf
.type _Z19cudaKernelTexture2DPhiimf, @function
_Z19cudaKernelTexture2DPhiimf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19cudaKernelTexture2DPhiimf, .-_Z19cudaKernelTexture2DPhiimf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19cudaKernelTexture2DPhiimf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19cudaKernelTexture2DPhiimf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void cudaKernelTexture2D(unsigned char* surface, int width, int height, size_t pitch, float t)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned char* pixel;
// in the case where, due to quantization into grids, we have
// more threads than pixels, skip the threads which don't
// correspond to valid pixels
if (x >= width || y >= height) return;
// get a pointer to the pixel at (x,y)
pixel = (unsigned char*)(surface + y*pitch) + 4*x;
// populate it
float value_x = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*x)/width - 1.0f ) );
float value_y = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*y)/height - 1.0f ) );
// Color : DirectX BGRA, OpenGL RGBA
pixel[0] = 255*(0.5f + 0.5f*cos(t)); // blue
pixel[1] = 255*(0.5*pixel[1]/255.0 + 0.5*pow(value_y, 3.0f)); // green
pixel[2] = 255*(0.5*pixel[0]/255.0 + 0.5*pow(value_x, 3.0f)); // red
pixel[3] = 255; // alpha
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaKernelTexture2D(unsigned char* surface, int width, int height, size_t pitch, float t)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned char* pixel;
// in the case where, due to quantization into grids, we have
// more threads than pixels, skip the threads which don't
// correspond to valid pixels
if (x >= width || y >= height) return;
// get a pointer to the pixel at (x,y)
pixel = (unsigned char*)(surface + y*pitch) + 4*x;
// populate it
float value_x = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*x)/width - 1.0f ) );
float value_y = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*y)/height - 1.0f ) );
// Color : DirectX BGRA, OpenGL RGBA
pixel[0] = 255*(0.5f + 0.5f*cos(t)); // blue
pixel[1] = 255*(0.5*pixel[1]/255.0 + 0.5*pow(value_y, 3.0f)); // green
pixel[2] = 255*(0.5*pixel[0]/255.0 + 0.5*pow(value_x, 3.0f)); // red
pixel[3] = 255; // alpha
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void cudaKernelTexture2D(unsigned char* surface, int width, int height, size_t pitch, float t)
{
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
unsigned char* pixel;
// in the case where, due to quantization into grids, we have
// more threads than pixels, skip the threads which don't
// correspond to valid pixels
if (x >= width || y >= height) return;
// get a pointer to the pixel at (x,y)
pixel = (unsigned char*)(surface + y*pitch) + 4*x;
// populate it
float value_x = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*x)/width - 1.0f ) );
float value_y = 0.5f + 0.5f*cos(t + 10.0f*( (2.0f*y)/height - 1.0f ) );
// Color : DirectX BGRA, OpenGL RGBA
pixel[0] = 255*(0.5f + 0.5f*cos(t)); // blue
pixel[1] = 255*(0.5*pixel[1]/255.0 + 0.5*pow(value_y, 3.0f)); // green
pixel[2] = 255*(0.5*pixel[0]/255.0 + 0.5*pow(value_x, 3.0f)); // red
pixel[3] = 255; // alpha
} | .text
.file "cudaKernelTexture2D.hip"
.globl _Z34__device_stub__cudaKernelTexture2DPhiimf # -- Begin function _Z34__device_stub__cudaKernelTexture2DPhiimf
.p2align 4, 0x90
.type _Z34__device_stub__cudaKernelTexture2DPhiimf,@function
_Z34__device_stub__cudaKernelTexture2DPhiimf: # @_Z34__device_stub__cudaKernelTexture2DPhiimf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19cudaKernelTexture2DPhiimf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__cudaKernelTexture2DPhiimf, .Lfunc_end0-_Z34__device_stub__cudaKernelTexture2DPhiimf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19cudaKernelTexture2DPhiimf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19cudaKernelTexture2DPhiimf,@object # @_Z19cudaKernelTexture2DPhiimf
.section .rodata,"a",@progbits
.globl _Z19cudaKernelTexture2DPhiimf
.p2align 3, 0x0
_Z19cudaKernelTexture2DPhiimf:
.quad _Z34__device_stub__cudaKernelTexture2DPhiimf
.size _Z19cudaKernelTexture2DPhiimf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19cudaKernelTexture2DPhiimf"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__cudaKernelTexture2DPhiimf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19cudaKernelTexture2DPhiimf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00062363_00000000-6_cudaKernelTexture2D.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf
.type _Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf, @function
_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z19cudaKernelTexture2DPhiimf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf, .-_Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf
.globl _Z19cudaKernelTexture2DPhiimf
.type _Z19cudaKernelTexture2DPhiimf, @function
_Z19cudaKernelTexture2DPhiimf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z19cudaKernelTexture2DPhiimfPhiimf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z19cudaKernelTexture2DPhiimf, .-_Z19cudaKernelTexture2DPhiimf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z19cudaKernelTexture2DPhiimf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z19cudaKernelTexture2DPhiimf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudaKernelTexture2D.hip"
.globl _Z34__device_stub__cudaKernelTexture2DPhiimf # -- Begin function _Z34__device_stub__cudaKernelTexture2DPhiimf
.p2align 4, 0x90
.type _Z34__device_stub__cudaKernelTexture2DPhiimf,@function
_Z34__device_stub__cudaKernelTexture2DPhiimf: # @_Z34__device_stub__cudaKernelTexture2DPhiimf
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z19cudaKernelTexture2DPhiimf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z34__device_stub__cudaKernelTexture2DPhiimf, .Lfunc_end0-_Z34__device_stub__cudaKernelTexture2DPhiimf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z19cudaKernelTexture2DPhiimf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z19cudaKernelTexture2DPhiimf,@object # @_Z19cudaKernelTexture2DPhiimf
.section .rodata,"a",@progbits
.globl _Z19cudaKernelTexture2DPhiimf
.p2align 3, 0x0
_Z19cudaKernelTexture2DPhiimf:
.quad _Z34__device_stub__cudaKernelTexture2DPhiimf
.size _Z19cudaKernelTexture2DPhiimf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z19cudaKernelTexture2DPhiimf"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z34__device_stub__cudaKernelTexture2DPhiimf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z19cudaKernelTexture2DPhiimf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __device__ inline double sq(double x) { return x*x;}
__device__ double optimsquare_eps_2d_descent(double u[4], double xi[4], double epsilon, double w, int steps) {
double no, nxi[4], r;
r = 1./(1+epsilon/4.);
u[0] -= xi[0]-xi[3];
for (int i=1;i<=3;i++) {
u[i] -= xi[i]-xi[i-1];
}
for (int it=0; it<steps; it++) {
if ((no = sq(nxi[0]=r*(.5*xi[0]+.25*(xi[3]+xi[1]+ u[1]-u[0])))
+ sq(nxi[1]=r*(.5*xi[1]+.25*(xi[0]+xi[2]+ u[2]-u[1])))
+ sq(nxi[2]=r*(.5*xi[2]+.25*(xi[1]+xi[3]+ u[3]-u[2])))
+ sq(nxi[3]=r*(.5*xi[3]+.25*(xi[2]+xi[0]+ u[0]-u[3])))) > w) {
no = sqrt(w/no);
} else {
no = 1;
}
xi[0]= nxi[0]*no;
xi[1]= nxi[1]*no;
xi[2]= nxi[2]*no;
xi[3]= nxi[3]*no;
}
u[0] += xi[0]-xi[3];
for (int i=1;i<=3;i++) {
u[i] += xi[i]-xi[i-1];
}
return 0.0;
}
__device__ double optimsquare_eps_2d(double u[4], double xi[4], double epsilon, double w, int steps)
{
double z0, z1, z2;
double t0, t1, t2;
double a, b;
double dno, no, noa, nob; // Derivative of the objective
double tm, tp;
double tmu;
u[0] -= xi[0]-xi[3];
for (int i=1;i<=3;i++) {
u[i] -= xi[i]-xi[i-1];
}
z0 = u[3]-u[1];
z1 = u[2]-u[0];
z2 = (u[0]+u[2])-(u[3]+u[1]);
a = z0*z0 + z1*z1;
b = z2*z2;
// If the current no is bigger than w, we do a Newton descent
// for solving f_{a,b} = w. Otherwise, we keep mu = 0.
tmu = epsilon;
no = a/((2+tmu)*(2+tmu))+b/((4+tmu)*(4+tmu));
if (no > w) {
for (int i=0; i < steps; i++) {
noa = a/((2+tmu)*(2+tmu));
nob = b/((4+tmu)*(4+tmu));
dno = noa/(2+tmu)+nob/(4+tmu);
tmu += .5*(noa+nob-w)/dno;
tmu = max(epsilon, tmu);
}
}
// Recover the values of xi and u after finding mu.
t0 = .5*z0/(2.+tmu);
t1 = .5*z1/(2.+tmu);
t2 = .5*z2/(4.+tmu);
tm = t0-t1;
tp = t0+t1;
xi[1] = tp+t2;
xi[2] = tm-t2;
xi[3] = t2-tp;
xi[0] = -tm-t2;
double s = sq(xi[0]) + sq(xi[1]) + sq(xi[2]) + sq(xi[3]);
if (s > w) {
double factor = sqrt(w/s);
for (int i=0; i<4; i++) {
xi[i] *= factor;
}
}
u[0] += xi[0]-xi[3];
for (int i=1;i<=3;i++) {
u[i] += xi[i]-xi[i-1];
}
return tmu;
}
__global__ void opt_eps_split(int sx, double *xi, double *u, double epsilon, double w, double ws, double we2, int L, int K, int steps, int use_newton, int is_even_step) {
int i,kk;
int l = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if ((l < L) && (k < K)) {
if (is_even_step) {
i = l * 2 * sx + 2 * k;
kk = l * K + k;
} else {
i = (1 + l * 2) * sx + 1 + 2 * k;
kk = l * K + k;
}
double aru[4];
aru[0]=u[i];
aru[1]=u[i+1];
aru[2]=u[i+1+sx];
aru[3]=u[i+sx];
double axi[4];
axi[0] = xi[kk*4];
axi[1] = xi[kk*4 + 1];
axi[2] = xi[kk*4 + 2];
axi[3] = xi[kk*4 + 3];
if (use_newton) {
optimsquare_eps_2d(aru, axi, epsilon, w, steps);
} else {
optimsquare_eps_2d_descent(aru, axi, epsilon, w, steps);
}
u[i]=aru[0];
u[i+1]=aru[1];
u[i+1+sx]=aru[2];
u[i+sx]=aru[3];
xi[kk*4] = axi[0];
xi[kk*4 + 1] = axi[1];
xi[kk*4 + 2] = axi[2];
xi[kk*4 + 3] = axi[3];
}
}
__global__ void over_relax_eps_2d(int sx, double *xio, double *xiobar, double *u, double theta, int Lo, int Ko, int is_even_step) {
int l = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if ((l < Lo) && (k < Ko)) {
int i, kk;
if (is_even_step) {
i = l * 2 * sx + 2 * k;
kk = l * Ko + k;
} else {
i = (1 + l * 2) * sx + 1 + 2 * k;
kk = l * Ko + k;
}
double dx[4];
int m;
int kx = kk * 4;
for (m=0; m < 4; m++)
dx[m] = theta * (xiobar[kx+m] - xio[kx+m]);
u[i] += dx[0]-dx[3];
u[i+1] += dx[1]-dx[0];
u[i+1+sx] += dx[2]-dx[1];
u[i+sx] += dx[3]-dx[2];
for (m=0; m<4; m++)
xio[kx+m] = xiobar[kx+m] + dx[m];
}
}
__global__ void gap_arr_eps_2d(int sx, double* gl, double *xie, double *u, double epsilon, double w, double ws, double we2, int Le, int Ke, int is_even_step) {
int l = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if ((l < Le) && (k < Ke)) {
int i;
if (is_even_step) {
i = 2 * l * sx + 2 * k;
} else {
i = (2 * l + 1) * sx + 1 + 2 * k;
}
int kx = 4*(l*Ke + k);
double aru[4], a[4], b, c, d, gap = 0;
double *xi = xie + kx;
aru[0]=u[i];
aru[1]=u[i+1];
aru[2]=u[i+1+sx];
aru[3]=u[i+sx];
// TV_e(Du) - <xi,Du> + e*xi^2/2
a[3] = aru[0]-aru[3];
b = a[3]*a[3];
c = xi[3]*a[3];
d = xi[3]*xi[3];
for (int m=0;m<3;m++) {
a[m] = aru[m+1]-aru[m];
b += a[m]*a[m];
c += xi[m]*a[m];
d += xi[m]*xi[m];
}
gap += epsilon*.5*d-c;
if (b < we2) {
gap += .5*b/epsilon; // here epsilon>0
} else {
gap += ws*sqrt(b)-.5*epsilon*w; // TV_eps
}
gl[l*Ke + k] = gap;
}
} | .file "tmpxft_00087176_00000000-6_kernels-2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26optimsquare_eps_2d_descentPdS_ddi
.type _Z26optimsquare_eps_2d_descentPdS_ddi, @function
_Z26optimsquare_eps_2d_descentPdS_ddi:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z26optimsquare_eps_2d_descentPdS_ddi, .-_Z26optimsquare_eps_2d_descentPdS_ddi
.globl _Z18optimsquare_eps_2dPdS_ddi
.type _Z18optimsquare_eps_2dPdS_ddi, @function
_Z18optimsquare_eps_2dPdS_ddi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z18optimsquare_eps_2dPdS_ddi, .-_Z18optimsquare_eps_2dPdS_ddi
.globl _Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii
.type _Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii, @function
_Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii:
.LFB2054:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 60(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movsd %xmm2, 16(%rsp)
movsd %xmm3, 8(%rsp)
movl %ecx, 56(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 256(%rsp), %rax
movq %rax, 208(%rsp)
leaq 264(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13opt_eps_splitiPdS_ddddiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii, .-_Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii
.globl _Z13opt_eps_splitiPdS_ddddiiiii
.type _Z13opt_eps_splitiPdS_ddddiiiii, @function
_Z13opt_eps_splitiPdS_ddddiiiii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z13opt_eps_splitiPdS_ddddiiiii, .-_Z13opt_eps_splitiPdS_ddddiiiii
.globl _Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii
.type _Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii, @function
_Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii:
.LFB2056:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %r8d, 40(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17over_relax_eps_2diPdS_S_diii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii, .-_Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii
.globl _Z17over_relax_eps_2diPdS_S_diii
.type _Z17over_relax_eps_2diPdS_S_diii, @function
_Z17over_relax_eps_2diPdS_S_diii:
.LFB2057:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z17over_relax_eps_2diPdS_S_diii, .-_Z17over_relax_eps_2diPdS_S_diii
.globl _Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii
.type _Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii, @function
_Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii:
.LFB2058:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 76(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movsd %xmm0, 40(%rsp)
movsd %xmm1, 32(%rsp)
movsd %xmm2, 24(%rsp)
movsd %xmm3, 16(%rsp)
movl %r8d, 72(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 12(%rsp), %rax
movq %rax, 216(%rsp)
leaq 256(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z14gap_arr_eps_2diPdS_S_ddddiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii, .-_Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii
.globl _Z14gap_arr_eps_2diPdS_S_ddddiii
.type _Z14gap_arr_eps_2diPdS_S_ddddiii, @function
_Z14gap_arr_eps_2diPdS_S_ddddiii:
.LFB2059:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z14gap_arr_eps_2diPdS_S_ddddiii, .-_Z14gap_arr_eps_2diPdS_S_ddddiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14gap_arr_eps_2diPdS_S_ddddiii"
.align 8
.LC1:
.string "_Z17over_relax_eps_2diPdS_S_diii"
.align 8
.LC2:
.string "_Z13opt_eps_splitiPdS_ddddiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14gap_arr_eps_2diPdS_S_ddddiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17over_relax_eps_2diPdS_S_diii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13opt_eps_splitiPdS_ddddiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __device__ inline double sq(double x) { return x*x;}
__device__ double optimsquare_eps_2d_descent(double u[4], double xi[4], double epsilon, double w, int steps) {
double no, nxi[4], r;
r = 1./(1+epsilon/4.);
u[0] -= xi[0]-xi[3];
for (int i=1;i<=3;i++) {
u[i] -= xi[i]-xi[i-1];
}
for (int it=0; it<steps; it++) {
if ((no = sq(nxi[0]=r*(.5*xi[0]+.25*(xi[3]+xi[1]+ u[1]-u[0])))
+ sq(nxi[1]=r*(.5*xi[1]+.25*(xi[0]+xi[2]+ u[2]-u[1])))
+ sq(nxi[2]=r*(.5*xi[2]+.25*(xi[1]+xi[3]+ u[3]-u[2])))
+ sq(nxi[3]=r*(.5*xi[3]+.25*(xi[2]+xi[0]+ u[0]-u[3])))) > w) {
no = sqrt(w/no);
} else {
no = 1;
}
xi[0]= nxi[0]*no;
xi[1]= nxi[1]*no;
xi[2]= nxi[2]*no;
xi[3]= nxi[3]*no;
}
u[0] += xi[0]-xi[3];
for (int i=1;i<=3;i++) {
u[i] += xi[i]-xi[i-1];
}
return 0.0;
}
__device__ double optimsquare_eps_2d(double u[4], double xi[4], double epsilon, double w, int steps)
{
double z0, z1, z2;
double t0, t1, t2;
double a, b;
double dno, no, noa, nob; // Derivative of the objective
double tm, tp;
double tmu;
u[0] -= xi[0]-xi[3];
for (int i=1;i<=3;i++) {
u[i] -= xi[i]-xi[i-1];
}
z0 = u[3]-u[1];
z1 = u[2]-u[0];
z2 = (u[0]+u[2])-(u[3]+u[1]);
a = z0*z0 + z1*z1;
b = z2*z2;
// If the current no is bigger than w, we do a Newton descent
// for solving f_{a,b} = w. Otherwise, we keep mu = 0.
tmu = epsilon;
no = a/((2+tmu)*(2+tmu))+b/((4+tmu)*(4+tmu));
if (no > w) {
for (int i=0; i < steps; i++) {
noa = a/((2+tmu)*(2+tmu));
nob = b/((4+tmu)*(4+tmu));
dno = noa/(2+tmu)+nob/(4+tmu);
tmu += .5*(noa+nob-w)/dno;
tmu = max(epsilon, tmu);
}
}
// Recover the values of xi and u after finding mu.
t0 = .5*z0/(2.+tmu);
t1 = .5*z1/(2.+tmu);
t2 = .5*z2/(4.+tmu);
tm = t0-t1;
tp = t0+t1;
xi[1] = tp+t2;
xi[2] = tm-t2;
xi[3] = t2-tp;
xi[0] = -tm-t2;
double s = sq(xi[0]) + sq(xi[1]) + sq(xi[2]) + sq(xi[3]);
if (s > w) {
double factor = sqrt(w/s);
for (int i=0; i<4; i++) {
xi[i] *= factor;
}
}
u[0] += xi[0]-xi[3];
for (int i=1;i<=3;i++) {
u[i] += xi[i]-xi[i-1];
}
return tmu;
}
__global__ void opt_eps_split(int sx, double *xi, double *u, double epsilon, double w, double ws, double we2, int L, int K, int steps, int use_newton, int is_even_step) {
int i,kk;
int l = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if ((l < L) && (k < K)) {
if (is_even_step) {
i = l * 2 * sx + 2 * k;
kk = l * K + k;
} else {
i = (1 + l * 2) * sx + 1 + 2 * k;
kk = l * K + k;
}
double aru[4];
aru[0]=u[i];
aru[1]=u[i+1];
aru[2]=u[i+1+sx];
aru[3]=u[i+sx];
double axi[4];
axi[0] = xi[kk*4];
axi[1] = xi[kk*4 + 1];
axi[2] = xi[kk*4 + 2];
axi[3] = xi[kk*4 + 3];
if (use_newton) {
optimsquare_eps_2d(aru, axi, epsilon, w, steps);
} else {
optimsquare_eps_2d_descent(aru, axi, epsilon, w, steps);
}
u[i]=aru[0];
u[i+1]=aru[1];
u[i+1+sx]=aru[2];
u[i+sx]=aru[3];
xi[kk*4] = axi[0];
xi[kk*4 + 1] = axi[1];
xi[kk*4 + 2] = axi[2];
xi[kk*4 + 3] = axi[3];
}
}
__global__ void over_relax_eps_2d(int sx, double *xio, double *xiobar, double *u, double theta, int Lo, int Ko, int is_even_step) {
int l = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if ((l < Lo) && (k < Ko)) {
int i, kk;
if (is_even_step) {
i = l * 2 * sx + 2 * k;
kk = l * Ko + k;
} else {
i = (1 + l * 2) * sx + 1 + 2 * k;
kk = l * Ko + k;
}
double dx[4];
int m;
int kx = kk * 4;
for (m=0; m < 4; m++)
dx[m] = theta * (xiobar[kx+m] - xio[kx+m]);
u[i] += dx[0]-dx[3];
u[i+1] += dx[1]-dx[0];
u[i+1+sx] += dx[2]-dx[1];
u[i+sx] += dx[3]-dx[2];
for (m=0; m<4; m++)
xio[kx+m] = xiobar[kx+m] + dx[m];
}
}
__global__ void gap_arr_eps_2d(int sx, double* gl, double *xie, double *u, double epsilon, double w, double ws, double we2, int Le, int Ke, int is_even_step) {
int l = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if ((l < Le) && (k < Ke)) {
int i;
if (is_even_step) {
i = 2 * l * sx + 2 * k;
} else {
i = (2 * l + 1) * sx + 1 + 2 * k;
}
int kx = 4*(l*Ke + k);
double aru[4], a[4], b, c, d, gap = 0;
double *xi = xie + kx;
aru[0]=u[i];
aru[1]=u[i+1];
aru[2]=u[i+1+sx];
aru[3]=u[i+sx];
// TV_e(Du) - <xi,Du> + e*xi^2/2
a[3] = aru[0]-aru[3];
b = a[3]*a[3];
c = xi[3]*a[3];
d = xi[3]*xi[3];
for (int m=0;m<3;m++) {
a[m] = aru[m+1]-aru[m];
b += a[m]*a[m];
c += xi[m]*a[m];
d += xi[m]*xi[m];
}
gap += epsilon*.5*d-c;
if (b < we2) {
gap += .5*b/epsilon; // here epsilon>0
} else {
gap += ws*sqrt(b)-.5*epsilon*w; // TV_eps
}
gl[l*Ke + k] = gap;
}
} | #ifndef KERNELS_EPS_2D_CUH
#define KERNELS_EPS_2D_CUH
__global__ void opt_eps_split(int sx, double *xi, double *u, double epsilon, double w, double ws, double we2, int L, int K, int steps, int use_newton, int is_even_step);
__global__ void over_relax_eps_2d(int sx, double *xio, double *xiobar, double *u, double theta, int Lo, int Ko, int is_even_step);
__global__ void gap_arr_eps_2d(int sx, double* gl, double *xie, double *u, double epsilon, double w, double ws, double we2, int Le, int Ke, int is_even_step);
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #ifndef KERNELS_EPS_2D_CUH
#define KERNELS_EPS_2D_CUH
__global__ void opt_eps_split(int sx, double *xi, double *u, double epsilon, double w, double ws, double we2, int L, int K, int steps, int use_newton, int is_even_step);
__global__ void over_relax_eps_2d(int sx, double *xio, double *xiobar, double *u, double theta, int Lo, int Ko, int is_even_step);
__global__ void gap_arr_eps_2d(int sx, double* gl, double *xie, double *u, double epsilon, double w, double ws, double we2, int Le, int Ke, int is_even_step);
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #ifndef KERNELS_EPS_2D_CUH
#define KERNELS_EPS_2D_CUH
__global__ void opt_eps_split(int sx, double *xi, double *u, double epsilon, double w, double ws, double we2, int L, int K, int steps, int use_newton, int is_even_step);
__global__ void over_relax_eps_2d(int sx, double *xio, double *xiobar, double *u, double theta, int Lo, int Ko, int is_even_step);
__global__ void gap_arr_eps_2d(int sx, double* gl, double *xie, double *u, double epsilon, double w, double ws, double we2, int Le, int Ke, int is_even_step);
#endif | .text
.file "kernels-2d.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00087176_00000000-6_kernels-2d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2032:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26optimsquare_eps_2d_descentPdS_ddi
.type _Z26optimsquare_eps_2d_descentPdS_ddi, @function
_Z26optimsquare_eps_2d_descentPdS_ddi:
.LFB2028:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2028:
.size _Z26optimsquare_eps_2d_descentPdS_ddi, .-_Z26optimsquare_eps_2d_descentPdS_ddi
.globl _Z18optimsquare_eps_2dPdS_ddi
.type _Z18optimsquare_eps_2dPdS_ddi, @function
_Z18optimsquare_eps_2dPdS_ddi:
.LFB2029:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2029:
.size _Z18optimsquare_eps_2dPdS_ddi, .-_Z18optimsquare_eps_2dPdS_ddi
.globl _Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii
.type _Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii, @function
_Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii:
.LFB2054:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 60(%rsp)
movq %rsi, 48(%rsp)
movq %rdx, 40(%rsp)
movsd %xmm0, 32(%rsp)
movsd %xmm1, 24(%rsp)
movsd %xmm2, 16(%rsp)
movsd %xmm3, 8(%rsp)
movl %ecx, 56(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
leaq 56(%rsp), %rax
movq %rax, 184(%rsp)
leaq 4(%rsp), %rax
movq %rax, 192(%rsp)
movq %rsp, %rax
movq %rax, 200(%rsp)
leaq 256(%rsp), %rax
movq %rax, 208(%rsp)
leaq 264(%rsp), %rax
movq %rax, 216(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 264
pushq 72(%rsp)
.cfi_def_cfa_offset 272
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z13opt_eps_splitiPdS_ddddiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2054:
.size _Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii, .-_Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii
.globl _Z13opt_eps_splitiPdS_ddddiiiii
.type _Z13opt_eps_splitiPdS_ddddiiiii, @function
_Z13opt_eps_splitiPdS_ddddiiiii:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z13opt_eps_splitiPdS_ddddiiiiiiPdS_ddddiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _Z13opt_eps_splitiPdS_ddddiiiii, .-_Z13opt_eps_splitiPdS_ddddiiiii
.globl _Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii
.type _Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii, @function
_Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii:
.LFB2056:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movsd %xmm0, 8(%rsp)
movl %r8d, 40(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 40(%rsp), %rax
movq %rax, 152(%rsp)
leaq 4(%rsp), %rax
movq %rax, 160(%rsp)
leaq 208(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17over_relax_eps_2diPdS_S_diii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2056:
.size _Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii, .-_Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii
.globl _Z17over_relax_eps_2diPdS_S_diii
.type _Z17over_relax_eps_2diPdS_S_diii, @function
_Z17over_relax_eps_2diPdS_S_diii:
.LFB2057:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z17over_relax_eps_2diPdS_S_diiiiPdS_S_diii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z17over_relax_eps_2diPdS_S_diii, .-_Z17over_relax_eps_2diPdS_S_diii
.globl _Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii
.type _Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii, @function
_Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii:
.LFB2058:
.cfi_startproc
endbr64
subq $248, %rsp
.cfi_def_cfa_offset 256
movl %edi, 76(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
movsd %xmm0, 40(%rsp)
movsd %xmm1, 32(%rsp)
movsd %xmm2, 24(%rsp)
movsd %xmm3, 16(%rsp)
movl %r8d, 72(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 232(%rsp)
xorl %eax, %eax
leaq 76(%rsp), %rax
movq %rax, 144(%rsp)
leaq 64(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 40(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 72(%rsp), %rax
movq %rax, 208(%rsp)
leaq 12(%rsp), %rax
movq %rax, 216(%rsp)
leaq 256(%rsp), %rax
movq %rax, 224(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
movl $1, 112(%rsp)
movl $1, 116(%rsp)
leaq 88(%rsp), %rcx
leaq 80(%rsp), %rdx
leaq 108(%rsp), %rsi
leaq 96(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 232(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $248, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 88(%rsp)
.cfi_def_cfa_offset 264
pushq 88(%rsp)
.cfi_def_cfa_offset 272
leaq 160(%rsp), %r9
movq 124(%rsp), %rcx
movl 132(%rsp), %r8d
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
leaq _Z14gap_arr_eps_2diPdS_S_ddddiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 256
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii, .-_Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii
.globl _Z14gap_arr_eps_2diPdS_S_ddddiii
.type _Z14gap_arr_eps_2diPdS_S_ddddiii, @function
_Z14gap_arr_eps_2diPdS_S_ddddiii:
.LFB2059:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z46__device_stub__Z14gap_arr_eps_2diPdS_S_ddddiiiiPdS_S_ddddiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _Z14gap_arr_eps_2diPdS_S_ddddiii, .-_Z14gap_arr_eps_2diPdS_S_ddddiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z14gap_arr_eps_2diPdS_S_ddddiii"
.align 8
.LC1:
.string "_Z17over_relax_eps_2diPdS_S_diii"
.align 8
.LC2:
.string "_Z13opt_eps_splitiPdS_ddddiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2061:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14gap_arr_eps_2diPdS_S_ddddiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17over_relax_eps_2diPdS_S_diii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z13opt_eps_splitiPdS_ddddiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernels-2d.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<cstdint>
typedef uint32_t u32;
__global__ void gen(u32 *src, int nsrc, u32 *choice, int nchoices, u32 *dest, int bufsize, int *ngen) {
__shared__ u32 some[256];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int nthreads = blockDim.x * gridDim.x;
for (int i = threadIdx.x; i < nchoices; i += blockDim.x) {
some[i] = choice[i];
}
__syncthreads();
int sum = 0;
for (int i = tid; i < nsrc; i += nthreads) {
u32 a = src[i];
for (int j = 0; j < nchoices; j++) {
if ((a & some[j]) == 0) {
int at = atomicAdd(ngen, 1);
if (at >= bufsize) goto bye;
dest[at] = a + some[j];
}
}
}
dest[tid] = sum;
return;
bye:
dest[tid] = 0;
}
int main() {
int nsrc = 1000000, nchoices = 100, bufsize = 30000000;
u32 *gsrc, *gchoice, *gdest;
int *gcnt;
cudaMalloc(&gsrc, sizeof(u32) * nsrc);
cudaMalloc(&gchoice, sizeof(u32) * nchoices);
cudaMalloc(&gdest, sizeof(u32) * bufsize);
cudaMalloc(&gcnt, sizeof(int));
u32 *src, *choice, *dest;
src = new u32[nsrc];
choice = new u32[nchoices];
dest = new u32[bufsize];
unsigned seed = 2;
for (int i = 0; i < nsrc; i++) {
src[i] = seed;
seed = seed*0xdefaced + 1;
}
for (int i = 0; i < nchoices; i++) {
u32 rr = seed;
seed = seed*0xdefaced + 1;
choice[i] = 0;
for (int yy = 0; yy < 5; yy++) {
choice[i] += 1<<(rr>>yy*5&31);
}
}
cudaMemcpy(gsrc, src, sizeof(u32) * nsrc, cudaMemcpyHostToDevice);
cudaMemcpy(gchoice, choice, sizeof(u32) * nchoices, cudaMemcpyHostToDevice);
cudaMemset(gcnt, 0, sizeof(int));
int ans = 0;
gen<<<40, 256>>>(gsrc, nsrc, gchoice, nchoices, gdest, bufsize, gcnt);
cudaMemcpy(&ans, gcnt, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(dest, gdest, sizeof(u32) * ans, cudaMemcpyDeviceToHost);
printf("generated: %d\n", ans);
} | code for sm_80
Function : _Z3genPjiS_iS_iPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x100 ; /* 0x000000c000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x001fda0003f06270 */
/*0060*/ @P0 BRA 0xf0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, R5 ; /* 0x000000ffff007224 */
/* 0x002fe400078e0005 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x0041e40000004800 */
/*00c0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x001fc80007ffe0ff */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x80 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ IMAD R0, R4, c[0x0][0x0], R5 ; /* 0x0000000004007a24 */
/* 0x000fc600078e0205 */
/*0130*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f06270 */
/*0140*/ BSSY B0, 0x410 ; /* 0x000002c000007945 */
/* 0x000fe40003800000 */
/*0150*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0004706670 */
/*0160*/ @P0 BRA 0x400 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0180*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0203 */
/*01a0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000162000c1e1900 */
/*01b0*/ BSSY B1, 0x3c0 ; /* 0x0000020000017945 */
/* 0x000fe20003800000 */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fca00078e00ff */
/*01d0*/ LDS R11, [R5.X4] ; /* 0x00000000050b7984 */
/* 0x000e620000004800 */
/*01e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*01f0*/ BSSY B2, 0x380 ; /* 0x0000018000027945 */
/* 0x000fe20003800000 */
/*0200*/ LOP3.LUT P0, RZ, R11, R10, RZ, 0xc0, !PT ; /* 0x0000000a0bff7212 */
/* 0x022fda000780c0ff */
/*0210*/ @P0 BRA 0x370 ; /* 0x0000015000000947 */
/* 0x001fea0003800000 */
/*0220*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x001e220000000000 */
/*0230*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff027624 */
/* 0x000fe200078e00ff */
/*0250*/ FLO.U32 R8, UR6 ; /* 0x0000000600087d00 */
/* 0x000e3000080e0000 */
/*0260*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x000e620008000000 */
/*0270*/ ISETP.EQ.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x001fc40003f02070 */
/*0280*/ MOV R3, c[0x0][0x194] ; /* 0x0000650000037a02 */
/* 0x000fd60000000f00 */
/*0290*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R3, [R2.64], R7 ; /* 0x00000007020309a8 */
/* 0x002ea800081ee1c4 */
/*02a0*/ S2R R9, SR_LTMASK ; /* 0x0000000000097919 */
/* 0x000e240000003900 */
/*02b0*/ LOP3.LUT R9, R9, UR6, RZ, 0xc0, !PT ; /* 0x0000000609097c12 */
/* 0x001fcc000f8ec0ff */
/*02c0*/ POPC R9, R9 ; /* 0x0000000900097309 */
/* 0x000e220000000000 */
/*02d0*/ SHFL.IDX PT, R6, R3, R8, 0x1f ; /* 0x00001f0803067589 */
/* 0x004e2400000e0000 */
/*02e0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x001fca00078e0209 */
/*02f0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x188], PT ; /* 0x0000620006007a0c */
/* 0x000fda0003f06270 */
/*0300*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0310*/ @P0 BREAK B1 ; /* 0x0000000000010942 */
/* 0x000fe20003800000 */
/*0320*/ @P0 BRA 0x400 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0340*/ IADD3 R7, R10, R11, RZ ; /* 0x0000000b0a077210 */
/* 0x000fc60007ffe0ff */
/*0350*/ IMAD.WIDE R2, R6, R3, c[0x0][0x180] ; /* 0x0000600006027625 */
/* 0x000fca00078e0203 */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0370*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc80007ffe0ff */
/*0390*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fda0003f06270 */
/*03a0*/ @!P0 BRA 0x1d0 ; /* 0xfffffe2000008947 */
/* 0x000fea000383ffff */
/*03b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*03d0*/ IMAD R4, R3, c[0x0][0xc], R4 ; /* 0x0000030003047a24 */
/* 0x000fca00078e0204 */
/*03e0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*03f0*/ @!P0 BRA 0x180 ; /* 0xfffffd8000008947 */
/* 0x000fea000383ffff */
/*0400*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0410*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0420*/ IMAD.WIDE R2, R0, R3, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fca00078e0203 */
/*0430*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0440*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0450*/ BRA 0x450; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<cstdint>
typedef uint32_t u32;
__global__ void gen(u32 *src, int nsrc, u32 *choice, int nchoices, u32 *dest, int bufsize, int *ngen) {
__shared__ u32 some[256];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int nthreads = blockDim.x * gridDim.x;
for (int i = threadIdx.x; i < nchoices; i += blockDim.x) {
some[i] = choice[i];
}
__syncthreads();
int sum = 0;
for (int i = tid; i < nsrc; i += nthreads) {
u32 a = src[i];
for (int j = 0; j < nchoices; j++) {
if ((a & some[j]) == 0) {
int at = atomicAdd(ngen, 1);
if (at >= bufsize) goto bye;
dest[at] = a + some[j];
}
}
}
dest[tid] = sum;
return;
bye:
dest[tid] = 0;
}
int main() {
int nsrc = 1000000, nchoices = 100, bufsize = 30000000;
u32 *gsrc, *gchoice, *gdest;
int *gcnt;
cudaMalloc(&gsrc, sizeof(u32) * nsrc);
cudaMalloc(&gchoice, sizeof(u32) * nchoices);
cudaMalloc(&gdest, sizeof(u32) * bufsize);
cudaMalloc(&gcnt, sizeof(int));
u32 *src, *choice, *dest;
src = new u32[nsrc];
choice = new u32[nchoices];
dest = new u32[bufsize];
unsigned seed = 2;
for (int i = 0; i < nsrc; i++) {
src[i] = seed;
seed = seed*0xdefaced + 1;
}
for (int i = 0; i < nchoices; i++) {
u32 rr = seed;
seed = seed*0xdefaced + 1;
choice[i] = 0;
for (int yy = 0; yy < 5; yy++) {
choice[i] += 1<<(rr>>yy*5&31);
}
}
cudaMemcpy(gsrc, src, sizeof(u32) * nsrc, cudaMemcpyHostToDevice);
cudaMemcpy(gchoice, choice, sizeof(u32) * nchoices, cudaMemcpyHostToDevice);
cudaMemset(gcnt, 0, sizeof(int));
int ans = 0;
gen<<<40, 256>>>(gsrc, nsrc, gchoice, nchoices, gdest, bufsize, gcnt);
cudaMemcpy(&ans, gcnt, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(dest, gdest, sizeof(u32) * ans, cudaMemcpyDeviceToHost);
printf("generated: %d\n", ans);
} | .file "tmpxft_0017c154_00000000-6_expansion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi
.type _Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi, @function
_Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3genPjiS_iS_iPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi, .-_Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi
.globl _Z3genPjiS_iS_iPi
.type _Z3genPjiS_iS_iPi, @function
_Z3genPjiS_iS_iPi:
.LFB2083:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3genPjiS_iS_iPi, .-_Z3genPjiS_iS_iPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "generated: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $120000000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4000000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $400, %edi
call _Znam@PLT
movq %rax, %rbx
movl $120000000, %edi
call _Znam@PLT
movq %rax, %r12
movq %rbp, %rax
leaq 4000000(%rbp), %rdx
movl $2, %esi
.L12:
movl %esi, (%rax)
imull $233811181, %esi, %esi
addl $1, %esi
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq %rbx, %r9
leaq 400(%rbx), %r11
movl $1, %r8d
jmp .L14
.L22:
movl %edx, (%r10)
addq $4, %r9
cmpq %r11, %r9
je .L21
.L14:
imull $233811181, %esi, %eax
movl %esi, %edi
leal 1(%rax), %esi
movq %r9, %r10
movl $0, %eax
movl $0, %edx
.L13:
movl %edi, %r14d
movl %eax, %ecx
shrl %cl, %r14d
movl %r14d, %ecx
movl %r8d, %r14d
sall %cl, %r14d
addl %r14d, %edx
addl $5, %eax
cmpl $25, %eax
jne .L13
jmp .L22
.L21:
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $0, 12(%rsp)
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $40, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq 48(%rsp)
.cfi_def_cfa_offset 144
movl $30000000, %r9d
movq 48(%rsp), %r8
movl $100, %ecx
movq 40(%rsp), %rdx
movl $1000000, %esi
movq 32(%rsp), %rdi
call _Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3genPjiS_iS_iPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3genPjiS_iS_iPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<cstdint>
typedef uint32_t u32;
__global__ void gen(u32 *src, int nsrc, u32 *choice, int nchoices, u32 *dest, int bufsize, int *ngen) {
__shared__ u32 some[256];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int nthreads = blockDim.x * gridDim.x;
for (int i = threadIdx.x; i < nchoices; i += blockDim.x) {
some[i] = choice[i];
}
__syncthreads();
int sum = 0;
for (int i = tid; i < nsrc; i += nthreads) {
u32 a = src[i];
for (int j = 0; j < nchoices; j++) {
if ((a & some[j]) == 0) {
int at = atomicAdd(ngen, 1);
if (at >= bufsize) goto bye;
dest[at] = a + some[j];
}
}
}
dest[tid] = sum;
return;
bye:
dest[tid] = 0;
}
int main() {
int nsrc = 1000000, nchoices = 100, bufsize = 30000000;
u32 *gsrc, *gchoice, *gdest;
int *gcnt;
cudaMalloc(&gsrc, sizeof(u32) * nsrc);
cudaMalloc(&gchoice, sizeof(u32) * nchoices);
cudaMalloc(&gdest, sizeof(u32) * bufsize);
cudaMalloc(&gcnt, sizeof(int));
u32 *src, *choice, *dest;
src = new u32[nsrc];
choice = new u32[nchoices];
dest = new u32[bufsize];
unsigned seed = 2;
for (int i = 0; i < nsrc; i++) {
src[i] = seed;
seed = seed*0xdefaced + 1;
}
for (int i = 0; i < nchoices; i++) {
u32 rr = seed;
seed = seed*0xdefaced + 1;
choice[i] = 0;
for (int yy = 0; yy < 5; yy++) {
choice[i] += 1<<(rr>>yy*5&31);
}
}
cudaMemcpy(gsrc, src, sizeof(u32) * nsrc, cudaMemcpyHostToDevice);
cudaMemcpy(gchoice, choice, sizeof(u32) * nchoices, cudaMemcpyHostToDevice);
cudaMemset(gcnt, 0, sizeof(int));
int ans = 0;
gen<<<40, 256>>>(gsrc, nsrc, gchoice, nchoices, gdest, bufsize, gcnt);
cudaMemcpy(&ans, gcnt, sizeof(int), cudaMemcpyDeviceToHost);
cudaMemcpy(dest, gdest, sizeof(u32) * ans, cudaMemcpyDeviceToHost);
printf("generated: %d\n", ans);
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<cstdint>
typedef uint32_t u32;
__global__ void gen(u32 *src, int nsrc, u32 *choice, int nchoices, u32 *dest, int bufsize, int *ngen) {
__shared__ u32 some[256];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int nthreads = blockDim.x * gridDim.x;
for (int i = threadIdx.x; i < nchoices; i += blockDim.x) {
some[i] = choice[i];
}
__syncthreads();
int sum = 0;
for (int i = tid; i < nsrc; i += nthreads) {
u32 a = src[i];
for (int j = 0; j < nchoices; j++) {
if ((a & some[j]) == 0) {
int at = atomicAdd(ngen, 1);
if (at >= bufsize) goto bye;
dest[at] = a + some[j];
}
}
}
dest[tid] = sum;
return;
bye:
dest[tid] = 0;
}
int main() {
int nsrc = 1000000, nchoices = 100, bufsize = 30000000;
u32 *gsrc, *gchoice, *gdest;
int *gcnt;
hipMalloc(&gsrc, sizeof(u32) * nsrc);
hipMalloc(&gchoice, sizeof(u32) * nchoices);
hipMalloc(&gdest, sizeof(u32) * bufsize);
hipMalloc(&gcnt, sizeof(int));
u32 *src, *choice, *dest;
src = new u32[nsrc];
choice = new u32[nchoices];
dest = new u32[bufsize];
unsigned seed = 2;
for (int i = 0; i < nsrc; i++) {
src[i] = seed;
seed = seed*0xdefaced + 1;
}
for (int i = 0; i < nchoices; i++) {
u32 rr = seed;
seed = seed*0xdefaced + 1;
choice[i] = 0;
for (int yy = 0; yy < 5; yy++) {
choice[i] += 1<<(rr>>yy*5&31);
}
}
hipMemcpy(gsrc, src, sizeof(u32) * nsrc, hipMemcpyHostToDevice);
hipMemcpy(gchoice, choice, sizeof(u32) * nchoices, hipMemcpyHostToDevice);
hipMemset(gcnt, 0, sizeof(int));
int ans = 0;
gen<<<40, 256>>>(gsrc, nsrc, gchoice, nchoices, gdest, bufsize, gcnt);
hipMemcpy(&ans, gcnt, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(dest, gdest, sizeof(u32) * ans, hipMemcpyDeviceToHost);
printf("generated: %d\n", ans);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<cstdint>
typedef uint32_t u32;
__global__ void gen(u32 *src, int nsrc, u32 *choice, int nchoices, u32 *dest, int bufsize, int *ngen) {
__shared__ u32 some[256];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int nthreads = blockDim.x * gridDim.x;
for (int i = threadIdx.x; i < nchoices; i += blockDim.x) {
some[i] = choice[i];
}
__syncthreads();
int sum = 0;
for (int i = tid; i < nsrc; i += nthreads) {
u32 a = src[i];
for (int j = 0; j < nchoices; j++) {
if ((a & some[j]) == 0) {
int at = atomicAdd(ngen, 1);
if (at >= bufsize) goto bye;
dest[at] = a + some[j];
}
}
}
dest[tid] = sum;
return;
bye:
dest[tid] = 0;
}
int main() {
int nsrc = 1000000, nchoices = 100, bufsize = 30000000;
u32 *gsrc, *gchoice, *gdest;
int *gcnt;
hipMalloc(&gsrc, sizeof(u32) * nsrc);
hipMalloc(&gchoice, sizeof(u32) * nchoices);
hipMalloc(&gdest, sizeof(u32) * bufsize);
hipMalloc(&gcnt, sizeof(int));
u32 *src, *choice, *dest;
src = new u32[nsrc];
choice = new u32[nchoices];
dest = new u32[bufsize];
unsigned seed = 2;
for (int i = 0; i < nsrc; i++) {
src[i] = seed;
seed = seed*0xdefaced + 1;
}
for (int i = 0; i < nchoices; i++) {
u32 rr = seed;
seed = seed*0xdefaced + 1;
choice[i] = 0;
for (int yy = 0; yy < 5; yy++) {
choice[i] += 1<<(rr>>yy*5&31);
}
}
hipMemcpy(gsrc, src, sizeof(u32) * nsrc, hipMemcpyHostToDevice);
hipMemcpy(gchoice, choice, sizeof(u32) * nchoices, hipMemcpyHostToDevice);
hipMemset(gcnt, 0, sizeof(int));
int ans = 0;
gen<<<40, 256>>>(gsrc, nsrc, gchoice, nchoices, gdest, bufsize, gcnt);
hipMemcpy(&ans, gcnt, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(dest, gdest, sizeof(u32) * ans, hipMemcpyDeviceToHost);
printf("generated: %d\n", ans);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3genPjiS_iS_iPi
.globl _Z3genPjiS_iS_iPi
.p2align 8
.type _Z3genPjiS_iS_iPi,@function
_Z3genPjiS_iS_iPi:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s13, s[0:1], 0x38
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s2, 0xffff
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v3, 2, v0
v_mov_b32_e32 v1, v0
s_lshl_b32 s5, s12, 2
s_mov_b32 s6, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s12, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b32 v2, v[4:5], off
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
v_add_nc_u32_e32 v3, s5, v3
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
s_load_b32 s9, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x20
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
v_mov_b32_e32 v4, 5
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s9, v1
s_cbranch_execz .LBB0_22
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s11, s[0:1], 0x28
s_load_b64 s[6:7], s[0:1], 0x30
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, v1
s_cmp_gt_i32 s8, 0
s_mul_i32 s13, s13, s12
s_cselect_b32 s1, -1, 0
s_mov_b32 s12, 0
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s0
s_or_b32 s12, s0, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_21
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_18
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s15, 0
s_mov_b32 s14, 0
s_mov_b32 s16, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v5, v[3:4], off
s_branch .LBB0_9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s17
s_or_b32 s14, s0, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_17
.LBB0_9:
v_mov_b32_e32 v3, s15
s_mov_b32 s17, -1
s_mov_b32 s0, -1
s_mov_b32 s18, exec_lo
ds_load_b32 v6, v3
s_waitcnt vmcnt(0) lgkmcnt(0)
v_and_b32_e32 v3, v6, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_15
s_mov_b32 s19, exec_lo
s_mov_b32 s0, exec_lo
v_mbcnt_lo_u32_b32 v3, s19, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_12
s_bcnt1_i32_b32 s19, s19
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v4, s19
global_atomic_add_u32 v4, v0, v4, s[6:7] glc
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v4, 11 :: v_dual_add_nc_u32 v3, s0, v3
v_cmp_gt_i32_e32 vcc_lo, s11, v3
s_and_saveexec_b32 s19, vcc_lo
s_cbranch_execz .LBB0_14
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v8, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v6, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s3, v4, s0
v_mov_b32_e32 v4, 0
global_store_b32 v[6:7], v8, off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s0, vcc_lo, exec_lo
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s18, s0
s_cbranch_execz .LBB0_8
s_add_i32 s16, s16, -1
s_add_i32 s15, s15, 4
s_cmp_eq_u32 s16, 0
v_mov_b32_e32 v4, 8
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s17, s0, exec_lo
s_branch .LBB0_8
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s14
s_branch .LBB0_19
.LBB0_18:
v_mov_b32_e32 v4, 8
.LBB0_19:
s_mov_b32 s0, -1
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 8, v4
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v2, s13, v2
v_mov_b32_e32 v4, 5
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s9, v2
s_or_not1_b32 s0, vcc_lo, exec_lo
s_branch .LBB0_5
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s12
.LBB0_22:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
s_mov_b32 s0, -1
s_mov_b32 s1, exec_lo
v_cmpx_gt_i32_e32 11, v4
v_cmp_eq_u32_e32 vcc_lo, 5, v4
s_or_not1_b32 s0, vcc_lo, exec_lo
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_26:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3genPjiS_iS_iPi
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3genPjiS_iS_iPi, .Lfunc_end0-_Z3genPjiS_iS_iPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3genPjiS_iS_iPi
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z3genPjiS_iS_iPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<cstdint>
typedef uint32_t u32;
__global__ void gen(u32 *src, int nsrc, u32 *choice, int nchoices, u32 *dest, int bufsize, int *ngen) {
__shared__ u32 some[256];
int tid = threadIdx.x + blockIdx.x * blockDim.x;
int nthreads = blockDim.x * gridDim.x;
for (int i = threadIdx.x; i < nchoices; i += blockDim.x) {
some[i] = choice[i];
}
__syncthreads();
int sum = 0;
for (int i = tid; i < nsrc; i += nthreads) {
u32 a = src[i];
for (int j = 0; j < nchoices; j++) {
if ((a & some[j]) == 0) {
int at = atomicAdd(ngen, 1);
if (at >= bufsize) goto bye;
dest[at] = a + some[j];
}
}
}
dest[tid] = sum;
return;
bye:
dest[tid] = 0;
}
int main() {
int nsrc = 1000000, nchoices = 100, bufsize = 30000000;
u32 *gsrc, *gchoice, *gdest;
int *gcnt;
hipMalloc(&gsrc, sizeof(u32) * nsrc);
hipMalloc(&gchoice, sizeof(u32) * nchoices);
hipMalloc(&gdest, sizeof(u32) * bufsize);
hipMalloc(&gcnt, sizeof(int));
u32 *src, *choice, *dest;
src = new u32[nsrc];
choice = new u32[nchoices];
dest = new u32[bufsize];
unsigned seed = 2;
for (int i = 0; i < nsrc; i++) {
src[i] = seed;
seed = seed*0xdefaced + 1;
}
for (int i = 0; i < nchoices; i++) {
u32 rr = seed;
seed = seed*0xdefaced + 1;
choice[i] = 0;
for (int yy = 0; yy < 5; yy++) {
choice[i] += 1<<(rr>>yy*5&31);
}
}
hipMemcpy(gsrc, src, sizeof(u32) * nsrc, hipMemcpyHostToDevice);
hipMemcpy(gchoice, choice, sizeof(u32) * nchoices, hipMemcpyHostToDevice);
hipMemset(gcnt, 0, sizeof(int));
int ans = 0;
gen<<<40, 256>>>(gsrc, nsrc, gchoice, nchoices, gdest, bufsize, gcnt);
hipMemcpy(&ans, gcnt, sizeof(int), hipMemcpyDeviceToHost);
hipMemcpy(dest, gdest, sizeof(u32) * ans, hipMemcpyDeviceToHost);
printf("generated: %d\n", ans);
} | .text
.file "expansion.hip"
.globl _Z18__device_stub__genPjiS_iS_iPi # -- Begin function _Z18__device_stub__genPjiS_iS_iPi
.p2align 4, 0x90
.type _Z18__device_stub__genPjiS_iS_iPi,@function
_Z18__device_stub__genPjiS_iS_iPi: # @_Z18__device_stub__genPjiS_iS_iPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3genPjiS_iS_iPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z18__device_stub__genPjiS_iS_iPi, .Lfunc_end0-_Z18__device_stub__genPjiS_iS_iPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $208, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 48(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 40(%rsp), %rdi
movl $120000000, %esi # imm = 0x7270E00
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %r15
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r14
movl $120000000, %edi # imm = 0x7270E00
callq _Znam
movq %rax, %rbx
movl $2, %esi
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %esi, (%r15,%rax,4)
imull $233811181, %esi, %esi # imm = 0xDEFACED
incl %esi
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
imull $233811181, %esi, %r8d # imm = 0xDEFACED
movl $0, (%r14,%rdi,4)
xorl %eax, %eax
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, %edx
movl %eax, %ecx
shrl %cl, %edx
movl $1, %r10d
movl %edx, %ecx
shll %cl, %r10d
addl %r10d, %r9d
addl $5, %eax
cmpl $25, %eax
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
incl %r8d
movl %r9d, (%r14,%rdi,4)
incq %rdi
movl %r8d, %esi
cmpq $100, %rdi
jne .LBB1_3
# %bb.6:
movq 56(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4, %edx
xorl %esi, %esi
callq hipMemset
movl $0, 12(%rsp)
movabsq $4294967336, %rdi # imm = 0x100000028
leaq 216(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rax, 136(%rsp)
movl $1000000, 36(%rsp) # imm = 0xF4240
movq %rcx, 128(%rsp)
movl $100, 32(%rsp)
movq %rdx, 120(%rsp)
movl $30000000, 28(%rsp) # imm = 0x1C9C380
movq %rsi, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 28(%rsp), %rax
movq %rax, 184(%rsp)
leaq 112(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z3genPjiS_iS_iPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 16(%rsp), %rsi
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $208, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3genPjiS_iS_iPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3genPjiS_iS_iPi,@object # @_Z3genPjiS_iS_iPi
.section .rodata,"a",@progbits
.globl _Z3genPjiS_iS_iPi
.p2align 3, 0x0
_Z3genPjiS_iS_iPi:
.quad _Z18__device_stub__genPjiS_iS_iPi
.size _Z3genPjiS_iS_iPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "generated: %d\n"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3genPjiS_iS_iPi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__genPjiS_iS_iPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3genPjiS_iS_iPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3genPjiS_iS_iPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x100 ; /* 0x000000c000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0050*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x001fda0003f06270 */
/*0060*/ @P0 BRA 0xf0 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*0070*/ IMAD.MOV.U32 R0, RZ, RZ, R5 ; /* 0x000000ffff007224 */
/* 0x002fe400078e0005 */
/*0080*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0203 */
/*00a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ STS [R0.X4], R3 ; /* 0x0000000300007388 */
/* 0x0041e40000004800 */
/*00c0*/ IADD3 R0, R0, c[0x0][0x0], RZ ; /* 0x0000000000007a10 */
/* 0x001fc80007ffe0ff */
/*00d0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x80 ; /* 0xffffff9000008947 */
/* 0x000fea000383ffff */
/*00f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x002fea0003800000 */
/*0100*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff027624 */
/* 0x000fe200078e00ff */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0120*/ IMAD R0, R4, c[0x0][0x0], R5 ; /* 0x0000000004007a24 */
/* 0x000fc600078e0205 */
/*0130*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe40003f06270 */
/*0140*/ BSSY B0, 0x410 ; /* 0x000002c000007945 */
/* 0x000fe40003800000 */
/*0150*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], !P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0004706670 */
/*0160*/ @P0 BRA 0x400 ; /* 0x0000029000000947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0180*/ MOV R3, 0x4 ; /* 0x0000000400037802 */
/* 0x000fca0000000f00 */
/*0190*/ IMAD.WIDE R2, R4, R3, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fca00078e0203 */
/*01a0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000162000c1e1900 */
/*01b0*/ BSSY B1, 0x3c0 ; /* 0x0000020000017945 */
/* 0x000fe20003800000 */
/*01c0*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fca00078e00ff */
/*01d0*/ LDS R11, [R5.X4] ; /* 0x00000000050b7984 */
/* 0x000e620000004800 */
/*01e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*01f0*/ BSSY B2, 0x380 ; /* 0x0000018000027945 */
/* 0x000fe20003800000 */
/*0200*/ LOP3.LUT P0, RZ, R11, R10, RZ, 0xc0, !PT ; /* 0x0000000a0bff7212 */
/* 0x022fda000780c0ff */
/*0210*/ @P0 BRA 0x370 ; /* 0x0000015000000947 */
/* 0x001fea0003800000 */
/*0220*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x001e220000000000 */
/*0230*/ VOTEU.ANY UR6, UPT, PT ; /* 0x0000000000067886 */
/* 0x000fe200038e0100 */
/*0240*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x190] ; /* 0x00006400ff027624 */
/* 0x000fe200078e00ff */
/*0250*/ FLO.U32 R8, UR6 ; /* 0x0000000600087d00 */
/* 0x000e3000080e0000 */
/*0260*/ POPC R7, UR6 ; /* 0x0000000600077d09 */
/* 0x000e620008000000 */
/*0270*/ ISETP.EQ.U32.AND P0, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x001fc40003f02070 */
/*0280*/ MOV R3, c[0x0][0x194] ; /* 0x0000650000037a02 */
/* 0x000fd60000000f00 */
/*0290*/ @P0 ATOMG.E.ADD.STRONG.GPU PT, R3, [R2.64], R7 ; /* 0x00000007020309a8 */
/* 0x002ea800081ee1c4 */
/*02a0*/ S2R R9, SR_LTMASK ; /* 0x0000000000097919 */
/* 0x000e240000003900 */
/*02b0*/ LOP3.LUT R9, R9, UR6, RZ, 0xc0, !PT ; /* 0x0000000609097c12 */
/* 0x001fcc000f8ec0ff */
/*02c0*/ POPC R9, R9 ; /* 0x0000000900097309 */
/* 0x000e220000000000 */
/*02d0*/ SHFL.IDX PT, R6, R3, R8, 0x1f ; /* 0x00001f0803067589 */
/* 0x004e2400000e0000 */
/*02e0*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x001fca00078e0209 */
/*02f0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x188], PT ; /* 0x0000620006007a0c */
/* 0x000fda0003f06270 */
/*0300*/ @P0 BREAK B2 ; /* 0x0000000000020942 */
/* 0x000fe20003800000 */
/*0310*/ @P0 BREAK B1 ; /* 0x0000000000010942 */
/* 0x000fe20003800000 */
/*0320*/ @P0 BRA 0x400 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0330*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0340*/ IADD3 R7, R10, R11, RZ ; /* 0x0000000b0a077210 */
/* 0x000fc60007ffe0ff */
/*0350*/ IMAD.WIDE R2, R6, R3, c[0x0][0x180] ; /* 0x0000600006027625 */
/* 0x000fca00078e0203 */
/*0360*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0370*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0380*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fc80007ffe0ff */
/*0390*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fda0003f06270 */
/*03a0*/ @!P0 BRA 0x1d0 ; /* 0xfffffe2000008947 */
/* 0x000fea000383ffff */
/*03b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*03c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff037624 */
/* 0x001fc800078e00ff */
/*03d0*/ IMAD R4, R3, c[0x0][0xc], R4 ; /* 0x0000030003047a24 */
/* 0x000fca00078e0204 */
/*03e0*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x168], PT ; /* 0x00005a0004007a0c */
/* 0x000fda0003f06270 */
/*03f0*/ @!P0 BRA 0x180 ; /* 0xfffffd8000008947 */
/* 0x000fea000383ffff */
/*0400*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0410*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0420*/ IMAD.WIDE R2, R0, R3, c[0x0][0x180] ; /* 0x0000600000027625 */
/* 0x000fca00078e0203 */
/*0430*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*0440*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0450*/ BRA 0x450; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0480*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0490*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3genPjiS_iS_iPi
.globl _Z3genPjiS_iS_iPi
.p2align 8
.type _Z3genPjiS_iS_iPi,@function
_Z3genPjiS_iS_iPi:
s_clause 0x2
s_load_b32 s8, s[0:1], 0x18
s_load_b32 s2, s[0:1], 0x44
s_load_b32 s13, s[0:1], 0x38
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s2, 0xffff
v_cmpx_gt_i32_e64 s8, v0
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_lshlrev_b32_e32 v3, 2, v0
v_mov_b32_e32 v1, v0
s_lshl_b32 s5, s12, 2
s_mov_b32 s6, 0
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[4:5], 2, v[1:2]
v_add_nc_u32_e32 v1, s12, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_load_b32 v2, v[4:5], off
s_or_b32 s6, vcc_lo, s6
s_waitcnt vmcnt(0)
ds_store_b32 v3, v2
v_add_nc_u32_e32 v3, s5, v3
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
s_load_b32 s9, s[0:1], 0x8
s_load_b64 s[2:3], s[0:1], 0x20
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
v_mov_b32_e32 v4, 5
s_mov_b32 s10, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmpx_gt_i32_e64 s9, v1
s_cbranch_execz .LBB0_22
s_clause 0x2
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s11, s[0:1], 0x28
s_load_b64 s[6:7], s[0:1], 0x30
v_mov_b32_e32 v0, 0
v_mov_b32_e32 v2, v1
s_cmp_gt_i32 s8, 0
s_mul_i32 s13, s13, s12
s_cselect_b32 s1, -1, 0
s_mov_b32 s12, 0
s_branch .LBB0_6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s0
s_or_b32 s12, s0, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s12
s_cbranch_execz .LBB0_21
.LBB0_6:
s_and_not1_b32 vcc_lo, exec_lo, s1
s_cbranch_vccnz .LBB0_18
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s15, 0
s_mov_b32 s14, 0
s_mov_b32 s16, s8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v5, v[3:4], off
s_branch .LBB0_9
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s17
s_or_b32 s14, s0, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s14
s_cbranch_execz .LBB0_17
.LBB0_9:
v_mov_b32_e32 v3, s15
s_mov_b32 s17, -1
s_mov_b32 s0, -1
s_mov_b32 s18, exec_lo
ds_load_b32 v6, v3
s_waitcnt vmcnt(0) lgkmcnt(0)
v_and_b32_e32 v3, v6, v5
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_15
s_mov_b32 s19, exec_lo
s_mov_b32 s0, exec_lo
v_mbcnt_lo_u32_b32 v3, s19, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_12
s_bcnt1_i32_b32 s19, s19
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v4, s19
global_atomic_add_u32 v4, v0, v4, s[6:7] glc
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v4, 11 :: v_dual_add_nc_u32 v3, s0, v3
v_cmp_gt_i32_e32 vcc_lo, s11, v3
s_and_saveexec_b32 s19, vcc_lo
s_cbranch_execz .LBB0_14
v_ashrrev_i32_e32 v4, 31, v3
v_add_nc_u32_e32 v8, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v6, s0, s2, v3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s0, s3, v4, s0
v_mov_b32_e32 v4, 0
global_store_b32 v[6:7], v8, off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s19
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s0, vcc_lo, exec_lo
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s18
s_and_saveexec_b32 s18, s0
s_cbranch_execz .LBB0_8
s_add_i32 s16, s16, -1
s_add_i32 s15, s15, 4
s_cmp_eq_u32 s16, 0
v_mov_b32_e32 v4, 8
s_cselect_b32 s0, -1, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s17, s0, exec_lo
s_branch .LBB0_8
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s14
s_branch .LBB0_19
.LBB0_18:
v_mov_b32_e32 v4, 8
.LBB0_19:
s_mov_b32 s0, -1
s_mov_b32 s14, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 8, v4
s_cbranch_execz .LBB0_5
v_add_nc_u32_e32 v2, s13, v2
v_mov_b32_e32 v4, 5
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_i32_e32 vcc_lo, s9, v2
s_or_not1_b32 s0, vcc_lo, exec_lo
s_branch .LBB0_5
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s12
.LBB0_22:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
s_mov_b32 s0, -1
s_mov_b32 s1, exec_lo
v_cmpx_gt_i32_e32 11, v4
v_cmp_eq_u32_e32 vcc_lo, 5, v4
s_or_not1_b32 s0, vcc_lo, exec_lo
s_or_b32 exec_lo, exec_lo, s1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
v_add_co_u32 v0, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_26:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3genPjiS_iS_iPi
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3genPjiS_iS_iPi, .Lfunc_end0-_Z3genPjiS_iS_iPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3genPjiS_iS_iPi
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z3genPjiS_iS_iPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017c154_00000000-6_expansion.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi
.type _Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi, @function
_Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi:
.LFB2082:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movl %esi, 36(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 32(%rsp)
movq %r8, 16(%rsp)
movl %r9d, 12(%rsp)
movq 192(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 36(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movq %rsp, %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z3genPjiS_iS_iPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi, .-_Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi
.globl _Z3genPjiS_iS_iPi
.type _Z3genPjiS_iS_iPi, @function
_Z3genPjiS_iS_iPi:
.LFB2083:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3genPjiS_iS_iPi, .-_Z3genPjiS_iS_iPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "generated: %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $88, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $400, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $120000000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $4000000, %edi
call _Znam@PLT
movq %rax, %rbp
movl $400, %edi
call _Znam@PLT
movq %rax, %rbx
movl $120000000, %edi
call _Znam@PLT
movq %rax, %r12
movq %rbp, %rax
leaq 4000000(%rbp), %rdx
movl $2, %esi
.L12:
movl %esi, (%rax)
imull $233811181, %esi, %esi
addl $1, %esi
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq %rbx, %r9
leaq 400(%rbx), %r11
movl $1, %r8d
jmp .L14
.L22:
movl %edx, (%r10)
addq $4, %r9
cmpq %r11, %r9
je .L21
.L14:
imull $233811181, %esi, %eax
movl %esi, %edi
leal 1(%rax), %esi
movq %r9, %r10
movl $0, %eax
movl $0, %edx
.L13:
movl %edi, %r14d
movl %eax, %ecx
shrl %cl, %r14d
movl %r14d, %ecx
movl %r8d, %r14d
sall %cl, %r14d
addl %r14d, %edx
addl $5, %eax
cmpl $25, %eax
jne .L13
jmp .L22
.L21:
movl $1, %ecx
movl $4000000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $400, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $4, %edx
movl $0, %esi
movq 40(%rsp), %rdi
call cudaMemset@PLT
movl $0, 12(%rsp)
movl $256, 60(%rsp)
movl $1, 64(%rsp)
movl $40, 48(%rsp)
movl $1, 52(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L15:
leaq 12(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 40(%rsp), %rsi
call cudaMemcpy@PLT
movslq 12(%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movl 12(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L24
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
subq $8, %rsp
.cfi_def_cfa_offset 136
pushq 48(%rsp)
.cfi_def_cfa_offset 144
movl $30000000, %r9d
movq 48(%rsp), %r8
movl $100, %ecx
movq 40(%rsp), %rdx
movl $1000000, %esi
movq 32(%rsp), %rdi
call _Z31__device_stub__Z3genPjiS_iS_iPiPjiS_iS_iPi
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L15
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z3genPjiS_iS_iPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z3genPjiS_iS_iPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "expansion.hip"
.globl _Z18__device_stub__genPjiS_iS_iPi # -- Begin function _Z18__device_stub__genPjiS_iS_iPi
.p2align 4, 0x90
.type _Z18__device_stub__genPjiS_iS_iPi,@function
_Z18__device_stub__genPjiS_iS_iPi: # @_Z18__device_stub__genPjiS_iS_iPi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 80(%rsp)
movl %ecx, 16(%rsp)
movq %r8, 72(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z3genPjiS_iS_iPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z18__device_stub__genPjiS_iS_iPi, .Lfunc_end0-_Z18__device_stub__genPjiS_iS_iPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $208, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 56(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 48(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hipMalloc
leaq 40(%rsp), %rdi
movl $120000000, %esi # imm = 0x7270E00
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %r15
movl $400, %edi # imm = 0x190
callq _Znam
movq %rax, %r14
movl $120000000, %edi # imm = 0x7270E00
callq _Znam
movq %rax, %rbx
movl $2, %esi
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl %esi, (%r15,%rax,4)
imull $233811181, %esi, %esi # imm = 0xDEFACED
incl %esi
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
imull $233811181, %esi, %r8d # imm = 0xDEFACED
movl $0, (%r14,%rdi,4)
xorl %eax, %eax
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_3 Depth=1
# => This Inner Loop Header: Depth=2
movl %esi, %edx
movl %eax, %ecx
shrl %cl, %edx
movl $1, %r10d
movl %edx, %ecx
shll %cl, %r10d
addl %r10d, %r9d
addl $5, %eax
cmpl $25, %eax
jne .LBB1_4
# %bb.5: # in Loop: Header=BB1_3 Depth=1
incl %r8d
movl %r9d, (%r14,%rdi,4)
incq %rdi
movl %r8d, %esi
cmpq $100, %rdi
jne .LBB1_3
# %bb.6:
movq 56(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
movl $400, %edx # imm = 0x190
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4, %edx
xorl %esi, %esi
callq hipMemset
movl $0, 12(%rsp)
movabsq $4294967336, %rdi # imm = 0x100000028
leaq 216(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_8
# %bb.7:
movq 56(%rsp), %rax
movq 48(%rsp), %rcx
movq 40(%rsp), %rdx
movq 16(%rsp), %rsi
movq %rax, 136(%rsp)
movl $1000000, 36(%rsp) # imm = 0xF4240
movq %rcx, 128(%rsp)
movl $100, 32(%rsp)
movq %rdx, 120(%rsp)
movl $30000000, 28(%rsp) # imm = 0x1C9C380
movq %rsi, 112(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 32(%rsp), %rax
movq %rax, 168(%rsp)
leaq 120(%rsp), %rax
movq %rax, 176(%rsp)
leaq 28(%rsp), %rax
movq %rax, 184(%rsp)
leaq 112(%rsp), %rax
movq %rax, 192(%rsp)
leaq 96(%rsp), %rdi
leaq 80(%rsp), %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z3genPjiS_iS_iPi, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_8:
movq 16(%rsp), %rsi
leaq 12(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movq 40(%rsp), %rsi
movslq 12(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl 12(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
xorl %eax, %eax
addq $208, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3genPjiS_iS_iPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3genPjiS_iS_iPi,@object # @_Z3genPjiS_iS_iPi
.section .rodata,"a",@progbits
.globl _Z3genPjiS_iS_iPi
.p2align 3, 0x0
_Z3genPjiS_iS_iPi:
.quad _Z18__device_stub__genPjiS_iS_iPi
.size _Z3genPjiS_iS_iPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "generated: %d\n"
.size .L.str, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3genPjiS_iS_iPi"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__genPjiS_iS_iPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3genPjiS_iS_iPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "merge_func.cuh"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void MergeRank(float * d_input, float * d_output)
{
int indexA = blockIdx.x * blockDim.x + threadIdx.x;
int indexB = indexA + 2048;
float temp1 = d_input[indexA];
float temp2 = d_input[indexB];
int indexAB = 2048;
while (d_input[indexAB] < temp1) {
indexAB++;
}
int indexBA = 0;
while (d_input[indexBA] < temp2) {
indexBA++;
}
__syncthreads();
d_output[indexA + indexAB + 1] = temp1;
d_output[indexB + indexBA + 1] = temp2;
}
void orderBitonicArray(float* d_in, int size, int part_size, float* d_out, bool log)
{
/**
* \brief Order output array of the bitonic sort function
* \param d_in - a partially sorted array, global memory, gpu
* \param size - the size of the input array
* \param part_size - the size of a sorted subarray
* \param d_out - a pointer to the output array, global memory, gpu, where
* function execution result will be stored
* \param log - show information about performance during each step
* \return
* void
*/
int iter_number = static_cast<int>(log2(size / part_size));
int init_num_threads = size / (2 * part_size);
int init_num_blocks = ((init_num_threads - 1) / 1024) + 1;
if (log)
{
std::cout << "--------------------------start log--------------------------------" << std::endl;
std::cout << "Number of steps\t" << iter_number << std::endl;
}
float* t_d_in = d_in;
for (int i = 0; i < iter_number; i++)
{
if (log)
{
std::cout << "-------------------------------------------------------------------" << std::endl;
std::cout << "Merging step #" << i << std::endl;
std::cout << "Number of blocks\t" << init_num_threads << std::endl;
std::cout << "Number of threads\t" << init_num_threads << std::endl;
}
mergingKernel << <init_num_blocks, init_num_threads >> >(t_d_in, part_size, d_out);
part_size *= 2;
init_num_threads = init_num_threads / 2;
init_num_blocks = ((init_num_threads - 1) / 1024) + 1;
cudaFree(t_d_in);
cudaMalloc((void **)&t_d_in, size * sizeof(int));
cudaMemcpy(t_d_in, d_out, size * sizeof(int), cudaMemcpyDeviceToDevice);
if (log)
{
float *out = new float[size];
cudaMemcpy(out, d_out, size * sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < size; i++) {
std::cout << out[i] << "\t";
}
std::cout << std::endl;
std::cout << std::endl;
delete[] out;
if (i == iter_number - 1)
{
std::cout << "----------------------------end log--------------------------------" << std::endl;
}
}
}
}
__global__ void mergingKernel(float* in_array, int part_size, float* out_array)
{
/**
* \brief kernel function for merging of the arrays of the partially sorted array
* \param in_array - the input array
* \param part_size - the size of a sorted subarray
* \param out_array - a pointer to the output array,
* where result of merging will be stored
* \return
* void
*/
int index = blockDim.x * blockIdx.x + threadIdx.x;
float* arr_left = in_array + 2 * part_size * index;
float* arr_right = arr_left + part_size;
int out_shift = 2 * part_size * index;
mergeArraysAsc(arr_left, arr_right, part_size, part_size, out_array, out_shift);
__syncthreads();
}
__device__ void mergeArraysAsc(float* arr_left, float* arr_right, int length_left, int length_right, float* out, int out_shift)
{
/**
* \brief Helper function for the mergingKernel function, merges subarrays
* \param arr_left - the first sorted array
* \param arr_right - the second sorted array
* \param length_left - size of the first array
* \param length_right - size of the second array
* \param out - a pointer to the output array, where result will be stored
* \param out_shift - shift, from which to start writing in output array.
* \return
* void
*/
int totalLength = length_left + length_right;
//running indices
int i = 0;
int j = 0;
int index = out_shift;
while (i < length_left && j < length_right)
{
if (arr_left[i] <= arr_right[j])
{
out[index] = arr_left[i];
i++;
index++;
}
else {
out[index] = arr_right[j];
j++;
index++;
}
}
//only one of these two loops will run
while (i < length_left)
{
out[index] = arr_left[i];
index++;
i++;
}
while (j < length_right)
{
out[index] = arr_right[j];
index++;
j++;
}
} | .file "tmpxft_001514d5_00000000-6_merge_func.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14mergeArraysAscPfS_iiS_i
.type _Z14mergeArraysAscPfS_iiS_i, @function
_Z14mergeArraysAscPfS_iiS_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z14mergeArraysAscPfS_iiS_i, .-_Z14mergeArraysAscPfS_iiS_i
.globl _Z30__device_stub__Z9MergeRankPfS_PfS_
.type _Z30__device_stub__Z9MergeRankPfS_PfS_, @function
_Z30__device_stub__Z9MergeRankPfS_PfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9MergeRankPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z30__device_stub__Z9MergeRankPfS_PfS_, .-_Z30__device_stub__Z9MergeRankPfS_PfS_
.globl _Z9MergeRankPfS_
.type _Z9MergeRankPfS_, @function
_Z9MergeRankPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9MergeRankPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9MergeRankPfS_, .-_Z9MergeRankPfS_
.globl _Z36__device_stub__Z13mergingKernelPfiS_PfiS_
.type _Z36__device_stub__Z13mergingKernelPfiS_PfiS_, @function
_Z36__device_stub__Z13mergingKernelPfiS_PfiS_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13mergingKernelPfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z36__device_stub__Z13mergingKernelPfiS_PfiS_, .-_Z36__device_stub__Z13mergingKernelPfiS_PfiS_
.globl _Z13mergingKernelPfiS_
.type _Z13mergingKernelPfiS_, @function
_Z13mergingKernelPfiS_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13mergingKernelPfiS_PfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z13mergingKernelPfiS_, .-_Z13mergingKernelPfiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "--------------------------start log--------------------------------"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of steps\t"
.section .rodata.str1.8
.align 8
.LC2:
.string "-------------------------------------------------------------------"
.section .rodata.str1.1
.LC3:
.string "Merging step #"
.LC4:
.string "Number of blocks\t"
.LC5:
.string "Number of threads\t"
.LC6:
.string "\t"
.section .rodata.str1.8
.align 8
.LC7:
.string "----------------------------end log--------------------------------"
.text
.globl _Z17orderBitonicArrayPfiiS_b
.type _Z17orderBitonicArrayPfiiS_b, @function
_Z17orderBitonicArrayPfiiS_b:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %rbp
movl %esi, %ebx
movl %edx, %r15d
movq %rcx, 16(%rsp)
movl %r8d, %r12d
movb %r8b, 7(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %esi, 36(%rsp)
movl %esi, %eax
cltd
idivl %r15d
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
call log2@PLT
cvttsd2sil %xmm0, %ecx
movl %ecx, 32(%rsp)
leal (%r15,%r15), %ecx
movl %ebx, %eax
cltd
idivl %ecx
movl %eax, %ebx
leal 1022(%rax), %edx
subl $1, %eax
cmovns %eax, %edx
sarl $10, %edx
leal 1(%rdx), %eax
movl %eax, (%rsp)
testb %r12b, %r12b
jne .L75
.L22:
movq %rbp, 56(%rsp)
cmpl $0, 32(%rsp)
jle .L21
movslq 36(%rsp), %rdx
leaq 0(,%rdx,4), %rax
movq %rax, 8(%rsp)
movl $0, %r13d
leaq _ZSt4cout(%rip), %r12
movq %rdx, 40(%rsp)
jmp .L68
.L75:
movl $67, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r12
testq %r12, %r12
je .L76
cmpb $0, 56(%r12)
je .L25
movzbl 67(%r12), %esi
.L26:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $16, %edx
leaq .LC1(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 32(%rsp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L77
cmpb $0, 56(%r13)
je .L29
movzbl 67(%r13), %esi
.L30:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L22
.L76:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L78
call _ZSt16__throw_bad_castv@PLT
.L78:
call __stack_chk_fail@PLT
.L25:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L77:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L79
call _ZSt16__throw_bad_castv@PLT
.L79:
call __stack_chk_fail@PLT
.L29:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L30
.L89:
movl $67, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L80
cmpb $0, 56(%rbp)
je .L35
movzbl 67(%rbp), %esi
.L36:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $14, %edx
leaq .LC3(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L81
cmpb $0, 56(%r14)
je .L39
movzbl 67(%r14), %esi
.L40:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $17, %edx
leaq .LC4(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L82
cmpb $0, 56(%r14)
je .L43
movzbl 67(%r14), %esi
.L44:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $18, %edx
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L83
cmpb $0, 56(%r14)
je .L47
movzbl 67(%r14), %esi
.L48:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L32
.L80:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L84
call _ZSt16__throw_bad_castv@PLT
.L84:
call __stack_chk_fail@PLT
.L35:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L81:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L85
call _ZSt16__throw_bad_castv@PLT
.L85:
call __stack_chk_fail@PLT
.L39:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L40
.L82:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L86
call _ZSt16__throw_bad_castv@PLT
.L86:
call __stack_chk_fail@PLT
.L43:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L44
.L83:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L87
call _ZSt16__throw_bad_castv@PLT
.L87:
call __stack_chk_fail@PLT
.L47:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L48
.L49:
addl %r15d, %r15d
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
movl %eax, %ebx
leal 1022(%rax), %edx
subl $1, %eax
cmovs %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, (%rsp)
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq 56(%rsp), %rdi
movq 8(%rsp), %r14
movq %r14, %rsi
call cudaMalloc@PLT
movl $3, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
cmpb $0, 7(%rsp)
jne .L88
.L50:
addl $1, %r13d
cmpl %r13d, 32(%rsp)
je .L21
.L68:
cmpb $0, 7(%rsp)
jne .L89
.L32:
movl %ebx, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl (%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L49
movq 16(%rsp), %rdx
movl %r15d, %esi
movq 56(%rsp), %rdi
call _Z36__device_stub__Z13mergingKernelPfiS_PfiS_
jmp .L49
.L88:
movabsq $2305843009213693950, %rax
movq 40(%rsp), %rcx
cmpq %rcx, %rax
jb .L51
movq 8(%rsp), %r14
movq %r14, %rdi
call _Znam@PLT
movq %rax, 24(%rsp)
movl $2, %ecx
movq %r14, 8(%rsp)
movq %r14, %rdx
movq 16(%rsp), %rsi
movq %rax, %r14
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r14, %rbp
movq 8(%rsp), %rcx
leaq (%rcx,%r14), %r14
cmpl $0, 36(%rsp)
jle .L53
.L55:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC6(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbp
cmpq %r14, %rbp
jne .L55
.L53:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L90
cmpb $0, 56(%rbp)
je .L58
movzbl 67(%rbp), %esi
.L59:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L91
cmpb $0, 56(%rbp)
je .L62
movzbl 67(%rbp), %esi
.L63:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 24(%rsp), %rdi
call _ZdaPv@PLT
movl 32(%rsp), %eax
subl $1, %eax
cmpl %r13d, %eax
jne .L50
movl $67, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L92
cmpb $0, 56(%rbp)
je .L66
movzbl 67(%rbp), %eax
.L67:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L50
.L51:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
call __cxa_throw_bad_array_new_length@PLT
.L90:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L93
call _ZSt16__throw_bad_castv@PLT
.L93:
call __stack_chk_fail@PLT
.L58:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L59
.L91:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L94
call _ZSt16__throw_bad_castv@PLT
.L94:
call __stack_chk_fail@PLT
.L62:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L63
.L92:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L95
call _ZSt16__throw_bad_castv@PLT
.L95:
call __stack_chk_fail@PLT
.L66:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L67
.L21:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L96
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z17orderBitonicArrayPfiiS_b, .-_Z17orderBitonicArrayPfiiS_b
.section .rodata.str1.1
.LC8:
.string "_Z13mergingKernelPfiS_"
.LC9:
.string "_Z9MergeRankPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mergingKernelPfiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9MergeRankPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
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