system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "merge_func.cuh"
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
__global__ void MergeRank(float * d_input, float * d_output)
{
int indexA = blockIdx.x * blockDim.x + threadIdx.x;
int indexB = indexA + 2048;
float temp1 = d_input[indexA];
float temp2 = d_input[indexB];
int indexAB = 2048;
while (d_input[indexAB] < temp1) {
indexAB++;
}
int indexBA = 0;
while (d_input[indexBA] < temp2) {
indexBA++;
}
__syncthreads();
d_output[indexA + indexAB + 1] = temp1;
d_output[indexB + indexBA + 1] = temp2;
}
void orderBitonicArray(float* d_in, int size, int part_size, float* d_out, bool log)
{
/**
* \brief Order output array of the bitonic sort function
* \param d_in - a partially sorted array, global memory, gpu
* \param size - the size of the input array
* \param part_size - the size of a sorted subarray
* \param d_out - a pointer to the output array, global memory, gpu, where
* function execution result will be stored
* \param log - show information about performance during each step
* \return
* void
*/
int iter_number = static_cast<int>(log2(size / part_size));
int init_num_threads = size / (2 * part_size);
int init_num_blocks = ((init_num_threads - 1) / 1024) + 1;
if (log)
{
std::cout << "--------------------------start log--------------------------------" << std::endl;
std::cout << "Number of steps\t" << iter_number << std::endl;
}
float* t_d_in = d_in;
for (int i = 0; i < iter_number; i++)
{
if (log)
{
std::cout << "-------------------------------------------------------------------" << std::endl;
std::cout << "Merging step #" << i << std::endl;
std::cout << "Number of blocks\t" << init_num_threads << std::endl;
std::cout << "Number of threads\t" << init_num_threads << std::endl;
}
mergingKernel << <init_num_blocks, init_num_threads >> >(t_d_in, part_size, d_out);
part_size *= 2;
init_num_threads = init_num_threads / 2;
init_num_blocks = ((init_num_threads - 1) / 1024) + 1;
cudaFree(t_d_in);
cudaMalloc((void **)&t_d_in, size * sizeof(int));
cudaMemcpy(t_d_in, d_out, size * sizeof(int), cudaMemcpyDeviceToDevice);
if (log)
{
float *out = new float[size];
cudaMemcpy(out, d_out, size * sizeof(int), cudaMemcpyDeviceToHost);
for (int i = 0; i < size; i++) {
std::cout << out[i] << "\t";
}
std::cout << std::endl;
std::cout << std::endl;
delete[] out;
if (i == iter_number - 1)
{
std::cout << "----------------------------end log--------------------------------" << std::endl;
}
}
}
}
__global__ void mergingKernel(float* in_array, int part_size, float* out_array)
{
/**
* \brief kernel function for merging of the arrays of the partially sorted array
* \param in_array - the input array
* \param part_size - the size of a sorted subarray
* \param out_array - a pointer to the output array,
* where result of merging will be stored
* \return
* void
*/
int index = blockDim.x * blockIdx.x + threadIdx.x;
float* arr_left = in_array + 2 * part_size * index;
float* arr_right = arr_left + part_size;
int out_shift = 2 * part_size * index;
mergeArraysAsc(arr_left, arr_right, part_size, part_size, out_array, out_shift);
__syncthreads();
}
__device__ void mergeArraysAsc(float* arr_left, float* arr_right, int length_left, int length_right, float* out, int out_shift)
{
/**
* \brief Helper function for the mergingKernel function, merges subarrays
* \param arr_left - the first sorted array
* \param arr_right - the second sorted array
* \param length_left - size of the first array
* \param length_right - size of the second array
* \param out - a pointer to the output array, where result will be stored
* \param out_shift - shift, from which to start writing in output array.
* \return
* void
*/
int totalLength = length_left + length_right;
//running indices
int i = 0;
int j = 0;
int index = out_shift;
while (i < length_left && j < length_right)
{
if (arr_left[i] <= arr_right[j])
{
out[index] = arr_left[i];
i++;
index++;
}
else {
out[index] = arr_right[j];
j++;
index++;
}
}
//only one of these two loops will run
while (i < length_left)
{
out[index] = arr_left[i];
index++;
i++;
}
while (j < length_right)
{
out[index] = arr_right[j];
index++;
j++;
}
} | #include "hip/hip_runtime.h"
#include <iostream>
__global__ void MergeRank(float * d_input, float * d_output);
void orderBitonicArray(float* d_in, int size, int part_size, float* d_out, bool log=false);
__global__ void mergingKernel(float* in_array, int part_size, float* out_array);
__device__ void mergeArraysAsc(float* arr_left, float* arr_right, int length_left, int length_right, float* out, int out_shift); |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <iostream>
__global__ void MergeRank(float * d_input, float * d_output);
void orderBitonicArray(float* d_in, int size, int part_size, float* d_out, bool log=false);
__global__ void mergingKernel(float* in_array, int part_size, float* out_array);
__device__ void mergeArraysAsc(float* arr_left, float* arr_right, int length_left, int length_right, float* out, int out_shift); | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <iostream>
__global__ void MergeRank(float * d_input, float * d_output);
void orderBitonicArray(float* d_in, int size, int part_size, float* d_out, bool log=false);
__global__ void mergingKernel(float* in_array, int part_size, float* out_array);
__device__ void mergeArraysAsc(float* arr_left, float* arr_right, int length_left, int length_right, float* out, int out_shift); | .text
.file "merge_func.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001514d5_00000000-6_merge_func.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3673:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3673:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14mergeArraysAscPfS_iiS_i
.type _Z14mergeArraysAscPfS_iiS_i, @function
_Z14mergeArraysAscPfS_iiS_i:
.LFB3670:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE3670:
.size _Z14mergeArraysAscPfS_iiS_i, .-_Z14mergeArraysAscPfS_iiS_i
.globl _Z30__device_stub__Z9MergeRankPfS_PfS_
.type _Z30__device_stub__Z9MergeRankPfS_PfS_, @function
_Z30__device_stub__Z9MergeRankPfS_PfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9MergeRankPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z30__device_stub__Z9MergeRankPfS_PfS_, .-_Z30__device_stub__Z9MergeRankPfS_PfS_
.globl _Z9MergeRankPfS_
.type _Z9MergeRankPfS_, @function
_Z9MergeRankPfS_:
.LFB3696:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9MergeRankPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z9MergeRankPfS_, .-_Z9MergeRankPfS_
.globl _Z36__device_stub__Z13mergingKernelPfiS_PfiS_
.type _Z36__device_stub__Z13mergingKernelPfiS_PfiS_, @function
_Z36__device_stub__Z13mergingKernelPfiS_PfiS_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13mergingKernelPfiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z36__device_stub__Z13mergingKernelPfiS_PfiS_, .-_Z36__device_stub__Z13mergingKernelPfiS_PfiS_
.globl _Z13mergingKernelPfiS_
.type _Z13mergingKernelPfiS_, @function
_Z13mergingKernelPfiS_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13mergingKernelPfiS_PfiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z13mergingKernelPfiS_, .-_Z13mergingKernelPfiS_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "--------------------------start log--------------------------------"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Number of steps\t"
.section .rodata.str1.8
.align 8
.LC2:
.string "-------------------------------------------------------------------"
.section .rodata.str1.1
.LC3:
.string "Merging step #"
.LC4:
.string "Number of blocks\t"
.LC5:
.string "Number of threads\t"
.LC6:
.string "\t"
.section .rodata.str1.8
.align 8
.LC7:
.string "----------------------------end log--------------------------------"
.text
.globl _Z17orderBitonicArrayPfiiS_b
.type _Z17orderBitonicArrayPfiiS_b, @function
_Z17orderBitonicArrayPfiiS_b:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, %rbp
movl %esi, %ebx
movl %edx, %r15d
movq %rcx, 16(%rsp)
movl %r8d, %r12d
movb %r8b, 7(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl %esi, 36(%rsp)
movl %esi, %eax
cltd
idivl %r15d
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
call log2@PLT
cvttsd2sil %xmm0, %ecx
movl %ecx, 32(%rsp)
leal (%r15,%r15), %ecx
movl %ebx, %eax
cltd
idivl %ecx
movl %eax, %ebx
leal 1022(%rax), %edx
subl $1, %eax
cmovns %eax, %edx
sarl $10, %edx
leal 1(%rdx), %eax
movl %eax, (%rsp)
testb %r12b, %r12b
jne .L75
.L22:
movq %rbp, 56(%rsp)
cmpl $0, 32(%rsp)
jle .L21
movslq 36(%rsp), %rdx
leaq 0(,%rdx,4), %rax
movq %rax, 8(%rsp)
movl $0, %r13d
leaq _ZSt4cout(%rip), %r12
movq %rdx, 40(%rsp)
jmp .L68
.L75:
movl $67, %edx
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r12
testq %r12, %r12
je .L76
cmpb $0, 56(%r12)
je .L25
movzbl 67(%r12), %esi
.L26:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $16, %edx
leaq .LC1(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl 32(%rsp), %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .L77
cmpb $0, 56(%r13)
je .L29
movzbl 67(%r13), %esi
.L30:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L22
.L76:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L78
call _ZSt16__throw_bad_castv@PLT
.L78:
call __stack_chk_fail@PLT
.L25:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L26
.L77:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L79
call _ZSt16__throw_bad_castv@PLT
.L79:
call __stack_chk_fail@PLT
.L29:
movq %r13, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%r13), %rax
movl $10, %esi
movq %r13, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L30
.L89:
movl $67, %edx
leaq .LC2(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L80
cmpb $0, 56(%rbp)
je .L35
movzbl 67(%rbp), %esi
.L36:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $14, %edx
leaq .LC3(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %r13d, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L81
cmpb $0, 56(%r14)
je .L39
movzbl 67(%r14), %esi
.L40:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $17, %edx
leaq .LC4(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L82
cmpb $0, 56(%r14)
je .L43
movzbl 67(%r14), %esi
.L44:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $18, %edx
leaq .LC5(%rip), %rsi
movq %r12, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movl %ebx, %esi
movq %r12, %rdi
call _ZNSolsEi@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r14
testq %r14, %r14
je .L83
cmpb $0, 56(%r14)
je .L47
movzbl 67(%r14), %esi
.L48:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L32
.L80:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L84
call _ZSt16__throw_bad_castv@PLT
.L84:
call __stack_chk_fail@PLT
.L35:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L36
.L81:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L85
call _ZSt16__throw_bad_castv@PLT
.L85:
call __stack_chk_fail@PLT
.L39:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L40
.L82:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L86
call _ZSt16__throw_bad_castv@PLT
.L86:
call __stack_chk_fail@PLT
.L43:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L44
.L83:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L87
call _ZSt16__throw_bad_castv@PLT
.L87:
call __stack_chk_fail@PLT
.L47:
movq %r14, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r14), %rax
movl $10, %esi
movq %r14, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L48
.L49:
addl %r15d, %r15d
movl %ebx, %eax
shrl $31, %eax
addl %ebx, %eax
sarl %eax
movl %eax, %ebx
leal 1022(%rax), %edx
subl $1, %eax
cmovs %edx, %eax
sarl $10, %eax
addl $1, %eax
movl %eax, (%rsp)
movq 56(%rsp), %rdi
call cudaFree@PLT
leaq 56(%rsp), %rdi
movq 8(%rsp), %r14
movq %r14, %rsi
call cudaMalloc@PLT
movl $3, %ecx
movq %r14, %rdx
movq 16(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
cmpb $0, 7(%rsp)
jne .L88
.L50:
addl $1, %r13d
cmpl %r13d, 32(%rsp)
je .L21
.L68:
cmpb $0, 7(%rsp)
jne .L89
.L32:
movl %ebx, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl (%rsp), %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L49
movq 16(%rsp), %rdx
movl %r15d, %esi
movq 56(%rsp), %rdi
call _Z36__device_stub__Z13mergingKernelPfiS_PfiS_
jmp .L49
.L88:
movabsq $2305843009213693950, %rax
movq 40(%rsp), %rcx
cmpq %rcx, %rax
jb .L51
movq 8(%rsp), %r14
movq %r14, %rdi
call _Znam@PLT
movq %rax, 24(%rsp)
movl $2, %ecx
movq %r14, 8(%rsp)
movq %r14, %rdx
movq 16(%rsp), %rsi
movq %rax, %r14
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r14, %rbp
movq 8(%rsp), %rcx
leaq (%rcx,%r14), %r14
cmpl $0, 36(%rsp)
jle .L53
.L55:
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
leaq .LC6(%rip), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbp
cmpq %r14, %rbp
jne .L55
.L53:
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L90
cmpb $0, 56(%rbp)
je .L58
movzbl 67(%rbp), %esi
.L59:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbp
testq %rbp, %rbp
je .L91
cmpb $0, 56(%rbp)
je .L62
movzbl 67(%rbp), %esi
.L63:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 24(%rsp), %rdi
call _ZdaPv@PLT
movl 32(%rsp), %eax
subl $1, %eax
cmpl %r13d, %eax
jne .L50
movl $67, %edx
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %rbp
testq %rbp, %rbp
je .L92
cmpb $0, 56(%rbp)
je .L66
movzbl 67(%rbp), %eax
.L67:
movsbl %al, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
jmp .L50
.L51:
movq 88(%rsp), %rax
subq %fs:40, %rax
je .L54
call __stack_chk_fail@PLT
.L54:
call __cxa_throw_bad_array_new_length@PLT
.L90:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L93
call _ZSt16__throw_bad_castv@PLT
.L93:
call __stack_chk_fail@PLT
.L58:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L59
.L91:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L94
call _ZSt16__throw_bad_castv@PLT
.L94:
call __stack_chk_fail@PLT
.L62:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L63
.L92:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L95
call _ZSt16__throw_bad_castv@PLT
.L95:
call __stack_chk_fail@PLT
.L66:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
jmp .L67
.L21:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L96
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L96:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size _Z17orderBitonicArrayPfiiS_b, .-_Z17orderBitonicArrayPfiiS_b
.section .rodata.str1.1
.LC8:
.string "_Z13mergingKernelPfiS_"
.LC9:
.string "_Z9MergeRankPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z13mergingKernelPfiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z9MergeRankPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "merge_func.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
__global__ void mem_trs_test(int* input)
{
int grid = blockIdx.x * blockDim.x + threadIdx.x;
printf("tid : %d, gid : %d, value : %d \n", threadIdx.x, grid, input[grid]);
}
int main(void)
{
int size = 128;
int byte_size = size * sizeof(int);
int* h_input = (int*)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for ( int i = 0;i < size;i++ ) {
h_input[i] = (int)(rand() & 0xff);
}
int* d_input;
cudaMalloc((void**)&d_input, byte_size);
cudaMemcpy(d_input, h_input, byte_size, cudaMemcpyHostToDevice);
dim3 block(64);
dim3 grid(2);
mem_trs_test<<<grid, block>>>(d_input);
cudaDeviceSynchronize();
cudaFree(d_input);
free(h_input);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z12mem_trs_testPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_CTAID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R10, SR_TID.X ; /* 0x00000000000a7919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R11, R11, c[0x0][0x0], R10 ; /* 0x000000000b0b7a24 */
/* 0x001fc800078e020a */
/*0070*/ IMAD.WIDE R2, R11, R2, c[0x0][0x160] ; /* 0x000058000b027625 */
/* 0x000fcc00078e0202 */
/*0080*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0090*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f1e0ff */
/*00c0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e20000100a00 */
/*00d0*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*00e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0100*/ STL [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0041e80000100800 */
/*0110*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fc60000000000 */
/*0120*/ MOV R11, 0x190 ; /* 0x00000190000b7802 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R20, 0x110 ; /* 0x0000011000147802 */
/* 0x000fc40000000f00 */
/*0140*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0160*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0170*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0180*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
__global__ void mem_trs_test(int* input)
{
int grid = blockIdx.x * blockDim.x + threadIdx.x;
printf("tid : %d, gid : %d, value : %d \n", threadIdx.x, grid, input[grid]);
}
int main(void)
{
int size = 128;
int byte_size = size * sizeof(int);
int* h_input = (int*)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for ( int i = 0;i < size;i++ ) {
h_input[i] = (int)(rand() & 0xff);
}
int* d_input;
cudaMalloc((void**)&d_input, byte_size);
cudaMemcpy(d_input, h_input, byte_size, cudaMemcpyHostToDevice);
dim3 block(64);
dim3 grid(2);
mem_trs_test<<<grid, block>>>(d_input);
cudaDeviceSynchronize();
cudaFree(d_input);
free(h_input);
cudaDeviceReset();
return 0;
} | .file "tmpxft_0008a2a3_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z12mem_trs_testPiPi
.type _Z32__device_stub__Z12mem_trs_testPiPi, @function
_Z32__device_stub__Z12mem_trs_testPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12mem_trs_testPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z12mem_trs_testPiPi, .-_Z32__device_stub__Z12mem_trs_testPiPi
.globl _Z12mem_trs_testPi
.type _Z12mem_trs_testPi, @function
_Z12mem_trs_testPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12mem_trs_testPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12mem_trs_testPi, .-_Z12mem_trs_testPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 512(%r12), %rbp
.L12:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $512, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 16(%rsp)
movl $1, 20(%rsp)
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z32__device_stub__Z12mem_trs_testPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mem_trs_testPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mem_trs_testPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
__global__ void mem_trs_test(int* input)
{
int grid = blockIdx.x * blockDim.x + threadIdx.x;
printf("tid : %d, gid : %d, value : %d \n", threadIdx.x, grid, input[grid]);
}
int main(void)
{
int size = 128;
int byte_size = size * sizeof(int);
int* h_input = (int*)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for ( int i = 0;i < size;i++ ) {
h_input[i] = (int)(rand() & 0xff);
}
int* d_input;
cudaMalloc((void**)&d_input, byte_size);
cudaMemcpy(d_input, h_input, byte_size, cudaMemcpyHostToDevice);
dim3 block(64);
dim3 grid(2);
mem_trs_test<<<grid, block>>>(d_input);
cudaDeviceSynchronize();
cudaFree(d_input);
free(h_input);
cudaDeviceReset();
return 0;
} | #include "hip/hip_runtime.h"
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
__global__ void mem_trs_test(int* input)
{
int grid = blockIdx.x * blockDim.x + threadIdx.x;
printf("tid : %d, gid : %d, value : %d \n", threadIdx.x, grid, input[grid]);
}
int main(void)
{
int size = 128;
int byte_size = size * sizeof(int);
int* h_input = (int*)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for ( int i = 0;i < size;i++ ) {
h_input[i] = (int)(rand() & 0xff);
}
int* d_input;
hipMalloc((void**)&d_input, byte_size);
hipMemcpy(d_input, h_input, byte_size, hipMemcpyHostToDevice);
dim3 block(64);
dim3 grid(2);
mem_trs_test<<<grid, block>>>(d_input);
hipDeviceSynchronize();
hipFree(d_input);
free(h_input);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <cstdio>
#include <cstdlib>
#include <cstring>
#include <ctime>
__global__ void mem_trs_test(int* input)
{
int grid = blockIdx.x * blockDim.x + threadIdx.x;
printf("tid : %d, gid : %d, value : %d \n", threadIdx.x, grid, input[grid]);
}
int main(void)
{
int size = 128;
int byte_size = size * sizeof(int);
int* h_input = (int*)malloc(byte_size);
time_t t;
srand((unsigned)time(&t));
for ( int i = 0;i < size;i++ ) {
h_input[i] = (int)(rand() & 0xff);
}
int* d_input;
hipMalloc((void**)&d_input, byte_size);
hipMemcpy(d_input, h_input, byte_size, hipMemcpyHostToDevice);
dim3 block(64);
dim3 grid(2);
mem_trs_test<<<grid, block>>>(d_input);
hipDeviceSynchronize();
hipFree(d_input);
free(h_input);
hipDeviceReset();
return 0;
} | .text
.file "main.hip"
.globl _Z27__device_stub__mem_trs_testPi # -- Begin function _Z27__device_stub__mem_trs_testPi
.p2align 4, 0x90
.type _Z27__device_stub__mem_trs_testPi,@function
_Z27__device_stub__mem_trs_testPi: # @_Z27__device_stub__mem_trs_testPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z12mem_trs_testPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z27__device_stub__mem_trs_testPi, .Lfunc_end0-_Z27__device_stub__mem_trs_testPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
leaq 80(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $128, %r14
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 8(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 62(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12mem_trs_testPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mem_trs_testPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mem_trs_testPi,@object # @_Z12mem_trs_testPi
.section .rodata,"a",@progbits
.globl _Z12mem_trs_testPi
.p2align 3, 0x0
_Z12mem_trs_testPi:
.quad _Z27__device_stub__mem_trs_testPi
.size _Z12mem_trs_testPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mem_trs_testPi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mem_trs_testPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mem_trs_testPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008a2a3_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z12mem_trs_testPiPi
.type _Z32__device_stub__Z12mem_trs_testPiPi, @function
_Z32__device_stub__Z12mem_trs_testPiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z12mem_trs_testPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z12mem_trs_testPiPi, .-_Z32__device_stub__Z12mem_trs_testPiPi
.globl _Z12mem_trs_testPi
.type _Z12mem_trs_testPi, @function
_Z12mem_trs_testPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z12mem_trs_testPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z12mem_trs_testPi, .-_Z12mem_trs_testPi
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $512, %edi
call malloc@PLT
movq %rax, %r12
movq %rsp, %rdi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r12, %rbx
leaq 512(%r12), %rbp
.L12:
call rand@PLT
movzbl %al, %eax
movl %eax, (%rbx)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L12
leaq 8(%rsp), %rdi
movl $512, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $512, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 16(%rsp)
movl $1, 20(%rsp)
movl $2, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaDeviceSynchronize@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movq 8(%rsp), %rdi
call _Z32__device_stub__Z12mem_trs_testPiPi
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12mem_trs_testPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12mem_trs_testPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z27__device_stub__mem_trs_testPi # -- Begin function _Z27__device_stub__mem_trs_testPi
.p2align 4, 0x90
.type _Z27__device_stub__mem_trs_testPi,@function
_Z27__device_stub__mem_trs_testPi: # @_Z27__device_stub__mem_trs_testPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z12mem_trs_testPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z27__device_stub__mem_trs_testPi, .Lfunc_end0-_Z27__device_stub__mem_trs_testPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $88, %rsp
.cfi_def_cfa_offset 112
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $512, %edi # imm = 0x200
callq malloc
movq %rax, %rbx
leaq 80(%rsp), %rdi
callq time
movl %eax, %edi
callq srand
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movzbl %al, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
cmpq $128, %r14
jne .LBB1_1
# %bb.2:
leaq 8(%rsp), %rdi
movl $512, %esi # imm = 0x200
callq hipMalloc
movq 8(%rsp), %rdi
movl $512, %edx # imm = 0x200
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 62(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z12mem_trs_testPi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
callq hipDeviceReset
xorl %eax, %eax
addq $88, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12mem_trs_testPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12mem_trs_testPi,@object # @_Z12mem_trs_testPi
.section .rodata,"a",@progbits
.globl _Z12mem_trs_testPi
.p2align 3, 0x0
_Z12mem_trs_testPi:
.quad _Z27__device_stub__mem_trs_testPi
.size _Z12mem_trs_testPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12mem_trs_testPi"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__mem_trs_testPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12mem_trs_testPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
/*#define M(row, col) *(M.elements + (row) (*) M.width + col)*/
typedef struct {
int width;
int height;
float* elements;
} Matrix;
//a h w B h w C
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[i * C.width + j] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[i * C.width + j] +=
A.elements[i * A.width + k]
* B.elements[k * B.width + j];
}
}
}
}
void fill_Matrix(Matrix A)
{
for (int i = 0; i < A.height ; i++) {
for (int j = 0; j < A.width; j++) {
A.elements[i * A.width + j] = rand() / (float)RAND_MAX * 10;
}
}
}
void print_Matrix(Matrix A)
{
/*for (int i = 0; i < A.height; i++) {*/
/*for (int j = 0; j < A.width; j++) {*/
/*printf("%4.1f ", A.elements[i * A.width + j]);*/
/*}*/
/*printf("\n");*/
/*}*/
}
int main(int argc, char **argv)
{
if (argc != 2) {
printf("usage: n\n");
return -1;
}
int nnn = atoi(argv[1]);
int n = 1 << nnn;
srand(time(0));
Matrix A, B, C;
A.width = A.height = n;
A.elements = (float *)malloc(sizeof(float) * n * n);
B.width = B.height = n;
B.elements = (float *)malloc(sizeof(float) * n * n);
C.width = C.height = n;
C.elements = (float *)malloc(sizeof(float) * n * n);
fill_Matrix(A);
print_Matrix(A);
printf("\n");
fill_Matrix(B);
print_Matrix(B);
printf("\n");
MatMul(A, B, C);
print_Matrix(C);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
/*#define M(row, col) *(M.elements + (row) (*) M.width + col)*/
typedef struct {
int width;
int height;
float* elements;
} Matrix;
//a h w B h w C
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[i * C.width + j] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[i * C.width + j] +=
A.elements[i * A.width + k]
* B.elements[k * B.width + j];
}
}
}
}
void fill_Matrix(Matrix A)
{
for (int i = 0; i < A.height ; i++) {
for (int j = 0; j < A.width; j++) {
A.elements[i * A.width + j] = rand() / (float)RAND_MAX * 10;
}
}
}
void print_Matrix(Matrix A)
{
/*for (int i = 0; i < A.height; i++) {*/
/*for (int j = 0; j < A.width; j++) {*/
/*printf("%4.1f ", A.elements[i * A.width + j]);*/
/*}*/
/*printf("\n");*/
/*}*/
}
int main(int argc, char **argv)
{
if (argc != 2) {
printf("usage: n\n");
return -1;
}
int nnn = atoi(argv[1]);
int n = 1 << nnn;
srand(time(0));
Matrix A, B, C;
A.width = A.height = n;
A.elements = (float *)malloc(sizeof(float) * n * n);
B.width = B.height = n;
B.elements = (float *)malloc(sizeof(float) * n * n);
C.width = C.height = n;
C.elements = (float *)malloc(sizeof(float) * n * n);
fill_Matrix(A);
print_Matrix(A);
printf("\n");
fill_Matrix(B);
print_Matrix(B);
printf("\n");
MatMul(A, B, C);
print_Matrix(C);
} | .file "tmpxft_00168800_00000000-6_mat_c.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rcx, -24(%rsp)
movq %r9, -16(%rsp)
movq %rdi, %rcx
sarq $32, %rcx
testl %ecx, %ecx
jle .L3
movq %rsi, %rbp
movq %rdx, %rax
movl %ecx, %r14d
movl %edi, %ebx
movl %edx, %r11d
movl %edi, -32(%rsp)
cltq
leaq 0(,%rax,4), %rdi
movl $0, %r13d
movl $0, %ecx
movl $0, %edx
movslq %ebx, %rax
movq %rax, -8(%rsp)
movl %r14d, -28(%rsp)
movl %r8d, %esi
jmp .L5
.L9:
movslq %ecx, %rax
movq -16(%rsp), %r15
leaq (%r15,%rax,4), %r10
movq -24(%rsp), %r14
movslq %r13d, %rax
leaq 0(%rbp,%rax,4), %r15
movq -8(%rsp), %r9
addq %r9, %rax
leaq 0(%rbp,%rax,4), %r9
movl $0, %r12d
movl %edx, -36(%rsp)
.L8:
movq %r10, %r8
movl $0x00000000, (%r10)
testl %ebx, %ebx
jle .L6
movq %r14, %rdx
movq %r15, %rax
.L7:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%r8), %xmm0
movss %xmm0, (%r8)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L7
.L6:
addl $1, %r12d
addq $4, %r10
addq $4, %r14
cmpl %r12d, %r11d
jne .L8
movl -36(%rsp), %edx
.L10:
addl $1, %edx
addl %esi, %ecx
movl -32(%rsp), %eax
addl %eax, %r13d
movl -28(%rsp), %eax
cmpl %eax, %edx
je .L3
.L5:
testl %r11d, %r11d
jg .L9
jmp .L10
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.globl _Z11fill_Matrix6Matrix
.type _Z11fill_Matrix6Matrix, @function
_Z11fill_Matrix6Matrix:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rax
sarq $32, %rax
movl %eax, (%rsp)
testl %eax, %eax
jle .L14
movq %rsi, %r12
movl %edi, %r15d
movl %edi, 4(%rsp)
movl $0, %r14d
movl $0, %r13d
movslq %edi, %rax
movq %rax, 8(%rsp)
jmp .L16
.L18:
movslq %r14d, %rbp
leaq 0(,%rbp,4), %rbx
movq 8(%rsp), %rax
addq %rax, %rbp
salq $2, %rbp
.L17:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, (%rbx,%r12)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
.L19:
addl $1, %r13d
movl 4(%rsp), %eax
addl %eax, %r14d
movl (%rsp), %eax
cmpl %eax, %r13d
je .L14
.L16:
testl %r15d, %r15d
jg .L18
jmp .L19
.L14:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11fill_Matrix6Matrix, .-_Z11fill_Matrix6Matrix
.globl _Z12print_Matrix6Matrix
.type _Z12print_Matrix6Matrix, @function
_Z12print_Matrix6Matrix:
.LFB2059:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2059:
.size _Z12print_Matrix6Matrix, .-_Z12print_Matrix6Matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "usage: n\n"
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
cmpl $2, %edi
jne .L27
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $1, %ebx
movl %eax, %ecx
sall %cl, %ebx
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl %ebx, %r15d
movl %ebx, %r12d
movslq %ebx, %rbx
imulq %rbx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, (%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r15, %rbx
salq $32, %rbx
orq %rbx, %r12
movq %r12, %rdi
movq %rbp, %rsi
call _Z11fill_Matrix6Matrix
leaq .LC4(%rip), %r15
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
movq %r13, %rsi
call _Z11fill_Matrix6Matrix
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %r8
orq %rbx, %r8
movq 8(%rsp), %r9
movq %r12, %rdx
movq %r13, %rcx
movq %r12, %rdi
movq %rbp, %rsi
call _Z6MatMul6MatrixS_S_
movl $0, %eax
.L25:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L25
.cfi_endproc
.LFE2060:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.align 4
.LC2:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <time.h>
/*#define M(row, col) *(M.elements + (row) (*) M.width + col)*/
typedef struct {
int width;
int height;
float* elements;
} Matrix;
//a h w B h w C
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[i * C.width + j] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[i * C.width + j] +=
A.elements[i * A.width + k]
* B.elements[k * B.width + j];
}
}
}
}
void fill_Matrix(Matrix A)
{
for (int i = 0; i < A.height ; i++) {
for (int j = 0; j < A.width; j++) {
A.elements[i * A.width + j] = rand() / (float)RAND_MAX * 10;
}
}
}
void print_Matrix(Matrix A)
{
/*for (int i = 0; i < A.height; i++) {*/
/*for (int j = 0; j < A.width; j++) {*/
/*printf("%4.1f ", A.elements[i * A.width + j]);*/
/*}*/
/*printf("\n");*/
/*}*/
}
int main(int argc, char **argv)
{
if (argc != 2) {
printf("usage: n\n");
return -1;
}
int nnn = atoi(argv[1]);
int n = 1 << nnn;
srand(time(0));
Matrix A, B, C;
A.width = A.height = n;
A.elements = (float *)malloc(sizeof(float) * n * n);
B.width = B.height = n;
B.elements = (float *)malloc(sizeof(float) * n * n);
C.width = C.height = n;
C.elements = (float *)malloc(sizeof(float) * n * n);
fill_Matrix(A);
print_Matrix(A);
printf("\n");
fill_Matrix(B);
print_Matrix(B);
printf("\n");
MatMul(A, B, C);
print_Matrix(C);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
/*#define M(row, col) *(M.elements + (row) (*) M.width + col)*/
typedef struct {
int width;
int height;
float* elements;
} Matrix;
//a h w B h w C
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[i * C.width + j] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[i * C.width + j] +=
A.elements[i * A.width + k]
* B.elements[k * B.width + j];
}
}
}
}
void fill_Matrix(Matrix A)
{
for (int i = 0; i < A.height ; i++) {
for (int j = 0; j < A.width; j++) {
A.elements[i * A.width + j] = rand() / (float)RAND_MAX * 10;
}
}
}
void print_Matrix(Matrix A)
{
/*for (int i = 0; i < A.height; i++) {*/
/*for (int j = 0; j < A.width; j++) {*/
/*printf("%4.1f ", A.elements[i * A.width + j]);*/
/*}*/
/*printf("\n");*/
/*}*/
}
int main(int argc, char **argv)
{
if (argc != 2) {
printf("usage: n\n");
return -1;
}
int nnn = atoi(argv[1]);
int n = 1 << nnn;
srand(time(0));
Matrix A, B, C;
A.width = A.height = n;
A.elements = (float *)malloc(sizeof(float) * n * n);
B.width = B.height = n;
B.elements = (float *)malloc(sizeof(float) * n * n);
C.width = C.height = n;
C.elements = (float *)malloc(sizeof(float) * n * n);
fill_Matrix(A);
print_Matrix(A);
printf("\n");
fill_Matrix(B);
print_Matrix(B);
printf("\n");
MatMul(A, B, C);
print_Matrix(C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
/*#define M(row, col) *(M.elements + (row) (*) M.width + col)*/
typedef struct {
int width;
int height;
float* elements;
} Matrix;
//a h w B h w C
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[i * C.width + j] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[i * C.width + j] +=
A.elements[i * A.width + k]
* B.elements[k * B.width + j];
}
}
}
}
void fill_Matrix(Matrix A)
{
for (int i = 0; i < A.height ; i++) {
for (int j = 0; j < A.width; j++) {
A.elements[i * A.width + j] = rand() / (float)RAND_MAX * 10;
}
}
}
void print_Matrix(Matrix A)
{
/*for (int i = 0; i < A.height; i++) {*/
/*for (int j = 0; j < A.width; j++) {*/
/*printf("%4.1f ", A.elements[i * A.width + j]);*/
/*}*/
/*printf("\n");*/
/*}*/
}
int main(int argc, char **argv)
{
if (argc != 2) {
printf("usage: n\n");
return -1;
}
int nnn = atoi(argv[1]);
int n = 1 << nnn;
srand(time(0));
Matrix A, B, C;
A.width = A.height = n;
A.elements = (float *)malloc(sizeof(float) * n * n);
B.width = B.height = n;
B.elements = (float *)malloc(sizeof(float) * n * n);
C.width = C.height = n;
C.elements = (float *)malloc(sizeof(float) * n * n);
fill_Matrix(A);
print_Matrix(A);
printf("\n");
fill_Matrix(B);
print_Matrix(B);
printf("\n");
MatMul(A, B, C);
print_Matrix(C);
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
/*#define M(row, col) *(M.elements + (row) (*) M.width + col)*/
typedef struct {
int width;
int height;
float* elements;
} Matrix;
//a h w B h w C
void MatMul(const Matrix A, const Matrix B, Matrix C)
{
for (int i = 0; i < A.height; i++) {
for (int j = 0; j < B.width; j++) {
C.elements[i * C.width + j] = 0;
for (int k = 0; k < A.width; k++) {
C.elements[i * C.width + j] +=
A.elements[i * A.width + k]
* B.elements[k * B.width + j];
}
}
}
}
void fill_Matrix(Matrix A)
{
for (int i = 0; i < A.height ; i++) {
for (int j = 0; j < A.width; j++) {
A.elements[i * A.width + j] = rand() / (float)RAND_MAX * 10;
}
}
}
void print_Matrix(Matrix A)
{
/*for (int i = 0; i < A.height; i++) {*/
/*for (int j = 0; j < A.width; j++) {*/
/*printf("%4.1f ", A.elements[i * A.width + j]);*/
/*}*/
/*printf("\n");*/
/*}*/
}
int main(int argc, char **argv)
{
if (argc != 2) {
printf("usage: n\n");
return -1;
}
int nnn = atoi(argv[1]);
int n = 1 << nnn;
srand(time(0));
Matrix A, B, C;
A.width = A.height = n;
A.elements = (float *)malloc(sizeof(float) * n * n);
B.width = B.height = n;
B.elements = (float *)malloc(sizeof(float) * n * n);
C.width = C.height = n;
C.elements = (float *)malloc(sizeof(float) * n * n);
fill_Matrix(A);
print_Matrix(A);
printf("\n");
fill_Matrix(B);
print_Matrix(B);
printf("\n");
MatMul(A, B, C);
print_Matrix(C);
} | .text
.file "mat_c.hip"
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, -8(%rsp) # 8-byte Spill
movq %rcx, -16(%rsp) # 8-byte Spill
movq %rsi, -24(%rsp) # 8-byte Spill
movq %rdi, %rax
shrq $32, %rax
testl %eax, %eax
jle .LBB0_9
# %bb.1: # %.preheader.lr.ph
movslq %edx, %r10
movslq %r8d, %rsi
movl %r10d, %r11d
movl %edi, %ebx
shlq $2, %r10
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_8: # %._crit_edge29
# in Loop: Header=BB0_2 Depth=1
incq %r15
addl %edi, %r14d
cmpq %rax, %r15
je .LBB0_9
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_6 Depth 3
testl %edx, %edx
jle .LBB0_8
# %bb.3: # %.lr.ph28
# in Loop: Header=BB0_2 Depth=1
movl %r14d, %ecx
movq -24(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rcx,4), %r12
movq %r15, %rcx
imulq %rsi, %rcx
movq -8(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rcx,4), %r13
movq -16(%rsp), %rcx # 8-byte Reload
xorl %r8d, %r8d
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_7: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
incq %r8
addq $4, %rcx
cmpq %r11, %r8
je .LBB0_8
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_6 Depth 3
movl $0, (%r13,%r8,4)
testl %edi, %edi
jle .LBB0_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB0_4 Depth=2
movss (%r13,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rcx, %rbp
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r13,%r8,4)
incq %r9
addq %r10, %rbp
cmpq %r9, %rbx
jne .LBB0_6
jmp .LBB0_7
.LBB0_9: # %._crit_edge31
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end0-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_Matrix6Matrix
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x41200000 # float 10
.text
.globl _Z11fill_Matrix6Matrix
.p2align 4, 0x90
.type _Z11fill_Matrix6Matrix,@function
_Z11fill_Matrix6Matrix: # @_Z11fill_Matrix6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %rax
shrq $32, %rax
movq %rax, 16(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movq %rdi, %r14
movl %r14d, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbp
addl %r14d, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %r14d, %r14d
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge10
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11fill_Matrix6Matrix, .Lfunc_end1-_Z11fill_Matrix6Matrix
.cfi_endproc
# -- End function
.globl _Z12print_Matrix6Matrix # -- Begin function _Z12print_Matrix6Matrix
.p2align 4, 0x90
.type _Z12print_Matrix6Matrix,@function
_Z12print_Matrix6Matrix: # @_Z12print_Matrix6Matrix
.cfi_startproc
# %bb.0:
retq
.Lfunc_end2:
.size _Z12print_Matrix6Matrix, .Lfunc_end2-_Z12print_Matrix6Matrix
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $2, %edi
jne .LBB3_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $1, %r14d
movl %ebx, %ecx
shll %cl, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cmpl $31, %ebx
jne .LBB3_3
# %bb.12: # %_Z11fill_Matrix6Matrix.exit47.critedge
movl $10, %edi
callq putchar@PLT
jmp .LBB3_13
.LBB3_1:
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB3_14
.LBB3_3: # %.preheader.i.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movq %r14, %r12
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
decq %r12
jne .LBB3_5
# %bb.6: # %._crit_edge.i
# in Loop: Header=BB3_4 Depth=1
incq %r15
cmpq %r14, %r15
jne .LBB3_4
# %bb.7: # %_Z11fill_Matrix6Matrix.exit
movl $10, %edi
callq putchar@PLT
cmpl $31, %ebx
je .LBB3_13
# %bb.8: # %.preheader.i38.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_9: # %.preheader.i38
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
movq %r14, %r15
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
decq %r15
jne .LBB3_10
# %bb.11: # %._crit_edge.i40
# in Loop: Header=BB3_9 Depth=1
incq %rbx
cmpq %r14, %rbx
jne .LBB3_9
.LBB3_13: # %_Z6MatMul6MatrixS_S_.exit.critedge
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
.LBB3_14: # %_Z6MatMul6MatrixS_S_.exit
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: n"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00168800_00000000-6_mat_c.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rcx, -24(%rsp)
movq %r9, -16(%rsp)
movq %rdi, %rcx
sarq $32, %rcx
testl %ecx, %ecx
jle .L3
movq %rsi, %rbp
movq %rdx, %rax
movl %ecx, %r14d
movl %edi, %ebx
movl %edx, %r11d
movl %edi, -32(%rsp)
cltq
leaq 0(,%rax,4), %rdi
movl $0, %r13d
movl $0, %ecx
movl $0, %edx
movslq %ebx, %rax
movq %rax, -8(%rsp)
movl %r14d, -28(%rsp)
movl %r8d, %esi
jmp .L5
.L9:
movslq %ecx, %rax
movq -16(%rsp), %r15
leaq (%r15,%rax,4), %r10
movq -24(%rsp), %r14
movslq %r13d, %rax
leaq 0(%rbp,%rax,4), %r15
movq -8(%rsp), %r9
addq %r9, %rax
leaq 0(%rbp,%rax,4), %r9
movl $0, %r12d
movl %edx, -36(%rsp)
.L8:
movq %r10, %r8
movl $0x00000000, (%r10)
testl %ebx, %ebx
jle .L6
movq %r14, %rdx
movq %r15, %rax
.L7:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%r8), %xmm0
movss %xmm0, (%r8)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L7
.L6:
addl $1, %r12d
addq $4, %r10
addq $4, %r14
cmpl %r12d, %r11d
jne .L8
movl -36(%rsp), %edx
.L10:
addl $1, %edx
addl %esi, %ecx
movl -32(%rsp), %eax
addl %eax, %r13d
movl -28(%rsp), %eax
cmpl %eax, %edx
je .L3
.L5:
testl %r11d, %r11d
jg .L9
jmp .L10
.L3:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.globl _Z11fill_Matrix6Matrix
.type _Z11fill_Matrix6Matrix, @function
_Z11fill_Matrix6Matrix:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rax
sarq $32, %rax
movl %eax, (%rsp)
testl %eax, %eax
jle .L14
movq %rsi, %r12
movl %edi, %r15d
movl %edi, 4(%rsp)
movl $0, %r14d
movl $0, %r13d
movslq %edi, %rax
movq %rax, 8(%rsp)
jmp .L16
.L18:
movslq %r14d, %rbp
leaq 0(,%rbp,4), %rbx
movq 8(%rsp), %rax
addq %rax, %rbp
salq $2, %rbp
.L17:
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC1(%rip), %xmm0
mulss .LC2(%rip), %xmm0
movss %xmm0, (%rbx,%r12)
addq $4, %rbx
cmpq %rbp, %rbx
jne .L17
.L19:
addl $1, %r13d
movl 4(%rsp), %eax
addl %eax, %r14d
movl (%rsp), %eax
cmpl %eax, %r13d
je .L14
.L16:
testl %r15d, %r15d
jg .L18
jmp .L19
.L14:
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z11fill_Matrix6Matrix, .-_Z11fill_Matrix6Matrix
.globl _Z12print_Matrix6Matrix
.type _Z12print_Matrix6Matrix, @function
_Z12print_Matrix6Matrix:
.LFB2059:
.cfi_startproc
endbr64
ret
.cfi_endproc
.LFE2059:
.size _Z12print_Matrix6Matrix, .-_Z12print_Matrix6Matrix
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "usage: n\n"
.LC4:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
cmpl $2, %edi
jne .L27
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl $1, %ebx
movl %eax, %ecx
sall %cl, %ebx
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl %ebx, %r15d
movl %ebx, %r12d
movslq %ebx, %rbx
imulq %rbx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movq %r15, (%rsp)
movq %rbx, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %r15, %rbx
salq $32, %rbx
orq %rbx, %r12
movq %r12, %rdi
movq %rbp, %rsi
call _Z11fill_Matrix6Matrix
leaq .LC4(%rip), %r15
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
movq %r13, %rsi
call _Z11fill_Matrix6Matrix
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq (%rsp), %r8
orq %rbx, %r8
movq 8(%rsp), %r9
movq %r12, %rdx
movq %r13, %rcx
movq %r12, %rdi
movq %rbp, %rsi
call _Z6MatMul6MatrixS_S_
movl $0, %eax
.L25:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %eax
jmp .L25
.cfi_endproc
.LFE2060:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC1:
.long 805306368
.align 4
.LC2:
.long 1092616192
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_c.hip"
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, -8(%rsp) # 8-byte Spill
movq %rcx, -16(%rsp) # 8-byte Spill
movq %rsi, -24(%rsp) # 8-byte Spill
movq %rdi, %rax
shrq $32, %rax
testl %eax, %eax
jle .LBB0_9
# %bb.1: # %.preheader.lr.ph
movslq %edx, %r10
movslq %r8d, %rsi
movl %r10d, %r11d
movl %edi, %ebx
shlq $2, %r10
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_8: # %._crit_edge29
# in Loop: Header=BB0_2 Depth=1
incq %r15
addl %edi, %r14d
cmpq %rax, %r15
je .LBB0_9
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
# Child Loop BB0_6 Depth 3
testl %edx, %edx
jle .LBB0_8
# %bb.3: # %.lr.ph28
# in Loop: Header=BB0_2 Depth=1
movl %r14d, %ecx
movq -24(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rcx,4), %r12
movq %r15, %rcx
imulq %rsi, %rcx
movq -8(%rsp), %r8 # 8-byte Reload
leaq (%r8,%rcx,4), %r13
movq -16(%rsp), %rcx # 8-byte Reload
xorl %r8d, %r8d
jmp .LBB0_4
.p2align 4, 0x90
.LBB0_7: # %._crit_edge
# in Loop: Header=BB0_4 Depth=2
incq %r8
addq $4, %rcx
cmpq %r11, %r8
je .LBB0_8
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB0_6 Depth 3
movl $0, (%r13,%r8,4)
testl %edi, %edi
jle .LBB0_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB0_4 Depth=2
movss (%r13,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rcx, %rbp
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB0_6: # Parent Loop BB0_2 Depth=1
# Parent Loop BB0_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r13,%r8,4)
incq %r9
addq %r10, %rbp
cmpq %r9, %rbx
jne .LBB0_6
jmp .LBB0_7
.LBB0_9: # %._crit_edge31
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end0-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11fill_Matrix6Matrix
.LCPI1_0:
.long 0x30000000 # float 4.65661287E-10
.LCPI1_1:
.long 0x41200000 # float 10
.text
.globl _Z11fill_Matrix6Matrix
.p2align 4, 0x90
.type _Z11fill_Matrix6Matrix,@function
_Z11fill_Matrix6Matrix: # @_Z11fill_Matrix6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %rax
shrq $32, %rax
movq %rax, 16(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB1_6
# %bb.1: # %.preheader.lr.ph
movq %rdi, %r14
movl %r14d, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_5: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rbp
addl %r14d, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB1_6
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
testl %r14d, %r14d
jle .LBB1_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB1_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI1_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss %xmm1, %xmm0
movss %xmm0, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r12
jne .LBB1_4
jmp .LBB1_5
.LBB1_6: # %._crit_edge10
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11fill_Matrix6Matrix, .Lfunc_end1-_Z11fill_Matrix6Matrix
.cfi_endproc
# -- End function
.globl _Z12print_Matrix6Matrix # -- Begin function _Z12print_Matrix6Matrix
.p2align 4, 0x90
.type _Z12print_Matrix6Matrix,@function
_Z12print_Matrix6Matrix: # @_Z12print_Matrix6Matrix
.cfi_startproc
# %bb.0:
retq
.Lfunc_end2:
.size _Z12print_Matrix6Matrix, .Lfunc_end2-_Z12print_Matrix6Matrix
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
cmpl $2, %edi
jne .LBB3_1
# %bb.2:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movl $1, %r14d
movl %ebx, %ecx
shll %cl, %r14d
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
cmpl $31, %ebx
jne .LBB3_3
# %bb.12: # %_Z11fill_Matrix6Matrix.exit47.critedge
movl $10, %edi
callq putchar@PLT
jmp .LBB3_13
.LBB3_1:
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %eax
jmp .LBB3_14
.LBB3_3: # %.preheader.i.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_4: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movq %r14, %r12
.p2align 4, 0x90
.LBB3_5: # Parent Loop BB3_4 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
decq %r12
jne .LBB3_5
# %bb.6: # %._crit_edge.i
# in Loop: Header=BB3_4 Depth=1
incq %r15
cmpq %r14, %r15
jne .LBB3_4
# %bb.7: # %_Z11fill_Matrix6Matrix.exit
movl $10, %edi
callq putchar@PLT
cmpl $31, %ebx
je .LBB3_13
# %bb.8: # %.preheader.i38.preheader
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_9: # %.preheader.i38
# =>This Loop Header: Depth=1
# Child Loop BB3_10 Depth 2
movq %r14, %r15
.p2align 4, 0x90
.LBB3_10: # Parent Loop BB3_9 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
decq %r15
jne .LBB3_10
# %bb.11: # %._crit_edge.i40
# in Loop: Header=BB3_9 Depth=1
incq %rbx
cmpq %r14, %rbx
jne .LBB3_9
.LBB3_13: # %_Z6MatMul6MatrixS_S_.exit.critedge
movl $10, %edi
callq putchar@PLT
xorl %eax, %eax
.LBB3_14: # %_Z6MatMul6MatrixS_S_.exit
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: n"
.size .Lstr, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
float* elements;
} Matrix;
void print_matrix(const Matrix mat) {
for(int r=0; r<mat.height; ++r) {
for(int c=0; c<mat.width; ++c) {
printf("%.2f\t", mat.elements[mat.width * r + c]);
}
printf("\n");
}
}
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); // 16x16
// result shape, e.g. mat_C.shape is (A.height x b.width)
dim3 dimGrid((B.width + dimBlock.x -1) / dimBlock.x, (A.height + dimBlock.y -1) / dimBlock.y); // 2x2
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row >= C.height || col >= C.width) return; // this thread should not do any computing
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(int argc, char*argv[]) {
Matrix mat_A;
mat_A.height = 30;
mat_A.width = 40;
mat_A.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_A.elements[i] = 1.0;
Matrix mat_B;
mat_B.height = 40;
mat_B.width = 30;
mat_B.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_B.elements[i] = 1.0;
Matrix mat_C;
mat_C.width = 30;
mat_C.height = 30;
mat_C.elements = (float*)malloc(900 * sizeof(float));
MatMul(mat_A, mat_B, mat_C);
print_matrix(mat_C);
return 0;
} | code for sm_80
Function : _Z12MatMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x180], P0 ; /* 0x0000600003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fcc00078e0208 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R0, c[0x0][0x160], R2 ; /* 0x0000580000067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x170], R3 ; /* 0x00005c0002027a24 */
/* 0x000fce00078e0203 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R0, c[0x0][0x180], R3 ; /* 0x0000600000037a24 */
/* 0x000fc800078e0203 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
float* elements;
} Matrix;
void print_matrix(const Matrix mat) {
for(int r=0; r<mat.height; ++r) {
for(int c=0; c<mat.width; ++c) {
printf("%.2f\t", mat.elements[mat.width * r + c]);
}
printf("\n");
}
}
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); // 16x16
// result shape, e.g. mat_C.shape is (A.height x b.width)
dim3 dimGrid((B.width + dimBlock.x -1) / dimBlock.x, (A.height + dimBlock.y -1) / dimBlock.y); // 2x2
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row >= C.height || col >= C.width) return; // this thread should not do any computing
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(int argc, char*argv[]) {
Matrix mat_A;
mat_A.height = 30;
mat_A.width = 40;
mat_A.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_A.elements[i] = 1.0;
Matrix mat_B;
mat_B.height = 40;
mat_B.width = 30;
mat_B.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_B.elements[i] = 1.0;
Matrix mat_C;
mat_C.width = 30;
mat_C.height = 30;
mat_C.elements = (float*)malloc(900 * sizeof(float));
MatMul(mat_A, mat_B, mat_C);
print_matrix(mat_C);
return 0;
} | .file "tmpxft_00145207_00000000-6_mat_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.2f\t"
.LC1:
.string "\n"
.text
.globl _Z12print_matrix6Matrix
.type _Z12print_matrix6Matrix, @function
_Z12print_matrix6Matrix:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rax
sarq $32, %rax
movl %eax, 16(%rsp)
movl %edi, 12(%rsp)
testl %eax, %eax
jle .L3
movq %rsi, %r12
movl %edi, 20(%rsp)
movl $0, %r15d
movl $0, %r14d
movslq %edi, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r13
jmp .L5
.L7:
movslq %r15d, %rbp
leaq 0(,%rbp,4), %rbx
movq 24(%rsp), %rax
addq %rax, %rbp
salq $2, %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
movl 20(%rsp), %eax
addl %eax, %r15d
movl 16(%rsp), %eax
cmpl %eax, %r14d
je .L3
.L5:
cmpl $0, 12(%rsp)
jg .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12print_matrix6Matrix, .-_Z12print_matrix6Matrix
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, 16(%rsp)
movq %r8, %r15
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, %r14
sarq $32, %r14
movq %rdx, %r13
sarq $32, %r13
movq %r8, %r12
sarq $32, %r12
movl %edi, 64(%rsp)
movl %r14d, 68(%rsp)
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 80(%rsp)
movl %r13d, 84(%rsp)
imull %ebp, %r13d
movslq %r13d, %r13
salq $2, %r13
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 96(%rsp)
movl %r12d, 100(%rsp)
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
addl $15, %ebp
shrl $4, %ebp
movl %ebp, 52(%rsp)
addl $15, %r14d
shrl $4, %r14d
movl %r14d, 56(%rsp)
movl $16, 40(%rsp)
movl $16, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movq %r12, %rdx
movq 104(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movdqa 64(%rsp), %xmm0
movaps %xmm0, 112(%rsp)
movdqa 80(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 144(%rsp)
leaq 144(%rsp), %rdx
leaq 128(%rsp), %rsi
leaq 112(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $4800, %edi
call malloc@PLT
movq %rax, %rbx
leaq 4800(%rax), %rdx
movss .LC2(%rip), %xmm0
.L26:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L26
movl $4800, %edi
call malloc@PLT
movq %rax, %rbp
leaq 4800(%rax), %rdx
movss .LC2(%rip), %xmm0
.L27:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L27
movabsq $128849018910, %r13
movl $3600, %edi
call malloc@PLT
movq %rax, %r12
movq %r13, %r8
movq %rax, %r9
movabsq $171798691870, %rdx
movq %rbp, %rcx
movabsq $128849018920, %rdi
movq %rbx, %rsi
call _Z6MatMul6MatrixS_S_
movq %r13, %rdi
movq %r12, %rsi
call _Z12print_matrix6Matrix
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
float* elements;
} Matrix;
void print_matrix(const Matrix mat) {
for(int r=0; r<mat.height; ++r) {
for(int c=0; c<mat.width; ++c) {
printf("%.2f\t", mat.elements[mat.width * r + c]);
}
printf("\n");
}
}
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
cudaMalloc(&d_A.elements, size);
cudaMemcpy(d_A.elements, A.elements, size, cudaMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
cudaMalloc(&d_B.elements, size);
cudaMemcpy(d_B.elements, B.elements, size, cudaMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
cudaMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); // 16x16
// result shape, e.g. mat_C.shape is (A.height x b.width)
dim3 dimGrid((B.width + dimBlock.x -1) / dimBlock.x, (A.height + dimBlock.y -1) / dimBlock.y); // 2x2
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
cudaMemcpy(C.elements, d_C.elements, size, cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_A.elements);
cudaFree(d_B.elements);
cudaFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row >= C.height || col >= C.width) return; // this thread should not do any computing
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(int argc, char*argv[]) {
Matrix mat_A;
mat_A.height = 30;
mat_A.width = 40;
mat_A.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_A.elements[i] = 1.0;
Matrix mat_B;
mat_B.height = 40;
mat_B.width = 30;
mat_B.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_B.elements[i] = 1.0;
Matrix mat_C;
mat_C.width = 30;
mat_C.height = 30;
mat_C.elements = (float*)malloc(900 * sizeof(float));
MatMul(mat_A, mat_B, mat_C);
print_matrix(mat_C);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
float* elements;
} Matrix;
void print_matrix(const Matrix mat) {
for(int r=0; r<mat.height; ++r) {
for(int c=0; c<mat.width; ++c) {
printf("%.2f\t", mat.elements[mat.width * r + c]);
}
printf("\n");
}
}
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); // 16x16
// result shape, e.g. mat_C.shape is (A.height x b.width)
dim3 dimGrid((B.width + dimBlock.x -1) / dimBlock.x, (A.height + dimBlock.y -1) / dimBlock.y); // 2x2
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row >= C.height || col >= C.width) return; // this thread should not do any computing
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(int argc, char*argv[]) {
Matrix mat_A;
mat_A.height = 30;
mat_A.width = 40;
mat_A.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_A.elements[i] = 1.0;
Matrix mat_B;
mat_B.height = 40;
mat_B.width = 30;
mat_B.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_B.elements[i] = 1.0;
Matrix mat_C;
mat_C.width = 30;
mat_C.height = 30;
mat_C.elements = (float*)malloc(900 * sizeof(float));
MatMul(mat_A, mat_B, mat_C);
print_matrix(mat_C);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
float* elements;
} Matrix;
void print_matrix(const Matrix mat) {
for(int r=0; r<mat.height; ++r) {
for(int c=0; c<mat.width; ++c) {
printf("%.2f\t", mat.elements[mat.width * r + c]);
}
printf("\n");
}
}
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); // 16x16
// result shape, e.g. mat_C.shape is (A.height x b.width)
dim3 dimGrid((B.width + dimBlock.x -1) / dimBlock.x, (A.height + dimBlock.y -1) / dimBlock.y); // 2x2
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row >= C.height || col >= C.width) return; // this thread should not do any computing
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(int argc, char*argv[]) {
Matrix mat_A;
mat_A.height = 30;
mat_A.width = 40;
mat_A.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_A.elements[i] = 1.0;
Matrix mat_B;
mat_B.height = 40;
mat_B.width = 30;
mat_B.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_B.elements[i] = 1.0;
Matrix mat_C;
mat_C.width = 30;
mat_C.height = 30;
mat_C.elements = (float*)malloc(900 * sizeof(float));
MatMul(mat_A, mat_B, mat_C);
print_matrix(mat_C);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s6, s0, 32
s_addc_u32 s7, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s5, s[0:1], 0x0
s_load_b64 s[2:3], s[6:7], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[8:9], s[0:1], 0x8
v_mul_lo_u32 v2, v0, s5
s_clause 0x1
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s5, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
// Matrices are stored in row-major order:
// M(row, col) = *(M.elements + row * M.width + col)
typedef struct {
int width;
int height;
float* elements;
} Matrix;
void print_matrix(const Matrix mat) {
for(int r=0; r<mat.height; ++r) {
for(int c=0; c<mat.width; ++c) {
printf("%.2f\t", mat.elements[mat.width * r + c]);
}
printf("\n");
}
}
// Thread block size
#define BLOCK_SIZE 16
// Forward declaration of the matrix multiplication kernel
__global__ void MatMulKernel(const Matrix, const Matrix, Matrix);
// Matrix multiplication - Host code
// Matrix dimensions are assumed to be multiples of BLOCK_SIZE
void MatMul(const Matrix A, const Matrix B, Matrix C) {
// Load A and B to device memory
Matrix d_A;
d_A.width = A.width;
d_A.height = A.height;
size_t size = A.width * A.height * sizeof(float);
hipMalloc(&d_A.elements, size);
hipMemcpy(d_A.elements, A.elements, size, hipMemcpyHostToDevice);
Matrix d_B;
d_B.width = B.width;
d_B.height = B.height;
size = B.width * B.height * sizeof(float);
hipMalloc(&d_B.elements, size);
hipMemcpy(d_B.elements, B.elements, size, hipMemcpyHostToDevice);
// Allocate C in device memory
Matrix d_C;
d_C.width = C.width;
d_C.height = C.height;
size = C.width * C.height * sizeof(float);
hipMalloc(&d_C.elements, size);
// Invoke kernel
dim3 dimBlock(BLOCK_SIZE, BLOCK_SIZE); // 16x16
// result shape, e.g. mat_C.shape is (A.height x b.width)
dim3 dimGrid((B.width + dimBlock.x -1) / dimBlock.x, (A.height + dimBlock.y -1) / dimBlock.y); // 2x2
MatMulKernel<<<dimGrid, dimBlock>>>(d_A, d_B, d_C);
// Read C from device memory
hipMemcpy(C.elements, d_C.elements, size, hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_A.elements);
hipFree(d_B.elements);
hipFree(d_C.elements);
}
// Matrix multiplication kernel called by MatMul()
__global__ void MatMulKernel(Matrix A, Matrix B, Matrix C) {
// Each thread computes one element of C
// by accumulating results into Cvalue
float Cvalue = 0;
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row >= C.height || col >= C.width) return; // this thread should not do any computing
for (int e = 0; e < A.width; ++e)
Cvalue += A.elements[row * A.width + e] * B.elements[e * B.width + col];
C.elements[row * C.width + col] = Cvalue;
}
int main(int argc, char*argv[]) {
Matrix mat_A;
mat_A.height = 30;
mat_A.width = 40;
mat_A.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_A.elements[i] = 1.0;
Matrix mat_B;
mat_B.height = 40;
mat_B.width = 30;
mat_B.elements = (float*)malloc(1200 * sizeof(float));
for(int i=0; i<1200; ++i)mat_B.elements[i] = 1.0;
Matrix mat_C;
mat_C.width = 30;
mat_C.height = 30;
mat_C.elements = (float*)malloc(900 * sizeof(float));
MatMul(mat_A, mat_B, mat_C);
print_matrix(mat_C);
return 0;
} | .text
.file "mat_mul.hip"
.globl _Z12print_matrix6Matrix # -- Begin function _Z12print_matrix6Matrix
.p2align 4, 0x90
.type _Z12print_matrix6Matrix,@function
_Z12print_matrix6Matrix: # @_Z12print_matrix6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %rax
shrq $32, %rax
movq %rax, 16(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movq %rdi, %r14
movl %r14d, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %r14d, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %r14d, %r14d
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge10
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12print_matrix6Matrix, .Lfunc_end0-_Z12print_matrix6Matrix
.cfi_endproc
# -- End function
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 72(%rsp) # 8-byte Spill
movq %r8, %r14
movq %r8, 56(%rsp) # 8-byte Spill
movq %rcx, 64(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, %r13
movq %rdx, %r15
shrq $32, %r15
shrq $32, %r14
movq %rdi, 40(%rsp)
movq %rdi, %rbx
shrq $32, %rbx
movl %ebx, %eax
imull %edi, %eax
movslq %eax, %rbp
shlq $2, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, 24(%rsp)
imull %r12d, %r15d
movslq %r15d, %r13
shlq $2, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rax # 8-byte Reload
movq %rax, 8(%rsp)
imull %eax, %r14d
movslq %r14d, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leal 15(%r12), %eax
shrl $4, %eax
shlq $28, %rbx
orq %rax, %rbx
movl $4026531840, %eax # imm = 0xF0000000
addq %rbx, %rax
movabsq $1152921500580315135, %rdi # imm = 0xFFFFFFF0FFFFFFF
andq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movups 40(%rsp), %xmm0
movups 24(%rsp), %xmm1
movups 8(%rsp), %xmm2
movups %xmm0, 184(%rsp)
movups %xmm1, 168(%rsp)
movups %xmm2, 152(%rsp)
leaq 184(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 152(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end1-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end2-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1200, %rax # imm = 0x4B0
jne .LBB3_1
# %bb.2:
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r15,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1200, %rax # imm = 0x4B0
jne .LBB3_3
# %bb.4:
movl $3600, %edi # imm = 0xE10
callq malloc
movq %rax, %rbx
movabsq $128849018910, %r8 # imm = 0x1E0000001E
leaq 10(%r8), %rdi
movabsq $171798691870, %rdx # imm = 0x280000001E
movq %r14, %rsi
movq %r15, %rcx
movq %rax, %r9
callq _Z6MatMul6MatrixS_S_
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $30, %r15
jne .LBB3_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB3_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $120, %rbx
cmpq $30, %r14
jne .LBB3_5
# %bb.8: # %_Z12print_matrix6Matrix.exit
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f\t"
.size .L.str, 6
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12MatMulKernel6MatrixS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x184], PT ; /* 0x0000610000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R3, R2, c[0x0][0x0], R5 ; /* 0x0000000002037a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R3, c[0x0][0x180], P0 ; /* 0x0000600003007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0xc40 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R4.reuse, -0x1, RZ ; /* 0xffffffff04027810 */
/* 0x040fe40007ffe0ff */
/*0100*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe400078ec0ff */
/*0110*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0120*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fe40000000f00 */
/*0130*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fd20000000f00 */
/*0140*/ @!P0 BRA 0xb30 ; /* 0x000009e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R5, -R4, c[0x0][0x160], RZ ; /* 0x0000580004057a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R8, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff087435 */
/* 0x000fe200000001ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*0190*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD R6, R0, c[0x0][0x160], RZ ; /* 0x0000580000067a24 */
/* 0x000fe200078e02ff */
/*01b0*/ MOV R2, RZ ; /* 0x000000ff00027202 */
/* 0x000fca0000000f00 */
/*01c0*/ IMAD.WIDE R8, R3, R8, c[0x0][0x178] ; /* 0x00005e0003087625 */
/* 0x000fcc00078e0208 */
/*01d0*/ @!P0 BRA 0x990 ; /* 0x000007b000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6c0 ; /* 0x000004b000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R12, UR6 ; /* 0x00000006000c7c02 */
/* 0x000fe20008000f00 */
/*0230*/ LDG.E R21, [R8.64] ; /* 0x0000000408157981 */
/* 0x0000a2000c1e1900 */
/*0240*/ MOV R13, UR7 ; /* 0x00000007000d7c02 */
/* 0x000fca0008000f00 */
/*0250*/ IMAD.WIDE R12, R6, 0x4, R12 ; /* 0x00000004060c7825 */
/* 0x000fca00078e020c */
/*0260*/ LDG.E R20, [R12.64] ; /* 0x000000040c147981 */
/* 0x000ea2000c1e1900 */
/*0270*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*0280*/ LDG.E R14, [R12.64+0x4] ; /* 0x000004040c0e7981 */
/* 0x000ee4000c1e1900 */
/*0290*/ IMAD.WIDE R10, R7.reuse, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x040fe400078e0208 */
/*02a0*/ LDG.E R27, [R12.64+0x8] ; /* 0x000008040c1b7981 */
/* 0x000f28000c1e1900 */
/*02b0*/ LDG.E R15, [R10.64] ; /* 0x000000040a0f7981 */
/* 0x0002e2000c1e1900 */
/*02c0*/ IMAD.WIDE R22, R7, 0x4, R10 ; /* 0x0000000407167825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R18, [R12.64+0xc] ; /* 0x00000c040c127981 */
/* 0x000f66000c1e1900 */
/*02e0*/ IMAD.WIDE R28, R7.reuse, 0x4, R22 ; /* 0x00000004071c7825 */
/* 0x040fe200078e0216 */
/*02f0*/ LDG.E R26, [R22.64] ; /* 0x00000004161a7981 */
/* 0x000328000c1e1900 */
/*0300*/ LDG.E R19, [R28.64] ; /* 0x000000041c137981 */
/* 0x000362000c1e1900 */
/*0310*/ IMAD.WIDE R16, R7, 0x4, R28 ; /* 0x0000000407107825 */
/* 0x000fc600078e021c */
/*0320*/ LDG.E R8, [R12.64+0x10] ; /* 0x000010040c087981 */
/* 0x001f68000c1e1900 */
/*0330*/ LDG.E R9, [R16.64] ; /* 0x0000000410097981 */
/* 0x000168000c1e1900 */
/*0340*/ LDG.E R10, [R12.64+0x14] ; /* 0x000014040c0a7981 */
/* 0x002f68000c1e1900 */
/*0350*/ LDG.E R28, [R12.64+0x1c] ; /* 0x00001c040c1c7981 */
/* 0x000f62000c1e1900 */
/*0360*/ IMAD.WIDE R16, R7, 0x4, R16 ; /* 0x0000000407107825 */
/* 0x001fca00078e0210 */
/*0370*/ LDG.E R11, [R16.64] ; /* 0x00000004100b7981 */
/* 0x000562000c1e1900 */
/*0380*/ IMAD.WIDE R22, R7, 0x4, R16 ; /* 0x0000000407167825 */
/* 0x000fc800078e0210 */
/*0390*/ FFMA R16, R21, R20, R24 ; /* 0x0000001415107223 */
/* 0x004fe40000000018 */
/*03a0*/ LDG.E R20, [R12.64+0x18] ; /* 0x000018040c147981 */
/* 0x000ea2000c1e1900 */
/*03b0*/ IMAD.WIDE R24, R7, 0x4, R22 ; /* 0x0000000407187825 */
/* 0x000fc600078e0216 */
/*03c0*/ LDG.E R21, [R22.64] ; /* 0x0000000416157981 */
/* 0x0000a8000c1e1900 */
/*03d0*/ LDG.E R29, [R24.64] ; /* 0x00000004181d7981 */
/* 0x0002a2000c1e1900 */
/*03e0*/ FFMA R16, R15, R14, R16 ; /* 0x0000000e0f107223 */
/* 0x008fe40000000010 */
/*03f0*/ IMAD.WIDE R14, R7.reuse, 0x4, R24 ; /* 0x00000004070e7825 */
/* 0x040fe200078e0218 */
/*0400*/ LDG.E R23, [R12.64+0x20] ; /* 0x000020040c177981 */
/* 0x001ee6000c1e1900 */
/*0410*/ FFMA R26, R26, R27, R16 ; /* 0x0000001b1a1a7223 */
/* 0x010fe20000000010 */
/*0420*/ LDG.E R25, [R12.64+0x24] ; /* 0x000024040c197981 */
/* 0x002f22000c1e1900 */
/*0430*/ IMAD.WIDE R16, R7, 0x4, R14 ; /* 0x0000000407107825 */
/* 0x000fc600078e020e */
/*0440*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x0000e2000c1e1900 */
/*0450*/ FFMA R26, R19, R18, R26 ; /* 0x00000012131a7223 */
/* 0x020fe4000000001a */
/*0460*/ IMAD.WIDE R18, R7, 0x4, R16 ; /* 0x0000000407127825 */
/* 0x000fe200078e0210 */
/*0470*/ LDG.E R22, [R12.64+0x28] ; /* 0x000028040c167981 */
/* 0x000f66000c1e1900 */
/*0480*/ FFMA R26, R9, R8, R26 ; /* 0x00000008091a7223 */
/* 0x000fe2000000001a */
/*0490*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000322000c1e1900 */
/*04a0*/ IMAD.WIDE R8, R7, 0x4, R18 ; /* 0x0000000407087825 */
/* 0x000fc600078e0212 */
/*04b0*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000368000c1e1900 */
/*04c0*/ LDG.E R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x000568000c1e1900 */
/*04d0*/ LDG.E R15, [R12.64+0x2c] ; /* 0x00002c040c0f7981 */
/* 0x001f62000c1e1900 */
/*04e0*/ FFMA R26, R11, R10, R26 ; /* 0x0000000a0b1a7223 */
/* 0x000fe4000000001a */
/*04f0*/ IMAD.WIDE R10, R7, 0x4, R8 ; /* 0x00000004070a7825 */
/* 0x000fe200078e0208 */
/*0500*/ LDG.E R17, [R12.64+0x30] ; /* 0x000030040c117981 */
/* 0x002f66000c1e1900 */
/*0510*/ FFMA R26, R21, R20, R26 ; /* 0x00000014151a7223 */
/* 0x004fc4000000001a */
/*0520*/ IMAD.WIDE R20, R7, 0x4, R10 ; /* 0x0000000407147825 */
/* 0x000fe400078e020a */
/*0530*/ LDG.E R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x0000a4000c1e1900 */
/*0540*/ FFMA R28, R29, R28, R26 ; /* 0x0000001c1d1c7223 */
/* 0x000fe4000000001a */
/*0550*/ IMAD.WIDE R26, R7.reuse, 0x4, R20 ; /* 0x00000004071a7825 */
/* 0x040fe200078e0214 */
/*0560*/ LDG.E R29, [R12.64+0x34] ; /* 0x000034040c1d7981 */
/* 0x000ea8000c1e1900 */
/*0570*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x0002a2000c1e1900 */
/*0580*/ IMAD.WIDE R8, R7, 0x4, R26 ; /* 0x0000000407087825 */
/* 0x000fc600078e021a */
/*0590*/ LDG.E R19, [R26.64] ; /* 0x000000041a137981 */
/* 0x0006a8000c1e1900 */
/*05a0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x0010a8000c1e1900 */
/*05b0*/ LDG.E R21, [R12.64+0x38] ; /* 0x000038040c157981 */
/* 0x002ea8000c1e1900 */
/*05c0*/ LDG.E R26, [R12.64+0x3c] ; /* 0x00003c040c1a7981 */
/* 0x008ee2000c1e1900 */
/*05d0*/ FFMA R14, R14, R23, R28 ; /* 0x000000170e0e7223 */
/* 0x000fc8000000001c */
/*05e0*/ FFMA R25, R16, R25, R14 ; /* 0x0000001910197223 */
/* 0x010fe2000000000e */
/*05f0*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fc60007ffe0ff */
/*0600*/ FFMA R18, R18, R22, R25 ; /* 0x0000001612127223 */
/* 0x020fe20000000019 */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fc60003f24270 */
/*0620*/ FFMA R15, R24, R15, R18 ; /* 0x0000000f180f7223 */
/* 0x000fe20000000012 */
/*0630*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0640*/ IMAD.WIDE R8, R7, 0x4, R8 ; /* 0x0000000407087825 */
/* 0x001fc600078e0208 */
/*0650*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0660*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe20007ffe0ff */
/*0670*/ FFMA R10, R10, R17, R15 ; /* 0x000000110a0a7223 */
/* 0x004fc8000000000f */
/*0680*/ FFMA R10, R20, R29, R10 ; /* 0x0000001d140a7223 */
/* 0x000fc8000000000a */
/*0690*/ FFMA R10, R19, R21, R10 ; /* 0x00000015130a7223 */
/* 0x000fc8000000000a */
/*06a0*/ FFMA R24, R11, R26, R10 ; /* 0x0000001a0b187223 */
/* 0x008fe2000000000a */
/*06b0*/ @P1 BRA 0x220 ; /* 0xfffffb6000001947 */
/* 0x000fea000383ffff */
/*06c0*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*06d0*/ @!P1 BRA 0x970 ; /* 0x0000029000009947 */
/* 0x000fea0003800000 */
/*06e0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fe20000000f00 */
/*06f0*/ LDG.E R23, [R8.64] ; /* 0x0000000408177981 */
/* 0x0000a2000c1e1900 */
/*0700*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*0710*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe20008000f00 */
/*0720*/ IMAD.WIDE R16, R7, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x000fc800078e0208 */
/*0730*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*0740*/ IMAD.WIDE R12, R7.reuse, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x040fe200078e0210 */
/*0750*/ LDG.E R22, [R10.64] ; /* 0x000000040a167981 */
/* 0x000ea8000c1e1900 */
/*0760*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002e2000c1e1900 */
/*0770*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0780*/ LDG.E R25, [R10.64+0x4] ; /* 0x000004040a197981 */
/* 0x000ee6000c1e1900 */
/*0790*/ IMAD.WIDE R18, R7.reuse, 0x4, R14 ; /* 0x0000000407127825 */
/* 0x040fe200078e020e */
/*07a0*/ LDG.E R26, [R12.64] ; /* 0x000000040c1a7981 */
/* 0x000968000c1e1900 */
/*07b0*/ LDG.E R27, [R10.64+0x8] ; /* 0x000008040a1b7981 */
/* 0x000f62000c1e1900 */
/*07c0*/ IMAD.WIDE R20, R7, 0x4, R18 ; /* 0x0000000407147825 */
/* 0x000fc600078e0212 */
/*07d0*/ LDG.E R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000368000c1e1900 */
/*07e0*/ LDG.E R29, [R10.64+0xc] ; /* 0x00000c040a1d7981 */
/* 0x000f62000c1e1900 */
/*07f0*/ IMAD.WIDE R8, R7, 0x4, R20 ; /* 0x0000000407087825 */
/* 0x001fc600078e0214 */
/*0800*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000168000c1e1900 */
/*0810*/ LDG.E R28, [R10.64+0x10] ; /* 0x000010040a1c7981 */
/* 0x000f62000c1e1900 */
/*0820*/ IMAD.WIDE R12, R7, 0x4, R8 ; /* 0x00000004070c7825 */
/* 0x010fc600078e0208 */
/*0830*/ LDG.E R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000968000c1e1900 */
/*0840*/ LDG.E R15, [R10.64+0x14] ; /* 0x000014040a0f7981 */
/* 0x002f68000c1e1900 */
/*0850*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000368000c1e1900 */
/*0860*/ LDG.E R21, [R10.64+0x1c] ; /* 0x00001c040a157981 */
/* 0x010f28000c1e1900 */
/*0870*/ LDG.E R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001f28000c1e1900 */
/*0880*/ LDG.E R8, [R10.64+0x18] ; /* 0x000018040a087981 */
/* 0x002f22000c1e1900 */
/*0890*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*08a0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*08c0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*08d0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08e0*/ FFMA R22, R23, R22, R24 ; /* 0x0000001617167223 */
/* 0x004fc80000000018 */
/*08f0*/ FFMA R16, R16, R25, R22 ; /* 0x0000001910107223 */
/* 0x008fc80000000016 */
/*0900*/ FFMA R16, R26, R27, R16 ; /* 0x0000001b1a107223 */
/* 0x020fc80000000010 */
/*0910*/ FFMA R29, R14, R29, R16 ; /* 0x0000001d0e1d7223 */
/* 0x000fc80000000010 */
/*0920*/ FFMA R18, R18, R28, R29 ; /* 0x0000001c12127223 */
/* 0x000fc8000000001d */
/*0930*/ FFMA R15, R20, R15, R18 ; /* 0x0000000f140f7223 */
/* 0x000fc80000000012 */
/*0940*/ FFMA R24, R17, R8, R15 ; /* 0x0000000811187223 */
/* 0x010fe4000000000f */
/*0950*/ IMAD.WIDE R8, R7, 0x4, R12 ; /* 0x0000000407087825 */
/* 0x000fc800078e020c */
/*0960*/ FFMA R24, R19, R21, R24 ; /* 0x0000001513187223 */
/* 0x000fe40000000018 */
/*0970*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000705670 */
/*0980*/ @!P0 BRA 0xb30 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0990*/ MOV R10, UR6 ; /* 0x00000006000a7c02 */
/* 0x000fe40008000f00 */
/*09a0*/ MOV R11, UR7 ; /* 0x00000007000b7c02 */
/* 0x000fe40008000f00 */
/*09b0*/ MOV R7, c[0x0][0x170] ; /* 0x00005c0000077a02 */
/* 0x000fc60000000f00 */
/*09c0*/ IMAD.WIDE R10, R6, 0x4, R10 ; /* 0x00000004060a7825 */
/* 0x000fc800078e020a */
/*09d0*/ IMAD.WIDE R16, R7.reuse, 0x4, R8 ; /* 0x0000000407107825 */
/* 0x040fe200078e0208 */
/*09e0*/ LDG.E R18, [R10.64] ; /* 0x000000040a127981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea2000c1e1900 */
/*0a00*/ IMAD.WIDE R12, R7, 0x4, R16 ; /* 0x00000004070c7825 */
/* 0x000fc600078e0210 */
/*0a10*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee8000c1e1900 */
/*0a20*/ LDG.E R19, [R10.64+0x4] ; /* 0x000004040a137981 */
/* 0x000ee2000c1e1900 */
/*0a30*/ IMAD.WIDE R14, R7, 0x4, R12 ; /* 0x00000004070e7825 */
/* 0x000fc600078e020c */
/*0a40*/ LDG.E R21, [R12.64] ; /* 0x000000040c157981 */
/* 0x000f28000c1e1900 */
/*0a50*/ LDG.E R20, [R10.64+0x8] ; /* 0x000008040a147981 */
/* 0x000f28000c1e1900 */
/*0a60*/ LDG.E R22, [R10.64+0xc] ; /* 0x00000c040a167981 */
/* 0x000f68000c1e1900 */
/*0a70*/ LDG.E R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x000f62000c1e1900 */
/*0a80*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0aa0*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0ab0*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc60007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R18, R9, R18, R24 ; /* 0x0000001209127223 */
/* 0x004fc80000000018 */
/*0ae0*/ FFMA R18, R17, R19, R18 ; /* 0x0000001311127223 */
/* 0x008fe40000000012 */
/*0af0*/ IMAD.WIDE R8, R7, 0x4, R14 ; /* 0x0000000407087825 */
/* 0x000fc800078e020e */
/*0b00*/ FFMA R18, R21, R20, R18 ; /* 0x0000001415127223 */
/* 0x010fc80000000012 */
/*0b10*/ FFMA R24, R23, R22, R18 ; /* 0x0000001617187223 */
/* 0x020fe20000000012 */
/*0b20*/ @P0 BRA 0x990 ; /* 0xfffffe6000000947 */
/* 0x000fea000383ffff */
/*0b30*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0b40*/ @!P0 BRA 0xc40 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0b50*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0b60*/ IMAD R6, R0, c[0x0][0x160], R2 ; /* 0x0000580000067a24 */
/* 0x000fe400078e0202 */
/*0b70*/ IMAD R2, R2, c[0x0][0x170], R3 ; /* 0x00005c0002027a24 */
/* 0x000fce00078e0203 */
/*0b80*/ IMAD.WIDE R6, R6, R9, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fc800078e0209 */
/*0b90*/ IMAD.WIDE R8, R2, R9, c[0x0][0x178] ; /* 0x00005e0002087625 */
/* 0x000fca00078e0209 */
/*0ba0*/ LDG.E R5, [R8.64] ; /* 0x0000000408057981 */
/* 0x0000a8000c1e1900 */
/*0bb0*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x0002a2000c1e1900 */
/*0bc0*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0bd0*/ MOV R11, c[0x0][0x170] ; /* 0x00005c00000b7a02 */
/* 0x000fe40000000f00 */
/*0be0*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc60003f05270 */
/*0bf0*/ IMAD.WIDE R8, R11, 0x4, R8 ; /* 0x000000040b087825 */
/* 0x001fe200078e0208 */
/*0c00*/ IADD3 R6, P1, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x002fc80007f3e0ff */
/*0c10*/ IADD3.X R7, RZ, R7, RZ, P1, !PT ; /* 0x00000007ff077210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ FFMA R24, R5, R2, R24 ; /* 0x0000000205187223 */
/* 0x004fc80000000018 */
/*0c30*/ @P0 BRA 0xba0 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0c40*/ MOV R2, 0x4 ; /* 0x0000000400027802 */
/* 0x000fe20000000f00 */
/*0c50*/ IMAD R3, R0, c[0x0][0x180], R3 ; /* 0x0000600000037a24 */
/* 0x000fc800078e0203 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x188] ; /* 0x0000620003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E [R2.64], R24 ; /* 0x0000001802007986 */
/* 0x000fe2000c101904 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12MatMulKernel6MatrixS_S_
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 8
.type _Z12MatMulKernel6MatrixS_S_,@function
_Z12MatMulKernel6MatrixS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b64 s[4:5], s[0:1], 0x20
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_add_u32 s6, s0, 32
s_addc_u32 s7, s1, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s5, v0
v_cmp_gt_i32_e64 s2, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_clause 0x1
s_load_b32 s5, s[0:1], 0x0
s_load_b64 s[2:3], s[6:7], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[8:9], s[0:1], 0x8
v_mul_lo_u32 v2, v0, s5
s_clause 0x1
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[0:1], s[0:1], 0x18
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v4, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s8, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v5, 31, v4
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s5, 0
v_lshlrev_b64 v[7:8], 2, v[4:5]
v_add_nc_u32_e32 v4, s6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v5, v[2:3], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v5, v7
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v6, 0
.LBB0_5:
v_mad_u64_u32 v[2:3], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_store_b32 v[0:1], v6, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12MatMulKernel6MatrixS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12MatMulKernel6MatrixS_S_, .Lfunc_end0-_Z12MatMulKernel6MatrixS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 16
.value_kind: by_value
- .offset: 32
.size: 16
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12MatMulKernel6MatrixS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12MatMulKernel6MatrixS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00145207_00000000-6_mat_mul.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.2f\t"
.LC1:
.string "\n"
.text
.globl _Z12print_matrix6Matrix
.type _Z12print_matrix6Matrix, @function
_Z12print_matrix6Matrix:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rax
sarq $32, %rax
movl %eax, 16(%rsp)
movl %edi, 12(%rsp)
testl %eax, %eax
jle .L3
movq %rsi, %r12
movl %edi, 20(%rsp)
movl $0, %r15d
movl $0, %r14d
movslq %edi, %rax
movq %rax, 24(%rsp)
leaq .LC0(%rip), %r13
jmp .L5
.L7:
movslq %r15d, %rbp
leaq 0(,%rbp,4), %rbx
movq 24(%rsp), %rax
addq %rax, %rbp
salq $2, %rbp
.L6:
pxor %xmm0, %xmm0
cvtss2sd (%rbx,%r12), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L6
.L8:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r14d
movl 20(%rsp), %eax
addl %eax, %r15d
movl 16(%rsp), %eax
cmpl %eax, %r14d
je .L3
.L5:
cmpl $0, 12(%rsp)
jg .L7
jmp .L8
.L3:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z12print_matrix6Matrix, .-_Z12print_matrix6Matrix
.globl _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.type _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, @function
_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movq %rdi, 64(%rsp)
movq %rsi, 72(%rsp)
movq %rdx, 80(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 120
pushq 8(%rsp)
.cfi_def_cfa_offset 128
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_, .-_Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
.globl _Z12MatMulKernel6MatrixS_S_
.type _Z12MatMulKernel6MatrixS_S_, @function
_Z12MatMulKernel6MatrixS_S_:
.LFB2085:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %rdi, 32(%rsp)
movq %rsi, 40(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 24(%rsp)
movq %r8, (%rsp)
movq %r9, 8(%rsp)
movq %rsp, %rdx
leaq 16(%rsp), %rsi
leaq 32(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
addq $56, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12MatMulKernel6MatrixS_S_, .-_Z12MatMulKernel6MatrixS_S_
.globl _Z6MatMul6MatrixS_S_
.type _Z6MatMul6MatrixS_S_, @function
_Z6MatMul6MatrixS_S_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $184, %rsp
.cfi_def_cfa_offset 240
movq %rdi, %rbx
movq %rsi, 8(%rsp)
movq %rdx, %rbp
movq %rcx, 16(%rsp)
movq %r8, %r15
movq %r9, 24(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, %r14
sarq $32, %r14
movq %rdx, %r13
sarq $32, %r13
movq %r8, %r12
sarq $32, %r12
movl %edi, 64(%rsp)
movl %r14d, 68(%rsp)
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
movl %ebp, 80(%rsp)
movl %r13d, 84(%rsp)
imull %ebp, %r13d
movslq %r13d, %r13
salq $2, %r13
leaq 88(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r13, %rdx
movq 16(%rsp), %rsi
movq 88(%rsp), %rdi
call cudaMemcpy@PLT
movl %r15d, 96(%rsp)
movl %r12d, 100(%rsp)
imull %r15d, %r12d
movslq %r12d, %r12
salq $2, %r12
leaq 104(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
addl $15, %ebp
shrl $4, %ebp
movl %ebp, 52(%rsp)
addl $15, %r14d
shrl $4, %r14d
movl %r14d, 56(%rsp)
movl $16, 40(%rsp)
movl $16, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 40(%rsp), %rdx
movl $1, %ecx
movq 52(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L23
.L20:
movl $2, %ecx
movq %r12, %rdx
movq 104(%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rdi
call cudaFree@PLT
movq 104(%rsp), %rdi
call cudaFree@PLT
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
movdqa 64(%rsp), %xmm0
movaps %xmm0, 112(%rsp)
movdqa 80(%rsp), %xmm1
movaps %xmm1, 128(%rsp)
movdqa 96(%rsp), %xmm2
movaps %xmm2, 144(%rsp)
leaq 144(%rsp), %rdx
leaq 128(%rsp), %rsi
leaq 112(%rsp), %rdi
call _Z41__device_stub__Z12MatMulKernel6MatrixS_S_R6MatrixS0_S0_
jmp .L20
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z6MatMul6MatrixS_S_, .-_Z6MatMul6MatrixS_S_
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
movl $4800, %edi
call malloc@PLT
movq %rax, %rbx
leaq 4800(%rax), %rdx
movss .LC2(%rip), %xmm0
.L26:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L26
movl $4800, %edi
call malloc@PLT
movq %rax, %rbp
leaq 4800(%rax), %rdx
movss .LC2(%rip), %xmm0
.L27:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L27
movabsq $128849018910, %r13
movl $3600, %edi
call malloc@PLT
movq %rax, %r12
movq %r13, %r8
movq %rax, %r9
movabsq $171798691870, %rdx
movq %rbp, %rcx
movabsq $128849018920, %rdi
movq %rbx, %rsi
call _Z6MatMul6MatrixS_S_
movq %r13, %rdi
movq %r12, %rsi
call _Z12print_matrix6Matrix
movl $0, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z12MatMulKernel6MatrixS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z12MatMulKernel6MatrixS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "mat_mul.hip"
.globl _Z12print_matrix6Matrix # -- Begin function _Z12print_matrix6Matrix
.p2align 4, 0x90
.type _Z12print_matrix6Matrix,@function
_Z12print_matrix6Matrix: # @_Z12print_matrix6Matrix
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %rax
shrq $32, %rax
movq %rax, 16(%rsp) # 8-byte Spill
testl %eax, %eax
jle .LBB0_6
# %bb.1: # %.preheader.lr.ph
movq %rdi, %r14
movl %r14d, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_5: # %._crit_edge
# in Loop: Header=BB0_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %r14d, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB0_6
.LBB0_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_4 Depth 2
testl %r14d, %r14d
jle .LBB0_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB0_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %rbx
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_4: # Parent Loop BB0_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB0_4
jmp .LBB0_5
.LBB0_6: # %._crit_edge10
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z12print_matrix6Matrix, .Lfunc_end0-_Z12print_matrix6Matrix
.cfi_endproc
# -- End function
.globl _Z6MatMul6MatrixS_S_ # -- Begin function _Z6MatMul6MatrixS_S_
.p2align 4, 0x90
.type _Z6MatMul6MatrixS_S_,@function
_Z6MatMul6MatrixS_S_: # @_Z6MatMul6MatrixS_S_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 72(%rsp) # 8-byte Spill
movq %r8, %r14
movq %r8, 56(%rsp) # 8-byte Spill
movq %rcx, 64(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, %r13
movq %rdx, %r15
shrq $32, %r15
shrq $32, %r14
movq %rdi, 40(%rsp)
movq %rdi, %rbx
shrq $32, %rbx
movl %ebx, %eax
imull %edi, %eax
movslq %eax, %rbp
shlq $2, %rbp
leaq 48(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq %r12, 24(%rsp)
imull %r12d, %r15d
movslq %r15d, %r13
shlq $2, %r13
leaq 32(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 32(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 56(%rsp), %rax # 8-byte Reload
movq %rax, 8(%rsp)
imull %eax, %r14d
movslq %r14d, %r14
shlq $2, %r14
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leal 15(%r12), %eax
shrl $4, %eax
shlq $28, %rbx
orq %rax, %rbx
movl $4026531840, %eax # imm = 0xF0000000
addq %rbx, %rax
movabsq $1152921500580315135, %rdi # imm = 0xFFFFFFF0FFFFFFF
andq %rax, %rdi
movabsq $68719476752, %rdx # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movups 40(%rsp), %xmm0
movups 24(%rsp), %xmm1
movups 8(%rsp), %xmm2
movups %xmm0, 184(%rsp)
movups %xmm1, 168(%rsp)
movups %xmm2, 152(%rsp)
leaq 184(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 152(%rsp), %rax
movq %rax, 144(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi # 8-byte Reload
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6MatMul6MatrixS_S_, .Lfunc_end1-_Z6MatMul6MatrixS_S_
.cfi_endproc
# -- End function
.globl _Z27__device_stub__MatMulKernel6MatrixS_S_ # -- Begin function _Z27__device_stub__MatMulKernel6MatrixS_S_
.p2align 4, 0x90
.type _Z27__device_stub__MatMulKernel6MatrixS_S_,@function
_Z27__device_stub__MatMulKernel6MatrixS_S_: # @_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 80(%rsp)
movq %rsi, 88(%rsp)
movq %rdx, 64(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 48(%rsp)
movq %r9, 56(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12MatMulKernel6MatrixS_S_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z27__device_stub__MatMulKernel6MatrixS_S_, .Lfunc_end2-_Z27__device_stub__MatMulKernel6MatrixS_S_
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r14
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_1: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r14,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1200, %rax # imm = 0x4B0
jne .LBB3_1
# %bb.2:
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB3_3: # =>This Inner Loop Header: Depth=1
movl $1065353216, (%r15,%rax,4) # imm = 0x3F800000
incq %rax
cmpq $1200, %rax # imm = 0x4B0
jne .LBB3_3
# %bb.4:
movl $3600, %edi # imm = 0xE10
callq malloc
movq %rax, %rbx
movabsq $128849018910, %r8 # imm = 0x1E0000001E
leaq 10(%r8), %rdi
movabsq $171798691870, %rdx # imm = 0x280000001E
movq %r14, %rsi
movq %r15, %rcx
movq %rax, %r9
callq _Z6MatMul6MatrixS_S_
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_5: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB3_6 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB3_6: # Parent Loop BB3_5 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq $30, %r15
jne .LBB3_6
# %bb.7: # %._crit_edge.i
# in Loop: Header=BB3_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $120, %rbx
cmpq $30, %r14
jne .LBB3_5
# %bb.8: # %_Z12print_matrix6Matrix.exit
xorl %eax, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12MatMulKernel6MatrixS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f\t"
.size .L.str, 6
.type _Z12MatMulKernel6MatrixS_S_,@object # @_Z12MatMulKernel6MatrixS_S_
.section .rodata,"a",@progbits
.globl _Z12MatMulKernel6MatrixS_S_
.p2align 3, 0x0
_Z12MatMulKernel6MatrixS_S_:
.quad _Z27__device_stub__MatMulKernel6MatrixS_S_
.size _Z12MatMulKernel6MatrixS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12MatMulKernel6MatrixS_S_"
.size .L__unnamed_1, 28
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__MatMulKernel6MatrixS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12MatMulKernel6MatrixS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cufft.h>
#include <cuda_profiler_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
extern "C"
__global__
void data_transfer_real_cplx(
int nx
, int ny
, int nz
, float * in
, cufftComplex * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
for (std::size_t kz = 0; kz < nz; kz++)
{
out[(kx*ny + ky)*nz + kz].x = ldg(&in[(kx*ny + ky)*nz + kz]);
out[(kx*ny + ky)*nz + kz].y = 0;
}
}
}
extern "C"
__global__
void data_transfer_cplx_real(
int nx
, int ny
, int nz
, cufftComplex * in
, float * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
for (int i = 0; i < nz; i++, k_1 += nx*ny)
{
out[k_1] = ldg(&in[k_1]).x;
}
}
} | code for sm_80
Function : data_transfer_cplx_real
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x160], P0 ; /* 0x0000580000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fc80000000f00 */
/*00b0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R4, R2, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD R25, R3, c[0x0][0x160], R0 ; /* 0x0000580003197a24 */
/* 0x000fe200078e0200 */
/*00f0*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0110*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0120*/ LOP3.LUT R0, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302007812 */
/* 0x000fe200078ec0ff */
/*0130*/ IMAD R2, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a24 */
/* 0x000fd400078e02ff */
/*0140*/ @!P0 BRA 0xac0 ; /* 0x0000097000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R3, -R0, c[0x0][0x168], RZ ; /* 0x00005a0000037a10 */
/* 0x000fc80007ffe1ff */
/*0160*/ ISETP.GT.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f04270 */
/*0170*/ @!P0 BRA 0x950 ; /* 0x000007d000008947 */
/* 0x000fea0003800000 */
/*0180*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe40003f24270 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01a0*/ @!P1 BRA 0x690 ; /* 0x000004e000009947 */
/* 0x000fea0003800000 */
/*01b0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01c0*/ HFMA2.MMA R22, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff167435 */
/* 0x000fe200000001ff */
/*01d0*/ IADD3 R5, R2, R25, R2 ; /* 0x0000001902057210 */
/* 0x000fc80007ffe002 */
/*01e0*/ IADD3 R4, R2, R5, R2 ; /* 0x0000000502047210 */
/* 0x000fca0007ffe002 */
/*01f0*/ IMAD.WIDE R8, R25, R22, c[0x0][0x170] ; /* 0x00005c0019087625 */
/* 0x000fe200078e0216 */
/*0200*/ IADD3 R7, R2, R4, R2 ; /* 0x0000000402077210 */
/* 0x000fc80007ffe002 */
/*0210*/ LDG.E.CONSTANT R24, [R8.64] ; /* 0x0000000408187981 */
/* 0x0000a2000c1e9900 */
/*0220*/ IMAD.WIDE R10, R2.reuse, 0x8, R8 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0208 */
/*0230*/ IADD3 R6, R2, R7, R2 ; /* 0x0000000702067210 */
/* 0x000fc60007ffe002 */
/*0240*/ IMAD.WIDE R26, R4, R22, c[0x0][0x170] ; /* 0x00005c00041a7625 */
/* 0x000fe200078e0216 */
/*0250*/ LDG.E.CONSTANT R5, [R10.64] ; /* 0x000000040a057981 */
/* 0x0022e6000c1e9900 */
/*0260*/ IMAD.WIDE R28, R2.reuse, 0x8, R10 ; /* 0x00000008021c7825 */
/* 0x040fe200078e020a */
/*0270*/ IADD3 R17, R2, R6, R2 ; /* 0x0000000602117210 */
/* 0x000fc60007ffe002 */
/*0280*/ IMAD.WIDE R14, R2, 0x8, R26 ; /* 0x00000008020e7825 */
/* 0x000fe200078e021a */
/*0290*/ LDG.E.CONSTANT R7, [R28.64] ; /* 0x000000041c077981 */
/* 0x000966000c1e9900 */
/*02a0*/ IMAD.WIDE R12, R6, R22, c[0x0][0x170] ; /* 0x00005c00060c7625 */
/* 0x000fe200078e0216 */
/*02b0*/ IADD3 R9, R2.reuse, R17, R2 ; /* 0x0000001102097210 */
/* 0x041fe20007ffe002 */
/*02c0*/ LDG.E.CONSTANT R10, [R26.64] ; /* 0x000000041a0a7981 */
/* 0x002164000c1e9900 */
/*02d0*/ IMAD.WIDE R18, R2.reuse, 0x8, R14 ; /* 0x0000000802127825 */
/* 0x040fe400078e020e */
/*02e0*/ LDG.E.CONSTANT R11, [R14.64] ; /* 0x000000040e0b7981 */
/* 0x000364000c1e9900 */
/*02f0*/ IMAD.WIDE R28, R2, 0x8, R28 ; /* 0x00000008021c7825 */
/* 0x010fc800078e021c */
/*0300*/ IMAD.WIDE R16, R2, 0x8, R12 ; /* 0x0000000802107825 */
/* 0x000fe200078e020c */
/*0310*/ LDG.E.CONSTANT R8, [R28.64] ; /* 0x000000041c087981 */
/* 0x000f26000c1e9900 */
/*0320*/ IMAD.WIDE R22, R9, R22, c[0x0][0x170] ; /* 0x00005c0009167625 */
/* 0x000fc800078e0216 */
/*0330*/ IMAD.WIDE R20, R2.reuse, 0x8, R18 ; /* 0x0000000802147825 */
/* 0x040fe400078e0212 */
/*0340*/ LDG.E.CONSTANT R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000124000c1e9900 */
/*0350*/ IMAD.WIDE R14, R2.reuse, 0x8, R16 ; /* 0x00000008020e7825 */
/* 0x042fe400078e0210 */
/*0360*/ LDG.E.CONSTANT R20, [R20.64] ; /* 0x0000000414147981 */
/* 0x000328000c1e9900 */
/*0370*/ LDG.E.CONSTANT R19, [R12.64] ; /* 0x000000040c137981 */
/* 0x001128000c1e9900 */
/*0380*/ LDG.E.CONSTANT R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x002322000c1e9900 */
/*0390*/ IMAD.WIDE R12, R2, 0x8, R22 ; /* 0x00000008020c7825 */
/* 0x001fc600078e0216 */
/*03a0*/ LDG.E.CONSTANT R22, [R22.64] ; /* 0x0000000416167981 */
/* 0x000126000c1e9900 */
/*03b0*/ IMAD.WIDE R16, R2.reuse, 0x8, R12 ; /* 0x0000000802107825 */
/* 0x042fe200078e020c */
/*03c0*/ LDG.E.CONSTANT R23, [R14.64] ; /* 0x000000040e177981 */
/* 0x001126000c1e9900 */
/*03d0*/ IMAD.WIDE R14, R2, 0x8, R14 ; /* 0x00000008020e7825 */
/* 0x001fcc00078e020e */
/*03e0*/ LDG.E.CONSTANT R14, [R14.64] ; /* 0x000000040e0e7981 */
/* 0x000128000c1e9900 */
/*03f0*/ LDG.E.CONSTANT R15, [R12.64] ; /* 0x000000040c0f7981 */
/* 0x001124000c1e9900 */
/*0400*/ IMAD.WIDE R12, R2, 0x8, R16 ; /* 0x00000008020c7825 */
/* 0x001fe400078e0210 */
/*0410*/ LDG.E.CONSTANT R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000128000c1e9900 */
/*0420*/ LDG.E.CONSTANT R17, [R12.64] ; /* 0x000000040c117981 */
/* 0x001122000c1e9900 */
/*0430*/ MOV R26, 0x4 ; /* 0x00000004001a7802 */
/* 0x000fca0000000f00 */
/*0440*/ IMAD.WIDE R12, R25, R26, c[0x0][0x178] ; /* 0x00005e00190c7625 */
/* 0x001fe200078e021a */
/*0450*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fc80007ffe0ff */
/*0460*/ ISETP.GT.AND P1, PT, R3, 0xc, PT ; /* 0x0000000c0300780c */
/* 0x000fe20003f24270 */
/*0470*/ STG.E [R12.64], R24 ; /* 0x000000180c007986 */
/* 0x0041e4000c101904 */
/*0480*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x001fca00078e020c */
/*0490*/ STG.E [R12.64], R5 ; /* 0x000000050c007986 */
/* 0x0081e4000c101904 */
/*04a0*/ IMAD.WIDE R12, R2, 0x4, R12 ; /* 0x00000004020c7825 */
/* 0x001fc800078e020c */
/*04b0*/ IMAD.WIDE R4, R4, R26, c[0x0][0x178] ; /* 0x00005e0004047625 */
/* 0x000fe200078e021a */
/*04c0*/ STG.E [R12.64], R7 ; /* 0x000000070c007986 */
/* 0x0201e6000c101904 */
/*04d0*/ IMAD.WIDE R24, R2, 0x4, R12 ; /* 0x0000000402187825 */
/* 0x000fca00078e020c */
/*04e0*/ STG.E [R24.64], R8 ; /* 0x0000000818007986 */
/* 0x010fe2000c101904 */
/*04f0*/ IMAD.WIDE R12, R2, 0x4, R4 ; /* 0x00000004020c7825 */
/* 0x001fc600078e0204 */
/*0500*/ STG.E [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0001e2000c101904 */
/*0510*/ IMAD.WIDE R6, R6, R26, c[0x0][0x178] ; /* 0x00005e0006067625 */
/* 0x000fc600078e021a */
/*0520*/ STG.E [R12.64], R11 ; /* 0x0000000b0c007986 */
/* 0x0003e2000c101904 */
/*0530*/ IMAD.WIDE R26, R9, R26, c[0x0][0x178] ; /* 0x00005e00091a7625 */
/* 0x000fc800078e021a */
/*0540*/ IMAD.WIDE R4, R2, 0x4, R12 ; /* 0x0000000402047825 */
/* 0x001fc800078e020c */
/*0550*/ IMAD.WIDE R10, R2.reuse, 0x4, R6 ; /* 0x00000004020a7825 */
/* 0x042fe200078e0206 */
/*0560*/ STG.E [R4.64], R18 ; /* 0x0000001204007986 */
/* 0x0001e6000c101904 */
/*0570*/ IMAD.WIDE R24, R2, 0x4, R4 ; /* 0x0000000402187825 */
/* 0x000fc800078e0204 */
/*0580*/ IMAD.WIDE R12, R2, 0x4, R10 ; /* 0x00000004020c7825 */
/* 0x000fc800078e020a */
/*0590*/ IMAD.WIDE R4, R2.reuse, 0x4, R26 ; /* 0x0000000402047825 */
/* 0x041fe200078e021a */
/*05a0*/ STG.E [R24.64], R20 ; /* 0x0000001418007986 */
/* 0x0001e8000c101904 */
/*05b0*/ STG.E [R6.64], R19 ; /* 0x0000001306007986 */
/* 0x0003e2000c101904 */
/*05c0*/ IMAD.WIDE R24, R2, 0x4, R4 ; /* 0x0000000402187825 */
/* 0x001fc600078e0204 */
/*05d0*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x000fe2000c101904 */
/*05e0*/ IMAD.WIDE R6, R2, 0x4, R12 ; /* 0x0000000402067825 */
/* 0x002fc600078e020c */
/*05f0*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x000fe2000c101904 */
/*0600*/ IMAD.WIDE R28, R2, 0x4, R24 ; /* 0x00000004021c7825 */
/* 0x000fc600078e0218 */
/*0610*/ STG.E [R6.64], R14 ; /* 0x0000000e06007986 */
/* 0x000fe2000c101904 */
/*0620*/ IADD3 R9, R2, R9, R2 ; /* 0x0000000902097210 */
/* 0x000fc60007ffe002 */
/*0630*/ STG.E [R26.64], R22 ; /* 0x000000161a007986 */
/* 0x000fe8000c101904 */
/*0640*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x000fe8000c101904 */
/*0650*/ STG.E [R24.64], R16 ; /* 0x0000001018007986 */
/* 0x0001e8000c101904 */
/*0660*/ STG.E [R28.64], R17 ; /* 0x000000111c007986 */
/* 0x0003e2000c101904 */
/*0670*/ IADD3 R25, R2, R9, R2 ; /* 0x0000000902197210 */
/* 0x001fe20007ffe002 */
/*0680*/ @P1 BRA 0x1c0 ; /* 0xfffffb3000001947 */
/* 0x000fea000383ffff */
/*0690*/ ISETP.GT.AND P1, PT, R3, 0x4, PT ; /* 0x000000040300780c */
/* 0x000fda0003f24270 */
/*06a0*/ @!P1 BRA 0x930 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06b0*/ HFMA2.MMA R22, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff167435 */
/* 0x000fe200000001ff */
/*06c0*/ IADD3 R17, R2, R25, R2 ; /* 0x0000001902117210 */
/* 0x002fc80007ffe002 */
/*06d0*/ IADD3 R17, R2, R17, R2 ; /* 0x0000001102117210 */
/* 0x000fca0007ffe002 */
/*06e0*/ IMAD.WIDE R8, R25, R22, c[0x0][0x170] ; /* 0x00005c0019087625 */
/* 0x000fc800078e0216 */
/*06f0*/ IMAD.WIDE R22, R17, R22, c[0x0][0x170] ; /* 0x00005c0011167625 */
/* 0x000fe200078e0216 */
/*0700*/ LDG.E.CONSTANT R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x0000a6000c1e9900 */
/*0710*/ IMAD.WIDE R10, R2, 0x8, R8 ; /* 0x00000008020a7825 */
/* 0x000fc800078e0208 */
/*0720*/ IMAD.WIDE R26, R2.reuse, 0x8, R22 ; /* 0x00000008021a7825 */
/* 0x040fe200078e0216 */
/*0730*/ LDG.E.CONSTANT R19, [R10.64] ; /* 0x000000040a137981 */
/* 0x0002e6000c1e9900 */
/*0740*/ IMAD.WIDE R4, R2.reuse, 0x8, R10 ; /* 0x0000000802047825 */
/* 0x040fe200078e020a */
/*0750*/ LDG.E.CONSTANT R23, [R22.64] ; /* 0x0000000416177981 */
/* 0x000f26000c1e9900 */
/*0760*/ IMAD.WIDE R28, R2.reuse, 0x8, R26 ; /* 0x00000008021c7825 */
/* 0x040fe200078e021a */
/*0770*/ LDG.E.CONSTANT R21, [R4.64] ; /* 0x0000000404157981 */
/* 0x000b26000c1e9900 */
/*0780*/ IMAD.WIDE R6, R2.reuse, 0x8, R4 ; /* 0x0000000802067825 */
/* 0x040fe200078e0204 */
/*0790*/ LDG.E.CONSTANT R20, [R26.64] ; /* 0x000000041a147981 */
/* 0x000128000c1e9900 */
/*07a0*/ LDG.E.CONSTANT R16, [R6.64] ; /* 0x0000000406107981 */
/* 0x000122000c1e9900 */
/*07b0*/ IMAD.WIDE R4, R2, 0x8, R28 ; /* 0x0000000802047825 */
/* 0x020fc600078e021c */
/*07c0*/ LDG.E.CONSTANT R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x000f68000c1e9900 */
/*07d0*/ LDG.E.CONSTANT R24, [R4.64] ; /* 0x0000000404187981 */
/* 0x000162000c1e9900 */
/*07e0*/ MOV R12, 0x4 ; /* 0x00000004000c7802 */
/* 0x000fca0000000f00 */
/*07f0*/ IMAD.WIDE R14, R25, R12, c[0x0][0x178] ; /* 0x00005e00190e7625 */
/* 0x000fc800078e020c */
/*0800*/ IMAD.WIDE R8, R17, R12, c[0x0][0x178] ; /* 0x00005e0011087625 */
/* 0x001fc800078e020c */
/*0810*/ IMAD.WIDE R12, R2, 0x4, R14 ; /* 0x00000004020c7825 */
/* 0x000fc800078e020e */
/*0820*/ IMAD.WIDE R6, R2, 0x4, R8 ; /* 0x0000000402067825 */
/* 0x000fc800078e0208 */
/*0830*/ IMAD.WIDE R10, R2, 0x4, R12 ; /* 0x00000004020a7825 */
/* 0x002fc800078e020c */
/*0840*/ IMAD.WIDE R4, R2, 0x4, R6 ; /* 0x0000000402047825 */
/* 0x000fc800078e0206 */
/*0850*/ IMAD.WIDE R26, R2.reuse, 0x4, R10 ; /* 0x00000004021a7825 */
/* 0x040fe200078e020a */
/*0860*/ IADD3 R17, R2.reuse, R17, R2.reuse ; /* 0x0000001102117210 */
/* 0x140fe40007ffe002 */
/*0870*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0880*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe40007ffe0ff */
/*0890*/ IADD3 R25, R2.reuse, R17, R2 ; /* 0x0000001102197210 */
/* 0x040fe20007ffe002 */
/*08a0*/ STG.E [R14.64], R18 ; /* 0x000000120e007986 */
/* 0x004fe8000c101904 */
/*08b0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x008fe8000c101904 */
/*08c0*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0101e8000c101904 */
/*08d0*/ STG.E [R26.64], R16 ; /* 0x000000101a007986 */
/* 0x0003e2000c101904 */
/*08e0*/ IMAD.WIDE R10, R2, 0x4, R4 ; /* 0x00000004020a7825 */
/* 0x001fc600078e0204 */
/*08f0*/ STG.E [R8.64], R23 ; /* 0x0000001708007986 */
/* 0x0003e8000c101904 */
/*0900*/ STG.E [R6.64], R20 ; /* 0x0000001406007986 */
/* 0x0003e8000c101904 */
/*0910*/ STG.E [R4.64], R29 ; /* 0x0000001d04007986 */
/* 0x0203e8000c101904 */
/*0920*/ STG.E [R10.64], R24 ; /* 0x000000180a007986 */
/* 0x0003e4000c101904 */
/*0930*/ ISETP.NE.OR P0, PT, R3, RZ, P0 ; /* 0x000000ff0300720c */
/* 0x000fda0000705670 */
/*0940*/ @!P0 BRA 0xac0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0950*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x002fd400000001ff */
/*0960*/ IMAD.WIDE R4, R25, R4, c[0x0][0x170] ; /* 0x00005c0019047625 */
/* 0x000fcc00078e0204 */
/*0970*/ IMAD.WIDE R8, R2.reuse, 0x8, R4 ; /* 0x0000000802087825 */
/* 0x040fe400078e0204 */
/*0980*/ LDG.E.CONSTANT R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e9900 */
/*0990*/ IMAD.WIDE R12, R2.reuse, 0x8, R8 ; /* 0x00000008020c7825 */
/* 0x040fe400078e0208 */
/*09a0*/ LDG.E.CONSTANT R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ee8000c1e9900 */
/*09b0*/ IMAD.WIDE R16, R2, 0x8, R12 ; /* 0x0000000802107825 */
/* 0x000fc400078e020c */
/*09c0*/ LDG.E.CONSTANT R13, [R12.64] ; /* 0x000000040c0d7981 */
/* 0x000f28000c1e9900 */
/*09d0*/ LDG.E.CONSTANT R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000f62000c1e9900 */
/*09e0*/ MOV R6, 0x4 ; /* 0x0000000400067802 */
/* 0x000fca0000000f00 */
/*09f0*/ IMAD.WIDE R6, R25, R6, c[0x0][0x178] ; /* 0x00005e0019067625 */
/* 0x000fe200078e0206 */
/*0a00*/ IADD3 R3, R3, -0x4, RZ ; /* 0xfffffffc03037810 */
/* 0x000fca0007ffe0ff */
/*0a10*/ IMAD.WIDE R10, R2, 0x4, R6 ; /* 0x00000004020a7825 */
/* 0x000fe200078e0206 */
/*0a20*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fca0003f05270 */
/*0a30*/ IMAD.WIDE R14, R2.reuse, 0x4, R10 ; /* 0x00000004020e7825 */
/* 0x040fe200078e020a */
/*0a40*/ IADD3 R25, R2, R25, R2 ; /* 0x0000001902197210 */
/* 0x000fca0007ffe002 */
/*0a50*/ IMAD.WIDE R18, R2.reuse, 0x4, R14 ; /* 0x0000000402127825 */
/* 0x040fe200078e020e */
/*0a60*/ IADD3 R25, R2, R25, R2 ; /* 0x0000001902197210 */
/* 0x000fe20007ffe002 */
/*0a70*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x0041e8000c101904 */
/*0a80*/ STG.E [R10.64], R9 ; /* 0x000000090a007986 */
/* 0x0081e8000c101904 */
/*0a90*/ STG.E [R14.64], R13 ; /* 0x0000000d0e007986 */
/* 0x0101e8000c101904 */
/*0aa0*/ STG.E [R18.64], R17 ; /* 0x0000001112007986 */
/* 0x0201e4000c101904 */
/*0ab0*/ @P0 BRA 0x950 ; /* 0xfffffe9000000947 */
/* 0x001fea000383ffff */
/*0ac0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05270 */
/*0ad0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0ae0*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x002fe200000001ff */
/*0af0*/ MOV R6, 0x8 ; /* 0x0000000800067802 */
/* 0x000fca0000000f00 */
/*0b00*/ IMAD.WIDE R6, R25, R6, c[0x0][0x170] ; /* 0x00005c0019067625 */
/* 0x000fc800078e0206 */
/*0b10*/ IMAD.WIDE R4, R25, R4, c[0x0][0x178] ; /* 0x00005e0019047625 */
/* 0x000fc800078e0204 */
/*0b20*/ LDG.E.CONSTANT R3, [R6.64] ; /* 0x0000000406037981 */
/* 0x0000a2000c1e9900 */
/*0b30*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fc80007ffe0ff */
/*0b40*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*0b50*/ IMAD.WIDE R6, R2.reuse, 0x8, R6 ; /* 0x0000000802067825 */
/* 0x041fe200078e0206 */
/*0b60*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041e6000c101904 */
/*0b70*/ IMAD.WIDE R4, R2, 0x4, R4 ; /* 0x0000000402047825 */
/* 0x001fd000078e0204 */
/*0b80*/ @P0 BRA 0xb20 ; /* 0xffffff9000000947 */
/* 0x000fea000383ffff */
/*0b90*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0ba0*/ BRA 0xba0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : data_transfer_real_cplx
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R0 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x164], PT ; /* 0x0000590003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R2, R2, c[0x0][0x0], R5 ; /* 0x0000000002027a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R2, c[0x0][0x160], P0 ; /* 0x0000580002007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0c */
/* 0x000fda0003f05270 */
/*00b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff057624 */
/* 0x000fe200078e00ff */
/*00d0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*00e0*/ IMAD R2, R2, c[0x0][0x164], R3 ; /* 0x0000590002027a24 */
/* 0x000fe200078e0203 */
/*00f0*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe40008000000 */
/*0100*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe20003f04070 */
/*0110*/ IMAD R7, R2, c[0x0][0x168], RZ ; /* 0x00005a0002077a24 */
/* 0x000fe200078e02ff */
/*0120*/ SHF.R.S32.HI R0, RZ, 0x1f, R5 ; /* 0x0000001fff007819 */
/* 0x000fe20000011405 */
/*0130*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0140*/ ISETP.GT.U32.AND.EX P0, PT, R0.reuse, RZ, PT, P0 ; /* 0x000000ff0000720c */
/* 0x040fe40003f04100 */
/*0150*/ SHF.R.S32.HI R6, RZ, 0x1f, R7 ; /* 0x0000001fff067819 */
/* 0x000fe40000011407 */
/*0160*/ SEL R5, R5, 0x1, P0 ; /* 0x0000000105057807 */
/* 0x000fe40000000000 */
/*0170*/ SEL R19, R0, RZ, P0 ; /* 0x000000ff00137207 */
/* 0x000fe40000000000 */
/*0180*/ IADD3 R4, P2, R5.reuse, -0x1, RZ ; /* 0xffffffff05047810 */
/* 0x040fe40007f5e0ff */
/*0190*/ LOP3.LUT R0, R5, 0x3, RZ, 0xc0, !PT ; /* 0x0000000305007812 */
/* 0x000fc400078ec0ff */
/*01a0*/ ISETP.GE.U32.AND P1, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f26070 */
/*01b0*/ IADD3.X R4, R19, -0x1, RZ, P2, !PT ; /* 0xffffffff13047810 */
/* 0x000fe400017fe4ff */
/*01c0*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe40003f05070 */
/*01d0*/ ISETP.GE.U32.AND.EX P1, PT, R4, RZ, PT, P1 ; /* 0x000000ff0400720c */
/* 0x000fe40003f26110 */
/*01e0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd60003f05300 */
/*01f0*/ @!P1 BRA 0x430 ; /* 0x0000023000009947 */
/* 0x000fea0003800000 */
/*0200*/ LEA R16, P3, R7.reuse, c[0x0][0x178], 0x3 ; /* 0x00005e0007107a11 */
/* 0x040fe200078618ff */
/*0210*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0220*/ IADD3 R18, P1, R0, -R5, RZ ; /* 0x8000000500127210 */
/* 0x000fe20007f3e0ff */
/*0230*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0240*/ IADD3 R16, P4, R16, 0x10, RZ ; /* 0x0000001010107810 */
/* 0x000fe40007f9e0ff */
/*0250*/ LEA.HI.X R17, R7.reuse, c[0x0][0x17c], R6, 0x3, P3 ; /* 0x00005f0007117a11 */
/* 0x040fe200018f1c06 */
/*0260*/ IMAD.X R19, RZ, RZ, ~R19, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0e13 */
/*0270*/ LEA R2, P2, R7, c[0x0][0x170], 0x2 ; /* 0x00005c0007027a11 */
/* 0x000fc600078410ff */
/*0280*/ IMAD.X R17, RZ, RZ, R17, P4 ; /* 0x000000ffff117224 */
/* 0x000fe200020e0611 */
/*0290*/ LEA.HI.X R3, R7, c[0x0][0x174], R6, 0x2, P2 ; /* 0x00005d0007037a11 */
/* 0x000fca00010f1406 */
/*02a0*/ LDG.E.CONSTANT R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x0010a8000c1e9900 */
/*02b0*/ LDG.E.CONSTANT R10, [R2.64+0x4] ; /* 0x00000406020a7981 */
/* 0x0000e8000c1e9900 */
/*02c0*/ LDG.E.CONSTANT R12, [R2.64+0x8] ; /* 0x00000806020c7981 */
/* 0x000128000c1e9900 */
/*02d0*/ LDG.E.CONSTANT R14, [R2.64+0xc] ; /* 0x00000c06020e7981 */
/* 0x000162000c1e9900 */
/*02e0*/ UIADD3 UR4, UP0, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fe2000ff1e03f */
/*02f0*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fc400078e0010 */
/*0300*/ IMAD.MOV.U32 R5, RZ, RZ, R17 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0011 */
/*0310*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0320*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0330*/ IADD3 R16, P2, R18, UR4, RZ ; /* 0x0000000412107c10 */
/* 0x000fe2000ff5e0ff */
/*0340*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e00ff */
/*0350*/ IMAD.MOV.U32 R13, RZ, RZ, RZ ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e00ff */
/*0360*/ ISETP.NE.U32.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe20003f25070 */
/*0370*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0380*/ IADD3.X R16, R19, UR5, RZ, P2, !PT ; /* 0x0000000513107c10 */
/* 0x000fe400097fe4ff */
/*0390*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x001fc40007f5e0ff */
/*03a0*/ ISETP.NE.AND.EX P1, PT, R16, RZ, PT, P1 ; /* 0x000000ff1000720c */
/* 0x000fe40003f25310 */
/*03b0*/ IADD3 R16, P3, R4, 0x20, RZ ; /* 0x0000002004107810 */
/* 0x000fe20007f7e0ff */
/*03c0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fc800010e0603 */
/*03d0*/ IMAD.X R17, RZ, RZ, R5, P3 ; /* 0x000000ffff117224 */
/* 0x000fe200018e0605 */
/*03e0*/ STG.E.64 [R4.64+-0x10], R8 ; /* 0xfffff00804007986 */
/* 0x0041e8000c101b06 */
/*03f0*/ STG.E.64 [R4.64+-0x8], R10 ; /* 0xfffff80a04007986 */
/* 0x0081e8000c101b06 */
/*0400*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0101e8000c101b06 */
/*0410*/ STG.E.64 [R4.64+0x8], R14 ; /* 0x0000080e04007986 */
/* 0x0201e2000c101b06 */
/*0420*/ @P1 BRA 0x2a0 ; /* 0xfffffe7000001947 */
/* 0x000fea000383ffff */
/*0430*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R8, P0, R7, UR4, RZ ; /* 0x0000000407087c10 */
/* 0x001fe4000ff1e0ff */
/*0450*/ IADD3 R0, P3, RZ, -R0, RZ ; /* 0x80000000ff007210 */
/* 0x000fc40007f7e0ff */
/*0460*/ LEA R9, P1, R8, c[0x0][0x178], 0x3 ; /* 0x00005e0008097a11 */
/* 0x000fe400078218ff */
/*0470*/ IADD3.X R3, R6, UR5, RZ, P0, !PT ; /* 0x0000000506037c10 */
/* 0x000fe200087fe4ff */
/*0480*/ IMAD.X R6, RZ, RZ, -0x1, P3 ; /* 0xffffffffff067424 */
/* 0x000fe200018e06ff */
/*0490*/ LEA R7, P2, R8.reuse, c[0x0][0x170], 0x2 ; /* 0x00005c0008077a11 */
/* 0x040fe400078410ff */
/*04a0*/ LEA.HI.X R10, R8.reuse, c[0x0][0x17c], R3.reuse, 0x3, P1 ; /* 0x00005f00080a7a11 */
/* 0x140fe400008f1c03 */
/*04b0*/ LEA.HI.X R8, R8, c[0x0][0x174], R3, 0x2, P2 ; /* 0x00005d0008087a11 */
/* 0x000fc600010f1403 */
/*04c0*/ IMAD.MOV.U32 R2, RZ, RZ, R7 ; /* 0x000000ffff027224 */
/* 0x001fe400078e0007 */
/*04d0*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0008 */
/*04e0*/ LDG.E.CONSTANT R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x0000a2000c1e9900 */
/*04f0*/ IADD3 R0, P0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007f1e0ff */
/*0500*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0510*/ IADD3 R7, P2, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc60007f5e0ff */
/*0520*/ IMAD.X R6, RZ, RZ, R6, P0 ; /* 0x000000ffff067224 */
/* 0x000fe200000e0606 */
/*0530*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05070 */
/*0540*/ IMAD.X R8, RZ, RZ, R8, P2 ; /* 0x000000ffff087224 */
/* 0x000fe400010e0608 */
/*0550*/ IMAD.MOV.U32 R2, RZ, RZ, R9 ; /* 0x000000ffff027224 */
/* 0x001fe200078e0009 */
/*0560*/ ISETP.NE.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fe20003f05300 */
/*0570*/ IMAD.MOV.U32 R3, RZ, RZ, R10 ; /* 0x000000ffff037224 */
/* 0x000fe200078e000a */
/*0580*/ IADD3 R9, P1, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fca0007f3e0ff */
/*0590*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fe200008e060a */
/*05a0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0041ea000c101b06 */
/*05b0*/ @P0 BRA 0x4c0 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*05c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*05d0*/ BRA 0x5d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cufft.h>
#include <cuda_profiler_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
extern "C"
__global__
void data_transfer_real_cplx(
int nx
, int ny
, int nz
, float * in
, cufftComplex * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
for (std::size_t kz = 0; kz < nz; kz++)
{
out[(kx*ny + ky)*nz + kz].x = ldg(&in[(kx*ny + ky)*nz + kz]);
out[(kx*ny + ky)*nz + kz].y = 0;
}
}
}
extern "C"
__global__
void data_transfer_cplx_real(
int nx
, int ny
, int nz
, cufftComplex * in
, float * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
for (int i = 0; i < nz; i++, k_1 += nx*ny)
{
out[k_1] = ldg(&in[k_1]).x;
}
}
} | .file "tmpxft_000bca14_00000000-6_cu_data_transfer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2
.type _Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2, @function
_Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2:
.LFB2105:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq data_transfer_real_cplx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2105:
.size _Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2, .-_Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2
.globl data_transfer_real_cplx
.type data_transfer_real_cplx, @function
data_transfer_real_cplx:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size data_transfer_real_cplx, .-data_transfer_real_cplx
.globl _Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf
.type _Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf, @function
_Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf:
.LFB2107:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq data_transfer_cplx_real(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2107:
.size _Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf, .-_Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf
.globl data_transfer_cplx_real
.type data_transfer_cplx_real, @function
data_transfer_cplx_real:
.LFB2108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size data_transfer_cplx_real, .-data_transfer_cplx_real
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "data_transfer_cplx_real"
.LC1:
.string "data_transfer_real_cplx"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2110:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq data_transfer_cplx_real(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq data_transfer_real_cplx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cufft.h>
#include <cuda_profiler_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
extern "C"
__global__
void data_transfer_real_cplx(
int nx
, int ny
, int nz
, float * in
, cufftComplex * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
for (std::size_t kz = 0; kz < nz; kz++)
{
out[(kx*ny + ky)*nz + kz].x = ldg(&in[(kx*ny + ky)*nz + kz]);
out[(kx*ny + ky)*nz + kz].y = 0;
}
}
}
extern "C"
__global__
void data_transfer_cplx_real(
int nx
, int ny
, int nz
, cufftComplex * in
, float * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
for (int i = 0; i < nz; i++, k_1 += nx*ny)
{
out[k_1] = ldg(&in[k_1]).x;
}
}
} | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
extern "C"
__global__
void data_transfer_real_cplx(
int nx
, int ny
, int nz
, float * in
, hipfftComplex * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
for (std::size_t kz = 0; kz < nz; kz++)
{
out[(kx*ny + ky)*nz + kz].x = ldg(&in[(kx*ny + ky)*nz + kz]);
out[(kx*ny + ky)*nz + kz].y = 0;
}
}
}
extern "C"
__global__
void data_transfer_cplx_real(
int nx
, int ny
, int nz
, hipfftComplex * in
, float * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
for (int i = 0; i < nz; i++, k_1 += nx*ny)
{
out[k_1] = ldg(&in[k_1]).x;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
extern "C"
__global__
void data_transfer_real_cplx(
int nx
, int ny
, int nz
, float * in
, hipfftComplex * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
for (std::size_t kz = 0; kz < nz; kz++)
{
out[(kx*ny + ky)*nz + kz].x = ldg(&in[(kx*ny + ky)*nz + kz]);
out[(kx*ny + ky)*nz + kz].y = 0;
}
}
}
extern "C"
__global__
void data_transfer_cplx_real(
int nx
, int ny
, int nz
, hipfftComplex * in
, float * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
for (int i = 0; i < nz; i++, k_1 += nx*ny)
{
out[k_1] = ldg(&in[k_1]).x;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected data_transfer_real_cplx
.globl data_transfer_real_cplx
.p2align 8
.type data_transfer_real_cplx,@function
data_transfer_real_cplx:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s5, s4, 0xffff
s_lshr_b32 s4, s4, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_4
v_mad_u64_u32 v[2:3], null, v0, s3, v[1:2]
s_load_b128 s[4:7], s[0:1], 0x10
v_mov_b32_e32 v4, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v2, s2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[0:1]
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s6
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB0_3:
global_load_b32 v5, v[0:1], off
v_add_co_u32 v0, vcc_lo, v0, 4
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_add_u32 s2, s2, -1
s_addc_u32 s3, s3, -1
s_waitcnt vmcnt(0)
s_clause 0x1
global_store_b32 v[2:3], v5, off offset:-4
global_store_b32 v[2:3], v4, off
v_add_co_u32 v2, vcc_lo, v2, 8
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_cmp_lg_u64 s[2:3], 0
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel data_transfer_real_cplx
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size data_transfer_real_cplx, .Lfunc_end0-data_transfer_real_cplx
.section .AMDGPU.csdata,"",@progbits
.text
.protected data_transfer_cplx_real
.globl data_transfer_cplx_real
.p2align 8
.type data_transfer_cplx_real,@function
data_transfer_cplx_real:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
v_cmp_gt_i32_e32 vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s5, v1
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s6, 0
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB1_3
s_load_b128 s[0:3], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
s_mul_i32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_ashr_i32 s5, s4, 31
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 3, v[2:3]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_lshl_b64 s[0:1], s[4:5], 3
s_lshl_b64 s[2:3], s[4:5], 2
.LBB1_2:
global_load_b32 v4, v[0:1], off
v_add_co_u32 v0, vcc_lo, v0, s0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_i32 s6, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s6, 0
s_waitcnt vmcnt(0)
global_store_b32 v[2:3], v4, off
v_add_co_u32 v2, vcc_lo, v2, s2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
s_cbranch_scc1 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel data_transfer_cplx_real
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size data_transfer_cplx_real, .Lfunc_end1-data_transfer_cplx_real
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: data_transfer_real_cplx
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: data_transfer_real_cplx.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: data_transfer_cplx_real
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: data_transfer_cplx_real.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <hipfft/hipfft.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>
template<typename T>
__device__ __forceinline__ T ldg(const T* ptr) {
#if __CUDA_ARCH__ >= 350
return __ldg(ptr);
#else
return *ptr;
#endif
}
extern "C"
__global__
void data_transfer_real_cplx(
int nx
, int ny
, int nz
, float * in
, hipfftComplex * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
for (std::size_t kz = 0; kz < nz; kz++)
{
out[(kx*ny + ky)*nz + kz].x = ldg(&in[(kx*ny + ky)*nz + kz]);
out[(kx*ny + ky)*nz + kz].y = 0;
}
}
}
extern "C"
__global__
void data_transfer_cplx_real(
int nx
, int ny
, int nz
, hipfftComplex * in
, float * out
)
{
int kx = blockIdx.x*blockDim.x + threadIdx.x;
int ky = blockIdx.y*blockDim.y + threadIdx.y;
if (kx < nx && ky < ny)
{
int k_1 = nx*ky + kx;
for (int i = 0; i < nz; i++, k_1 += nx*ny)
{
out[k_1] = ldg(&in[k_1]).x;
}
}
} | .text
.file "cu_data_transfer.hip"
.globl __device_stub__data_transfer_real_cplx # -- Begin function __device_stub__data_transfer_real_cplx
.p2align 4, 0x90
.type __device_stub__data_transfer_real_cplx,@function
__device_stub__data_transfer_real_cplx: # @__device_stub__data_transfer_real_cplx
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $data_transfer_real_cplx, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__data_transfer_real_cplx, .Lfunc_end0-__device_stub__data_transfer_real_cplx
.cfi_endproc
# -- End function
.globl __device_stub__data_transfer_cplx_real # -- Begin function __device_stub__data_transfer_cplx_real
.p2align 4, 0x90
.type __device_stub__data_transfer_cplx_real,@function
__device_stub__data_transfer_cplx_real: # @__device_stub__data_transfer_cplx_real
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $data_transfer_cplx_real, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__data_transfer_cplx_real, .Lfunc_end1-__device_stub__data_transfer_cplx_real
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $data_transfer_real_cplx, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $data_transfer_cplx_real, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type data_transfer_real_cplx,@object # @data_transfer_real_cplx
.section .rodata,"a",@progbits
.globl data_transfer_real_cplx
.p2align 3, 0x0
data_transfer_real_cplx:
.quad __device_stub__data_transfer_real_cplx
.size data_transfer_real_cplx, 8
.type data_transfer_cplx_real,@object # @data_transfer_cplx_real
.globl data_transfer_cplx_real
.p2align 3, 0x0
data_transfer_cplx_real:
.quad __device_stub__data_transfer_cplx_real
.size data_transfer_cplx_real, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "data_transfer_real_cplx"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "data_transfer_cplx_real"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__data_transfer_real_cplx
.addrsig_sym __device_stub__data_transfer_cplx_real
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym data_transfer_real_cplx
.addrsig_sym data_transfer_cplx_real
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000bca14_00000000-6_cu_data_transfer.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2
.type _Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2, @function
_Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2:
.LFB2105:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq data_transfer_real_cplx(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2105:
.size _Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2, .-_Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2
.globl data_transfer_real_cplx
.type data_transfer_real_cplx, @function
data_transfer_real_cplx:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z23data_transfer_real_cplxiiiPfP6float2iiiPfP6float2
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size data_transfer_real_cplx, .-data_transfer_real_cplx
.globl _Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf
.type _Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf, @function
_Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf:
.LFB2107:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq data_transfer_cplx_real(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2107:
.size _Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf, .-_Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf
.globl data_transfer_cplx_real
.type data_transfer_cplx_real, @function
data_transfer_cplx_real:
.LFB2108:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z23data_transfer_cplx_realiiiP6float2PfiiiP6float2Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size data_transfer_cplx_real, .-data_transfer_cplx_real
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "data_transfer_cplx_real"
.LC1:
.string "data_transfer_real_cplx"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2110:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq data_transfer_cplx_real(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq data_transfer_real_cplx(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2110:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cu_data_transfer.hip"
.globl __device_stub__data_transfer_real_cplx # -- Begin function __device_stub__data_transfer_real_cplx
.p2align 4, 0x90
.type __device_stub__data_transfer_real_cplx,@function
__device_stub__data_transfer_real_cplx: # @__device_stub__data_transfer_real_cplx
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $data_transfer_real_cplx, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__data_transfer_real_cplx, .Lfunc_end0-__device_stub__data_transfer_real_cplx
.cfi_endproc
# -- End function
.globl __device_stub__data_transfer_cplx_real # -- Begin function __device_stub__data_transfer_cplx_real
.p2align 4, 0x90
.type __device_stub__data_transfer_cplx_real,@function
__device_stub__data_transfer_cplx_real: # @__device_stub__data_transfer_cplx_real
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movl %edx, 4(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $data_transfer_cplx_real, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size __device_stub__data_transfer_cplx_real, .Lfunc_end1-__device_stub__data_transfer_cplx_real
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $data_transfer_real_cplx, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $data_transfer_cplx_real, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type data_transfer_real_cplx,@object # @data_transfer_real_cplx
.section .rodata,"a",@progbits
.globl data_transfer_real_cplx
.p2align 3, 0x0
data_transfer_real_cplx:
.quad __device_stub__data_transfer_real_cplx
.size data_transfer_real_cplx, 8
.type data_transfer_cplx_real,@object # @data_transfer_cplx_real
.globl data_transfer_cplx_real
.p2align 3, 0x0
data_transfer_cplx_real:
.quad __device_stub__data_transfer_cplx_real
.size data_transfer_cplx_real, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "data_transfer_real_cplx"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "data_transfer_cplx_real"
.size .L__unnamed_2, 24
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__data_transfer_real_cplx
.addrsig_sym __device_stub__data_transfer_cplx_real
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym data_transfer_real_cplx
.addrsig_sym data_transfer_cplx_real
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ExpProbPolynomProbsImpl( const float* features, int batchSize, const int* splits, const float* conditions, const int* polynomOffsets, int polynomCount, float lambda, float* probs) {
if (threadIdx.x < batchSize) {
int polynomId = blockIdx.x;
features += threadIdx.x;
probs += threadIdx.x;
while (polynomId < polynomCount) {
int offset = polynomOffsets[polynomId];
int nextOffset = polynomOffsets[polynomId + 1];
const int depth = nextOffset - offset;
float logProb = 0;
bool zeroProb = false;
for (int i = 0; i < depth; ++i) {
if (zeroProb) {
continue;
}
const int f = __ldg(splits + offset + i);
const float c = __ldg(conditions + offset + i);
const float x = __ldg(features + f * batchSize);
const float val = -lambda * x;
const float expVal = 1.0f - expf(val);
if (isfinite(log(expVal))) {
logProb += log(expVal);
} else {
zeroProb = true;
}
}
float prob = 0.0f;
if (!zeroProb) {
prob = expf(logProb);
}
probs[polynomId * batchSize] = prob;
polynomId += gridDim.x;
}
}
} | code for sm_80
Function : _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0050*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x188], PT ; /* 0x0000620002007a0c */
/* 0x001fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE R8, R2, R9, c[0x0][0x180] ; /* 0x0000600002087625 */
/* 0x000fca00078e0209 */
/*00a0*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x001ea8000c1e1900 */
/*00b0*/ LDG.E R11, [R8.64+0x4] ; /* 0x00000404080b7981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2e170 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GT.AND P0, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x004fda0003f04270 */
/*0100*/ @!P0 BRA 0xcd0 ; /* 0x00000bc000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.IADD R8, R11.reuse, 0x1, -R4.reuse ; /* 0x000000010b087824 */
/* 0x140fe200078e0a04 */
/*0130*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2e170 */
/*0140*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0150*/ ISETP.NE.AND P0, PT, R11, R5, PT ; /* 0x000000050b00720c */
/* 0x000fe40003f05270 */
/*0160*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*0170*/ PRMT R10, RZ, 0x7610, R10 ; /* 0x00007610ff0a7816 */
/* 0x000fe4000000000a */
/*0180*/ LOP3.LUT R9, R8, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108097812 */
/* 0x000fce00078ec0ff */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2e170 */
/*01b0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*01c0*/ IADD3 R8, R8, -R9, RZ ; /* 0x8000000908087210 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PRMT R10, RZ, 0x7610, R10 ; /* 0x00007610ff0a7816 */
/* 0x000fc8000000000a */
/*01e0*/ IADD3 R8, R8, -0x2, RZ ; /* 0xfffffffe08087810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ BSSY B0, 0x570 ; /* 0x0000037000007945 */
/* 0x000fe60003800000 */
/*0200*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0210*/ @P1 BRA 0x560 ; /* 0x0000034000001947 */
/* 0x000fee0003800000 */
/*0220*/ IADD3 R11, P1, R4, R6, RZ ; /* 0x00000006040b7210 */
/* 0x000fc80007f3e0ff */
/*0230*/ LEA.HI.X.SX32 R12, R6, R5, 0x1, P1 ; /* 0x00000005060c7211 */
/* 0x000fe400008f0eff */
/*0240*/ LEA R10, P1, R11, c[0x0][0x170], 0x2 ; /* 0x00005c000b0a7a11 */
/* 0x000fc800078210ff */
/*0250*/ LEA.HI.X R11, R11, c[0x0][0x174], R12, 0x2, P1 ; /* 0x00005d000b0b7a11 */
/* 0x000fca00008f140c */
/*0260*/ LDG.E.CONSTANT R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e9900 */
/*0270*/ IMAD R13, R10, c[0x0][0x168], RZ ; /* 0x00005a000a0d7a24 */
/* 0x004fca00078e02ff */
/*0280*/ IADD3 R14, P1, R13, R0, RZ ; /* 0x000000000d0e7210 */
/* 0x000fc80007f3e0ff */
/*0290*/ LEA.HI.X.SX32 R13, R13, RZ, 0x1, P1 ; /* 0x000000ff0d0d7211 */
/* 0x000fe400008f0eff */
/*02a0*/ LEA R12, P1, R14, c[0x0][0x160], 0x2 ; /* 0x000058000e0c7a11 */
/* 0x000fc800078210ff */
/*02b0*/ LEA.HI.X R13, R14, c[0x0][0x164], R13, 0x2, P1 ; /* 0x000059000e0d7a11 */
/* 0x000fca00008f140d */
/*02c0*/ LDG.E.CONSTANT R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e9900 */
/*02d0*/ HFMA2.MMA R16, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff107435 */
/* 0x000fe200000001ff */
/*02e0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff0f7424 */
/* 0x000fe400078e00ff */
/*02f0*/ FMUL R14, R12, c[0x0][0x18c] ; /* 0x000063000c0e7a20 */
/* 0x004fc80000400000 */
/*0300*/ FFMA.SAT R15, -R14, R15, 0.5 ; /* 0x3f0000000e0f7423 */
/* 0x000fc8000000210f */
/*0310*/ FFMA.RM R15, R15, R16, 12582913 ; /* 0x4b4000010f0f7423 */
/* 0x000fc80000004010 */
/*0320*/ FADD R11, R15.reuse, -12583039 ; /* 0xcb40007f0f0b7421 */
/* 0x040fe40000000000 */
/*0330*/ IMAD.SHL.U32 R10, R15, 0x800000, RZ ; /* 0x008000000f0a7824 */
/* 0x000fe400078e00ff */
/*0340*/ FFMA R11, -R14.reuse, 1.4426950216293334961, -R11 ; /* 0x3fb8aa3b0e0b7823 */
/* 0x040fe4000000090b */
/*0350*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3e055027 ; /* 0x3e055027ff0f7424 */
/* 0x000fe400078e00ff */
/*0360*/ FFMA R11, -R14, 1.925963033500011079e-08, R11 ; /* 0x32a570600e0b7823 */
/* 0x000fcc000000010b */
/*0370*/ MUFU.EX2 R11, R11 ; /* 0x0000000b000b7308 */
/* 0x000e240000000800 */
/*0380*/ FFMA R10, R10, -R11, 1 ; /* 0x3f8000000a0a7423 */
/* 0x001fca000000080b */
/*0390*/ FSETP.GEU.AND P1, PT, R10, 1.175494350822287508e-38, PT ; /* 0x008000000a00780b */
/* 0x000fc80003f2e000 */
/*03a0*/ FSEL R11, RZ, -23, P1 ; /* 0xc1b80000ff0b7808 */
/* 0x000fd20000800000 */
/*03b0*/ @!P1 FMUL R10, R10, 8388608 ; /* 0x4b0000000a0a9820 */
/* 0x000fca0000400000 */
/*03c0*/ IADD3 R12, R10.reuse, -0x3f2aaaab, RZ ; /* 0xc0d555550a0c7810 */
/* 0x040fe40007ffe0ff */
/*03d0*/ ISETP.GE.U32.AND P2, PT, R10, 0x7f800000, PT ; /* 0x7f8000000a00780c */
/* 0x000fe40003f46070 */
/*03e0*/ LOP3.LUT R13, R12, 0xff800000, RZ, 0xc0, !PT ; /* 0xff8000000c0d7812 */
/* 0x000fe400078ec0ff */
/*03f0*/ FSETP.NEU.AND P1, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x040fe40003f2d000 */
/*0400*/ IADD3 R12, R10, -R13, RZ ; /* 0x8000000d0a0c7210 */
/* 0x000fca0007ffe0ff */
/*0410*/ FADD R14, R12, -1 ; /* 0xbf8000000c0e7421 */
/* 0x000fe40000000000 */
/*0420*/ I2F R12, R13 ; /* 0x0000000d000c7306 */
/* 0x000e240000201400 */
/*0430*/ FFMA R15, R14, -R15, 0.14084610342979431152 ; /* 0x3e1039f60e0f7423 */
/* 0x000fc8000000080f */
/*0440*/ FFMA R15, R14, R15, -0.12148627638816833496 ; /* 0xbdf8cdcc0e0f7423 */
/* 0x000fc8000000000f */
/*0450*/ FFMA R15, R14, R15, 0.13980610668659210205 ; /* 0x3e0f29550e0f7423 */
/* 0x000fc8000000000f */
/*0460*/ FFMA R15, R14, R15, -0.16684235632419586182 ; /* 0xbe2ad8b90e0f7423 */
/* 0x000fe4000000000f */
/*0470*/ FFMA R11, R12, 1.1920928955078125e-07, R11 ; /* 0x340000000c0b7823 */
/* 0x001fe4000000000b */
/*0480*/ FFMA R15, R14, R15, 0.20012299716472625732 ; /* 0x3e4ced0b0e0f7423 */
/* 0x000fc8000000000f */
/*0490*/ FFMA R15, R14, R15, -0.24999669194221496582 ; /* 0xbe7fff220e0f7423 */
/* 0x000fc8000000000f */
/*04a0*/ FFMA R15, R14, R15, 0.33333182334899902344 ; /* 0x3eaaaa780e0f7423 */
/* 0x000fc8000000000f */
/*04b0*/ FFMA R15, R14, R15, -0.5 ; /* 0xbf0000000e0f7423 */
/* 0x000fc8000000000f */
/*04c0*/ FMUL R15, R14, R15 ; /* 0x0000000f0e0f7220 */
/* 0x000fc80000400000 */
/*04d0*/ FFMA R14, R14, R15, R14 ; /* 0x0000000f0e0e7223 */
/* 0x000fe2000000000e */
/*04e0*/ @P2 MOV R15, 0x7f800000 ; /* 0x7f800000000f2802 */
/* 0x000fc60000000f00 */
/*04f0*/ FFMA R11, R11, 0.69314718246459960938, R14 ; /* 0x3f3172180b0b7823 */
/* 0x000fe4000000000e */
/*0500*/ @P2 FFMA R11, R10, R15, +INF ; /* 0x7f8000000a0b2423 */
/* 0x000fca000000000f */
/*0510*/ FSEL R10, R11, -INF , P1 ; /* 0xff8000000b0a7808 */
/* 0x000fc80000800000 */
/*0520*/ FSETP.GEU.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fc80003f2e200 */
/*0530*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fd20004800000 */
/*0540*/ @!P1 FADD R7, R7, R10.reuse ; /* 0x0000000a07079221 */
/* 0x100fe20000000000 */
/*0550*/ PRMT R10, R11, 0x7610, R10 ; /* 0x000076100b0a7816 */
/* 0x000fe4000000000a */
/*0560*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0570*/ LOP3.LUT P1, RZ, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0aff7812 */
/* 0x000fe2000782c0ff */
/*0580*/ BSSY B0, 0x900 ; /* 0x0000037000007945 */
/* 0x000fd80003800000 */
/*0590*/ @P1 BRA 0x8f0 ; /* 0x0000035000001947 */
/* 0x000fea0003800000 */
/*05a0*/ IADD3 R10, R6, 0x1, RZ ; /* 0x00000001060a7810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ IADD3 R11, P1, R4, R10, RZ ; /* 0x0000000a040b7210 */
/* 0x000fc80007f3e0ff */
/*05c0*/ LEA.HI.X.SX32 R12, R10, R5, 0x1, P1 ; /* 0x000000050a0c7211 */
/* 0x000fe400008f0eff */
/*05d0*/ LEA R10, P1, R11, c[0x0][0x170], 0x2 ; /* 0x00005c000b0a7a11 */
/* 0x000fc800078210ff */
/*05e0*/ LEA.HI.X R11, R11, c[0x0][0x174], R12, 0x2, P1 ; /* 0x00005d000b0b7a11 */
/* 0x000fca00008f140c */
/*05f0*/ LDG.E.CONSTANT R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e9900 */
/*0600*/ IMAD R13, R10, c[0x0][0x168], RZ ; /* 0x00005a000a0d7a24 */
/* 0x004fca00078e02ff */
/*0610*/ IADD3 R14, P1, R13, R0, RZ ; /* 0x000000000d0e7210 */
/* 0x000fc80007f3e0ff */
/*0620*/ LEA.HI.X.SX32 R13, R13, RZ, 0x1, P1 ; /* 0x000000ff0d0d7211 */
/* 0x000fe400008f0eff */
/*0630*/ LEA R12, P1, R14, c[0x0][0x160], 0x2 ; /* 0x000058000e0c7a11 */
/* 0x000fc800078210ff */
/*0640*/ LEA.HI.X R13, R14, c[0x0][0x164], R13, 0x2, P1 ; /* 0x000059000e0d7a11 */
/* 0x000fca00008f140d */
/*0650*/ LDG.E.CONSTANT R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e9900 */
/*0660*/ HFMA2.MMA R16, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff107435 */
/* 0x000fe200000001ff */
/*0670*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff0f7424 */
/* 0x000fe400078e00ff */
/*0680*/ FMUL R14, R12, c[0x0][0x18c] ; /* 0x000063000c0e7a20 */
/* 0x004fc80000400000 */
/*0690*/ FFMA.SAT R15, -R14, R15, 0.5 ; /* 0x3f0000000e0f7423 */
/* 0x000fc8000000210f */
/*06a0*/ FFMA.RM R15, R15, R16, 12582913 ; /* 0x4b4000010f0f7423 */
/* 0x000fc80000004010 */
/*06b0*/ FADD R11, R15.reuse, -12583039 ; /* 0xcb40007f0f0b7421 */
/* 0x040fe40000000000 */
/*06c0*/ IMAD.SHL.U32 R10, R15, 0x800000, RZ ; /* 0x008000000f0a7824 */
/* 0x000fe400078e00ff */
/*06d0*/ FFMA R11, -R14.reuse, 1.4426950216293334961, -R11 ; /* 0x3fb8aa3b0e0b7823 */
/* 0x040fe4000000090b */
/*06e0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3e055027 ; /* 0x3e055027ff0f7424 */
/* 0x000fe400078e00ff */
/*06f0*/ FFMA R11, -R14, 1.925963033500011079e-08, R11 ; /* 0x32a570600e0b7823 */
/* 0x000fcc000000010b */
/*0700*/ MUFU.EX2 R11, R11 ; /* 0x0000000b000b7308 */
/* 0x000e240000000800 */
/*0710*/ FFMA R10, R10, -R11, 1 ; /* 0x3f8000000a0a7423 */
/* 0x001fca000000080b */
/*0720*/ FSETP.GEU.AND P1, PT, R10, 1.175494350822287508e-38, PT ; /* 0x008000000a00780b */
/* 0x000fc80003f2e000 */
/*0730*/ FSEL R11, RZ, -23, P1 ; /* 0xc1b80000ff0b7808 */
/* 0x000fd20000800000 */
/*0740*/ @!P1 FMUL R10, R10, 8388608 ; /* 0x4b0000000a0a9820 */
/* 0x000fca0000400000 */
/*0750*/ IADD3 R12, R10.reuse, -0x3f2aaaab, RZ ; /* 0xc0d555550a0c7810 */
/* 0x040fe40007ffe0ff */
/*0760*/ ISETP.GE.U32.AND P2, PT, R10, 0x7f800000, PT ; /* 0x7f8000000a00780c */
/* 0x000fe40003f46070 */
/*0770*/ LOP3.LUT R13, R12, 0xff800000, RZ, 0xc0, !PT ; /* 0xff8000000c0d7812 */
/* 0x000fe400078ec0ff */
/*0780*/ FSETP.NEU.AND P1, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x040fe40003f2d000 */
/*0790*/ IADD3 R12, R10, -R13, RZ ; /* 0x8000000d0a0c7210 */
/* 0x000fca0007ffe0ff */
/*07a0*/ FADD R14, R12, -1 ; /* 0xbf8000000c0e7421 */
/* 0x000fe40000000000 */
/*07b0*/ I2F R12, R13 ; /* 0x0000000d000c7306 */
/* 0x000e240000201400 */
/*07c0*/ FFMA R15, R14, -R15, 0.14084610342979431152 ; /* 0x3e1039f60e0f7423 */
/* 0x000fc8000000080f */
/*07d0*/ FFMA R15, R14, R15, -0.12148627638816833496 ; /* 0xbdf8cdcc0e0f7423 */
/* 0x000fc8000000000f */
/*07e0*/ FFMA R15, R14, R15, 0.13980610668659210205 ; /* 0x3e0f29550e0f7423 */
/* 0x000fc8000000000f */
/*07f0*/ FFMA R15, R14, R15, -0.16684235632419586182 ; /* 0xbe2ad8b90e0f7423 */
/* 0x000fe4000000000f */
/*0800*/ FFMA R11, R12, 1.1920928955078125e-07, R11 ; /* 0x340000000c0b7823 */
/* 0x001fe4000000000b */
/*0810*/ FFMA R15, R14, R15, 0.20012299716472625732 ; /* 0x3e4ced0b0e0f7423 */
/* 0x000fc8000000000f */
/*0820*/ FFMA R15, R14, R15, -0.24999669194221496582 ; /* 0xbe7fff220e0f7423 */
/* 0x000fc8000000000f */
/*0830*/ FFMA R15, R14, R15, 0.33333182334899902344 ; /* 0x3eaaaa780e0f7423 */
/* 0x000fc8000000000f */
/*0840*/ FFMA R15, R14, R15, -0.5 ; /* 0xbf0000000e0f7423 */
/* 0x000fc8000000000f */
/*0850*/ FMUL R15, R14, R15 ; /* 0x0000000f0e0f7220 */
/* 0x000fc80000400000 */
/*0860*/ FFMA R14, R14, R15, R14 ; /* 0x0000000f0e0e7223 */
/* 0x000fe2000000000e */
/*0870*/ @P2 MOV R15, 0x7f800000 ; /* 0x7f800000000f2802 */
/* 0x000fc60000000f00 */
/*0880*/ FFMA R11, R11, 0.69314718246459960938, R14 ; /* 0x3f3172180b0b7823 */
/* 0x000fe4000000000e */
/*0890*/ @P2 FFMA R11, R10, R15, +INF ; /* 0x7f8000000a0b2423 */
/* 0x000fca000000000f */
/*08a0*/ FSEL R10, R11, -INF , P1 ; /* 0xff8000000b0a7808 */
/* 0x000fc80000800000 */
/*08b0*/ FSETP.GEU.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fc80003f2e200 */
/*08c0*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fd20004800000 */
/*08d0*/ @!P1 FADD R7, R7, R10.reuse ; /* 0x0000000a07079221 */
/* 0x100fe20000000000 */
/*08e0*/ PRMT R10, R11, 0x7610, R10 ; /* 0x000076100b0a7816 */
/* 0x000fe4000000000a */
/*08f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0900*/ LOP3.LUT P1, RZ, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0aff7812 */
/* 0x000fe4000782c0ff */
/*0910*/ IADD3 R6, R6, 0x2, RZ ; /* 0x0000000206067810 */
/* 0x000fe20007ffe0ff */
/*0920*/ @P0 BRA 0x1e0 ; /* 0xfffff8b000000947 */
/* 0x000fea000383ffff */
/*0930*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0940*/ @!P0 BRA 0xcd0 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0950*/ BSSY B0, 0xcc0 ; /* 0x0000036000007945 */
/* 0x000fe20003800000 */
/*0960*/ @P1 BRA 0xcb0 ; /* 0x0000034000001947 */
/* 0x000fea0003800000 */
/*0970*/ IADD3 R8, P0, R4, R6, RZ ; /* 0x0000000604087210 */
/* 0x000fc80007f1e0ff */
/*0980*/ LEA.HI.X.SX32 R5, R6, R5, 0x1, P0 ; /* 0x0000000506057211 */
/* 0x000fe400000f0eff */
/*0990*/ LEA R4, P0, R8, c[0x0][0x170], 0x2 ; /* 0x00005c0008047a11 */
/* 0x000fc800078010ff */
/*09a0*/ LEA.HI.X R5, R8, c[0x0][0x174], R5, 0x2, P0 ; /* 0x00005d0008057a11 */
/* 0x000fca00000f1405 */
/*09b0*/ LDG.E.CONSTANT R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e9900 */
/*09c0*/ IMAD R9, R4, c[0x0][0x168], RZ ; /* 0x00005a0004097a24 */
/* 0x004fca00078e02ff */
/*09d0*/ IADD3 R6, P0, R9, R0, RZ ; /* 0x0000000009067210 */
/* 0x000fc80007f1e0ff */
/*09e0*/ LEA.HI.X.SX32 R9, R9, RZ, 0x1, P0 ; /* 0x000000ff09097211 */
/* 0x000fe400000f0eff */
/*09f0*/ LEA R8, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006087a11 */
/* 0x000fc800078010ff */
/*0a00*/ LEA.HI.X R9, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006097a11 */
/* 0x000fca00000f1409 */
/*0a10*/ LDG.E.CONSTANT R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e9900 */
/*0a20*/ HFMA2.MMA R13, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff0d7435 */
/* 0x000fe200000001ff */
/*0a30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff0b7424 */
/* 0x000fe400078e00ff */
/*0a40*/ FMUL R6, R8, c[0x0][0x18c] ; /* 0x0000630008067a20 */
/* 0x004fc80000400000 */
/*0a50*/ FFMA.SAT R10, -R6, R11, 0.5 ; /* 0x3f000000060a7423 */
/* 0x000fe4000000210b */
/*0a60*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3e055027 ; /* 0x3e055027ff0b7424 */
/* 0x000fe400078e00ff */
/*0a70*/ FFMA.RM R10, R10, R13, 12582913 ; /* 0x4b4000010a0a7423 */
/* 0x000fc8000000400d */
/*0a80*/ FADD R5, R10.reuse, -12583039 ; /* 0xcb40007f0a057421 */
/* 0x040fe40000000000 */
/*0a90*/ IMAD.SHL.U32 R10, R10, 0x800000, RZ ; /* 0x008000000a0a7824 */
/* 0x000fe400078e00ff */
/*0aa0*/ FFMA R5, -R6, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b06057823 */
/* 0x000fc80000000905 */
/*0ab0*/ FFMA R5, -R6, 1.925963033500011079e-08, R5 ; /* 0x32a5706006057823 */
/* 0x000fcc0000000105 */
/*0ac0*/ MUFU.EX2 R5, R5 ; /* 0x0000000500057308 */
/* 0x000e240000000800 */
/*0ad0*/ FFMA R10, R10, -R5, 1 ; /* 0x3f8000000a0a7423 */
/* 0x001fca0000000805 */
/*0ae0*/ FSETP.GEU.AND P0, PT, R10, 1.175494350822287508e-38, PT ; /* 0x008000000a00780b */
/* 0x000fda0003f0e000 */
/*0af0*/ @!P0 FMUL R10, R10, 8388608 ; /* 0x4b0000000a0a8820 */
/* 0x000fca0000400000 */
/*0b00*/ IADD3 R4, R10.reuse, -0x3f2aaaab, RZ ; /* 0xc0d555550a047810 */
/* 0x040fe40007ffe0ff */
/*0b10*/ ISETP.GE.U32.AND P1, PT, R10, 0x7f800000, PT ; /* 0x7f8000000a00780c */
/* 0x000fe40003f26070 */
/*0b20*/ LOP3.LUT R9, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004097812 */
/* 0x000fc800078ec0ff */
/*0b30*/ IADD3 R4, R10, -R9, RZ ; /* 0x800000090a047210 */
/* 0x000fe40007ffe0ff */
/*0b40*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000e260000201400 */
/*0b50*/ FADD R6, R4, -1 ; /* 0xbf80000004067421 */
/* 0x000fe20000000000 */
/*0b60*/ FSEL R4, RZ, -23, P0 ; /* 0xc1b80000ff047808 */
/* 0x000fe40000000000 */
/*0b70*/ @P1 MOV R5, 0x7f800000 ; /* 0x7f80000000051802 */
/* 0x000fe20000000f00 */
/*0b80*/ FFMA R11, R6, -R11, 0.14084610342979431152 ; /* 0x3e1039f6060b7423 */
/* 0x000fe2000000080b */
/*0b90*/ FSETP.NEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fc60003f0d000 */
/*0ba0*/ FFMA R11, R6, R11, -0.12148627638816833496 ; /* 0xbdf8cdcc060b7423 */
/* 0x000fc8000000000b */
/*0bb0*/ FFMA R11, R6.reuse, R11, 0.13980610668659210205 ; /* 0x3e0f2955060b7423 */
/* 0x040fe4000000000b */
/*0bc0*/ FFMA R4, R9, 1.1920928955078125e-07, R4 ; /* 0x3400000009047823 */
/* 0x001fe40000000004 */
/*0bd0*/ FFMA R11, R6, R11, -0.16684235632419586182 ; /* 0xbe2ad8b9060b7423 */
/* 0x000fc8000000000b */
/*0be0*/ FFMA R11, R6, R11, 0.20012299716472625732 ; /* 0x3e4ced0b060b7423 */
/* 0x000fc8000000000b */
/*0bf0*/ FFMA R11, R6, R11, -0.24999669194221496582 ; /* 0xbe7fff22060b7423 */
/* 0x000fc8000000000b */
/*0c00*/ FFMA R11, R6, R11, 0.33333182334899902344 ; /* 0x3eaaaa78060b7423 */
/* 0x000fc8000000000b */
/*0c10*/ FFMA R11, R6, R11, -0.5 ; /* 0xbf000000060b7423 */
/* 0x000fc8000000000b */
/*0c20*/ FMUL R11, R6, R11 ; /* 0x0000000b060b7220 */
/* 0x000fc80000400000 */
/*0c30*/ FFMA R11, R6, R11, R6 ; /* 0x0000000b060b7223 */
/* 0x000fc80000000006 */
/*0c40*/ FFMA R4, R4, 0.69314718246459960938, R11 ; /* 0x3f31721804047823 */
/* 0x000fe4000000000b */
/*0c50*/ @P1 FFMA R4, R10, R5, +INF ; /* 0x7f8000000a041423 */
/* 0x000fca0000000005 */
/*0c60*/ FSEL R4, R4, -INF , P0 ; /* 0xff80000004047808 */
/* 0x000fc80000000000 */
/*0c70*/ FSETP.GEU.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f0e200 */
/*0c80*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0c90*/ PRMT R10, R5, 0x7610, R10 ; /* 0x00007610050a7816 */
/* 0x000fca000000000a */
/*0ca0*/ @!P0 FADD R7, R4, R7 ; /* 0x0000000704078221 */
/* 0x000fe40000000000 */
/*0cb0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0cc0*/ LOP3.LUT P1, RZ, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0aff7812 */
/* 0x000fd8000782c0ff */
/*0cd0*/ BSSY B0, 0xda0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0ce0*/ @P1 BRA 0xd90 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0cf0*/ HFMA2.MMA R6, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff067435 */
/* 0x000fe200000001ff */
/*0d00*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff047424 */
/* 0x000fc800078e00ff */
/*0d10*/ FFMA.SAT R3, R7, R4, 0.5 ; /* 0x3f00000007037423 */
/* 0x000fca0000002004 */
/*0d20*/ FFMA.RM R3, R3, R6, 12582913 ; /* 0x4b40000103037423 */
/* 0x000fc80000004006 */
/*0d30*/ FADD R4, R3.reuse, -12583039 ; /* 0xcb40007f03047421 */
/* 0x040fe40000000000 */
/*0d40*/ IMAD.SHL.U32 R3, R3, 0x800000, RZ ; /* 0x0080000003037824 */
/* 0x000fe400078e00ff */
/*0d50*/ FFMA R4, R7, 1.4426950216293334961, -R4 ; /* 0x3fb8aa3b07047823 */
/* 0x000fc80000000804 */
/*0d60*/ FFMA R4, R7, 1.925963033500011079e-08, R4 ; /* 0x32a5706007047823 */
/* 0x000fcc0000000004 */
/*0d70*/ MUFU.EX2 R4, R4 ; /* 0x0000000400047308 */
/* 0x000e240000000800 */
/*0d80*/ FMUL R3, R3, R4 ; /* 0x0000000403037220 */
/* 0x001fcc0000400000 */
/*0d90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0da0*/ IMAD R5, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002057a24 */
/* 0x040fe200078e02ff */
/*0db0*/ IADD3 R2, R2, c[0x0][0xc], RZ ; /* 0x0000030002027a10 */
/* 0x000fc80007ffe0ff */
/*0dc0*/ IADD3 R6, P0, R5, R0, RZ ; /* 0x0000000005067210 */
/* 0x000fc80007f1e0ff */
/*0dd0*/ LEA.HI.X.SX32 R5, R5, RZ, 0x1, P0 ; /* 0x000000ff05057211 */
/* 0x000fe400000f0eff */
/*0de0*/ LEA R4, P0, R6, c[0x0][0x190], 0x2 ; /* 0x0000640006047a11 */
/* 0x000fc800078010ff */
/*0df0*/ LEA.HI.X R5, R6, c[0x0][0x194], R5, 0x2, P0 ; /* 0x0000650006057a11 */
/* 0x000fe400000f1405 */
/*0e00*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x188], PT ; /* 0x0000620002007a0c */
/* 0x000fc60003f06270 */
/*0e10*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001f4000c101904 */
/*0e20*/ @!P0 BRA 0x80 ; /* 0xfffff25000008947 */
/* 0x000fea000383ffff */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ExpProbPolynomProbsImpl( const float* features, int batchSize, const int* splits, const float* conditions, const int* polynomOffsets, int polynomCount, float lambda, float* probs) {
if (threadIdx.x < batchSize) {
int polynomId = blockIdx.x;
features += threadIdx.x;
probs += threadIdx.x;
while (polynomId < polynomCount) {
int offset = polynomOffsets[polynomId];
int nextOffset = polynomOffsets[polynomId + 1];
const int depth = nextOffset - offset;
float logProb = 0;
bool zeroProb = false;
for (int i = 0; i < depth; ++i) {
if (zeroProb) {
continue;
}
const int f = __ldg(splits + offset + i);
const float c = __ldg(conditions + offset + i);
const float x = __ldg(features + f * batchSize);
const float val = -lambda * x;
const float expVal = 1.0f - expf(val);
if (isfinite(log(expVal))) {
logProb += log(expVal);
} else {
zeroProb = true;
}
}
float prob = 0.0f;
if (!zeroProb) {
prob = expf(logProb);
}
probs[polynomId * batchSize] = prob;
polynomId += gridDim.x;
}
}
} | .file "tmpxft_0018898e_00000000-6_ExpProbPolynomProbsImpl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf
.type _Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf, @function
_Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movl %esi, 52(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 48(%rsp)
movss %xmm0, 20(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf, .-_Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf
.globl _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.type _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, @function
_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, .-_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ExpProbPolynomProbsImpl( const float* features, int batchSize, const int* splits, const float* conditions, const int* polynomOffsets, int polynomCount, float lambda, float* probs) {
if (threadIdx.x < batchSize) {
int polynomId = blockIdx.x;
features += threadIdx.x;
probs += threadIdx.x;
while (polynomId < polynomCount) {
int offset = polynomOffsets[polynomId];
int nextOffset = polynomOffsets[polynomId + 1];
const int depth = nextOffset - offset;
float logProb = 0;
bool zeroProb = false;
for (int i = 0; i < depth; ++i) {
if (zeroProb) {
continue;
}
const int f = __ldg(splits + offset + i);
const float c = __ldg(conditions + offset + i);
const float x = __ldg(features + f * batchSize);
const float val = -lambda * x;
const float expVal = 1.0f - expf(val);
if (isfinite(log(expVal))) {
logProb += log(expVal);
} else {
zeroProb = true;
}
}
float prob = 0.0f;
if (!zeroProb) {
prob = expf(logProb);
}
probs[polynomId * batchSize] = prob;
polynomId += gridDim.x;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ExpProbPolynomProbsImpl( const float* features, int batchSize, const int* splits, const float* conditions, const int* polynomOffsets, int polynomCount, float lambda, float* probs) {
if (threadIdx.x < batchSize) {
int polynomId = blockIdx.x;
features += threadIdx.x;
probs += threadIdx.x;
while (polynomId < polynomCount) {
int offset = polynomOffsets[polynomId];
int nextOffset = polynomOffsets[polynomId + 1];
const int depth = nextOffset - offset;
float logProb = 0;
bool zeroProb = false;
for (int i = 0; i < depth; ++i) {
if (zeroProb) {
continue;
}
const int f = __ldg(splits + offset + i);
const float c = __ldg(conditions + offset + i);
const float x = __ldg(features + f * batchSize);
const float val = -lambda * x;
const float expVal = 1.0f - expf(val);
if (isfinite(log(expVal))) {
logProb += log(expVal);
} else {
zeroProb = true;
}
}
float prob = 0.0f;
if (!zeroProb) {
prob = expf(logProb);
}
probs[polynomId * batchSize] = prob;
polynomId += gridDim.x;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ExpProbPolynomProbsImpl( const float* features, int batchSize, const int* splits, const float* conditions, const int* polynomOffsets, int polynomCount, float lambda, float* probs) {
if (threadIdx.x < batchSize) {
int polynomId = blockIdx.x;
features += threadIdx.x;
probs += threadIdx.x;
while (polynomId < polynomCount) {
int offset = polynomOffsets[polynomId];
int nextOffset = polynomOffsets[polynomId + 1];
const int depth = nextOffset - offset;
float logProb = 0;
bool zeroProb = false;
for (int i = 0; i < depth; ++i) {
if (zeroProb) {
continue;
}
const int f = __ldg(splits + offset + i);
const float c = __ldg(conditions + offset + i);
const float x = __ldg(features + f * batchSize);
const float val = -lambda * x;
const float expVal = 1.0f - expf(val);
if (isfinite(log(expVal))) {
logProb += log(expVal);
} else {
zeroProb = true;
}
}
float prob = 0.0f;
if (!zeroProb) {
prob = expf(logProb);
}
probs[polynomId * batchSize] = prob;
polynomId += gridDim.x;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.globl _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.p2align 8
.type _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf,@function
_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf:
s_load_b32 s10, s[0:1], 0x8
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s10, v0
s_cbranch_execz .LBB0_11
s_load_b32 s11, s[0:1], 0x28
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s11
s_cbranch_scc1 .LBB0_11
s_clause 0x5
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[14:15], s[0:1], 0x30
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
s_load_b32 s12, s[0:1], 0x2c
s_load_b32 s13, s[0:1], 0x38
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s8, v2
v_add_co_ci_u32_e64 v1, null, s9, 0, s0
v_add_co_u32 v2, s0, s14, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s15, 0, s0
s_branch .LBB0_4
.LBB0_3:
v_mul_f32_e32 v5, 0x3fb8aa3b, v4
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
s_mul_i32 s8, s2, s10
s_add_i32 s2, s13, s2
s_ashr_i32 s9, s8, 31
v_rndne_f32_e32 v6, v5
v_fma_f32 v7, v4, 0x3fb8aa3b, -v5
s_lshl_b64 s[8:9], s[8:9], 2
s_cmp_ge_i32 s2, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v5, v6
v_fmac_f32_e32 v7, 0x32a5705f, v4
v_cvt_i32_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v7
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v6, v4, 0, s1
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
global_store_b32 v[4:5], v6, off
s_cbranch_scc1 .LBB0_11
.LBB0_4:
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v4, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s3, s1, s0
s_mov_b32 s1, 0
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_3
s_ashr_i32 s1, s0, 31
v_mov_b32_e32 v4, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_mov_b32 s14, 0
s_add_u32 s8, s4, s0
s_addc_u32 s9, s5, s1
s_mov_b32 s15, 0
s_branch .LBB0_8
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s1, s1, exec_lo
s_and_b32 s0, s0, exec_lo
s_or_b32 s1, s1, s0
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s16
s_add_i32 s14, s14, 1
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_and_not1_b32 s0, s15, exec_lo
s_and_b32 s15, s1, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s15, s0, s15
s_cmp_ge_i32 s14, s3
s_cbranch_scc1 .LBB0_3
.LBB0_8:
s_and_not1_b32 s0, s1, exec_lo
s_and_b32 s1, s15, exec_lo
s_xor_b32 s17, s15, -1
s_or_b32 s1, s0, s1
s_and_saveexec_b32 s16, s17
s_cbranch_execz .LBB0_7
s_load_b32 s0, s[8:9], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s18, s0, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s19, s18, 31
s_lshl_b64 s[18:19], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, v0, s18
v_add_co_ci_u32_e32 v6, vcc_lo, s19, v1, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e64 v5, v5, -s12
v_mul_f32_e32 v6, 0x3fb8aa3b, v5
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v7, v5, 0x3fb8aa3b, -v6
v_rndne_f32_e32 v8, v6
v_dual_fmac_f32 v7, 0x32a5705f, v5 :: v_dual_sub_f32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v6, v7
v_cvt_i32_f32_e32 v7, v8
v_exp_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
v_cndmask_b32_e32 v5, 0x7f800000, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, 1.0, v5
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v5
v_cndmask_b32_e64 v6, 1.0, 0x4f800000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v5, v6
v_log_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x3f317217, v5
v_cmp_gt_f32_e64 s0, 0x7f800000, |v5|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v5, 0x3f317217, -v6
v_fmac_f32_e32 v7, 0x3377d1cf, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v6, v7
v_cndmask_b32_e64 v5, v5, v6, s0
v_cndmask_b32_e64 v6, 0, 0x41b17218, vcc_lo
s_mov_b32 s0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v6
v_cmp_class_f32_e64 s18, v5, 0x1f8
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s17, s18
s_cbranch_execz .LBB0_6
v_add_f32_e32 v4, v4, v5
s_or_not1_b32 s0, s15, exec_lo
s_branch .LBB0_6
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, .Lfunc_end0-_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ExpProbPolynomProbsImpl( const float* features, int batchSize, const int* splits, const float* conditions, const int* polynomOffsets, int polynomCount, float lambda, float* probs) {
if (threadIdx.x < batchSize) {
int polynomId = blockIdx.x;
features += threadIdx.x;
probs += threadIdx.x;
while (polynomId < polynomCount) {
int offset = polynomOffsets[polynomId];
int nextOffset = polynomOffsets[polynomId + 1];
const int depth = nextOffset - offset;
float logProb = 0;
bool zeroProb = false;
for (int i = 0; i < depth; ++i) {
if (zeroProb) {
continue;
}
const int f = __ldg(splits + offset + i);
const float c = __ldg(conditions + offset + i);
const float x = __ldg(features + f * batchSize);
const float val = -lambda * x;
const float expVal = 1.0f - expf(val);
if (isfinite(log(expVal))) {
logProb += log(expVal);
} else {
zeroProb = true;
}
}
float prob = 0.0f;
if (!zeroProb) {
prob = expf(logProb);
}
probs[polynomId * batchSize] = prob;
polynomId += gridDim.x;
}
}
} | .text
.file "ExpProbPolynomProbsImpl.hip"
.globl _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf # -- Begin function _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.p2align 4, 0x90
.type _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf,@function
_Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf: # @_Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, .Lfunc_end0-_Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf,@object # @_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.section .rodata,"a",@progbits
.globl _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.p2align 3, 0x0
_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf:
.quad _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.size _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x001fda0003f06070 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e240000002500 */
/*0050*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x188], PT ; /* 0x0000620002007a0c */
/* 0x001fda0003f06270 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0080*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fd400000001ff */
/*0090*/ IMAD.WIDE R8, R2, R9, c[0x0][0x180] ; /* 0x0000600002087625 */
/* 0x000fca00078e0209 */
/*00a0*/ LDG.E R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x001ea8000c1e1900 */
/*00b0*/ LDG.E R11, [R8.64+0x4] ; /* 0x00000404080b7981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2e170 */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, RZ ; /* 0x000000ffff037224 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GT.AND P0, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x004fda0003f04270 */
/*0100*/ @!P0 BRA 0xcd0 ; /* 0x00000bc000008947 */
/* 0x000fea0003800000 */
/*0110*/ IADD3 R5, R4, 0x1, RZ ; /* 0x0000000104057810 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.IADD R8, R11.reuse, 0x1, -R4.reuse ; /* 0x000000010b087824 */
/* 0x140fe200078e0a04 */
/*0130*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2e170 */
/*0140*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0150*/ ISETP.NE.AND P0, PT, R11, R5, PT ; /* 0x000000050b00720c */
/* 0x000fe40003f05270 */
/*0160*/ SHF.R.S32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fe40000011404 */
/*0170*/ PRMT R10, RZ, 0x7610, R10 ; /* 0x00007610ff0a7816 */
/* 0x000fe4000000000a */
/*0180*/ LOP3.LUT R9, R8, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108097812 */
/* 0x000fce00078ec0ff */
/*0190*/ @!P0 BRA 0x930 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01a0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f2e170 */
/*01b0*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*01c0*/ IADD3 R8, R8, -R9, RZ ; /* 0x8000000908087210 */
/* 0x000fe40007ffe0ff */
/*01d0*/ PRMT R10, RZ, 0x7610, R10 ; /* 0x00007610ff0a7816 */
/* 0x000fc8000000000a */
/*01e0*/ IADD3 R8, R8, -0x2, RZ ; /* 0xfffffffe08087810 */
/* 0x000fe20007ffe0ff */
/*01f0*/ BSSY B0, 0x570 ; /* 0x0000037000007945 */
/* 0x000fe60003800000 */
/*0200*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0210*/ @P1 BRA 0x560 ; /* 0x0000034000001947 */
/* 0x000fee0003800000 */
/*0220*/ IADD3 R11, P1, R4, R6, RZ ; /* 0x00000006040b7210 */
/* 0x000fc80007f3e0ff */
/*0230*/ LEA.HI.X.SX32 R12, R6, R5, 0x1, P1 ; /* 0x00000005060c7211 */
/* 0x000fe400008f0eff */
/*0240*/ LEA R10, P1, R11, c[0x0][0x170], 0x2 ; /* 0x00005c000b0a7a11 */
/* 0x000fc800078210ff */
/*0250*/ LEA.HI.X R11, R11, c[0x0][0x174], R12, 0x2, P1 ; /* 0x00005d000b0b7a11 */
/* 0x000fca00008f140c */
/*0260*/ LDG.E.CONSTANT R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e9900 */
/*0270*/ IMAD R13, R10, c[0x0][0x168], RZ ; /* 0x00005a000a0d7a24 */
/* 0x004fca00078e02ff */
/*0280*/ IADD3 R14, P1, R13, R0, RZ ; /* 0x000000000d0e7210 */
/* 0x000fc80007f3e0ff */
/*0290*/ LEA.HI.X.SX32 R13, R13, RZ, 0x1, P1 ; /* 0x000000ff0d0d7211 */
/* 0x000fe400008f0eff */
/*02a0*/ LEA R12, P1, R14, c[0x0][0x160], 0x2 ; /* 0x000058000e0c7a11 */
/* 0x000fc800078210ff */
/*02b0*/ LEA.HI.X R13, R14, c[0x0][0x164], R13, 0x2, P1 ; /* 0x000059000e0d7a11 */
/* 0x000fca00008f140d */
/*02c0*/ LDG.E.CONSTANT R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e9900 */
/*02d0*/ HFMA2.MMA R16, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff107435 */
/* 0x000fe200000001ff */
/*02e0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff0f7424 */
/* 0x000fe400078e00ff */
/*02f0*/ FMUL R14, R12, c[0x0][0x18c] ; /* 0x000063000c0e7a20 */
/* 0x004fc80000400000 */
/*0300*/ FFMA.SAT R15, -R14, R15, 0.5 ; /* 0x3f0000000e0f7423 */
/* 0x000fc8000000210f */
/*0310*/ FFMA.RM R15, R15, R16, 12582913 ; /* 0x4b4000010f0f7423 */
/* 0x000fc80000004010 */
/*0320*/ FADD R11, R15.reuse, -12583039 ; /* 0xcb40007f0f0b7421 */
/* 0x040fe40000000000 */
/*0330*/ IMAD.SHL.U32 R10, R15, 0x800000, RZ ; /* 0x008000000f0a7824 */
/* 0x000fe400078e00ff */
/*0340*/ FFMA R11, -R14.reuse, 1.4426950216293334961, -R11 ; /* 0x3fb8aa3b0e0b7823 */
/* 0x040fe4000000090b */
/*0350*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3e055027 ; /* 0x3e055027ff0f7424 */
/* 0x000fe400078e00ff */
/*0360*/ FFMA R11, -R14, 1.925963033500011079e-08, R11 ; /* 0x32a570600e0b7823 */
/* 0x000fcc000000010b */
/*0370*/ MUFU.EX2 R11, R11 ; /* 0x0000000b000b7308 */
/* 0x000e240000000800 */
/*0380*/ FFMA R10, R10, -R11, 1 ; /* 0x3f8000000a0a7423 */
/* 0x001fca000000080b */
/*0390*/ FSETP.GEU.AND P1, PT, R10, 1.175494350822287508e-38, PT ; /* 0x008000000a00780b */
/* 0x000fc80003f2e000 */
/*03a0*/ FSEL R11, RZ, -23, P1 ; /* 0xc1b80000ff0b7808 */
/* 0x000fd20000800000 */
/*03b0*/ @!P1 FMUL R10, R10, 8388608 ; /* 0x4b0000000a0a9820 */
/* 0x000fca0000400000 */
/*03c0*/ IADD3 R12, R10.reuse, -0x3f2aaaab, RZ ; /* 0xc0d555550a0c7810 */
/* 0x040fe40007ffe0ff */
/*03d0*/ ISETP.GE.U32.AND P2, PT, R10, 0x7f800000, PT ; /* 0x7f8000000a00780c */
/* 0x000fe40003f46070 */
/*03e0*/ LOP3.LUT R13, R12, 0xff800000, RZ, 0xc0, !PT ; /* 0xff8000000c0d7812 */
/* 0x000fe400078ec0ff */
/*03f0*/ FSETP.NEU.AND P1, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x040fe40003f2d000 */
/*0400*/ IADD3 R12, R10, -R13, RZ ; /* 0x8000000d0a0c7210 */
/* 0x000fca0007ffe0ff */
/*0410*/ FADD R14, R12, -1 ; /* 0xbf8000000c0e7421 */
/* 0x000fe40000000000 */
/*0420*/ I2F R12, R13 ; /* 0x0000000d000c7306 */
/* 0x000e240000201400 */
/*0430*/ FFMA R15, R14, -R15, 0.14084610342979431152 ; /* 0x3e1039f60e0f7423 */
/* 0x000fc8000000080f */
/*0440*/ FFMA R15, R14, R15, -0.12148627638816833496 ; /* 0xbdf8cdcc0e0f7423 */
/* 0x000fc8000000000f */
/*0450*/ FFMA R15, R14, R15, 0.13980610668659210205 ; /* 0x3e0f29550e0f7423 */
/* 0x000fc8000000000f */
/*0460*/ FFMA R15, R14, R15, -0.16684235632419586182 ; /* 0xbe2ad8b90e0f7423 */
/* 0x000fe4000000000f */
/*0470*/ FFMA R11, R12, 1.1920928955078125e-07, R11 ; /* 0x340000000c0b7823 */
/* 0x001fe4000000000b */
/*0480*/ FFMA R15, R14, R15, 0.20012299716472625732 ; /* 0x3e4ced0b0e0f7423 */
/* 0x000fc8000000000f */
/*0490*/ FFMA R15, R14, R15, -0.24999669194221496582 ; /* 0xbe7fff220e0f7423 */
/* 0x000fc8000000000f */
/*04a0*/ FFMA R15, R14, R15, 0.33333182334899902344 ; /* 0x3eaaaa780e0f7423 */
/* 0x000fc8000000000f */
/*04b0*/ FFMA R15, R14, R15, -0.5 ; /* 0xbf0000000e0f7423 */
/* 0x000fc8000000000f */
/*04c0*/ FMUL R15, R14, R15 ; /* 0x0000000f0e0f7220 */
/* 0x000fc80000400000 */
/*04d0*/ FFMA R14, R14, R15, R14 ; /* 0x0000000f0e0e7223 */
/* 0x000fe2000000000e */
/*04e0*/ @P2 MOV R15, 0x7f800000 ; /* 0x7f800000000f2802 */
/* 0x000fc60000000f00 */
/*04f0*/ FFMA R11, R11, 0.69314718246459960938, R14 ; /* 0x3f3172180b0b7823 */
/* 0x000fe4000000000e */
/*0500*/ @P2 FFMA R11, R10, R15, +INF ; /* 0x7f8000000a0b2423 */
/* 0x000fca000000000f */
/*0510*/ FSEL R10, R11, -INF , P1 ; /* 0xff8000000b0a7808 */
/* 0x000fc80000800000 */
/*0520*/ FSETP.GEU.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fc80003f2e200 */
/*0530*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fd20004800000 */
/*0540*/ @!P1 FADD R7, R7, R10.reuse ; /* 0x0000000a07079221 */
/* 0x100fe20000000000 */
/*0550*/ PRMT R10, R11, 0x7610, R10 ; /* 0x000076100b0a7816 */
/* 0x000fe4000000000a */
/*0560*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0570*/ LOP3.LUT P1, RZ, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0aff7812 */
/* 0x000fe2000782c0ff */
/*0580*/ BSSY B0, 0x900 ; /* 0x0000037000007945 */
/* 0x000fd80003800000 */
/*0590*/ @P1 BRA 0x8f0 ; /* 0x0000035000001947 */
/* 0x000fea0003800000 */
/*05a0*/ IADD3 R10, R6, 0x1, RZ ; /* 0x00000001060a7810 */
/* 0x000fc80007ffe0ff */
/*05b0*/ IADD3 R11, P1, R4, R10, RZ ; /* 0x0000000a040b7210 */
/* 0x000fc80007f3e0ff */
/*05c0*/ LEA.HI.X.SX32 R12, R10, R5, 0x1, P1 ; /* 0x000000050a0c7211 */
/* 0x000fe400008f0eff */
/*05d0*/ LEA R10, P1, R11, c[0x0][0x170], 0x2 ; /* 0x00005c000b0a7a11 */
/* 0x000fc800078210ff */
/*05e0*/ LEA.HI.X R11, R11, c[0x0][0x174], R12, 0x2, P1 ; /* 0x00005d000b0b7a11 */
/* 0x000fca00008f140c */
/*05f0*/ LDG.E.CONSTANT R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea4000c1e9900 */
/*0600*/ IMAD R13, R10, c[0x0][0x168], RZ ; /* 0x00005a000a0d7a24 */
/* 0x004fca00078e02ff */
/*0610*/ IADD3 R14, P1, R13, R0, RZ ; /* 0x000000000d0e7210 */
/* 0x000fc80007f3e0ff */
/*0620*/ LEA.HI.X.SX32 R13, R13, RZ, 0x1, P1 ; /* 0x000000ff0d0d7211 */
/* 0x000fe400008f0eff */
/*0630*/ LEA R12, P1, R14, c[0x0][0x160], 0x2 ; /* 0x000058000e0c7a11 */
/* 0x000fc800078210ff */
/*0640*/ LEA.HI.X R13, R14, c[0x0][0x164], R13, 0x2, P1 ; /* 0x000059000e0d7a11 */
/* 0x000fca00008f140d */
/*0650*/ LDG.E.CONSTANT R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e9900 */
/*0660*/ HFMA2.MMA R16, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff107435 */
/* 0x000fe200000001ff */
/*0670*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff0f7424 */
/* 0x000fe400078e00ff */
/*0680*/ FMUL R14, R12, c[0x0][0x18c] ; /* 0x000063000c0e7a20 */
/* 0x004fc80000400000 */
/*0690*/ FFMA.SAT R15, -R14, R15, 0.5 ; /* 0x3f0000000e0f7423 */
/* 0x000fc8000000210f */
/*06a0*/ FFMA.RM R15, R15, R16, 12582913 ; /* 0x4b4000010f0f7423 */
/* 0x000fc80000004010 */
/*06b0*/ FADD R11, R15.reuse, -12583039 ; /* 0xcb40007f0f0b7421 */
/* 0x040fe40000000000 */
/*06c0*/ IMAD.SHL.U32 R10, R15, 0x800000, RZ ; /* 0x008000000f0a7824 */
/* 0x000fe400078e00ff */
/*06d0*/ FFMA R11, -R14.reuse, 1.4426950216293334961, -R11 ; /* 0x3fb8aa3b0e0b7823 */
/* 0x040fe4000000090b */
/*06e0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3e055027 ; /* 0x3e055027ff0f7424 */
/* 0x000fe400078e00ff */
/*06f0*/ FFMA R11, -R14, 1.925963033500011079e-08, R11 ; /* 0x32a570600e0b7823 */
/* 0x000fcc000000010b */
/*0700*/ MUFU.EX2 R11, R11 ; /* 0x0000000b000b7308 */
/* 0x000e240000000800 */
/*0710*/ FFMA R10, R10, -R11, 1 ; /* 0x3f8000000a0a7423 */
/* 0x001fca000000080b */
/*0720*/ FSETP.GEU.AND P1, PT, R10, 1.175494350822287508e-38, PT ; /* 0x008000000a00780b */
/* 0x000fc80003f2e000 */
/*0730*/ FSEL R11, RZ, -23, P1 ; /* 0xc1b80000ff0b7808 */
/* 0x000fd20000800000 */
/*0740*/ @!P1 FMUL R10, R10, 8388608 ; /* 0x4b0000000a0a9820 */
/* 0x000fca0000400000 */
/*0750*/ IADD3 R12, R10.reuse, -0x3f2aaaab, RZ ; /* 0xc0d555550a0c7810 */
/* 0x040fe40007ffe0ff */
/*0760*/ ISETP.GE.U32.AND P2, PT, R10, 0x7f800000, PT ; /* 0x7f8000000a00780c */
/* 0x000fe40003f46070 */
/*0770*/ LOP3.LUT R13, R12, 0xff800000, RZ, 0xc0, !PT ; /* 0xff8000000c0d7812 */
/* 0x000fe400078ec0ff */
/*0780*/ FSETP.NEU.AND P1, PT, R10.reuse, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x040fe40003f2d000 */
/*0790*/ IADD3 R12, R10, -R13, RZ ; /* 0x8000000d0a0c7210 */
/* 0x000fca0007ffe0ff */
/*07a0*/ FADD R14, R12, -1 ; /* 0xbf8000000c0e7421 */
/* 0x000fe40000000000 */
/*07b0*/ I2F R12, R13 ; /* 0x0000000d000c7306 */
/* 0x000e240000201400 */
/*07c0*/ FFMA R15, R14, -R15, 0.14084610342979431152 ; /* 0x3e1039f60e0f7423 */
/* 0x000fc8000000080f */
/*07d0*/ FFMA R15, R14, R15, -0.12148627638816833496 ; /* 0xbdf8cdcc0e0f7423 */
/* 0x000fc8000000000f */
/*07e0*/ FFMA R15, R14, R15, 0.13980610668659210205 ; /* 0x3e0f29550e0f7423 */
/* 0x000fc8000000000f */
/*07f0*/ FFMA R15, R14, R15, -0.16684235632419586182 ; /* 0xbe2ad8b90e0f7423 */
/* 0x000fe4000000000f */
/*0800*/ FFMA R11, R12, 1.1920928955078125e-07, R11 ; /* 0x340000000c0b7823 */
/* 0x001fe4000000000b */
/*0810*/ FFMA R15, R14, R15, 0.20012299716472625732 ; /* 0x3e4ced0b0e0f7423 */
/* 0x000fc8000000000f */
/*0820*/ FFMA R15, R14, R15, -0.24999669194221496582 ; /* 0xbe7fff220e0f7423 */
/* 0x000fc8000000000f */
/*0830*/ FFMA R15, R14, R15, 0.33333182334899902344 ; /* 0x3eaaaa780e0f7423 */
/* 0x000fc8000000000f */
/*0840*/ FFMA R15, R14, R15, -0.5 ; /* 0xbf0000000e0f7423 */
/* 0x000fc8000000000f */
/*0850*/ FMUL R15, R14, R15 ; /* 0x0000000f0e0f7220 */
/* 0x000fc80000400000 */
/*0860*/ FFMA R14, R14, R15, R14 ; /* 0x0000000f0e0e7223 */
/* 0x000fe2000000000e */
/*0870*/ @P2 MOV R15, 0x7f800000 ; /* 0x7f800000000f2802 */
/* 0x000fc60000000f00 */
/*0880*/ FFMA R11, R11, 0.69314718246459960938, R14 ; /* 0x3f3172180b0b7823 */
/* 0x000fe4000000000e */
/*0890*/ @P2 FFMA R11, R10, R15, +INF ; /* 0x7f8000000a0b2423 */
/* 0x000fca000000000f */
/*08a0*/ FSEL R10, R11, -INF , P1 ; /* 0xff8000000b0a7808 */
/* 0x000fc80000800000 */
/*08b0*/ FSETP.GEU.AND P1, PT, |R10|, +INF , PT ; /* 0x7f8000000a00780b */
/* 0x000fc80003f2e200 */
/*08c0*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fd20004800000 */
/*08d0*/ @!P1 FADD R7, R7, R10.reuse ; /* 0x0000000a07079221 */
/* 0x100fe20000000000 */
/*08e0*/ PRMT R10, R11, 0x7610, R10 ; /* 0x000076100b0a7816 */
/* 0x000fe4000000000a */
/*08f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0900*/ LOP3.LUT P1, RZ, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0aff7812 */
/* 0x000fe4000782c0ff */
/*0910*/ IADD3 R6, R6, 0x2, RZ ; /* 0x0000000206067810 */
/* 0x000fe20007ffe0ff */
/*0920*/ @P0 BRA 0x1e0 ; /* 0xfffff8b000000947 */
/* 0x000fea000383ffff */
/*0930*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f05270 */
/*0940*/ @!P0 BRA 0xcd0 ; /* 0x0000038000008947 */
/* 0x000fea0003800000 */
/*0950*/ BSSY B0, 0xcc0 ; /* 0x0000036000007945 */
/* 0x000fe20003800000 */
/*0960*/ @P1 BRA 0xcb0 ; /* 0x0000034000001947 */
/* 0x000fea0003800000 */
/*0970*/ IADD3 R8, P0, R4, R6, RZ ; /* 0x0000000604087210 */
/* 0x000fc80007f1e0ff */
/*0980*/ LEA.HI.X.SX32 R5, R6, R5, 0x1, P0 ; /* 0x0000000506057211 */
/* 0x000fe400000f0eff */
/*0990*/ LEA R4, P0, R8, c[0x0][0x170], 0x2 ; /* 0x00005c0008047a11 */
/* 0x000fc800078010ff */
/*09a0*/ LEA.HI.X R5, R8, c[0x0][0x174], R5, 0x2, P0 ; /* 0x00005d0008057a11 */
/* 0x000fca00000f1405 */
/*09b0*/ LDG.E.CONSTANT R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e9900 */
/*09c0*/ IMAD R9, R4, c[0x0][0x168], RZ ; /* 0x00005a0004097a24 */
/* 0x004fca00078e02ff */
/*09d0*/ IADD3 R6, P0, R9, R0, RZ ; /* 0x0000000009067210 */
/* 0x000fc80007f1e0ff */
/*09e0*/ LEA.HI.X.SX32 R9, R9, RZ, 0x1, P0 ; /* 0x000000ff09097211 */
/* 0x000fe400000f0eff */
/*09f0*/ LEA R8, P0, R6, c[0x0][0x160], 0x2 ; /* 0x0000580006087a11 */
/* 0x000fc800078010ff */
/*0a00*/ LEA.HI.X R9, R6, c[0x0][0x164], R9, 0x2, P0 ; /* 0x0000590006097a11 */
/* 0x000fca00000f1409 */
/*0a10*/ LDG.E.CONSTANT R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e9900 */
/*0a20*/ HFMA2.MMA R13, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff0d7435 */
/* 0x000fe200000001ff */
/*0a30*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff0b7424 */
/* 0x000fe400078e00ff */
/*0a40*/ FMUL R6, R8, c[0x0][0x18c] ; /* 0x0000630008067a20 */
/* 0x004fc80000400000 */
/*0a50*/ FFMA.SAT R10, -R6, R11, 0.5 ; /* 0x3f000000060a7423 */
/* 0x000fe4000000210b */
/*0a60*/ IMAD.MOV.U32 R11, RZ, RZ, 0x3e055027 ; /* 0x3e055027ff0b7424 */
/* 0x000fe400078e00ff */
/*0a70*/ FFMA.RM R10, R10, R13, 12582913 ; /* 0x4b4000010a0a7423 */
/* 0x000fc8000000400d */
/*0a80*/ FADD R5, R10.reuse, -12583039 ; /* 0xcb40007f0a057421 */
/* 0x040fe40000000000 */
/*0a90*/ IMAD.SHL.U32 R10, R10, 0x800000, RZ ; /* 0x008000000a0a7824 */
/* 0x000fe400078e00ff */
/*0aa0*/ FFMA R5, -R6, 1.4426950216293334961, -R5 ; /* 0x3fb8aa3b06057823 */
/* 0x000fc80000000905 */
/*0ab0*/ FFMA R5, -R6, 1.925963033500011079e-08, R5 ; /* 0x32a5706006057823 */
/* 0x000fcc0000000105 */
/*0ac0*/ MUFU.EX2 R5, R5 ; /* 0x0000000500057308 */
/* 0x000e240000000800 */
/*0ad0*/ FFMA R10, R10, -R5, 1 ; /* 0x3f8000000a0a7423 */
/* 0x001fca0000000805 */
/*0ae0*/ FSETP.GEU.AND P0, PT, R10, 1.175494350822287508e-38, PT ; /* 0x008000000a00780b */
/* 0x000fda0003f0e000 */
/*0af0*/ @!P0 FMUL R10, R10, 8388608 ; /* 0x4b0000000a0a8820 */
/* 0x000fca0000400000 */
/*0b00*/ IADD3 R4, R10.reuse, -0x3f2aaaab, RZ ; /* 0xc0d555550a047810 */
/* 0x040fe40007ffe0ff */
/*0b10*/ ISETP.GE.U32.AND P1, PT, R10, 0x7f800000, PT ; /* 0x7f8000000a00780c */
/* 0x000fe40003f26070 */
/*0b20*/ LOP3.LUT R9, R4, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000004097812 */
/* 0x000fc800078ec0ff */
/*0b30*/ IADD3 R4, R10, -R9, RZ ; /* 0x800000090a047210 */
/* 0x000fe40007ffe0ff */
/*0b40*/ I2F R9, R9 ; /* 0x0000000900097306 */
/* 0x000e260000201400 */
/*0b50*/ FADD R6, R4, -1 ; /* 0xbf80000004067421 */
/* 0x000fe20000000000 */
/*0b60*/ FSEL R4, RZ, -23, P0 ; /* 0xc1b80000ff047808 */
/* 0x000fe40000000000 */
/*0b70*/ @P1 MOV R5, 0x7f800000 ; /* 0x7f80000000051802 */
/* 0x000fe20000000f00 */
/*0b80*/ FFMA R11, R6, -R11, 0.14084610342979431152 ; /* 0x3e1039f6060b7423 */
/* 0x000fe2000000080b */
/*0b90*/ FSETP.NEU.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720b */
/* 0x000fc60003f0d000 */
/*0ba0*/ FFMA R11, R6, R11, -0.12148627638816833496 ; /* 0xbdf8cdcc060b7423 */
/* 0x000fc8000000000b */
/*0bb0*/ FFMA R11, R6.reuse, R11, 0.13980610668659210205 ; /* 0x3e0f2955060b7423 */
/* 0x040fe4000000000b */
/*0bc0*/ FFMA R4, R9, 1.1920928955078125e-07, R4 ; /* 0x3400000009047823 */
/* 0x001fe40000000004 */
/*0bd0*/ FFMA R11, R6, R11, -0.16684235632419586182 ; /* 0xbe2ad8b9060b7423 */
/* 0x000fc8000000000b */
/*0be0*/ FFMA R11, R6, R11, 0.20012299716472625732 ; /* 0x3e4ced0b060b7423 */
/* 0x000fc8000000000b */
/*0bf0*/ FFMA R11, R6, R11, -0.24999669194221496582 ; /* 0xbe7fff22060b7423 */
/* 0x000fc8000000000b */
/*0c00*/ FFMA R11, R6, R11, 0.33333182334899902344 ; /* 0x3eaaaa78060b7423 */
/* 0x000fc8000000000b */
/*0c10*/ FFMA R11, R6, R11, -0.5 ; /* 0xbf000000060b7423 */
/* 0x000fc8000000000b */
/*0c20*/ FMUL R11, R6, R11 ; /* 0x0000000b060b7220 */
/* 0x000fc80000400000 */
/*0c30*/ FFMA R11, R6, R11, R6 ; /* 0x0000000b060b7223 */
/* 0x000fc80000000006 */
/*0c40*/ FFMA R4, R4, 0.69314718246459960938, R11 ; /* 0x3f31721804047823 */
/* 0x000fe4000000000b */
/*0c50*/ @P1 FFMA R4, R10, R5, +INF ; /* 0x7f8000000a041423 */
/* 0x000fca0000000005 */
/*0c60*/ FSEL R4, R4, -INF , P0 ; /* 0xff80000004047808 */
/* 0x000fc80000000000 */
/*0c70*/ FSETP.GEU.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fc80003f0e200 */
/*0c80*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fc80004000000 */
/*0c90*/ PRMT R10, R5, 0x7610, R10 ; /* 0x00007610050a7816 */
/* 0x000fca000000000a */
/*0ca0*/ @!P0 FADD R7, R4, R7 ; /* 0x0000000704078221 */
/* 0x000fe40000000000 */
/*0cb0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0cc0*/ LOP3.LUT P1, RZ, R10, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0aff7812 */
/* 0x000fd8000782c0ff */
/*0cd0*/ BSSY B0, 0xda0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0ce0*/ @P1 BRA 0xd90 ; /* 0x000000a000001947 */
/* 0x000fea0003800000 */
/*0cf0*/ HFMA2.MMA R6, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff067435 */
/* 0x000fe200000001ff */
/*0d00*/ IMAD.MOV.U32 R4, RZ, RZ, 0x3bbb989d ; /* 0x3bbb989dff047424 */
/* 0x000fc800078e00ff */
/*0d10*/ FFMA.SAT R3, R7, R4, 0.5 ; /* 0x3f00000007037423 */
/* 0x000fca0000002004 */
/*0d20*/ FFMA.RM R3, R3, R6, 12582913 ; /* 0x4b40000103037423 */
/* 0x000fc80000004006 */
/*0d30*/ FADD R4, R3.reuse, -12583039 ; /* 0xcb40007f03047421 */
/* 0x040fe40000000000 */
/*0d40*/ IMAD.SHL.U32 R3, R3, 0x800000, RZ ; /* 0x0080000003037824 */
/* 0x000fe400078e00ff */
/*0d50*/ FFMA R4, R7, 1.4426950216293334961, -R4 ; /* 0x3fb8aa3b07047823 */
/* 0x000fc80000000804 */
/*0d60*/ FFMA R4, R7, 1.925963033500011079e-08, R4 ; /* 0x32a5706007047823 */
/* 0x000fcc0000000004 */
/*0d70*/ MUFU.EX2 R4, R4 ; /* 0x0000000400047308 */
/* 0x000e240000000800 */
/*0d80*/ FMUL R3, R3, R4 ; /* 0x0000000403037220 */
/* 0x001fcc0000400000 */
/*0d90*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0da0*/ IMAD R5, R2.reuse, c[0x0][0x168], RZ ; /* 0x00005a0002057a24 */
/* 0x040fe200078e02ff */
/*0db0*/ IADD3 R2, R2, c[0x0][0xc], RZ ; /* 0x0000030002027a10 */
/* 0x000fc80007ffe0ff */
/*0dc0*/ IADD3 R6, P0, R5, R0, RZ ; /* 0x0000000005067210 */
/* 0x000fc80007f1e0ff */
/*0dd0*/ LEA.HI.X.SX32 R5, R5, RZ, 0x1, P0 ; /* 0x000000ff05057211 */
/* 0x000fe400000f0eff */
/*0de0*/ LEA R4, P0, R6, c[0x0][0x190], 0x2 ; /* 0x0000640006047a11 */
/* 0x000fc800078010ff */
/*0df0*/ LEA.HI.X R5, R6, c[0x0][0x194], R5, 0x2, P0 ; /* 0x0000650006057a11 */
/* 0x000fe400000f1405 */
/*0e00*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x188], PT ; /* 0x0000620002007a0c */
/* 0x000fc60003f06270 */
/*0e10*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0001f4000c101904 */
/*0e20*/ @!P0 BRA 0x80 ; /* 0xfffff25000008947 */
/* 0x000fea000383ffff */
/*0e30*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e40*/ BRA 0xe40; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.globl _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.p2align 8
.type _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf,@function
_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf:
s_load_b32 s10, s[0:1], 0x8
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s10, v0
s_cbranch_execz .LBB0_11
s_load_b32 s11, s[0:1], 0x28
s_mov_b32 s2, s15
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s11
s_cbranch_scc1 .LBB0_11
s_clause 0x5
s_load_b64 s[8:9], s[0:1], 0x0
s_load_b64 s[14:15], s[0:1], 0x30
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b64 s[6:7], s[0:1], 0x20
s_load_b32 s12, s[0:1], 0x2c
s_load_b32 s13, s[0:1], 0x38
v_lshlrev_b32_e32 v2, 2, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v0, s0, s8, v2
v_add_co_ci_u32_e64 v1, null, s9, 0, s0
v_add_co_u32 v2, s0, s14, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, null, s15, 0, s0
s_branch .LBB0_4
.LBB0_3:
v_mul_f32_e32 v5, 0x3fb8aa3b, v4
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
s_mul_i32 s8, s2, s10
s_add_i32 s2, s13, s2
s_ashr_i32 s9, s8, 31
v_rndne_f32_e32 v6, v5
v_fma_f32 v7, v4, 0x3fb8aa3b, -v5
s_lshl_b64 s[8:9], s[8:9], 2
s_cmp_ge_i32 s2, s11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v5, v5, v6
v_fmac_f32_e32 v7, 0x32a5705f, v4
v_cvt_i32_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v7
v_exp_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_ldexp_f32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cndmask_b32_e64 v6, v4, 0, s1
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
global_store_b32 v[4:5], v6, off
s_cbranch_scc1 .LBB0_11
.LBB0_4:
s_ashr_i32 s3, s2, 31
v_mov_b32_e32 v4, 0
s_lshl_b64 s[0:1], s[2:3], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_sub_i32 s3, s1, s0
s_mov_b32 s1, 0
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB0_3
s_ashr_i32 s1, s0, 31
v_mov_b32_e32 v4, 0
s_lshl_b64 s[0:1], s[0:1], 2
s_mov_b32 s14, 0
s_add_u32 s8, s4, s0
s_addc_u32 s9, s5, s1
s_mov_b32 s15, 0
s_branch .LBB0_8
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s17
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_and_not1_b32 s1, s1, exec_lo
s_and_b32 s0, s0, exec_lo
s_or_b32 s1, s1, s0
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s16
s_add_i32 s14, s14, 1
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_and_not1_b32 s0, s15, exec_lo
s_and_b32 s15, s1, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s15, s0, s15
s_cmp_ge_i32 s14, s3
s_cbranch_scc1 .LBB0_3
.LBB0_8:
s_and_not1_b32 s0, s1, exec_lo
s_and_b32 s1, s15, exec_lo
s_xor_b32 s17, s15, -1
s_or_b32 s1, s0, s1
s_and_saveexec_b32 s16, s17
s_cbranch_execz .LBB0_7
s_load_b32 s0, s[8:9], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s18, s0, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s19, s18, 31
s_lshl_b64 s[18:19], s[18:19], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_u32 v5, vcc_lo, v0, s18
v_add_co_ci_u32_e32 v6, vcc_lo, s19, v1, vcc_lo
global_load_b32 v5, v[5:6], off
s_waitcnt vmcnt(0)
v_mul_f32_e64 v5, v5, -s12
v_mul_f32_e32 v6, 0x3fb8aa3b, v5
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v7, v5, 0x3fb8aa3b, -v6
v_rndne_f32_e32 v8, v6
v_dual_fmac_f32 v7, 0x32a5705f, v5 :: v_dual_sub_f32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v6, v6, v7
v_cvt_i32_f32_e32 v7, v8
v_exp_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v5
v_cndmask_b32_e32 v5, 0x7f800000, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, 1.0, v5
v_cmp_gt_f32_e32 vcc_lo, 0x800000, v5
v_cndmask_b32_e64 v6, 1.0, 0x4f800000, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v5, v6
v_log_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x3f317217, v5
v_cmp_gt_f32_e64 s0, 0x7f800000, |v5|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v5, 0x3f317217, -v6
v_fmac_f32_e32 v7, 0x3377d1cf, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v6, v7
v_cndmask_b32_e64 v5, v5, v6, s0
v_cndmask_b32_e64 v6, 0, 0x41b17218, vcc_lo
s_mov_b32 s0, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v6
v_cmp_class_f32_e64 s18, v5, 0x1f8
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s17, s18
s_cbranch_execz .LBB0_6
v_add_f32_e32 v4, v4, v5
s_or_not1_b32 s0, s15, exec_lo
s_branch .LBB0_6
.LBB0_11:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 20
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, .Lfunc_end0-_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.private_segment_fixed_size: 0
.sgpr_count: 22
.sgpr_spill_count: 0
.symbol: _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018898e_00000000-6_ExpProbPolynomProbsImpl.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf
.type _Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf, @function
_Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movq %rdi, 56(%rsp)
movl %esi, 52(%rsp)
movq %rdx, 40(%rsp)
movq %rcx, 32(%rsp)
movq %r8, 24(%rsp)
movl %r9d, 48(%rsp)
movss %xmm0, 20(%rsp)
movq 224(%rsp), %rax
movq %rax, 8(%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 52(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 24(%rsp), %rax
movq %rax, 160(%rsp)
leaq 48(%rsp), %rax
movq %rax, 168(%rsp)
leaq 20(%rsp), %rax
movq %rax, 176(%rsp)
leaq 8(%rsp), %rax
movq %rax, 184(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 232
pushq 72(%rsp)
.cfi_def_cfa_offset 240
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf, .-_Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf
.globl _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.type _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, @function
_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
pushq 24(%rsp)
.cfi_def_cfa_offset 32
call _Z58__device_stub__Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPfPKfiPKiS0_S2_ifPf
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, .-_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ExpProbPolynomProbsImpl.hip"
.globl _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf # -- Begin function _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.p2align 4, 0x90
.type _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf,@function
_Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf: # @_Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 80(%rsp)
movq %rcx, 72(%rsp)
movq %r8, 64(%rsp)
movl %r9d, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 72(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rax
movq %rax, 128(%rsp)
leaq 8(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 176(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, .Lfunc_end0-_Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf,@object # @_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.section .rodata,"a",@progbits
.globl _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.p2align 3, 0x0
_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf:
.quad _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.size _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf"
.size .L__unnamed_1, 45
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z38__device_stub__ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z23ExpProbPolynomProbsImplPKfiPKiS0_S2_ifPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64
#define m 0.001/2000
#define c 10
#define rho0 1
#define p0 1
#define gamma 7
#define PI 3.14159265359f
//__device__ float calc_p(float rho){
// return c*c*rho0*(powf(rho/rho0,gamma) -1)/gamma+p0;
//}
__global__ void ker_dv(float *out, const float *x, const float *v, const float *rho, const int *ind, const float h)
{
//int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z
int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];
for (int i = istart; i < iend; i += Block_Size)
{
int id = i + threadIdx.x;
float xi[3];
float vi[3];
float rhoi;
if (id < iend)
{
xi[0] = x[3 * id + 0];
xi[1] = x[3 * id + 1];
xi[2] = x[3 * id + 2];
vi[0] = v[3 * id + 0];
vi[1] = v[3 * id + 1];
vi[2] = v[3 * id + 2];
rhoi = rho[id];
}
float dx[3];
float dv[3];
float r2;
float r;
float dW;
//float pi = calc_p(rhoi);
float pi = c*c*rho0*(powf(rhoi/rho0,gamma) -1)/gamma+p0;
float pj;
float dV[3] = {0,0,0};
__shared__ float xj[Block_Size * 3];
__shared__ float vj[Block_Size * 3];
__shared__ float rhoj[Block_Size];
for (int a = -1; a < 2; a++)
{
for (int b = -1; b < 2; b++)
{
if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
{
continue;
}
int Zstart = max((int)blockIdx.z - 1, 0);
int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);
int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];
for (int j = jstart; j < jend; j += Block_Size)
{
int jd = j + threadIdx.x;
if (jd < jend)
{
xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
vj[3 * threadIdx.x + 0] = v[3 * jd + 0];
vj[3 * threadIdx.x + 1] = v[3 * jd + 1];
vj[3 * threadIdx.x + 2] = v[3 * jd + 2];
rhoj[threadIdx.x] = rho[jd];
}
__syncthreads();
if (id < iend)
{
for (int k = 0; k < Block_Size; k++)
{
if (j + k < jend)
{
dx[0] = xj[3 * k + 0] - xi[0];
dx[1] = xj[3 * k + 1] - xi[1];
dx[2] = xj[3 * k + 2] - xi[2];
dv[0] = vj[3 * k + 0] - vi[0];
dv[1] = vj[3 * k + 1] - vi[1];
dv[2] = vj[3 * k + 2] - vi[2];
r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
if (r2 < 1.0)
{
r = sqrtf(r2+0.001*h*h);
dW = (1.0 - r);
dW *= dW*dW; //(1-r)^3
dW = -dW*r*20;
dW *= 21.0 / (2.0 * PI * h * h * h * h);
//pj = calc_p(rhoj[k]);
pj = c*c*rho0*(powf(rhoj[k]/rho0,gamma) -1)/gamma+p0;
float d = ( pi/(rhoi*rhoi) + pj/(rhoj[k]*rhoj[k]) );
d -= 2*(dv[0]*dx[0]+dv[1]*dx[1]+dv[2]*dx[2])/((r2+0.001*h*h)*rhoj[k]*rhoi);
d *= m*dW/r;
dV[0] += d*dx[0];
dV[1] += d*dx[1];
dV[2] += d*dx[2];
}
}
}
}
__syncthreads();
}
//ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
}
}
if (id < iend)
{
out[3*id+0] = dV[0] + 10*c*c*fmaxf(0.0,-xi[0])/h - 10*c*c*fmaxf(0.0,xi[0]-2)/h;
out[3*id+1] = dV[1] + 10*c*c*fmaxf(0.0,-xi[1])/h - 10*c*c*fmaxf(0.0,xi[1]-1)/h;
out[3*id+2] = dV[2] + 10*c*c*fmaxf(0.0,-xi[2])/h - 1;
}
}
} | .file "tmpxft_00141a95_00000000-6_ker_dv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif
.type _Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif, @function
_Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq ker_dv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif, .-_Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif
.globl ker_dv
.type ker_dv, @function
ker_dv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size ker_dv, .-ker_dv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ker_dv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq ker_dv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64
#define m 0.001/2000
#define c 10
#define rho0 1
#define p0 1
#define gamma 7
#define PI 3.14159265359f
//__device__ float calc_p(float rho){
// return c*c*rho0*(powf(rho/rho0,gamma) -1)/gamma+p0;
//}
__global__ void ker_dv(float *out, const float *x, const float *v, const float *rho, const int *ind, const float h)
{
//int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z
int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];
for (int i = istart; i < iend; i += Block_Size)
{
int id = i + threadIdx.x;
float xi[3];
float vi[3];
float rhoi;
if (id < iend)
{
xi[0] = x[3 * id + 0];
xi[1] = x[3 * id + 1];
xi[2] = x[3 * id + 2];
vi[0] = v[3 * id + 0];
vi[1] = v[3 * id + 1];
vi[2] = v[3 * id + 2];
rhoi = rho[id];
}
float dx[3];
float dv[3];
float r2;
float r;
float dW;
//float pi = calc_p(rhoi);
float pi = c*c*rho0*(powf(rhoi/rho0,gamma) -1)/gamma+p0;
float pj;
float dV[3] = {0,0,0};
__shared__ float xj[Block_Size * 3];
__shared__ float vj[Block_Size * 3];
__shared__ float rhoj[Block_Size];
for (int a = -1; a < 2; a++)
{
for (int b = -1; b < 2; b++)
{
if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
{
continue;
}
int Zstart = max((int)blockIdx.z - 1, 0);
int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);
int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];
for (int j = jstart; j < jend; j += Block_Size)
{
int jd = j + threadIdx.x;
if (jd < jend)
{
xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
vj[3 * threadIdx.x + 0] = v[3 * jd + 0];
vj[3 * threadIdx.x + 1] = v[3 * jd + 1];
vj[3 * threadIdx.x + 2] = v[3 * jd + 2];
rhoj[threadIdx.x] = rho[jd];
}
__syncthreads();
if (id < iend)
{
for (int k = 0; k < Block_Size; k++)
{
if (j + k < jend)
{
dx[0] = xj[3 * k + 0] - xi[0];
dx[1] = xj[3 * k + 1] - xi[1];
dx[2] = xj[3 * k + 2] - xi[2];
dv[0] = vj[3 * k + 0] - vi[0];
dv[1] = vj[3 * k + 1] - vi[1];
dv[2] = vj[3 * k + 2] - vi[2];
r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
if (r2 < 1.0)
{
r = sqrtf(r2+0.001*h*h);
dW = (1.0 - r);
dW *= dW*dW; //(1-r)^3
dW = -dW*r*20;
dW *= 21.0 / (2.0 * PI * h * h * h * h);
//pj = calc_p(rhoj[k]);
pj = c*c*rho0*(powf(rhoj[k]/rho0,gamma) -1)/gamma+p0;
float d = ( pi/(rhoi*rhoi) + pj/(rhoj[k]*rhoj[k]) );
d -= 2*(dv[0]*dx[0]+dv[1]*dx[1]+dv[2]*dx[2])/((r2+0.001*h*h)*rhoj[k]*rhoi);
d *= m*dW/r;
dV[0] += d*dx[0];
dV[1] += d*dx[1];
dV[2] += d*dx[2];
}
}
}
}
__syncthreads();
}
//ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
}
}
if (id < iend)
{
out[3*id+0] = dV[0] + 10*c*c*fmaxf(0.0,-xi[0])/h - 10*c*c*fmaxf(0.0,xi[0]-2)/h;
out[3*id+1] = dV[1] + 10*c*c*fmaxf(0.0,-xi[1])/h - 10*c*c*fmaxf(0.0,xi[1]-1)/h;
out[3*id+2] = dV[2] + 10*c*c*fmaxf(0.0,-xi[2])/h - 1;
}
}
} | #include <hip/hip_runtime.h>
extern "C"
//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64
#define m 0.001/2000
#define c 10
#define rho0 1
#define p0 1
#define gamma 7
#define PI 3.14159265359f
//__device__ float calc_p(float rho){
// return c*c*rho0*(powf(rho/rho0,gamma) -1)/gamma+p0;
//}
__global__ void ker_dv(float *out, const float *x, const float *v, const float *rho, const int *ind, const float h)
{
//int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z
int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];
for (int i = istart; i < iend; i += Block_Size)
{
int id = i + threadIdx.x;
float xi[3];
float vi[3];
float rhoi;
if (id < iend)
{
xi[0] = x[3 * id + 0];
xi[1] = x[3 * id + 1];
xi[2] = x[3 * id + 2];
vi[0] = v[3 * id + 0];
vi[1] = v[3 * id + 1];
vi[2] = v[3 * id + 2];
rhoi = rho[id];
}
float dx[3];
float dv[3];
float r2;
float r;
float dW;
//float pi = calc_p(rhoi);
float pi = c*c*rho0*(powf(rhoi/rho0,gamma) -1)/gamma+p0;
float pj;
float dV[3] = {0,0,0};
__shared__ float xj[Block_Size * 3];
__shared__ float vj[Block_Size * 3];
__shared__ float rhoj[Block_Size];
for (int a = -1; a < 2; a++)
{
for (int b = -1; b < 2; b++)
{
if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
{
continue;
}
int Zstart = max((int)blockIdx.z - 1, 0);
int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);
int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];
for (int j = jstart; j < jend; j += Block_Size)
{
int jd = j + threadIdx.x;
if (jd < jend)
{
xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
vj[3 * threadIdx.x + 0] = v[3 * jd + 0];
vj[3 * threadIdx.x + 1] = v[3 * jd + 1];
vj[3 * threadIdx.x + 2] = v[3 * jd + 2];
rhoj[threadIdx.x] = rho[jd];
}
__syncthreads();
if (id < iend)
{
for (int k = 0; k < Block_Size; k++)
{
if (j + k < jend)
{
dx[0] = xj[3 * k + 0] - xi[0];
dx[1] = xj[3 * k + 1] - xi[1];
dx[2] = xj[3 * k + 2] - xi[2];
dv[0] = vj[3 * k + 0] - vi[0];
dv[1] = vj[3 * k + 1] - vi[1];
dv[2] = vj[3 * k + 2] - vi[2];
r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
if (r2 < 1.0)
{
r = sqrtf(r2+0.001*h*h);
dW = (1.0 - r);
dW *= dW*dW; //(1-r)^3
dW = -dW*r*20;
dW *= 21.0 / (2.0 * PI * h * h * h * h);
//pj = calc_p(rhoj[k]);
pj = c*c*rho0*(powf(rhoj[k]/rho0,gamma) -1)/gamma+p0;
float d = ( pi/(rhoi*rhoi) + pj/(rhoj[k]*rhoj[k]) );
d -= 2*(dv[0]*dx[0]+dv[1]*dx[1]+dv[2]*dx[2])/((r2+0.001*h*h)*rhoj[k]*rhoi);
d *= m*dW/r;
dV[0] += d*dx[0];
dV[1] += d*dx[1];
dV[2] += d*dx[2];
}
}
}
}
__syncthreads();
}
//ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
}
}
if (id < iend)
{
out[3*id+0] = dV[0] + 10*c*c*fmaxf(0.0,-xi[0])/h - 10*c*c*fmaxf(0.0,xi[0]-2)/h;
out[3*id+1] = dV[1] + 10*c*c*fmaxf(0.0,-xi[1])/h - 10*c*c*fmaxf(0.0,xi[1]-1)/h;
out[3*id+2] = dV[2] + 10*c*c*fmaxf(0.0,-xi[2])/h - 1;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64
#define m 0.001/2000
#define c 10
#define rho0 1
#define p0 1
#define gamma 7
#define PI 3.14159265359f
//__device__ float calc_p(float rho){
// return c*c*rho0*(powf(rho/rho0,gamma) -1)/gamma+p0;
//}
__global__ void ker_dv(float *out, const float *x, const float *v, const float *rho, const int *ind, const float h)
{
//int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z
int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];
for (int i = istart; i < iend; i += Block_Size)
{
int id = i + threadIdx.x;
float xi[3];
float vi[3];
float rhoi;
if (id < iend)
{
xi[0] = x[3 * id + 0];
xi[1] = x[3 * id + 1];
xi[2] = x[3 * id + 2];
vi[0] = v[3 * id + 0];
vi[1] = v[3 * id + 1];
vi[2] = v[3 * id + 2];
rhoi = rho[id];
}
float dx[3];
float dv[3];
float r2;
float r;
float dW;
//float pi = calc_p(rhoi);
float pi = c*c*rho0*(powf(rhoi/rho0,gamma) -1)/gamma+p0;
float pj;
float dV[3] = {0,0,0};
__shared__ float xj[Block_Size * 3];
__shared__ float vj[Block_Size * 3];
__shared__ float rhoj[Block_Size];
for (int a = -1; a < 2; a++)
{
for (int b = -1; b < 2; b++)
{
if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
{
continue;
}
int Zstart = max((int)blockIdx.z - 1, 0);
int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);
int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];
for (int j = jstart; j < jend; j += Block_Size)
{
int jd = j + threadIdx.x;
if (jd < jend)
{
xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
vj[3 * threadIdx.x + 0] = v[3 * jd + 0];
vj[3 * threadIdx.x + 1] = v[3 * jd + 1];
vj[3 * threadIdx.x + 2] = v[3 * jd + 2];
rhoj[threadIdx.x] = rho[jd];
}
__syncthreads();
if (id < iend)
{
for (int k = 0; k < Block_Size; k++)
{
if (j + k < jend)
{
dx[0] = xj[3 * k + 0] - xi[0];
dx[1] = xj[3 * k + 1] - xi[1];
dx[2] = xj[3 * k + 2] - xi[2];
dv[0] = vj[3 * k + 0] - vi[0];
dv[1] = vj[3 * k + 1] - vi[1];
dv[2] = vj[3 * k + 2] - vi[2];
r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
if (r2 < 1.0)
{
r = sqrtf(r2+0.001*h*h);
dW = (1.0 - r);
dW *= dW*dW; //(1-r)^3
dW = -dW*r*20;
dW *= 21.0 / (2.0 * PI * h * h * h * h);
//pj = calc_p(rhoj[k]);
pj = c*c*rho0*(powf(rhoj[k]/rho0,gamma) -1)/gamma+p0;
float d = ( pi/(rhoi*rhoi) + pj/(rhoj[k]*rhoj[k]) );
d -= 2*(dv[0]*dx[0]+dv[1]*dx[1]+dv[2]*dx[2])/((r2+0.001*h*h)*rhoj[k]*rhoi);
d *= m*dW/r;
dV[0] += d*dx[0];
dV[1] += d*dx[1];
dV[2] += d*dx[2];
}
}
}
}
__syncthreads();
}
//ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
}
}
if (id < iend)
{
out[3*id+0] = dV[0] + 10*c*c*fmaxf(0.0,-xi[0])/h - 10*c*c*fmaxf(0.0,xi[0]-2)/h;
out[3*id+1] = dV[1] + 10*c*c*fmaxf(0.0,-xi[1])/h - 10*c*c*fmaxf(0.0,xi[1]-1)/h;
out[3*id+2] = dV[2] + 10*c*c*fmaxf(0.0,-xi[2])/h - 1;
}
}
} | .text
.file "ker_dv.hip"
.globl __device_stub__ker_dv # -- Begin function __device_stub__ker_dv
.p2align 4, 0x90
.type __device_stub__ker_dv,@function
__device_stub__ker_dv: # @__device_stub__ker_dv
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $ker_dv, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__ker_dv, .Lfunc_end0-__device_stub__ker_dv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ker_dv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type ker_dv,@object # @ker_dv
.section .rodata,"a",@progbits
.globl ker_dv
.p2align 3, 0x0
ker_dv:
.quad __device_stub__ker_dv
.size ker_dv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "ker_dv"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__ker_dv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym ker_dv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00141a95_00000000-6_ker_dv.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif
.type _Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif, @function
_Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq ker_dv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif, .-_Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif
.globl ker_dv
.type ker_dv, @function
ker_dv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z6ker_dvPfPKfS1_S1_PKifPfPKfS1_S1_PKif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size ker_dv, .-ker_dv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ker_dv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq ker_dv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ker_dv.hip"
.globl __device_stub__ker_dv # -- Begin function __device_stub__ker_dv
.p2align 4, 0x90
.type __device_stub__ker_dv,@function
__device_stub__ker_dv: # @__device_stub__ker_dv
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $ker_dv, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size __device_stub__ker_dv, .Lfunc_end0-__device_stub__ker_dv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ker_dv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type ker_dv,@object # @ker_dv
.section .rodata,"a",@progbits
.globl ker_dv
.p2align 3, 0x0
ker_dv:
.quad __device_stub__ker_dv
.size ker_dv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "ker_dv"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__ker_dv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym ker_dv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define N 1200
#define THREADS 1024
#include <stdio.h>
#include <math.h>
__global__ void vecAdd(int *a, int *b, int *c);
int main(){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
int size;
size = N*sizeof(int);
cudaMalloc((void**) &dev_a, size);
cudaMalloc((void**) &dev_b, size);
cudaMalloc((void**) &dev_c, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = b[i] = i;
c[i] = 0;
}
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
vecAdd<<<(int)ceil(THREADS/N),N>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++){
printf("c[%d] = %d\n", i, c[i]);
}
free(a);
free(b);
free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
exit(0);
}
__global__ void vecAdd(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i < N){
c[i] = a[i] + b[i];
printf("Sou a thread %d em %d\n", threadIdx.x, i);
}
} | code for sm_80
Function : _Z6vecAddPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R13, SR_CTAID.X ; /* 0x00000000000d7919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R12, SR_TID.X ; /* 0x00000000000c7919 */
/* 0x000e220000002100 */
/*0040*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0050*/ IMAD R13, R13, c[0x0][0x0], R12 ; /* 0x000000000d0d7a24 */
/* 0x001fca00078e020c */
/*0060*/ ISETP.GT.AND P0, PT, R13, 0x4af, PT ; /* 0x000004af0d00780c */
/* 0x000fda0003f04270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD.MOV.U32 R10, RZ, RZ, 0x4 ; /* 0x00000004ff0a7424 */
/* 0x000fe200078e00ff */
/*0090*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00a0*/ IMAD.WIDE R8, R13, R10, c[0x0][0x160] ; /* 0x000058000d087625 */
/* 0x000fc800078e020a */
/*00b0*/ IMAD.WIDE R4, R13.reuse, R10.reuse, c[0x0][0x168] ; /* 0x00005a000d047625 */
/* 0x0c0fe400078e020a */
/*00c0*/ LDG.E R9, [R8.64] ; /* 0x0000000408097981 */
/* 0x000ea8000c1e1900 */
/*00d0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0000a2000c1e1900 */
/*00e0*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*00f0*/ IMAD.WIDE R10, R13, R10, c[0x0][0x170] ; /* 0x00005c000d0a7625 */
/* 0x000fe400078e020a */
/*0100*/ STL.64 [R1], R12 ; /* 0x0000000c01007387 */
/* 0x0003e60000100a00 */
/*0110*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000ee20000000a00 */
/*0120*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fc400008e06ff */
/*0130*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x001fe400078e00ff */
/*0140*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.IADD R0, R0, 0x1, R9 ; /* 0x0000000100007824 */
/* 0x004fca00078e0209 */
/*0160*/ STG.E [R10.64], R0 ; /* 0x000000000a007986 */
/* 0x0003e4000c101904 */
/*0170*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x008fe40000000000 */
/*0180*/ MOV R11, 0x1f0 ; /* 0x000001f0000b7802 */
/* 0x002fe40000000f00 */
/*0190*/ MOV R20, 0x170 ; /* 0x0000017000147802 */
/* 0x000fe40000000f00 */
/*01a0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*01b0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*01c0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*01d0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*01e0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define N 1200
#define THREADS 1024
#include <stdio.h>
#include <math.h>
__global__ void vecAdd(int *a, int *b, int *c);
int main(){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
int size;
size = N*sizeof(int);
cudaMalloc((void**) &dev_a, size);
cudaMalloc((void**) &dev_b, size);
cudaMalloc((void**) &dev_c, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = b[i] = i;
c[i] = 0;
}
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
vecAdd<<<(int)ceil(THREADS/N),N>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++){
printf("c[%d] = %d\n", i, c[i]);
}
free(a);
free(b);
free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
exit(0);
}
__global__ void vecAdd(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i < N){
c[i] = a[i] + b[i];
printf("Sou a thread %d em %d\n", threadIdx.x, i);
}
} | .file "tmpxft_000e163e_00000000-6_vector_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecAddPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.globl _Z6vecAddPiS_S_
.type _Z6vecAddPiS_S_, @function
_Z6vecAddPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6vecAddPiS_S_, .-_Z6vecAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4800, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4800, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4800, %esi
call cudaMalloc@PLT
movl $4800, %edi
call malloc@PLT
movq %rax, %r13
movl $4800, %edi
call malloc@PLT
movq %rax, %r12
movl $4800, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%r13,%rax,4)
movl $0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $1200, %rax
jne .L12
movl $1, %ecx
movl $4800, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4800, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1200, 44(%rsp)
movl $1, 48(%rsp)
movl $0, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $4800, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r14
.L14:
movl 0(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1200, %rbx
jne .L14
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %edi
call exit@PLT
.L19:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6vecAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define N 1200
#define THREADS 1024
#include <stdio.h>
#include <math.h>
__global__ void vecAdd(int *a, int *b, int *c);
int main(){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
int size;
size = N*sizeof(int);
cudaMalloc((void**) &dev_a, size);
cudaMalloc((void**) &dev_b, size);
cudaMalloc((void**) &dev_c, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = b[i] = i;
c[i] = 0;
}
cudaMemcpy(dev_a, a, size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_b, b, size, cudaMemcpyHostToDevice);
vecAdd<<<(int)ceil(THREADS/N),N>>>(dev_a, dev_b, dev_c);
cudaMemcpy(c, dev_c, size, cudaMemcpyDeviceToHost);
for(int i = 0; i < N; i++){
printf("c[%d] = %d\n", i, c[i]);
}
free(a);
free(b);
free(c);
cudaFree(dev_a);
cudaFree(dev_b);
cudaFree(dev_c);
exit(0);
}
__global__ void vecAdd(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i < N){
c[i] = a[i] + b[i];
printf("Sou a thread %d em %d\n", threadIdx.x, i);
}
} | #define N 1200
#define THREADS 1024
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
__global__ void vecAdd(int *a, int *b, int *c);
int main(){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
int size;
size = N*sizeof(int);
hipMalloc((void**) &dev_a, size);
hipMalloc((void**) &dev_b, size);
hipMalloc((void**) &dev_c, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = b[i] = i;
c[i] = 0;
}
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
vecAdd<<<(int)ceil(THREADS/N),N>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++){
printf("c[%d] = %d\n", i, c[i]);
}
free(a);
free(b);
free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
exit(0);
}
__global__ void vecAdd(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i < N){
c[i] = a[i] + b[i];
printf("Sou a thread %d em %d\n", threadIdx.x, i);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define N 1200
#define THREADS 1024
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <math.h>
__global__ void vecAdd(int *a, int *b, int *c);
int main(){
int *a, *b, *c;
int *dev_a, *dev_b, *dev_c;
int size;
size = N*sizeof(int);
hipMalloc((void**) &dev_a, size);
hipMalloc((void**) &dev_b, size);
hipMalloc((void**) &dev_c, size);
a = (int *)malloc(size);
b = (int *)malloc(size);
c = (int *)malloc(size);
for(int i = 0; i < N; i++){
a[i] = b[i] = i;
c[i] = 0;
}
hipMemcpy(dev_a, a, size, hipMemcpyHostToDevice);
hipMemcpy(dev_b, b, size, hipMemcpyHostToDevice);
vecAdd<<<(int)ceil(THREADS/N),N>>>(dev_a, dev_b, dev_c);
hipMemcpy(c, dev_c, size, hipMemcpyDeviceToHost);
for(int i = 0; i < N; i++){
printf("c[%d] = %d\n", i, c[i]);
}
free(a);
free(b);
free(c);
hipFree(dev_a);
hipFree(dev_b);
hipFree(dev_c);
exit(0);
}
__global__ void vecAdd(int *a, int *b, int *c){
int i = blockIdx.x*blockDim.x + threadIdx.x;
if(i < N){
c[i] = a[i] + b[i];
printf("Sou a thread %d em %d\n", threadIdx.x, i);
}
} | .text
.file "vector_sum.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $4800, %esi # imm = 0x12C0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4800, %esi # imm = 0x12C0
callq hipMalloc
movq %rsp, %rdi
movl $4800, %esi # imm = 0x12C0
callq hipMalloc
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %rbx
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r14
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4800, %edx # imm = 0x12C0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %r12d, (%r14,%r12,4)
movl %r12d, (%rbx,%r12,4)
incq %r12
cmpq $1200, %r12 # imm = 0x4B0
jne .LBB0_1
# %bb.2:
movq 16(%rsp), %rdi
movl $4800, %edx # imm = 0x12C0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4800, %edx # imm = 0x12C0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdi # imm = 0x100000000
leaq 1200(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
movq (%rsp), %rsi
movl $4800, %edx # imm = 0x12C0
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1200, %r12 # imm = 0x4B0
jne .LBB0_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z21__device_stub__vecAddPiS_S_ # -- Begin function _Z21__device_stub__vecAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPiS_S_,@function
_Z21__device_stub__vecAddPiS_S_: # @_Z21__device_stub__vecAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__vecAddPiS_S_, .Lfunc_end1-_Z21__device_stub__vecAddPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPiS_S_,@object # @_Z6vecAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPiS_S_
.p2align 3, 0x0
_Z6vecAddPiS_S_:
.quad _Z21__device_stub__vecAddPiS_S_
.size _Z6vecAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[%d] = %d\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000e163e_00000000-6_vector_sum.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.type _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, @function
_Z29__device_stub__Z6vecAddPiS_S_PiS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPiS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z6vecAddPiS_S_PiS_S_, .-_Z29__device_stub__Z6vecAddPiS_S_PiS_S_
.globl _Z6vecAddPiS_S_
.type _Z6vecAddPiS_S_, @function
_Z6vecAddPiS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6vecAddPiS_S_, .-_Z6vecAddPiS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "c[%d] = %d\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4800, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $4800, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $4800, %esi
call cudaMalloc@PLT
movl $4800, %edi
call malloc@PLT
movq %rax, %r13
movl $4800, %edi
call malloc@PLT
movq %rax, %r12
movl $4800, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L12:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%r13,%rax,4)
movl $0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $1200, %rax
jne .L12
movl $1, %ecx
movl $4800, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4800, %edx
movq %r12, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1200, 44(%rsp)
movl $1, 48(%rsp)
movl $0, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L13:
movl $2, %ecx
movl $4800, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC0(%rip), %r14
.L14:
movl 0(%rbp,%rbx,4), %ecx
movl %ebx, %edx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $1200, %rbx
jne .L14
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movl $0, %edi
call exit@PLT
.L19:
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z6vecAddPiS_S_PiS_S_
jmp .L13
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z6vecAddPiS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPiS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "vector_sum.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 16(%rsp), %rdi
movl $4800, %esi # imm = 0x12C0
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4800, %esi # imm = 0x12C0
callq hipMalloc
movq %rsp, %rdi
movl $4800, %esi # imm = 0x12C0
callq hipMalloc
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %rbx
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r14
movl $4800, %edi # imm = 0x12C0
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
movl $4800, %edx # imm = 0x12C0
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl %r12d, (%r14,%r12,4)
movl %r12d, (%rbx,%r12,4)
incq %r12
cmpq $1200, %r12 # imm = 0x4B0
jne .LBB0_1
# %bb.2:
movq 16(%rsp), %rdi
movl $4800, %edx # imm = 0x12C0
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4800, %edx # imm = 0x12C0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdi # imm = 0x100000000
leaq 1200(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB0_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movq %rdx, 72(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB0_4:
movq (%rsp), %rsi
movl $4800, %edx # imm = 0x12C0
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %edx
movl $.L.str, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
incq %r12
cmpq $1200, %r12 # imm = 0x4B0
jne .LBB0_5
# %bb.6:
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
xorl %edi, %edi
callq exit
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.globl _Z21__device_stub__vecAddPiS_S_ # -- Begin function _Z21__device_stub__vecAddPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPiS_S_,@function
_Z21__device_stub__vecAddPiS_S_: # @_Z21__device_stub__vecAddPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z21__device_stub__vecAddPiS_S_, .Lfunc_end1-_Z21__device_stub__vecAddPiS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPiS_S_,@object # @_Z6vecAddPiS_S_
.section .rodata,"a",@progbits
.globl _Z6vecAddPiS_S_
.p2align 3, 0x0
_Z6vecAddPiS_S_:
.quad _Z21__device_stub__vecAddPiS_S_
.size _Z6vecAddPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "c[%d] = %d\n"
.size .L.str, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPiS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //pass
//--blockDim=256 --gridDim=2 -DWIDTH=2064 --no-inline
#include <cuda.h>
#include <stdio.h>
#define GRIDDIM 1
#define BLOCKDIM 2//256
#define WIDTH 2//2048
#define N WIDTH
/*
* This kernel demonstrates a blockwise strength-reduction loop.
* Each block is given a disjoint partition (of length WIDTH) of A.
* Then each thread writes multiple elements in the partition.
* It is not necessarily the case that WIDTH%blockDim.x == 0
*/
__global__ void k(int *A) {
// __assert(blockDim.x <= WIDTH);
//#ifdef BLOCK_DIVIDES_WIDTH
// //__assert(__mod_pow2(WIDTH, blockDim.x) == 0);
//#endif
for (int i=threadIdx.x; i<WIDTH; i+=blockDim.x) {
//#ifndef BLOCK_DIVIDES_WIDTH
// // working set(1) using global invariants
// /*A*/__global_invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__global_invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(i % blockDim.x == threadIdx.x),
// __global_invariant(__write_implies(A, (((__write_offset_bytes(A)/sizeof(int)) % WIDTH) % blockDim.x) == threadIdx.x)),
//#else
// // working set(2) iff WIDTH % blockDim.x == 0
// /*A*/__invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(__uniform_int((i-threadIdx.x))),
// __invariant(__uniform_bool(__enabled())),
//#endif
A[blockIdx.x*WIDTH+i] = i;
}
//#ifdef FORCE_FAIL
// __assert(false);
//#endif
} | code for sm_80
Function : _Z1kPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0070*/ IMAD R2, R0, 0x2, R5 ; /* 0x0000000200027824 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0007 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*00a0*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x001fc80007ffe0ff */
/*00b0*/ ISETP.GE.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 BRA 0x70 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //pass
//--blockDim=256 --gridDim=2 -DWIDTH=2064 --no-inline
#include <cuda.h>
#include <stdio.h>
#define GRIDDIM 1
#define BLOCKDIM 2//256
#define WIDTH 2//2048
#define N WIDTH
/*
* This kernel demonstrates a blockwise strength-reduction loop.
* Each block is given a disjoint partition (of length WIDTH) of A.
* Then each thread writes multiple elements in the partition.
* It is not necessarily the case that WIDTH%blockDim.x == 0
*/
__global__ void k(int *A) {
// __assert(blockDim.x <= WIDTH);
//#ifdef BLOCK_DIVIDES_WIDTH
// //__assert(__mod_pow2(WIDTH, blockDim.x) == 0);
//#endif
for (int i=threadIdx.x; i<WIDTH; i+=blockDim.x) {
//#ifndef BLOCK_DIVIDES_WIDTH
// // working set(1) using global invariants
// /*A*/__global_invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__global_invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(i % blockDim.x == threadIdx.x),
// __global_invariant(__write_implies(A, (((__write_offset_bytes(A)/sizeof(int)) % WIDTH) % blockDim.x) == threadIdx.x)),
//#else
// // working set(2) iff WIDTH % blockDim.x == 0
// /*A*/__invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(__uniform_int((i-threadIdx.x))),
// __invariant(__uniform_bool(__enabled())),
//#endif
A[blockIdx.x*WIDTH+i] = i;
}
//#ifdef FORCE_FAIL
// __assert(false);
//#endif
} | .file "tmpxft_00054219_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z1kPiPi
.type _Z20__device_stub__Z1kPiPi, @function
_Z20__device_stub__Z1kPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z1kPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z20__device_stub__Z1kPiPi, .-_Z20__device_stub__Z1kPiPi
.globl _Z1kPi
.type _Z1kPi, @function
_Z1kPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z1kPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z1kPi, .-_Z1kPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1kPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1kPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //pass
//--blockDim=256 --gridDim=2 -DWIDTH=2064 --no-inline
#include <cuda.h>
#include <stdio.h>
#define GRIDDIM 1
#define BLOCKDIM 2//256
#define WIDTH 2//2048
#define N WIDTH
/*
* This kernel demonstrates a blockwise strength-reduction loop.
* Each block is given a disjoint partition (of length WIDTH) of A.
* Then each thread writes multiple elements in the partition.
* It is not necessarily the case that WIDTH%blockDim.x == 0
*/
__global__ void k(int *A) {
// __assert(blockDim.x <= WIDTH);
//#ifdef BLOCK_DIVIDES_WIDTH
// //__assert(__mod_pow2(WIDTH, blockDim.x) == 0);
//#endif
for (int i=threadIdx.x; i<WIDTH; i+=blockDim.x) {
//#ifndef BLOCK_DIVIDES_WIDTH
// // working set(1) using global invariants
// /*A*/__global_invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__global_invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(i % blockDim.x == threadIdx.x),
// __global_invariant(__write_implies(A, (((__write_offset_bytes(A)/sizeof(int)) % WIDTH) % blockDim.x) == threadIdx.x)),
//#else
// // working set(2) iff WIDTH % blockDim.x == 0
// /*A*/__invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(__uniform_int((i-threadIdx.x))),
// __invariant(__uniform_bool(__enabled())),
//#endif
A[blockIdx.x*WIDTH+i] = i;
}
//#ifdef FORCE_FAIL
// __assert(false);
//#endif
} | //pass
//--blockDim=256 --gridDim=2 -DWIDTH=2064 --no-inline
#include <hip/hip_runtime.h>
#include <stdio.h>
#define GRIDDIM 1
#define BLOCKDIM 2//256
#define WIDTH 2//2048
#define N WIDTH
/*
* This kernel demonstrates a blockwise strength-reduction loop.
* Each block is given a disjoint partition (of length WIDTH) of A.
* Then each thread writes multiple elements in the partition.
* It is not necessarily the case that WIDTH%blockDim.x == 0
*/
__global__ void k(int *A) {
// __assert(blockDim.x <= WIDTH);
//#ifdef BLOCK_DIVIDES_WIDTH
// //__assert(__mod_pow2(WIDTH, blockDim.x) == 0);
//#endif
for (int i=threadIdx.x; i<WIDTH; i+=blockDim.x) {
//#ifndef BLOCK_DIVIDES_WIDTH
// // working set(1) using global invariants
// /*A*/__global_invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__global_invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(i % blockDim.x == threadIdx.x),
// __global_invariant(__write_implies(A, (((__write_offset_bytes(A)/sizeof(int)) % WIDTH) % blockDim.x) == threadIdx.x)),
//#else
// // working set(2) iff WIDTH % blockDim.x == 0
// /*A*/__invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(__uniform_int((i-threadIdx.x))),
// __invariant(__uniform_bool(__enabled())),
//#endif
A[blockIdx.x*WIDTH+i] = i;
}
//#ifdef FORCE_FAIL
// __assert(false);
//#endif
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //pass
//--blockDim=256 --gridDim=2 -DWIDTH=2064 --no-inline
#include <hip/hip_runtime.h>
#include <stdio.h>
#define GRIDDIM 1
#define BLOCKDIM 2//256
#define WIDTH 2//2048
#define N WIDTH
/*
* This kernel demonstrates a blockwise strength-reduction loop.
* Each block is given a disjoint partition (of length WIDTH) of A.
* Then each thread writes multiple elements in the partition.
* It is not necessarily the case that WIDTH%blockDim.x == 0
*/
__global__ void k(int *A) {
// __assert(blockDim.x <= WIDTH);
//#ifdef BLOCK_DIVIDES_WIDTH
// //__assert(__mod_pow2(WIDTH, blockDim.x) == 0);
//#endif
for (int i=threadIdx.x; i<WIDTH; i+=blockDim.x) {
//#ifndef BLOCK_DIVIDES_WIDTH
// // working set(1) using global invariants
// /*A*/__global_invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__global_invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(i % blockDim.x == threadIdx.x),
// __global_invariant(__write_implies(A, (((__write_offset_bytes(A)/sizeof(int)) % WIDTH) % blockDim.x) == threadIdx.x)),
//#else
// // working set(2) iff WIDTH % blockDim.x == 0
// /*A*/__invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(__uniform_int((i-threadIdx.x))),
// __invariant(__uniform_bool(__enabled())),
//#endif
A[blockIdx.x*WIDTH+i] = i;
}
//#ifdef FORCE_FAIL
// __assert(false);
//#endif
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1kPi
.globl _Z1kPi
.p2align 8
.type _Z1kPi,@function
_Z1kPi:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x0
s_lshl_b32 s0, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, v0, s0
v_add_co_ci_u32_e64 v2, null, 0, 0, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s4, 0xffff
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_mov_b32 s2, 0
s_lshl_b32 s3, s1, 2
s_mov_b32 s4, s2
.LBB0_2:
global_store_b32 v[1:2], v0, off
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v1, s0, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, s0, s2, v2, s0
v_cmp_lt_u32_e32 vcc_lo, 1, v0
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1kPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1kPi, .Lfunc_end0-_Z1kPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1kPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z1kPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //pass
//--blockDim=256 --gridDim=2 -DWIDTH=2064 --no-inline
#include <hip/hip_runtime.h>
#include <stdio.h>
#define GRIDDIM 1
#define BLOCKDIM 2//256
#define WIDTH 2//2048
#define N WIDTH
/*
* This kernel demonstrates a blockwise strength-reduction loop.
* Each block is given a disjoint partition (of length WIDTH) of A.
* Then each thread writes multiple elements in the partition.
* It is not necessarily the case that WIDTH%blockDim.x == 0
*/
__global__ void k(int *A) {
// __assert(blockDim.x <= WIDTH);
//#ifdef BLOCK_DIVIDES_WIDTH
// //__assert(__mod_pow2(WIDTH, blockDim.x) == 0);
//#endif
for (int i=threadIdx.x; i<WIDTH; i+=blockDim.x) {
//#ifndef BLOCK_DIVIDES_WIDTH
// // working set(1) using global invariants
// /*A*/__global_invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__global_invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(i % blockDim.x == threadIdx.x),
// __global_invariant(__write_implies(A, (((__write_offset_bytes(A)/sizeof(int)) % WIDTH) % blockDim.x) == threadIdx.x)),
//#else
// // working set(2) iff WIDTH % blockDim.x == 0
// /*A*/__invariant(__write_implies(A, (blockIdx.x*WIDTH) <= __write_offset_bytes(A)/sizeof(int))),
// /*B*/__invariant(__write_implies(A, __write_offset_bytes(A)/sizeof(int) < (blockIdx.x+1)*WIDTH)),
// /*C*/__invariant(threadIdx.x <= i),
// /*D*/__invariant( i <= WIDTH+blockDim.x),
// __invariant(__uniform_int((i-threadIdx.x))),
// __invariant(__uniform_bool(__enabled())),
//#endif
A[blockIdx.x*WIDTH+i] = i;
}
//#ifdef FORCE_FAIL
// __assert(false);
//#endif
} | .text
.file "main.hip"
.globl _Z16__device_stub__kPi # -- Begin function _Z16__device_stub__kPi
.p2align 4, 0x90
.type _Z16__device_stub__kPi,@function
_Z16__device_stub__kPi: # @_Z16__device_stub__kPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1kPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z16__device_stub__kPi, .Lfunc_end0-_Z16__device_stub__kPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1kPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1kPi,@object # @_Z1kPi
.section .rodata,"a",@progbits
.globl _Z1kPi
.p2align 3, 0x0
_Z1kPi:
.quad _Z16__device_stub__kPi
.size _Z1kPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1kPi"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__kPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1kPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z1kPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0020*/ ISETP.GT.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x001fda0003f04270 */
/*0030*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0050*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0070*/ IMAD R2, R0, 0x2, R5 ; /* 0x0000000200027824 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0007 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*00a0*/ IADD3 R5, R5, c[0x0][0x0], RZ ; /* 0x0000000005057a10 */
/* 0x001fc80007ffe0ff */
/*00b0*/ ISETP.GE.AND P0, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fda0003f06270 */
/*00c0*/ @!P0 BRA 0x70 ; /* 0xffffffa000008947 */
/* 0x000fea000383ffff */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z1kPi
.globl _Z1kPi
.p2align 8
.type _Z1kPi,@function
_Z1kPi:
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 2, v0
s_cbranch_execz .LBB0_3
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[2:3], s[0:1], 0x0
s_lshl_b32 s0, s15, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v1, s0, v0, s0
v_add_co_ci_u32_e64 v2, null, 0, 0, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_and_b32 s1, s4, 0xffff
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_mov_b32 s2, 0
s_lshl_b32 s3, s1, 2
s_mov_b32 s4, s2
.LBB0_2:
global_store_b32 v[1:2], v0, off
v_add_nc_u32_e32 v0, s1, v0
v_add_co_u32 v1, s0, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v2, s0, s2, v2, s0
v_cmp_lt_u32_e32 vcc_lo, 1, v0
s_or_b32 s4, vcc_lo, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s4
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z1kPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z1kPi, .Lfunc_end0-_Z1kPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z1kPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z1kPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00054219_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z20__device_stub__Z1kPiPi
.type _Z20__device_stub__Z1kPiPi, @function
_Z20__device_stub__Z1kPiPi:
.LFB2081:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z1kPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z20__device_stub__Z1kPiPi, .-_Z20__device_stub__Z1kPiPi
.globl _Z1kPi
.type _Z1kPi, @function
_Z1kPi:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z20__device_stub__Z1kPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z1kPi, .-_Z1kPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z1kPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z1kPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z16__device_stub__kPi # -- Begin function _Z16__device_stub__kPi
.p2align 4, 0x90
.type _Z16__device_stub__kPi,@function
_Z16__device_stub__kPi: # @_Z16__device_stub__kPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z1kPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z16__device_stub__kPi, .Lfunc_end0-_Z16__device_stub__kPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z1kPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z1kPi,@object # @_Z1kPi
.section .rodata,"a",@progbits
.globl _Z1kPi
.p2align 3, 0x0
_Z1kPi:
.quad _Z16__device_stub__kPi
.size _Z1kPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z1kPi"
.size .L__unnamed_1, 7
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z16__device_stub__kPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z1kPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define THREAD_PER_BLOCK 1024
#define RADIUS 1000
__global__ void cudaVecAddKernel(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
c[id] = a[id] + b[id];
}
}
/**
* an optimized stencial_add kernel with shared_memory
* the motivation here is that each element is loaded by threads (2*radius+1) times.
* we definitely want to optimize it.
*/
__global__ void cudaStencialAddKernel_optimized(int* a, int* c, int size)
{
__shared__ int temp[THREAD_PER_BLOCK + RADIUS * 2];
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size) return;
// all threads within the block collaboratievly load the
// data required into the on-chip shared memory.
int sid = threadIdx.x + RADIUS;
temp[sid] = a[id];
int offset1 = THREAD_PER_BLOCK + RADIUS;
if (threadIdx.x < RADIUS) {
int id1 = id - RADIUS;
if (id1 >= 0) temp[threadIdx.x] = a[id1];
int id2 = id + THREAD_PER_BLOCK;
if (id2 < size) temp[threadIdx.x + offset1] = a[id2];
}
__syncthreads(); //synchronize to ensure all data are available
// perfrom stencil add on the shared memory
int offset2 = blockIdx.x * blockDim.x - RADIUS;
for (int i = threadIdx.x; i <= threadIdx.x + RADIUS * 2; i++)
{
int g_i = offset2 + i;
if (g_i < 0 || g_i >= size) continue;
c[id] += temp[i];
}
}
__global__ void cudaSencialAddKernel(int* a, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
for (int i = id - RADIUS; i <= id + RADIUS; i++)
{
if (i < 0 || i >= size) continue;
c[id] += a[i];
}
}
}
void cudaVecAdd(int* a, int* b, int* c, int size)
{
cudaVecAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(a, b, c, size);
}
void cudaStencialAdd(int* a, int *c, int size)
{
cudaSencialAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
}
void cudaStencialAdd_optimized(int* a, int *c, int size)
{
cudaStencialAddKernel_optimized <<< (size + THREAD_PER_BLOCK - 1) / THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
} | code for sm_80
Function : _Z20cudaSencialAddKernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R2, c[0x0][0x0], R5 ; /* 0x0000000002047a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R3, R4.reuse, 0x3e8, RZ ; /* 0x000003e804037810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a02 */
/*0080*/ IADD3 R0, R4, -0x3e8, RZ ; /* 0xfffffc1804007810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ BSSY B0, 0x270 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*00c0*/ IMNMX R3, R3, R0, !PT ; /* 0x0000000003037217 */
/* 0x000fc80007800200 */
/*00d0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ IADD3 R3, R3, 0x3e8, RZ ; /* 0x000003e803037810 */
/* 0x000fc60007ffe0ff */
/*00f0*/ IMAD R2, R6.reuse, c[0x0][0x0], R2 ; /* 0x0000000006027a24 */
/* 0x040fe400078e0202 */
/*0100*/ IMAD R3, R6, c[0x0][0x0], R3 ; /* 0x0000000006037a24 */
/* 0x000fe400078e0203 */
/*0110*/ IMAD.IADD R2, R2, 0x1, -R5.reuse ; /* 0x0000000102027824 */
/* 0x100fe400078e0a05 */
/*0120*/ IMAD.IADD R3, R3, 0x1, -R5 ; /* 0x0000000103037824 */
/* 0x000fc600078e0a05 */
/*0130*/ LOP3.LUT P0, R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe4000780c0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*0150*/ IMAD.WIDE R2, R4, R7, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fd400078e0207 */
/*0160*/ @!P0 BRA 0x260 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*0190*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06270 */
/*01a0*/ ISETP.LT.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000701670 */
/*01b0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff068224 */
/* 0x000fe200078e0008 */
/*01c0*/ @!P0 LDG.E R9, [R2.64] ; /* 0x0000000402098981 */
/* 0x001eaa000c1e1900 */
/*01d0*/ @!P0 LDG.E R6, [R6.64] ; /* 0x0000000406068981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.NE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f45270 */
/*0210*/ @!P0 IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106098824 */
/* 0x004fca00078e0209 */
/*0220*/ @!P0 STG.E [R2.64], R9 ; /* 0x0000000902008986 */
/* 0x0001e2000c101904 */
/*0230*/ IADD3 R8, P0, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fca0007f1e0ff */
/*0240*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0607 */
/*0250*/ @P2 BRA 0x190 ; /* 0xffffff3000002947 */
/* 0x000fea000383ffff */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R9, R4, 0x3e5, RZ ; /* 0x000003e504097810 */
/* 0x001fc60007ffe0ff */
/*02a0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*02b0*/ ISETP.GE.AND P1, PT, R0.reuse, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x040fe20003f26270 */
/*02c0*/ BSSY B0, 0x3c0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*02d0*/ IADD3 R4, R0.reuse, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x040fe40007ffe0ff */
/*02e0*/ ISETP.LT.OR P1, PT, R0.reuse, RZ, P1 ; /* 0x000000ff0000720c */
/* 0x040fe40000f21670 */
/*02f0*/ IADD3 R5, R0, 0x2, RZ ; /* 0x0000000200057810 */
/* 0x000fe40007ffe0ff */
/*0300*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f46270 */
/*0310*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0320*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe20003f06270 */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0340*/ ISETP.LT.OR P2, PT, R0, -0x1, P2 ; /* 0xffffffff0000780c */
/* 0x000fc40001741670 */
/*0350*/ ISETP.LT.OR P0, PT, R0, -0x2, P0 ; /* 0xfffffffe0000780c */
/* 0x000fc60000701670 */
/*0360*/ @P1 BRA 0x3b0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0390*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x004fca00078e0207 */
/*03a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*03b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03c0*/ BSSY B0, 0x430 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*03d0*/ @P2 BRA 0x420 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x001ea8000c1e1900 */
/*03f0*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040404067981 */
/* 0x000ea4000c1e1900 */
/*0400*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x004fca00078e0207 */
/*0410*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ BSSY B0, 0x4a0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0440*/ @P0 BRA 0x490 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x001ea8000c1e1900 */
/*0460*/ LDG.E R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ea4000c1e1900 */
/*0470*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x004fca00078e0207 */
/*0480*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04a0*/ IADD3 R6, R0, 0x3, RZ ; /* 0x0000000300067810 */
/* 0x000fc80007ffe0ff */
/*04b0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fc80003f06270 */
/*04c0*/ ISETP.LT.OR P0, PT, R0, -0x3, P0 ; /* 0xfffffffd0000780c */
/* 0x000fda0000701670 */
/*04d0*/ @!P0 LDG.E R7, [R2.64] ; /* 0x0000000402078981 */
/* 0x001ea8000c1e1900 */
/*04e0*/ @!P0 LDG.E R6, [R4.64+0xc] ; /* 0x00000c0404068981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ @!P0 IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106078824 */
/* 0x004fe200078e0207 */
/*0500*/ IADD3 R6, P1, R4, 0x10, RZ ; /* 0x0000001004067810 */
/* 0x000fc80007f3e0ff */
/*0510*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e2000c101904 */
/*0520*/ ISETP.GE.AND P0, PT, R0.reuse, R9, PT ; /* 0x000000090000720c */
/* 0x040fe40003f06270 */
/*0530*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD.X R7, RZ, RZ, R5, P1 ; /* 0x000000ffff077224 */
/* 0x001fd400008e0605 */
/*0550*/ @!P0 BRA 0x2b0 ; /* 0xfffffd5000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z31cudaStencialAddKernel_optimizedPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R4 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.GT.U32.AND P1, PT, R4.reuse, 0x3e7, PT ; /* 0x000003e70400780c */
/* 0x040fe20003f24070 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*00c0*/ ISETP.GT.U32.AND P0, PT, R4.reuse, -0x7d1, PT ; /* 0xfffff82f0400780c */
/* 0x040fe20003f04070 */
/*00d0*/ IMAD.SHL.U32 R6, R4, 0x4, RZ ; /* 0x0000000404067824 */
/* 0x000fe200078e00ff */
/*00e0*/ STS [R4.X4+0xfa0], R5 ; /* 0x000fa00504007388 */
/* 0x0041f20000004800 */
/*00f0*/ @P1 BRA 0x170 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R5, R0.reuse, 0x400, RZ ; /* 0x0000040000057810 */
/* 0x041fe40007ffe0ff */
/*0110*/ ISETP.GE.AND P1, PT, R0, 0x3e8, PT ; /* 0x000003e80000780c */
/* 0x000fc40003f26270 */
/*0120*/ ISETP.GE.AND P2, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fd60003f46270 */
/*0130*/ @P1 LDG.E R5, [R2.64+-0xfa0] ; /* 0xfff0600402051981 */
/* 0x000ea8000c1e1900 */
/*0140*/ @!P2 LDG.E R7, [R2.64+0x1000] ; /* 0x001000040207a981 */
/* 0x000ee8000c1e1900 */
/*0150*/ @P1 STS [R6], R5 ; /* 0x0000000506001388 */
/* 0x0041e80000000800 */
/*0160*/ @!P2 STS [R6+0x1fa0], R7 ; /* 0x001fa0070600a388 */
/* 0x0081e40000000800 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078010ff */
/*01b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc40000011400 */
/*01c0*/ IADD3 R5, R0, -0x3e8, RZ ; /* 0xfffffc1800057810 */
/* 0x001fe40007ffe0ff */
/*01d0*/ IADD3 R9, R4, 0x7d0, RZ ; /* 0x000007d004097810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe400000f1403 */
/*01f0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc80003f06270 */
/*0200*/ ISETP.LT.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000701670 */
/*0210*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000402008981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*0240*/ @!P0 LDS R7, [R6] ; /* 0x0000000006078984 */
/* 0x0000a40000000800 */
/*0250*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fe20007ffe0ff */
/*0260*/ @!P0 IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100078824 */
/* 0x004fca00078e0207 */
/*0270*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e2000c101904 */
/*0280*/ ISETP.GT.U32.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fda0003f04070 */
/*0290*/ @!P0 BRA 0x1f0 ; /* 0xffffff5000008947 */
/* 0x001fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16cudaVecAddKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define THREAD_PER_BLOCK 1024
#define RADIUS 1000
__global__ void cudaVecAddKernel(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
c[id] = a[id] + b[id];
}
}
/**
* an optimized stencial_add kernel with shared_memory
* the motivation here is that each element is loaded by threads (2*radius+1) times.
* we definitely want to optimize it.
*/
__global__ void cudaStencialAddKernel_optimized(int* a, int* c, int size)
{
__shared__ int temp[THREAD_PER_BLOCK + RADIUS * 2];
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size) return;
// all threads within the block collaboratievly load the
// data required into the on-chip shared memory.
int sid = threadIdx.x + RADIUS;
temp[sid] = a[id];
int offset1 = THREAD_PER_BLOCK + RADIUS;
if (threadIdx.x < RADIUS) {
int id1 = id - RADIUS;
if (id1 >= 0) temp[threadIdx.x] = a[id1];
int id2 = id + THREAD_PER_BLOCK;
if (id2 < size) temp[threadIdx.x + offset1] = a[id2];
}
__syncthreads(); //synchronize to ensure all data are available
// perfrom stencil add on the shared memory
int offset2 = blockIdx.x * blockDim.x - RADIUS;
for (int i = threadIdx.x; i <= threadIdx.x + RADIUS * 2; i++)
{
int g_i = offset2 + i;
if (g_i < 0 || g_i >= size) continue;
c[id] += temp[i];
}
}
__global__ void cudaSencialAddKernel(int* a, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
for (int i = id - RADIUS; i <= id + RADIUS; i++)
{
if (i < 0 || i >= size) continue;
c[id] += a[i];
}
}
}
void cudaVecAdd(int* a, int* b, int* c, int size)
{
cudaVecAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(a, b, c, size);
}
void cudaStencialAdd(int* a, int *c, int size)
{
cudaSencialAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
}
void cudaStencialAdd_optimized(int* a, int *c, int size)
{
cudaStencialAddKernel_optimized <<< (size + THREAD_PER_BLOCK - 1) / THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
} | .file "tmpxft_0014e112_00000000-6_CUDAtest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i
.type _Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i, @function
_Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16cudaVecAddKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i, .-_Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i
.globl _Z16cudaVecAddKernelPiS_S_i
.type _Z16cudaVecAddKernelPiS_S_i, @function
_Z16cudaVecAddKernelPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16cudaVecAddKernelPiS_S_i, .-_Z16cudaVecAddKernelPiS_S_i
.globl _Z10cudaVecAddPiS_S_i
.type _Z10cudaVecAddPiS_S_i, @function
_Z10cudaVecAddPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
leal 2046(%rcx), %eax
movl %ecx, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z10cudaVecAddPiS_S_i, .-_Z10cudaVecAddPiS_S_i
.globl _Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i
.type _Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i, @function
_Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z31cudaStencialAddKernel_optimizedPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i, .-_Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i
.globl _Z31cudaStencialAddKernel_optimizedPiS_i
.type _Z31cudaStencialAddKernel_optimizedPiS_i, @function
_Z31cudaStencialAddKernel_optimizedPiS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z31cudaStencialAddKernel_optimizedPiS_i, .-_Z31cudaStencialAddKernel_optimizedPiS_i
.globl _Z25cudaStencialAdd_optimizedPiS_i
.type _Z25cudaStencialAdd_optimizedPiS_i, @function
_Z25cudaStencialAdd_optimizedPiS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i
jmp .L23
.cfi_endproc
.LFE2059:
.size _Z25cudaStencialAdd_optimizedPiS_i, .-_Z25cudaStencialAdd_optimizedPiS_i
.globl _Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i
.type _Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i, @function
_Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20cudaSencialAddKernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i, .-_Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i
.globl _Z20cudaSencialAddKernelPiS_i
.type _Z20cudaSencialAddKernelPiS_i, @function
_Z20cudaSencialAddKernelPiS_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z20cudaSencialAddKernelPiS_i, .-_Z20cudaSencialAddKernelPiS_i
.globl _Z15cudaStencialAddPiS_i
.type _Z15cudaStencialAddPiS_i, @function
_Z15cudaStencialAddPiS_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i
jmp .L35
.cfi_endproc
.LFE2058:
.size _Z15cudaStencialAddPiS_i, .-_Z15cudaStencialAddPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20cudaSencialAddKernelPiS_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z31cudaStencialAddKernel_optimizedPiS_i"
.section .rodata.str1.1
.LC2:
.string "_Z16cudaVecAddKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20cudaSencialAddKernelPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z31cudaStencialAddKernel_optimizedPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16cudaVecAddKernelPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <cuda.h>
#include <cuda_runtime.h>
#define THREAD_PER_BLOCK 1024
#define RADIUS 1000
__global__ void cudaVecAddKernel(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
c[id] = a[id] + b[id];
}
}
/**
* an optimized stencial_add kernel with shared_memory
* the motivation here is that each element is loaded by threads (2*radius+1) times.
* we definitely want to optimize it.
*/
__global__ void cudaStencialAddKernel_optimized(int* a, int* c, int size)
{
__shared__ int temp[THREAD_PER_BLOCK + RADIUS * 2];
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size) return;
// all threads within the block collaboratievly load the
// data required into the on-chip shared memory.
int sid = threadIdx.x + RADIUS;
temp[sid] = a[id];
int offset1 = THREAD_PER_BLOCK + RADIUS;
if (threadIdx.x < RADIUS) {
int id1 = id - RADIUS;
if (id1 >= 0) temp[threadIdx.x] = a[id1];
int id2 = id + THREAD_PER_BLOCK;
if (id2 < size) temp[threadIdx.x + offset1] = a[id2];
}
__syncthreads(); //synchronize to ensure all data are available
// perfrom stencil add on the shared memory
int offset2 = blockIdx.x * blockDim.x - RADIUS;
for (int i = threadIdx.x; i <= threadIdx.x + RADIUS * 2; i++)
{
int g_i = offset2 + i;
if (g_i < 0 || g_i >= size) continue;
c[id] += temp[i];
}
}
__global__ void cudaSencialAddKernel(int* a, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
for (int i = id - RADIUS; i <= id + RADIUS; i++)
{
if (i < 0 || i >= size) continue;
c[id] += a[i];
}
}
}
void cudaVecAdd(int* a, int* b, int* c, int size)
{
cudaVecAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(a, b, c, size);
}
void cudaStencialAdd(int* a, int *c, int size)
{
cudaSencialAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
}
void cudaStencialAdd_optimized(int* a, int *c, int size)
{
cudaStencialAddKernel_optimized <<< (size + THREAD_PER_BLOCK - 1) / THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
} | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define THREAD_PER_BLOCK 1024
#define RADIUS 1000
__global__ void cudaVecAddKernel(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
c[id] = a[id] + b[id];
}
}
/**
* an optimized stencial_add kernel with shared_memory
* the motivation here is that each element is loaded by threads (2*radius+1) times.
* we definitely want to optimize it.
*/
__global__ void cudaStencialAddKernel_optimized(int* a, int* c, int size)
{
__shared__ int temp[THREAD_PER_BLOCK + RADIUS * 2];
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size) return;
// all threads within the block collaboratievly load the
// data required into the on-chip shared memory.
int sid = threadIdx.x + RADIUS;
temp[sid] = a[id];
int offset1 = THREAD_PER_BLOCK + RADIUS;
if (threadIdx.x < RADIUS) {
int id1 = id - RADIUS;
if (id1 >= 0) temp[threadIdx.x] = a[id1];
int id2 = id + THREAD_PER_BLOCK;
if (id2 < size) temp[threadIdx.x + offset1] = a[id2];
}
__syncthreads(); //synchronize to ensure all data are available
// perfrom stencil add on the shared memory
int offset2 = blockIdx.x * blockDim.x - RADIUS;
for (int i = threadIdx.x; i <= threadIdx.x + RADIUS * 2; i++)
{
int g_i = offset2 + i;
if (g_i < 0 || g_i >= size) continue;
c[id] += temp[i];
}
}
__global__ void cudaSencialAddKernel(int* a, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
for (int i = id - RADIUS; i <= id + RADIUS; i++)
{
if (i < 0 || i >= size) continue;
c[id] += a[i];
}
}
}
void cudaVecAdd(int* a, int* b, int* c, int size)
{
cudaVecAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(a, b, c, size);
}
void cudaStencialAdd(int* a, int *c, int size)
{
cudaSencialAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
}
void cudaStencialAdd_optimized(int* a, int *c, int size)
{
cudaStencialAddKernel_optimized <<< (size + THREAD_PER_BLOCK - 1) / THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define THREAD_PER_BLOCK 1024
#define RADIUS 1000
__global__ void cudaVecAddKernel(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
c[id] = a[id] + b[id];
}
}
/**
* an optimized stencial_add kernel with shared_memory
* the motivation here is that each element is loaded by threads (2*radius+1) times.
* we definitely want to optimize it.
*/
__global__ void cudaStencialAddKernel_optimized(int* a, int* c, int size)
{
__shared__ int temp[THREAD_PER_BLOCK + RADIUS * 2];
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size) return;
// all threads within the block collaboratievly load the
// data required into the on-chip shared memory.
int sid = threadIdx.x + RADIUS;
temp[sid] = a[id];
int offset1 = THREAD_PER_BLOCK + RADIUS;
if (threadIdx.x < RADIUS) {
int id1 = id - RADIUS;
if (id1 >= 0) temp[threadIdx.x] = a[id1];
int id2 = id + THREAD_PER_BLOCK;
if (id2 < size) temp[threadIdx.x + offset1] = a[id2];
}
__syncthreads(); //synchronize to ensure all data are available
// perfrom stencil add on the shared memory
int offset2 = blockIdx.x * blockDim.x - RADIUS;
for (int i = threadIdx.x; i <= threadIdx.x + RADIUS * 2; i++)
{
int g_i = offset2 + i;
if (g_i < 0 || g_i >= size) continue;
c[id] += temp[i];
}
}
__global__ void cudaSencialAddKernel(int* a, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
for (int i = id - RADIUS; i <= id + RADIUS; i++)
{
if (i < 0 || i >= size) continue;
c[id] += a[i];
}
}
}
void cudaVecAdd(int* a, int* b, int* c, int size)
{
cudaVecAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(a, b, c, size);
}
void cudaStencialAdd(int* a, int *c, int size)
{
cudaSencialAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
}
void cudaStencialAdd_optimized(int* a, int *c, int size)
{
cudaStencialAddKernel_optimized <<< (size + THREAD_PER_BLOCK - 1) / THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16cudaVecAddKernelPiS_S_i
.globl _Z16cudaVecAddKernelPiS_S_i
.p2align 8
.type _Z16cudaVecAddKernelPiS_S_i,@function
_Z16cudaVecAddKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16cudaVecAddKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16cudaVecAddKernelPiS_S_i, .Lfunc_end0-_Z16cudaVecAddKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z31cudaStencialAddKernel_optimizedPiS_i
.globl _Z31cudaStencialAddKernel_optimizedPiS_i
.p2align 8
.type _Z31cudaStencialAddKernel_optimizedPiS_i,@function
_Z31cudaStencialAddKernel_optimizedPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v1, s15, v0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_10
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3 offset:4000
v_cmpx_gt_u32_e32 0x3e8, v0
s_cbranch_execz .LBB1_6
s_mov_b32 s6, exec_lo
v_cmpx_lt_i32_e32 0x3e7, v1
s_cbranch_execz .LBB1_4
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off offset:-4000
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v3, 0x400, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_6
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3 offset:8096
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add3_u32 v3, v0, s15, 0xfffffc18
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_movk_i32 s1, 0xe0bc
s_branch .LBB1_8
.p2align 6
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, 1, v3
s_add_i32 s1, s1, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 0
s_cbranch_scc0 .LBB1_10
.LBB1_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s0, s4, v3
s_and_b32 s2, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB1_7
global_load_b32 v4, v[1:2], off
v_add_nc_u32_e32 v5, s1, v0
ds_load_b32 v5, v5 offset:8004
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v4, v4, v5
global_store_b32 v[1:2], v4, off
s_branch .LBB1_7
.LBB1_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31cudaStencialAddKernel_optimizedPiS_i
.amdhsa_group_segment_fixed_size 12096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z31cudaStencialAddKernel_optimizedPiS_i, .Lfunc_end1-_Z31cudaStencialAddKernel_optimizedPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20cudaSencialAddKernelPiS_i
.globl _Z20cudaSencialAddKernelPiS_i
.p2align 8
.type _Z20cudaSencialAddKernelPiS_i,@function
_Z20cudaSencialAddKernelPiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s3
s_mov_b32 s3, exec_lo
v_add_nc_u32_e32 v1, s15, v0
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB2_5
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v4, 0x3e8, v1
v_add3_u32 v0, v0, s15, 0xfffffc17
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_3
.p2align 6
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v4
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB2_5
.LBB2_3:
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
v_cmp_gt_i32_e64 s0, s2, v0
s_and_b32 s3, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB2_2
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
global_store_b32 v[2:3], v5, off
s_branch .LBB2_2
.LBB2_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20cudaSencialAddKernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z20cudaSencialAddKernelPiS_i, .Lfunc_end2-_Z20cudaSencialAddKernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16cudaVecAddKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16cudaVecAddKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 12096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31cudaStencialAddKernel_optimizedPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31cudaStencialAddKernel_optimizedPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20cudaSencialAddKernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20cudaSencialAddKernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <assert.h>
#include <hip/hip_runtime.h>
#define THREAD_PER_BLOCK 1024
#define RADIUS 1000
__global__ void cudaVecAddKernel(int* a, int* b, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
c[id] = a[id] + b[id];
}
}
/**
* an optimized stencial_add kernel with shared_memory
* the motivation here is that each element is loaded by threads (2*radius+1) times.
* we definitely want to optimize it.
*/
__global__ void cudaStencialAddKernel_optimized(int* a, int* c, int size)
{
__shared__ int temp[THREAD_PER_BLOCK + RADIUS * 2];
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id >= size) return;
// all threads within the block collaboratievly load the
// data required into the on-chip shared memory.
int sid = threadIdx.x + RADIUS;
temp[sid] = a[id];
int offset1 = THREAD_PER_BLOCK + RADIUS;
if (threadIdx.x < RADIUS) {
int id1 = id - RADIUS;
if (id1 >= 0) temp[threadIdx.x] = a[id1];
int id2 = id + THREAD_PER_BLOCK;
if (id2 < size) temp[threadIdx.x + offset1] = a[id2];
}
__syncthreads(); //synchronize to ensure all data are available
// perfrom stencil add on the shared memory
int offset2 = blockIdx.x * blockDim.x - RADIUS;
for (int i = threadIdx.x; i <= threadIdx.x + RADIUS * 2; i++)
{
int g_i = offset2 + i;
if (g_i < 0 || g_i >= size) continue;
c[id] += temp[i];
}
}
__global__ void cudaSencialAddKernel(int* a, int* c, int size)
{
int id = blockIdx.x * blockDim.x + threadIdx.x;
if (id < size) {
for (int i = id - RADIUS; i <= id + RADIUS; i++)
{
if (i < 0 || i >= size) continue;
c[id] += a[i];
}
}
}
void cudaVecAdd(int* a, int* b, int* c, int size)
{
cudaVecAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>>(a, b, c, size);
}
void cudaStencialAdd(int* a, int *c, int size)
{
cudaSencialAddKernel <<< (size + THREAD_PER_BLOCK - 1)/THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
}
void cudaStencialAdd_optimized(int* a, int *c, int size)
{
cudaStencialAddKernel_optimized <<< (size + THREAD_PER_BLOCK - 1) / THREAD_PER_BLOCK, THREAD_PER_BLOCK >>> (a, c, size);
} | .text
.file "CUDAtest.hip"
.globl _Z31__device_stub__cudaVecAddKernelPiS_S_i # -- Begin function _Z31__device_stub__cudaVecAddKernelPiS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__cudaVecAddKernelPiS_S_i,@function
_Z31__device_stub__cudaVecAddKernelPiS_S_i: # @_Z31__device_stub__cudaVecAddKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16cudaVecAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__cudaVecAddKernelPiS_S_i, .Lfunc_end0-_Z31__device_stub__cudaVecAddKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i # -- Begin function _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i
.p2align 4, 0x90
.type _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i,@function
_Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i: # @_Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z31cudaStencialAddKernel_optimizedPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i, .Lfunc_end1-_Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__cudaSencialAddKernelPiS_i # -- Begin function _Z35__device_stub__cudaSencialAddKernelPiS_i
.p2align 4, 0x90
.type _Z35__device_stub__cudaSencialAddKernelPiS_i,@function
_Z35__device_stub__cudaSencialAddKernelPiS_i: # @_Z35__device_stub__cudaSencialAddKernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20cudaSencialAddKernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z35__device_stub__cudaSencialAddKernelPiS_i, .Lfunc_end2-_Z35__device_stub__cudaSencialAddKernelPiS_i
.cfi_endproc
# -- End function
.globl _Z10cudaVecAddPiS_S_i # -- Begin function _Z10cudaVecAddPiS_S_i
.p2align 4, 0x90
.type _Z10cudaVecAddPiS_S_i,@function
_Z10cudaVecAddPiS_S_i: # @_Z10cudaVecAddPiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16cudaVecAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10cudaVecAddPiS_S_i, .Lfunc_end3-_Z10cudaVecAddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z15cudaStencialAddPiS_i # -- Begin function _Z15cudaStencialAddPiS_i
.p2align 4, 0x90
.type _Z15cudaStencialAddPiS_i,@function
_Z15cudaStencialAddPiS_i: # @_Z15cudaStencialAddPiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20cudaSencialAddKernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z15cudaStencialAddPiS_i, .Lfunc_end4-_Z15cudaStencialAddPiS_i
.cfi_endproc
# -- End function
.globl _Z25cudaStencialAdd_optimizedPiS_i # -- Begin function _Z25cudaStencialAdd_optimizedPiS_i
.p2align 4, 0x90
.type _Z25cudaStencialAdd_optimizedPiS_i,@function
_Z25cudaStencialAdd_optimizedPiS_i: # @_Z25cudaStencialAdd_optimizedPiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z31cudaStencialAddKernel_optimizedPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z25cudaStencialAdd_optimizedPiS_i, .Lfunc_end5-_Z25cudaStencialAdd_optimizedPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16cudaVecAddKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31cudaStencialAddKernel_optimizedPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20cudaSencialAddKernelPiS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16cudaVecAddKernelPiS_S_i,@object # @_Z16cudaVecAddKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z16cudaVecAddKernelPiS_S_i
.p2align 3, 0x0
_Z16cudaVecAddKernelPiS_S_i:
.quad _Z31__device_stub__cudaVecAddKernelPiS_S_i
.size _Z16cudaVecAddKernelPiS_S_i, 8
.type _Z31cudaStencialAddKernel_optimizedPiS_i,@object # @_Z31cudaStencialAddKernel_optimizedPiS_i
.globl _Z31cudaStencialAddKernel_optimizedPiS_i
.p2align 3, 0x0
_Z31cudaStencialAddKernel_optimizedPiS_i:
.quad _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i
.size _Z31cudaStencialAddKernel_optimizedPiS_i, 8
.type _Z20cudaSencialAddKernelPiS_i,@object # @_Z20cudaSencialAddKernelPiS_i
.globl _Z20cudaSencialAddKernelPiS_i
.p2align 3, 0x0
_Z20cudaSencialAddKernelPiS_i:
.quad _Z35__device_stub__cudaSencialAddKernelPiS_i
.size _Z20cudaSencialAddKernelPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16cudaVecAddKernelPiS_S_i"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z31cudaStencialAddKernel_optimizedPiS_i"
.size .L__unnamed_2, 41
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20cudaSencialAddKernelPiS_i"
.size .L__unnamed_3, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__cudaVecAddKernelPiS_S_i
.addrsig_sym _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i
.addrsig_sym _Z35__device_stub__cudaSencialAddKernelPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16cudaVecAddKernelPiS_S_i
.addrsig_sym _Z31cudaStencialAddKernel_optimizedPiS_i
.addrsig_sym _Z20cudaSencialAddKernelPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20cudaSencialAddKernelPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R4, R2, c[0x0][0x0], R5 ; /* 0x0000000002047a24 */
/* 0x001fca00078e0205 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IADD3 R3, R4.reuse, 0x3e8, RZ ; /* 0x000003e804037810 */
/* 0x040fe20007ffe0ff */
/*0070*/ IMAD.MOV R6, RZ, RZ, -R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0a02 */
/*0080*/ IADD3 R0, R4, -0x3e8, RZ ; /* 0xfffffc1804007810 */
/* 0x000fe20007ffe0ff */
/*0090*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ BSSY B0, 0x270 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*00c0*/ IMNMX R3, R3, R0, !PT ; /* 0x0000000003037217 */
/* 0x000fc80007800200 */
/*00d0*/ IADD3 R2, R3.reuse, 0x1, RZ ; /* 0x0000000103027810 */
/* 0x040fe40007ffe0ff */
/*00e0*/ IADD3 R3, R3, 0x3e8, RZ ; /* 0x000003e803037810 */
/* 0x000fc60007ffe0ff */
/*00f0*/ IMAD R2, R6.reuse, c[0x0][0x0], R2 ; /* 0x0000000006027a24 */
/* 0x040fe400078e0202 */
/*0100*/ IMAD R3, R6, c[0x0][0x0], R3 ; /* 0x0000000006037a24 */
/* 0x000fe400078e0203 */
/*0110*/ IMAD.IADD R2, R2, 0x1, -R5.reuse ; /* 0x0000000102027824 */
/* 0x100fe400078e0a05 */
/*0120*/ IMAD.IADD R3, R3, 0x1, -R5 ; /* 0x0000000103037824 */
/* 0x000fc600078e0a05 */
/*0130*/ LOP3.LUT P0, R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe4000780c0ff */
/*0140*/ ISETP.GE.U32.AND P1, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe20003f26070 */
/*0150*/ IMAD.WIDE R2, R4, R7, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fd400078e0207 */
/*0160*/ @!P0 BRA 0x260 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fe400078e0006 */
/*0190*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06270 */
/*01a0*/ ISETP.LT.OR P0, PT, R0, RZ, P0 ; /* 0x000000ff0000720c */
/* 0x000fda0000701670 */
/*01b0*/ @!P0 IMAD.MOV.U32 R6, RZ, RZ, R8 ; /* 0x000000ffff068224 */
/* 0x000fe200078e0008 */
/*01c0*/ @!P0 LDG.E R9, [R2.64] ; /* 0x0000000402098981 */
/* 0x001eaa000c1e1900 */
/*01d0*/ @!P0 LDG.E R6, [R6.64] ; /* 0x0000000406068981 */
/* 0x000ea2000c1e1900 */
/*01e0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*0200*/ ISETP.NE.AND P2, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f45270 */
/*0210*/ @!P0 IMAD.IADD R9, R6, 0x1, R9 ; /* 0x0000000106098824 */
/* 0x004fca00078e0209 */
/*0220*/ @!P0 STG.E [R2.64], R9 ; /* 0x0000000902008986 */
/* 0x0001e2000c101904 */
/*0230*/ IADD3 R8, P0, R8, 0x4, RZ ; /* 0x0000000408087810 */
/* 0x000fca0007f1e0ff */
/*0240*/ IMAD.X R7, RZ, RZ, R7, P0 ; /* 0x000000ffff077224 */
/* 0x000fe200000e0607 */
/*0250*/ @P2 BRA 0x190 ; /* 0xffffff3000002947 */
/* 0x000fea000383ffff */
/*0260*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0270*/ @!P1 EXIT ; /* 0x000000000000994d */
/* 0x000fea0003800000 */
/*0280*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0290*/ IADD3 R9, R4, 0x3e5, RZ ; /* 0x000003e504097810 */
/* 0x001fc60007ffe0ff */
/*02a0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x160] ; /* 0x0000580000067625 */
/* 0x000fc800078e0207 */
/*02b0*/ ISETP.GE.AND P1, PT, R0.reuse, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x040fe20003f26270 */
/*02c0*/ BSSY B0, 0x3c0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*02d0*/ IADD3 R4, R0.reuse, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x040fe40007ffe0ff */
/*02e0*/ ISETP.LT.OR P1, PT, R0.reuse, RZ, P1 ; /* 0x000000ff0000720c */
/* 0x040fe40000f21670 */
/*02f0*/ IADD3 R5, R0, 0x2, RZ ; /* 0x0000000200057810 */
/* 0x000fe40007ffe0ff */
/*0300*/ ISETP.GE.AND P2, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fe20003f46270 */
/*0310*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0006 */
/*0320*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fe20003f06270 */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*0340*/ ISETP.LT.OR P2, PT, R0, -0x1, P2 ; /* 0xffffffff0000780c */
/* 0x000fc40001741670 */
/*0350*/ ISETP.LT.OR P0, PT, R0, -0x2, P0 ; /* 0xfffffffe0000780c */
/* 0x000fc60000701670 */
/*0360*/ @P1 BRA 0x3b0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0370*/ LDG.E R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ea8000c1e1900 */
/*0380*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x000ea4000c1e1900 */
/*0390*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x004fca00078e0207 */
/*03a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*03b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03c0*/ BSSY B0, 0x430 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*03d0*/ @P2 BRA 0x420 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*03e0*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x001ea8000c1e1900 */
/*03f0*/ LDG.E R6, [R4.64+0x4] ; /* 0x0000040404067981 */
/* 0x000ea4000c1e1900 */
/*0400*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x004fca00078e0207 */
/*0410*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ BSSY B0, 0x4a0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0440*/ @P0 BRA 0x490 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E R7, [R2.64] ; /* 0x0000000402077981 */
/* 0x001ea8000c1e1900 */
/*0460*/ LDG.E R6, [R4.64+0x8] ; /* 0x0000080404067981 */
/* 0x000ea4000c1e1900 */
/*0470*/ IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106077824 */
/* 0x004fca00078e0207 */
/*0480*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x0001e4000c101904 */
/*0490*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04a0*/ IADD3 R6, R0, 0x3, RZ ; /* 0x0000000300067810 */
/* 0x000fc80007ffe0ff */
/*04b0*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fc80003f06270 */
/*04c0*/ ISETP.LT.OR P0, PT, R0, -0x3, P0 ; /* 0xfffffffd0000780c */
/* 0x000fda0000701670 */
/*04d0*/ @!P0 LDG.E R7, [R2.64] ; /* 0x0000000402078981 */
/* 0x001ea8000c1e1900 */
/*04e0*/ @!P0 LDG.E R6, [R4.64+0xc] ; /* 0x00000c0404068981 */
/* 0x000ea4000c1e1900 */
/*04f0*/ @!P0 IMAD.IADD R7, R6, 0x1, R7 ; /* 0x0000000106078824 */
/* 0x004fe200078e0207 */
/*0500*/ IADD3 R6, P1, R4, 0x10, RZ ; /* 0x0000001004067810 */
/* 0x000fc80007f3e0ff */
/*0510*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e2000c101904 */
/*0520*/ ISETP.GE.AND P0, PT, R0.reuse, R9, PT ; /* 0x000000090000720c */
/* 0x040fe40003f06270 */
/*0530*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*0540*/ IMAD.X R7, RZ, RZ, R5, P1 ; /* 0x000000ffff077224 */
/* 0x001fd400008e0605 */
/*0550*/ @!P0 BRA 0x2b0 ; /* 0xfffffd5000008947 */
/* 0x000fea000383ffff */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z31cudaStencialAddKernel_optimizedPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R4 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0203 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ ISETP.GT.U32.AND P1, PT, R4.reuse, 0x3e7, PT ; /* 0x000003e70400780c */
/* 0x040fe20003f24070 */
/*00b0*/ BSSY B0, 0x180 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*00c0*/ ISETP.GT.U32.AND P0, PT, R4.reuse, -0x7d1, PT ; /* 0xfffff82f0400780c */
/* 0x040fe20003f04070 */
/*00d0*/ IMAD.SHL.U32 R6, R4, 0x4, RZ ; /* 0x0000000404067824 */
/* 0x000fe200078e00ff */
/*00e0*/ STS [R4.X4+0xfa0], R5 ; /* 0x000fa00504007388 */
/* 0x0041f20000004800 */
/*00f0*/ @P1 BRA 0x170 ; /* 0x0000007000001947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R5, R0.reuse, 0x400, RZ ; /* 0x0000040000057810 */
/* 0x041fe40007ffe0ff */
/*0110*/ ISETP.GE.AND P1, PT, R0, 0x3e8, PT ; /* 0x000003e80000780c */
/* 0x000fc40003f26270 */
/*0120*/ ISETP.GE.AND P2, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fd60003f46270 */
/*0130*/ @P1 LDG.E R5, [R2.64+-0xfa0] ; /* 0xfff0600402051981 */
/* 0x000ea8000c1e1900 */
/*0140*/ @!P2 LDG.E R7, [R2.64+0x1000] ; /* 0x001000040207a981 */
/* 0x000ee8000c1e1900 */
/*0150*/ @P1 STS [R6], R5 ; /* 0x0000000506001388 */
/* 0x0041e80000000800 */
/*0160*/ @!P2 STS [R6+0x1fa0], R7 ; /* 0x001fa0070600a388 */
/* 0x0081e40000000800 */
/*0170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0190*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01a0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078010ff */
/*01b0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc40000011400 */
/*01c0*/ IADD3 R5, R0, -0x3e8, RZ ; /* 0xfffffc1800057810 */
/* 0x001fe40007ffe0ff */
/*01d0*/ IADD3 R9, R4, 0x7d0, RZ ; /* 0x000007d004097810 */
/* 0x000fe40007ffe0ff */
/*01e0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fe400000f1403 */
/*01f0*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x170], PT ; /* 0x00005c0005007a0c */
/* 0x000fc80003f06270 */
/*0200*/ ISETP.LT.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0000701670 */
/*0210*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000402008981 */
/* 0x000ea2000c1e1900 */
/*0220*/ IADD3 R4, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105057810 */
/* 0x000fe20007ffe0ff */
/*0240*/ @!P0 LDS R7, [R6] ; /* 0x0000000006078984 */
/* 0x0000a40000000800 */
/*0250*/ IADD3 R6, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x001fe20007ffe0ff */
/*0260*/ @!P0 IMAD.IADD R7, R0, 0x1, R7 ; /* 0x0000000100078824 */
/* 0x004fca00078e0207 */
/*0270*/ @!P0 STG.E [R2.64], R7 ; /* 0x0000000702008986 */
/* 0x0001e2000c101904 */
/*0280*/ ISETP.GT.U32.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fda0003f04070 */
/*0290*/ @!P0 BRA 0x1f0 ; /* 0xffffff5000008947 */
/* 0x001fea000383ffff */
/*02a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02b0*/ BRA 0x2b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z16cudaVecAddKernelPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x178], PT ; /* 0x00005e0006007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fc800078e0207 */
/*0090*/ IMAD.WIDE R2, R6.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x0c0fe400078e0207 */
/*00a0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*00d0*/ IADD3 R9, R4, R3, RZ ; /* 0x0000000304097210 */
/* 0x004fca0007ffe0ff */
/*00e0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z16cudaVecAddKernelPiS_S_i
.globl _Z16cudaVecAddKernelPiS_S_i
.p2align 8
.type _Z16cudaVecAddKernelPiS_S_i,@function
_Z16cudaVecAddKernelPiS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z16cudaVecAddKernelPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z16cudaVecAddKernelPiS_S_i, .Lfunc_end0-_Z16cudaVecAddKernelPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z31cudaStencialAddKernel_optimizedPiS_i
.globl _Z31cudaStencialAddKernel_optimizedPiS_i
.p2align 8
.type _Z31cudaStencialAddKernel_optimizedPiS_i,@function
_Z31cudaStencialAddKernel_optimizedPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s4, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v1, s15, v0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_10
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3 offset:4000
v_cmpx_gt_u32_e32 0x3e8, v0
s_cbranch_execz .LBB1_6
s_mov_b32 s6, exec_lo
v_cmpx_lt_i32_e32 0x3e7, v1
s_cbranch_execz .LBB1_4
v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v3, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off offset:-4000
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s6
v_add_nc_u32_e32 v3, 0x400, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, s4, v3
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_6
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v3, v[3:4], off
v_lshlrev_b32_e32 v4, 2, v0
s_waitcnt vmcnt(0)
ds_store_b32 v4, v3 offset:8096
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s5
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[1:2], 2, v[1:2]
v_add3_u32 v3, v0, s15, 0xfffffc18
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
s_movk_i32 s1, 0xe0bc
s_branch .LBB1_8
.p2align 6
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v3, 1, v3
s_add_i32 s1, s1, 4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lg_u32 s1, 0
s_cbranch_scc0 .LBB1_10
.LBB1_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v3
v_cmp_gt_i32_e64 s0, s4, v3
s_and_b32 s2, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB1_7
global_load_b32 v4, v[1:2], off
v_add_nc_u32_e32 v5, s1, v0
ds_load_b32 v5, v5 offset:8004
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v4, v4, v5
global_store_b32 v[1:2], v4, off
s_branch .LBB1_7
.LBB1_10:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z31cudaStencialAddKernel_optimizedPiS_i
.amdhsa_group_segment_fixed_size 12096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z31cudaStencialAddKernel_optimizedPiS_i, .Lfunc_end1-_Z31cudaStencialAddKernel_optimizedPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z20cudaSencialAddKernelPiS_i
.globl _Z20cudaSencialAddKernelPiS_i
.p2align 8
.type _Z20cudaSencialAddKernelPiS_i,@function
_Z20cudaSencialAddKernelPiS_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s3
s_mov_b32 s3, exec_lo
v_add_nc_u32_e32 v1, s15, v0
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB2_5
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v4, 0x3e8, v1
v_add3_u32 v0, v0, s15, 0xfffffc17
s_mov_b32 s1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_3
.p2align 6
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s0
v_cmp_ge_i32_e32 vcc_lo, v0, v4
s_or_b32 s1, vcc_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execz .LBB2_5
.LBB2_3:
v_add_nc_u32_e32 v0, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, -1, v0
v_cmp_gt_i32_e64 s0, s2, v0
s_and_b32 s3, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB2_2
v_lshlrev_b64 v[5:6], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_load_b32 v5, v[5:6], off
global_load_b32 v6, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
global_store_b32 v[2:3], v5, off
s_branch .LBB2_2
.LBB2_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20cudaSencialAddKernelPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z20cudaSencialAddKernelPiS_i, .Lfunc_end2-_Z20cudaSencialAddKernelPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z16cudaVecAddKernelPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z16cudaVecAddKernelPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 12096
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z31cudaStencialAddKernel_optimizedPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z31cudaStencialAddKernel_optimizedPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20cudaSencialAddKernelPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20cudaSencialAddKernelPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0014e112_00000000-6_CUDAtest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i
.type _Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i, @function
_Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z16cudaVecAddKernelPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i, .-_Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i
.globl _Z16cudaVecAddKernelPiS_S_i
.type _Z16cudaVecAddKernelPiS_S_i, @function
_Z16cudaVecAddKernelPiS_S_i:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z16cudaVecAddKernelPiS_S_i, .-_Z16cudaVecAddKernelPiS_S_i
.globl _Z10cudaVecAddPiS_S_i
.type _Z10cudaVecAddPiS_S_i, @function
_Z10cudaVecAddPiS_S_i:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbp
movq %rsi, %r12
movq %rdx, %r13
movl %ecx, %ebx
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
leal 2046(%rcx), %eax
movl %ecx, %edx
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L11:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movl %ebx, %ecx
movq %r13, %rdx
movq %r12, %rsi
movq %rbp, %rdi
call _Z41__device_stub__Z16cudaVecAddKernelPiS_S_iPiS_S_i
jmp .L11
.cfi_endproc
.LFE2057:
.size _Z10cudaVecAddPiS_S_i, .-_Z10cudaVecAddPiS_S_i
.globl _Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i
.type _Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i, @function
_Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L19
.L15:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L20
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z31cudaStencialAddKernel_optimizedPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L15
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i, .-_Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i
.globl _Z31cudaStencialAddKernel_optimizedPiS_i
.type _Z31cudaStencialAddKernel_optimizedPiS_i, @function
_Z31cudaStencialAddKernel_optimizedPiS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z31cudaStencialAddKernel_optimizedPiS_i, .-_Z31cudaStencialAddKernel_optimizedPiS_i
.globl _Z25cudaStencialAdd_optimizedPiS_i
.type _Z25cudaStencialAdd_optimizedPiS_i, @function
_Z25cudaStencialAdd_optimizedPiS_i:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L26
.L23:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z54__device_stub__Z31cudaStencialAddKernel_optimizedPiS_iPiS_i
jmp .L23
.cfi_endproc
.LFE2059:
.size _Z25cudaStencialAdd_optimizedPiS_i, .-_Z25cudaStencialAdd_optimizedPiS_i
.globl _Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i
.type _Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i, @function
_Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20cudaSencialAddKernelPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i, .-_Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i
.globl _Z20cudaSencialAddKernelPiS_i
.type _Z20cudaSencialAddKernelPiS_i, @function
_Z20cudaSencialAddKernelPiS_i:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z20cudaSencialAddKernelPiS_i, .-_Z20cudaSencialAddKernelPiS_i
.globl _Z15cudaStencialAddPiS_i
.type _Z15cudaStencialAddPiS_i, @function
_Z15cudaStencialAddPiS_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $32, %rsp
.cfi_def_cfa_offset 64
movq %rdi, %rbp
movq %rsi, %r12
movl %edx, %ebx
movl $1024, 20(%rsp)
movl $1, 24(%rsp)
leal 2046(%rdx), %eax
addl $1023, %edx
cmovns %edx, %eax
sarl $10, %eax
movl %eax, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movl %ebx, %edx
movq %r12, %rsi
movq %rbp, %rdi
call _Z43__device_stub__Z20cudaSencialAddKernelPiS_iPiS_i
jmp .L35
.cfi_endproc
.LFE2058:
.size _Z15cudaStencialAddPiS_i, .-_Z15cudaStencialAddPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20cudaSencialAddKernelPiS_i"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z31cudaStencialAddKernel_optimizedPiS_i"
.section .rodata.str1.1
.LC2:
.string "_Z16cudaVecAddKernelPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20cudaSencialAddKernelPiS_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z31cudaStencialAddKernel_optimizedPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z16cudaVecAddKernelPiS_S_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDAtest.hip"
.globl _Z31__device_stub__cudaVecAddKernelPiS_S_i # -- Begin function _Z31__device_stub__cudaVecAddKernelPiS_S_i
.p2align 4, 0x90
.type _Z31__device_stub__cudaVecAddKernelPiS_S_i,@function
_Z31__device_stub__cudaVecAddKernelPiS_S_i: # @_Z31__device_stub__cudaVecAddKernelPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16cudaVecAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z31__device_stub__cudaVecAddKernelPiS_S_i, .Lfunc_end0-_Z31__device_stub__cudaVecAddKernelPiS_S_i
.cfi_endproc
# -- End function
.globl _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i # -- Begin function _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i
.p2align 4, 0x90
.type _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i,@function
_Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i: # @_Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z31cudaStencialAddKernel_optimizedPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i, .Lfunc_end1-_Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i
.cfi_endproc
# -- End function
.globl _Z35__device_stub__cudaSencialAddKernelPiS_i # -- Begin function _Z35__device_stub__cudaSencialAddKernelPiS_i
.p2align 4, 0x90
.type _Z35__device_stub__cudaSencialAddKernelPiS_i,@function
_Z35__device_stub__cudaSencialAddKernelPiS_i: # @_Z35__device_stub__cudaSencialAddKernelPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20cudaSencialAddKernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z35__device_stub__cudaSencialAddKernelPiS_i, .Lfunc_end2-_Z35__device_stub__cudaSencialAddKernelPiS_i
.cfi_endproc
# -- End function
.globl _Z10cudaVecAddPiS_S_i # -- Begin function _Z10cudaVecAddPiS_S_i
.p2align 4, 0x90
.type _Z10cudaVecAddPiS_S_i,@function
_Z10cudaVecAddPiS_S_i: # @_Z10cudaVecAddPiS_S_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %ebx
movq %rdx, %r14
movq %rsi, %r15
movq %rdi, %r12
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq %r12, 72(%rsp)
movq %r15, 64(%rsp)
movq %r14, 56(%rsp)
movl %ebx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z16cudaVecAddKernelPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z10cudaVecAddPiS_S_i, .Lfunc_end3-_Z10cudaVecAddPiS_S_i
.cfi_endproc
# -- End function
.globl _Z15cudaStencialAddPiS_i # -- Begin function _Z15cudaStencialAddPiS_i
.p2align 4, 0x90
.type _Z15cudaStencialAddPiS_i,@function
_Z15cudaStencialAddPiS_i: # @_Z15cudaStencialAddPiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20cudaSencialAddKernelPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z15cudaStencialAddPiS_i, .Lfunc_end4-_Z15cudaStencialAddPiS_i
.cfi_endproc
# -- End function
.globl _Z25cudaStencialAdd_optimizedPiS_i # -- Begin function _Z25cudaStencialAdd_optimizedPiS_i
.p2align 4, 0x90
.type _Z25cudaStencialAdd_optimizedPiS_i,@function
_Z25cudaStencialAdd_optimizedPiS_i: # @_Z25cudaStencialAdd_optimizedPiS_i
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $112, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %edx, %ebx
movq %rsi, %r14
movq %rdi, %r15
leal 1023(%rbx), %eax
leal 2046(%rbx), %edi
testl %eax, %eax
cmovnsl %eax, %edi
sarl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $1024, %rdx # imm = 0x400
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq %r15, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z31cudaStencialAddKernel_optimizedPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $112, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z25cudaStencialAdd_optimizedPiS_i, .Lfunc_end5-_Z25cudaStencialAdd_optimizedPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z16cudaVecAddKernelPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z31cudaStencialAddKernel_optimizedPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20cudaSencialAddKernelPiS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z16cudaVecAddKernelPiS_S_i,@object # @_Z16cudaVecAddKernelPiS_S_i
.section .rodata,"a",@progbits
.globl _Z16cudaVecAddKernelPiS_S_i
.p2align 3, 0x0
_Z16cudaVecAddKernelPiS_S_i:
.quad _Z31__device_stub__cudaVecAddKernelPiS_S_i
.size _Z16cudaVecAddKernelPiS_S_i, 8
.type _Z31cudaStencialAddKernel_optimizedPiS_i,@object # @_Z31cudaStencialAddKernel_optimizedPiS_i
.globl _Z31cudaStencialAddKernel_optimizedPiS_i
.p2align 3, 0x0
_Z31cudaStencialAddKernel_optimizedPiS_i:
.quad _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i
.size _Z31cudaStencialAddKernel_optimizedPiS_i, 8
.type _Z20cudaSencialAddKernelPiS_i,@object # @_Z20cudaSencialAddKernelPiS_i
.globl _Z20cudaSencialAddKernelPiS_i
.p2align 3, 0x0
_Z20cudaSencialAddKernelPiS_i:
.quad _Z35__device_stub__cudaSencialAddKernelPiS_i
.size _Z20cudaSencialAddKernelPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z16cudaVecAddKernelPiS_S_i"
.size .L__unnamed_1, 28
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z31cudaStencialAddKernel_optimizedPiS_i"
.size .L__unnamed_2, 41
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z20cudaSencialAddKernelPiS_i"
.size .L__unnamed_3, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z31__device_stub__cudaVecAddKernelPiS_S_i
.addrsig_sym _Z46__device_stub__cudaStencialAddKernel_optimizedPiS_i
.addrsig_sym _Z35__device_stub__cudaSencialAddKernelPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z16cudaVecAddKernelPiS_S_i
.addrsig_sym _Z31cudaStencialAddKernel_optimizedPiS_i
.addrsig_sym _Z20cudaSencialAddKernelPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void VecAdd(float *A, float *B, float *C)
{
int i = threadIdx.x;
C[i] = A[i] + B[i];
}
void printVec(int N, float *vec)
{
for (int i = 0; i < N; i++)
{
printf("%.2f ", vec[i]);
}
printf("\n");
}
int main(int argc, char const *argv[])
{
int deviceCount, device;
cudaGetDeviceCount(&deviceCount);
for (device = 0; device < deviceCount; ++device)
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has %d multiprocessors, and warps of size %d\n",
device, deviceProp.name, deviceProp.multiProcessorCount, deviceProp.warpSize);
}
int N = 50000;
size_t size = N * sizeof(float);
float *hA = (float *)malloc(size);
float *hB = (float *)malloc(size);
float *hC = (float *)malloc(size);
for (int i = 0; i < N; i++)
{
hA[i] = i;
hB[i] = -2*i;
}
printVec(10, hA);
printf("+\n");
printVec(10, hB);
float *dA, *dB, *dC;
cudaMalloc(&dA, size);
cudaMalloc(&dB, size);
cudaMalloc(&dC, size);
cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, size, cudaMemcpyHostToDevice);
VecAdd<<<4, N/4>>>(dA, dB, dC);
cudaMemcpy(hC, dC, size, cudaMemcpyDeviceToHost);
printf("=\n");
printVec(10, hC);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
free(hA);
free(hB);
free(hC);
} | code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
__global__ void VecAdd(float *A, float *B, float *C)
{
int i = threadIdx.x;
C[i] = A[i] + B[i];
}
void printVec(int N, float *vec)
{
for (int i = 0; i < N; i++)
{
printf("%.2f ", vec[i]);
}
printf("\n");
}
int main(int argc, char const *argv[])
{
int deviceCount, device;
cudaGetDeviceCount(&deviceCount);
for (device = 0; device < deviceCount; ++device)
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has %d multiprocessors, and warps of size %d\n",
device, deviceProp.name, deviceProp.multiProcessorCount, deviceProp.warpSize);
}
int N = 50000;
size_t size = N * sizeof(float);
float *hA = (float *)malloc(size);
float *hB = (float *)malloc(size);
float *hC = (float *)malloc(size);
for (int i = 0; i < N; i++)
{
hA[i] = i;
hB[i] = -2*i;
}
printVec(10, hA);
printf("+\n");
printVec(10, hB);
float *dA, *dB, *dC;
cudaMalloc(&dA, size);
cudaMalloc(&dB, size);
cudaMalloc(&dC, size);
cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, size, cudaMemcpyHostToDevice);
VecAdd<<<4, N/4>>>(dA, dB, dC);
cudaMemcpy(hC, dC, size, cudaMemcpyDeviceToHost);
printf("=\n");
printVec(10, hC);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
free(hA);
free(hB);
free(hC);
} | .file "tmpxft_0010b324_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.2f "
.LC1:
.string "\n"
.text
.globl _Z8printVeciPf
.type _Z8printVeciPf, @function
_Z8printVeciPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %edi, %edi
jle .L4
movq %rsi, %rbx
movslq %edi, %rdi
leaq (%rsi,%rdi,4), %r12
leaq .LC0(%rip), %rbp
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8printVeciPf, .-_Z8printVeciPf
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Device %d (%s) has %d multiprocessors, and warps of size %d\n"
.section .rodata.str1.1
.LC3:
.string "+\n"
.LC4:
.string "=\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1104, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L17
movl $0, %ebx
leaq .LC2(%rip), %r12
.L18:
leaq 64(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 372(%rsp), %r9d
movl 452(%rsp), %r8d
movq %rbp, %rcx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L18
.L17:
movl $200000, %edi
call malloc@PLT
movq %rax, %rbp
movl $200000, %edi
call malloc@PLT
movq %rax, %rbx
movl $200000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %edx
movl $0, %eax
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
subl $2, %edx
cmpq $50000, %rax
jne .L19
movq %rbp, %rsi
movl $10, %edi
call _Z8printVeciPf
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $10, %edi
call _Z8printVeciPf
leaq 16(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $200000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $200000, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $12500, 52(%rsp)
movl $1, 56(%rsp)
movl $4, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
movl $2, %ecx
movl $200000, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $10, %edi
call _Z8printVeciPf
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $1104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
__global__ void VecAdd(float *A, float *B, float *C)
{
int i = threadIdx.x;
C[i] = A[i] + B[i];
}
void printVec(int N, float *vec)
{
for (int i = 0; i < N; i++)
{
printf("%.2f ", vec[i]);
}
printf("\n");
}
int main(int argc, char const *argv[])
{
int deviceCount, device;
cudaGetDeviceCount(&deviceCount);
for (device = 0; device < deviceCount; ++device)
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has %d multiprocessors, and warps of size %d\n",
device, deviceProp.name, deviceProp.multiProcessorCount, deviceProp.warpSize);
}
int N = 50000;
size_t size = N * sizeof(float);
float *hA = (float *)malloc(size);
float *hB = (float *)malloc(size);
float *hC = (float *)malloc(size);
for (int i = 0; i < N; i++)
{
hA[i] = i;
hB[i] = -2*i;
}
printVec(10, hA);
printf("+\n");
printVec(10, hB);
float *dA, *dB, *dC;
cudaMalloc(&dA, size);
cudaMalloc(&dB, size);
cudaMalloc(&dC, size);
cudaMemcpy(dA, hA, size, cudaMemcpyHostToDevice);
cudaMemcpy(dB, hB, size, cudaMemcpyHostToDevice);
VecAdd<<<4, N/4>>>(dA, dB, dC);
cudaMemcpy(hC, dC, size, cudaMemcpyDeviceToHost);
printf("=\n");
printVec(10, hC);
cudaFree(dA);
cudaFree(dB);
cudaFree(dC);
free(hA);
free(hB);
free(hC);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void VecAdd(float *A, float *B, float *C)
{
int i = threadIdx.x;
C[i] = A[i] + B[i];
}
void printVec(int N, float *vec)
{
for (int i = 0; i < N; i++)
{
printf("%.2f ", vec[i]);
}
printf("\n");
}
int main(int argc, char const *argv[])
{
int deviceCount, device;
hipGetDeviceCount(&deviceCount);
for (device = 0; device < deviceCount; ++device)
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has %d multiprocessors, and warps of size %d\n",
device, deviceProp.name, deviceProp.multiProcessorCount, deviceProp.warpSize);
}
int N = 50000;
size_t size = N * sizeof(float);
float *hA = (float *)malloc(size);
float *hB = (float *)malloc(size);
float *hC = (float *)malloc(size);
for (int i = 0; i < N; i++)
{
hA[i] = i;
hB[i] = -2*i;
}
printVec(10, hA);
printf("+\n");
printVec(10, hB);
float *dA, *dB, *dC;
hipMalloc(&dA, size);
hipMalloc(&dB, size);
hipMalloc(&dC, size);
hipMemcpy(dA, hA, size, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, size, hipMemcpyHostToDevice);
VecAdd<<<4, N/4>>>(dA, dB, dC);
hipMemcpy(hC, dC, size, hipMemcpyDeviceToHost);
printf("=\n");
printVec(10, hC);
hipFree(dA);
hipFree(dB);
hipFree(dC);
free(hA);
free(hB);
free(hC);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void VecAdd(float *A, float *B, float *C)
{
int i = threadIdx.x;
C[i] = A[i] + B[i];
}
void printVec(int N, float *vec)
{
for (int i = 0; i < N; i++)
{
printf("%.2f ", vec[i]);
}
printf("\n");
}
int main(int argc, char const *argv[])
{
int deviceCount, device;
hipGetDeviceCount(&deviceCount);
for (device = 0; device < deviceCount; ++device)
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has %d multiprocessors, and warps of size %d\n",
device, deviceProp.name, deviceProp.multiProcessorCount, deviceProp.warpSize);
}
int N = 50000;
size_t size = N * sizeof(float);
float *hA = (float *)malloc(size);
float *hB = (float *)malloc(size);
float *hC = (float *)malloc(size);
for (int i = 0; i < N; i++)
{
hA[i] = i;
hB[i] = -2*i;
}
printVec(10, hA);
printf("+\n");
printVec(10, hB);
float *dA, *dB, *dC;
hipMalloc(&dA, size);
hipMalloc(&dB, size);
hipMalloc(&dC, size);
hipMemcpy(dA, hA, size, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, size, hipMemcpyHostToDevice);
VecAdd<<<4, N/4>>>(dA, dB, dC);
hipMemcpy(hC, dC, size, hipMemcpyDeviceToHost);
printf("=\n");
printVec(10, hC);
hipFree(dA);
hipFree(dB);
hipFree(dC);
free(hA);
free(hB);
free(hC);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
__global__ void VecAdd(float *A, float *B, float *C)
{
int i = threadIdx.x;
C[i] = A[i] + B[i];
}
void printVec(int N, float *vec)
{
for (int i = 0; i < N; i++)
{
printf("%.2f ", vec[i]);
}
printf("\n");
}
int main(int argc, char const *argv[])
{
int deviceCount, device;
hipGetDeviceCount(&deviceCount);
for (device = 0; device < deviceCount; ++device)
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, device);
printf("Device %d (%s) has %d multiprocessors, and warps of size %d\n",
device, deviceProp.name, deviceProp.multiProcessorCount, deviceProp.warpSize);
}
int N = 50000;
size_t size = N * sizeof(float);
float *hA = (float *)malloc(size);
float *hB = (float *)malloc(size);
float *hC = (float *)malloc(size);
for (int i = 0; i < N; i++)
{
hA[i] = i;
hB[i] = -2*i;
}
printVec(10, hA);
printf("+\n");
printVec(10, hB);
float *dA, *dB, *dC;
hipMalloc(&dA, size);
hipMalloc(&dB, size);
hipMalloc(&dC, size);
hipMemcpy(dA, hA, size, hipMemcpyHostToDevice);
hipMemcpy(dB, hB, size, hipMemcpyHostToDevice);
VecAdd<<<4, N/4>>>(dA, dB, dC);
hipMemcpy(hC, dC, size, hipMemcpyDeviceToHost);
printf("=\n");
printVec(10, hC);
hipFree(dA);
hipFree(dB);
hipFree(dC);
free(hA);
free(hB);
free(hC);
} | .text
.file "test.hip"
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.globl _Z8printVeciPf # -- Begin function _Z8printVeciPf
.p2align 4, 0x90
.type _Z8printVeciPf,@function
_Z8printVeciPf: # @_Z8printVeciPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z8printVeciPf, .Lfunc_end1-_Z8printVeciPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 1632
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 112(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 420(%rsp), %r8d
movl 500(%rsp), %ecx
movl $.L.str.2, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB2_2
.LBB2_3: # %._crit_edge
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %rbx
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %r14
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %r15
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rcx,4)
incq %rcx
addl $-2, %eax
cmpq $50000, %rcx # imm = 0xC350
jne .LBB2_4
# %bb.5: # %.lr.ph.i.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB2_6
# %bb.7: # %_Z8printVeciPf.exit
movl $10, %edi
callq putchar@PLT
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_8: # %.lr.ph.i37
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB2_8
# %bb.9: # %_Z8printVeciPf.exit42
movl $10, %edi
callq putchar@PLT
leaq 32(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
leaq 24(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
movq 32(%rsp), %rdi
movl $200000, %edx # imm = 0x30D40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $200000, %edx # imm = 0x30D40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 12496(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
movq 16(%rsp), %rsi
movl $200000, %edx # imm = 0x30D40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_12: # %.lr.ph.i43
# =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB2_12
# %bb.13: # %_Z8printVeciPf.exit48
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device %d (%s) has %d multiprocessors, and warps of size %d\n"
.size .L.str.2, 61
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "+"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "="
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6VecAddPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6VecAddPfS_S_
.globl _Z6VecAddPfS_S_
.p2align 8
.type _Z6VecAddPfS_S_,@function
_Z6VecAddPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6VecAddPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6VecAddPfS_S_, .Lfunc_end0-_Z6VecAddPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6VecAddPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z6VecAddPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0010b324_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%.2f "
.LC1:
.string "\n"
.text
.globl _Z8printVeciPf
.type _Z8printVeciPf, @function
_Z8printVeciPf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
testl %edi, %edi
jle .L4
movq %rsi, %rbx
movslq %edi, %rdi
leaq (%rsi,%rdi,4), %r12
leaq .LC0(%rip), %rbp
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %rbp, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L5
.L4:
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z8printVeciPf, .-_Z8printVeciPf
.globl _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.type _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, @function
_Z29__device_stub__Z6VecAddPfS_S_PfS_S_:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6VecAddPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z29__device_stub__Z6VecAddPfS_S_PfS_S_, .-_Z29__device_stub__Z6VecAddPfS_S_PfS_S_
.globl _Z6VecAddPfS_S_
.type _Z6VecAddPfS_S_, @function
_Z6VecAddPfS_S_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z6VecAddPfS_S_, .-_Z6VecAddPfS_S_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Device %d (%s) has %d multiprocessors, and warps of size %d\n"
.section .rodata.str1.1
.LC3:
.string "+\n"
.LC4:
.string "=\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1104, %rsp
.cfi_def_cfa_offset 1136
movq %fs:40, %rax
movq %rax, 1096(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L17
movl $0, %ebx
leaq .LC2(%rip), %r12
.L18:
leaq 64(%rsp), %rbp
movl %ebx, %esi
movq %rbp, %rdi
call cudaGetDeviceProperties_v2@PLT
movl 372(%rsp), %r9d
movl 452(%rsp), %r8d
movq %rbp, %rcx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L18
.L17:
movl $200000, %edi
call malloc@PLT
movq %rax, %rbp
movl $200000, %edi
call malloc@PLT
movq %rax, %rbx
movl $200000, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %edx
movl $0, %eax
.L19:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
pxor %xmm0, %xmm0
cvtsi2ssl %edx, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
subl $2, %edx
cmpq $50000, %rax
jne .L19
movq %rbp, %rsi
movl $10, %edi
call _Z8printVeciPf
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbx, %rsi
movl $10, %edi
call _Z8printVeciPf
leaq 16(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $200000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $200000, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $200000, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $12500, 52(%rsp)
movl $1, 56(%rsp)
movl $4, 40(%rsp)
movl $1, 44(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L20:
movl $2, %ecx
movl $200000, %edx
movq 32(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rsi
movl $10, %edi
call _Z8printVeciPf
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movq 1096(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $1104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L25:
.cfi_restore_state
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z29__device_stub__Z6VecAddPfS_S_PfS_S_
jmp .L20
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z6VecAddPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6VecAddPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z21__device_stub__VecAddPfS_S_ # -- Begin function _Z21__device_stub__VecAddPfS_S_
.p2align 4, 0x90
.type _Z21__device_stub__VecAddPfS_S_,@function
_Z21__device_stub__VecAddPfS_S_: # @_Z21__device_stub__VecAddPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__VecAddPfS_S_, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_
.cfi_endproc
# -- End function
.globl _Z8printVeciPf # -- Begin function _Z8printVeciPf
.p2align 4, 0x90
.type _Z8printVeciPf,@function
_Z8printVeciPf: # @_Z8printVeciPf
.cfi_startproc
# %bb.0:
testl %edi, %edi
jle .LBB1_4
# %bb.1: # %.lr.ph.preheader
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rsi, %rbx
movl %edi, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB1_2
# %bb.3:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r14
.cfi_restore %r15
.LBB1_4: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end1:
.size _Z8printVeciPf, .Lfunc_end1-_Z8printVeciPf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 1632
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB2_3
# %bb.1: # %.lr.ph
leaq 112(%rsp), %rbx
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB2_2: # =>This Inner Loop Header: Depth=1
movq %rbx, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
movl 420(%rsp), %r8d
movl 500(%rsp), %ecx
movl $.L.str.2, %edi
movl %ebp, %esi
movq %rbx, %rdx
xorl %eax, %eax
callq printf
incl %ebp
cmpl 12(%rsp), %ebp
jl .LBB2_2
.LBB2_3: # %._crit_edge
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %rbx
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %r14
movl $200000, %edi # imm = 0x30D40
callq malloc
movq %rax, %r15
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_4: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbx,%rcx,4)
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rcx,4)
incq %rcx
addl $-2, %eax
cmpq $50000, %rcx # imm = 0xC350
jne .LBB2_4
# %bb.5: # %.lr.ph.i.preheader
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB2_6
# %bb.7: # %_Z8printVeciPf.exit
movl $10, %edi
callq putchar@PLT
movl $.Lstr, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_8: # %.lr.ph.i37
# =>This Inner Loop Header: Depth=1
movss (%r14,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB2_8
# %bb.9: # %_Z8printVeciPf.exit42
movl $10, %edi
callq putchar@PLT
leaq 32(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
leaq 24(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
leaq 16(%rsp), %rdi
movl $200000, %esi # imm = 0x30D40
callq hipMalloc
movq 32(%rsp), %rdi
movl $200000, %edx # imm = 0x30D40
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
movl $200000, %edx # imm = 0x30D40
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967300, %rdi # imm = 0x100000004
leaq 12496(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_11
# %bb.10:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6VecAddPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_11:
movq 16(%rsp), %rsi
movl $200000, %edx # imm = 0x30D40
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_12: # %.lr.ph.i43
# =>This Inner Loop Header: Depth=1
movss (%r15,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r12
cmpq $10, %r12
jne .LBB2_12
# %bb.13: # %_Z8printVeciPf.exit48
movl $10, %edi
callq putchar@PLT
movq 32(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $1584, %rsp # imm = 0x630
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6VecAddPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6VecAddPfS_S_,@object # @_Z6VecAddPfS_S_
.section .rodata,"a",@progbits
.globl _Z6VecAddPfS_S_
.p2align 3, 0x0
_Z6VecAddPfS_S_:
.quad _Z21__device_stub__VecAddPfS_S_
.size _Z6VecAddPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%.2f "
.size .L.str, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Device %d (%s) has %d multiprocessors, and warps of size %d\n"
.size .L.str.2, 61
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6VecAddPfS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "+"
.size .Lstr, 2
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "="
.size .Lstr.1, 2
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__VecAddPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6VecAddPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <assert.h>
#include <vector>
#include <utility>
#include <iostream>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
std::pair<float,float> profileCopies(float* h_a,
float* h_b,
float* d,
unsigned int n)
{
unsigned int bytes = n*sizeof(float);
// events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda(cudaEventCreate(&startEvent));
checkCuda(cudaEventCreate(&stopEvent));
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(d, h_a, bytes, cudaMemcpyHostToDevice));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
//times are in miliseconds
float timeh2d, timed2h;
checkCuda(cudaEventElapsedTime(&timeh2d, startEvent, stopEvent));
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(h_b, d, bytes, cudaMemcpyDeviceToHost));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&timed2h, startEvent, stopEvent));
for (int i = 0; i<n; ++i) {
if (h_a[i]!=h_b[i]) {
printf("*** transfers failed ***");
break;
}
}
// clean up events
checkCuda(cudaEventDestroy(startEvent));
checkCuda(cudaEventDestroy(stopEvent));
return std::make_pair(timeh2d,timed2h);
}
int main()
{
size_t kb = 1024;
size_t GB = kb*kb*kb;
std::vector<size_t> sizes;
for (size_t current = kb; current<=GB; current *= 2)
sizes.push_back(current/sizeof(float));
std::cout << "#Size; H2DPage; H2DPin; D2HPage; D2HPin" << std::endl;
for (unsigned int nElements: sizes) {
const unsigned int bytes = nElements*sizeof(float);
// host arrays
float* h_aPageable, * h_bPageable;
float* h_aPinned, * h_bPinned;
// device array
float* d_a;
// allocate and initialize
h_aPageable = (float*) malloc(bytes); // host pageable
h_bPageable = (float*) malloc(bytes); // host pageable
checkCuda(cudaMallocHost((void**) &h_aPinned, bytes)); // host pinned
checkCuda(cudaMallocHost((void**) &h_bPinned, bytes)); // host pinned
checkCuda(cudaMalloc((void**) &d_a, bytes)); // device
for (int i = 0; i<nElements; ++i) h_aPageable[i] = i;
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPinned, 0, bytes);
// output device info and transfer size
cudaDeviceProp prop;
checkCuda(cudaGetDeviceProperties(&prop, 0));
// perform copies and report bandwidth
auto tPage = profileCopies(h_aPageable, h_bPageable, d_a, nElements);
auto tPinned = profileCopies(h_aPinned, h_bPinned, d_a, nElements);
std::cout << bytes << ";"
<< tPage.first << ";"
<< tPinned.first << ";"
<< tPage.second << ";"
<< tPinned.second << std::endl;
// cleanup
cudaFree(d_a);
cudaFreeHost(h_aPinned);
cudaFreeHost(h_bPinned);
free(h_aPageable);
free(h_bPageable);
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <assert.h>
#include <vector>
#include <utility>
#include <iostream>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
std::pair<float,float> profileCopies(float* h_a,
float* h_b,
float* d,
unsigned int n)
{
unsigned int bytes = n*sizeof(float);
// events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda(cudaEventCreate(&startEvent));
checkCuda(cudaEventCreate(&stopEvent));
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(d, h_a, bytes, cudaMemcpyHostToDevice));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
//times are in miliseconds
float timeh2d, timed2h;
checkCuda(cudaEventElapsedTime(&timeh2d, startEvent, stopEvent));
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(h_b, d, bytes, cudaMemcpyDeviceToHost));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&timed2h, startEvent, stopEvent));
for (int i = 0; i<n; ++i) {
if (h_a[i]!=h_b[i]) {
printf("*** transfers failed ***");
break;
}
}
// clean up events
checkCuda(cudaEventDestroy(startEvent));
checkCuda(cudaEventDestroy(stopEvent));
return std::make_pair(timeh2d,timed2h);
}
int main()
{
size_t kb = 1024;
size_t GB = kb*kb*kb;
std::vector<size_t> sizes;
for (size_t current = kb; current<=GB; current *= 2)
sizes.push_back(current/sizeof(float));
std::cout << "#Size; H2DPage; H2DPin; D2HPage; D2HPin" << std::endl;
for (unsigned int nElements: sizes) {
const unsigned int bytes = nElements*sizeof(float);
// host arrays
float* h_aPageable, * h_bPageable;
float* h_aPinned, * h_bPinned;
// device array
float* d_a;
// allocate and initialize
h_aPageable = (float*) malloc(bytes); // host pageable
h_bPageable = (float*) malloc(bytes); // host pageable
checkCuda(cudaMallocHost((void**) &h_aPinned, bytes)); // host pinned
checkCuda(cudaMallocHost((void**) &h_bPinned, bytes)); // host pinned
checkCuda(cudaMalloc((void**) &d_a, bytes)); // device
for (int i = 0; i<nElements; ++i) h_aPageable[i] = i;
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPinned, 0, bytes);
// output device info and transfer size
cudaDeviceProp prop;
checkCuda(cudaGetDeviceProperties(&prop, 0));
// perform copies and report bandwidth
auto tPage = profileCopies(h_aPageable, h_bPageable, d_a, nElements);
auto tPinned = profileCopies(h_aPinned, h_bPinned, d_a, nElements);
std::cout << bytes << ";"
<< tPage.first << ";"
<< tPinned.first << ";"
<< tPage.second << ";"
<< tPinned.second << std::endl;
// cleanup
cudaFree(d_a);
cudaFreeHost(h_aPinned);
cudaFreeHost(h_bPinned);
free(h_aPageable);
free(h_bPageable);
}
return 0;
} | .file "tmpxft_0009957d_00000000-6_memory_modnvidia.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4057:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "*** transfers failed ***"
.text
.globl _Z13profileCopiesPfS_S_j
.type _Z13profileCopiesPfS_S_j, @function
_Z13profileCopiesPfS_S_j:
.LFB4034:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r13
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leal 0(,%r12,4), %r14d
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movq %rsp, %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %r12d, %r12d
je .L4
movl %r12d, %edx
salq $2, %rdx
movl $0, %eax
.L7:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L9
jne .L9
addq $4, %rax
cmpq %rdx, %rax
jne .L7
jmp .L4
.L9:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L4:
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movl 4(%rsp), %eax
salq $32, %rax
movl (%rsp), %edx
orq %rax, %rdx
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L12
movq %rdx, %xmm0
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4034:
.size _Z13profileCopiesPfS_S_j, .-_Z13profileCopiesPfS_S_j
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4080:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4080:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorImSaImEED2Ev,"axG",@progbits,_ZNSt6vectorImSaImEED5Ev,comdat
.align 2
.weak _ZNSt6vectorImSaImEED2Ev
.type _ZNSt6vectorImSaImEED2Ev, @function
_ZNSt6vectorImSaImEED2Ev:
.LFB4390:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L18
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L18:
ret
.cfi_endproc
.LFE4390:
.size _ZNSt6vectorImSaImEED2Ev, .-_ZNSt6vectorImSaImEED2Ev
.weak _ZNSt6vectorImSaImEED1Ev
.set _ZNSt6vectorImSaImEED1Ev,_ZNSt6vectorImSaImEED2Ev
.section .rodata._ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC1:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
.type _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_, @function
_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_:
.LFB4659:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L38
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L24
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L25
jmp .L32
.L38:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L39:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L27
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L31
.L24:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L32:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L25:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L39
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L29
.L27:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L29:
addq %rbp, %r15
testq %r13, %r13
je .L30
movq 16(%rbx), %rsi
subq %r13, %rsi
.L31:
movq %r13, %rdi
call _ZdlPvm@PLT
.L30:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4659:
.size _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_, .-_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "#Size; H2DPage; H2DPin; D2HPage; D2HPin"
.section .rodata.str1.1
.LC3:
.string ";"
.text
.globl main
.type main, @function
main:
.LFB4044:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4044
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1144, %rsp
.cfi_def_cfa_offset 1200
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $1024, %ebx
leaq 56(%rsp), %rbp
jmp .L43
.L62:
movq %rax, (%rsi)
addq $8, %rsi
movq %rsi, 72(%rsp)
.L42:
addq %rbx, %rbx
cmpq $1073741824, %rbx
ja .L61
.L43:
movq %rbx, %rax
shrq $2, %rax
movq %rax, 56(%rsp)
movq 72(%rsp), %rsi
cmpq 80(%rsp), %rsi
jne .L62
leaq 64(%rsp), %rdi
movq %rbp, %rdx
.LEHB0:
call _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
jmp .L42
.L61:
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 64(%rsp), %r14
movq 72(%rsp), %rax
movq %rax, 8(%rsp)
cmpq %r14, %rax
je .L44
leaq 40(%rsp), %rax
movq %rax, 16(%rsp)
leaq 48(%rsp), %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r15
jmp .L51
.L66:
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMallocHost@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %r12d, %r12d
je .L45
movl %r12d, %r12d
movl $0, %eax
.L46:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq %rax, %r12
jne .L46
.L45:
movq %rbp, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call memcpy@PLT
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %r13, %rdi
call __memset_chk@PLT
movq %rbp, %rdx
movl $0, %esi
movq 48(%rsp), %rdi
call memset@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl (%rsp), %ecx
movq 56(%rsp), %rdx
movq %r13, %rsi
movq %rbx, %rdi
call _Z13profileCopiesPfS_S_j
movq %xmm0, %r12
movl (%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z13profileCopiesPfS_S_j
movq %xmm0, (%rsp)
movq %rbp, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movd %r12d, %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movd (%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r12, %xmm1
shufps $85, %xmm1, %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rsp), %xmm2
shufps $85, %xmm2, %xmm2
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L63
cmpb $0, 56(%r12)
je .L49
movzbl 67(%r12), %esi
.L50:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L64
.L63:
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L65
call _ZSt16__throw_bad_castv@PLT
.L55:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt6vectorImSaImEED1Ev
movq 1128(%rsp), %rax
subq %fs:40, %rax
je .L53
call __stack_chk_fail@PLT
.L65:
call __stack_chk_fail@PLT
.L49:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L50
.L64:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
addq $8, %r14
cmpq %r14, 8(%rsp)
je .L44
.L51:
movq (%r14), %r12
movl %r12d, (%rsp)
leal 0(,%r12,4), %ebp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMallocHost@PLT
.LEHE0:
jmp .L66
.L44:
leaq 64(%rsp), %rdi
call _ZNSt6vectorImSaImEED1Ev
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4044:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4044:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4044-.LLSDACSB4044
.LLSDACSB4044:
.uleb128 .LEHB0-.LFB4044
.uleb128 .LEHE0-.LEHB0
.uleb128 .L55-.LFB4044
.uleb128 0
.uleb128 .LEHB1-.LFB4044
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4044:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <stdio.h>
#include <assert.h>
#include <vector>
#include <utility>
#include <iostream>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
cudaError_t checkCuda(cudaError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != cudaSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", cudaGetErrorString(result));
assert(result == cudaSuccess);
}
#endif
return result;
}
std::pair<float,float> profileCopies(float* h_a,
float* h_b,
float* d,
unsigned int n)
{
unsigned int bytes = n*sizeof(float);
// events for timing
cudaEvent_t startEvent, stopEvent;
checkCuda(cudaEventCreate(&startEvent));
checkCuda(cudaEventCreate(&stopEvent));
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(d, h_a, bytes, cudaMemcpyHostToDevice));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
//times are in miliseconds
float timeh2d, timed2h;
checkCuda(cudaEventElapsedTime(&timeh2d, startEvent, stopEvent));
checkCuda(cudaEventRecord(startEvent, 0));
checkCuda(cudaMemcpy(h_b, d, bytes, cudaMemcpyDeviceToHost));
checkCuda(cudaEventRecord(stopEvent, 0));
checkCuda(cudaEventSynchronize(stopEvent));
checkCuda(cudaEventElapsedTime(&timed2h, startEvent, stopEvent));
for (int i = 0; i<n; ++i) {
if (h_a[i]!=h_b[i]) {
printf("*** transfers failed ***");
break;
}
}
// clean up events
checkCuda(cudaEventDestroy(startEvent));
checkCuda(cudaEventDestroy(stopEvent));
return std::make_pair(timeh2d,timed2h);
}
int main()
{
size_t kb = 1024;
size_t GB = kb*kb*kb;
std::vector<size_t> sizes;
for (size_t current = kb; current<=GB; current *= 2)
sizes.push_back(current/sizeof(float));
std::cout << "#Size; H2DPage; H2DPin; D2HPage; D2HPin" << std::endl;
for (unsigned int nElements: sizes) {
const unsigned int bytes = nElements*sizeof(float);
// host arrays
float* h_aPageable, * h_bPageable;
float* h_aPinned, * h_bPinned;
// device array
float* d_a;
// allocate and initialize
h_aPageable = (float*) malloc(bytes); // host pageable
h_bPageable = (float*) malloc(bytes); // host pageable
checkCuda(cudaMallocHost((void**) &h_aPinned, bytes)); // host pinned
checkCuda(cudaMallocHost((void**) &h_bPinned, bytes)); // host pinned
checkCuda(cudaMalloc((void**) &d_a, bytes)); // device
for (int i = 0; i<nElements; ++i) h_aPageable[i] = i;
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPinned, 0, bytes);
// output device info and transfer size
cudaDeviceProp prop;
checkCuda(cudaGetDeviceProperties(&prop, 0));
// perform copies and report bandwidth
auto tPage = profileCopies(h_aPageable, h_bPageable, d_a, nElements);
auto tPinned = profileCopies(h_aPinned, h_bPinned, d_a, nElements);
std::cout << bytes << ";"
<< tPage.first << ";"
<< tPinned.first << ";"
<< tPage.second << ";"
<< tPinned.second << std::endl;
// cleanup
cudaFree(d_a);
cudaFreeHost(h_aPinned);
cudaFreeHost(h_bPinned);
free(h_aPageable);
free(h_bPageable);
}
return 0;
} | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <vector>
#include <utility>
#include <iostream>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
std::pair<float,float> profileCopies(float* h_a,
float* h_b,
float* d,
unsigned int n)
{
unsigned int bytes = n*sizeof(float);
// events for timing
hipEvent_t startEvent, stopEvent;
checkCuda(hipEventCreate(&startEvent));
checkCuda(hipEventCreate(&stopEvent));
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(d, h_a, bytes, hipMemcpyHostToDevice));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
//times are in miliseconds
float timeh2d, timed2h;
checkCuda(hipEventElapsedTime(&timeh2d, startEvent, stopEvent));
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(h_b, d, bytes, hipMemcpyDeviceToHost));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&timed2h, startEvent, stopEvent));
for (int i = 0; i<n; ++i) {
if (h_a[i]!=h_b[i]) {
printf("*** transfers failed ***");
break;
}
}
// clean up events
checkCuda(hipEventDestroy(startEvent));
checkCuda(hipEventDestroy(stopEvent));
return std::make_pair(timeh2d,timed2h);
}
int main()
{
size_t kb = 1024;
size_t GB = kb*kb*kb;
std::vector<size_t> sizes;
for (size_t current = kb; current<=GB; current *= 2)
sizes.push_back(current/sizeof(float));
std::cout << "#Size; H2DPage; H2DPin; D2HPage; D2HPin" << std::endl;
for (unsigned int nElements: sizes) {
const unsigned int bytes = nElements*sizeof(float);
// host arrays
float* h_aPageable, * h_bPageable;
float* h_aPinned, * h_bPinned;
// device array
float* d_a;
// allocate and initialize
h_aPageable = (float*) malloc(bytes); // host pageable
h_bPageable = (float*) malloc(bytes); // host pageable
checkCuda(hipHostMalloc((void**) &h_aPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipHostMalloc((void**) &h_bPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipMalloc((void**) &d_a, bytes)); // device
for (int i = 0; i<nElements; ++i) h_aPageable[i] = i;
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPinned, 0, bytes);
// output device info and transfer size
hipDeviceProp_t prop;
checkCuda(hipGetDeviceProperties(&prop, 0));
// perform copies and report bandwidth
auto tPage = profileCopies(h_aPageable, h_bPageable, d_a, nElements);
auto tPinned = profileCopies(h_aPinned, h_bPinned, d_a, nElements);
std::cout << bytes << ";"
<< tPage.first << ";"
<< tPinned.first << ";"
<< tPage.second << ";"
<< tPinned.second << std::endl;
// cleanup
hipFree(d_a);
hipHostFree(h_aPinned);
hipHostFree(h_bPinned);
free(h_aPageable);
free(h_bPageable);
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <vector>
#include <utility>
#include <iostream>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
std::pair<float,float> profileCopies(float* h_a,
float* h_b,
float* d,
unsigned int n)
{
unsigned int bytes = n*sizeof(float);
// events for timing
hipEvent_t startEvent, stopEvent;
checkCuda(hipEventCreate(&startEvent));
checkCuda(hipEventCreate(&stopEvent));
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(d, h_a, bytes, hipMemcpyHostToDevice));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
//times are in miliseconds
float timeh2d, timed2h;
checkCuda(hipEventElapsedTime(&timeh2d, startEvent, stopEvent));
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(h_b, d, bytes, hipMemcpyDeviceToHost));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&timed2h, startEvent, stopEvent));
for (int i = 0; i<n; ++i) {
if (h_a[i]!=h_b[i]) {
printf("*** transfers failed ***");
break;
}
}
// clean up events
checkCuda(hipEventDestroy(startEvent));
checkCuda(hipEventDestroy(stopEvent));
return std::make_pair(timeh2d,timed2h);
}
int main()
{
size_t kb = 1024;
size_t GB = kb*kb*kb;
std::vector<size_t> sizes;
for (size_t current = kb; current<=GB; current *= 2)
sizes.push_back(current/sizeof(float));
std::cout << "#Size; H2DPage; H2DPin; D2HPage; D2HPin" << std::endl;
for (unsigned int nElements: sizes) {
const unsigned int bytes = nElements*sizeof(float);
// host arrays
float* h_aPageable, * h_bPageable;
float* h_aPinned, * h_bPinned;
// device array
float* d_a;
// allocate and initialize
h_aPageable = (float*) malloc(bytes); // host pageable
h_bPageable = (float*) malloc(bytes); // host pageable
checkCuda(hipHostMalloc((void**) &h_aPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipHostMalloc((void**) &h_bPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipMalloc((void**) &d_a, bytes)); // device
for (int i = 0; i<nElements; ++i) h_aPageable[i] = i;
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPinned, 0, bytes);
// output device info and transfer size
hipDeviceProp_t prop;
checkCuda(hipGetDeviceProperties(&prop, 0));
// perform copies and report bandwidth
auto tPage = profileCopies(h_aPageable, h_bPageable, d_a, nElements);
auto tPinned = profileCopies(h_aPinned, h_bPinned, d_a, nElements);
std::cout << bytes << ";"
<< tPage.first << ";"
<< tPinned.first << ";"
<< tPage.second << ";"
<< tPinned.second << std::endl;
// cleanup
hipFree(d_a);
hipHostFree(h_aPinned);
hipHostFree(h_bPinned);
free(h_aPageable);
free(h_bPageable);
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Copyright (c) 1993-2015, NVIDIA CORPORATION. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of NVIDIA CORPORATION nor the names of its
* contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <assert.h>
#include <vector>
#include <utility>
#include <iostream>
// Convenience function for checking CUDA runtime API results
// can be wrapped around any runtime API call. No-op in release builds.
inline
hipError_t checkCuda(hipError_t result)
{
#if defined(DEBUG) || defined(_DEBUG)
if (result != hipSuccess) {
fprintf(stderr, "CUDA Runtime Error: %s\n", hipGetErrorString(result));
assert(result == hipSuccess);
}
#endif
return result;
}
std::pair<float,float> profileCopies(float* h_a,
float* h_b,
float* d,
unsigned int n)
{
unsigned int bytes = n*sizeof(float);
// events for timing
hipEvent_t startEvent, stopEvent;
checkCuda(hipEventCreate(&startEvent));
checkCuda(hipEventCreate(&stopEvent));
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(d, h_a, bytes, hipMemcpyHostToDevice));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
//times are in miliseconds
float timeh2d, timed2h;
checkCuda(hipEventElapsedTime(&timeh2d, startEvent, stopEvent));
checkCuda(hipEventRecord(startEvent, 0));
checkCuda(hipMemcpy(h_b, d, bytes, hipMemcpyDeviceToHost));
checkCuda(hipEventRecord(stopEvent, 0));
checkCuda(hipEventSynchronize(stopEvent));
checkCuda(hipEventElapsedTime(&timed2h, startEvent, stopEvent));
for (int i = 0; i<n; ++i) {
if (h_a[i]!=h_b[i]) {
printf("*** transfers failed ***");
break;
}
}
// clean up events
checkCuda(hipEventDestroy(startEvent));
checkCuda(hipEventDestroy(stopEvent));
return std::make_pair(timeh2d,timed2h);
}
int main()
{
size_t kb = 1024;
size_t GB = kb*kb*kb;
std::vector<size_t> sizes;
for (size_t current = kb; current<=GB; current *= 2)
sizes.push_back(current/sizeof(float));
std::cout << "#Size; H2DPage; H2DPin; D2HPage; D2HPin" << std::endl;
for (unsigned int nElements: sizes) {
const unsigned int bytes = nElements*sizeof(float);
// host arrays
float* h_aPageable, * h_bPageable;
float* h_aPinned, * h_bPinned;
// device array
float* d_a;
// allocate and initialize
h_aPageable = (float*) malloc(bytes); // host pageable
h_bPageable = (float*) malloc(bytes); // host pageable
checkCuda(hipHostMalloc((void**) &h_aPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipHostMalloc((void**) &h_bPinned, bytes, hipHostMallocDefault)); // host pinned
checkCuda(hipMalloc((void**) &d_a, bytes)); // device
for (int i = 0; i<nElements; ++i) h_aPageable[i] = i;
memcpy(h_aPinned, h_aPageable, bytes);
memset(h_bPageable, 0, bytes);
memset(h_bPinned, 0, bytes);
// output device info and transfer size
hipDeviceProp_t prop;
checkCuda(hipGetDeviceProperties(&prop, 0));
// perform copies and report bandwidth
auto tPage = profileCopies(h_aPageable, h_bPageable, d_a, nElements);
auto tPinned = profileCopies(h_aPinned, h_bPinned, d_a, nElements);
std::cout << bytes << ";"
<< tPage.first << ";"
<< tPinned.first << ";"
<< tPage.second << ";"
<< tPinned.second << std::endl;
// cleanup
hipFree(d_a);
hipHostFree(h_aPinned);
hipHostFree(h_bPinned);
free(h_aPageable);
free(h_bPageable);
}
return 0;
} | .text
.file "memory_modnvidia.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z13profileCopiesPfS_S_j # -- Begin function _Z13profileCopiesPfS_S_j
.p2align 4, 0x90
.type _Z13profileCopiesPfS_S_j,@function
_Z13profileCopiesPfS_S_j: # @_Z13profileCopiesPfS_S_j
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %r12
movq %rsi, %rbx
movq %rdi, %r14
leal (,%r15,4), %r13d
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 28(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
testl %r15d, %r15d
je .LBB0_5
# %bb.1: # %.lr.ph.preheader
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rbx,%rcx,4), %xmm0
jne .LBB0_4
jp .LBB0_4
# %bb.2: # in Loop: Header=BB0_3 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB0_3
jmp .LBB0_5
.LBB0_4:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.LBB0_5: # %.loopexit
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 24(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
unpcklps %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13profileCopiesPfS_S_j, .Lfunc_end0-_Z13profileCopiesPfS_S_j
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 1600
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1024, %ebx # imm = 0x400
xorl %r12d, %r12d
movabsq $1152921504606846975, %rbp # imm = 0xFFFFFFFFFFFFFFF
xorl %r14d, %r14d
xorl %eax, %eax
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_2: # in Loop: Header=BB1_1 Depth=1
movq %r13, (%r14)
movq %r14, %r13
.LBB1_19: # %_ZNSt6vectorImSaImEE9push_backEOm.exit
# in Loop: Header=BB1_1 Depth=1
leaq 8(%r13), %r14
leaq (%rbx,%rbx), %rcx
cmpq $536870913, %rbx # imm = 0x20000001
movq %rcx, %rbx
jae .LBB1_20
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %r13
shrq $2, %r13
cmpq %rax, %r14
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
subq %r12, %r14
movabsq $9223372036854775800, %rax # imm = 0x7FFFFFFFFFFFFFF8
cmpq %rax, %r14
je .LBB1_4
# %bb.6: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %r12, (%rsp) # 8-byte Spill
movq %r14, %r12
sarq $3, %r12
cmpq $1, %r12
movq %r12, %rax
adcq $0, %rax
leaq (%rax,%r12), %rcx
cmpq %rbp, %rcx
jae .LBB1_7
# %bb.8: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
addq %r12, %rax
jae .LBB1_9
.LBB1_10: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
testq %rbp, %rbp
je .LBB1_11
.LBB1_12: # in Loop: Header=BB1_1 Depth=1
leaq (,%rbp,8), %rdi
.Ltmp0:
callq _Znwm
.Ltmp1:
# %bb.13: # in Loop: Header=BB1_1 Depth=1
movq %rax, %r15
jmp .LBB1_14
.LBB1_7: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %rbp, %rcx
addq %r12, %rax
jb .LBB1_10
.LBB1_9: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %rcx, %rbp
testq %rbp, %rbp
jne .LBB1_12
.LBB1_11: # in Loop: Header=BB1_1 Depth=1
xorl %r15d, %r15d
.LBB1_14: # %_ZNSt12_Vector_baseImSaImEE11_M_allocateEm.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %r13, (%r15,%r12,8)
testq %r14, %r14
movq (%rsp), %r12 # 8-byte Reload
jle .LBB1_16
# %bb.15: # in Loop: Header=BB1_1 Depth=1
movq %r15, %rdi
movq %r12, %rsi
movq %r14, %rdx
callq memmove@PLT
.LBB1_16: # %_ZNSt6vectorImSaImEE11_S_relocateEPmS2_S2_RS0_.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
testq %r12, %r12
je .LBB1_18
# %bb.17: # in Loop: Header=BB1_1 Depth=1
movq %r12, %rdi
callq _ZdlPv
.LBB1_18: # %_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
addq %r15, %r14
leaq (%r15,%rbp,8), %rax
movq %r14, %r13
movq %r15, %r12
movabsq $1152921504606846975, %rbp # imm = 0xFFFFFFFFFFFFFFF
jmp .LBB1_19
.LBB1_20:
.Ltmp3:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp4:
# %bb.21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_22
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_28
# %bb.27:
movzbl 67(%r15), %eax
jmp .LBB1_30
.LBB1_28:
.Ltmp5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp6:
# %bb.29: # %.noexc73
movq (%r15), %rax
.Ltmp7:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp8:
.LBB1_30: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp9:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp10:
# %bb.31: # %.noexc75
.Ltmp11:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp12:
# %bb.32: # %_ZNSolsEPFRSoS_E.exit.preheader
movq %r12, (%rsp) # 8-byte Spill
cmpq %r14, %r12
je .LBB1_54
# %bb.33:
movq (%rsp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB1_34: # %.lr.ph117
# =>This Loop Header: Depth=1
# Child Loop BB1_39 Depth 2
movq (%rbx), %r12
leal (,%r12,4), %r15d
movq %r15, %rdi
callq malloc
movq %rax, %rbp
movq %r15, %rdi
callq malloc
movq %rax, %r14
.Ltmp13:
leaq 24(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostMalloc
.Ltmp14:
# %bb.35: # in Loop: Header=BB1_34 Depth=1
.Ltmp15:
leaq 16(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostMalloc
.Ltmp16:
# %bb.36: # in Loop: Header=BB1_34 Depth=1
.Ltmp17:
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
.Ltmp18:
# %bb.37: # %.preheader
# in Loop: Header=BB1_34 Depth=1
testl %r12d, %r12d
je .LBB1_40
# %bb.38: # %.lr.ph.preheader
# in Loop: Header=BB1_34 Depth=1
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_39: # %.lr.ph
# Parent Loop BB1_34 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbp,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_39
.LBB1_40: # %._crit_edge
# in Loop: Header=BB1_34 Depth=1
movq 24(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq %r14, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
movq 16(%rsp), %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
.Ltmp20:
leaq 72(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
.Ltmp21:
# %bb.41: # in Loop: Header=BB1_34 Depth=1
movq 8(%rsp), %rdx
.Ltmp23:
movq %rbp, %rdi
movq %r14, %rsi
movl %r12d, %ecx
callq _Z13profileCopiesPfS_S_j
movaps %xmm0, 48(%rsp) # 16-byte Spill
.Ltmp24:
# %bb.42: # in Loop: Header=BB1_34 Depth=1
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp26:
movl %r12d, %ecx
callq _Z13profileCopiesPfS_S_j
movaps %xmm0, 32(%rsp) # 16-byte Spill
.Ltmp27:
# %bb.43: # in Loop: Header=BB1_34 Depth=1
.Ltmp28:
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp29:
# %bb.44: # %_ZNSolsEj.exit
# in Loop: Header=BB1_34 Depth=1
.Ltmp30:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp31:
# %bb.45: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit53
# in Loop: Header=BB1_34 Depth=1
movaps 48(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
.Ltmp32:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp33:
# %bb.46: # %_ZNSolsEf.exit
# in Loop: Header=BB1_34 Depth=1
.Ltmp34:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp35:
# %bb.47: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit56
# in Loop: Header=BB1_34 Depth=1
movaps 32(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
.Ltmp36:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp37:
# %bb.48: # %_ZNSolsEf.exit58
# in Loop: Header=BB1_34 Depth=1
.Ltmp38:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp39:
# %bb.49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit60
# in Loop: Header=BB1_34 Depth=1
movaps 48(%rsp), %xmm0 # 16-byte Reload
shufps $85, %xmm0, %xmm0 # xmm0 = xmm0[1,1,1,1]
cvtss2sd %xmm0, %xmm0
.Ltmp40:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp41:
# %bb.50: # %_ZNSolsEf.exit62
# in Loop: Header=BB1_34 Depth=1
.Ltmp42:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp43:
# %bb.51: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit64
# in Loop: Header=BB1_34 Depth=1
movaps 32(%rsp), %xmm0 # 16-byte Reload
shufps $85, %xmm0, %xmm0 # xmm0 = xmm0[1,1,1,1]
cvtss2sd %xmm0, %xmm0
.Ltmp44:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp45:
# %bb.52: # %_ZNSolsEf.exit66
# in Loop: Header=BB1_34 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_53
# %bb.60: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78
# in Loop: Header=BB1_34 Depth=1
cmpb $0, 56(%r12)
je .LBB1_62
# %bb.61: # in Loop: Header=BB1_34 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_64
.p2align 4, 0x90
.LBB1_62: # in Loop: Header=BB1_34 Depth=1
.Ltmp46:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp47:
# %bb.63: # %.noexc83
# in Loop: Header=BB1_34 Depth=1
movq (%r12), %rax
.Ltmp48:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp49:
.LBB1_64: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i80
# in Loop: Header=BB1_34 Depth=1
.Ltmp50:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp51:
# %bb.65: # %.noexc85
# in Loop: Header=BB1_34 Depth=1
.Ltmp52:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp53:
# %bb.66: # %_ZNSolsEPFRSoS_E.exit68
# in Loop: Header=BB1_34 Depth=1
movq 8(%rsp), %rdi
.Ltmp54:
callq hipFree
.Ltmp55:
# %bb.67: # in Loop: Header=BB1_34 Depth=1
movq 24(%rsp), %rdi
.Ltmp56:
callq hipHostFree
.Ltmp57:
# %bb.68: # in Loop: Header=BB1_34 Depth=1
movq 16(%rsp), %rdi
.Ltmp58:
callq hipHostFree
.Ltmp59:
# %bb.69: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_34 Depth=1
movq %rbp, %rdi
callq free
movq %r14, %rdi
callq free
leaq 8(%rbx), %rax
cmpq %r13, %rbx
movq %rax, %rbx
jne .LBB1_34
.LBB1_54: # %_ZNSolsEPFRSoS_E.exit._crit_edge
movq (%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB1_56
# %bb.55:
callq _ZdlPv
.LBB1_56: # %_ZNSt6vectorImSaImEED2Ev.exit
xorl %eax, %eax
addq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_53:
.cfi_def_cfa_offset 1600
.Ltmp61:
callq _ZSt16__throw_bad_castv
.Ltmp62:
# %bb.59: # %.noexc82
.LBB1_4:
.Ltmp67:
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp68:
# %bb.5: # %.noexc
.LBB1_22:
.Ltmp64:
callq _ZSt16__throw_bad_castv
.Ltmp65:
# %bb.25: # %.noexc72
.LBB1_57:
.Ltmp66:
movq %rax, %r14
jmp .LBB1_75
.LBB1_23: # %.loopexit97
.Ltmp2:
jmp .LBB1_74
.LBB1_24: # %.loopexit.split-lp98
.Ltmp69:
movq %rax, %r14
jmp .LBB1_75
.LBB1_73: # %.loopexit.split-lp
.Ltmp63:
jmp .LBB1_74
.LBB1_70:
.Ltmp22:
jmp .LBB1_74
.LBB1_71:
.Ltmp25:
jmp .LBB1_74
.LBB1_58:
.Ltmp19:
jmp .LBB1_74
.LBB1_72: # %.loopexit
.Ltmp60:
.LBB1_74:
movq %rax, %r14
movq (%rsp), %r12 # 8-byte Reload
.LBB1_75:
testq %r12, %r12
je .LBB1_77
# %bb.76:
movq %r12, %rdi
callq _ZdlPv
.LBB1_77: # %_ZNSt6vectorImSaImEED2Ev.exit70
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp3 # Call between .Ltmp3 and .Ltmp12
.uleb128 .Ltmp66-.Lfunc_begin0 # jumps to .Ltmp66
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp18-.Ltmp13 # Call between .Ltmp13 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp20-.Ltmp18 # Call between .Ltmp18 and .Ltmp20
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp59-.Ltmp26 # Call between .Ltmp26 and .Ltmp59
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp61-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp62-.Ltmp61 # Call between .Ltmp61 and .Ltmp62
.uleb128 .Ltmp63-.Lfunc_begin0 # jumps to .Ltmp63
.byte 0 # On action: cleanup
.uleb128 .Ltmp67-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp68-.Ltmp67 # Call between .Ltmp67 and .Ltmp68
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp64-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp65-.Ltmp64 # Call between .Ltmp64 and .Ltmp65
.uleb128 .Ltmp66-.Lfunc_begin0 # jumps to .Ltmp66
.byte 0 # On action: cleanup
.uleb128 .Ltmp65-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end1-.Ltmp65 # Call between .Ltmp65 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "*** transfers failed ***"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "#Size
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "vector::_M_realloc_insert"
.size .L.str.3, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009957d_00000000-6_memory_modnvidia.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4057:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "*** transfers failed ***"
.text
.globl _Z13profileCopiesPfS_S_j
.type _Z13profileCopiesPfS_S_j, @function
_Z13profileCopiesPfS_S_j:
.LFB4034:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $32, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, %r13
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
leal 0(,%r12,4), %r14d
movl $1, %ecx
movq %r14, %rdx
movq %rbx, %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
movq %rsp, %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $2, %ecx
movq %r14, %rdx
movq %r13, %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq 16(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %r12d, %r12d
je .L4
movl %r12d, %edx
salq $2, %rdx
movl $0, %eax
.L7:
movss (%rbx,%rax), %xmm0
ucomiss 0(%rbp,%rax), %xmm0
jp .L9
jne .L9
addq $4, %rax
cmpq %rdx, %rax
jne .L7
jmp .L4
.L9:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L4:
movq 8(%rsp), %rdi
call cudaEventDestroy@PLT
movq 16(%rsp), %rdi
call cudaEventDestroy@PLT
movl 4(%rsp), %eax
salq $32, %rax
movl (%rsp), %edx
orq %rax, %rdx
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L12
movq %rdx, %xmm0
addq $32, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4034:
.size _Z13profileCopiesPfS_S_j, .-_Z13profileCopiesPfS_S_j
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4080:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4080:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorImSaImEED2Ev,"axG",@progbits,_ZNSt6vectorImSaImEED5Ev,comdat
.align 2
.weak _ZNSt6vectorImSaImEED2Ev
.type _ZNSt6vectorImSaImEED2Ev, @function
_ZNSt6vectorImSaImEED2Ev:
.LFB4390:
.cfi_startproc
endbr64
movq (%rdi), %rax
testq %rax, %rax
je .L18
subq $8, %rsp
.cfi_def_cfa_offset 16
movq 16(%rdi), %rsi
subq %rax, %rsi
movq %rax, %rdi
call _ZdlPvm@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.L18:
ret
.cfi_endproc
.LFE4390:
.size _ZNSt6vectorImSaImEED2Ev, .-_ZNSt6vectorImSaImEED2Ev
.weak _ZNSt6vectorImSaImEED1Ev
.set _ZNSt6vectorImSaImEED1Ev,_ZNSt6vectorImSaImEED2Ev
.section .rodata._ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_.str1.1,"aMS",@progbits,1
.LC1:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_,"axG",@progbits,_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
.type _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_, @function
_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_:
.LFB4659:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rsi, (%rsp)
movq %rdx, 8(%rsp)
movq 8(%rdi), %rbp
movq (%rdi), %r13
movq %rbp, %rax
subq %r13, %rax
sarq $3, %rax
movabsq $1152921504606846975, %rdx
cmpq %rdx, %rax
je .L38
movq %rdi, %rbx
cmpq %r13, %rbp
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L24
movabsq $1152921504606846975, %r14
cmpq %r14, %rax
cmovbe %rax, %r14
movq (%rsp), %r15
subq %r13, %r15
movl $0, %r12d
testq %rax, %rax
je .L25
jmp .L32
.L38:
leaq .LC1(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L39:
movq %r15, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memmove@PLT
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jg .L27
addq %rbp, %r15
movq 16(%rbx), %rsi
subq %r13, %rsi
jmp .L31
.L24:
movq (%rsp), %r15
subq %r13, %r15
movabsq $1152921504606846975, %r14
.L32:
leaq 0(,%r14,8), %rdi
call _Znwm@PLT
movq %rax, %r12
.L25:
movq 8(%rsp), %rax
movq (%rax), %rax
movq %rax, (%r12,%r15)
testq %r15, %r15
jg .L39
leaq 8(%r12,%r15), %r15
movq (%rsp), %rax
subq %rax, %rbp
testq %rbp, %rbp
jle .L29
.L27:
movq %rbp, %rdx
movq (%rsp), %rsi
movq %r15, %rdi
call memcpy@PLT
.L29:
addq %rbp, %r15
testq %r13, %r13
je .L30
movq 16(%rbx), %rsi
subq %r13, %rsi
.L31:
movq %r13, %rdi
call _ZdlPvm@PLT
.L30:
movq %r12, (%rbx)
movq %r15, 8(%rbx)
leaq (%r12,%r14,8), %rax
movq %rax, 16(%rbx)
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4659:
.size _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_, .-_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "#Size; H2DPage; H2DPin; D2HPage; D2HPin"
.section .rodata.str1.1
.LC3:
.string ";"
.text
.globl main
.type main, @function
main:
.LFB4044:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4044
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $1144, %rsp
.cfi_def_cfa_offset 1200
movq %fs:40, %rax
movq %rax, 1128(%rsp)
xorl %eax, %eax
movq $0, 64(%rsp)
movq $0, 72(%rsp)
movq $0, 80(%rsp)
movl $1024, %ebx
leaq 56(%rsp), %rbp
jmp .L43
.L62:
movq %rax, (%rsi)
addq $8, %rsi
movq %rsi, 72(%rsp)
.L42:
addq %rbx, %rbx
cmpq $1073741824, %rbx
ja .L61
.L43:
movq %rbx, %rax
shrq $2, %rax
movq %rax, 56(%rsp)
movq 72(%rsp), %rsi
cmpq 80(%rsp), %rsi
jne .L62
leaq 64(%rsp), %rdi
movq %rbp, %rdx
.LEHB0:
call _ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_
jmp .L42
.L61:
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 64(%rsp), %r14
movq 72(%rsp), %rax
movq %rax, 8(%rsp)
cmpq %r14, %rax
je .L44
leaq 40(%rsp), %rax
movq %rax, 16(%rsp)
leaq 48(%rsp), %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r15
jmp .L51
.L66:
movq %rbp, %rsi
movq 24(%rsp), %rdi
call cudaMallocHost@PLT
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
testl %r12d, %r12d
je .L45
movl %r12d, %r12d
movl $0, %eax
.L46:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq %rax, %r12
jne .L46
.L45:
movq %rbp, %rdx
movq %rbx, %rsi
movq 40(%rsp), %rdi
call memcpy@PLT
movq %rbp, %rcx
movq %rbp, %rdx
movl $0, %esi
movq %r13, %rdi
call __memset_chk@PLT
movq %rbp, %rdx
movl $0, %esi
movq 48(%rsp), %rdi
call memset@PLT
leaq 96(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
movl (%rsp), %ecx
movq 56(%rsp), %rdx
movq %r13, %rsi
movq %rbx, %rdi
call _Z13profileCopiesPfS_S_j
movq %xmm0, %r12
movl (%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z13profileCopiesPfS_S_j
movq %xmm0, (%rsp)
movq %rbp, %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movd %r12d, %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movd (%rsp), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %r12, %xmm1
shufps $85, %xmm1, %xmm1
pxor %xmm0, %xmm0
cvtss2sd %xmm1, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movl $1, %edx
movq %r15, %rsi
movq %rax, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq (%rsp), %xmm2
shufps $85, %xmm2, %xmm2
pxor %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
movq %rbp, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rbp
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%rbp,%rax), %r12
testq %r12, %r12
je .L63
cmpb $0, 56(%r12)
je .L49
movzbl 67(%r12), %esi
.L50:
movsbl %sil, %esi
movq %rbp, %rdi
call _ZNSo3putEc@PLT
jmp .L64
.L63:
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L65
call _ZSt16__throw_bad_castv@PLT
.L55:
endbr64
movq %rax, %rbx
leaq 64(%rsp), %rdi
call _ZNSt6vectorImSaImEED1Ev
movq 1128(%rsp), %rax
subq %fs:40, %rax
je .L53
call __stack_chk_fail@PLT
.L65:
call __stack_chk_fail@PLT
.L49:
movq %r12, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%r12), %rax
movl $10, %esi
movq %r12, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L50
.L64:
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFreeHost@PLT
movq 48(%rsp), %rdi
call cudaFreeHost@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
addq $8, %r14
cmpq %r14, 8(%rsp)
je .L44
.L51:
movq (%r14), %r12
movl %r12d, (%rsp)
leal 0(,%r12,4), %ebp
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movq %rbp, %rdi
call malloc@PLT
movq %rax, %r13
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMallocHost@PLT
.LEHE0:
jmp .L66
.L44:
leaq 64(%rsp), %rdi
call _ZNSt6vectorImSaImEED1Ev
movq 1128(%rsp), %rax
subq %fs:40, %rax
jne .L67
movl $0, %eax
addq $1144, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L53:
.cfi_restore_state
movq %rbx, %rdi
.LEHB1:
call _Unwind_Resume@PLT
.LEHE1:
.L67:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4044:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4044:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4044-.LLSDACSB4044
.LLSDACSB4044:
.uleb128 .LEHB0-.LFB4044
.uleb128 .LEHE0-.LEHB0
.uleb128 .L55-.LFB4044
.uleb128 0
.uleb128 .LEHB1-.LFB4044
.uleb128 .LEHE1-.LEHB1
.uleb128 0
.uleb128 0
.LLSDACSE4044:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "memory_modnvidia.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z13profileCopiesPfS_S_j # -- Begin function _Z13profileCopiesPfS_S_j
.p2align 4, 0x90
.type _Z13profileCopiesPfS_S_j,@function
_Z13profileCopiesPfS_S_j: # @_Z13profileCopiesPfS_S_j
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %ecx, %r15d
movq %rdx, %r12
movq %rsi, %rbx
movq %rdi, %r14
leal (,%r15,4), %r13d
leaq 16(%rsp), %rdi
callq hipEventCreate
leaq 8(%rsp), %rdi
callq hipEventCreate
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %r12, %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 28(%rsp), %rdi
callq hipEventElapsedTime
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rdi
movq %r12, %rsi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 8(%rsp), %rdi
callq hipEventSynchronize
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
testl %r15d, %r15d
je .LBB0_5
# %bb.1: # %.lr.ph.preheader
movl %r15d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_3: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movss (%r14,%rcx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
ucomiss (%rbx,%rcx,4), %xmm0
jne .LBB0_4
jp .LBB0_4
# %bb.2: # in Loop: Header=BB0_3 Depth=1
incq %rcx
cmpq %rcx, %rax
jne .LBB0_3
jmp .LBB0_5
.LBB0_4:
movl $.L.str, %edi
xorl %eax, %eax
callq printf
.LBB0_5: # %.loopexit
movq 16(%rsp), %rdi
callq hipEventDestroy
movq 8(%rsp), %rdi
callq hipEventDestroy
movss 28(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss 24(%rsp), %xmm1 # xmm1 = mem[0],zero,zero,zero
unpcklps %xmm1, %xmm0 # xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13profileCopiesPfS_S_j, .Lfunc_end0-_Z13profileCopiesPfS_S_j
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 1600
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1024, %ebx # imm = 0x400
xorl %r12d, %r12d
movabsq $1152921504606846975, %rbp # imm = 0xFFFFFFFFFFFFFFF
xorl %r14d, %r14d
xorl %eax, %eax
jmp .LBB1_1
.p2align 4, 0x90
.LBB1_2: # in Loop: Header=BB1_1 Depth=1
movq %r13, (%r14)
movq %r14, %r13
.LBB1_19: # %_ZNSt6vectorImSaImEE9push_backEOm.exit
# in Loop: Header=BB1_1 Depth=1
leaq 8(%r13), %r14
leaq (%rbx,%rbx), %rcx
cmpq $536870913, %rbx # imm = 0x20000001
movq %rcx, %rbx
jae .LBB1_20
.LBB1_1: # =>This Inner Loop Header: Depth=1
movq %rbx, %r13
shrq $2, %r13
cmpq %rax, %r14
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
subq %r12, %r14
movabsq $9223372036854775800, %rax # imm = 0x7FFFFFFFFFFFFFF8
cmpq %rax, %r14
je .LBB1_4
# %bb.6: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %r12, (%rsp) # 8-byte Spill
movq %r14, %r12
sarq $3, %r12
cmpq $1, %r12
movq %r12, %rax
adcq $0, %rax
leaq (%rax,%r12), %rcx
cmpq %rbp, %rcx
jae .LBB1_7
# %bb.8: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
addq %r12, %rax
jae .LBB1_9
.LBB1_10: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
testq %rbp, %rbp
je .LBB1_11
.LBB1_12: # in Loop: Header=BB1_1 Depth=1
leaq (,%rbp,8), %rdi
.Ltmp0:
callq _Znwm
.Ltmp1:
# %bb.13: # in Loop: Header=BB1_1 Depth=1
movq %rax, %r15
jmp .LBB1_14
.LBB1_7: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %rbp, %rcx
addq %r12, %rax
jb .LBB1_10
.LBB1_9: # %_ZNKSt6vectorImSaImEE12_M_check_lenEmPKc.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %rcx, %rbp
testq %rbp, %rbp
jne .LBB1_12
.LBB1_11: # in Loop: Header=BB1_1 Depth=1
xorl %r15d, %r15d
.LBB1_14: # %_ZNSt12_Vector_baseImSaImEE11_M_allocateEm.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
movq %r13, (%r15,%r12,8)
testq %r14, %r14
movq (%rsp), %r12 # 8-byte Reload
jle .LBB1_16
# %bb.15: # in Loop: Header=BB1_1 Depth=1
movq %r15, %rdi
movq %r12, %rsi
movq %r14, %rdx
callq memmove@PLT
.LBB1_16: # %_ZNSt6vectorImSaImEE11_S_relocateEPmS2_S2_RS0_.exit.i.i.i
# in Loop: Header=BB1_1 Depth=1
testq %r12, %r12
je .LBB1_18
# %bb.17: # in Loop: Header=BB1_1 Depth=1
movq %r12, %rdi
callq _ZdlPv
.LBB1_18: # %_ZNSt6vectorImSaImEE17_M_realloc_insertIJmEEEvN9__gnu_cxx17__normal_iteratorIPmS1_EEDpOT_.exit.i.i
# in Loop: Header=BB1_1 Depth=1
addq %r15, %r14
leaq (%r15,%rbp,8), %rax
movq %r14, %r13
movq %r15, %r12
movabsq $1152921504606846975, %rbp # imm = 0xFFFFFFFFFFFFFFF
jmp .LBB1_19
.LBB1_20:
.Ltmp3:
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $39, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp4:
# %bb.21: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r15
testq %r15, %r15
je .LBB1_22
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB1_28
# %bb.27:
movzbl 67(%r15), %eax
jmp .LBB1_30
.LBB1_28:
.Ltmp5:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp6:
# %bb.29: # %.noexc73
movq (%r15), %rax
.Ltmp7:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp8:
.LBB1_30: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp9:
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
.Ltmp10:
# %bb.31: # %.noexc75
.Ltmp11:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp12:
# %bb.32: # %_ZNSolsEPFRSoS_E.exit.preheader
movq %r12, (%rsp) # 8-byte Spill
cmpq %r14, %r12
je .LBB1_54
# %bb.33:
movq (%rsp), %rbx # 8-byte Reload
.p2align 4, 0x90
.LBB1_34: # %.lr.ph117
# =>This Loop Header: Depth=1
# Child Loop BB1_39 Depth 2
movq (%rbx), %r12
leal (,%r12,4), %r15d
movq %r15, %rdi
callq malloc
movq %rax, %rbp
movq %r15, %rdi
callq malloc
movq %rax, %r14
.Ltmp13:
leaq 24(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostMalloc
.Ltmp14:
# %bb.35: # in Loop: Header=BB1_34 Depth=1
.Ltmp15:
leaq 16(%rsp), %rdi
movq %r15, %rsi
xorl %edx, %edx
callq hipHostMalloc
.Ltmp16:
# %bb.36: # in Loop: Header=BB1_34 Depth=1
.Ltmp17:
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
.Ltmp18:
# %bb.37: # %.preheader
# in Loop: Header=BB1_34 Depth=1
testl %r12d, %r12d
je .LBB1_40
# %bb.38: # %.lr.ph.preheader
# in Loop: Header=BB1_34 Depth=1
movl %r12d, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_39: # %.lr.ph
# Parent Loop BB1_34 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %ecx, %xmm0
movss %xmm0, (%rbp,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_39
.LBB1_40: # %._crit_edge
# in Loop: Header=BB1_34 Depth=1
movq 24(%rsp), %rdi
movq %rbp, %rsi
movq %r15, %rdx
callq memcpy@PLT
movq %r14, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
movq 16(%rsp), %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
.Ltmp20:
leaq 72(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
.Ltmp21:
# %bb.41: # in Loop: Header=BB1_34 Depth=1
movq 8(%rsp), %rdx
.Ltmp23:
movq %rbp, %rdi
movq %r14, %rsi
movl %r12d, %ecx
callq _Z13profileCopiesPfS_S_j
movaps %xmm0, 48(%rsp) # 16-byte Spill
.Ltmp24:
# %bb.42: # in Loop: Header=BB1_34 Depth=1
movq 24(%rsp), %rdi
movq 16(%rsp), %rsi
movq 8(%rsp), %rdx
.Ltmp26:
movl %r12d, %ecx
callq _Z13profileCopiesPfS_S_j
movaps %xmm0, 32(%rsp) # 16-byte Spill
.Ltmp27:
# %bb.43: # in Loop: Header=BB1_34 Depth=1
.Ltmp28:
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertImEERSoT_
.Ltmp29:
# %bb.44: # %_ZNSolsEj.exit
# in Loop: Header=BB1_34 Depth=1
.Ltmp30:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp31:
# %bb.45: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit53
# in Loop: Header=BB1_34 Depth=1
movaps 48(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
.Ltmp32:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp33:
# %bb.46: # %_ZNSolsEf.exit
# in Loop: Header=BB1_34 Depth=1
.Ltmp34:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp35:
# %bb.47: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit56
# in Loop: Header=BB1_34 Depth=1
movaps 32(%rsp), %xmm0 # 16-byte Reload
cvtss2sd %xmm0, %xmm0
.Ltmp36:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp37:
# %bb.48: # %_ZNSolsEf.exit58
# in Loop: Header=BB1_34 Depth=1
.Ltmp38:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp39:
# %bb.49: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit60
# in Loop: Header=BB1_34 Depth=1
movaps 48(%rsp), %xmm0 # 16-byte Reload
shufps $85, %xmm0, %xmm0 # xmm0 = xmm0[1,1,1,1]
cvtss2sd %xmm0, %xmm0
.Ltmp40:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp41:
# %bb.50: # %_ZNSolsEf.exit62
# in Loop: Header=BB1_34 Depth=1
.Ltmp42:
movq %rax, %r15
movl $.L.str.2, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp43:
# %bb.51: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit64
# in Loop: Header=BB1_34 Depth=1
movaps 32(%rsp), %xmm0 # 16-byte Reload
shufps $85, %xmm0, %xmm0 # xmm0 = xmm0[1,1,1,1]
cvtss2sd %xmm0, %xmm0
.Ltmp44:
movq %r15, %rdi
callq _ZNSo9_M_insertIdEERSoT_
.Ltmp45:
# %bb.52: # %_ZNSolsEf.exit66
# in Loop: Header=BB1_34 Depth=1
movq %rax, %r15
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r15,%rax), %r12
testq %r12, %r12
je .LBB1_53
# %bb.60: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78
# in Loop: Header=BB1_34 Depth=1
cmpb $0, 56(%r12)
je .LBB1_62
# %bb.61: # in Loop: Header=BB1_34 Depth=1
movzbl 67(%r12), %eax
jmp .LBB1_64
.p2align 4, 0x90
.LBB1_62: # in Loop: Header=BB1_34 Depth=1
.Ltmp46:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp47:
# %bb.63: # %.noexc83
# in Loop: Header=BB1_34 Depth=1
movq (%r12), %rax
.Ltmp48:
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp49:
.LBB1_64: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i80
# in Loop: Header=BB1_34 Depth=1
.Ltmp50:
movsbl %al, %esi
movq %r15, %rdi
callq _ZNSo3putEc
.Ltmp51:
# %bb.65: # %.noexc85
# in Loop: Header=BB1_34 Depth=1
.Ltmp52:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp53:
# %bb.66: # %_ZNSolsEPFRSoS_E.exit68
# in Loop: Header=BB1_34 Depth=1
movq 8(%rsp), %rdi
.Ltmp54:
callq hipFree
.Ltmp55:
# %bb.67: # in Loop: Header=BB1_34 Depth=1
movq 24(%rsp), %rdi
.Ltmp56:
callq hipHostFree
.Ltmp57:
# %bb.68: # in Loop: Header=BB1_34 Depth=1
movq 16(%rsp), %rdi
.Ltmp58:
callq hipHostFree
.Ltmp59:
# %bb.69: # %_ZNSolsEPFRSoS_E.exit
# in Loop: Header=BB1_34 Depth=1
movq %rbp, %rdi
callq free
movq %r14, %rdi
callq free
leaq 8(%rbx), %rax
cmpq %r13, %rbx
movq %rax, %rbx
jne .LBB1_34
.LBB1_54: # %_ZNSolsEPFRSoS_E.exit._crit_edge
movq (%rsp), %rdi # 8-byte Reload
testq %rdi, %rdi
je .LBB1_56
# %bb.55:
callq _ZdlPv
.LBB1_56: # %_ZNSt6vectorImSaImEED2Ev.exit
xorl %eax, %eax
addq $1544, %rsp # imm = 0x608
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_53:
.cfi_def_cfa_offset 1600
.Ltmp61:
callq _ZSt16__throw_bad_castv
.Ltmp62:
# %bb.59: # %.noexc82
.LBB1_4:
.Ltmp67:
movl $.L.str.3, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp68:
# %bb.5: # %.noexc
.LBB1_22:
.Ltmp64:
callq _ZSt16__throw_bad_castv
.Ltmp65:
# %bb.25: # %.noexc72
.LBB1_57:
.Ltmp66:
movq %rax, %r14
jmp .LBB1_75
.LBB1_23: # %.loopexit97
.Ltmp2:
jmp .LBB1_74
.LBB1_24: # %.loopexit.split-lp98
.Ltmp69:
movq %rax, %r14
jmp .LBB1_75
.LBB1_73: # %.loopexit.split-lp
.Ltmp63:
jmp .LBB1_74
.LBB1_70:
.Ltmp22:
jmp .LBB1_74
.LBB1_71:
.Ltmp25:
jmp .LBB1_74
.LBB1_58:
.Ltmp19:
jmp .LBB1_74
.LBB1_72: # %.loopexit
.Ltmp60:
.LBB1_74:
movq %rax, %r14
movq (%rsp), %r12 # 8-byte Reload
.LBB1_75:
testq %r12, %r12
je .LBB1_77
# %bb.76:
movq %r12, %rdi
callq _ZdlPv
.LBB1_77: # %_ZNSt6vectorImSaImEED2Ev.exit70
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp1-.Ltmp0 # Call between .Ltmp0 and .Ltmp1
.uleb128 .Ltmp2-.Lfunc_begin0 # jumps to .Ltmp2
.byte 0 # On action: cleanup
.uleb128 .Ltmp1-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp3-.Ltmp1 # Call between .Ltmp1 and .Ltmp3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp3-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp12-.Ltmp3 # Call between .Ltmp3 and .Ltmp12
.uleb128 .Ltmp66-.Lfunc_begin0 # jumps to .Ltmp66
.byte 0 # On action: cleanup
.uleb128 .Ltmp13-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp18-.Ltmp13 # Call between .Ltmp13 and .Ltmp18
.uleb128 .Ltmp19-.Lfunc_begin0 # jumps to .Ltmp19
.byte 0 # On action: cleanup
.uleb128 .Ltmp18-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp20-.Ltmp18 # Call between .Ltmp18 and .Ltmp20
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp20-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp21-.Ltmp20 # Call between .Ltmp20 and .Ltmp21
.uleb128 .Ltmp22-.Lfunc_begin0 # jumps to .Ltmp22
.byte 0 # On action: cleanup
.uleb128 .Ltmp23-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp24-.Ltmp23 # Call between .Ltmp23 and .Ltmp24
.uleb128 .Ltmp25-.Lfunc_begin0 # jumps to .Ltmp25
.byte 0 # On action: cleanup
.uleb128 .Ltmp26-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp59-.Ltmp26 # Call between .Ltmp26 and .Ltmp59
.uleb128 .Ltmp60-.Lfunc_begin0 # jumps to .Ltmp60
.byte 0 # On action: cleanup
.uleb128 .Ltmp61-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp62-.Ltmp61 # Call between .Ltmp61 and .Ltmp62
.uleb128 .Ltmp63-.Lfunc_begin0 # jumps to .Ltmp63
.byte 0 # On action: cleanup
.uleb128 .Ltmp67-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp68-.Ltmp67 # Call between .Ltmp67 and .Ltmp68
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp64-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp65-.Ltmp64 # Call between .Ltmp64 and .Ltmp65
.uleb128 .Ltmp66-.Lfunc_begin0 # jumps to .Ltmp66
.byte 0 # On action: cleanup
.uleb128 .Ltmp65-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Lfunc_end1-.Ltmp65 # Call between .Ltmp65 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "*** transfers failed ***"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "#Size
.size .L.str.1, 40
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "vector::_M_realloc_insert"
.size .L.str.3, 26
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void convn_same_kernel(float *output, float *data, float *kernel, const int H, const int W, const int kH, const int kW) {
// Matrix index
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= H || y >= W)
return;
const int i0 = kW / 2, j0 = kH / 2;
float sum = 0;
for (int i = 0; i < kW; ++i) {
for(int j = 0; j < kH; ++j) {
int ii = y - i + i0;
int jj = x - j + j0;
if ( ii < 0 || ii >= W || jj < 0 || jj >= H )
continue;
sum += kernel[ i * kH + j ] * data[ ii * H + jj ];
}
}
output[y * H + x] = sum;
} | code for sm_80
Function : _Z17convn_same_kernelPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x4], R3 ; /* 0x0000010006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f03270 */
/*00d0*/ ISETP.GT.OR P0, PT, R0, c[0x0][0x184], !P0 ; /* 0x0000610000007a0c */
/* 0x000fe20004704670 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*00f0*/ @P0 BRA 0x7d0 ; /* 0x000006d000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0110*/ UMOV UR6, 0x2 ; /* 0x0000000200067882 */
/* 0x000fe20000000000 */
/*0120*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe200078e00ff */
/*0130*/ ULDC UR5, c[0x0][0x184] ; /* 0x0000610000057ab9 */
/* 0x000fe20000000800 */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R0, -R0, c[0x0][0x180], RZ ; /* 0x0000600000007a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ LEA.HI R10, R8.reuse, c[0x0][0x180], RZ, 0x1 ; /* 0x00006000080a7a11 */
/* 0x040fe200078f08ff */
/*0180*/ UIMAD.WIDE.U32 UR4, UR6, UR5, UR4 ; /* 0x00000005060472a5 */
/* 0x000fe2000f8e0004 */
/*0190*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*01a0*/ ISETP.GE.U32.AND P3, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f66070 */
/*01b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*01c0*/ SHF.R.S32.HI R10, RZ, 0x1, R10 ; /* 0x00000001ff0a7819 */
/* 0x000fe2000001140a */
/*01d0*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe20008011405 */
/*01e0*/ IADD3 R11, -R8, c[0x0][0x180], RZ ; /* 0x00006000080b7a10 */
/* 0x000fc80007ffe1ff */
/*01f0*/ IMAD.MOV.U32 R15, RZ, RZ, R9.reuse ; /* 0x000000ffff0f7224 */
/* 0x100fe200078e0009 */
/*0200*/ IADD3 R12, R6, UR5, -R9 ; /* 0x00000005060c7c10 */
/* 0x000fe2000fffe809 */
/*0210*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc40007ffe0ff */
/*0230*/ ISETP.NE.AND P4, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f85270 */
/*0240*/ ISETP.GE.AND P5, PT, R9, c[0x0][0x184], PT ; /* 0x0000610009007a0c */
/* 0x000fe20003fa6270 */
/*0250*/ @!P3 BRA 0x510 ; /* 0x000002b00000b947 */
/* 0x000ff40003800000 */
/*0260*/ ISETP.GE.AND P6, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003fc6270 */
/*0270*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fc600078e000b */
/*0290*/ IADD3 R3, R10, R7, -R14 ; /* 0x000000070a037210 */
/* 0x000fe20007ffe80e */
/*02a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*02b0*/ LOP3.LUT R2, R3, R12, RZ, 0xfc, !PT ; /* 0x0000000c03027212 */
/* 0x000fe200078efcff */
/*02c0*/ IMAD R4, R12, c[0x0][0x178], R3 ; /* 0x00005e000c047a24 */
/* 0x000fc600078e0203 */
/*02d0*/ ISETP.LT.OR P1, PT, R2, RZ, P6 ; /* 0x000000ff0200720c */
/* 0x000fe20003721670 */
/*02e0*/ IMAD R2, R15, c[0x0][0x180], R14 ; /* 0x000060000f027a24 */
/* 0x000fc600078e020e */
/*02f0*/ ISETP.GE.OR P1, PT, R3, c[0x0][0x178], P1 ; /* 0x00005e0003007a0c */
/* 0x000fe20000f26670 */
/*0300*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0205 */
/*0310*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fd000078e0205 */
/*0320*/ @!P1 LDG.E R17, [R2.64] ; /* 0x0000000802119981 */
/* 0x000ea8000c1e1900 */
/*0330*/ @!P1 LDG.E R16, [R4.64] ; /* 0x0000000804109981 */
/* 0x000ea2000c1e1900 */
/*0340*/ IADD3 R19, R7.reuse, -0x1, -R14.reuse ; /* 0xffffffff07137810 */
/* 0x140fe40007ffe80e */
/*0350*/ IADD3 R21, R7.reuse, -0x2, -R14.reuse ; /* 0xfffffffe07157810 */
/* 0x140fe40007ffe80e */
/*0360*/ IADD3 R23, R7, -0x3, -R14 ; /* 0xfffffffd07177810 */
/* 0x000fe20007ffe80e */
/*0370*/ IMAD.IADD R19, R19, 0x1, R10 ; /* 0x0000000113137824 */
/* 0x000fc400078e020a */
/*0380*/ IMAD.IADD R21, R21, 0x1, R10.reuse ; /* 0x0000000115157824 */
/* 0x100fe400078e020a */
/*0390*/ IMAD.IADD R23, R23, 0x1, R10 ; /* 0x0000000117177824 */
/* 0x000fe200078e020a */
/*03a0*/ LOP3.LUT R18, R19, R12.reuse, RZ, 0xfc, !PT ; /* 0x0000000c13127212 */
/* 0x080fe400078efcff */
/*03b0*/ LOP3.LUT R20, R21, R12, RZ, 0xfc, !PT ; /* 0x0000000c15147212 */
/* 0x000fe400078efcff */
/*03c0*/ ISETP.LT.OR P0, PT, R18, RZ, P6 ; /* 0x000000ff1200720c */
/* 0x000fe40003701670 */
/*03d0*/ ISETP.LT.OR P2, PT, R20, RZ, P6 ; /* 0x000000ff1400720c */
/* 0x000fe40003741670 */
/*03e0*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x178], P0 ; /* 0x00005e0013007a0c */
/* 0x000fc40000706670 */
/*03f0*/ LOP3.LUT R18, R23, R12, RZ, 0xfc, !PT ; /* 0x0000000c17127212 */
/* 0x000fe400078efcff */
/*0400*/ ISETP.GE.OR P2, PT, R21, c[0x0][0x178], P2 ; /* 0x00005e0015007a0c */
/* 0x000fda0001746670 */
/*0410*/ @!P2 LDG.E R19, [R4.64+-0x8] ; /* 0xfffff8080413a981 */
/* 0x000ee2000c1e1900 */
/*0420*/ @!P1 FFMA R0, R17, R16, R0 ; /* 0x0000001011009223 */
/* 0x004fe20000000000 */
/*0430*/ ISETP.LT.OR P1, PT, R18, RZ, P6 ; /* 0x000000ff1200720c */
/* 0x000fe40003721670 */
/*0440*/ @!P0 LDG.E R17, [R4.64+-0x4] ; /* 0xfffffc0804118981 */
/* 0x000ea4000c1e1900 */
/*0450*/ ISETP.GE.OR P1, PT, R23, c[0x0][0x178], P1 ; /* 0x00005e0017007a0c */
/* 0x000fe40000f26670 */
/*0460*/ @!P0 LDG.E R16, [R2.64+0x4] ; /* 0x0000040802108981 */
/* 0x000ea8000c1e1900 */
/*0470*/ @!P2 LDG.E R18, [R2.64+0x8] ; /* 0x000008080212a981 */
/* 0x000eee000c1e1900 */
/*0480*/ @!P1 LDG.E R20, [R2.64+0xc] ; /* 0x00000c0802149981 */
/* 0x000f28000c1e1900 */
/*0490*/ @!P1 LDG.E R21, [R4.64+-0xc] ; /* 0xfffff40804159981 */
/* 0x000f22000c1e1900 */
/*04a0*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fc40007ffe0ff */
/*04b0*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ @!P0 FFMA R0, R17, R16, R0 ; /* 0x0000001011008223 */
/* 0x004fe20000000000 */
/*04d0*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc60003f05270 */
/*04e0*/ @!P2 FFMA R0, R19, R18, R0 ; /* 0x000000121300a223 */
/* 0x008fc80000000000 */
/*04f0*/ @!P1 FFMA R0, R21, R20, R0 ; /* 0x0000001415009223 */
/* 0x010fcc0000000000 */
/*0500*/ @P0 BRA 0x290 ; /* 0xfffffd8000000947 */
/* 0x000fea000383ffff */
/*0510*/ @!P4 BRA 0x7c0 ; /* 0x000002a00000c947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R3, R10, R7, -R14.reuse ; /* 0x000000070a037210 */
/* 0x100fe20007ffe80e */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0540*/ ISETP.GE.AND P0, PT, R12.reuse, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x040fe20003f06270 */
/*0550*/ BSSY B0, 0x630 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0560*/ LOP3.LUT R2, R3, R12, RZ, 0xfc, !PT ; /* 0x0000000c03027212 */
/* 0x000fe200078efcff */
/*0570*/ IMAD R4, R12, c[0x0][0x178], R3 ; /* 0x00005e000c047a24 */
/* 0x000fe200078e0203 */
/*0580*/ ISETP.NE.AND P2, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe40003f45270 */
/*0590*/ ISETP.LT.OR P1, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe20000721670 */
/*05a0*/ IMAD R2, R15, c[0x0][0x180], R14 ; /* 0x000060000f027a24 */
/* 0x000fc600078e020e */
/*05b0*/ ISETP.GE.OR P1, PT, R3, c[0x0][0x178], P1 ; /* 0x00005e0003007a0c */
/* 0x000fe20000f26670 */
/*05c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0205 */
/*05d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fd000078e0205 */
/*05e0*/ @P1 BRA 0x620 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R13, [R2.64] ; /* 0x00000008020d7981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R15, [R4.64] ; /* 0x00000008040f7981 */
/* 0x000ea4000c1e1900 */
/*0610*/ FFMA R0, R13, R15, R0 ; /* 0x0000000f0d007223 */
/* 0x004fe40000000000 */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ @!P2 BRA 0x7c0 ; /* 0x000001800000a947 */
/* 0x000fea0003800000 */
/*0640*/ IADD3 R13, R7, -0x1, -R14 ; /* 0xffffffff070d7810 */
/* 0x000fe20007ffe80e */
/*0650*/ BSSY B0, 0x700 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0660*/ ISETP.NE.AND P2, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc60003f45270 */
/*0670*/ IMAD.IADD R13, R13, 0x1, R10 ; /* 0x000000010d0d7824 */
/* 0x000fca00078e020a */
/*0680*/ LOP3.LUT R15, R13, R12, RZ, 0xfc, !PT ; /* 0x0000000c0d0f7212 */
/* 0x000fc800078efcff */
/*0690*/ ISETP.LT.OR P1, PT, R15, RZ, P0 ; /* 0x000000ff0f00720c */
/* 0x000fc80000721670 */
/*06a0*/ ISETP.GE.OR P1, PT, R13, c[0x0][0x178], P1 ; /* 0x00005e000d007a0c */
/* 0x000fda0000f26670 */
/*06b0*/ @P1 BRA 0x6f0 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E R13, [R4.64+-0x4] ; /* 0xfffffc08040d7981 */
/* 0x000ea8000c1e1900 */
/*06d0*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000408020f7981 */
/* 0x000ea4000c1e1900 */
/*06e0*/ FFMA R0, R13, R15, R0 ; /* 0x0000000f0d007223 */
/* 0x004fe40000000000 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ @!P2 BRA 0x7c0 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*0710*/ IADD3 R13, R7, -0x2, -R14 ; /* 0xfffffffe070d7810 */
/* 0x000fe20007ffe80e */
/*0720*/ BSSY B0, 0x7c0 ; /* 0x0000009000007945 */
/* 0x000fe80003800000 */
/*0730*/ IMAD.IADD R13, R13, 0x1, R10 ; /* 0x000000010d0d7824 */
/* 0x000fca00078e020a */
/*0740*/ LOP3.LUT R12, R13, R12, RZ, 0xfc, !PT ; /* 0x0000000c0d0c7212 */
/* 0x000fc800078efcff */
/*0750*/ ISETP.LT.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x000fc80000701670 */
/*0760*/ ISETP.GE.OR P0, PT, R13, c[0x0][0x178], P0 ; /* 0x00005e000d007a0c */
/* 0x000fda0000706670 */
/*0770*/ @P0 BRA 0x7b0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0780*/ LDG.E R5, [R4.64+-0x8] ; /* 0xfffff80804057981 */
/* 0x000ea8000c1e1900 */
/*0790*/ LDG.E R2, [R2.64+0x8] ; /* 0x0000080802027981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ FFMA R0, R5, R2, R0 ; /* 0x0000000205007223 */
/* 0x004fe40000000000 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ @!P5 BRA 0x1f0 ; /* 0xfffffa200000d947 */
/* 0x000fea000383ffff */
/*07d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*07e0*/ IMAD R2, R6, c[0x0][0x178], R7 ; /* 0x00005e0006027a24 */
/* 0x000fc800078e0207 */
/*07f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0800*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101908 */
/*0810*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0820*/ BRA 0x820; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void convn_same_kernel(float *output, float *data, float *kernel, const int H, const int W, const int kH, const int kW) {
// Matrix index
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= H || y >= W)
return;
const int i0 = kW / 2, j0 = kH / 2;
float sum = 0;
for (int i = 0; i < kW; ++i) {
for(int j = 0; j < kH; ++j) {
int ii = y - i + i0;
int jj = x - j + j0;
if ( ii < 0 || ii >= W || jj < 0 || jj >= H )
continue;
sum += kernel[ i * kH + j ] * data[ ii * H + jj ];
}
}
output[y * H + x] = sum;
} | .file "tmpxft_000b078a_00000000-6_convn_same_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii
.type _Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii, @function
_Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17convn_same_kernelPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii, .-_Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii
.globl _Z17convn_same_kernelPfS_S_iiii
.type _Z17convn_same_kernelPfS_S_iiii, @function
_Z17convn_same_kernelPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17convn_same_kernelPfS_S_iiii, .-_Z17convn_same_kernelPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17convn_same_kernelPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17convn_same_kernelPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void convn_same_kernel(float *output, float *data, float *kernel, const int H, const int W, const int kH, const int kW) {
// Matrix index
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= H || y >= W)
return;
const int i0 = kW / 2, j0 = kH / 2;
float sum = 0;
for (int i = 0; i < kW; ++i) {
for(int j = 0; j < kH; ++j) {
int ii = y - i + i0;
int jj = x - j + j0;
if ( ii < 0 || ii >= W || jj < 0 || jj >= H )
continue;
sum += kernel[ i * kH + j ] * data[ ii * H + jj ];
}
}
output[y * H + x] = sum;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convn_same_kernel(float *output, float *data, float *kernel, const int H, const int W, const int kH, const int kW) {
// Matrix index
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= H || y >= W)
return;
const int i0 = kW / 2, j0 = kH / 2;
float sum = 0;
for (int i = 0; i < kW; ++i) {
for(int j = 0; j < kH; ++j) {
int ii = y - i + i0;
int jj = x - j + j0;
if ( ii < 0 || ii >= W || jj < 0 || jj >= H )
continue;
sum += kernel[ i * kH + j ] * data[ ii * H + jj ];
}
}
output[y * H + x] = sum;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convn_same_kernel(float *output, float *data, float *kernel, const int H, const int W, const int kH, const int kW) {
// Matrix index
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= H || y >= W)
return;
const int i0 = kW / 2, j0 = kH / 2;
float sum = 0;
for (int i = 0; i < kW; ++i) {
for(int j = 0; j < kH; ++j) {
int ii = y - i + i0;
int jj = x - j + j0;
if ( ii < 0 || ii >= W || jj < 0 || jj >= H )
continue;
sum += kernel[ i * kH + j ] * data[ ii * H + jj ];
}
}
output[y * H + x] = sum;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17convn_same_kernelPfS_S_iiii
.globl _Z17convn_same_kernelPfS_S_iiii
.p2align 8
.type _Z17convn_same_kernelPfS_S_iiii,@function
_Z17convn_same_kernelPfS_S_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[6:7], s[0:1], 0x18
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s3, s14, s3
s_mul_i32 s4, s15, s2
v_add_nc_u32_e32 v0, s3, v4
v_add_nc_u32_e32 v1, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_13
s_load_b32 s5, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_11
s_clause 0x1
s_load_b32 s14, s[0:1], 0x20
s_load_b128 s[8:11], s[0:1], 0x8
s_lshr_b32 s2, s5, 31
s_mov_b32 s13, 0
s_add_i32 s2, s5, s2
s_mov_b32 s17, 0
s_ashr_i32 s15, s2, 1
s_mov_b32 s18, 0
v_add3_u32 v3, s4, s15, v2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v3, s6, v3
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s14, 31
s_add_i32 s2, s14, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s2, s2, 1
s_cmp_gt_i32 s14, 0
v_add3_u32 v4, s3, s2, v4
s_cselect_b32 s16, -1, 0
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_subrev_nc_u32_e32 v3, s6, v3
s_add_i32 s18, s18, 1
s_add_i32 s17, s17, s14
s_cmp_eq_u32 s18, s5
s_cbranch_scc1 .LBB0_12
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_3
v_subrev_nc_u32_e32 v5, s18, v1
s_mov_b32 s19, s14
s_mov_b32 s12, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, s15, v5
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s2, s7, v5
v_mov_b32_e32 v5, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s20
v_add_nc_u32_e32 v5, -1, v5
s_add_i32 s19, s19, -1
s_add_i32 s12, s12, 1
s_cmp_eq_u32 s19, 0
s_cbranch_scc1 .LBB0_3
.LBB0_8:
s_and_saveexec_b32 s20, vcc_lo
s_cbranch_execz .LBB0_7
v_cmp_lt_i32_e64 s3, -1, v5
v_cmp_gt_i32_e64 s4, s6, v5
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v6, v3, v5
s_lshl_b64 s[22:23], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s22, s10, s22
s_addc_u32 s23, s11, s23
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, s3, s8, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s3, s9, v7, s3
s_load_b32 s3, s[22:23], 0x0
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v2, s3, v6
s_branch .LBB0_6
.LBB0_11:
v_mov_b32_e32 v2, 0
.LBB0_12:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v1, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17convn_same_kernelPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17convn_same_kernelPfS_S_iiii, .Lfunc_end0-_Z17convn_same_kernelPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17convn_same_kernelPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z17convn_same_kernelPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convn_same_kernel(float *output, float *data, float *kernel, const int H, const int W, const int kH, const int kW) {
// Matrix index
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= H || y >= W)
return;
const int i0 = kW / 2, j0 = kH / 2;
float sum = 0;
for (int i = 0; i < kW; ++i) {
for(int j = 0; j < kH; ++j) {
int ii = y - i + i0;
int jj = x - j + j0;
if ( ii < 0 || ii >= W || jj < 0 || jj >= H )
continue;
sum += kernel[ i * kH + j ] * data[ ii * H + jj ];
}
}
output[y * H + x] = sum;
} | .text
.file "convn_same_kernel.hip"
.globl _Z32__device_stub__convn_same_kernelPfS_S_iiii # -- Begin function _Z32__device_stub__convn_same_kernelPfS_S_iiii
.p2align 4, 0x90
.type _Z32__device_stub__convn_same_kernelPfS_S_iiii,@function
_Z32__device_stub__convn_same_kernelPfS_S_iiii: # @_Z32__device_stub__convn_same_kernelPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17convn_same_kernelPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__convn_same_kernelPfS_S_iiii, .Lfunc_end0-_Z32__device_stub__convn_same_kernelPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17convn_same_kernelPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17convn_same_kernelPfS_S_iiii,@object # @_Z17convn_same_kernelPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z17convn_same_kernelPfS_S_iiii
.p2align 3, 0x0
_Z17convn_same_kernelPfS_S_iiii:
.quad _Z32__device_stub__convn_same_kernelPfS_S_iiii
.size _Z17convn_same_kernelPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17convn_same_kernelPfS_S_iiii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__convn_same_kernelPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17convn_same_kernelPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17convn_same_kernelPfS_S_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x4], R3 ; /* 0x0000010006067a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R6, c[0x0][0x17c], PT ; /* 0x00005f0006007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R0 ; /* 0x0000000007077a24 */
/* 0x002fca00078e0200 */
/*0080*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x178], P0 ; /* 0x00005e0007007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fc80000000a00 */
/*00c0*/ ISETP.LE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fc80003f03270 */
/*00d0*/ ISETP.GT.OR P0, PT, R0, c[0x0][0x184], !P0 ; /* 0x0000610000007a0c */
/* 0x000fe20004704670 */
/*00e0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fd800078e00ff */
/*00f0*/ @P0 BRA 0x7d0 ; /* 0x000006d000000947 */
/* 0x000fea0003800000 */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0110*/ UMOV UR6, 0x2 ; /* 0x0000000200067882 */
/* 0x000fe20000000000 */
/*0120*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff087624 */
/* 0x000fe200078e00ff */
/*0130*/ ULDC UR5, c[0x0][0x184] ; /* 0x0000610000057ab9 */
/* 0x000fe20000000800 */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0150*/ IADD3 R0, -R0, c[0x0][0x180], RZ ; /* 0x0000600000007a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0170*/ LEA.HI R10, R8.reuse, c[0x0][0x180], RZ, 0x1 ; /* 0x00006000080a7a11 */
/* 0x040fe200078f08ff */
/*0180*/ UIMAD.WIDE.U32 UR4, UR6, UR5, UR4 ; /* 0x00000005060472a5 */
/* 0x000fe2000f8e0004 */
/*0190*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe400078ec0ff */
/*01a0*/ ISETP.GE.U32.AND P3, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f66070 */
/*01b0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fe200078e00ff */
/*01c0*/ SHF.R.S32.HI R10, RZ, 0x1, R10 ; /* 0x00000001ff0a7819 */
/* 0x000fe2000001140a */
/*01d0*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe20008011405 */
/*01e0*/ IADD3 R11, -R8, c[0x0][0x180], RZ ; /* 0x00006000080b7a10 */
/* 0x000fc80007ffe1ff */
/*01f0*/ IMAD.MOV.U32 R15, RZ, RZ, R9.reuse ; /* 0x000000ffff0f7224 */
/* 0x100fe200078e0009 */
/*0200*/ IADD3 R12, R6, UR5, -R9 ; /* 0x00000005060c7c10 */
/* 0x000fe2000fffe809 */
/*0210*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e00ff */
/*0220*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fc40007ffe0ff */
/*0230*/ ISETP.NE.AND P4, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f85270 */
/*0240*/ ISETP.GE.AND P5, PT, R9, c[0x0][0x184], PT ; /* 0x0000610009007a0c */
/* 0x000fe20003fa6270 */
/*0250*/ @!P3 BRA 0x510 ; /* 0x000002b00000b947 */
/* 0x000ff40003800000 */
/*0260*/ ISETP.GE.AND P6, PT, R12, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x000fe20003fc6270 */
/*0270*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e00ff */
/*0280*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fc600078e000b */
/*0290*/ IADD3 R3, R10, R7, -R14 ; /* 0x000000070a037210 */
/* 0x000fe20007ffe80e */
/*02a0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc600078e00ff */
/*02b0*/ LOP3.LUT R2, R3, R12, RZ, 0xfc, !PT ; /* 0x0000000c03027212 */
/* 0x000fe200078efcff */
/*02c0*/ IMAD R4, R12, c[0x0][0x178], R3 ; /* 0x00005e000c047a24 */
/* 0x000fc600078e0203 */
/*02d0*/ ISETP.LT.OR P1, PT, R2, RZ, P6 ; /* 0x000000ff0200720c */
/* 0x000fe20003721670 */
/*02e0*/ IMAD R2, R15, c[0x0][0x180], R14 ; /* 0x000060000f027a24 */
/* 0x000fc600078e020e */
/*02f0*/ ISETP.GE.OR P1, PT, R3, c[0x0][0x178], P1 ; /* 0x00005e0003007a0c */
/* 0x000fe20000f26670 */
/*0300*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0205 */
/*0310*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fd000078e0205 */
/*0320*/ @!P1 LDG.E R17, [R2.64] ; /* 0x0000000802119981 */
/* 0x000ea8000c1e1900 */
/*0330*/ @!P1 LDG.E R16, [R4.64] ; /* 0x0000000804109981 */
/* 0x000ea2000c1e1900 */
/*0340*/ IADD3 R19, R7.reuse, -0x1, -R14.reuse ; /* 0xffffffff07137810 */
/* 0x140fe40007ffe80e */
/*0350*/ IADD3 R21, R7.reuse, -0x2, -R14.reuse ; /* 0xfffffffe07157810 */
/* 0x140fe40007ffe80e */
/*0360*/ IADD3 R23, R7, -0x3, -R14 ; /* 0xfffffffd07177810 */
/* 0x000fe20007ffe80e */
/*0370*/ IMAD.IADD R19, R19, 0x1, R10 ; /* 0x0000000113137824 */
/* 0x000fc400078e020a */
/*0380*/ IMAD.IADD R21, R21, 0x1, R10.reuse ; /* 0x0000000115157824 */
/* 0x100fe400078e020a */
/*0390*/ IMAD.IADD R23, R23, 0x1, R10 ; /* 0x0000000117177824 */
/* 0x000fe200078e020a */
/*03a0*/ LOP3.LUT R18, R19, R12.reuse, RZ, 0xfc, !PT ; /* 0x0000000c13127212 */
/* 0x080fe400078efcff */
/*03b0*/ LOP3.LUT R20, R21, R12, RZ, 0xfc, !PT ; /* 0x0000000c15147212 */
/* 0x000fe400078efcff */
/*03c0*/ ISETP.LT.OR P0, PT, R18, RZ, P6 ; /* 0x000000ff1200720c */
/* 0x000fe40003701670 */
/*03d0*/ ISETP.LT.OR P2, PT, R20, RZ, P6 ; /* 0x000000ff1400720c */
/* 0x000fe40003741670 */
/*03e0*/ ISETP.GE.OR P0, PT, R19, c[0x0][0x178], P0 ; /* 0x00005e0013007a0c */
/* 0x000fc40000706670 */
/*03f0*/ LOP3.LUT R18, R23, R12, RZ, 0xfc, !PT ; /* 0x0000000c17127212 */
/* 0x000fe400078efcff */
/*0400*/ ISETP.GE.OR P2, PT, R21, c[0x0][0x178], P2 ; /* 0x00005e0015007a0c */
/* 0x000fda0001746670 */
/*0410*/ @!P2 LDG.E R19, [R4.64+-0x8] ; /* 0xfffff8080413a981 */
/* 0x000ee2000c1e1900 */
/*0420*/ @!P1 FFMA R0, R17, R16, R0 ; /* 0x0000001011009223 */
/* 0x004fe20000000000 */
/*0430*/ ISETP.LT.OR P1, PT, R18, RZ, P6 ; /* 0x000000ff1200720c */
/* 0x000fe40003721670 */
/*0440*/ @!P0 LDG.E R17, [R4.64+-0x4] ; /* 0xfffffc0804118981 */
/* 0x000ea4000c1e1900 */
/*0450*/ ISETP.GE.OR P1, PT, R23, c[0x0][0x178], P1 ; /* 0x00005e0017007a0c */
/* 0x000fe40000f26670 */
/*0460*/ @!P0 LDG.E R16, [R2.64+0x4] ; /* 0x0000040802108981 */
/* 0x000ea8000c1e1900 */
/*0470*/ @!P2 LDG.E R18, [R2.64+0x8] ; /* 0x000008080212a981 */
/* 0x000eee000c1e1900 */
/*0480*/ @!P1 LDG.E R20, [R2.64+0xc] ; /* 0x00000c0802149981 */
/* 0x000f28000c1e1900 */
/*0490*/ @!P1 LDG.E R21, [R4.64+-0xc] ; /* 0xfffff40804159981 */
/* 0x000f22000c1e1900 */
/*04a0*/ IADD3 R13, R13, -0x4, RZ ; /* 0xfffffffc0d0d7810 */
/* 0x000fc40007ffe0ff */
/*04b0*/ IADD3 R14, R14, 0x4, RZ ; /* 0x000000040e0e7810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ @!P0 FFMA R0, R17, R16, R0 ; /* 0x0000001011008223 */
/* 0x004fe20000000000 */
/*04d0*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fc60003f05270 */
/*04e0*/ @!P2 FFMA R0, R19, R18, R0 ; /* 0x000000121300a223 */
/* 0x008fc80000000000 */
/*04f0*/ @!P1 FFMA R0, R21, R20, R0 ; /* 0x0000001415009223 */
/* 0x010fcc0000000000 */
/*0500*/ @P0 BRA 0x290 ; /* 0xfffffd8000000947 */
/* 0x000fea000383ffff */
/*0510*/ @!P4 BRA 0x7c0 ; /* 0x000002a00000c947 */
/* 0x000fea0003800000 */
/*0520*/ IADD3 R3, R10, R7, -R14.reuse ; /* 0x000000070a037210 */
/* 0x100fe20007ffe80e */
/*0530*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0540*/ ISETP.GE.AND P0, PT, R12.reuse, c[0x0][0x17c], PT ; /* 0x00005f000c007a0c */
/* 0x040fe20003f06270 */
/*0550*/ BSSY B0, 0x630 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0560*/ LOP3.LUT R2, R3, R12, RZ, 0xfc, !PT ; /* 0x0000000c03027212 */
/* 0x000fe200078efcff */
/*0570*/ IMAD R4, R12, c[0x0][0x178], R3 ; /* 0x00005e000c047a24 */
/* 0x000fe200078e0203 */
/*0580*/ ISETP.NE.AND P2, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe40003f45270 */
/*0590*/ ISETP.LT.OR P1, PT, R2, RZ, P0 ; /* 0x000000ff0200720c */
/* 0x000fe20000721670 */
/*05a0*/ IMAD R2, R15, c[0x0][0x180], R14 ; /* 0x000060000f027a24 */
/* 0x000fc600078e020e */
/*05b0*/ ISETP.GE.OR P1, PT, R3, c[0x0][0x178], P1 ; /* 0x00005e0003007a0c */
/* 0x000fe20000f26670 */
/*05c0*/ IMAD.WIDE R2, R2, R5, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fc800078e0205 */
/*05d0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fd000078e0205 */
/*05e0*/ @P1 BRA 0x620 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*05f0*/ LDG.E R13, [R2.64] ; /* 0x00000008020d7981 */
/* 0x000ea8000c1e1900 */
/*0600*/ LDG.E R15, [R4.64] ; /* 0x00000008040f7981 */
/* 0x000ea4000c1e1900 */
/*0610*/ FFMA R0, R13, R15, R0 ; /* 0x0000000f0d007223 */
/* 0x004fe40000000000 */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ @!P2 BRA 0x7c0 ; /* 0x000001800000a947 */
/* 0x000fea0003800000 */
/*0640*/ IADD3 R13, R7, -0x1, -R14 ; /* 0xffffffff070d7810 */
/* 0x000fe20007ffe80e */
/*0650*/ BSSY B0, 0x700 ; /* 0x000000a000007945 */
/* 0x000fe20003800000 */
/*0660*/ ISETP.NE.AND P2, PT, R8, 0x2, PT ; /* 0x000000020800780c */
/* 0x000fc60003f45270 */
/*0670*/ IMAD.IADD R13, R13, 0x1, R10 ; /* 0x000000010d0d7824 */
/* 0x000fca00078e020a */
/*0680*/ LOP3.LUT R15, R13, R12, RZ, 0xfc, !PT ; /* 0x0000000c0d0f7212 */
/* 0x000fc800078efcff */
/*0690*/ ISETP.LT.OR P1, PT, R15, RZ, P0 ; /* 0x000000ff0f00720c */
/* 0x000fc80000721670 */
/*06a0*/ ISETP.GE.OR P1, PT, R13, c[0x0][0x178], P1 ; /* 0x00005e000d007a0c */
/* 0x000fda0000f26670 */
/*06b0*/ @P1 BRA 0x6f0 ; /* 0x0000003000001947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E R13, [R4.64+-0x4] ; /* 0xfffffc08040d7981 */
/* 0x000ea8000c1e1900 */
/*06d0*/ LDG.E R15, [R2.64+0x4] ; /* 0x00000408020f7981 */
/* 0x000ea4000c1e1900 */
/*06e0*/ FFMA R0, R13, R15, R0 ; /* 0x0000000f0d007223 */
/* 0x004fe40000000000 */
/*06f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0700*/ @!P2 BRA 0x7c0 ; /* 0x000000b00000a947 */
/* 0x000fea0003800000 */
/*0710*/ IADD3 R13, R7, -0x2, -R14 ; /* 0xfffffffe070d7810 */
/* 0x000fe20007ffe80e */
/*0720*/ BSSY B0, 0x7c0 ; /* 0x0000009000007945 */
/* 0x000fe80003800000 */
/*0730*/ IMAD.IADD R13, R13, 0x1, R10 ; /* 0x000000010d0d7824 */
/* 0x000fca00078e020a */
/*0740*/ LOP3.LUT R12, R13, R12, RZ, 0xfc, !PT ; /* 0x0000000c0d0c7212 */
/* 0x000fc800078efcff */
/*0750*/ ISETP.LT.OR P0, PT, R12, RZ, P0 ; /* 0x000000ff0c00720c */
/* 0x000fc80000701670 */
/*0760*/ ISETP.GE.OR P0, PT, R13, c[0x0][0x178], P0 ; /* 0x00005e000d007a0c */
/* 0x000fda0000706670 */
/*0770*/ @P0 BRA 0x7b0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0780*/ LDG.E R5, [R4.64+-0x8] ; /* 0xfffff80804057981 */
/* 0x000ea8000c1e1900 */
/*0790*/ LDG.E R2, [R2.64+0x8] ; /* 0x0000080802027981 */
/* 0x000ea4000c1e1900 */
/*07a0*/ FFMA R0, R5, R2, R0 ; /* 0x0000000205007223 */
/* 0x004fe40000000000 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ @!P5 BRA 0x1f0 ; /* 0xfffffa200000d947 */
/* 0x000fea000383ffff */
/*07d0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*07e0*/ IMAD R2, R6, c[0x0][0x178], R7 ; /* 0x00005e0006027a24 */
/* 0x000fc800078e0207 */
/*07f0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0800*/ STG.E [R2.64], R0 ; /* 0x0000000002007986 */
/* 0x000fe2000c101908 */
/*0810*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0820*/ BRA 0x820; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17convn_same_kernelPfS_S_iiii
.globl _Z17convn_same_kernelPfS_S_iiii
.p2align 8
.type _Z17convn_same_kernelPfS_S_iiii,@function
_Z17convn_same_kernelPfS_S_iiii:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[6:7], s[0:1], 0x18
v_and_b32_e32 v4, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_mul_i32 s3, s14, s3
s_mul_i32 s4, s15, s2
v_add_nc_u32_e32 v0, s3, v4
v_add_nc_u32_e32 v1, s4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s6, v0
v_cmp_gt_i32_e64 s2, s7, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_13
s_load_b32 s5, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s5, 1
s_cbranch_scc1 .LBB0_11
s_clause 0x1
s_load_b32 s14, s[0:1], 0x20
s_load_b128 s[8:11], s[0:1], 0x8
s_lshr_b32 s2, s5, 31
s_mov_b32 s13, 0
s_add_i32 s2, s5, s2
s_mov_b32 s17, 0
s_ashr_i32 s15, s2, 1
s_mov_b32 s18, 0
v_add3_u32 v3, s4, s15, v2
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v3, s6, v3
s_waitcnt lgkmcnt(0)
s_lshr_b32 s2, s14, 31
s_add_i32 s2, s14, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_ashr_i32 s2, s2, 1
s_cmp_gt_i32 s14, 0
v_add3_u32 v4, s3, s2, v4
s_cselect_b32 s16, -1, 0
s_branch .LBB0_4
.LBB0_3:
s_set_inst_prefetch_distance 0x2
v_subrev_nc_u32_e32 v3, s6, v3
s_add_i32 s18, s18, 1
s_add_i32 s17, s17, s14
s_cmp_eq_u32 s18, s5
s_cbranch_scc1 .LBB0_12
.LBB0_4:
s_and_not1_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_3
v_subrev_nc_u32_e32 v5, s18, v1
s_mov_b32 s19, s14
s_mov_b32 s12, s17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, s15, v5
v_cmp_lt_i32_e32 vcc_lo, -1, v5
v_cmp_gt_i32_e64 s2, s7, v5
v_mov_b32_e32 v5, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_8
.p2align 6
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
.LBB0_7:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s20
v_add_nc_u32_e32 v5, -1, v5
s_add_i32 s19, s19, -1
s_add_i32 s12, s12, 1
s_cmp_eq_u32 s19, 0
s_cbranch_scc1 .LBB0_3
.LBB0_8:
s_and_saveexec_b32 s20, vcc_lo
s_cbranch_execz .LBB0_7
v_cmp_lt_i32_e64 s3, -1, v5
v_cmp_gt_i32_e64 s4, s6, v5
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s3, s3, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s4, s3
s_cbranch_execz .LBB0_6
v_add_nc_u32_e32 v6, v3, v5
s_lshl_b64 s[22:23], s[12:13], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s22, s10, s22
s_addc_u32 s23, s11, s23
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[6:7]
v_add_co_u32 v6, s3, s8, v6
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v7, s3, s9, v7, s3
s_load_b32 s3, s[22:23], 0x0
global_load_b32 v6, v[6:7], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_fmac_f32_e32 v2, s3, v6
s_branch .LBB0_6
.LBB0_11:
v_mov_b32_e32 v2, 0
.LBB0_12:
s_load_b64 s[0:1], s[0:1], 0x0
v_mad_u64_u32 v[3:4], null, v1, s6, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_13:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17convn_same_kernelPfS_S_iiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17convn_same_kernelPfS_S_iiii, .Lfunc_end0-_Z17convn_same_kernelPfS_S_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17convn_same_kernelPfS_S_iiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z17convn_same_kernelPfS_S_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000b078a_00000000-6_convn_same_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii
.type _Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii, @function
_Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17convn_same_kernelPfS_S_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii, .-_Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii
.globl _Z17convn_same_kernelPfS_S_iiii
.type _Z17convn_same_kernelPfS_S_iiii, @function
_Z17convn_same_kernelPfS_S_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z17convn_same_kernelPfS_S_iiiiPfS_S_iiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17convn_same_kernelPfS_S_iiii, .-_Z17convn_same_kernelPfS_S_iiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17convn_same_kernelPfS_S_iiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17convn_same_kernelPfS_S_iiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convn_same_kernel.hip"
.globl _Z32__device_stub__convn_same_kernelPfS_S_iiii # -- Begin function _Z32__device_stub__convn_same_kernelPfS_S_iiii
.p2align 4, 0x90
.type _Z32__device_stub__convn_same_kernelPfS_S_iiii,@function
_Z32__device_stub__convn_same_kernelPfS_S_iiii: # @_Z32__device_stub__convn_same_kernelPfS_S_iiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17convn_same_kernelPfS_S_iiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z32__device_stub__convn_same_kernelPfS_S_iiii, .Lfunc_end0-_Z32__device_stub__convn_same_kernelPfS_S_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17convn_same_kernelPfS_S_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17convn_same_kernelPfS_S_iiii,@object # @_Z17convn_same_kernelPfS_S_iiii
.section .rodata,"a",@progbits
.globl _Z17convn_same_kernelPfS_S_iiii
.p2align 3, 0x0
_Z17convn_same_kernelPfS_S_iiii:
.quad _Z32__device_stub__convn_same_kernelPfS_S_iiii
.size _Z17convn_same_kernelPfS_S_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17convn_same_kernelPfS_S_iiii"
.size .L__unnamed_1, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__convn_same_kernelPfS_S_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17convn_same_kernelPfS_S_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
// CUDA kernel. Each thread takes care of one element of c
__device__ int isPrime(bignum x)
{
bignum i;
bignum lim = (bignum)sqrt((float)x) + 1;
if (x % 2 == 0)
{
return 0;
}
for (i = 3; i < lim; i += 2)
{
if (x % i == 0)
return 0;
}
return 1;
}
__global__ void checkPrimes(int *results, int arr_size)
{
// Get our global thread ID
bignum index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < arr_size)
{
bignum number = 2 * index + 1;
results[index] = isPrime(number);
}
}
int main(int argc, char *argv[])
{
if (argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum n = (bignum)atoi(argv[1]);
// Host input vectors
int *h_results;
// Device input vectors
int *d_results;
size_t arr_size = (int)ceil((float) ((n - 1.0) / 2.0));
printf("arr_size: %ld\n", arr_size);
// Size, in bytes, of each vector
size_t results_num_bytes = arr_size * sizeof(int);
// Allocate memory for each vector on host
h_results = (int *)malloc(results_num_bytes);
// Allocate memory for each vector on GPU
cudaMalloc(&d_results, results_num_bytes);
bignum i;
// Initialize vectors on host
for (i = 0; i < arr_size; i++)
{
h_results[i] = 0;
}
// Copy host vectors to device
cudaMemcpy(d_results, h_results, results_num_bytes, cudaMemcpyHostToDevice);
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid
gridSize = (int)ceil((float) ((n + 1.0) / 2.0 / blockSize));
// gridSize = (int)ceil((float)n / blockSize);
printf("gridSize: %d\n", gridSize);
printf("gridSize * blockSize: %d\n", gridSize*blockSize);
// Execute the kernel
checkPrimes<<<gridSize, blockSize>>>(d_results, arr_size);
// Copy array back to host
cudaMemcpy(h_results, d_results, results_num_bytes, cudaMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 without error
bignum sum = 0;
for (i = 0; i < arr_size; i++)
{
sum += h_results[i];
}
printf("final result: %lld\n", sum);
// Release device memory
cudaFree(d_results);
// Release host memory
free(h_results);
return 0;
} | code for sm_80
Function : _Z11checkPrimesPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011404 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda000bf06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x2, RZ ; /* 0x0000000200027824 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.U32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011600 */
/*00b0*/ BSSY B0, 0x1c0 ; /* 0x0000010000007945 */
/* 0x000fe60003800000 */
/*00c0*/ LOP3.LUT R2, R2, 0x1, RZ, 0xfc, !PT ; /* 0x0000000102027812 */
/* 0x000fc800078efcff */
/*00d0*/ I2F.U64 R4, R2 ; /* 0x0000000200047312 */
/* 0x000e240000301000 */
/*00e0*/ IADD3 R6, R4, -0xd000000, RZ ; /* 0xf300000004067810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ MUFU.RSQ R5, R4 ; /* 0x0000000400057308 */
/* 0x0000620000001400 */
/*0100*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0110*/ @!P0 BRA 0x170 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0120*/ BSSY B1, 0x160 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0130*/ MOV R10, 0x150 ; /* 0x00000150000a7802 */
/* 0x000fe40000000f00 */
/*0140*/ CALL.REL.NOINC 0x940 ; /* 0x000007f000007944 */
/* 0x000fea0003c00000 */
/*0150*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x1b0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0170*/ FMUL.FTZ R7, R4, R5 ; /* 0x0000000504077220 */
/* 0x003fe40000410000 */
/*0180*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0190*/ FFMA R4, -R7, R7, R4 ; /* 0x0000000707047223 */
/* 0x000fc80000000104 */
/*01a0*/ FFMA R6, R4, R5, R7 ; /* 0x0000000504067223 */
/* 0x000fe40000000007 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ F2I.U64.TRUNC R4, R6 ; /* 0x0000000600047311 */
/* 0x000e22000020d800 */
/*01d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01e0*/ BSSY B0, 0x4e0 ; /* 0x000002f000007945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R4, P0, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x001fc80007f1e0ff */
/*0210*/ IADD3.X R5, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff057210 */
/* 0x000fe400007fe4ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fc80003f06070 */
/*0230*/ ISETP.GE.U32.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0003f06100 */
/*0240*/ @!P0 BRA 0x4d0 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*0250*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fd200078e00ff */
/*0270*/ LOP3.LUT R6, R3, R8, RZ, 0xfc, !PT ; /* 0x0000000803067212 */
/* 0x000fe200078efcff */
/*0280*/ BSSY B1, 0x440 ; /* 0x000001b000017945 */
/* 0x000fe60003800000 */
/*0290*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05070 */
/*02a0*/ @!P0 BRA 0x300 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02b0*/ MOV R6, 0x2d0 ; /* 0x000002d000067802 */
/* 0x000fe40000000f00 */
/*02c0*/ CALL.REL.NOINC 0x520 ; /* 0x0000025000007944 */
/* 0x000fea0003c00000 */
/*02d0*/ ISETP.NE.U32.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f05070 */
/*02e0*/ ISETP.NE.AND.EX P0, PT, R12, RZ, PT, P0 ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05300 */
/*02f0*/ BRA 0x430 ; /* 0x0000013000007947 */
/* 0x000fee0003800000 */
/*0300*/ I2F.U32.RP R6, R7 ; /* 0x0000000700067306 */
/* 0x000e220000209000 */
/*0310*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fce0003f25070 */
/*0320*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0330*/ IADD3 R10, R6, 0xffffffe, RZ ; /* 0x0ffffffe060a7810 */
/* 0x001fcc0007ffe0ff */
/*0340*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000064000021f000 */
/*0350*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e00ff */
/*0360*/ IMAD.MOV R12, RZ, RZ, -R11 ; /* 0x000000ffff0c7224 */
/* 0x002fc800078e0a0b */
/*0370*/ IMAD R9, R12, R7, RZ ; /* 0x000000070c097224 */
/* 0x000fc800078e02ff */
/*0380*/ IMAD.HI.U32 R11, R11, R9, R10 ; /* 0x000000090b0b7227 */
/* 0x000fcc00078e000a */
/*0390*/ IMAD.HI.U32 R11, R11, R2, RZ ; /* 0x000000020b0b7227 */
/* 0x000fca00078e00ff */
/*03a0*/ IADD3 R11, -R11, RZ, RZ ; /* 0x000000ff0b0b7210 */
/* 0x000fca0007ffe1ff */
/*03b0*/ IMAD R12, R7, R11, R2 ; /* 0x0000000b070c7224 */
/* 0x000fca00078e0202 */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x000fda0003f06070 */
/*03d0*/ @P0 IMAD.IADD R12, R12, 0x1, -R7 ; /* 0x000000010c0c0824 */
/* 0x000fca00078e0a07 */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x000fda0003f06070 */
/*03f0*/ @P0 IMAD.IADD R12, R12, 0x1, -R7 ; /* 0x000000010c0c0824 */
/* 0x000fe200078e0a07 */
/*0400*/ @!P1 LOP3.LUT R12, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff0c9212 */
/* 0x000fc800078e33ff */
/*0410*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc80003f05070 */
/*0420*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd00003f05300 */
/*0430*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R6, P1, R7, 0x2, RZ ; /* 0x0000000207067810 */
/* 0x000fe40007f3e0ff */
/*0450*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fc60000000f00 */
/*0460*/ IMAD.X R8, RZ, RZ, R8, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0608 */
/*0470*/ @!P0 BRA 0x4d0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0480*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0006 */
/*0490*/ ISETP.GE.U32.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fc80003f06070 */
/*04a0*/ ISETP.GE.U32.AND.EX P0, PT, R8, R5, PT, P0 ; /* 0x000000050800720c */
/* 0x000fda0003f06100 */
/*04b0*/ @!P0 BRA 0x270 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*04c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fcc00000001ff */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*04f0*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*0500*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ IMAD.MOV.U32 R14, RZ, RZ, R7 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0007 */
/*0530*/ IMAD.MOV.U32 R15, RZ, RZ, R8 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0008 */
/*0540*/ I2F.U64.RP R9, R14 ; /* 0x0000000e00097312 */
/* 0x000e300000309000 */
/*0550*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x001e240000001000 */
/*0560*/ IADD3 R10, R9, 0x1ffffffe, RZ ; /* 0x1ffffffe090a7810 */
/* 0x001fcc0007ffe0ff */
/*0570*/ F2I.U64.TRUNC R10, R10 ; /* 0x0000000a000a7311 */
/* 0x000e24000020d800 */
/*0580*/ IMAD.WIDE.U32 R12, R10, R7, RZ ; /* 0x000000070a0c7225 */
/* 0x001fc800078e00ff */
/*0590*/ IMAD R13, R10, R8, R13 ; /* 0x000000080a0d7224 */
/* 0x000fe200078e020d */
/*05a0*/ IADD3 R17, P0, RZ, -R12, RZ ; /* 0x8000000cff117210 */
/* 0x000fc60007f1e0ff */
/*05b0*/ IMAD R13, R11, R7, R13 ; /* 0x000000070b0d7224 */
/* 0x000fe400078e020d */
/*05c0*/ IMAD.HI.U32 R12, R10, R17, RZ ; /* 0x000000110a0c7227 */
/* 0x000fc600078e00ff */
/*05d0*/ IADD3.X R19, RZ, ~R13, RZ, P0, !PT ; /* 0x8000000dff137210 */
/* 0x000fe200007fe4ff */
/*05e0*/ IMAD.MOV.U32 R13, RZ, RZ, R10 ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e000a */
/*05f0*/ IMAD.WIDE.U32 R12, P0, R10, R19, R12 ; /* 0x000000130a0c7225 */
/* 0x000fc8000780000c */
/*0600*/ IMAD R15, R11.reuse, R19, RZ ; /* 0x000000130b0f7224 */
/* 0x040fe400078e02ff */
/*0610*/ IMAD.HI.U32 R12, P1, R11, R17, R12 ; /* 0x000000110b0c7227 */
/* 0x000fc8000782000c */
/*0620*/ IMAD.HI.U32 R9, R11, R19, RZ ; /* 0x000000130b097227 */
/* 0x000fe200078e00ff */
/*0630*/ IADD3 R13, P2, R15, R12, RZ ; /* 0x0000000c0f0d7210 */
/* 0x000fc60007f5e0ff */
/*0640*/ IMAD.X R9, R9, 0x1, R11, P0 ; /* 0x0000000109097824 */
/* 0x000fe400000e060b */
/*0650*/ IMAD.WIDE.U32 R10, R13, R7, RZ ; /* 0x000000070d0a7225 */
/* 0x000fc600078e00ff */
/*0660*/ IADD3.X R9, RZ, RZ, R9, P2, P1 ; /* 0x000000ffff097210 */
/* 0x000fe200017e2409 */
/*0670*/ IMAD R12, R13, R8, R11 ; /* 0x000000080d0c7224 */
/* 0x000fe200078e020b */
/*0680*/ IADD3 R11, P0, RZ, -R10, RZ ; /* 0x8000000aff0b7210 */
/* 0x000fc60007f1e0ff */
/*0690*/ IMAD R10, R9, R7, R12 ; /* 0x00000007090a7224 */
/* 0x000fe400078e020c */
/*06a0*/ IMAD.HI.U32 R12, R13, R11, RZ ; /* 0x0000000b0d0c7227 */
/* 0x000fc600078e00ff */
/*06b0*/ IADD3.X R10, RZ, ~R10, RZ, P0, !PT ; /* 0x8000000aff0a7210 */
/* 0x000fca00007fe4ff */
/*06c0*/ IMAD.WIDE.U32 R12, P0, R13, R10, R12 ; /* 0x0000000a0d0c7225 */
/* 0x000fc8000780000c */
/*06d0*/ IMAD R14, R9.reuse, R10, RZ ; /* 0x0000000a090e7224 */
/* 0x040fe400078e02ff */
/*06e0*/ IMAD.HI.U32 R13, P1, R9, R11, R12 ; /* 0x0000000b090d7227 */
/* 0x000fc8000782000c */
/*06f0*/ IMAD.HI.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7227 */
/* 0x000fe200078e00ff */
/*0700*/ IADD3 R13, P2, R14, R13, RZ ; /* 0x0000000d0e0d7210 */
/* 0x000fc60007f5e0ff */
/*0710*/ IMAD.X R9, R10, 0x1, R9, P0 ; /* 0x000000010a097824 */
/* 0x000fe400000e0609 */
/*0720*/ IMAD.HI.U32 R10, R13, R2, RZ ; /* 0x000000020d0a7227 */
/* 0x000fc600078e00ff */
/*0730*/ IADD3.X R9, RZ, RZ, R9, P2, P1 ; /* 0x000000ffff097210 */
/* 0x000fe200017e2409 */
/*0740*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e00ff */
/*0750*/ IMAD.WIDE.U32 R10, R13, R3, R10 ; /* 0x000000030d0a7225 */
/* 0x000fc800078e000a */
/*0760*/ IMAD R13, R9.reuse, R3, RZ ; /* 0x00000003090d7224 */
/* 0x040fe400078e02ff */
/*0770*/ IMAD.HI.U32 R10, P0, R9, R2, R10 ; /* 0x00000002090a7227 */
/* 0x000fc8000780000a */
/*0780*/ IMAD.HI.U32 R9, R9, R3, RZ ; /* 0x0000000309097227 */
/* 0x000fe200078e00ff */
/*0790*/ IADD3 R13, P1, R13, R10, RZ ; /* 0x0000000a0d0d7210 */
/* 0x000fc80007f3e0ff */
/*07a0*/ IADD3.X R9, R9, RZ, RZ, P0, !PT ; /* 0x000000ff09097210 */
/* 0x000fe200007fe4ff */
/*07b0*/ IMAD.WIDE.U32 R10, R13, R7, RZ ; /* 0x000000070d0a7225 */
/* 0x000fc800078e00ff */
/*07c0*/ IMAD.X R12, RZ, RZ, R9, P1 ; /* 0x000000ffff0c7224 */
/* 0x000fe200008e0609 */
/*07d0*/ IADD3 R14, P1, -R10, R2, RZ ; /* 0x000000020a0e7210 */
/* 0x000fe20007f3e1ff */
/*07e0*/ IMAD R13, R13, R8, R11 ; /* 0x000000080d0d7224 */
/* 0x000fc600078e020b */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R14, R7.reuse, PT ; /* 0x000000070e00720c */
/* 0x080fe20003f06070 */
/*0800*/ IMAD R13, R12, R7, R13 ; /* 0x000000070c0d7224 */
/* 0x000fc800078e020d */
/*0810*/ IMAD.X R13, R3, 0x1, ~R13, P1 ; /* 0x00000001030d7824 */
/* 0x000fe200008e0e0d */
/*0820*/ IADD3 R10, P1, -R7, R14, RZ ; /* 0x0000000e070a7210 */
/* 0x000fc80007f3e1ff */
/*0830*/ ISETP.GE.U32.AND.EX P0, PT, R13, R8, PT, P0 ; /* 0x000000080d00720c */
/* 0x000fe40003f06100 */
/*0840*/ IADD3.X R11, ~R8, R13.reuse, RZ, P1, !PT ; /* 0x0000000d080b7210 */
/* 0x080fe40000ffe5ff */
/*0850*/ SEL R10, R10, R14, P0 ; /* 0x0000000e0a0a7207 */
/* 0x000fe40000000000 */
/*0860*/ SEL R11, R11, R13, P0 ; /* 0x0000000d0b0b7207 */
/* 0x000fe40000000000 */
/*0870*/ IADD3 R9, P2, -R7, R10, RZ ; /* 0x0000000a07097210 */
/* 0x000fe40007f5e1ff */
/*0880*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fc40003f06070 */
/*0890*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25070 */
/*08a0*/ IMAD.X R12, R11.reuse, 0x1, ~R8, P2 ; /* 0x000000010b0c7824 */
/* 0x040fe200010e0e08 */
/*08b0*/ ISETP.GE.U32.AND.EX P0, PT, R11, R8, PT, P0 ; /* 0x000000080b00720c */
/* 0x000fe40003f06100 */
/*08c0*/ ISETP.NE.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40003f25310 */
/*08d0*/ SEL R9, R9, R10, P0 ; /* 0x0000000a09097207 */
/* 0x000fe20000000000 */
/*08e0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*08f0*/ SEL R12, R12, R11, P0 ; /* 0x0000000b0c0c7207 */
/* 0x000fe40000000000 */
/*0900*/ MOV R11, 0x0 ; /* 0x00000000000b7802 */
/* 0x000fc40000000f00 */
/*0910*/ SEL R9, R9, 0xffffffff, P1 ; /* 0xffffffff09097807 */
/* 0x000fe40000800000 */
/*0920*/ SEL R12, R12, 0xffffffff, P1 ; /* 0xffffffff0c0c7807 */
/* 0x000fe20000800000 */
/*0930*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff6c00a007950 */
/* 0x000fec0003c3ffff */
/*0940*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c0ff */
/*0950*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff058224 */
/* 0x000fe200078e0004 */
/*0960*/ @!P0 BRA 0xa70 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0970*/ FSETP.GEU.FTZ.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fda0003f1e000 */
/*0980*/ @!P0 MOV R5, 0x7fffffff ; /* 0x7fffffff00058802 */
/* 0x000fe20000000f00 */
/*0990*/ @!P0 BRA 0xa70 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09a0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*09b0*/ @P0 FADD.FTZ R5, R4, 1 ; /* 0x3f80000004050421 */
/* 0x000fe20000010000 */
/*09c0*/ @P0 BRA 0xa70 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*09d0*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1d200 */
/*09e0*/ @P0 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004060823 */
/* 0x000fc800000000ff */
/*09f0*/ @P0 MUFU.RSQ R5, R6 ; /* 0x0000000600050308 */
/* 0x000e240000001400 */
/*0a00*/ @P0 FMUL.FTZ R7, R6, R5 ; /* 0x0000000506070220 */
/* 0x001fe40000410000 */
/*0a10*/ @P0 FMUL.FTZ R9, R5, 0.5 ; /* 0x3f00000005090820 */
/* 0x000fe40000410000 */
/*0a20*/ @P0 FADD.FTZ R8, -R7.reuse, -RZ ; /* 0x800000ff07080221 */
/* 0x040fe40000010100 */
/*0a30*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff058224 */
/* 0x000fe400078e0004 */
/*0a40*/ @P0 FFMA R8, R7, R8, R6 ; /* 0x0000000807080223 */
/* 0x000fc80000000006 */
/*0a50*/ @P0 FFMA R8, R8, R9, R7 ; /* 0x0000000908080223 */
/* 0x000fc80000000007 */
/*0a60*/ @P0 FMUL.FTZ R5, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008050820 */
/* 0x000fca0000410000 */
/*0a70*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x000fe20000000f00 */
/*0a80*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0a90*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fca00078e000a */
/*0aa0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff55004007950 */
/* 0x000fea0003c3ffff */
/*0ab0*/ BRA 0xab0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
// CUDA kernel. Each thread takes care of one element of c
__device__ int isPrime(bignum x)
{
bignum i;
bignum lim = (bignum)sqrt((float)x) + 1;
if (x % 2 == 0)
{
return 0;
}
for (i = 3; i < lim; i += 2)
{
if (x % i == 0)
return 0;
}
return 1;
}
__global__ void checkPrimes(int *results, int arr_size)
{
// Get our global thread ID
bignum index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < arr_size)
{
bignum number = 2 * index + 1;
results[index] = isPrime(number);
}
}
int main(int argc, char *argv[])
{
if (argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum n = (bignum)atoi(argv[1]);
// Host input vectors
int *h_results;
// Device input vectors
int *d_results;
size_t arr_size = (int)ceil((float) ((n - 1.0) / 2.0));
printf("arr_size: %ld\n", arr_size);
// Size, in bytes, of each vector
size_t results_num_bytes = arr_size * sizeof(int);
// Allocate memory for each vector on host
h_results = (int *)malloc(results_num_bytes);
// Allocate memory for each vector on GPU
cudaMalloc(&d_results, results_num_bytes);
bignum i;
// Initialize vectors on host
for (i = 0; i < arr_size; i++)
{
h_results[i] = 0;
}
// Copy host vectors to device
cudaMemcpy(d_results, h_results, results_num_bytes, cudaMemcpyHostToDevice);
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid
gridSize = (int)ceil((float) ((n + 1.0) / 2.0 / blockSize));
// gridSize = (int)ceil((float)n / blockSize);
printf("gridSize: %d\n", gridSize);
printf("gridSize * blockSize: %d\n", gridSize*blockSize);
// Execute the kernel
checkPrimes<<<gridSize, blockSize>>>(d_results, arr_size);
// Copy array back to host
cudaMemcpy(h_results, d_results, results_num_bytes, cudaMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 without error
bignum sum = 0;
for (i = 0; i < arr_size; i++)
{
sum += h_results[i];
}
printf("final result: %lld\n", sum);
// Release device memory
cudaFree(d_results);
// Release host memory
free(h_results);
return 0;
} | .file "tmpxft_001a6b18_00000000-6_lab1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7isPrimey
.type _Z7isPrimey, @function
_Z7isPrimey:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z7isPrimey, .-_Z7isPrimey
.globl _Z32__device_stub__Z11checkPrimesPiiPii
.type _Z32__device_stub__Z11checkPrimesPiiPii, @function
_Z32__device_stub__Z11checkPrimesPiiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11checkPrimesPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z11checkPrimesPiiPii, .-_Z32__device_stub__Z11checkPrimesPiiPii
.globl _Z11checkPrimesPii
.type _Z11checkPrimesPii, @function
_Z11checkPrimesPii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11checkPrimesPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11checkPrimesPii, .-_Z11checkPrimesPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: prime upbound\n"
.LC6:
.string "arr_size: %ld\n"
.LC8:
.string "gridSize: %d\n"
.LC9:
.string "gridSize * blockSize: %d\n"
.LC10:
.string "final result: %lld\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L28
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cltq
testq %rax, %rax
js .L15
pxor %xmm5, %xmm5
cvtsi2sdq %rax, %xmm5
movq %xmm5, %r14
.L16:
movq %r14, %xmm0
subsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, %xmm3
movss .LC11(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L17
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC5(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L17:
cvttss2sil %xmm3, %r13d
movslq %r13d, %rbx
movq %rbx, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 0(,%rbx,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testq %rbx, %rbx
je .L18
movq %rbp, %rax
leaq (%r12,%rbp), %rdx
.L19:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L19
.L18:
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %r14, %xmm0
addsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
mulsd .LC7(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, %xmm3
movss .LC11(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC5(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L20:
cvttss2sil %xmm3, %r14d
movl %r14d, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %edx
sall $10, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl %r14d, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
movl $2, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testq %rbx, %rbx
je .L22
movq %rbp, %rax
leaq (%r12,%rbp), %rcx
movl $0, %ebx
.L23:
movslq (%rax), %rdx
addq %rdx, %rbx
addq $4, %rax
cmpq %rcx, %rax
jne .L23
.L22:
movq %rbx, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L15:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
movq %xmm0, %r14
jmp .L16
.L29:
movl %r13d, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z11checkPrimesPiiPii
jmp .L21
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z11checkPrimesPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11checkPrimesPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1071644672
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1258291200
.align 4
.LC5:
.long 1065353216
.section .rodata.cst8
.align 8
.LC7:
.long 0
.long 1062207488
.section .rodata.cst4
.align 4
.LC11:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
// CUDA kernel. Each thread takes care of one element of c
__device__ int isPrime(bignum x)
{
bignum i;
bignum lim = (bignum)sqrt((float)x) + 1;
if (x % 2 == 0)
{
return 0;
}
for (i = 3; i < lim; i += 2)
{
if (x % i == 0)
return 0;
}
return 1;
}
__global__ void checkPrimes(int *results, int arr_size)
{
// Get our global thread ID
bignum index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < arr_size)
{
bignum number = 2 * index + 1;
results[index] = isPrime(number);
}
}
int main(int argc, char *argv[])
{
if (argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum n = (bignum)atoi(argv[1]);
// Host input vectors
int *h_results;
// Device input vectors
int *d_results;
size_t arr_size = (int)ceil((float) ((n - 1.0) / 2.0));
printf("arr_size: %ld\n", arr_size);
// Size, in bytes, of each vector
size_t results_num_bytes = arr_size * sizeof(int);
// Allocate memory for each vector on host
h_results = (int *)malloc(results_num_bytes);
// Allocate memory for each vector on GPU
cudaMalloc(&d_results, results_num_bytes);
bignum i;
// Initialize vectors on host
for (i = 0; i < arr_size; i++)
{
h_results[i] = 0;
}
// Copy host vectors to device
cudaMemcpy(d_results, h_results, results_num_bytes, cudaMemcpyHostToDevice);
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid
gridSize = (int)ceil((float) ((n + 1.0) / 2.0 / blockSize));
// gridSize = (int)ceil((float)n / blockSize);
printf("gridSize: %d\n", gridSize);
printf("gridSize * blockSize: %d\n", gridSize*blockSize);
// Execute the kernel
checkPrimes<<<gridSize, blockSize>>>(d_results, arr_size);
// Copy array back to host
cudaMemcpy(h_results, d_results, results_num_bytes, cudaMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 without error
bignum sum = 0;
for (i = 0; i < arr_size; i++)
{
sum += h_results[i];
}
printf("final result: %lld\n", sum);
// Release device memory
cudaFree(d_results);
// Release host memory
free(h_results);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
// CUDA kernel. Each thread takes care of one element of c
__device__ int isPrime(bignum x)
{
bignum i;
bignum lim = (bignum)sqrt((float)x) + 1;
if (x % 2 == 0)
{
return 0;
}
for (i = 3; i < lim; i += 2)
{
if (x % i == 0)
return 0;
}
return 1;
}
__global__ void checkPrimes(int *results, int arr_size)
{
// Get our global thread ID
bignum index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < arr_size)
{
bignum number = 2 * index + 1;
results[index] = isPrime(number);
}
}
int main(int argc, char *argv[])
{
if (argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum n = (bignum)atoi(argv[1]);
// Host input vectors
int *h_results;
// Device input vectors
int *d_results;
size_t arr_size = (int)ceil((float) ((n - 1.0) / 2.0));
printf("arr_size: %ld\n", arr_size);
// Size, in bytes, of each vector
size_t results_num_bytes = arr_size * sizeof(int);
// Allocate memory for each vector on host
h_results = (int *)malloc(results_num_bytes);
// Allocate memory for each vector on GPU
hipMalloc(&d_results, results_num_bytes);
bignum i;
// Initialize vectors on host
for (i = 0; i < arr_size; i++)
{
h_results[i] = 0;
}
// Copy host vectors to device
hipMemcpy(d_results, h_results, results_num_bytes, hipMemcpyHostToDevice);
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid
gridSize = (int)ceil((float) ((n + 1.0) / 2.0 / blockSize));
// gridSize = (int)ceil((float)n / blockSize);
printf("gridSize: %d\n", gridSize);
printf("gridSize * blockSize: %d\n", gridSize*blockSize);
// Execute the kernel
checkPrimes<<<gridSize, blockSize>>>(d_results, arr_size);
// Copy array back to host
hipMemcpy(h_results, d_results, results_num_bytes, hipMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 without error
bignum sum = 0;
for (i = 0; i < arr_size; i++)
{
sum += h_results[i];
}
printf("final result: %lld\n", sum);
// Release device memory
hipFree(d_results);
// Release host memory
free(h_results);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
// CUDA kernel. Each thread takes care of one element of c
__device__ int isPrime(bignum x)
{
bignum i;
bignum lim = (bignum)sqrt((float)x) + 1;
if (x % 2 == 0)
{
return 0;
}
for (i = 3; i < lim; i += 2)
{
if (x % i == 0)
return 0;
}
return 1;
}
__global__ void checkPrimes(int *results, int arr_size)
{
// Get our global thread ID
bignum index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < arr_size)
{
bignum number = 2 * index + 1;
results[index] = isPrime(number);
}
}
int main(int argc, char *argv[])
{
if (argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum n = (bignum)atoi(argv[1]);
// Host input vectors
int *h_results;
// Device input vectors
int *d_results;
size_t arr_size = (int)ceil((float) ((n - 1.0) / 2.0));
printf("arr_size: %ld\n", arr_size);
// Size, in bytes, of each vector
size_t results_num_bytes = arr_size * sizeof(int);
// Allocate memory for each vector on host
h_results = (int *)malloc(results_num_bytes);
// Allocate memory for each vector on GPU
hipMalloc(&d_results, results_num_bytes);
bignum i;
// Initialize vectors on host
for (i = 0; i < arr_size; i++)
{
h_results[i] = 0;
}
// Copy host vectors to device
hipMemcpy(d_results, h_results, results_num_bytes, hipMemcpyHostToDevice);
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid
gridSize = (int)ceil((float) ((n + 1.0) / 2.0 / blockSize));
// gridSize = (int)ceil((float)n / blockSize);
printf("gridSize: %d\n", gridSize);
printf("gridSize * blockSize: %d\n", gridSize*blockSize);
// Execute the kernel
checkPrimes<<<gridSize, blockSize>>>(d_results, arr_size);
// Copy array back to host
hipMemcpy(h_results, d_results, results_num_bytes, hipMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 without error
bignum sum = 0;
for (i = 0; i < arr_size; i++)
{
sum += h_results[i];
}
printf("final result: %lld\n", sum);
// Release device memory
hipFree(d_results);
// Release host memory
free(h_results);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11checkPrimesPii
.globl _Z11checkPrimesPii
.p2align 8
.type _Z11checkPrimesPii,@function
_Z11checkPrimesPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
v_lshlrev_b64 v[3:4], 1, v[1:2]
s_mov_b32 s6, 0
s_mov_b64 s[4:5], 3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_clz_i32_u32_e32 v0, v4
v_or_b32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v0, 32, v0
v_lshlrev_b64 v[5:6], v0, v[3:4]
v_sub_nc_u32_e32 v0, 32, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v5, 1, v5
v_or_b32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v5, v5
v_ldexp_f32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v5, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v5, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v6, -1, v5
v_add_nc_u32_e32 v7, 1, v5
v_fma_f32 v8, -v6, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v5, v0
v_cmp_ge_f32_e64 s2, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, v5, v6, s2
v_cmp_lt_f32_e64 s2, 0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, v5, v7, s2
v_mul_f32_e32 v6, 0x37800000, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
v_cndmask_b32_e32 v0, v5, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v0, v0
v_mul_f32_e32 v5, 0x2f800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v5, v5
v_fmac_f32_e32 v0, 0xcf800000, v5
v_cvt_u32_f32_e32 v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_add_co_u32 v5, vcc_lo, v0, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_mov_b32_e32 v0, 1
v_cmpx_lt_u64_e32 3, v[5:6]
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v7, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s2
s_or_b32 s6, s2, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_10
.LBB0_4:
v_or_b32_e32 v8, s5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[7:8]
s_and_saveexec_b32 s2, vcc_lo
s_xor_b32 s7, exec_lo, s2
s_cbranch_execz .LBB0_6
v_cvt_f32_u32_e32 v0, s4
v_cvt_f32_u32_e32 v8, s5
s_sub_u32 s2, 0, s4
s_subb_u32 s8, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v0, 0x4f800000, v8
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, 0x2f800000, v0
v_trunc_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v0, 0xcf800000, v8
v_cvt_u32_f32_e32 v8, v8
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v9, s2, v8
v_mul_hi_u32 v10, s2, v0
v_mul_lo_u32 v11, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, v10, v9
v_mul_lo_u32 v10, s2, v0
v_add_nc_u32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v0, v10
v_mul_lo_u32 v12, v0, v9
v_mul_hi_u32 v13, v0, v9
v_mul_hi_u32 v14, v8, v10
v_mul_lo_u32 v10, v8, v10
v_mul_hi_u32 v15, v8, v9
v_mul_lo_u32 v9, v8, v9
v_add_co_u32 v11, vcc_lo, v11, v12
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v11, v10
v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v9
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v9, s2, v0
v_mul_lo_u32 v11, s8, v0
v_mul_lo_u32 v10, s2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, v9, v10
v_mul_lo_u32 v10, s2, v0
v_add_nc_u32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v0, v10
v_mul_lo_u32 v12, v0, v9
v_mul_hi_u32 v13, v0, v9
v_mul_hi_u32 v14, v8, v10
v_mul_lo_u32 v10, v8, v10
v_mul_hi_u32 v15, v8, v9
v_mul_lo_u32 v9, v8, v9
v_add_co_u32 v11, vcc_lo, v11, v12
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v11, v10
v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v9
v_add_co_ci_u32_e32 v12, vcc_lo, v8, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v13, v3, v0
v_mul_lo_u32 v0, v4, v0
v_mad_u64_u32 v[8:9], null, v3, v12, 0
v_mad_u64_u32 v[10:11], null, v4, v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, v13, v8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v8, v0
v_add_co_ci_u32_e32 v0, vcc_lo, 0, v9, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v11, s5, v0
v_mad_u64_u32 v[8:9], null, s4, v0, 0
v_mul_lo_u32 v0, s4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v8, vcc_lo, v3, v8
v_add3_u32 v0, v9, v0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v4, v0
v_subrev_co_ci_u32_e64 v9, s2, s5, v9, vcc_lo
v_sub_co_ci_u32_e32 v0, vcc_lo, v4, v0, vcc_lo
v_sub_co_u32 v10, vcc_lo, v8, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v11, s2, 0, v9, vcc_lo
v_cmp_le_u32_e64 s2, s4, v8
v_subrev_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v0
v_cndmask_b32_e64 v12, 0, -1, s2
v_cmp_le_u32_e64 s2, s4, v10
v_cndmask_b32_e64 v15, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s5, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v13, 0, -1, s2
v_cmp_le_u32_e64 s2, s5, v11
v_cndmask_b32_e64 v14, 0, -1, s2
v_cmp_eq_u32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v13, v14, v13, vcc_lo
v_sub_co_u32 v14, vcc_lo, v10, s4
v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v13
v_cndmask_b32_e64 v12, v15, v12, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v10, v10, v14
v_cmp_ne_u32_e32 vcc_lo, 0, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v0, v9, vcc_lo
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
.LBB0_6:
s_and_not1_saveexec_b32 s2, s7
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s7, 0, s4
v_mov_b32_e32 v9, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, s7, v0
v_mul_hi_u32 v8, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v8
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s4
v_sub_nc_u32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v8, v0, v8, vcc_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v0, 0
s_mov_b32 s2, -1
s_mov_b32 s7, exec_lo
v_cmpx_ne_u64_e32 0, v[8:9]
s_cbranch_execz .LBB0_3
s_add_u32 s4, s4, 2
s_addc_u32 s5, s5, 0
v_mov_b32_e32 v0, 1
v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
s_or_not1_b32 s2, vcc_lo, exec_lo
s_branch .LBB0_3
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s6
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11checkPrimesPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11checkPrimesPii, .Lfunc_end0-_Z11checkPrimesPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11checkPrimesPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11checkPrimesPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
typedef unsigned long long bignum;
// CUDA kernel. Each thread takes care of one element of c
__device__ int isPrime(bignum x)
{
bignum i;
bignum lim = (bignum)sqrt((float)x) + 1;
if (x % 2 == 0)
{
return 0;
}
for (i = 3; i < lim; i += 2)
{
if (x % i == 0)
return 0;
}
return 1;
}
__global__ void checkPrimes(int *results, int arr_size)
{
// Get our global thread ID
bignum index = blockIdx.x * blockDim.x + threadIdx.x;
if (index < arr_size)
{
bignum number = 2 * index + 1;
results[index] = isPrime(number);
}
}
int main(int argc, char *argv[])
{
if (argc < 2)
{
printf("Usage: prime upbound\n");
exit(-1);
}
bignum n = (bignum)atoi(argv[1]);
// Host input vectors
int *h_results;
// Device input vectors
int *d_results;
size_t arr_size = (int)ceil((float) ((n - 1.0) / 2.0));
printf("arr_size: %ld\n", arr_size);
// Size, in bytes, of each vector
size_t results_num_bytes = arr_size * sizeof(int);
// Allocate memory for each vector on host
h_results = (int *)malloc(results_num_bytes);
// Allocate memory for each vector on GPU
hipMalloc(&d_results, results_num_bytes);
bignum i;
// Initialize vectors on host
for (i = 0; i < arr_size; i++)
{
h_results[i] = 0;
}
// Copy host vectors to device
hipMemcpy(d_results, h_results, results_num_bytes, hipMemcpyHostToDevice);
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 1024;
// Number of thread blocks in grid
gridSize = (int)ceil((float) ((n + 1.0) / 2.0 / blockSize));
// gridSize = (int)ceil((float)n / blockSize);
printf("gridSize: %d\n", gridSize);
printf("gridSize * blockSize: %d\n", gridSize*blockSize);
// Execute the kernel
checkPrimes<<<gridSize, blockSize>>>(d_results, arr_size);
// Copy array back to host
hipMemcpy(h_results, d_results, results_num_bytes, hipMemcpyDeviceToHost);
// Sum up vector c and print result divided by n, this should equal 1 without error
bignum sum = 0;
for (i = 0; i < arr_size; i++)
{
sum += h_results[i];
}
printf("final result: %lld\n", sum);
// Release device memory
hipFree(d_results);
// Release host memory
free(h_results);
return 0;
} | .text
.file "lab1.hip"
.globl _Z26__device_stub__checkPrimesPii # -- Begin function _Z26__device_stub__checkPrimesPii
.p2align 4, 0x90
.type _Z26__device_stub__checkPrimesPii,@function
_Z26__device_stub__checkPrimesPii: # @_Z26__device_stub__checkPrimesPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11checkPrimesPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__checkPrimesPii, .Lfunc_end0-_Z26__device_stub__checkPrimesPii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0xbff0000000000000 # double -1
.LCPI1_3:
.quad 0x3fe0000000000000 # double 0.5
.LCPI1_4:
.quad 0x3ff0000000000000 # double 1
.LCPI1_5:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jle .LBB1_9
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cltq
movq %rax, %xmm0
punpckldq .LCPI1_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI1_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
movapd %xmm1, 96(%rsp) # 16-byte Spill
addsd %xmm1, %xmm0
mulsd .LCPI1_3(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebp
movslq %ebp, %r14
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
leaq (,%r14,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %r14d, %r14d
je .LBB1_3
# %bb.2: # %.lr.ph.preheader
movq %rbx, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
.LBB1_3: # %._crit_edge
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movapd 96(%rsp), %xmm0 # 16-byte Reload
addsd .LCPI1_4(%rip), %xmm0
mulsd .LCPI1_3(%rip), %xmm0
mulsd .LCPI1_5(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12d
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl %r12d, %esi
shll $10, %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $1024, %rdx # imm = 0x400
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11checkPrimesPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %esi, %esi
testl %ebp, %ebp
je .LBB1_8
# %bb.6: # %.lr.ph42.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # %.lr.ph42
# =>This Inner Loop Header: Depth=1
movslq (%rbx,%rax,4), %rcx
addq %rcx, %rsi
incq %rax
cmpq %rax, %r14
jne .LBB1_7
.LBB1_8: # %._crit_edge43
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 160
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11checkPrimesPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11checkPrimesPii,@object # @_Z11checkPrimesPii
.section .rodata,"a",@progbits
.globl _Z11checkPrimesPii
.p2align 3, 0x0
_Z11checkPrimesPii:
.quad _Z26__device_stub__checkPrimesPii
.size _Z11checkPrimesPii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "arr_size: %ld\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "gridSize: %d\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "gridSize * blockSize: %d\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "final result: %lld\n"
.size .L.str.4, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11checkPrimesPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: prime upbound"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__checkPrimesPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11checkPrimesPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11checkPrimesPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR4 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011404 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, RZ, UR4, PT, P0 ; /* 0x00000004ff007c0c */
/* 0x000fda000bf06100 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ IMAD.SHL.U32 R2, R0, 0x2, RZ ; /* 0x0000000200027824 */
/* 0x000fe200078e00ff */
/*00a0*/ SHF.R.U32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011600 */
/*00b0*/ BSSY B0, 0x1c0 ; /* 0x0000010000007945 */
/* 0x000fe60003800000 */
/*00c0*/ LOP3.LUT R2, R2, 0x1, RZ, 0xfc, !PT ; /* 0x0000000102027812 */
/* 0x000fc800078efcff */
/*00d0*/ I2F.U64 R4, R2 ; /* 0x0000000200047312 */
/* 0x000e240000301000 */
/*00e0*/ IADD3 R6, R4, -0xd000000, RZ ; /* 0xf300000004067810 */
/* 0x001fcc0007ffe0ff */
/*00f0*/ MUFU.RSQ R5, R4 ; /* 0x0000000400057308 */
/* 0x0000620000001400 */
/*0100*/ ISETP.GT.U32.AND P0, PT, R6, 0x727fffff, PT ; /* 0x727fffff0600780c */
/* 0x000fda0003f04070 */
/*0110*/ @!P0 BRA 0x170 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0120*/ BSSY B1, 0x160 ; /* 0x0000003000017945 */
/* 0x003fe20003800000 */
/*0130*/ MOV R10, 0x150 ; /* 0x00000150000a7802 */
/* 0x000fe40000000f00 */
/*0140*/ CALL.REL.NOINC 0x940 ; /* 0x000007f000007944 */
/* 0x000fea0003c00000 */
/*0150*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x1b0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0170*/ FMUL.FTZ R7, R4, R5 ; /* 0x0000000504077220 */
/* 0x003fe40000410000 */
/*0180*/ FMUL.FTZ R5, R5, 0.5 ; /* 0x3f00000005057820 */
/* 0x000fe40000410000 */
/*0190*/ FFMA R4, -R7, R7, R4 ; /* 0x0000000707047223 */
/* 0x000fc80000000104 */
/*01a0*/ FFMA R6, R4, R5, R7 ; /* 0x0000000504067223 */
/* 0x000fe40000000007 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ F2I.U64.TRUNC R4, R6 ; /* 0x0000000600047311 */
/* 0x000e22000020d800 */
/*01d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*01e0*/ BSSY B0, 0x4e0 ; /* 0x000002f000007945 */
/* 0x000fe20003800000 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R4, P0, R4, 0x1, RZ ; /* 0x0000000104047810 */
/* 0x001fc80007f1e0ff */
/*0210*/ IADD3.X R5, RZ, R5, RZ, P0, !PT ; /* 0x00000005ff057210 */
/* 0x000fe400007fe4ff */
/*0220*/ ISETP.GE.U32.AND P0, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fc80003f06070 */
/*0230*/ ISETP.GE.U32.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fda0003f06100 */
/*0240*/ @!P0 BRA 0x4d0 ; /* 0x0000028000008947 */
/* 0x000fea0003800000 */
/*0250*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0260*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fd200078e00ff */
/*0270*/ LOP3.LUT R6, R3, R8, RZ, 0xfc, !PT ; /* 0x0000000803067212 */
/* 0x000fe200078efcff */
/*0280*/ BSSY B1, 0x440 ; /* 0x000001b000017945 */
/* 0x000fe60003800000 */
/*0290*/ ISETP.NE.U32.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05070 */
/*02a0*/ @!P0 BRA 0x300 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*02b0*/ MOV R6, 0x2d0 ; /* 0x000002d000067802 */
/* 0x000fe40000000f00 */
/*02c0*/ CALL.REL.NOINC 0x520 ; /* 0x0000025000007944 */
/* 0x000fea0003c00000 */
/*02d0*/ ISETP.NE.U32.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fc80003f05070 */
/*02e0*/ ISETP.NE.AND.EX P0, PT, R12, RZ, PT, P0 ; /* 0x000000ff0c00720c */
/* 0x000fe20003f05300 */
/*02f0*/ BRA 0x430 ; /* 0x0000013000007947 */
/* 0x000fee0003800000 */
/*0300*/ I2F.U32.RP R6, R7 ; /* 0x0000000700067306 */
/* 0x000e220000209000 */
/*0310*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fce0003f25070 */
/*0320*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0330*/ IADD3 R10, R6, 0xffffffe, RZ ; /* 0x0ffffffe060a7810 */
/* 0x001fcc0007ffe0ff */
/*0340*/ F2I.FTZ.U32.TRUNC.NTZ R11, R10 ; /* 0x0000000a000b7305 */
/* 0x000064000021f000 */
/*0350*/ IMAD.MOV.U32 R10, RZ, RZ, RZ ; /* 0x000000ffff0a7224 */
/* 0x001fe400078e00ff */
/*0360*/ IMAD.MOV R12, RZ, RZ, -R11 ; /* 0x000000ffff0c7224 */
/* 0x002fc800078e0a0b */
/*0370*/ IMAD R9, R12, R7, RZ ; /* 0x000000070c097224 */
/* 0x000fc800078e02ff */
/*0380*/ IMAD.HI.U32 R11, R11, R9, R10 ; /* 0x000000090b0b7227 */
/* 0x000fcc00078e000a */
/*0390*/ IMAD.HI.U32 R11, R11, R2, RZ ; /* 0x000000020b0b7227 */
/* 0x000fca00078e00ff */
/*03a0*/ IADD3 R11, -R11, RZ, RZ ; /* 0x000000ff0b0b7210 */
/* 0x000fca0007ffe1ff */
/*03b0*/ IMAD R12, R7, R11, R2 ; /* 0x0000000b070c7224 */
/* 0x000fca00078e0202 */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x000fda0003f06070 */
/*03d0*/ @P0 IMAD.IADD R12, R12, 0x1, -R7 ; /* 0x000000010c0c0824 */
/* 0x000fca00078e0a07 */
/*03e0*/ ISETP.GE.U32.AND P0, PT, R12, R7, PT ; /* 0x000000070c00720c */
/* 0x000fda0003f06070 */
/*03f0*/ @P0 IMAD.IADD R12, R12, 0x1, -R7 ; /* 0x000000010c0c0824 */
/* 0x000fe200078e0a07 */
/*0400*/ @!P1 LOP3.LUT R12, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff0c9212 */
/* 0x000fc800078e33ff */
/*0410*/ ISETP.NE.U32.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc80003f05070 */
/*0420*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd00003f05300 */
/*0430*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0440*/ IADD3 R6, P1, R7, 0x2, RZ ; /* 0x0000000207067810 */
/* 0x000fe40007f3e0ff */
/*0450*/ MOV R7, RZ ; /* 0x000000ff00077202 */
/* 0x000fc60000000f00 */
/*0460*/ IMAD.X R8, RZ, RZ, R8, P1 ; /* 0x000000ffff087224 */
/* 0x000fe200008e0608 */
/*0470*/ @!P0 BRA 0x4d0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0480*/ IMAD.MOV.U32 R7, RZ, RZ, R6 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0006 */
/*0490*/ ISETP.GE.U32.AND P0, PT, R7, R4, PT ; /* 0x000000040700720c */
/* 0x000fc80003f06070 */
/*04a0*/ ISETP.GE.U32.AND.EX P0, PT, R8, R5, PT, P0 ; /* 0x000000050800720c */
/* 0x000fda0003f06100 */
/*04b0*/ @!P0 BRA 0x270 ; /* 0xfffffdb000008947 */
/* 0x000fea000383ffff */
/*04c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff077435 */
/* 0x000fcc00000001ff */
/*04d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04e0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*04f0*/ LEA.HI.X R3, R0, c[0x0][0x164], RZ, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f14ff */
/*0500*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ IMAD.MOV.U32 R14, RZ, RZ, R7 ; /* 0x000000ffff0e7224 */
/* 0x000fe400078e0007 */
/*0530*/ IMAD.MOV.U32 R15, RZ, RZ, R8 ; /* 0x000000ffff0f7224 */
/* 0x000fc800078e0008 */
/*0540*/ I2F.U64.RP R9, R14 ; /* 0x0000000e00097312 */
/* 0x000e300000309000 */
/*0550*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x001e240000001000 */
/*0560*/ IADD3 R10, R9, 0x1ffffffe, RZ ; /* 0x1ffffffe090a7810 */
/* 0x001fcc0007ffe0ff */
/*0570*/ F2I.U64.TRUNC R10, R10 ; /* 0x0000000a000a7311 */
/* 0x000e24000020d800 */
/*0580*/ IMAD.WIDE.U32 R12, R10, R7, RZ ; /* 0x000000070a0c7225 */
/* 0x001fc800078e00ff */
/*0590*/ IMAD R13, R10, R8, R13 ; /* 0x000000080a0d7224 */
/* 0x000fe200078e020d */
/*05a0*/ IADD3 R17, P0, RZ, -R12, RZ ; /* 0x8000000cff117210 */
/* 0x000fc60007f1e0ff */
/*05b0*/ IMAD R13, R11, R7, R13 ; /* 0x000000070b0d7224 */
/* 0x000fe400078e020d */
/*05c0*/ IMAD.HI.U32 R12, R10, R17, RZ ; /* 0x000000110a0c7227 */
/* 0x000fc600078e00ff */
/*05d0*/ IADD3.X R19, RZ, ~R13, RZ, P0, !PT ; /* 0x8000000dff137210 */
/* 0x000fe200007fe4ff */
/*05e0*/ IMAD.MOV.U32 R13, RZ, RZ, R10 ; /* 0x000000ffff0d7224 */
/* 0x000fc800078e000a */
/*05f0*/ IMAD.WIDE.U32 R12, P0, R10, R19, R12 ; /* 0x000000130a0c7225 */
/* 0x000fc8000780000c */
/*0600*/ IMAD R15, R11.reuse, R19, RZ ; /* 0x000000130b0f7224 */
/* 0x040fe400078e02ff */
/*0610*/ IMAD.HI.U32 R12, P1, R11, R17, R12 ; /* 0x000000110b0c7227 */
/* 0x000fc8000782000c */
/*0620*/ IMAD.HI.U32 R9, R11, R19, RZ ; /* 0x000000130b097227 */
/* 0x000fe200078e00ff */
/*0630*/ IADD3 R13, P2, R15, R12, RZ ; /* 0x0000000c0f0d7210 */
/* 0x000fc60007f5e0ff */
/*0640*/ IMAD.X R9, R9, 0x1, R11, P0 ; /* 0x0000000109097824 */
/* 0x000fe400000e060b */
/*0650*/ IMAD.WIDE.U32 R10, R13, R7, RZ ; /* 0x000000070d0a7225 */
/* 0x000fc600078e00ff */
/*0660*/ IADD3.X R9, RZ, RZ, R9, P2, P1 ; /* 0x000000ffff097210 */
/* 0x000fe200017e2409 */
/*0670*/ IMAD R12, R13, R8, R11 ; /* 0x000000080d0c7224 */
/* 0x000fe200078e020b */
/*0680*/ IADD3 R11, P0, RZ, -R10, RZ ; /* 0x8000000aff0b7210 */
/* 0x000fc60007f1e0ff */
/*0690*/ IMAD R10, R9, R7, R12 ; /* 0x00000007090a7224 */
/* 0x000fe400078e020c */
/*06a0*/ IMAD.HI.U32 R12, R13, R11, RZ ; /* 0x0000000b0d0c7227 */
/* 0x000fc600078e00ff */
/*06b0*/ IADD3.X R10, RZ, ~R10, RZ, P0, !PT ; /* 0x8000000aff0a7210 */
/* 0x000fca00007fe4ff */
/*06c0*/ IMAD.WIDE.U32 R12, P0, R13, R10, R12 ; /* 0x0000000a0d0c7225 */
/* 0x000fc8000780000c */
/*06d0*/ IMAD R14, R9.reuse, R10, RZ ; /* 0x0000000a090e7224 */
/* 0x040fe400078e02ff */
/*06e0*/ IMAD.HI.U32 R13, P1, R9, R11, R12 ; /* 0x0000000b090d7227 */
/* 0x000fc8000782000c */
/*06f0*/ IMAD.HI.U32 R10, R9, R10, RZ ; /* 0x0000000a090a7227 */
/* 0x000fe200078e00ff */
/*0700*/ IADD3 R13, P2, R14, R13, RZ ; /* 0x0000000d0e0d7210 */
/* 0x000fc60007f5e0ff */
/*0710*/ IMAD.X R9, R10, 0x1, R9, P0 ; /* 0x000000010a097824 */
/* 0x000fe400000e0609 */
/*0720*/ IMAD.HI.U32 R10, R13, R2, RZ ; /* 0x000000020d0a7227 */
/* 0x000fc600078e00ff */
/*0730*/ IADD3.X R9, RZ, RZ, R9, P2, P1 ; /* 0x000000ffff097210 */
/* 0x000fe200017e2409 */
/*0740*/ IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e00ff */
/*0750*/ IMAD.WIDE.U32 R10, R13, R3, R10 ; /* 0x000000030d0a7225 */
/* 0x000fc800078e000a */
/*0760*/ IMAD R13, R9.reuse, R3, RZ ; /* 0x00000003090d7224 */
/* 0x040fe400078e02ff */
/*0770*/ IMAD.HI.U32 R10, P0, R9, R2, R10 ; /* 0x00000002090a7227 */
/* 0x000fc8000780000a */
/*0780*/ IMAD.HI.U32 R9, R9, R3, RZ ; /* 0x0000000309097227 */
/* 0x000fe200078e00ff */
/*0790*/ IADD3 R13, P1, R13, R10, RZ ; /* 0x0000000a0d0d7210 */
/* 0x000fc80007f3e0ff */
/*07a0*/ IADD3.X R9, R9, RZ, RZ, P0, !PT ; /* 0x000000ff09097210 */
/* 0x000fe200007fe4ff */
/*07b0*/ IMAD.WIDE.U32 R10, R13, R7, RZ ; /* 0x000000070d0a7225 */
/* 0x000fc800078e00ff */
/*07c0*/ IMAD.X R12, RZ, RZ, R9, P1 ; /* 0x000000ffff0c7224 */
/* 0x000fe200008e0609 */
/*07d0*/ IADD3 R14, P1, -R10, R2, RZ ; /* 0x000000020a0e7210 */
/* 0x000fe20007f3e1ff */
/*07e0*/ IMAD R13, R13, R8, R11 ; /* 0x000000080d0d7224 */
/* 0x000fc600078e020b */
/*07f0*/ ISETP.GE.U32.AND P0, PT, R14, R7.reuse, PT ; /* 0x000000070e00720c */
/* 0x080fe20003f06070 */
/*0800*/ IMAD R13, R12, R7, R13 ; /* 0x000000070c0d7224 */
/* 0x000fc800078e020d */
/*0810*/ IMAD.X R13, R3, 0x1, ~R13, P1 ; /* 0x00000001030d7824 */
/* 0x000fe200008e0e0d */
/*0820*/ IADD3 R10, P1, -R7, R14, RZ ; /* 0x0000000e070a7210 */
/* 0x000fc80007f3e1ff */
/*0830*/ ISETP.GE.U32.AND.EX P0, PT, R13, R8, PT, P0 ; /* 0x000000080d00720c */
/* 0x000fe40003f06100 */
/*0840*/ IADD3.X R11, ~R8, R13.reuse, RZ, P1, !PT ; /* 0x0000000d080b7210 */
/* 0x080fe40000ffe5ff */
/*0850*/ SEL R10, R10, R14, P0 ; /* 0x0000000e0a0a7207 */
/* 0x000fe40000000000 */
/*0860*/ SEL R11, R11, R13, P0 ; /* 0x0000000d0b0b7207 */
/* 0x000fe40000000000 */
/*0870*/ IADD3 R9, P2, -R7, R10, RZ ; /* 0x0000000a07097210 */
/* 0x000fe40007f5e1ff */
/*0880*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fc40003f06070 */
/*0890*/ ISETP.NE.U32.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe20003f25070 */
/*08a0*/ IMAD.X R12, R11.reuse, 0x1, ~R8, P2 ; /* 0x000000010b0c7824 */
/* 0x040fe200010e0e08 */
/*08b0*/ ISETP.GE.U32.AND.EX P0, PT, R11, R8, PT, P0 ; /* 0x000000080b00720c */
/* 0x000fe40003f06100 */
/*08c0*/ ISETP.NE.AND.EX P1, PT, R8, RZ, PT, P1 ; /* 0x000000ff0800720c */
/* 0x000fe40003f25310 */
/*08d0*/ SEL R9, R9, R10, P0 ; /* 0x0000000a09097207 */
/* 0x000fe20000000000 */
/*08e0*/ IMAD.MOV.U32 R10, RZ, RZ, R6 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0006 */
/*08f0*/ SEL R12, R12, R11, P0 ; /* 0x0000000b0c0c7207 */
/* 0x000fe40000000000 */
/*0900*/ MOV R11, 0x0 ; /* 0x00000000000b7802 */
/* 0x000fc40000000f00 */
/*0910*/ SEL R9, R9, 0xffffffff, P1 ; /* 0xffffffff09097807 */
/* 0x000fe40000800000 */
/*0920*/ SEL R12, R12, 0xffffffff, P1 ; /* 0xffffffff0c0c7807 */
/* 0x000fe20000800000 */
/*0930*/ RET.REL.NODEC R10 0x0 ; /* 0xfffff6c00a007950 */
/* 0x000fec0003c3ffff */
/*0940*/ LOP3.LUT P0, RZ, R4, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff04ff7812 */
/* 0x000fda000780c0ff */
/*0950*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff058224 */
/* 0x000fe200078e0004 */
/*0960*/ @!P0 BRA 0xa70 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0970*/ FSETP.GEU.FTZ.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fda0003f1e000 */
/*0980*/ @!P0 MOV R5, 0x7fffffff ; /* 0x7fffffff00058802 */
/* 0x000fe20000000f00 */
/*0990*/ @!P0 BRA 0xa70 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*09a0*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1c200 */
/*09b0*/ @P0 FADD.FTZ R5, R4, 1 ; /* 0x3f80000004050421 */
/* 0x000fe20000010000 */
/*09c0*/ @P0 BRA 0xa70 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*09d0*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fda0003f1d200 */
/*09e0*/ @P0 FFMA R6, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004060823 */
/* 0x000fc800000000ff */
/*09f0*/ @P0 MUFU.RSQ R5, R6 ; /* 0x0000000600050308 */
/* 0x000e240000001400 */
/*0a00*/ @P0 FMUL.FTZ R7, R6, R5 ; /* 0x0000000506070220 */
/* 0x001fe40000410000 */
/*0a10*/ @P0 FMUL.FTZ R9, R5, 0.5 ; /* 0x3f00000005090820 */
/* 0x000fe40000410000 */
/*0a20*/ @P0 FADD.FTZ R8, -R7.reuse, -RZ ; /* 0x800000ff07080221 */
/* 0x040fe40000010100 */
/*0a30*/ @!P0 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff058224 */
/* 0x000fe400078e0004 */
/*0a40*/ @P0 FFMA R8, R7, R8, R6 ; /* 0x0000000807080223 */
/* 0x000fc80000000006 */
/*0a50*/ @P0 FFMA R8, R8, R9, R7 ; /* 0x0000000908080223 */
/* 0x000fc80000000007 */
/*0a60*/ @P0 FMUL.FTZ R5, R8, 2.3283064365386962891e-10 ; /* 0x2f80000008050820 */
/* 0x000fca0000410000 */
/*0a70*/ MOV R6, R5 ; /* 0x0000000500067202 */
/* 0x000fe20000000f00 */
/*0a80*/ HFMA2.MMA R5, -RZ, RZ, 0, 0 ; /* 0x00000000ff057435 */
/* 0x000fe200000001ff */
/*0a90*/ IMAD.MOV.U32 R4, RZ, RZ, R10 ; /* 0x000000ffff047224 */
/* 0x000fca00078e000a */
/*0aa0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffff55004007950 */
/* 0x000fea0003c3ffff */
/*0ab0*/ BRA 0xab0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11checkPrimesPii
.globl _Z11checkPrimesPii
.p2align 8
.type _Z11checkPrimesPii,@function
_Z11checkPrimesPii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
v_mov_b32_e32 v2, 0
s_ashr_i32 s3, s2, 31
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[1:2]
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_12
v_lshlrev_b64 v[3:4], 1, v[1:2]
s_mov_b32 s6, 0
s_mov_b64 s[4:5], 3
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_clz_i32_u32_e32 v0, v4
v_or_b32_e32 v3, 1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v0, 32, v0
v_lshlrev_b64 v[5:6], v0, v[3:4]
v_sub_nc_u32_e32 v0, 32, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v5, 1, v5
v_or_b32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_u32_e32 v5, v5
v_ldexp_f32 v0, v5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v5, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
v_cndmask_b32_e32 v0, v0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v5, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v6, -1, v5
v_add_nc_u32_e32 v7, 1, v5
v_fma_f32 v8, -v6, v5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v9, -v7, v5, v0
v_cmp_ge_f32_e64 s2, 0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v5, v5, v6, s2
v_cmp_lt_f32_e64 s2, 0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, v5, v7, s2
v_mul_f32_e32 v6, 0x37800000, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
v_cndmask_b32_e32 v0, v5, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_trunc_f32_e32 v0, v0
v_mul_f32_e32 v5, 0x2f800000, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_floor_f32_e32 v5, v5
v_fmac_f32_e32 v0, 0xcf800000, v5
v_cvt_u32_f32_e32 v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_add_co_u32 v5, vcc_lo, v0, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
v_mov_b32_e32 v0, 1
v_cmpx_lt_u64_e32 3, v[5:6]
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v7, 0
s_branch .LBB0_4
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s2
s_or_b32 s6, s2, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execz .LBB0_10
.LBB0_4:
v_or_b32_e32 v8, s5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ne_u64_e32 vcc_lo, 0, v[7:8]
s_and_saveexec_b32 s2, vcc_lo
s_xor_b32 s7, exec_lo, s2
s_cbranch_execz .LBB0_6
v_cvt_f32_u32_e32 v0, s4
v_cvt_f32_u32_e32 v8, s5
s_sub_u32 s2, 0, s4
s_subb_u32 s8, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v0, 0x4f800000, v8
v_rcp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x5f7ffffc, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, 0x2f800000, v0
v_trunc_f32_e32 v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v0, 0xcf800000, v8
v_cvt_u32_f32_e32 v8, v8
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v9, s2, v8
v_mul_hi_u32 v10, s2, v0
v_mul_lo_u32 v11, s8, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, v10, v9
v_mul_lo_u32 v10, s2, v0
v_add_nc_u32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v0, v10
v_mul_lo_u32 v12, v0, v9
v_mul_hi_u32 v13, v0, v9
v_mul_hi_u32 v14, v8, v10
v_mul_lo_u32 v10, v8, v10
v_mul_hi_u32 v15, v8, v9
v_mul_lo_u32 v9, v8, v9
v_add_co_u32 v11, vcc_lo, v11, v12
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v11, v10
v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v9
v_add_co_ci_u32_e32 v8, vcc_lo, v8, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v9, s2, v0
v_mul_lo_u32 v11, s8, v0
v_mul_lo_u32 v10, s2, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v9, v9, v10
v_mul_lo_u32 v10, s2, v0
v_add_nc_u32_e32 v9, v9, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v11, v0, v10
v_mul_lo_u32 v12, v0, v9
v_mul_hi_u32 v13, v0, v9
v_mul_hi_u32 v14, v8, v10
v_mul_lo_u32 v10, v8, v10
v_mul_hi_u32 v15, v8, v9
v_mul_lo_u32 v9, v8, v9
v_add_co_u32 v11, vcc_lo, v11, v12
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v10, vcc_lo, v11, v10
v_add_co_ci_u32_e32 v10, vcc_lo, v12, v14, vcc_lo
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v15, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, v10, v9
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v9
v_add_co_ci_u32_e32 v12, vcc_lo, v8, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_hi_u32 v13, v3, v0
v_mul_lo_u32 v0, v4, v0
v_mad_u64_u32 v[8:9], null, v3, v12, 0
v_mad_u64_u32 v[10:11], null, v4, v12, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v8, vcc_lo, v13, v8
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v8, v0
v_add_co_ci_u32_e32 v0, vcc_lo, 0, v9, vcc_lo
v_add_co_ci_u32_e32 v8, vcc_lo, 0, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v10
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_lo_u32 v11, s5, v0
v_mad_u64_u32 v[8:9], null, s4, v0, 0
v_mul_lo_u32 v0, s4, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v8, vcc_lo, v3, v8
v_add3_u32 v0, v9, v0, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v9, v4, v0
v_subrev_co_ci_u32_e64 v9, s2, s5, v9, vcc_lo
v_sub_co_ci_u32_e32 v0, vcc_lo, v4, v0, vcc_lo
v_sub_co_u32 v10, vcc_lo, v8, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_subrev_co_ci_u32_e64 v11, s2, 0, v9, vcc_lo
v_cmp_le_u32_e64 s2, s4, v8
v_subrev_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s5, v0
v_cndmask_b32_e64 v12, 0, -1, s2
v_cmp_le_u32_e64 s2, s4, v10
v_cndmask_b32_e64 v15, 0, -1, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, s5, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v13, 0, -1, s2
v_cmp_le_u32_e64 s2, s5, v11
v_cndmask_b32_e64 v14, 0, -1, s2
v_cmp_eq_u32_e64 s2, s5, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v13, v14, v13, vcc_lo
v_sub_co_u32 v14, vcc_lo, v10, s4
v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
v_cmp_ne_u32_e32 vcc_lo, 0, v13
v_cndmask_b32_e64 v12, v15, v12, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v10, v10, v14
v_cmp_ne_u32_e32 vcc_lo, 0, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v9, v0, v9, vcc_lo
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
.LBB0_6:
s_and_not1_saveexec_b32 s2, s7
s_cbranch_execz .LBB0_8
v_cvt_f32_u32_e32 v0, s4
s_sub_i32 s7, 0, s4
v_mov_b32_e32 v9, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
v_cvt_u32_f32_e32 v0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v8, s7, v0
v_mul_hi_u32 v8, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v8
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v0, v0, s4
v_sub_nc_u32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v0, v0, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v8, s4, v0
v_cmp_le_u32_e32 vcc_lo, s4, v0
v_cndmask_b32_e32 v8, v0, v8, vcc_lo
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
v_mov_b32_e32 v0, 0
s_mov_b32 s2, -1
s_mov_b32 s7, exec_lo
v_cmpx_ne_u64_e32 0, v[8:9]
s_cbranch_execz .LBB0_3
s_add_u32 s4, s4, 2
s_addc_u32 s5, s5, 0
v_mov_b32_e32 v0, 1
v_cmp_ge_u64_e32 vcc_lo, s[4:5], v[5:6]
s_or_not1_b32 s2, vcc_lo, exec_lo
s_branch .LBB0_3
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s6
.LBB0_11:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_or_b32 exec_lo, exec_lo, s3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11checkPrimesPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11checkPrimesPii, .Lfunc_end0-_Z11checkPrimesPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11checkPrimesPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11checkPrimesPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a6b18_00000000-6_lab1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z7isPrimey
.type _Z7isPrimey, @function
_Z7isPrimey:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z7isPrimey, .-_Z7isPrimey
.globl _Z32__device_stub__Z11checkPrimesPiiPii
.type _Z32__device_stub__Z11checkPrimesPiiPii, @function
_Z32__device_stub__Z11checkPrimesPiiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11checkPrimesPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z32__device_stub__Z11checkPrimesPiiPii, .-_Z32__device_stub__Z11checkPrimesPiiPii
.globl _Z11checkPrimesPii
.type _Z11checkPrimesPii, @function
_Z11checkPrimesPii:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11checkPrimesPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z11checkPrimesPii, .-_Z11checkPrimesPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Usage: prime upbound\n"
.LC6:
.string "arr_size: %ld\n"
.LC8:
.string "gridSize: %d\n"
.LC9:
.string "gridSize * blockSize: %d\n"
.LC10:
.string "final result: %lld\n"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
cmpl $1, %edi
jle .L28
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
cltq
testq %rax, %rax
js .L15
pxor %xmm5, %xmm5
cvtsi2sdq %rax, %xmm5
movq %xmm5, %r14
.L16:
movq %r14, %xmm0
subsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, %xmm3
movss .LC11(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L17
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC5(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L17:
cvttss2sil %xmm3, %r13d
movslq %r13d, %rbx
movq %rbx, %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 0(,%rbx,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
testq %rbx, %rbx
je .L18
movq %rbp, %rax
leaq (%r12,%rbp), %rdx
.L19:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L19
.L18:
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movq %r14, %xmm0
addsd .LC1(%rip), %xmm0
mulsd .LC2(%rip), %xmm0
mulsd .LC7(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
movaps %xmm0, %xmm3
movss .LC11(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC3(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L20
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC5(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L20:
cvttss2sil %xmm3, %r14d
movl %r14d, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, %edx
sall $10, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl %r14d, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L21:
movl $2, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testq %rbx, %rbx
je .L22
movq %rbp, %rax
leaq (%r12,%rbp), %rcx
movl $0, %ebx
.L23:
movslq (%rax), %rdx
addq %rdx, %rbx
addq $4, %rax
cmpq %rcx, %rax
jne .L23
.L22:
movq %rbx, %rdx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbp, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L30
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L28:
.cfi_restore_state
leaq .LC0(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L15:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2sdq %rdx, %xmm0
addsd %xmm0, %xmm0
movq %xmm0, %r14
jmp .L16
.L29:
movl %r13d, %esi
movq 8(%rsp), %rdi
call _Z32__device_stub__Z11checkPrimesPiiPii
jmp .L21
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z11checkPrimesPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11checkPrimesPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1071644672
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1258291200
.align 4
.LC5:
.long 1065353216
.section .rodata.cst8
.align 8
.LC7:
.long 0
.long 1062207488
.section .rodata.cst4
.align 4
.LC11:
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "lab1.hip"
.globl _Z26__device_stub__checkPrimesPii # -- Begin function _Z26__device_stub__checkPrimesPii
.p2align 4, 0x90
.type _Z26__device_stub__checkPrimesPii,@function
_Z26__device_stub__checkPrimesPii: # @_Z26__device_stub__checkPrimesPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11checkPrimesPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__checkPrimesPii, .Lfunc_end0-_Z26__device_stub__checkPrimesPii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0xbff0000000000000 # double -1
.LCPI1_3:
.quad 0x3fe0000000000000 # double 0.5
.LCPI1_4:
.quad 0x3ff0000000000000 # double 1
.LCPI1_5:
.quad 0x3f50000000000000 # double 9.765625E-4
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $112, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $1, %edi
jle .LBB1_9
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
cltq
movq %rax, %xmm0
punpckldq .LCPI1_0(%rip), %xmm0 # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1]
subpd .LCPI1_1(%rip), %xmm0
movapd %xmm0, %xmm1
unpckhpd %xmm0, %xmm1 # xmm1 = xmm1[1],xmm0[1]
addsd %xmm0, %xmm1
movsd .LCPI1_2(%rip), %xmm0 # xmm0 = mem[0],zero
movapd %xmm1, 96(%rsp) # 16-byte Spill
addsd %xmm1, %xmm0
mulsd .LCPI1_3(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebp
movslq %ebp, %r14
movl $.L.str.1, %edi
movq %r14, %rsi
xorl %eax, %eax
callq printf
leaq (,%r14,4), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %r14d, %r14d
je .LBB1_3
# %bb.2: # %.lr.ph.preheader
movq %rbx, %rdi
xorl %esi, %esi
movq %r15, %rdx
callq memset@PLT
.LBB1_3: # %._crit_edge
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movapd 96(%rsp), %xmm0 # 16-byte Reload
addsd .LCPI1_4(%rip), %xmm0
mulsd .LCPI1_3(%rip), %xmm0
mulsd .LCPI1_5(%rip), %xmm0
cvtsd2ss %xmm0, %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %r12d
movl $.L.str.2, %edi
movl %r12d, %esi
xorl %eax, %eax
callq printf
movl %r12d, %esi
shll $10, %esi
movl $.L.str.3, %edi
xorl %eax, %eax
callq printf
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r12
orq $1024, %rdx # imm = 0x400
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movl %ebp, 20(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11checkPrimesPii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
xorl %esi, %esi
testl %ebp, %ebp
je .LBB1_8
# %bb.6: # %.lr.ph42.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_7: # %.lr.ph42
# =>This Inner Loop Header: Depth=1
movslq (%rbx,%rax,4), %rcx
addq %rcx, %rsi
incq %rax
cmpq %rax, %r14
jne .LBB1_7
.LBB1_8: # %._crit_edge43
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_9:
.cfi_def_cfa_offset 160
movl $.Lstr, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11checkPrimesPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11checkPrimesPii,@object # @_Z11checkPrimesPii
.section .rodata,"a",@progbits
.globl _Z11checkPrimesPii
.p2align 3, 0x0
_Z11checkPrimesPii:
.quad _Z26__device_stub__checkPrimesPii
.size _Z11checkPrimesPii, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "arr_size: %ld\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "gridSize: %d\n"
.size .L.str.2, 14
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "gridSize * blockSize: %d\n"
.size .L.str.3, 26
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "final result: %lld\n"
.size .L.str.4, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11checkPrimesPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Usage: prime upbound"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__checkPrimesPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11checkPrimesPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__device__ void sleep0(void *p_kernel_time, int clockRate)
{
//This method will sleep for clockRate*kernel_time many clock ticks
// which is equivalent to sleeping for kernel_time milliseconds
int kernel_time = *((int *) p_kernel_time);
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__device__ void sleep0(void *p_kernel_time, int clockRate)
{
//This method will sleep for clockRate*kernel_time many clock ticks
// which is equivalent to sleeping for kernel_time milliseconds
int kernel_time = *((int *) p_kernel_time);
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
} | .file "tmpxft_0007bd3f_00000000-6_Sleep0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6sleep0Pvi
.type _Z6sleep0Pvi, @function
_Z6sleep0Pvi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6sleep0Pvi, .-_Z6sleep0Pvi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__device__ void sleep0(void *p_kernel_time, int clockRate)
{
//This method will sleep for clockRate*kernel_time many clock ticks
// which is equivalent to sleeping for kernel_time milliseconds
int kernel_time = *((int *) p_kernel_time);
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void sleep0(void *p_kernel_time, int clockRate)
{
//This method will sleep for clockRate*kernel_time many clock ticks
// which is equivalent to sleeping for kernel_time milliseconds
int kernel_time = *((int *) p_kernel_time);
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void sleep0(void *p_kernel_time, int clockRate)
{
//This method will sleep for clockRate*kernel_time many clock ticks
// which is equivalent to sleeping for kernel_time milliseconds
int kernel_time = *((int *) p_kernel_time);
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__device__ void sleep0(void *p_kernel_time, int clockRate)
{
//This method will sleep for clockRate*kernel_time many clock ticks
// which is equivalent to sleeping for kernel_time milliseconds
int kernel_time = *((int *) p_kernel_time);
int finish_clock;
int start_time;
for(int temp=0; temp<kernel_time; temp++){
start_time = clock();
finish_clock = start_time + clockRate;
bool wrapped = finish_clock < start_time;
while( clock() < finish_clock || wrapped) wrapped = clock()>0 && wrapped;
}
} | .text
.file "Sleep0.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007bd3f_00000000-6_Sleep0.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6sleep0Pvi
.type _Z6sleep0Pvi, @function
_Z6sleep0Pvi:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z6sleep0Pvi, .-_Z6sleep0Pvi
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Sleep0.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
cudaError err = cudaGetLastError();\
if( err != cudaSuccess){\
printf("Cuda Error: '%s' for %s\n", cudaGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__device__ unsigned int exor(unsigned long a,unsigned long b)
{
unsigned int res;
for (int i = 63; i >= 0; i--)
{
// Find current bits in x and y
bool b1 = a & (1 << i);
bool b2 = b & (1 << i);
// If both are 1 then 0 else xor is same as OR
bool xoredBit = (b1 & b2) ? 0 : (b1 | b2);
// Update result
res <<= 1;
res |= xoredBit;
}
//res=exor(a,b);
return res;
}
__global__ void calculate(unsigned long *mem,int num,int iter)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i >= num)
return;
// unsigned long *t1,*t2;
if(i<num/2){
int tmp=i*2;
if(tmp+iter<num)
mem[tmp]=exor(mem[tmp],mem[tmp+iter]);
// else
// mem[tmp]=exor(mem[tmp],0);
// mem[num]=res;
}
}
int main(int argc, char **argv){
struct timeval start, end, t_start, t_end;
int i,blocks=0;
unsigned long *p1,*g1;
unsigned long seed,num;
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
seed=atoi(argv[2]);
}
// printf("%d",time(0));
p1 = (unsigned long *)malloc((num+1) *sizeof(unsigned long));
srand(seed);
for(i=0; i<num; ++i){
p1[i]=random();
// printf("%d %lu\n",i,p1[i]);
}
p1[i]=0;
gettimeofday(&t_start, NULL);
//for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
cudaMalloc(&g1, (num+1) * sizeof(unsigned long));
CUDA_ERROR_EXIT("cudaMalloc");
cudaMemcpy(g1, p1, (num+1) * sizeof(unsigned long) , cudaMemcpyHostToDevice);
CUDA_ERROR_EXIT("cudaMemcpy");
gettimeofday(&start, NULL);
blocks = num /1024;
if(num % 1024)
++blocks;
for(i=0;i<log(num)/log(2);i++){
calculate<<<blocks,1024>>>(g1,num,(int)pow(2,i));
}
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
/* Copy back result*/
cudaMemcpy(p1, g1, (num+1) * sizeof(unsigned long), cudaMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
// for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
printf("%lu",p1[0]);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
cudaFree(g1);
/*Print the last element for sanity check*/
printf("The XOR final value is %lu",p1[num]);
free(p1);
// free(pfinal);
return 0;
} | code for sm_80
Function : _Z9calculatePmii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe40000000800 */
/*0030*/ ULEA.HI UR4, UR4, UR4, URZ, 0x1 ; /* 0x0000000404047291 */
/* 0x000fe2000f8f083f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e260000002100 */
/*0050*/ USHF.R.S32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fe20008011404 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc8000bf06270 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.SHL.U32 R0, R0, 0x2, RZ ; /* 0x0000000200007824 */
/* 0x000fca00078e00ff */
/*00b0*/ IADD3 R2, R0, c[0x0][0x16c], RZ ; /* 0x00005b0000027a10 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x168], PT ; /* 0x00005a0002007a0c */
/* 0x000fda0003f06270 */
/*00d0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*00f0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0100*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*0110*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*0120*/ IMAD.WIDE R6, R7, c[0x0][0x16c], R2 ; /* 0x00005b0007067a25 */
/* 0x000fcc00078e0202 */
/*0130*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0140*/ LOP3.LUT P1, RZ, R4, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000004ff7812 */
/* 0x004fe4000782c0ff */
/*0150*/ LOP3.LUT P2, RZ, R6.reuse, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000006ff7812 */
/* 0x048fe4000784c0ff */
/*0160*/ LOP3.LUT R9, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507097212 */
/* 0x000fe400078efcff */
/*0170*/ LOP3.LUT P0, RZ, R6.reuse, 0x80000000, R4, 0xc8, !PT ; /* 0x8000000006ff7812 */
/* 0x040fe4000780c804 */
/*0180*/ LOP3.LUT R0, R6, R4, RZ, 0xfc, !PT ; /* 0x0000000406007212 */
/* 0x000fe400078efcff */
/*0190*/ LOP3.LUT P1, RZ, R5, 0xffffffff, RZ, 0xc0, P1 ; /* 0xffffffff05ff7812 */
/* 0x000fc4000082c0ff */
/*01a0*/ LOP3.LUT P2, RZ, R7, 0xffffffff, RZ, 0xc0, P2 ; /* 0xffffffff07ff7812 */
/* 0x000fe4000104c0ff */
/*01b0*/ LOP3.LUT P0, RZ, R9, 0xffffffff, RZ, 0xc0, P0 ; /* 0xffffffff09ff7812 */
/* 0x000fe4000000c0ff */
/*01c0*/ SHF.R.U64 R8, R0, 0x1e, R9 ; /* 0x0000001e00087819 */
/* 0x000fe40000001209 */
/*01d0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0x70, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000702e20 */
/*01e0*/ LOP3.LUT R7, R8, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108077812 */
/* 0x000fe400078ec0ff */
/*01f0*/ SEL R8, RZ, 0xffffffff, !P0 ; /* 0xffffffffff087807 */
/* 0x000fc40004000000 */
/*0200*/ ISETP.EQ.U32.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f42070 */
/*0210*/ LOP3.LUT P1, RZ, R6, 0x40000000, R4, 0x80, !PT ; /* 0x4000000006ff7812 */
/* 0x000fe20007828004 */
/*0220*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0230*/ SHF.R.U64 R5, R0, 0x1d, R9 ; /* 0x0000001d00057819 */
/* 0x000fe40000001209 */
/*0240*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P1, P2 ; /* 0x000000ffff00720c */
/* 0x000fe40004f22120 */
/*0250*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe400078ec0ff */
/*0260*/ LOP3.LUT R10, R8, 0x2, RZ, 0xe2, !PT ; /* 0x00000002080a7812 */
/* 0x000fc400078ee2ff */
/*0270*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fe40004800000 */
/*0280*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f02070 */
/*0290*/ LOP3.LUT P2, RZ, R6, 0x20000000, R4, 0x80, !PT ; /* 0x2000000006ff7812 */
/* 0x000fe40007848004 */
/*02a0*/ SHF.R.U64 R7, R0, 0x1c, R9 ; /* 0x0000001c00077819 */
/* 0x000fe40000001209 */
/*02b0*/ LOP3.LUT R10, R10, 0xfffffffd, R11, 0xf8, !PT ; /* 0xfffffffd0a0a7812 */
/* 0x000fe400078ef80b */
/*02c0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fc40005702100 */
/*02d0*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe200078ec0ff */
/*02e0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*02f0*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fe40004000000 */
/*0300*/ ISETP.EQ.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f22070 */
/*0310*/ LOP3.LUT P2, RZ, R6, 0x10000000, R4, 0x80, !PT ; /* 0x1000000006ff7812 */
/* 0x000fe40007848004 */
/*0320*/ SHF.R.U64 R5, R0, 0x1b, R9 ; /* 0x0000001b00057819 */
/* 0x000fe40000001209 */
/*0330*/ LOP3.LUT R10, R10, R11, RZ, 0xfc, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fc400078efcff */
/*0340*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40005722110 */
/*0350*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe200078ec0ff */
/*0360*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*0370*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fe40004800000 */
/*0380*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f02070 */
/*0390*/ LOP3.LUT P2, RZ, R6, 0x8000000, R4, 0x80, !PT ; /* 0x0800000006ff7812 */
/* 0x000fe40007848004 */
/*03a0*/ SHF.R.U64 R7, R0, 0x1a, R9 ; /* 0x0000001a00077819 */
/* 0x000fc40000001209 */
/*03b0*/ LOP3.LUT R10, R10, R11, RZ, 0xfc, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fe400078efcff */
/*03c0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40005702100 */
/*03d0*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe200078ec0ff */
/*03e0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*03f0*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fe40004000000 */
/*0400*/ ISETP.EQ.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f22070 */
/*0410*/ LOP3.LUT P2, RZ, R6, 0x4000000, R4, 0x80, !PT ; /* 0x0400000006ff7812 */
/* 0x000fc40007848004 */
/*0420*/ SHF.R.U64 R5, R0, 0x19, R9 ; /* 0x0000001900057819 */
/* 0x000fe40000001209 */
/*0430*/ LOP3.LUT R10, R10, R11, RZ, 0xfc, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fe400078efcff */
/*0440*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40005722110 */
/*0450*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe200078ec0ff */
/*0460*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*0470*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fe40004800000 */
/*0480*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fc40003f02070 */
/*0490*/ LOP3.LUT P2, RZ, R6, 0x2000000, R4, 0x80, !PT ; /* 0x0200000006ff7812 */
/* 0x000fe40007848004 */
/*04a0*/ SHF.R.U64 R7, R0, 0x18, R9 ; /* 0x0000001800077819 */
/* 0x000fe40000001209 */
/*04b0*/ LOP3.LUT R10, R10, R11, RZ, 0xfc, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fe400078efcff */
/*04c0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40005702100 */
/*04d0*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe200078ec0ff */
/*04e0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*04f0*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004000000 */
/*0500*/ ISETP.EQ.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f22070 */
/*0510*/ LOP3.LUT P2, RZ, R6, 0x1000000, R4, 0x80, !PT ; /* 0x0100000006ff7812 */
/* 0x000fe40007848004 */
/*0520*/ SHF.R.U64 R5, R0, 0x17, R9 ; /* 0x0000001700057819 */
/* 0x000fe40000001209 */
/*0530*/ LOP3.LUT R10, R10, R11, RZ, 0xfc, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fe400078efcff */
/*0540*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40005722110 */
/*0550*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe200078ec0ff */
/*0560*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*0570*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004800000 */
/*0580*/ SHF.R.U64 R7, R0, 0x16, R9 ; /* 0x0000001600077819 */
/* 0x000fe40000001209 */
/*0590*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f02070 */
/*05a0*/ LOP3.LUT P2, RZ, R6, 0x800000, R4, 0x80, !PT ; /* 0x0080000006ff7812 */
/* 0x000fe40007848004 */
/*05b0*/ LOP3.LUT R10, R10, R11, RZ, 0xfc, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fe400078efcff */
/*05c0*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe400078ec0ff */
/*05d0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe20005702100 */
/*05e0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*05f0*/ ISETP.EQ.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fc40003f22070 */
/*0600*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fe40004000000 */
/*0610*/ LOP3.LUT P2, RZ, R6, 0x400000, R4, 0x80, !PT ; /* 0x0040000006ff7812 */
/* 0x000fe40007848004 */
/*0620*/ SHF.R.U64 R5, R0, 0x15, R9 ; /* 0x0000001500057819 */
/* 0x000fe40000001209 */
/*0630*/ LOP3.LUT R10, R10, R7, RZ, 0xfc, !PT ; /* 0x000000070a0a7212 */
/* 0x000fe400078efcff */
/*0640*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40005722110 */
/*0650*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe200078ec0ff */
/*0660*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*0670*/ SEL R7, RZ, 0x1, !P1 ; /* 0x00000001ff077807 */
/* 0x000fc40004800000 */
/*0680*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f02070 */
/*0690*/ LOP3.LUT P2, RZ, R6, 0x200000, R4, 0x80, !PT ; /* 0x0020000006ff7812 */
/* 0x000fe40007848004 */
/*06a0*/ SHF.R.U64 R5, R0, 0x14, R9 ; /* 0x0000001400057819 */
/* 0x000fe40000001209 */
/*06b0*/ LOP3.LUT R10, R10, R7, RZ, 0xfc, !PT ; /* 0x000000070a0a7212 */
/* 0x000fe400078efcff */
/*06c0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40005702100 */
/*06d0*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe200078ec0ff */
/*06e0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*06f0*/ SEL R7, RZ, 0x1, !P0 ; /* 0x00000001ff077807 */
/* 0x000fc40004000000 */
/*0700*/ ISETP.EQ.U32.AND P1, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f22070 */
/*0710*/ LOP3.LUT P2, RZ, R6, 0x100000, R4, 0x80, !PT ; /* 0x0010000006ff7812 */
/* 0x000fe40007848004 */
/*0720*/ SHF.R.U64 R5, R0, 0x13, R9 ; /* 0x0000001300057819 */
/* 0x000fe40000001209 */
/*0730*/ LOP3.LUT R10, R10, R7, RZ, 0xfc, !PT ; /* 0x000000070a0a7212 */
/* 0x000fe400078efcff */
/*0740*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40005722110 */
/*0750*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe200078ec0ff */
/*0760*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*0770*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004800000 */
/*0780*/ ISETP.EQ.U32.AND P2, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f42070 */
/*0790*/ LOP3.LUT P0, RZ, R6, 0x80000, R4, 0x80, !PT ; /* 0x0008000006ff7812 */
/* 0x000fe40007808004 */
/*07a0*/ SHF.R.U64 R7, R0, 0x12, R9 ; /* 0x0000001200077819 */
/* 0x000fe40000001209 */
/*07b0*/ LOP3.LUT R10, R10, R11, RZ, 0xfc, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fe400078efcff */
/*07c0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P0, P2 ; /* 0x000000ffff00720c */
/* 0x000fe40004702120 */
/*07d0*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe200078ec0ff */
/*07e0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*07f0*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004000000 */
/*0800*/ SHF.R.U64 R5, R0, 0x11, R9 ; /* 0x0000001100057819 */
/* 0x000fe40000001209 */
/*0810*/ ISETP.EQ.U32.AND P2, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f42070 */
/*0820*/ LOP3.LUT P1, RZ, R6, 0x40000, R4, 0x80, !PT ; /* 0x0004000006ff7812 */
/* 0x000fe40007828004 */
/*0830*/ LOP3.LUT R10, R10, R11, RZ, 0xfc, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fe400078efcff */
/*0840*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe400078ec0ff */
/*0850*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P1, P2 ; /* 0x000000ffff00720c */
/* 0x000fe20004f22120 */
/*0860*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*0870*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fc40003f02070 */
/*0880*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fe40004800000 */
/*0890*/ LOP3.LUT R5, R6.reuse, R4, RZ, 0xc0, !PT ; /* 0x0000000406057212 */
/* 0x040fe400078ec0ff */
/*08a0*/ LOP3.LUT P2, RZ, R6, 0x20000, R4, 0x80, !PT ; /* 0x0002000006ff7812 */
/* 0x000fe40007848004 */
/*08b0*/ SHF.R.U64 R7, R0, 0x10, R9 ; /* 0x0000001000077819 */
/* 0x000fe40000001209 */
/*08c0*/ LOP3.LUT R10, R10, R11, RZ, 0xfc, !PT ; /* 0x0000000b0a0a7212 */
/* 0x000fe400078efcff */
/*08d0*/ PRMT R5, R5, 0x9910, RZ ; /* 0x0000991005057816 */
/* 0x000fc400000000ff */
/*08e0*/ ISETP.EQ.U32.AND.EX P2, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe20005742100 */
/*08f0*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*0900*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe400078ec0ff */
/*0910*/ ISETP.GT.AND P0, PT, R5, -0x1, PT ; /* 0xffffffff0500780c */
/* 0x000fe40003f04270 */
/*0920*/ SEL R5, RZ, 0x1, !P2 ; /* 0x00000001ff057807 */
/* 0x000fe40005000000 */
/*0930*/ ISETP.EQ.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f22070 */
/*0940*/ LOP3.LUT P3, RZ, R6, 0x10000, R4, 0x80, !PT ; /* 0x0001000006ff7812 */
/* 0x000fc40007868004 */
/*0950*/ LOP3.LUT R10, R10, R5, RZ, 0xfc, !PT ; /* 0x000000050a0a7212 */
/* 0x000fe400078efcff */
/*0960*/ SHF.R.U64 R8, R0.reuse, 0xe, R9 ; /* 0x0000000e00087819 */
/* 0x040fe40000001209 */
/*0970*/ PRMT R7, R0, 0x9910, RZ ; /* 0x0000991000077816 */
/* 0x000fe400000000ff */
/*0980*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P3, P1 ; /* 0x000000ffff00720c */
/* 0x000fe20005f22110 */
/*0990*/ IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a7824 */
/* 0x000fe200078e00ff */
/*09a0*/ LOP3.LUT R8, R8, 0x1, RZ, 0xc0, !PT ; /* 0x0000000108087812 */
/* 0x000fe200078ec0ff */
/*09b0*/ IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0007 */
/*09c0*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004800000 */
/*09d0*/ ISETP.EQ.U32.AND P1, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fe40003f22070 */
/*09e0*/ LOP3.LUT R8, R10, R11, RZ, 0xfc, !PT ; /* 0x0000000b0a087212 */
/* 0x000fe400078efcff */
/*09f0*/ ISETP.LT.AND P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x000fc60000701270 */
/*0a00*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0a10*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fe40004000000 */
/*0a20*/ LOP3.LUT P2, RZ, R6, 0x4000, R4, 0x80, !PT ; /* 0x0000400006ff7812 */
/* 0x000fe40007848004 */
/*0a30*/ SHF.R.U64 R7, R0, 0xd, R9 ; /* 0x0000000d00077819 */
/* 0x000fe40000001209 */
/*0a40*/ LOP3.LUT R8, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08087212 */
/* 0x000fe400078efcff */
/*0a50*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40005722110 */
/*0a60*/ LOP3.LUT R5, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107057812 */
/* 0x000fe200078ec0ff */
/*0a70*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0a80*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004800000 */
/*0a90*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f02070 */
/*0aa0*/ LOP3.LUT P2, RZ, R6, 0x2000, R4, 0x80, !PT ; /* 0x0000200006ff7812 */
/* 0x000fe40007848004 */
/*0ab0*/ SHF.R.U64 R7, R0, 0xc, R9 ; /* 0x0000000c00077819 */
/* 0x000fe40000001209 */
/*0ac0*/ LOP3.LUT R8, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08087212 */
/* 0x000fe400078efcff */
/*0ad0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40005702100 */
/*0ae0*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe200078ec0ff */
/*0af0*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0b00*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004000000 */
/*0b10*/ ISETP.EQ.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f22070 */
/*0b20*/ LOP3.LUT P2, RZ, R6, 0x1000, R4, 0x80, !PT ; /* 0x0000100006ff7812 */
/* 0x000fe40007848004 */
/*0b30*/ SHF.R.U64 R5, R0, 0xb, R9 ; /* 0x0000000b00057819 */
/* 0x000fe40000001209 */
/*0b40*/ LOP3.LUT R8, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08087212 */
/* 0x000fe400078efcff */
/*0b50*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40005722110 */
/*0b60*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe200078ec0ff */
/*0b70*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0b80*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004800000 */
/*0b90*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f02070 */
/*0ba0*/ LOP3.LUT P2, RZ, R6, 0x800, R4, 0x80, !PT ; /* 0x0000080006ff7812 */
/* 0x000fe40007848004 */
/*0bb0*/ SHF.R.U64 R7, R0, 0xa, R9 ; /* 0x0000000a00077819 */
/* 0x000fe40000001209 */
/*0bc0*/ LOP3.LUT R8, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08087212 */
/* 0x000fe400078efcff */
/*0bd0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40005702100 */
/*0be0*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe200078ec0ff */
/*0bf0*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0c00*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004000000 */
/*0c10*/ ISETP.EQ.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f22070 */
/*0c20*/ LOP3.LUT P2, RZ, R6, 0x400, R4, 0x80, !PT ; /* 0x0000040006ff7812 */
/* 0x000fe40007848004 */
/*0c30*/ SHF.R.U64 R5, R0, 0x9, R9 ; /* 0x0000000900057819 */
/* 0x000fe40000001209 */
/*0c40*/ LOP3.LUT R8, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08087212 */
/* 0x000fe400078efcff */
/*0c50*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40005722110 */
/*0c60*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe200078ec0ff */
/*0c70*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0c80*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004800000 */
/*0c90*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f02070 */
/*0ca0*/ LOP3.LUT P2, RZ, R6, 0x200, R4, 0x80, !PT ; /* 0x0000020006ff7812 */
/* 0x000fe40007848004 */
/*0cb0*/ SHF.R.U64 R7, R0, 0x8, R9 ; /* 0x0000000800077819 */
/* 0x000fe40000001209 */
/*0cc0*/ LOP3.LUT R8, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08087212 */
/* 0x000fe400078efcff */
/*0cd0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40005702100 */
/*0ce0*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe200078ec0ff */
/*0cf0*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0d00*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004000000 */
/*0d10*/ ISETP.EQ.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f22070 */
/*0d20*/ LOP3.LUT P2, RZ, R6, 0x100, R4, 0x80, !PT ; /* 0x0000010006ff7812 */
/* 0x000fe40007848004 */
/*0d30*/ SHF.R.U64 R5, R0, 0x7, R9 ; /* 0x0000000700057819 */
/* 0x000fe40000001209 */
/*0d40*/ LOP3.LUT R8, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08087212 */
/* 0x000fe400078efcff */
/*0d50*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40005722110 */
/*0d60*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe200078ec0ff */
/*0d70*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0d80*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004800000 */
/*0d90*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f02070 */
/*0da0*/ LOP3.LUT P2, RZ, R6, 0x80, R4, 0x80, !PT ; /* 0x0000008006ff7812 */
/* 0x000fe40007848004 */
/*0db0*/ SHF.R.U64 R7, R0, 0x6, R9 ; /* 0x0000000600077819 */
/* 0x000fe40000001209 */
/*0dc0*/ LOP3.LUT R8, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08087212 */
/* 0x000fe400078efcff */
/*0dd0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40005702100 */
/*0de0*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe200078ec0ff */
/*0df0*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0e00*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc40004000000 */
/*0e10*/ ISETP.EQ.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f22070 */
/*0e20*/ LOP3.LUT P2, RZ, R6, 0x40, R4, 0x80, !PT ; /* 0x0000004006ff7812 */
/* 0x000fe40007848004 */
/*0e30*/ SHF.R.U64 R5, R0, 0x5, R9.reuse ; /* 0x0000000500057819 */
/* 0x100fe40000001209 */
/*0e40*/ LOP3.LUT R8, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08087212 */
/* 0x000fe400078efcff */
/*0e50*/ SHF.R.U64 R7, R0, 0x4, R9 ; /* 0x0000000400077819 */
/* 0x000fe40000001209 */
/*0e60*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe20005722110 */
/*0e70*/ IMAD.SHL.U32 R8, R8, 0x2, RZ ; /* 0x0000000208087824 */
/* 0x000fe200078e00ff */
/*0e80*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fc400078ec0ff */
/*0e90*/ LOP3.LUT R7, R7, 0x1, RZ, 0xc0, !PT ; /* 0x0000000107077812 */
/* 0x000fe400078ec0ff */
/*0ea0*/ SEL R11, RZ, 0x1, !P1 ; /* 0x00000001ff0b7807 */
/* 0x000fe40004800000 */
/*0eb0*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f02070 */
/*0ec0*/ LOP3.LUT P2, RZ, R6, 0x20, R4, 0x80, !PT ; /* 0x0000002006ff7812 */
/* 0x000fe40007848004 */
/*0ed0*/ ISETP.EQ.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fe40003f22070 */
/*0ee0*/ LOP3.LUT R7, R8, R11, RZ, 0xfc, !PT ; /* 0x0000000b08077212 */
/* 0x000fc400078efcff */
/*0ef0*/ SHF.R.U64 R5, R0, 0x3, R9 ; /* 0x0000000300057819 */
/* 0x000fe40000001209 */
/*0f00*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe20005702100 */
/*0f10*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0f20*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe400078ec0ff */
/*0f30*/ SEL R8, RZ, 0x1, !P0 ; /* 0x00000001ff087807 */
/* 0x000fe40004000000 */
/*0f40*/ LOP3.LUT P2, RZ, R6, 0x10, R4, 0x80, !PT ; /* 0x0000001006ff7812 */
/* 0x000fe40007848004 */
/*0f50*/ ISETP.EQ.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fc40003f02070 */
/*0f60*/ LOP3.LUT R7, R7, R8, RZ, 0xfc, !PT ; /* 0x0000000807077212 */
/* 0x000fe400078efcff */
/*0f70*/ SHF.R.U64 R5, R0, 0x2, R9 ; /* 0x0000000200057819 */
/* 0x000fe40000001209 */
/*0f80*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe20005722110 */
/*0f90*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fe200078e00ff */
/*0fa0*/ LOP3.LUT R5, R5, 0x1, RZ, 0xc0, !PT ; /* 0x0000000105057812 */
/* 0x000fe400078ec0ff */
/*0fb0*/ SEL R8, RZ, 0x1, !P1 ; /* 0x00000001ff087807 */
/* 0x000fe40004800000 */
/*0fc0*/ LOP3.LUT P2, RZ, R6, 0x8, R4, 0x80, !PT ; /* 0x0000000806ff7812 */
/* 0x000fc40007848004 */
/*0fd0*/ ISETP.EQ.U32.AND P1, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fe40003f22070 */
/*0fe0*/ LOP3.LUT R5, R7, R8, RZ, 0xfc, !PT ; /* 0x0000000807057212 */
/* 0x000fe400078efcff */
/*0ff0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fc60005702100 */
/*1000*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*1010*/ SEL R8, RZ, 0x1, !P0 ; /* 0x00000001ff087807 */
/* 0x000fe40004000000 */
/*1020*/ SHF.R.U64 R0, R0, 0x1, R9 ; /* 0x0000000100007819 */
/* 0x000fe40000001209 */
/*1030*/ LOP3.LUT P2, RZ, R6, 0x4, R4, 0x80, !PT ; /* 0x0000000406ff7812 */
/* 0x000fe40007848004 */
/*1040*/ LOP3.LUT R5, R5, R8, RZ, 0xfc, !PT ; /* 0x0000000805057212 */
/* 0x000fe400078efcff */
/*1050*/ LOP3.LUT R0, R0, 0x1, RZ, 0xc0, !PT ; /* 0x0000000100007812 */
/* 0x000fe400078ec0ff */
/*1060*/ ISETP.EQ.U32.AND.EX P1, PT, RZ, RZ, !P2, P1 ; /* 0x000000ffff00720c */
/* 0x000fe20005722110 */
/*1070*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*1080*/ ISETP.EQ.U32.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc40003f02070 */
/*1090*/ SEL R0, RZ, 0x1, !P1 ; /* 0x00000001ff007807 */
/* 0x000fe40004800000 */
/*10a0*/ LOP3.LUT P2, RZ, R6.reuse, 0x2, R4.reuse, 0x80, !PT ; /* 0x0000000206ff7812 */
/* 0x140fe40007848004 */
/*10b0*/ LOP3.LUT R7, R6.reuse, 0x1, R4.reuse, 0x80, !PT ; /* 0x0000000106077812 */
/* 0x140fe400078e8004 */
/*10c0*/ LOP3.LUT R5, R5, R0, RZ, 0xfc, !PT ; /* 0x0000000005057212 */
/* 0x000fe400078efcff */
/*10d0*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, !P2, P0 ; /* 0x000000ffff00720c */
/* 0x000fe40005702100 */
/*10e0*/ LOP3.LUT R4, R6, 0x1, R4, 0xc8, !PT ; /* 0x0000000106047812 */
/* 0x000fe200078ec804 */
/*10f0*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*1100*/ ISETP.NE.U32.AND P1, PT, R7, 0x1, PT ; /* 0x000000010700780c */
/* 0x000fc40003f25070 */
/*1110*/ SEL R0, RZ, 0x1, !P0 ; /* 0x00000001ff007807 */
/* 0x000fe40004000000 */
/*1120*/ ISETP.EQ.U32.AND P2, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe40003f42070 */
/*1130*/ ISETP.NE.U32.AND.EX P1, PT, RZ, RZ, PT, P1 ; /* 0x000000ffff00720c */
/* 0x000fe40003f25110 */
/*1140*/ LOP3.LUT R5, R5, R0, RZ, 0xfc, !PT ; /* 0x0000000005057212 */
/* 0x000fe400078efcff */
/*1150*/ ISETP.EQ.U32.AND.EX P0, PT, RZ, RZ, P1, P2 ; /* 0x000000ffff00720c */
/* 0x000fc60000f02120 */
/*1160*/ IMAD.SHL.U32 R5, R5, 0x2, RZ ; /* 0x0000000205057824 */
/* 0x000fe200078e00ff */
/*1170*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*1180*/ LOP3.LUT R4, R4, 0xfffffffe, R5, 0xf8, !PT ; /* 0xfffffffe04047812 */
/* 0x000fe200078ef805 */
/*1190*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fca00078e00ff */
/*11a0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*11b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*11c0*/ BRA 0x11c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*11d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*11f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
cudaError err = cudaGetLastError();\
if( err != cudaSuccess){\
printf("Cuda Error: '%s' for %s\n", cudaGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__device__ unsigned int exor(unsigned long a,unsigned long b)
{
unsigned int res;
for (int i = 63; i >= 0; i--)
{
// Find current bits in x and y
bool b1 = a & (1 << i);
bool b2 = b & (1 << i);
// If both are 1 then 0 else xor is same as OR
bool xoredBit = (b1 & b2) ? 0 : (b1 | b2);
// Update result
res <<= 1;
res |= xoredBit;
}
//res=exor(a,b);
return res;
}
__global__ void calculate(unsigned long *mem,int num,int iter)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i >= num)
return;
// unsigned long *t1,*t2;
if(i<num/2){
int tmp=i*2;
if(tmp+iter<num)
mem[tmp]=exor(mem[tmp],mem[tmp+iter]);
// else
// mem[tmp]=exor(mem[tmp],0);
// mem[num]=res;
}
}
int main(int argc, char **argv){
struct timeval start, end, t_start, t_end;
int i,blocks=0;
unsigned long *p1,*g1;
unsigned long seed,num;
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
seed=atoi(argv[2]);
}
// printf("%d",time(0));
p1 = (unsigned long *)malloc((num+1) *sizeof(unsigned long));
srand(seed);
for(i=0; i<num; ++i){
p1[i]=random();
// printf("%d %lu\n",i,p1[i]);
}
p1[i]=0;
gettimeofday(&t_start, NULL);
//for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
cudaMalloc(&g1, (num+1) * sizeof(unsigned long));
CUDA_ERROR_EXIT("cudaMalloc");
cudaMemcpy(g1, p1, (num+1) * sizeof(unsigned long) , cudaMemcpyHostToDevice);
CUDA_ERROR_EXIT("cudaMemcpy");
gettimeofday(&start, NULL);
blocks = num /1024;
if(num % 1024)
++blocks;
for(i=0;i<log(num)/log(2);i++){
calculate<<<blocks,1024>>>(g1,num,(int)pow(2,i));
}
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
/* Copy back result*/
cudaMemcpy(p1, g1, (num+1) * sizeof(unsigned long), cudaMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
// for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
printf("%lu",p1[0]);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
cudaFree(g1);
/*Print the last element for sanity check*/
printf("The XOR final value is %lu",p1[num]);
free(p1);
// free(pfinal);
return 0;
} | .file "tmpxft_0004184e_00000000-6_qn2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4exormm
.type _Z4exormm, @function
_Z4exormm:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z4exormm, .-_Z4exormm
.globl _Z30__device_stub__Z9calculatePmiiPmii
.type _Z30__device_stub__Z9calculatePmiiPmii, @function
_Z30__device_stub__Z9calculatePmiiPmii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9calculatePmii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z9calculatePmiiPmii, .-_Z30__device_stub__Z9calculatePmiiPmii
.globl _Z9calculatePmii
.type _Z9calculatePmii, @function
_Z9calculatePmii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9calculatePmiiPmii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9calculatePmii, .-_Z9calculatePmii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMalloc"
.LC1:
.string "Cuda Error: '%s' for %s\n"
.LC2:
.string "cudaMemcpy"
.LC5:
.string "kernel invocation"
.LC6:
.string "memcpy"
.LC7:
.string "%lu"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Total time = %ld microsecs Processsing =%ld microsecs\n"
.section .rodata.str1.1
.LC9:
.string "The XOR final value is %lu"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $3, %edi
je .L31
.L14:
leaq 8(,%rbx,8), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movl %r13d, %edi
call srand@PLT
movl $0, %ebp
.L16:
call random@PLT
movq %rax, (%r12,%rbp,8)
addq $1, %rbp
cmpq %rbx, %rbp
jne .L16
leaq -8(%r12,%r14), %rax
movq %rax, 24(%rsp)
movq $0, (%rax)
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L33
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq %rbx, %r13
shrq $10, %r13
movq %rbx, %rax
andl $1023, %eax
cmpq $1, %rax
sbbl $-1, %r13d
movl $0, %ebp
movq %rbx, %r15
andl $1, %r15d
movl %ebx, 20(%rsp)
jmp .L20
.L31:
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbx
testq %rbx, %rbx
jne .L15
movl $10000000, %ebx
.L15:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r13
jmp .L14
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
movsd 8(%rsp), %xmm1
movsd .LC3(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %edx
movl 20(%rsp), %esi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z9calculatePmiiPmii
jmp .L21
.L22:
movq %rbx, %rax
shrq %rax
orq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
.L23:
call log@PLT
divsd .LC4(%rip), %xmm0
comisd 8(%rsp), %xmm0
jbe .L34
movl $1024, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %r13d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L21:
addl $1, %ebp
.L20:
pxor %xmm2, %xmm2
cvtsi2sdl %ebp, %xmm2
movsd %xmm2, 8(%rsp)
testq %rbx, %rbx
js .L22
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
jmp .L23
.L34:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L36
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movq %r14, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq (%r12), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 64(%rsp), %rcx
subq 48(%rsp), %rcx
imulq $1000000, %rcx, %rcx
addq 72(%rsp), %rcx
subq 56(%rsp), %rcx
movq 96(%rsp), %rdx
subq 80(%rsp), %rdx
imulq $1000000, %rdx, %rdx
addq 104(%rsp), %rdx
subq 88(%rsp), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
movq (%rax), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z9calculatePmii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9calculatePmii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1073741824
.align 8
.LC4:
.long -17155601
.long 1072049730
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
cudaError err = cudaGetLastError();\
if( err != cudaSuccess){\
printf("Cuda Error: '%s' for %s\n", cudaGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__device__ unsigned int exor(unsigned long a,unsigned long b)
{
unsigned int res;
for (int i = 63; i >= 0; i--)
{
// Find current bits in x and y
bool b1 = a & (1 << i);
bool b2 = b & (1 << i);
// If both are 1 then 0 else xor is same as OR
bool xoredBit = (b1 & b2) ? 0 : (b1 | b2);
// Update result
res <<= 1;
res |= xoredBit;
}
//res=exor(a,b);
return res;
}
__global__ void calculate(unsigned long *mem,int num,int iter)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i >= num)
return;
// unsigned long *t1,*t2;
if(i<num/2){
int tmp=i*2;
if(tmp+iter<num)
mem[tmp]=exor(mem[tmp],mem[tmp+iter]);
// else
// mem[tmp]=exor(mem[tmp],0);
// mem[num]=res;
}
}
int main(int argc, char **argv){
struct timeval start, end, t_start, t_end;
int i,blocks=0;
unsigned long *p1,*g1;
unsigned long seed,num;
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
seed=atoi(argv[2]);
}
// printf("%d",time(0));
p1 = (unsigned long *)malloc((num+1) *sizeof(unsigned long));
srand(seed);
for(i=0; i<num; ++i){
p1[i]=random();
// printf("%d %lu\n",i,p1[i]);
}
p1[i]=0;
gettimeofday(&t_start, NULL);
//for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
cudaMalloc(&g1, (num+1) * sizeof(unsigned long));
CUDA_ERROR_EXIT("cudaMalloc");
cudaMemcpy(g1, p1, (num+1) * sizeof(unsigned long) , cudaMemcpyHostToDevice);
CUDA_ERROR_EXIT("cudaMemcpy");
gettimeofday(&start, NULL);
blocks = num /1024;
if(num % 1024)
++blocks;
for(i=0;i<log(num)/log(2);i++){
calculate<<<blocks,1024>>>(g1,num,(int)pow(2,i));
}
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
/* Copy back result*/
cudaMemcpy(p1, g1, (num+1) * sizeof(unsigned long), cudaMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
// for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
printf("%lu",p1[0]);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
cudaFree(g1);
/*Print the last element for sanity check*/
printf("The XOR final value is %lu",p1[num]);
free(p1);
// free(pfinal);
return 0;
} | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
hipError_t err = hipGetLastError();\
if( err != hipSuccess){\
printf("Cuda Error: '%s' for %s\n", hipGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__device__ unsigned int exor(unsigned long a,unsigned long b)
{
unsigned int res;
for (int i = 63; i >= 0; i--)
{
// Find current bits in x and y
bool b1 = a & (1 << i);
bool b2 = b & (1 << i);
// If both are 1 then 0 else xor is same as OR
bool xoredBit = (b1 & b2) ? 0 : (b1 | b2);
// Update result
res <<= 1;
res |= xoredBit;
}
//res=exor(a,b);
return res;
}
__global__ void calculate(unsigned long *mem,int num,int iter)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i >= num)
return;
// unsigned long *t1,*t2;
if(i<num/2){
int tmp=i*2;
if(tmp+iter<num)
mem[tmp]=exor(mem[tmp],mem[tmp+iter]);
// else
// mem[tmp]=exor(mem[tmp],0);
// mem[num]=res;
}
}
int main(int argc, char **argv){
struct timeval start, end, t_start, t_end;
int i,blocks=0;
unsigned long *p1,*g1;
unsigned long seed,num;
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
seed=atoi(argv[2]);
}
// printf("%d",time(0));
p1 = (unsigned long *)malloc((num+1) *sizeof(unsigned long));
srand(seed);
for(i=0; i<num; ++i){
p1[i]=random();
// printf("%d %lu\n",i,p1[i]);
}
p1[i]=0;
gettimeofday(&t_start, NULL);
//for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
hipMalloc(&g1, (num+1) * sizeof(unsigned long));
CUDA_ERROR_EXIT("hipMalloc");
hipMemcpy(g1, p1, (num+1) * sizeof(unsigned long) , hipMemcpyHostToDevice);
CUDA_ERROR_EXIT("hipMemcpy");
gettimeofday(&start, NULL);
blocks = num /1024;
if(num % 1024)
++blocks;
for(i=0;i<log(num)/log(2);i++){
calculate<<<blocks,1024>>>(g1,num,(int)pow(2,i));
}
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
/* Copy back result*/
hipMemcpy(p1, g1, (num+1) * sizeof(unsigned long), hipMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
// for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
printf("%lu",p1[0]);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
hipFree(g1);
/*Print the last element for sanity check*/
printf("The XOR final value is %lu",p1[num]);
free(p1);
// free(pfinal);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
hipError_t err = hipGetLastError();\
if( err != hipSuccess){\
printf("Cuda Error: '%s' for %s\n", hipGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__device__ unsigned int exor(unsigned long a,unsigned long b)
{
unsigned int res;
for (int i = 63; i >= 0; i--)
{
// Find current bits in x and y
bool b1 = a & (1 << i);
bool b2 = b & (1 << i);
// If both are 1 then 0 else xor is same as OR
bool xoredBit = (b1 & b2) ? 0 : (b1 | b2);
// Update result
res <<= 1;
res |= xoredBit;
}
//res=exor(a,b);
return res;
}
__global__ void calculate(unsigned long *mem,int num,int iter)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i >= num)
return;
// unsigned long *t1,*t2;
if(i<num/2){
int tmp=i*2;
if(tmp+iter<num)
mem[tmp]=exor(mem[tmp],mem[tmp+iter]);
// else
// mem[tmp]=exor(mem[tmp],0);
// mem[num]=res;
}
}
int main(int argc, char **argv){
struct timeval start, end, t_start, t_end;
int i,blocks=0;
unsigned long *p1,*g1;
unsigned long seed,num;
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
seed=atoi(argv[2]);
}
// printf("%d",time(0));
p1 = (unsigned long *)malloc((num+1) *sizeof(unsigned long));
srand(seed);
for(i=0; i<num; ++i){
p1[i]=random();
// printf("%d %lu\n",i,p1[i]);
}
p1[i]=0;
gettimeofday(&t_start, NULL);
//for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
hipMalloc(&g1, (num+1) * sizeof(unsigned long));
CUDA_ERROR_EXIT("hipMalloc");
hipMemcpy(g1, p1, (num+1) * sizeof(unsigned long) , hipMemcpyHostToDevice);
CUDA_ERROR_EXIT("hipMemcpy");
gettimeofday(&start, NULL);
blocks = num /1024;
if(num % 1024)
++blocks;
for(i=0;i<log(num)/log(2);i++){
calculate<<<blocks,1024>>>(g1,num,(int)pow(2,i));
}
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
/* Copy back result*/
hipMemcpy(p1, g1, (num+1) * sizeof(unsigned long), hipMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
// for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
printf("%lu",p1[0]);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
hipFree(g1);
/*Print the last element for sanity check*/
printf("The XOR final value is %lu",p1[num]);
free(p1);
// free(pfinal);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9calculatePmii
.globl _Z9calculatePmii
.p2align 8
.type _Z9calculatePmii,@function
_Z9calculatePmii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_lshr_b32 s3, s2, 31
s_add_i32 s3, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_ashr_i32 s3, s3, 1
s_min_i32 s3, s2, s3
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b32 s3, s[0:1], 0xc
v_lshlrev_b32_e32 v2, 1, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s3, v2
v_cmp_gt_i32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_5
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[2:3]
v_lshlrev_b64 v[4:5], 3, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s1, 63
s_clause 0x1
global_load_b64 v[2:3], v[0:1], off
global_load_b64 v[5:6], v[4:5], off
.p2align 6
.LBB0_3:
s_lshl_b32 s0, 1, s1
s_add_i32 s1, s1, -1
s_ashr_i32 s2, s0, 31
s_waitcnt vmcnt(1)
v_and_b32_e32 v7, s0, v2
v_and_b32_e32 v8, s2, v3
s_waitcnt vmcnt(0)
v_and_b32_e32 v9, s0, v5
v_and_b32_e32 v10, s2, v6
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_ne_u64_e32 vcc_lo, 0, v[7:8]
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
v_cmp_ne_u64_e32 vcc_lo, 0, v[9:10]
v_cndmask_b32_e64 v8, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_and_b32_e32 v9, v7, v8
v_or_b32_e32 v7, v7, v8
v_cmp_eq_u32_e32 vcc_lo, 0, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ne_u32_e64 s0, 0, v7
s_and_b32 s0, vcc_lo, s0
s_cmp_lg_u32 s1, -1
v_cndmask_b32_e64 v7, 0, 1, s0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_or_b32 v4, v4, 1, v7
s_cbranch_scc1 .LBB0_3
v_mov_b32_e32 v5, 0
global_store_b64 v[0:1], v[4:5], off
.LBB0_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9calculatePmii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9calculatePmii, .Lfunc_end0-_Z9calculatePmii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9calculatePmii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9calculatePmii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>
#include<math.h>
#define NUM 10000000
#define CUDA_ERROR_EXIT(str) do{\
hipError_t err = hipGetLastError();\
if( err != hipSuccess){\
printf("Cuda Error: '%s' for %s\n", hipGetErrorString(err), str);\
exit(-1);\
}\
}while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))
__device__ unsigned int exor(unsigned long a,unsigned long b)
{
unsigned int res;
for (int i = 63; i >= 0; i--)
{
// Find current bits in x and y
bool b1 = a & (1 << i);
bool b2 = b & (1 << i);
// If both are 1 then 0 else xor is same as OR
bool xoredBit = (b1 & b2) ? 0 : (b1 | b2);
// Update result
res <<= 1;
res |= xoredBit;
}
//res=exor(a,b);
return res;
}
__global__ void calculate(unsigned long *mem,int num,int iter)
{
int i = blockDim.x * blockIdx.x + threadIdx.x;
if(i >= num)
return;
// unsigned long *t1,*t2;
if(i<num/2){
int tmp=i*2;
if(tmp+iter<num)
mem[tmp]=exor(mem[tmp],mem[tmp+iter]);
// else
// mem[tmp]=exor(mem[tmp],0);
// mem[num]=res;
}
}
int main(int argc, char **argv){
struct timeval start, end, t_start, t_end;
int i,blocks=0;
unsigned long *p1,*g1;
unsigned long seed,num;
if(argc == 3){
num = atoi(argv[1]); /*Update after checking*/
if(num <= 0)
num = NUM;
seed=atoi(argv[2]);
}
// printf("%d",time(0));
p1 = (unsigned long *)malloc((num+1) *sizeof(unsigned long));
srand(seed);
for(i=0; i<num; ++i){
p1[i]=random();
// printf("%d %lu\n",i,p1[i]);
}
p1[i]=0;
gettimeofday(&t_start, NULL);
//for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
hipMalloc(&g1, (num+1) * sizeof(unsigned long));
CUDA_ERROR_EXIT("hipMalloc");
hipMemcpy(g1, p1, (num+1) * sizeof(unsigned long) , hipMemcpyHostToDevice);
CUDA_ERROR_EXIT("hipMemcpy");
gettimeofday(&start, NULL);
blocks = num /1024;
if(num % 1024)
++blocks;
for(i=0;i<log(num)/log(2);i++){
calculate<<<blocks,1024>>>(g1,num,(int)pow(2,i));
}
CUDA_ERROR_EXIT("kernel invocation");
gettimeofday(&end, NULL);
/* Copy back result*/
hipMemcpy(p1, g1, (num+1) * sizeof(unsigned long), hipMemcpyDeviceToHost);
CUDA_ERROR_EXIT("memcpy");
gettimeofday(&t_end, NULL);
// for(i=0;i<num;i++)
// printf("%d-%lu\n",i,p1[i]);
printf("%lu",p1[0]);
printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
hipFree(g1);
/*Print the last element for sanity check*/
printf("The XOR final value is %lu",p1[num]);
free(p1);
// free(pfinal);
return 0;
} | .text
.file "qn2.hip"
.globl _Z24__device_stub__calculatePmii # -- Begin function _Z24__device_stub__calculatePmii
.p2align 4, 0x90
.type _Z24__device_stub__calculatePmii,@function
_Z24__device_stub__calculatePmii: # @_Z24__device_stub__calculatePmii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9calculatePmii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__calculatePmii, .Lfunc_end0-_Z24__device_stub__calculatePmii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3fe62e42fefa39ef # double 0.69314718055994529
.LCPI1_3:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
movl $10000000, %r13d # imm = 0x989680
cmovnel %eax, %r13d
movslq %r13d, %r12
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
leaq 8(,%r12,8), %rdi
movq %rdi, 24(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movl %r14d, %edi
callq srand
cmpl $1, %r12d
movl %r12d, %r14d
adcl $0, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq random
movq %rax, (%rbx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB1_1
# %bb.2:
movq $0, (%rbx,%r15,8)
leaq 128(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 8(%rsp), %rdi
movq 24(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_3
# %bb.5:
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.7:
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %r12, 72(%rsp) # 8-byte Spill
movq %r12, %xmm1
punpckldq .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movapd %xmm0, 160(%rsp) # 16-byte Spill
callq log
divsd .LCPI1_2(%rip), %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jbe .LBB1_12
# %bb.8: # %.lr.ph
movabsq $4294967296, %r15 # imm = 0x100000000
movl %r13d, %eax
andl $1023, %eax # imm = 0x3FF
movl %r13d, %r12d
sarl $10, %r12d
cmpq $1, %rax
sbbl $-1, %r12d
orq %r15, %r12
movl $1, %r14d
addq $1024, %r15 # imm = 0x400
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movapd 160(%rsp), %xmm0 # 16-byte Reload
callq log
divsd .LCPI1_2(%rip), %xmm0
incl %r14d
ucomisd 80(%rsp), %xmm0 # 8-byte Folded Reload
jbe .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
leal -1(%r14), %edi
movq 8(%rsp), %rbp
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
callq ldexp@PLT
cvttsd2si %xmm0, %eax
movq %rbp, 120(%rsp)
movl %r13d, 20(%rsp)
movl %eax, 16(%rsp)
leaq 120(%rsp), %rax
movq %rax, 48(%rsp)
leaq 20(%rsp), %rax
movq %rax, 56(%rsp)
leaq 16(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z9calculatePmii, %edi
leaq 48(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_11
.LBB1_12: # %._crit_edge
callq hipGetLastError
testl %eax, %eax
jne .LBB1_13
# %bb.14:
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq 24(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
movq 72(%rsp), %r14 # 8-byte Reload
jne .LBB1_15
# %bb.16:
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rbx), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rax
movq 40(%rsp), %rsi
subq 128(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 136(%rsp), %rsi
addq %rax, %rsi
movq 48(%rsp), %rax
movq 56(%rsp), %rdx
subq 144(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 152(%rsp), %rdx
addq %rax, %rdx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rbx,%r14,8), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 240
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
jmp .LBB1_4
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %edx
jmp .LBB1_4
.LBB1_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.3, %edx
jmp .LBB1_4
.LBB1_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.4, %edx
.LBB1_4:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9calculatePmii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9calculatePmii,@object # @_Z9calculatePmii
.section .rodata,"a",@progbits
.globl _Z9calculatePmii
.p2align 3, 0x0
_Z9calculatePmii:
.quad _Z24__device_stub__calculatePmii
.size _Z9calculatePmii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda Error: '%s' for %s\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMemcpy"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "kernel invocation"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "memcpy"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%lu"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total time = %ld microsecs Processsing =%ld microsecs\n"
.size .L.str.6, 55
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "The XOR final value is %lu"
.size .L.str.7, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9calculatePmii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__calculatePmii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9calculatePmii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004184e_00000000-6_qn2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4exormm
.type _Z4exormm, @function
_Z4exormm:
.LFB2057:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2057:
.size _Z4exormm, .-_Z4exormm
.globl _Z30__device_stub__Z9calculatePmiiPmii
.type _Z30__device_stub__Z9calculatePmiiPmii, @function
_Z30__device_stub__Z9calculatePmiiPmii:
.LFB2084:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9calculatePmii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z30__device_stub__Z9calculatePmiiPmii, .-_Z30__device_stub__Z9calculatePmiiPmii
.globl _Z9calculatePmii
.type _Z9calculatePmii, @function
_Z9calculatePmii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9calculatePmiiPmii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z9calculatePmii, .-_Z9calculatePmii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "cudaMalloc"
.LC1:
.string "Cuda Error: '%s' for %s\n"
.LC2:
.string "cudaMemcpy"
.LC5:
.string "kernel invocation"
.LC6:
.string "memcpy"
.LC7:
.string "%lu"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Total time = %ld microsecs Processsing =%ld microsecs\n"
.section .rodata.str1.1
.LC9:
.string "The XOR final value is %lu"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
cmpl $3, %edi
je .L31
.L14:
leaq 8(,%rbx,8), %r14
movq %r14, %rdi
call malloc@PLT
movq %rax, %r12
movl %r13d, %edi
call srand@PLT
movl $0, %ebp
.L16:
call random@PLT
movq %rax, (%r12,%rbp,8)
addq $1, %rbp
cmpq %rbx, %rbp
jne .L16
leaq -8(%r12,%r14), %rax
movq %rax, 24(%rsp)
movq $0, (%rax)
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 40(%rsp), %rdi
movq %r14, %rsi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
movl $1, %ecx
movq %r14, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L33
leaq 48(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq %rbx, %r13
shrq $10, %r13
movq %rbx, %rax
andl $1023, %eax
cmpq $1, %rax
sbbl $-1, %r13d
movl $0, %ebp
movq %rbx, %r15
andl $1, %r15d
movl %ebx, 20(%rsp)
jmp .L20
.L31:
movq %rsi, %rbp
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %rbx
testq %rbx, %rbx
jne .L15
movl $10000000, %ebx
.L15:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movslq %eax, %r13
jmp .L14
.L32:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L33:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC2(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L35:
movsd 8(%rsp), %xmm1
movsd .LC3(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %edx
movl 20(%rsp), %esi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z9calculatePmiiPmii
jmp .L21
.L22:
movq %rbx, %rax
shrq %rax
orq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
addsd %xmm0, %xmm0
.L23:
call log@PLT
divsd .LC4(%rip), %xmm0
comisd 8(%rsp), %xmm0
jbe .L34
movl $1024, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %r13d, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L21:
addl $1, %ebp
.L20:
pxor %xmm2, %xmm2
cvtsi2sdl %ebp, %xmm2
movsd %xmm2, 8(%rsp)
testq %rbx, %rbx
js .L22
pxor %xmm0, %xmm0
cvtsi2sdq %rbx, %xmm0
jmp .L23
.L34:
call cudaGetLastError@PLT
testl %eax, %eax
jne .L36
leaq 64(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl $2, %ecx
movq %r14, %rdx
movq 40(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L37
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq (%r12), %rdx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 64(%rsp), %rcx
subq 48(%rsp), %rcx
imulq $1000000, %rcx, %rcx
addq 72(%rsp), %rcx
subq 56(%rsp), %rcx
movq 96(%rsp), %rdx
subq 80(%rsp), %rdx
imulq $1000000, %rdx, %rdx
addq 104(%rsp), %rdx
subq 88(%rsp), %rdx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
movq (%rax), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r12, %rdi
call free@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC5(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L37:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC6(%rip), %rcx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z9calculatePmii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z9calculatePmii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1073741824
.align 8
.LC4:
.long -17155601
.long 1072049730
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "qn2.hip"
.globl _Z24__device_stub__calculatePmii # -- Begin function _Z24__device_stub__calculatePmii
.p2align 4, 0x90
.type _Z24__device_stub__calculatePmii,@function
_Z24__device_stub__calculatePmii: # @_Z24__device_stub__calculatePmii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9calculatePmii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__calculatePmii, .Lfunc_end0-_Z24__device_stub__calculatePmii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI1_0:
.long 1127219200 # 0x43300000
.long 1160773632 # 0x45300000
.long 0 # 0x0
.long 0 # 0x0
.LCPI1_1:
.quad 0x4330000000000000 # double 4503599627370496
.quad 0x4530000000000000 # double 1.9342813113834067E+25
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3fe62e42fefa39ef # double 0.69314718055994529
.LCPI1_3:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $184, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq 8(%rsi), %rdi
xorl %r15d, %r15d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
testl %eax, %eax
movl $10000000, %r13d # imm = 0x989680
cmovnel %eax, %r13d
movslq %r13d, %r12
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
leaq 8(,%r12,8), %rdi
movq %rdi, 24(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movl %r14d, %edi
callq srand
cmpl $1, %r12d
movl %r12d, %r14d
adcl $0, %r14d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq random
movq %rax, (%rbx,%r15,8)
incq %r15
cmpq %r15, %r14
jne .LBB1_1
# %bb.2:
movq $0, (%rbx,%r15,8)
leaq 128(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
leaq 8(%rsp), %rdi
movq 24(%rsp), %r14 # 8-byte Reload
movq %r14, %rsi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB1_3
# %bb.5:
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB1_6
# %bb.7:
leaq 144(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq %r12, 72(%rsp) # 8-byte Spill
movq %r12, %xmm1
punpckldq .LCPI1_0(%rip), %xmm1 # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
subpd .LCPI1_1(%rip), %xmm1
movapd %xmm1, %xmm0
unpckhpd %xmm1, %xmm0 # xmm0 = xmm0[1],xmm1[1]
addsd %xmm1, %xmm0
movapd %xmm0, 160(%rsp) # 16-byte Spill
callq log
divsd .LCPI1_2(%rip), %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jbe .LBB1_12
# %bb.8: # %.lr.ph
movabsq $4294967296, %r15 # imm = 0x100000000
movl %r13d, %eax
andl $1023, %eax # imm = 0x3FF
movl %r13d, %r12d
sarl $10, %r12d
cmpq $1, %rax
sbbl $-1, %r12d
orq %r15, %r12
movl $1, %r14d
addq $1024, %r15 # imm = 0x400
jmp .LBB1_9
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_9 Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r14d, %xmm0
movsd %xmm0, 80(%rsp) # 8-byte Spill
movapd 160(%rsp), %xmm0 # 16-byte Reload
callq log
divsd .LCPI1_2(%rip), %xmm0
incl %r14d
ucomisd 80(%rsp), %xmm0 # 8-byte Folded Reload
jbe .LBB1_12
.LBB1_9: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.10: # in Loop: Header=BB1_9 Depth=1
leal -1(%r14), %edi
movq 8(%rsp), %rbp
movsd .LCPI1_3(%rip), %xmm0 # xmm0 = mem[0],zero
callq ldexp@PLT
cvttsd2si %xmm0, %eax
movq %rbp, 120(%rsp)
movl %r13d, 20(%rsp)
movl %eax, 16(%rsp)
leaq 120(%rsp), %rax
movq %rax, 48(%rsp)
leaq 20(%rsp), %rax
movq %rax, 56(%rsp)
leaq 16(%rsp), %rax
movq %rax, 64(%rsp)
leaq 32(%rsp), %rdi
leaq 104(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 104(%rsp), %rcx
movl 112(%rsp), %r8d
movl $_Z9calculatePmii, %edi
leaq 48(%rsp), %r9
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_11
.LBB1_12: # %._crit_edge
callq hipGetLastError
testl %eax, %eax
jne .LBB1_13
# %bb.14:
leaq 48(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq 24(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
movq 72(%rsp), %r14 # 8-byte Reload
jne .LBB1_15
# %bb.16:
leaq 32(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rbx), %rsi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
movq 32(%rsp), %rax
movq 40(%rsp), %rsi
subq 128(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 136(%rsp), %rsi
addq %rax, %rsi
movq 48(%rsp), %rax
movq 56(%rsp), %rdx
subq 144(%rsp), %rax
imulq $1000000, %rax, %rax # imm = 0xF4240
subq 152(%rsp), %rdx
addq %rax, %rdx
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 8(%rsp), %rdi
callq hipFree
movq (%rbx,%r14,8), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $184, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_3:
.cfi_def_cfa_offset 240
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %edx
jmp .LBB1_4
.LBB1_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.2, %edx
jmp .LBB1_4
.LBB1_13:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.3, %edx
jmp .LBB1_4
.LBB1_15:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.4, %edx
.LBB1_4:
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9calculatePmii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9calculatePmii,@object # @_Z9calculatePmii
.section .rodata,"a",@progbits
.globl _Z9calculatePmii
.p2align 3, 0x0
_Z9calculatePmii:
.quad _Z24__device_stub__calculatePmii
.size _Z9calculatePmii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda Error: '%s' for %s\n"
.size .L.str, 25
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "hipMalloc"
.size .L.str.1, 10
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "hipMemcpy"
.size .L.str.2, 10
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "kernel invocation"
.size .L.str.3, 18
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "memcpy"
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%lu"
.size .L.str.5, 4
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Total time = %ld microsecs Processsing =%ld microsecs\n"
.size .L.str.6, 55
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "The XOR final value is %lu"
.size .L.str.7, 27
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9calculatePmii"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__calculatePmii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9calculatePmii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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