system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*Realizar un programa CUDA que dado un vector V de N números enteros multiplique a
cada número por una constante C, se deben realizar dos implementaciones:
a.Tanto C como N deben ser pasados como parámetros al kernel.
b.Tanto C como N deben estar almacenados en la memoria de constantes de la GPU*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//M and N number of threads (grid and block)
#define M 1
#define N 2
__global__ void multiply( const int array[] , int dim,int result[], const int thread_number)
{
int index = blockIdx.x* blockDim.x* blockDim.y* blockDim.z+threadIdx.z* blockDim.y* blockDim.x+ threadIdx.y* blockDim.x+ threadIdx.x;
//printf("sum:%i\n", result[0]);
if(index<dim){
if(dim<=thread_number){ //if more threads than array size
printf("Thread %i; Adding value of index %i\n", index, index, array[index]);
atomicAdd(result,array[index]);
}
else{ //if less threads than array size
if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
for(int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
printf("Thread %i; Adding value of index %i\n", index, i, array[i]);
atomicAdd(result,array[i]);
}
}
else{ //if last thread deal with all remaining array entries
for(int i=index*(int)(dim/thread_number); i< dim; i++){
//printf("Thread %i; Adding value of index %i\n",index, i, array[i]);
atomicAdd(result,array[i]);
}
}
}
//printf("sum:%i\n", result[0]);
}
}
int main(int argc, char *argv[]){
//Measure time
clock_t time_begin;
time_begin=clock();
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
int size_array=9;
int *d_sum=NULL;
int *h_sum= 0;
h_sum=( int*)malloc(sizeof( int));
h_sum[0]=0;
// malloc a host array
host_array = (int*)malloc( size_array * sizeof(int));
for(int i=0; i<size_array; i++){
host_array[i]=rand()%10;
printf("%i\t", host_array[i]);
}
printf("\n");
printf("Sum of array: %i\n", h_sum[0]);
// cudaMalloc a device array
cudaMalloc(&device_array,size_array * sizeof(int));
cudaError_t er=cudaMalloc(&d_sum, sizeof(int));
// download and inspect the result on the host:
cudaError_t e=cudaMemcpy(device_array, host_array, sizeof(int)*size_array, cudaMemcpyHostToDevice);
cudaError_t error=cudaMemcpy(d_sum, h_sum, sizeof(int), cudaMemcpyHostToDevice);
//cudaerrorinvalidvalue(11)
dim3 bloque(N,N); //Bloque bidimensional de N*N hilos
dim3 grid(M,M); //Grid bidimensional de M*M bloques
int thread_number= N*N*M*M;
multiply<<<grid, bloque>>>(device_array, size_array , d_sum, thread_number);
cudaThreadSynchronize();
// download and inspect the result on the host:
//cudaMemcpy(host_array, device_array, sizeof(int)*size_array, cudaMemcpyDeviceToHost);
cudaMemcpy(h_sum, d_sum, sizeof(int), cudaMemcpyDeviceToHost);
printf("Sum of array: %i\n", h_sum[0]);
// deallocate memory
free(host_array);free(h_sum);
cudaFree(device_array); cudaFree(d_sum);
printf("Time elapsed: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.215s
} | code for sm_80
Function : _Z8multiplyPKiiPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc60007ffe0ff */
/*0030*/ S2R R3, SR_TID.Z ; /* 0x0000000000037919 */
/* 0x000e280000002300 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e680000002200 */
/*0050*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R0, c[0x0][0x8], R3 ; /* 0x0000020000007a24 */
/* 0x001fc800078e0203 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fc800078e0205 */
/*0080*/ IMAD R22, R0, c[0x0][0x0], R7 ; /* 0x0000000000167a24 */
/* 0x004fca00078e0207 */
/*0090*/ ISETP.GE.AND P0, PT, R22, c[0x0][0x168], PT ; /* 0x00005a0016007a0c */
/* 0x000fda0003f06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R24, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001187a10 */
/* 0x000fe20007f3e0ff */
/*00d0*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ ISETP.GT.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f04270 */
/*00f0*/ IMAD.X R2, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff027624 */
/* 0x000fd800008e06ff */
/*0100*/ @P0 BRA 0x300 ; /* 0x000001f000000947 */
/* 0x000fea0003800000 */
/*0110*/ IMAD.MOV.U32 R17, RZ, RZ, 0x4 ; /* 0x00000004ff117424 */
/* 0x000fc800078e00ff */
/*0120*/ IMAD.WIDE R16, R22, R17, c[0x0][0x160] ; /* 0x0000580016107625 */
/* 0x000fca00078e0211 */
/*0130*/ LDG.E R0, [R16.64] ; /* 0x0000002410007981 */
/* 0x000ea2000c1e1900 */
/*0140*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0150*/ IMAD.MOV.U32 R23, RZ, RZ, R22 ; /* 0x000000ffff177224 */
/* 0x000fe400078e0016 */
/*0160*/ IMAD.MOV.U32 R6, RZ, RZ, R24 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0018 */
/*0170*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0180*/ STL.64 [R1], R22 ; /* 0x0000001601007387 */
/* 0x0001e20000100a00 */
/*0190*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*01c0*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0041e80000100800 */
/*01d0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x002fe20000000000 */
/*01e0*/ MOV R11, 0x250 ; /* 0x00000250000b7802 */
/* 0x000fc40000000f00 */
/*01f0*/ MOV R20, 0x1d0 ; /* 0x000001d000147802 */
/* 0x000fe40000000f00 */
/*0200*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0220*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0230*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0240*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0250*/ LDG.E R16, [R16.64] ; /* 0x0000002410107981 */
/* 0x000ea2000c1e1900 */
/*0260*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0270*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0280*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0290*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fc800078e00ff */
/*02b0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*02c0*/ REDUX.SUM UR5, R16 ; /* 0x00000000100573c4 */
/* 0x004e24000000c000 */
/*02d0*/ IMAD.U32 R5, RZ, RZ, UR5 ; /* 0x00000005ff057e24 */
/* 0x001fd4000f8e00ff */
/*02e0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200098e */
/* 0x000fe2000c10e1a4 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ IABS R3, c[0x0][0x178] ; /* 0x00005e0000037a13 */
/* 0x000fe20000000000 */
/*0310*/ ULDC UR5, c[0x0][0x178] ; /* 0x00005e0000057ab9 */
/* 0x000fe40000000800 */
/*0320*/ ULDC UR4, c[0x0][0x168] ; /* 0x00005a0000047ab9 */
/* 0x000fe20000000800 */
/*0330*/ I2F.RP R0, R3 ; /* 0x0000000300007306 */
/* 0x000e220000209400 */
/*0340*/ ULOP3.LUT UR4, UR5, UR4, URZ, 0x3c, !UPT ; /* 0x0000000405047292 */
/* 0x000fcc000f8e3c3f */
/*0350*/ ISETP.LE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf23270 */
/*0360*/ UIADD3 UR4, UR5, -0x1, URZ ; /* 0xffffffff05047890 */
/* 0x000fe2000fffe03f */
/*0370*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0380*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*0390*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*03a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe400078e00ff */
/*03b0*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a05 */
/*03c0*/ IMAD R7, R6, R3, RZ ; /* 0x0000000306077224 */
/* 0x000fe200078e02ff */
/*03d0*/ IABS R6, c[0x0][0x168] ; /* 0x00005a0000067a13 */
/* 0x000fc60000000000 */
/*03e0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fcc00078e0004 */
/*03f0*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fc800078e00ff */
/*0400*/ IMAD.MOV R0, RZ, RZ, -R5 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0a05 */
/*0410*/ IMAD R0, R3, R0, R6 ; /* 0x0000000003007224 */
/* 0x000fca00078e0206 */
/*0420*/ ISETP.GT.U32.AND P2, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f44070 */
/*0430*/ @!P2 IMAD.IADD R0, R0, 0x1, -R3 ; /* 0x000000010000a824 */
/* 0x000fe200078e0a03 */
/*0440*/ @!P2 IADD3 R5, R5, 0x1, RZ ; /* 0x000000010505a810 */
/* 0x000fe40007ffe0ff */
/*0450*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f45270 */
/*0460*/ ISETP.GE.U32.AND P0, PT, R0, R3, PT ; /* 0x000000030000720c */
/* 0x000fda0003f06070 */
/*0470*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fe40007ffe0ff */
/*0480*/ ISETP.NE.AND P0, PT, R22, UR4, PT ; /* 0x0000000416007c0c */
/* 0x000fc6000bf05270 */
/*0490*/ @!P1 IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff059224 */
/* 0x000fe200078e0a05 */
/*04a0*/ @!P2 LOP3.LUT R5, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff05aa12 */
/* 0x000fca00078e33ff */
/*04b0*/ IMAD R28, R22, R5, RZ ; /* 0x00000005161c7224 */
/* 0x000fc800078e02ff */
/*04c0*/ @!P0 BRA 0xf90 ; /* 0x00000ac000008947 */
/* 0x000fea0003800000 */
/*04d0*/ ISETP.GE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f06270 */
/*04e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*04f0*/ IMAD.IADD R26, R5, 0x1, R28.reuse ; /* 0x00000001051a7824 */
/* 0x100fe200078e021c */
/*0500*/ IADD3 R19, R28, 0x1, RZ ; /* 0x000000011c137810 */
/* 0x000fe20007ffe0ff */
/*0510*/ BSSY B6, 0x810 ; /* 0x000002f000067945 */
/* 0x000fe20003800000 */
/*0520*/ IMAD.MOV.U32 R23, RZ, RZ, R28 ; /* 0x000000ffff177224 */
/* 0x000fe400078e001c */
/*0530*/ IMNMX R19, R26, R19, !PT ; /* 0x000000131a137217 */
/* 0x000fca0007800200 */
/*0540*/ IMAD.IADD R0, R19, 0x1, -R28 ; /* 0x0000000113007824 */
/* 0x000fca00078e0a1c */
/*0550*/ LOP3.LUT P0, R18, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300127812 */
/* 0x000fda000780c0ff */
/*0560*/ @!P0 BRA 0x800 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*0570*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*0580*/ IMAD.MOV.U32 R23, RZ, RZ, R28 ; /* 0x000000ffff177224 */
/* 0x000fe400078e001c */
/*0590*/ IMAD.WIDE R4, R28, R5, c[0x0][0x160] ; /* 0x000058001c047625 */
/* 0x000fc800078e0205 */
/*05a0*/ IMAD.MOV.U32 R16, RZ, RZ, R4 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0004 */
/*05b0*/ IMAD.MOV.U32 R17, RZ, RZ, R5 ; /* 0x000000ffff117224 */
/* 0x000fca00078e0005 */
/*05c0*/ LDG.E R0, [R16.64] ; /* 0x0000002410007981 */
/* 0x000ea2000c1e1900 */
/*05d0*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*05e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*05f0*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fe20007ffe0ff */
/*0600*/ STL.64 [R1], R22 ; /* 0x0000001601007387 */
/* 0x000fe20000100a00 */
/*0610*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x001fe400078e00ff */
/*0620*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e220000000a00 */
/*0630*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f05270 */
/*0640*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc400078e00ff */
/*0650*/ IMAD.MOV.U32 R6, RZ, RZ, R24 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0018 */
/*0660*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0670*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0043e40000100800 */
/*0680*/ P2R R0, PR, RZ, 0x1 ; /* 0x00000001ff007803 */
/* 0x002fe40000000000 */
/*0690*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x001fe20000000000 */
/*06a0*/ MOV R3, 0x710 ; /* 0x0000071000037802 */
/* 0x000fe40000000f00 */
/*06b0*/ MOV R20, 0x690 ; /* 0x0000069000147802 */
/* 0x000fe40000000f00 */
/*06c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*06d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*06e0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*06f0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0700*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0710*/ LDG.E R0, [R16.64] ; /* 0x0000002410007981 */
/* 0x000ea2000c1e1900 */
/*0720*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*0730*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe200078e00ff */
/*0740*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0750*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x000e220000000000 */
/*0760*/ ISETP.NE.AND P6, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003fc5270 */
/*0770*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe200078e00ff */
/*0780*/ IADD3 R23, R23, 0x1, RZ ; /* 0x0000000117177810 */
/* 0x000fe40007ffe0ff */
/*0790*/ ISETP.EQ.U32.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x001fe2000bf02070 */
/*07a0*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x004e24000000c000 */
/*07b0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x001fd4000f8e00ff */
/*07c0*/ @P0 RED.E.ADD.STRONG.GPU [R4.64], R3 ; /* 0x000000030400098e */
/* 0x0001e2000c10e1a4 */
/*07d0*/ IADD3 R16, P0, R16, 0x4, RZ ; /* 0x0000000410107810 */
/* 0x000fca0007f1e0ff */
/*07e0*/ IMAD.X R17, RZ, RZ, R17, P0 ; /* 0x000000ffff117224 */
/* 0x000fe200000e0611 */
/*07f0*/ @P6 BRA 0x5c0 ; /* 0xfffffdc000006947 */
/* 0x000fea000383ffff */
/*0800*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0810*/ LOP3.LUT R0, RZ, R28, RZ, 0x33, !PT ; /* 0x0000001cff007212 */
/* 0x000fca00078e33ff */
/*0820*/ IMAD.IADD R0, R19, 0x1, R0 ; /* 0x0000000113007824 */
/* 0x000fca00078e0200 */
/*0830*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f06070 */
/*0840*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0850*/ IMAD.MOV.U32 R4, RZ, RZ, 0x4 ; /* 0x00000004ff047424 */
/* 0x001fc800078e00ff */
/*0860*/ IMAD.WIDE R4, R23, R4, c[0x0][0x160] ; /* 0x0000580017047625 */
/* 0x000fca00078e0204 */
/*0870*/ IADD3 R18, P0, R4, 0x8, RZ ; /* 0x0000000804127810 */
/* 0x000fca0007f1e0ff */
/*0880*/ IMAD.X R19, RZ, RZ, R5, P0 ; /* 0x000000ffff137224 */
/* 0x000fca00000e0605 */
/*0890*/ LDG.E R0, [R18.64+-0x8] ; /* 0xfffff82412007981 */
/* 0x000ea2000c1e1900 */
/*08a0*/ MOV R25, 0x0 ; /* 0x0000000000197802 */
/* 0x000fe20000000f00 */
/*08b0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*08c0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*08d0*/ STL.64 [R1], R22 ; /* 0x0000001601007387 */
/* 0x0001e20000100a00 */
/*08e0*/ LDC.64 R8, c[0x4][R25] ; /* 0x0100000019087b82 */
/* 0x0000620000000a00 */
/*08f0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0900*/ IMAD.MOV.U32 R6, RZ, RZ, R24 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0018 */
/*0910*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0920*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0041e80000100800 */
/*0930*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x002fe20000000000 */
/*0940*/ MOV R3, 0x9b0 ; /* 0x000009b000037802 */
/* 0x000fc40000000f00 */
/*0950*/ MOV R20, 0x930 ; /* 0x0000093000147802 */
/* 0x000fe40000000f00 */
/*0960*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0970*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fe40000000f00 */
/*0980*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0990*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*09a0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*09b0*/ LDG.E R4, [R18.64+-0x8] ; /* 0xfffff82412047981 */
/* 0x000ea2000c1e1900 */
/*09c0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*09d0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff107624 */
/* 0x000fe200078e00ff */
/*09e0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*09f0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e220000000000 */
/*0a00*/ IMAD.MOV.U32 R17, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff117624 */
/* 0x000fc800078e00ff */
/*0a10*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*0a20*/ REDUX.SUM UR5, R4 ; /* 0x00000000040573c4 */
/* 0x004e24000000c000 */
/*0a30*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x001fd4000f8e00ff */
/*0a40*/ @P0 RED.E.ADD.STRONG.GPU [R16.64], R3 ; /* 0x000000031000098e */
/* 0x0001e8000c10e1a4 */
/*0a50*/ LDG.E R0, [R18.64+-0x4] ; /* 0xfffffc2412007981 */
/* 0x000ea2000c1e1900 */
/*0a60*/ IADD3 R11, R23, 0x1, RZ ; /* 0x00000001170b7810 */
/* 0x000fe20007ffe0ff */
/*0a70*/ IMAD.MOV.U32 R10, RZ, RZ, R22 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0016 */
/*0a80*/ LDC.64 R8, c[0x4][R25] ; /* 0x0100000019087b82 */
/* 0x0000620000000a00 */
/*0a90*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0aa0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0ab0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e20000100a00 */
/*0ac0*/ IMAD.MOV.U32 R6, RZ, RZ, R24 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0018 */
/*0ad0*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0ae0*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0041e80000100800 */
/*0af0*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe20000000000 */
/*0b00*/ MOV R3, 0xb70 ; /* 0x00000b7000037802 */
/* 0x000fe40000000f00 */
/*0b10*/ MOV R20, 0xaf0 ; /* 0x00000af000147802 */
/* 0x000fe40000000f00 */
/*0b20*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0b30*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0b40*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0b50*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0b60*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0b70*/ LDG.E R4, [R18.64+-0x4] ; /* 0xfffffc2412047981 */
/* 0x000ea2000c1e1900 */
/*0b80*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0b90*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0ba0*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e2a0000000000 */
/*0bb0*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*0bc0*/ REDUX.SUM UR5, R4 ; /* 0x00000000040573c4 */
/* 0x004e24000000c000 */
/*0bd0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x001fd4000f8e00ff */
/*0be0*/ @P0 RED.E.ADD.STRONG.GPU [R16.64], R3 ; /* 0x000000031000098e */
/* 0x0001e8000c10e1a4 */
/*0bf0*/ LDG.E R0, [R18.64] ; /* 0x0000002412007981 */
/* 0x000ea2000c1e1900 */
/*0c00*/ IADD3 R11, R23, 0x2, RZ ; /* 0x00000002170b7810 */
/* 0x000fe20007ffe0ff */
/*0c10*/ IMAD.MOV.U32 R10, RZ, RZ, R22 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0016 */
/*0c20*/ LDC.64 R8, c[0x4][R25] ; /* 0x0100000019087b82 */
/* 0x0000620000000a00 */
/*0c30*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0c40*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0c50*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e20000100a00 */
/*0c60*/ IMAD.MOV.U32 R6, RZ, RZ, R24 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0018 */
/*0c70*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0c80*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0041e80000100800 */
/*0c90*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe20000000000 */
/*0ca0*/ MOV R3, 0xd10 ; /* 0x00000d1000037802 */
/* 0x000fe40000000f00 */
/*0cb0*/ MOV R20, 0xc90 ; /* 0x00000c9000147802 */
/* 0x000fe40000000f00 */
/*0cc0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0cd0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0ce0*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0cf0*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0d00*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0d10*/ LDG.E R4, [R18.64] ; /* 0x0000002412047981 */
/* 0x000ea2000c1e1900 */
/*0d20*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0d30*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0d40*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000e2a0000000000 */
/*0d50*/ ISETP.EQ.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x001fe2000bf02070 */
/*0d60*/ REDUX.SUM UR5, R4 ; /* 0x00000000040573c4 */
/* 0x004e24000000c000 */
/*0d70*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x001fd4000f8e00ff */
/*0d80*/ @P0 RED.E.ADD.STRONG.GPU [R16.64], R3 ; /* 0x000000031000098e */
/* 0x0001e8000c10e1a4 */
/*0d90*/ LDG.E R0, [R18.64+0x4] ; /* 0x0000042412007981 */
/* 0x000ea2000c1e1900 */
/*0da0*/ IADD3 R11, R23, 0x3, RZ ; /* 0x00000003170b7810 */
/* 0x000fe20007ffe0ff */
/*0db0*/ IMAD.MOV.U32 R10, RZ, RZ, R22 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0016 */
/*0dc0*/ LDC.64 R8, c[0x4][R25] ; /* 0x0100000019087b82 */
/* 0x0000620000000a00 */
/*0dd0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0de0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0df0*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0001e20000100a00 */
/*0e00*/ IMAD.MOV.U32 R6, RZ, RZ, R24 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0018 */
/*0e10*/ IMAD.MOV.U32 R7, RZ, RZ, R2 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0002 */
/*0e20*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0041e80000100800 */
/*0e30*/ LEPC R10 ; /* 0x00000000000a734e */
/* 0x003fe20000000000 */
/*0e40*/ MOV R3, 0xeb0 ; /* 0x00000eb000037802 */
/* 0x000fe40000000f00 */
/*0e50*/ MOV R20, 0xe30 ; /* 0x00000e3000147802 */
/* 0x000fe40000000f00 */
/*0e60*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0e70*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0e80*/ IADD3 R20, P0, P1, -R20, R3, R10 ; /* 0x0000000314147210 */
/* 0x000fc8000791e10a */
/*0e90*/ IADD3.X R21, ~R0, R21, R11, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e250b */
/*0ea0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0eb0*/ LDG.E R0, [R18.64+0x4] ; /* 0x0000042412007981 */
/* 0x0000a2000c1e1900 */
/*0ec0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*0ed0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*0ee0*/ S2R R3, SR_LANEID ; /* 0x0000000000037919 */
/* 0x000e620000000000 */
/*0ef0*/ IADD3 R23, R23, 0x4, RZ ; /* 0x0000000417177810 */
/* 0x000fc80007ffe0ff */
/*0f00*/ ISETP.EQ.U32.AND P0, PT, R3, UR4, PT ; /* 0x0000000403007c0c */
/* 0x002fe4000bf02070 */
/*0f10*/ IADD3 R18, P1, R18, 0x10, RZ ; /* 0x0000001012127810 */
/* 0x001fca0007f3e0ff */
/*0f20*/ IMAD.X R19, RZ, RZ, R19, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0613 */
/*0f30*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x004e24000000c000 */
/*0f40*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x001fca000f8e00ff */
/*0f50*/ @P0 RED.E.ADD.STRONG.GPU [R16.64], R3 ; /* 0x000000031000098e */
/* 0x0001e2000c10e1a4 */
/*0f60*/ ISETP.GE.AND P0, PT, R23, R26, PT ; /* 0x0000001a1700720c */
/* 0x000fda0003f06270 */
/*0f70*/ @!P0 BRA 0x890 ; /* 0xfffff91000008947 */
/* 0x001fea000383ffff */
/*0f80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0f90*/ ISETP.GE.AND P0, PT, R28, c[0x0][0x168], PT ; /* 0x00005a001c007a0c */
/* 0x000fda0003f06270 */
/*0fa0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0fb0*/ IADD3 R0, -R28, c[0x0][0x168], RZ ; /* 0x00005a001c007a10 */
/* 0x000fe20007ffe1ff */
/*0fc0*/ BSSY B0, 0x1180 ; /* 0x000001b000007945 */
/* 0x000fe20003800000 */
/*0fd0*/ LOP3.LUT R2, RZ, R28, RZ, 0x33, !PT ; /* 0x0000001cff027212 */
/* 0x000fe400078e33ff */
/*0fe0*/ LOP3.LUT P1, R0, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300007812 */
/* 0x000fe4000782c0ff */
/*0ff0*/ IADD3 R2, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fc80007ffe0ff */
/*1000*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fce0003f06070 */
/*1010*/ @!P1 BRA 0x1170 ; /* 0x0000015000009947 */
/* 0x000fea0003800000 */
/*1020*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe400078e00ff */
/*1030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff047624 */
/* 0x000fe400078e00ff */
/*1040*/ IMAD.WIDE R2, R28, R3, c[0x0][0x160] ; /* 0x000058001c027625 */
/* 0x000fc800078e0203 */
/*1050*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0002 */
/*1060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff057624 */
/* 0x000fe400078e00ff */
/*1070*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fcc00078e0006 */
/*1080*/ LDG.E R2, [R2.64] ; /* 0x0000002402027981 */
/* 0x0000a2000c1e1900 */
/*1090*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*10a0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*10b0*/ S2R R7, SR_LANEID ; /* 0x0000000000077919 */
/* 0x000e620000000000 */
/*10c0*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fe200080e0000 */
/*10d0*/ IADD3 R0, R0, -0x1, RZ ; /* 0xffffffff00007810 */
/* 0x000fca0007ffe0ff */
/*10e0*/ ISETP.EQ.U32.AND P1, PT, R7, UR4, PT ; /* 0x0000000407007c0c */
/* 0x002fe4000bf22070 */
/*10f0*/ IADD3 R6, P2, R6, 0x4, RZ ; /* 0x0000000406067810 */
/* 0x000fe40007f5e0ff */
/*1100*/ IADD3 R28, R28, 0x1, RZ ; /* 0x000000011c1c7810 */
/* 0x000fc60007ffe0ff */
/*1110*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x001fe200010e0603 */
/*1120*/ REDUX.SUM UR5, R2 ; /* 0x00000000020573c4 */
/* 0x004e24000000c000 */
/*1130*/ IMAD.U32 R7, RZ, RZ, UR5 ; /* 0x00000005ff077e24 */
/* 0x001fca000f8e00ff */
/*1140*/ @P1 RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400198e */
/* 0x0001e2000c10e1a4 */
/*1150*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f25270 */
/*1160*/ @P1 BRA 0x1070 ; /* 0xffffff0000001947 */
/* 0x001fea000383ffff */
/*1170*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*1180*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*1190*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe400078e00ff */
/*11a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe400078e00ff */
/*11b0*/ IMAD.WIDE R4, R28, R5, c[0x0][0x160] ; /* 0x000058001c047625 */
/* 0x000fc800078e0205 */
/*11c0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff037624 */
/* 0x000fe200078e00ff */
/*11d0*/ IADD3 R6, P0, R4, 0x8, RZ ; /* 0x0000000804067810 */
/* 0x000fca0007f1e0ff */
/*11e0*/ IMAD.X R5, RZ, RZ, R5, P0 ; /* 0x000000ffff057224 */
/* 0x000fe400000e0605 */
/*11f0*/ IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff047224 */
/* 0x000fca00078e0006 */
/*1200*/ LDG.E R0, [R4.64+-0x8] ; /* 0xfffff82404007981 */
/* 0x000ea2000c1e1900 */
/*1210*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*1220*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe400038e0100 */
/*1230*/ S2R R6, SR_LANEID ; /* 0x0000000000067919 */
/* 0x000e220000000000 */
/*1240*/ UFLO.U32 UR4, UR4 ; /* 0x00000004000472bd */
/* 0x000fcc00080e0000 */
/*1250*/ ISETP.EQ.U32.AND P0, PT, R6, UR4, PT ; /* 0x0000000406007c0c */
/* 0x001fe2000bf02070 */
/*1260*/ REDUX.SUM UR5, R0 ; /* 0x00000000000573c4 */
/* 0x004e24000000c000 */
/*1270*/ IMAD.U32 R9, RZ, RZ, UR5 ; /* 0x00000005ff097e24 */
/* 0x001fd4000f8e00ff */
/*1280*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200098e */
/* 0x0001e8000c10e1a4 */
/*1290*/ LDG.E R6, [R4.64+-0x4] ; /* 0xfffffc2404067981 */
/* 0x000ea4000c1e1900 */
/*12a0*/ REDUX.SUM UR4, R6 ; /* 0x00000000060473c4 */
/* 0x004e64000000c000 */
/*12b0*/ IMAD.U32 R11, RZ, RZ, UR4 ; /* 0x00000004ff0b7e24 */
/* 0x002fca000f8e00ff */
/*12c0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R11 ; /* 0x0000000b0200098e */
/* 0x0003e8000c10e1a4 */
/*12d0*/ LDG.E R7, [R4.64] ; /* 0x0000002404077981 */
/* 0x000ea4000c1e1900 */
/*12e0*/ REDUX.SUM UR4, R7 ; /* 0x00000000070473c4 */
/* 0x004ea4000000c000 */
/*12f0*/ IMAD.U32 R13, RZ, RZ, UR4 ; /* 0x00000004ff0d7e24 */
/* 0x004fca000f8e00ff */
/*1300*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R13 ; /* 0x0000000d0200098e */
/* 0x0003e8000c10e1a4 */
/*1310*/ LDG.E R0, [R4.64+0x4] ; /* 0x0000042404007981 */
/* 0x0004e2000c1e1900 */
/*1320*/ IADD3 R28, R28, 0x4, RZ ; /* 0x000000041c1c7810 */
/* 0x000fe40007ffe0ff */
/*1330*/ IADD3 R6, P1, R4, 0x10, RZ ; /* 0x0000001004067810 */
/* 0x000fca0007f3e0ff */
/*1340*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x004fe200008e0605 */
/*1350*/ REDUX.SUM UR4, R0 ; /* 0x00000000000473c4 */
/* 0x008e24000000c000 */
/*1360*/ IMAD.U32 R9, RZ, RZ, UR4 ; /* 0x00000004ff097e24 */
/* 0x001fca000f8e00ff */
/*1370*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R9 ; /* 0x000000090200098e */
/* 0x0003e2000c10e1a4 */
/*1380*/ ISETP.GE.AND P0, PT, R28, c[0x0][0x168], PT ; /* 0x00005a001c007a0c */
/* 0x000fda0003f06270 */
/*1390*/ @!P0 BRA 0x11f0 ; /* 0xfffffe5000008947 */
/* 0x002fea000383ffff */
/*13a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*13b0*/ BRA 0x13b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*13c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*13f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*Realizar un programa CUDA que dado un vector V de N números enteros multiplique a
cada número por una constante C, se deben realizar dos implementaciones:
a.Tanto C como N deben ser pasados como parámetros al kernel.
b.Tanto C como N deben estar almacenados en la memoria de constantes de la GPU*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//M and N number of threads (grid and block)
#define M 1
#define N 2
__global__ void multiply( const int array[] , int dim,int result[], const int thread_number)
{
int index = blockIdx.x* blockDim.x* blockDim.y* blockDim.z+threadIdx.z* blockDim.y* blockDim.x+ threadIdx.y* blockDim.x+ threadIdx.x;
//printf("sum:%i\n", result[0]);
if(index<dim){
if(dim<=thread_number){ //if more threads than array size
printf("Thread %i; Adding value of index %i\n", index, index, array[index]);
atomicAdd(result,array[index]);
}
else{ //if less threads than array size
if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
for(int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
printf("Thread %i; Adding value of index %i\n", index, i, array[i]);
atomicAdd(result,array[i]);
}
}
else{ //if last thread deal with all remaining array entries
for(int i=index*(int)(dim/thread_number); i< dim; i++){
//printf("Thread %i; Adding value of index %i\n",index, i, array[i]);
atomicAdd(result,array[i]);
}
}
}
//printf("sum:%i\n", result[0]);
}
}
int main(int argc, char *argv[]){
//Measure time
clock_t time_begin;
time_begin=clock();
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
int size_array=9;
int *d_sum=NULL;
int *h_sum= 0;
h_sum=( int*)malloc(sizeof( int));
h_sum[0]=0;
// malloc a host array
host_array = (int*)malloc( size_array * sizeof(int));
for(int i=0; i<size_array; i++){
host_array[i]=rand()%10;
printf("%i\t", host_array[i]);
}
printf("\n");
printf("Sum of array: %i\n", h_sum[0]);
// cudaMalloc a device array
cudaMalloc(&device_array,size_array * sizeof(int));
cudaError_t er=cudaMalloc(&d_sum, sizeof(int));
// download and inspect the result on the host:
cudaError_t e=cudaMemcpy(device_array, host_array, sizeof(int)*size_array, cudaMemcpyHostToDevice);
cudaError_t error=cudaMemcpy(d_sum, h_sum, sizeof(int), cudaMemcpyHostToDevice);
//cudaerrorinvalidvalue(11)
dim3 bloque(N,N); //Bloque bidimensional de N*N hilos
dim3 grid(M,M); //Grid bidimensional de M*M bloques
int thread_number= N*N*M*M;
multiply<<<grid, bloque>>>(device_array, size_array , d_sum, thread_number);
cudaThreadSynchronize();
// download and inspect the result on the host:
//cudaMemcpy(host_array, device_array, sizeof(int)*size_array, cudaMemcpyDeviceToHost);
cudaMemcpy(h_sum, d_sum, sizeof(int), cudaMemcpyDeviceToHost);
printf("Sum of array: %i\n", h_sum[0]);
// deallocate memory
free(host_array);free(h_sum);
cudaFree(device_array); cudaFree(d_sum);
printf("Time elapsed: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.215s
} | .file "tmpxft_0013adbe_00000000-6_practica1_6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8multiplyPKiiPiiPKiiPii
.type _Z32__device_stub__Z8multiplyPKiiPiiPKiiPii, @function
_Z32__device_stub__Z8multiplyPKiiPiiPKiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPKiiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8multiplyPKiiPiiPKiiPii, .-_Z32__device_stub__Z8multiplyPKiiPiiPKiiPii
.globl _Z8multiplyPKiiPii
.type _Z8multiplyPKiiPii, @function
_Z8multiplyPKiiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8multiplyPKiiPiiPKiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8multiplyPKiiPii, .-_Z8multiplyPKiiPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i\t"
.LC1:
.string "\n"
.LC2:
.string "Sum of array: %i\n"
.LC5:
.string "Time elapsed: %f seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %r15
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movl $0, (%rax)
movl $36, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, %rbx
leaq 36(%rax), %r12
leaq .LC0(%rip), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
addl %ecx, %ecx
subl %ecx, %eax
movl %eax, %edx
movl %eax, (%rbx)
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 0(%r13), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $36, %edx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 16(%rsp)
movl $2, 20(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl 0(%r13), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r15, %xmm1
subss %xmm1, %xmm0
divss .LC3(%rip), %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $4, %ecx
movq 8(%rsp), %rdx
movl $9, %esi
movq (%rsp), %rdi
call _Z32__device_stub__Z8multiplyPKiiPiiPKiiPii
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8multiplyPKiiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPKiiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1232348160
.align 4
.LC4:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*Realizar un programa CUDA que dado un vector V de N números enteros multiplique a
cada número por una constante C, se deben realizar dos implementaciones:
a.Tanto C como N deben ser pasados como parámetros al kernel.
b.Tanto C como N deben estar almacenados en la memoria de constantes de la GPU*/
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//M and N number of threads (grid and block)
#define M 1
#define N 2
__global__ void multiply( const int array[] , int dim,int result[], const int thread_number)
{
int index = blockIdx.x* blockDim.x* blockDim.y* blockDim.z+threadIdx.z* blockDim.y* blockDim.x+ threadIdx.y* blockDim.x+ threadIdx.x;
//printf("sum:%i\n", result[0]);
if(index<dim){
if(dim<=thread_number){ //if more threads than array size
printf("Thread %i; Adding value of index %i\n", index, index, array[index]);
atomicAdd(result,array[index]);
}
else{ //if less threads than array size
if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
for(int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
printf("Thread %i; Adding value of index %i\n", index, i, array[i]);
atomicAdd(result,array[i]);
}
}
else{ //if last thread deal with all remaining array entries
for(int i=index*(int)(dim/thread_number); i< dim; i++){
//printf("Thread %i; Adding value of index %i\n",index, i, array[i]);
atomicAdd(result,array[i]);
}
}
}
//printf("sum:%i\n", result[0]);
}
}
int main(int argc, char *argv[]){
//Measure time
clock_t time_begin;
time_begin=clock();
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
int size_array=9;
int *d_sum=NULL;
int *h_sum= 0;
h_sum=( int*)malloc(sizeof( int));
h_sum[0]=0;
// malloc a host array
host_array = (int*)malloc( size_array * sizeof(int));
for(int i=0; i<size_array; i++){
host_array[i]=rand()%10;
printf("%i\t", host_array[i]);
}
printf("\n");
printf("Sum of array: %i\n", h_sum[0]);
// cudaMalloc a device array
cudaMalloc(&device_array,size_array * sizeof(int));
cudaError_t er=cudaMalloc(&d_sum, sizeof(int));
// download and inspect the result on the host:
cudaError_t e=cudaMemcpy(device_array, host_array, sizeof(int)*size_array, cudaMemcpyHostToDevice);
cudaError_t error=cudaMemcpy(d_sum, h_sum, sizeof(int), cudaMemcpyHostToDevice);
//cudaerrorinvalidvalue(11)
dim3 bloque(N,N); //Bloque bidimensional de N*N hilos
dim3 grid(M,M); //Grid bidimensional de M*M bloques
int thread_number= N*N*M*M;
multiply<<<grid, bloque>>>(device_array, size_array , d_sum, thread_number);
cudaThreadSynchronize();
// download and inspect the result on the host:
//cudaMemcpy(host_array, device_array, sizeof(int)*size_array, cudaMemcpyDeviceToHost);
cudaMemcpy(h_sum, d_sum, sizeof(int), cudaMemcpyDeviceToHost);
printf("Sum of array: %i\n", h_sum[0]);
// deallocate memory
free(host_array);free(h_sum);
cudaFree(device_array); cudaFree(d_sum);
printf("Time elapsed: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.215s
} | /*Realizar un programa CUDA que dado un vector V de N números enteros multiplique a
cada número por una constante C, se deben realizar dos implementaciones:
a.Tanto C como N deben ser pasados como parámetros al kernel.
b.Tanto C como N deben estar almacenados en la memoria de constantes de la GPU*/
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//M and N number of threads (grid and block)
#define M 1
#define N 2
__global__ void multiply( const int array[] , int dim,int result[], const int thread_number)
{
int index = blockIdx.x* blockDim.x* blockDim.y* blockDim.z+threadIdx.z* blockDim.y* blockDim.x+ threadIdx.y* blockDim.x+ threadIdx.x;
//printf("sum:%i\n", result[0]);
if(index<dim){
if(dim<=thread_number){ //if more threads than array size
printf("Thread %i; Adding value of index %i\n", index, index, array[index]);
atomicAdd(result,array[index]);
}
else{ //if less threads than array size
if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
for(int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
printf("Thread %i; Adding value of index %i\n", index, i, array[i]);
atomicAdd(result,array[i]);
}
}
else{ //if last thread deal with all remaining array entries
for(int i=index*(int)(dim/thread_number); i< dim; i++){
//printf("Thread %i; Adding value of index %i\n",index, i, array[i]);
atomicAdd(result,array[i]);
}
}
}
//printf("sum:%i\n", result[0]);
}
}
int main(int argc, char *argv[]){
//Measure time
clock_t time_begin;
time_begin=clock();
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
int size_array=9;
int *d_sum=NULL;
int *h_sum= 0;
h_sum=( int*)malloc(sizeof( int));
h_sum[0]=0;
// malloc a host array
host_array = (int*)malloc( size_array * sizeof(int));
for(int i=0; i<size_array; i++){
host_array[i]=rand()%10;
printf("%i\t", host_array[i]);
}
printf("\n");
printf("Sum of array: %i\n", h_sum[0]);
// cudaMalloc a device array
hipMalloc(&device_array,size_array * sizeof(int));
hipError_t er=hipMalloc(&d_sum, sizeof(int));
// download and inspect the result on the host:
hipError_t e=hipMemcpy(device_array, host_array, sizeof(int)*size_array, hipMemcpyHostToDevice);
hipError_t error=hipMemcpy(d_sum, h_sum, sizeof(int), hipMemcpyHostToDevice);
//cudaerrorinvalidvalue(11)
dim3 bloque(N,N); //Bloque bidimensional de N*N hilos
dim3 grid(M,M); //Grid bidimensional de M*M bloques
int thread_number= N*N*M*M;
multiply<<<grid, bloque>>>(device_array, size_array , d_sum, thread_number);
hipDeviceSynchronize();
// download and inspect the result on the host:
//cudaMemcpy(host_array, device_array, sizeof(int)*size_array, cudaMemcpyDeviceToHost);
hipMemcpy(h_sum, d_sum, sizeof(int), hipMemcpyDeviceToHost);
printf("Sum of array: %i\n", h_sum[0]);
// deallocate memory
free(host_array);free(h_sum);
hipFree(device_array); hipFree(d_sum);
printf("Time elapsed: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.215s
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*Realizar un programa CUDA que dado un vector V de N números enteros multiplique a
cada número por una constante C, se deben realizar dos implementaciones:
a.Tanto C como N deben ser pasados como parámetros al kernel.
b.Tanto C como N deben estar almacenados en la memoria de constantes de la GPU*/
#include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
//M and N number of threads (grid and block)
#define M 1
#define N 2
__global__ void multiply( const int array[] , int dim,int result[], const int thread_number)
{
int index = blockIdx.x* blockDim.x* blockDim.y* blockDim.z+threadIdx.z* blockDim.y* blockDim.x+ threadIdx.y* blockDim.x+ threadIdx.x;
//printf("sum:%i\n", result[0]);
if(index<dim){
if(dim<=thread_number){ //if more threads than array size
printf("Thread %i; Adding value of index %i\n", index, index, array[index]);
atomicAdd(result,array[index]);
}
else{ //if less threads than array size
if(index!=thread_number-1){//if not last thread deal with size_array/thread_nb array entries
for(int i=index*(int)(dim/thread_number); i< index*(int)(dim/thread_number)+(int)(dim/thread_number); i++){
printf("Thread %i; Adding value of index %i\n", index, i, array[i]);
atomicAdd(result,array[i]);
}
}
else{ //if last thread deal with all remaining array entries
for(int i=index*(int)(dim/thread_number); i< dim; i++){
//printf("Thread %i; Adding value of index %i\n",index, i, array[i]);
atomicAdd(result,array[i]);
}
}
}
//printf("sum:%i\n", result[0]);
}
}
int main(int argc, char *argv[]){
//Measure time
clock_t time_begin;
time_begin=clock();
// pointers to host & device arrays
int *device_array = 0;
int *host_array = 0;
int size_array=9;
int *d_sum=NULL;
int *h_sum= 0;
h_sum=( int*)malloc(sizeof( int));
h_sum[0]=0;
// malloc a host array
host_array = (int*)malloc( size_array * sizeof(int));
for(int i=0; i<size_array; i++){
host_array[i]=rand()%10;
printf("%i\t", host_array[i]);
}
printf("\n");
printf("Sum of array: %i\n", h_sum[0]);
// cudaMalloc a device array
hipMalloc(&device_array,size_array * sizeof(int));
hipError_t er=hipMalloc(&d_sum, sizeof(int));
// download and inspect the result on the host:
hipError_t e=hipMemcpy(device_array, host_array, sizeof(int)*size_array, hipMemcpyHostToDevice);
hipError_t error=hipMemcpy(d_sum, h_sum, sizeof(int), hipMemcpyHostToDevice);
//cudaerrorinvalidvalue(11)
dim3 bloque(N,N); //Bloque bidimensional de N*N hilos
dim3 grid(M,M); //Grid bidimensional de M*M bloques
int thread_number= N*N*M*M;
multiply<<<grid, bloque>>>(device_array, size_array , d_sum, thread_number);
hipDeviceSynchronize();
// download and inspect the result on the host:
//cudaMemcpy(host_array, device_array, sizeof(int)*size_array, cudaMemcpyDeviceToHost);
hipMemcpy(h_sum, d_sum, sizeof(int), hipMemcpyDeviceToHost);
printf("Sum of array: %i\n", h_sum[0]);
// deallocate memory
free(host_array);free(h_sum);
hipFree(device_array); hipFree(d_sum);
printf("Time elapsed: %f seconds\n", (((float)clock() - (float)time_begin) / 1000000.0F ) * 1000 ); //1.215s
} | .text
.file "practica1_6.hip"
.globl _Z23__device_stub__multiplyPKiiPii # -- Begin function _Z23__device_stub__multiplyPKiiPii
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPKiiPii,@function
_Z23__device_stub__multiplyPKiiPii: # @_Z23__device_stub__multiplyPKiiPii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPKiiPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPKiiPii, .Lfunc_end0-_Z23__device_stub__multiplyPKiiPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.LCPI1_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq clock
movq %rax, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movl $4, %edi
callq malloc
movq %rax, %r14
movl $0, (%rax)
movl $36, %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $34, %rax
addl %ecx, %eax
addl %eax, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movl %esi, (%r15,%r12,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r12
cmpq $9, %r12
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
movl (%r14), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $36, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl $9, 28(%rsp)
movq %rcx, 80(%rsp)
movl $4, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8multiplyPKiiPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%r14), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq clock
cvtsi2ss %rax, %xmm0
cvtsi2ss %rbx, %xmm1
subss %xmm1, %xmm0
divss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPKiiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPKiiPii,@object # @_Z8multiplyPKiiPii
.section .rodata,"a",@progbits
.globl _Z8multiplyPKiiPii
.p2align 3, 0x0
_Z8multiplyPKiiPii:
.quad _Z23__device_stub__multiplyPKiiPii
.size _Z8multiplyPKiiPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i\t"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Sum of array: %i\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time elapsed: %f seconds\n"
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPKiiPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPKiiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPKiiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013adbe_00000000-6_practica1_6.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z8multiplyPKiiPiiPKiiPii
.type _Z32__device_stub__Z8multiplyPKiiPiiPKiiPii, @function
_Z32__device_stub__Z8multiplyPKiiPiiPKiiPii:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPKiiPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z8multiplyPKiiPiiPKiiPii, .-_Z32__device_stub__Z8multiplyPKiiPiiPKiiPii
.globl _Z8multiplyPKiiPii
.type _Z8multiplyPKiiPii, @function
_Z8multiplyPKiiPii:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8multiplyPKiiPiiPKiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z8multiplyPKiiPii, .-_Z8multiplyPKiiPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%i\t"
.LC1:
.string "\n"
.LC2:
.string "Sum of array: %i\n"
.LC5:
.string "Time elapsed: %f seconds\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, %r15
movq $0, (%rsp)
movq $0, 8(%rsp)
movl $4, %edi
call malloc@PLT
movq %rax, %r13
movl $0, (%rax)
movl $36, %edi
call malloc@PLT
movq %rax, %r14
movq %rax, %rbx
leaq 36(%rax), %r12
leaq .LC0(%rip), %rbp
.L12:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %ecx
addl %ecx, %ecx
subl %ecx, %eax
movl %eax, %edx
movl %eax, (%rbx)
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 0(%r13), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rdi
movl $36, %esi
call cudaMalloc@PLT
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $36, %edx
movq %r14, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4, %edx
movq %r13, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $2, 16(%rsp)
movl $2, 20(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movl 0(%r13), %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call clock@PLT
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
pxor %xmm1, %xmm1
cvtsi2ssq %r15, %xmm1
subss %xmm1, %xmm0
divss .LC3(%rip), %xmm0
mulss .LC4(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L18
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
movl $4, %ecx
movq 8(%rsp), %rdx
movl $9, %esi
movq (%rsp), %rdi
call _Z32__device_stub__Z8multiplyPKiiPiiPKiiPii
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z8multiplyPKiiPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPKiiPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC3:
.long 1232348160
.align 4
.LC4:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "practica1_6.hip"
.globl _Z23__device_stub__multiplyPKiiPii # -- Begin function _Z23__device_stub__multiplyPKiiPii
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPKiiPii,@function
_Z23__device_stub__multiplyPKiiPii: # @_Z23__device_stub__multiplyPKiiPii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPKiiPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPKiiPii, .Lfunc_end0-_Z23__device_stub__multiplyPKiiPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x49742400 # float 1.0E+6
.LCPI1_1:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $136, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
callq clock
movq %rax, %rbx
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movl $4, %edi
callq malloc
movq %rax, %r14
movl $0, (%rax)
movl $36, %edi
callq malloc
movq %rax, %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
callq rand
movslq %eax, %rsi
imulq $1717986919, %rsi, %rax # imm = 0x66666667
movq %rax, %rcx
shrq $63, %rcx
sarq $34, %rax
addl %ecx, %eax
addl %eax, %eax
leal (%rax,%rax,4), %eax
subl %eax, %esi
movl %esi, (%r15,%r12,4)
movl $.L.str, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
incq %r12
cmpq $9, %r12
jne .LBB1_1
# %bb.2:
movl $10, %edi
callq putchar@PLT
movl (%r14), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
leaq 16(%rsp), %rdi
movl $36, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4, %esi
callq hipMalloc
movq 16(%rsp), %rdi
movl $36, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $4, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_4
# %bb.3:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 88(%rsp)
movl $9, 28(%rsp)
movq %rcx, 80(%rsp)
movl $4, 24(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 28(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8multiplyPKiiPii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_4:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $4, %edx
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
movl (%r14), %esi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
movq %r15, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
callq clock
cvtsi2ss %rax, %xmm0
cvtsi2ss %rbx, %xmm1
subss %xmm1, %xmm0
divss .LCPI1_0(%rip), %xmm0
mulss .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.3, %edi
movb $1, %al
callq printf
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPKiiPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPKiiPii,@object # @_Z8multiplyPKiiPii
.section .rodata,"a",@progbits
.globl _Z8multiplyPKiiPii
.p2align 3, 0x0
_Z8multiplyPKiiPii:
.quad _Z23__device_stub__multiplyPKiiPii
.size _Z8multiplyPKiiPii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%i\t"
.size .L.str, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Sum of array: %i\n"
.size .L.str.2, 18
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Time elapsed: %f seconds\n"
.size .L.str.3, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPKiiPii"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPKiiPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPKiiPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "cuda_runtime.h"
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
__global__ void action(int *array1, int* array2, int* array_res)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
switch(i % 3)
{
case 0:
array_res[i] = array1[i] + 1;
break;
case 1:
array_res[i] = array2[i] - 1;
break;
case 2:
array_res[i] = array1[i] * array2[i];
break;
}
}
//////////////////
struct is_first
{
int p = -1;
__device__ __host__ bool operator() (int x)
{
return x ;
}
};
template<typename T>
struct first_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x + 1;
}
};
template<typename T>
struct second_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x - 1;
}
};
template<typename T>
struct third_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x + 1;
}
};
//////////////////
void array_print(int* array, int array_len, const char* message)
{
cout << " " << message << ":\n [ ";
for (int i = 0; i < array_len; i++)
{
cout << array[i] << " ";
}
cout << "]" << endl;
}
int main(int argc, char** argv)
{
int array_len, start, stop;
//Obtaining command line arguments
switch (argc)
{
case 1:
array_len = 15;
cout << " #Warning# Default array size: " << array_len << endl;
start = 0;
cout << " #Warning# Default random start: " << start << endl;
stop = 100;
cout << " #Warning# Default random stop: " << stop << endl;
cout << endl;
break;
case 2:
array_len = atoi(argv[1]);
start = 0;
cout << " #Warning# Default random start: " << start << endl;
stop = 100;
cout << " #Warning# Default random stop: " << stop << endl;
cout << endl;
break;
case 4:
array_len = atoi(argv[1]);
start = atoi(argv[2]);
stop = atoi(argv[3]);
cout << endl;
break;
default:
cout << "Wrong input!" << endl;
}
//Prepairing variables
int *array1 = new int[array_len];
int *array2 = new int[array_len];
int *array_res = new int[array_len];
int * d_array1, *d_array2, *d_array_res;
// thrust::device_vector<int> t_array1(array_len);
// thrust::device_vector<int> t_array2(array_len);
// thrust::device_vector<int> t_array_res(array_len);
cudaMalloc((void**)&d_array1, sizeof(int)*array_len);
cudaMalloc((void**)&d_array2, sizeof(int)*array_len);
cudaMalloc((void**)&d_array_res, sizeof(int)*array_len);
//Randomizing array
srand(time(NULL));
for (int i = 0; i < array_len; i++)
{
array1[i] = start + rand() % stop;
//t_array1[i] = array1[i];
array2[i] = start + rand() % stop;
//t_array2[i] = array2[i];
}
array_print(array1, array_len, "Array1");
array_print(array2, array_len, "Array2");
//Some copies
cudaMemcpy(d_array1, array1, sizeof(int) * array_len, cudaMemcpyHostToDevice);
cudaMemcpy(d_array2, array2, sizeof(int) * array_len, cudaMemcpyHostToDevice);
action<<<array_len, 1>>>(d_array1, d_array2, d_array_res);
cudaDeviceSynchronize();
//thrust::transform_if(thrust::device, t_array1.begin(), t_array1.end(),
// t_array2.begin(), first_func<int>(), is_first());
// for(int i = 0; i < array_len; i++)
// {
// cout << t_array2[i] << " ";
// }
// cout << endl;
//Some copies
cudaMemcpy(array_res, d_array_res, sizeof(int) * array_len, cudaMemcpyDeviceToHost);
array_print(array_res, array_len, "Res array");
delete[] array1, array2, array_res;
cudaFree(d_array1);
cudaFree(d_array2);
cudaFree(d_array_res);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6actionPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.HI R0, R6, 0x55555556, RZ ; /* 0x5555555606007827 */
/* 0x000fc800078e02ff */
/*0070*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe200078e0207 */
/*0080*/ LEA.HI R3, R0, R0, RZ, 0x1 ; /* 0x0000000000037211 */
/* 0x000fca00078f08ff */
/*0090*/ IMAD R0, R3, -0x3, R6 ; /* 0xfffffffd03007824 */
/* 0x000fe400078e0206 */
/*00a0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc600078e0207 */
/*00b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fd800078e0207 */
/*00d0*/ @!P0 BRA 0x1b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05270 */
/*00f0*/ @!P0 BRA 0x170 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f05270 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IADD3 R3, R4, -0x1, RZ ; /* 0xffffffff04037810 */
/* 0x004fca0007ffe0ff */
/*0190*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x004fca0007ffe0ff */
/*01d0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "cuda_runtime.h"
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
__global__ void action(int *array1, int* array2, int* array_res)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
switch(i % 3)
{
case 0:
array_res[i] = array1[i] + 1;
break;
case 1:
array_res[i] = array2[i] - 1;
break;
case 2:
array_res[i] = array1[i] * array2[i];
break;
}
}
//////////////////
struct is_first
{
int p = -1;
__device__ __host__ bool operator() (int x)
{
return x ;
}
};
template<typename T>
struct first_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x + 1;
}
};
template<typename T>
struct second_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x - 1;
}
};
template<typename T>
struct third_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x + 1;
}
};
//////////////////
void array_print(int* array, int array_len, const char* message)
{
cout << " " << message << ":\n [ ";
for (int i = 0; i < array_len; i++)
{
cout << array[i] << " ";
}
cout << "]" << endl;
}
int main(int argc, char** argv)
{
int array_len, start, stop;
//Obtaining command line arguments
switch (argc)
{
case 1:
array_len = 15;
cout << " #Warning# Default array size: " << array_len << endl;
start = 0;
cout << " #Warning# Default random start: " << start << endl;
stop = 100;
cout << " #Warning# Default random stop: " << stop << endl;
cout << endl;
break;
case 2:
array_len = atoi(argv[1]);
start = 0;
cout << " #Warning# Default random start: " << start << endl;
stop = 100;
cout << " #Warning# Default random stop: " << stop << endl;
cout << endl;
break;
case 4:
array_len = atoi(argv[1]);
start = atoi(argv[2]);
stop = atoi(argv[3]);
cout << endl;
break;
default:
cout << "Wrong input!" << endl;
}
//Prepairing variables
int *array1 = new int[array_len];
int *array2 = new int[array_len];
int *array_res = new int[array_len];
int * d_array1, *d_array2, *d_array_res;
// thrust::device_vector<int> t_array1(array_len);
// thrust::device_vector<int> t_array2(array_len);
// thrust::device_vector<int> t_array_res(array_len);
cudaMalloc((void**)&d_array1, sizeof(int)*array_len);
cudaMalloc((void**)&d_array2, sizeof(int)*array_len);
cudaMalloc((void**)&d_array_res, sizeof(int)*array_len);
//Randomizing array
srand(time(NULL));
for (int i = 0; i < array_len; i++)
{
array1[i] = start + rand() % stop;
//t_array1[i] = array1[i];
array2[i] = start + rand() % stop;
//t_array2[i] = array2[i];
}
array_print(array1, array_len, "Array1");
array_print(array2, array_len, "Array2");
//Some copies
cudaMemcpy(d_array1, array1, sizeof(int) * array_len, cudaMemcpyHostToDevice);
cudaMemcpy(d_array2, array2, sizeof(int) * array_len, cudaMemcpyHostToDevice);
action<<<array_len, 1>>>(d_array1, d_array2, d_array_res);
cudaDeviceSynchronize();
//thrust::transform_if(thrust::device, t_array1.begin(), t_array1.end(),
// t_array2.begin(), first_func<int>(), is_first());
// for(int i = 0; i < array_len; i++)
// {
// cout << t_array2[i] << " ";
// }
// cout << endl;
//Some copies
cudaMemcpy(array_res, d_array_res, sizeof(int) * array_len, cudaMemcpyDeviceToHost);
array_print(array_res, array_len, "Res array");
delete[] array1, array2, array_res;
cudaFree(d_array1);
cudaFree(d_array2);
cudaFree(d_array_res);
cudaDeviceReset();
return 0;
} | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "hip/hip_runtime.h"
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
__global__ void action(int *array1, int* array2, int* array_res)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
switch(i % 3)
{
case 0:
array_res[i] = array1[i] + 1;
break;
case 1:
array_res[i] = array2[i] - 1;
break;
case 2:
array_res[i] = array1[i] * array2[i];
break;
}
}
//////////////////
struct is_first
{
int p = -1;
__device__ __host__ bool operator() (int x)
{
return x ;
}
};
template<typename T>
struct first_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x + 1;
}
};
template<typename T>
struct second_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x - 1;
}
};
template<typename T>
struct third_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x + 1;
}
};
//////////////////
void array_print(int* array, int array_len, const char* message)
{
cout << " " << message << ":\n [ ";
for (int i = 0; i < array_len; i++)
{
cout << array[i] << " ";
}
cout << "]" << endl;
}
int main(int argc, char** argv)
{
int array_len, start, stop;
//Obtaining command line arguments
switch (argc)
{
case 1:
array_len = 15;
cout << " #Warning# Default array size: " << array_len << endl;
start = 0;
cout << " #Warning# Default random start: " << start << endl;
stop = 100;
cout << " #Warning# Default random stop: " << stop << endl;
cout << endl;
break;
case 2:
array_len = atoi(argv[1]);
start = 0;
cout << " #Warning# Default random start: " << start << endl;
stop = 100;
cout << " #Warning# Default random stop: " << stop << endl;
cout << endl;
break;
case 4:
array_len = atoi(argv[1]);
start = atoi(argv[2]);
stop = atoi(argv[3]);
cout << endl;
break;
default:
cout << "Wrong input!" << endl;
}
//Prepairing variables
int *array1 = new int[array_len];
int *array2 = new int[array_len];
int *array_res = new int[array_len];
int * d_array1, *d_array2, *d_array_res;
// thrust::device_vector<int> t_array1(array_len);
// thrust::device_vector<int> t_array2(array_len);
// thrust::device_vector<int> t_array_res(array_len);
hipMalloc((void**)&d_array1, sizeof(int)*array_len);
hipMalloc((void**)&d_array2, sizeof(int)*array_len);
hipMalloc((void**)&d_array_res, sizeof(int)*array_len);
//Randomizing array
srand(time(NULL));
for (int i = 0; i < array_len; i++)
{
array1[i] = start + rand() % stop;
//t_array1[i] = array1[i];
array2[i] = start + rand() % stop;
//t_array2[i] = array2[i];
}
array_print(array1, array_len, "Array1");
array_print(array2, array_len, "Array2");
//Some copies
hipMemcpy(d_array1, array1, sizeof(int) * array_len, hipMemcpyHostToDevice);
hipMemcpy(d_array2, array2, sizeof(int) * array_len, hipMemcpyHostToDevice);
action<<<array_len, 1>>>(d_array1, d_array2, d_array_res);
hipDeviceSynchronize();
//thrust::transform_if(thrust::device, t_array1.begin(), t_array1.end(),
// t_array2.begin(), first_func<int>(), is_first());
// for(int i = 0; i < array_len; i++)
// {
// cout << t_array2[i] << " ";
// }
// cout << endl;
//Some copies
hipMemcpy(array_res, d_array_res, sizeof(int) * array_len, hipMemcpyDeviceToHost);
array_print(array_res, array_len, "Res array");
delete[] array1, array2, array_res;
hipFree(d_array1);
hipFree(d_array2);
hipFree(d_array_res);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "hip/hip_runtime.h"
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
__global__ void action(int *array1, int* array2, int* array_res)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
switch(i % 3)
{
case 0:
array_res[i] = array1[i] + 1;
break;
case 1:
array_res[i] = array2[i] - 1;
break;
case 2:
array_res[i] = array1[i] * array2[i];
break;
}
}
//////////////////
struct is_first
{
int p = -1;
__device__ __host__ bool operator() (int x)
{
return x ;
}
};
template<typename T>
struct first_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x + 1;
}
};
template<typename T>
struct second_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x - 1;
}
};
template<typename T>
struct third_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x + 1;
}
};
//////////////////
void array_print(int* array, int array_len, const char* message)
{
cout << " " << message << ":\n [ ";
for (int i = 0; i < array_len; i++)
{
cout << array[i] << " ";
}
cout << "]" << endl;
}
int main(int argc, char** argv)
{
int array_len, start, stop;
//Obtaining command line arguments
switch (argc)
{
case 1:
array_len = 15;
cout << " #Warning# Default array size: " << array_len << endl;
start = 0;
cout << " #Warning# Default random start: " << start << endl;
stop = 100;
cout << " #Warning# Default random stop: " << stop << endl;
cout << endl;
break;
case 2:
array_len = atoi(argv[1]);
start = 0;
cout << " #Warning# Default random start: " << start << endl;
stop = 100;
cout << " #Warning# Default random stop: " << stop << endl;
cout << endl;
break;
case 4:
array_len = atoi(argv[1]);
start = atoi(argv[2]);
stop = atoi(argv[3]);
cout << endl;
break;
default:
cout << "Wrong input!" << endl;
}
//Prepairing variables
int *array1 = new int[array_len];
int *array2 = new int[array_len];
int *array_res = new int[array_len];
int * d_array1, *d_array2, *d_array_res;
// thrust::device_vector<int> t_array1(array_len);
// thrust::device_vector<int> t_array2(array_len);
// thrust::device_vector<int> t_array_res(array_len);
hipMalloc((void**)&d_array1, sizeof(int)*array_len);
hipMalloc((void**)&d_array2, sizeof(int)*array_len);
hipMalloc((void**)&d_array_res, sizeof(int)*array_len);
//Randomizing array
srand(time(NULL));
for (int i = 0; i < array_len; i++)
{
array1[i] = start + rand() % stop;
//t_array1[i] = array1[i];
array2[i] = start + rand() % stop;
//t_array2[i] = array2[i];
}
array_print(array1, array_len, "Array1");
array_print(array2, array_len, "Array2");
//Some copies
hipMemcpy(d_array1, array1, sizeof(int) * array_len, hipMemcpyHostToDevice);
hipMemcpy(d_array2, array2, sizeof(int) * array_len, hipMemcpyHostToDevice);
action<<<array_len, 1>>>(d_array1, d_array2, d_array_res);
hipDeviceSynchronize();
//thrust::transform_if(thrust::device, t_array1.begin(), t_array1.end(),
// t_array2.begin(), first_func<int>(), is_first());
// for(int i = 0; i < array_len; i++)
// {
// cout << t_array2[i] << " ";
// }
// cout << endl;
//Some copies
hipMemcpy(array_res, d_array_res, sizeof(int) * array_len, hipMemcpyDeviceToHost);
array_print(array_res, array_len, "Res array");
delete[] array1, array2, array_res;
hipFree(d_array1);
hipFree(d_array2);
hipFree(d_array_res);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6actionPiS_S_
.globl _Z6actionPiS_S_
.p2align 8
.type _Z6actionPiS_S_,@function
_Z6actionPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_mov_b32 s4, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x0
v_mul_hi_i32 v0, v1, 0x55555556
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 1, v0
v_sub_nc_u32_e32 v3, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v3
s_xor_b32 s6, exec_lo, s5
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s7, exec_lo
v_cmpx_lt_i32_e32 1, v3
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v3, v0
.LBB0_3:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, -1, v0
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_mov_b32 s4, exec_lo
.LBB0_6:
s_and_not1_saveexec_b32 s5, s6
s_cbranch_execz .LBB0_10
s_mov_b32 s7, s4
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v2, 31, v1
s_or_b32 s7, s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 1, v0
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt lgkmcnt(0)
s_and_not1_b32 s2, s4, exec_lo
s_and_b32 s3, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s4, s2, s3
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_and_saveexec_b32 s2, s4
s_cbranch_execz .LBB0_12
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6actionPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6actionPiS_S_, .Lfunc_end0-_Z6actionPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6actionPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6actionPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <cstdlib>
#include <ctime>
#include "hip/hip_runtime.h"
#include <thrust/host_vector.h>
#include <thrust/device_vector.h>
using namespace std;
__global__ void action(int *array1, int* array2, int* array_res)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;
switch(i % 3)
{
case 0:
array_res[i] = array1[i] + 1;
break;
case 1:
array_res[i] = array2[i] - 1;
break;
case 2:
array_res[i] = array1[i] * array2[i];
break;
}
}
//////////////////
struct is_first
{
int p = -1;
__device__ __host__ bool operator() (int x)
{
return x ;
}
};
template<typename T>
struct first_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x + 1;
}
};
template<typename T>
struct second_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x - 1;
}
};
template<typename T>
struct third_func
{
__device__ __host__ T operator ()( const T& x ) const
{
return x + 1;
}
};
//////////////////
void array_print(int* array, int array_len, const char* message)
{
cout << " " << message << ":\n [ ";
for (int i = 0; i < array_len; i++)
{
cout << array[i] << " ";
}
cout << "]" << endl;
}
int main(int argc, char** argv)
{
int array_len, start, stop;
//Obtaining command line arguments
switch (argc)
{
case 1:
array_len = 15;
cout << " #Warning# Default array size: " << array_len << endl;
start = 0;
cout << " #Warning# Default random start: " << start << endl;
stop = 100;
cout << " #Warning# Default random stop: " << stop << endl;
cout << endl;
break;
case 2:
array_len = atoi(argv[1]);
start = 0;
cout << " #Warning# Default random start: " << start << endl;
stop = 100;
cout << " #Warning# Default random stop: " << stop << endl;
cout << endl;
break;
case 4:
array_len = atoi(argv[1]);
start = atoi(argv[2]);
stop = atoi(argv[3]);
cout << endl;
break;
default:
cout << "Wrong input!" << endl;
}
//Prepairing variables
int *array1 = new int[array_len];
int *array2 = new int[array_len];
int *array_res = new int[array_len];
int * d_array1, *d_array2, *d_array_res;
// thrust::device_vector<int> t_array1(array_len);
// thrust::device_vector<int> t_array2(array_len);
// thrust::device_vector<int> t_array_res(array_len);
hipMalloc((void**)&d_array1, sizeof(int)*array_len);
hipMalloc((void**)&d_array2, sizeof(int)*array_len);
hipMalloc((void**)&d_array_res, sizeof(int)*array_len);
//Randomizing array
srand(time(NULL));
for (int i = 0; i < array_len; i++)
{
array1[i] = start + rand() % stop;
//t_array1[i] = array1[i];
array2[i] = start + rand() % stop;
//t_array2[i] = array2[i];
}
array_print(array1, array_len, "Array1");
array_print(array2, array_len, "Array2");
//Some copies
hipMemcpy(d_array1, array1, sizeof(int) * array_len, hipMemcpyHostToDevice);
hipMemcpy(d_array2, array2, sizeof(int) * array_len, hipMemcpyHostToDevice);
action<<<array_len, 1>>>(d_array1, d_array2, d_array_res);
hipDeviceSynchronize();
//thrust::transform_if(thrust::device, t_array1.begin(), t_array1.end(),
// t_array2.begin(), first_func<int>(), is_first());
// for(int i = 0; i < array_len; i++)
// {
// cout << t_array2[i] << " ";
// }
// cout << endl;
//Some copies
hipMemcpy(array_res, d_array_res, sizeof(int) * array_len, hipMemcpyDeviceToHost);
array_print(array_res, array_len, "Res array");
delete[] array1, array2, array_res;
hipFree(d_array1);
hipFree(d_array2);
hipFree(d_array_res);
hipDeviceReset();
return 0;
} | .text
.file "paper.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__actionPiS_S_ # -- Begin function _Z21__device_stub__actionPiS_S_
.p2align 4, 0x90
.type _Z21__device_stub__actionPiS_S_,@function
_Z21__device_stub__actionPiS_S_: # @_Z21__device_stub__actionPiS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6actionPiS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z21__device_stub__actionPiS_S_, .Lfunc_end0-_Z21__device_stub__actionPiS_S_
.cfi_endproc
# -- End function
.globl _Z11array_printPiiPKc # -- Begin function _Z11array_printPiiPKc
.p2align 4, 0x90
.type _Z11array_printPiiPKc,@function
_Z11array_printPiiPKc: # @_Z11array_printPiiPKc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdx, %r14
movl %esi, %ebp
movq %rdi, %rbx
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testq %r14, %r14
je .LBB1_1
# %bb.2:
movq %r14, %rdi
callq strlen
movl $_ZSt4cout, %edi
movq %r14, %rsi
movq %rax, %rdx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
jmp .LBB1_3
.LBB1_1:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
leaq _ZSt4cout(%rax), %rdi
movl _ZSt4cout+32(%rax), %esi
orl $1, %esi
callq _ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_3: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
testl %ebp, %ebp
jle .LBB1_6
# %bb.4: # %.lr.ph.preheader
movl %ebp, %r14d
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_5: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r15,4), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r15
cmpq %r15, %r14
jne .LBB1_5
.LBB1_6: # %._crit_edge
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $1, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB1_11
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB1_9
# %bb.8:
movzbl 67(%rbx), %eax
jmp .LBB1_10
.LBB1_9:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp _ZNSo5flushEv # TAILCALL
.LBB1_11:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size _Z11array_printPiiPKc, .Lfunc_end1-_Z11array_printPiiPKc
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
cmpl $4, %edi
je .LBB2_33
# %bb.1:
cmpl $2, %edi
je .LBB2_21
# %bb.2:
cmpl $1, %edi
jne .LBB2_37
# %bb.3:
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $31, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $15, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_48
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB2_6
# %bb.5:
movzbl 67(%rbx), %ecx
jmp .LBB2_7
.LBB2_21:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
xorl %esi, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_48
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%rbx)
je .LBB2_24
# %bb.23:
movzbl 67(%rbx), %ecx
jmp .LBB2_25
.LBB2_33:
movq 8(%rsi), %rdi
movq %rsi, %rbx
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_48
# %bb.34: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i76
cmpb $0, 56(%rbx)
je .LBB2_36
# %bb.35:
movzbl 67(%rbx), %eax
jmp .LBB2_42
.LBB2_37:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_48
# %bb.38: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i81
cmpb $0, 56(%rbx)
je .LBB2_40
# %bb.39:
movzbl 67(%rbx), %eax
jmp .LBB2_41
.LBB2_24:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $100, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_48
# %bb.26: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i66
cmpb $0, 56(%rbx)
je .LBB2_28
# %bb.27:
movzbl 67(%rbx), %ecx
jmp .LBB2_29
.LBB2_36:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB2_42
.LBB2_6:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $33, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
xorl %esi, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_48
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%rbx)
je .LBB2_10
# %bb.9:
movzbl 67(%rbx), %ecx
jmp .LBB2_11
.LBB2_40:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_41: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
# implicit-def: $ebp
# implicit-def: $r12d
# implicit-def: $r15d
jmp .LBB2_42
.LBB2_28:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_29: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit69
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_48
# %bb.30: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i71
cmpb $0, 56(%rbx)
je .LBB2_32
# %bb.31:
movzbl 67(%rbx), %eax
jmp .LBB2_19
.LBB2_10:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $32, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $100, %esi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB2_48
# %bb.12: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%rbx)
je .LBB2_14
# %bb.13:
movzbl 67(%rbx), %ecx
jmp .LBB2_15
.LBB2_32:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB2_19
.LBB2_14:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB2_15: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB2_48
# %bb.16: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%rbx)
je .LBB2_20
# %bb.17:
movzbl 67(%rbx), %eax
jmp .LBB2_18
.LBB2_20:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movl $15, %r15d
.LBB2_19: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
xorl %r12d, %r12d
movl $100, %ebp
.LBB2_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit59
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %r15, 24(%rsp) # 8-byte Spill
movslq %r15d, %rax
movq %rax, 32(%rsp) # 8-byte Spill
leaq (,%rax,4), %r15
testl %eax, %eax
movq $-1, %r13
cmovnsq %r15, %r13
movq %r13, %rdi
callq _Znam
movq %rax, %r14
movq %r13, %rdi
callq _Znam
movq %rax, %rbx
movq %r13, %rdi
callq _Znam
movq %rax, 40(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
movq %rsp, %rdi
movq %r15, 48(%rsp) # 8-byte Spill
movq %r15, %rsi
callq hipMalloc
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl 24(%rsp), %r13d # 4-byte Reload
cmpl $0, 32(%rsp) # 4-byte Folded Reload
jle .LBB2_45
# %bb.43: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_44: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltd
idivl %ebp
addl %r12d, %edx
movl %edx, (%r14,%r15,4)
callq rand
cltd
idivl %ebp
addl %r12d, %edx
movl %edx, (%rbx,%r15,4)
incq %r15
cmpq %r15, %r13
jne .LBB2_44
.LBB2_45: # %._crit_edge
movl $.L.str.7, %edx
movq %r14, %rdi
movq 24(%rsp), %r15 # 8-byte Reload
movl %r15d, %esi
callq _Z11array_printPiiPKc
movl $.L.str.8, %edx
movq %rbx, %rdi
movl %r15d, %esi
callq _Z11array_printPiiPKc
movq 16(%rsp), %rdi
movq %r14, %rsi
movq 48(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r13
orq $1, %rdx
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_47
# %bb.46:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq (%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z6actionPiS_S_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_47:
callq hipDeviceSynchronize
movq (%rsp), %rsi
movq 40(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl $.L.str.9, %edx
movq %rbx, %rdi
movl %r15d, %esi
callq _Z11array_printPiiPKc
movq %r14, %rdi
callq _ZdaPv
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_48:
.cfi_def_cfa_offset 208
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6actionPiS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6actionPiS_S_,@object # @_Z6actionPiS_S_
.section .rodata,"a",@progbits
.globl _Z6actionPiS_S_
.p2align 3, 0x0
_Z6actionPiS_S_:
.quad _Z21__device_stub__actionPiS_S_
.size _Z6actionPiS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz ":\n [ "
.size .L.str.1, 6
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "]"
.size .L.str.2, 2
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " #Warning# Default array size: "
.size .L.str.3, 32
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " #Warning# Default random start: "
.size .L.str.4, 34
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " #Warning# Default random stop: "
.size .L.str.5, 33
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Wrong input!"
.size .L.str.6, 13
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Array1"
.size .L.str.7, 7
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Array2"
.size .L.str.8, 7
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Res array"
.size .L.str.9, 10
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6actionPiS_S_"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__actionPiS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6actionPiS_S_
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6actionPiS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fc800078e0203 */
/*0060*/ IMAD.HI R0, R6, 0x55555556, RZ ; /* 0x5555555606007827 */
/* 0x000fc800078e02ff */
/*0070*/ IMAD.WIDE R4, R6, R7, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x000fe200078e0207 */
/*0080*/ LEA.HI R3, R0, R0, RZ, 0x1 ; /* 0x0000000000037211 */
/* 0x000fca00078f08ff */
/*0090*/ IMAD R0, R3, -0x3, R6 ; /* 0xfffffffd03007824 */
/* 0x000fe400078e0206 */
/*00a0*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x000fc600078e0207 */
/*00b0*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f05270 */
/*00c0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fd800078e0207 */
/*00d0*/ @!P0 BRA 0x1b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.NE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fda0003f05270 */
/*00f0*/ @!P0 BRA 0x170 ; /* 0x0000007000008947 */
/* 0x000fea0003800000 */
/*0100*/ ISETP.NE.AND P0, PT, R0, 0x2, PT ; /* 0x000000020000780c */
/* 0x000fda0003f05270 */
/*0110*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0120*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*0140*/ IMAD R9, R2, R5, RZ ; /* 0x0000000502097224 */
/* 0x004fca00078e02ff */
/*0150*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IADD3 R3, R4, -0x1, RZ ; /* 0xffffffff04037810 */
/* 0x004fca0007ffe0ff */
/*0190*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*01c0*/ IADD3 R5, R2, 0x1, RZ ; /* 0x0000000102057810 */
/* 0x004fca0007ffe0ff */
/*01d0*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x000fe2000c101904 */
/*01e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01f0*/ BRA 0x1f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6actionPiS_S_
.globl _Z6actionPiS_S_
.p2align 8
.type _Z6actionPiS_S_,@function
_Z6actionPiS_S_:
s_load_b32 s2, s[0:1], 0x24
s_mov_b32 s4, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_load_b64 s[2:3], s[0:1], 0x0
v_mul_hi_i32 v0, v1, 0x55555556
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v2, 31, v0
v_add_nc_u32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshl_add_u32 v0, v0, 1, v0
v_sub_nc_u32_e32 v3, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e32 0, v3
s_xor_b32 s6, exec_lo, s5
s_cbranch_execz .LBB0_6
s_load_b64 s[4:5], s[0:1], 0x8
s_mov_b32 s7, exec_lo
v_cmpx_lt_i32_e32 1, v3
s_xor_b32 s7, exec_lo, s7
s_cbranch_execz .LBB0_3
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v4, vcc_lo
v_add_co_u32 v3, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[5:6], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_mul_lo_u32 v0, v3, v0
.LBB0_3:
s_and_not1_saveexec_b32 s7, s7
s_cbranch_execz .LBB0_5
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, -1, v0
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s7
s_waitcnt lgkmcnt(0)
s_mov_b32 s4, exec_lo
.LBB0_6:
s_and_not1_saveexec_b32 s5, s6
s_cbranch_execz .LBB0_10
s_mov_b32 s7, s4
s_mov_b32 s6, exec_lo
v_cmpx_eq_u32_e32 0, v3
s_cbranch_execz .LBB0_9
v_ashrrev_i32_e32 v2, 31, v1
s_or_b32 s7, s4, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, 1, v0
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s6
s_waitcnt lgkmcnt(0)
s_and_not1_b32 s2, s4, exec_lo
s_and_b32 s3, s7, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s4, s2, s3
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_and_saveexec_b32 s2, s4
s_cbranch_execz .LBB0_12
s_load_b64 s[0:1], s[0:1], 0x10
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v0, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6actionPiS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6actionPiS_S_, .Lfunc_end0-_Z6actionPiS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6actionPiS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6actionPiS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex cufftDoubleComplex
#define Real double
#define Transform CUFFT_Z2Z
#define TransformExec cufftExecZ2Z
#else
#define Complex cufftComplex
#define Real float
#define Transform CUFFT_C2C
#define TransformExec cufftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = (tid >= spitch) ? src[bid * spitch + tid-spitch] : 0.0;
if( tid < dpitch) {
dst[bid * dpitch + tid] = res;
}
} | code for sm_80
Function : _Z6spreadPdjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x110 ; /* 0x000000d000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5.reuse, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x041fe40003f06070 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe20003f26070 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fc400078e0203 */
/*0090*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fd0000001ff00 */
/*00a0*/ @!P0 BRA 0x100 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fe200000001ff */
/*00c0*/ IADD3 R3, R5, -c[0x0][0x168], RZ ; /* 0x80005a0005037a10 */
/* 0x000fca0007ffe0ff */
/*00d0*/ IMAD R3, R0, c[0x0][0x168], R3 ; /* 0x00005a0000037a24 */
/* 0x000fc800078e0203 */
/*00e0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0002 */
/*00f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f64000c1e1b00 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0120*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD R4, R0, c[0x0][0x178], R5 ; /* 0x00005e0000047a24 */
/* 0x000fc800078e0205 */
/*0140*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0007 */
/*0150*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x020fe2000c101b04 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex cufftDoubleComplex
#define Real double
#define Transform CUFFT_Z2Z
#define TransformExec cufftExecZ2Z
#else
#define Complex cufftComplex
#define Real float
#define Transform CUFFT_C2C
#define TransformExec cufftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = (tid >= spitch) ? src[bid * spitch + tid-spitch] : 0.0;
if( tid < dpitch) {
dst[bid * dpitch + tid] = res;
}
} | .file "tmpxft_0019f41e_00000000-6_spread.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6spreadPdjS_jPdjS_j
.type _Z29__device_stub__Z6spreadPdjS_jPdjS_j, @function
_Z29__device_stub__Z6spreadPdjS_jPdjS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6spreadPdjS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6spreadPdjS_jPdjS_j, .-_Z29__device_stub__Z6spreadPdjS_jPdjS_j
.globl _Z6spreadPdjS_j
.type _Z6spreadPdjS_j, @function
_Z6spreadPdjS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6spreadPdjS_jPdjS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6spreadPdjS_j, .-_Z6spreadPdjS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6spreadPdjS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6spreadPdjS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex cufftDoubleComplex
#define Real double
#define Transform CUFFT_Z2Z
#define TransformExec cufftExecZ2Z
#else
#define Complex cufftComplex
#define Real float
#define Transform CUFFT_C2C
#define TransformExec cufftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = (tid >= spitch) ? src[bid * spitch + tid-spitch] : 0.0;
if( tid < dpitch) {
dst[bid * dpitch + tid] = res;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex hipfftDoubleComplex
#define Real double
#define Transform HIPFFT_Z2Z
#define TransformExec hipfftExecZ2Z
#else
#define Complex hipfftComplex
#define Real float
#define Transform HIPFFT_C2C
#define TransformExec hipfftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = (tid >= spitch) ? src[bid * spitch + tid-spitch] : 0.0;
if( tid < dpitch) {
dst[bid * dpitch + tid] = res;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex hipfftDoubleComplex
#define Real double
#define Transform HIPFFT_Z2Z
#define TransformExec hipfftExecZ2Z
#else
#define Complex hipfftComplex
#define Real float
#define Transform HIPFFT_C2C
#define TransformExec hipfftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = (tid >= spitch) ? src[bid * spitch + tid-spitch] : 0.0;
if( tid < dpitch) {
dst[bid * dpitch + tid] = res;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6spreadPdjS_j
.globl _Z6spreadPdjS_j
.p2align 8
.type _Z6spreadPdjS_j,@function
_Z6spreadPdjS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x20
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
v_cmpx_le_u32_e64 s4, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_subrev_nc_u32_e32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s4, v[1:2]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[1:2], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0x18
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, s2, s3, v[0:1]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6spreadPdjS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6spreadPdjS_j, .Lfunc_end0-_Z6spreadPdjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6spreadPdjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6spreadPdjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define DOUBLE
#ifdef DOUBLE
#define Complex hipfftDoubleComplex
#define Real double
#define Transform HIPFFT_Z2Z
#define TransformExec hipfftExecZ2Z
#else
#define Complex hipfftComplex
#define Real float
#define Transform HIPFFT_C2C
#define TransformExec hipfftExecC2C
#endif
#define TILE_DIM 8
// synchronize blocks
__global__ void spread(Real* src, unsigned int spitch, Real* dst, unsigned int dpitch)
{
unsigned int bid = blockIdx.y * gridDim.x + blockIdx.x;
unsigned int tid = threadIdx.x;
Real res = (tid >= spitch) ? src[bid * spitch + tid-spitch] : 0.0;
if( tid < dpitch) {
dst[bid * dpitch + tid] = res;
}
} | .text
.file "spread.hip"
.globl _Z21__device_stub__spreadPdjS_j # -- Begin function _Z21__device_stub__spreadPdjS_j
.p2align 4, 0x90
.type _Z21__device_stub__spreadPdjS_j,@function
_Z21__device_stub__spreadPdjS_j: # @_Z21__device_stub__spreadPdjS_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6spreadPdjS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__spreadPdjS_j, .Lfunc_end0-_Z21__device_stub__spreadPdjS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6spreadPdjS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6spreadPdjS_j,@object # @_Z6spreadPdjS_j
.section .rodata,"a",@progbits
.globl _Z6spreadPdjS_j
.p2align 3, 0x0
_Z6spreadPdjS_j:
.quad _Z21__device_stub__spreadPdjS_j
.size _Z6spreadPdjS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6spreadPdjS_j"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__spreadPdjS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6spreadPdjS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6spreadPdjS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x110 ; /* 0x000000d000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0050*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e620000002500 */
/*0060*/ ISETP.GE.U32.AND P0, PT, R5.reuse, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x041fe40003f06070 */
/*0070*/ ISETP.GE.U32.AND P1, PT, R5, c[0x0][0x178], PT ; /* 0x00005e0005007a0c */
/* 0x000fe20003f26070 */
/*0080*/ IMAD R0, R0, c[0x0][0xc], R3 ; /* 0x0000030000007a24 */
/* 0x002fc400078e0203 */
/*0090*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fd0000001ff00 */
/*00a0*/ @!P0 BRA 0x100 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fe200000001ff */
/*00c0*/ IADD3 R3, R5, -c[0x0][0x168], RZ ; /* 0x80005a0005037a10 */
/* 0x000fca0007ffe0ff */
/*00d0*/ IMAD R3, R0, c[0x0][0x168], R3 ; /* 0x00005a0000037a24 */
/* 0x000fc800078e0203 */
/*00e0*/ IMAD.WIDE.U32 R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fcc00078e0002 */
/*00f0*/ LDG.E.64 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000f64000c1e1b00 */
/*0100*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0110*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0120*/ MOV R7, 0x8 ; /* 0x0000000800077802 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD R4, R0, c[0x0][0x178], R5 ; /* 0x00005e0000047a24 */
/* 0x000fc800078e0205 */
/*0140*/ IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fca00078e0007 */
/*0150*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x020fe2000c101b04 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6spreadPdjS_j
.globl _Z6spreadPdjS_j
.p2align 8
.type _Z6spreadPdjS_j,@function
_Z6spreadPdjS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x8
s_load_b32 s2, s[0:1], 0x20
v_mov_b32_e32 v1, 0
v_mov_b32_e32 v2, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_mul_i32 s2, s2, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s2, s14
v_cmpx_le_u32_e64 s4, v0
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_subrev_nc_u32_e32 v1, s4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s2, s4, v[1:2]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[1:2], 3, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b64 v[1:2], v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s3
s_load_b32 s3, s[0:1], 0x18
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB0_4
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, s2, s3, v[0:1]
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 3, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s0, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
global_store_b64 v[3:4], v[1:2], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6spreadPdjS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6spreadPdjS_j, .Lfunc_end0-_Z6spreadPdjS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6spreadPdjS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6spreadPdjS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0019f41e_00000000-6_spread.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z6spreadPdjS_jPdjS_j
.type _Z29__device_stub__Z6spreadPdjS_jPdjS_j, @function
_Z29__device_stub__Z6spreadPdjS_jPdjS_j:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 16(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 16(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6spreadPdjS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z29__device_stub__Z6spreadPdjS_jPdjS_j, .-_Z29__device_stub__Z6spreadPdjS_jPdjS_j
.globl _Z6spreadPdjS_j
.type _Z6spreadPdjS_j, @function
_Z6spreadPdjS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6spreadPdjS_jPdjS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z6spreadPdjS_j, .-_Z6spreadPdjS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6spreadPdjS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6spreadPdjS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "spread.hip"
.globl _Z21__device_stub__spreadPdjS_j # -- Begin function _Z21__device_stub__spreadPdjS_j
.p2align 4, 0x90
.type _Z21__device_stub__spreadPdjS_j,@function
_Z21__device_stub__spreadPdjS_j: # @_Z21__device_stub__spreadPdjS_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6spreadPdjS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__spreadPdjS_j, .Lfunc_end0-_Z21__device_stub__spreadPdjS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6spreadPdjS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6spreadPdjS_j,@object # @_Z6spreadPdjS_j
.section .rodata,"a",@progbits
.globl _Z6spreadPdjS_j
.p2align 3, 0x0
_Z6spreadPdjS_j:
.quad _Z21__device_stub__spreadPdjS_j
.size _Z6spreadPdjS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6spreadPdjS_j"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__spreadPdjS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6spreadPdjS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#define N 4;
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
//__global__ void addKernel(int *c, const int *a, const int *b)
//{
// int i = threadIdx.x;
// c[i] = a[i] + b[i];
//}
__global__ void addKernel(double *a, double *b, double *c,int size)
{
int i = threadIdx.x;
for(int k = 0;k<size; k++)
{
if(i < size)
c[i] += a[i*size+k] * b[k];
}
}
void simple_dgemv(double *A, double *B, double *C,int size)
{
int i,j;
for(i = 0;i < size; i++)
{
double prod = 0;
for(j = 0;j < size; j++)
{
prod += A[i * size + j] * B[j];
}
C[i] = prod;
}
}
//__global__ void MVKernel_gm(double *A, double *X, double *Y,int ARRAY_SIZE)
//{
// //int bx = blockIdx.x;
// //int by = blockIdx.y;
// int tid = threadIdx.x;
// //int ty = threadIdx.y;
// // Calculate the row index of the Pd element and M
// //int Row = bx * BLOCK_SIZE + tx;
// // Calculate the column idenx of Pd and N
// //int Col = bx * BLOCK_SIZE + tx;
//
// double tmpSum = 0;
//
// for (int k = 0; k < ARRAY_SIZE; k++)
// {
// if(tid < ARRAY_SIZE)
// tmpSum += A[tid*ARRAY_SIZE+k] * X[k];
// }
//
// __syncthreads();
//
// if(tid < ARRAY_SIZE)
// Y[tid] = tmpSum;
//
// __syncthreads();
//}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
int ARRAY_SIZE = 5;
int ARRAY_SIZE2 = ARRAY_SIZE*ARRAY_SIZE;
//Host
double *h_a;
double *h_b;
double *h_c;
//Device
double *d_a;
double *d_b;
double *d_c;
//generate the input array on the host
h_a=(double*)malloc(sizeof(double)*ARRAY_SIZE2);
h_b=(double*)malloc(sizeof(double)*ARRAY_SIZE);
h_c=(double*)malloc(sizeof(double)*ARRAY_SIZE);
//inital the h_a, h_b
for(int i = 0;i<ARRAY_SIZE2;i++){
h_a[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_b[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_c[i] = double(0);
}
////print out test
//printf("\nThe vector A is:\n");
//for(int i=0;i<ARRAY_SIZE2;i++){
// printf("%f", h_a[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//printf("\nThe Matrix X is:\n");
//for(int i=0;i<ARRAY_SIZE;i++){
// printf("%f", h_b[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addWithCuda failed!");
// return 1;
//}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
//// cudaDeviceReset must be called before exiting in order for profiling and
//// tracing tools such as Nsight and Visual Profiler to show complete traces.
//cudaStatus = cudaDeviceReset();
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceReset failed!");
// return 1;
//}
//allocate GPU memory
cudaMalloc((void**)&d_a, sizeof(double)*ARRAY_SIZE2);
cudaMalloc((void**)&d_b, sizeof(double)*ARRAY_SIZE);
cudaMalloc((void**)&d_c, sizeof(double)*ARRAY_SIZE);
//transfer the array from Host to device(CPU->GPU)
cudaMemcpy(d_a, h_a, sizeof(double)*ARRAY_SIZE2, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sizeof(double)*ARRAY_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, h_c, sizeof(double)*ARRAY_SIZE, cudaMemcpyHostToDevice);
//Run kernel function calculate the matrix-vector multiplication
printf("\n\nRunning Kernel...\n\n");
//MVKernel_gm<<<1,256>>>(d_a, d_b, d_c, ARRAY_SIZE);//ARRAY_SIZE/256+1, 256
addKernel<<<1, ARRAY_SIZE>>>(d_a,d_b,d_c,ARRAY_SIZE);
//transfer the array from Device to Host(GPU->CPU)
//cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c, d_c, sizeof(double)*ARRAY_SIZE, cudaMemcpyDeviceToHost);
//print out the result array
for(int i = 0; i<ARRAY_SIZE;i++){
printf("%f\n", h_c[i]);
//printf(((i%4)!=3)? "\t" : "\n");
}
//free GPU memory allocation
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
//free Host memory allocation
free(h_a);
free(h_b);
free(h_c);
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
//{
// int *dev_a = 0;
// int *dev_b = 0;
// int *dev_c = 0;
// cudaError_t cudaStatus;
//
// // Choose which GPU to run on, change this on a multi-GPU system.
// cudaStatus = cudaSetDevice(0);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
// }
//
// // Allocate GPU buffers for three vectors (two input, one output) .
// cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// // Copy input vectors from host memory to GPU buffers.
// cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// // Launch a kernel on the GPU with one thread for each element.
// //addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
//
// // Check for any errors launching the kernel
// cudaStatus = cudaGetLastError();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
// }
//
// // cudaDeviceSynchronize waits for the kernel to finish, and returns
// // any errors encountered during the launch.
// cudaStatus = cudaDeviceSynchronize();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
// goto Error;
// }
//
// // Copy output vector from GPU buffer to host memory.
// cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
//Error:
// cudaFree(dev_c);
// cudaFree(dev_a);
// cudaFree(dev_b);
//
//
//
// return cudaStatus;
//} | code for sm_80
Function : _Z9addKernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0050*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe20007ffe0ff */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe200078ec0ff */
/*0090*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*00b0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fd800078e0207 */
/*00c0*/ @!P0 BRA 0x10e0 ; /* 0x0000101000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R10, -R8, c[0x0][0x178], RZ ; /* 0x00005e00080a7a10 */
/* 0x000fe20007ffe1ff */
/*00e0*/ IMAD R6, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a24 */
/* 0x000fe400078e02ff */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f04270 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fd000078e0207 */
/*0140*/ @!P0 BRA 0xea0 ; /* 0x00000d5000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0170*/ @!P1 BRA 0xa00 ; /* 0x0000088000009947 */
/* 0x000fea0003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0190*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fd80003f26270 */
/*01a0*/ BSSY B0, 0x220 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*01b0*/ @P1 BRA 0x210 ; /* 0x0000005000001947 */
/* 0x001fea0003800000 */
/*01c0*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea8000c1e1b00 */
/*01d0*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*01e0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*01f0*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0200*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ BSSY B0, 0x2a0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0230*/ @P1 BRA 0x290 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0240*/ LDG.E.64 R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0250*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0270*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0280*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ BSSY B0, 0x320 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*02b0*/ @P1 BRA 0x310 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x001ea8000c1e1b00 */
/*02d0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ea8000c1e1b00 */
/*02e0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*02f0*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0300*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ BSSY B0, 0x3a0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0330*/ @P1 BRA 0x390 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0350*/ LDG.E.64 R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0360*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0370*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0380*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f26270 */
/*03b0*/ BSSY B0, 0x430 ; /* 0x0000007000007945 */
/* 0x000fd80003800000 */
/*03c0*/ @P1 BRA 0x420 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*03d0*/ LDG.E.64 R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x001ea8000c1e1b00 */
/*03e0*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000ea8000c1e1b00 */
/*03f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0400*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0410*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ BSSY B0, 0x4b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0440*/ @P1 BRA 0x4a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E.64 R12, [R4.64+0x28] ; /* 0x00002804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0460*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0470*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0480*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0490*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ BSSY B0, 0x530 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*04c0*/ @P1 BRA 0x520 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*04d0*/ LDG.E.64 R12, [R4.64+0x30] ; /* 0x00003004040c7981 */
/* 0x001ea8000c1e1b00 */
/*04e0*/ LDG.E.64 R14, [R6.64+0x30] ; /* 0x00003004060e7981 */
/* 0x000ea8000c1e1b00 */
/*04f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0500*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0510*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ BSSY B0, 0x5b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0540*/ @P1 BRA 0x5a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E.64 R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0560*/ LDG.E.64 R14, [R6.64+0x38] ; /* 0x00003804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0570*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0580*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0590*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*05a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05b0*/ BSSY B0, 0x630 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*05c0*/ @P1 BRA 0x620 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E.64 R12, [R6.64+0x40] ; /* 0x00004004060c7981 */
/* 0x001ea8000c1e1b00 */
/*05e0*/ LDG.E.64 R14, [R4.64+0x40] ; /* 0x00004004040e7981 */
/* 0x000ea8000c1e1b00 */
/*05f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0600*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0610*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ BSSY B0, 0x6b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0640*/ @P1 BRA 0x6a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0650*/ LDG.E.64 R12, [R4.64+0x48] ; /* 0x00004804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0660*/ LDG.E.64 R14, [R6.64+0x48] ; /* 0x00004804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0670*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0680*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0690*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*06a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06b0*/ BSSY B0, 0x730 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*06c0*/ @P1 BRA 0x720 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*06d0*/ LDG.E.64 R12, [R4.64+0x50] ; /* 0x00005004040c7981 */
/* 0x001ea8000c1e1b00 */
/*06e0*/ LDG.E.64 R14, [R6.64+0x50] ; /* 0x00005004060e7981 */
/* 0x000ea8000c1e1b00 */
/*06f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0700*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0710*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ BSSY B0, 0x7b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0740*/ @P1 BRA 0x7a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0750*/ LDG.E.64 R12, [R4.64+0x58] ; /* 0x00005804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0760*/ LDG.E.64 R14, [R6.64+0x58] ; /* 0x00005804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0770*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0780*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0790*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*07a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07b0*/ BSSY B0, 0x830 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*07c0*/ @P1 BRA 0x820 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*07d0*/ LDG.E.64 R12, [R6.64+0x60] ; /* 0x00006004060c7981 */
/* 0x001ea8000c1e1b00 */
/*07e0*/ LDG.E.64 R14, [R4.64+0x60] ; /* 0x00006004040e7981 */
/* 0x000ea8000c1e1b00 */
/*07f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0800*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0810*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0830*/ BSSY B0, 0x8b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0840*/ @P1 BRA 0x8a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0850*/ LDG.E.64 R12, [R4.64+0x68] ; /* 0x00006804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0860*/ LDG.E.64 R14, [R6.64+0x68] ; /* 0x00006804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0870*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0880*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0890*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*08a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08b0*/ BSSY B0, 0x930 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*08c0*/ @P1 BRA 0x920 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*08d0*/ LDG.E.64 R12, [R4.64+0x70] ; /* 0x00007004040c7981 */
/* 0x001ea8000c1e1b00 */
/*08e0*/ LDG.E.64 R14, [R6.64+0x70] ; /* 0x00007004060e7981 */
/* 0x000ea8000c1e1b00 */
/*08f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0900*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0910*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0920*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0930*/ @!P1 LDG.E.64 R12, [R4.64+0x78] ; /* 0x00007804040c9981 */
/* 0x0010a8000c1e1b00 */
/*0940*/ @!P1 LDG.E.64 R14, [R6.64+0x78] ; /* 0x00007804060e9981 */
/* 0x0002a8000c1e1b00 */
/*0950*/ @!P1 LDG.E.64 R16, [R2.64] ; /* 0x0000000402109981 */
/* 0x000ea2000c1e1b00 */
/*0960*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe40007ffe0ff */
/*0970*/ IADD3 R4, P4, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x001fc40007f9e0ff */
/*0980*/ ISETP.GT.AND P2, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f44270 */
/*0990*/ IADD3 R6, P3, R6, 0x80, RZ ; /* 0x0000008006067810 */
/* 0x002fe20007f7e0ff */
/*09a0*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */
/* 0x000fe200020e0605 */
/*09b0*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fc60007ffe0ff */
/*09c0*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe200018e0607 */
/*09d0*/ @!P1 DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c922b */
/* 0x004e0e0000000010 */
/*09e0*/ @!P1 STG.E.64 [R2.64], R12 ; /* 0x0000000c02009986 */
/* 0x0011e2000c101b04 */
/*09f0*/ @P2 BRA 0x1a0 ; /* 0xfffff7a000002947 */
/* 0x000fea000383ffff */
/*0a00*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*0a10*/ @!P1 BRA 0xe80 ; /* 0x0000046000009947 */
/* 0x000fea0003800000 */
/*0a20*/ ISETP.GE.AND P5, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003fa6270 */
/*0a30*/ BSSY B0, 0xb00 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*0a40*/ @P5 BRA 0xaf0 ; /* 0x000000a000005947 */
/* 0x000fea0003800000 */
/*0a50*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0a60*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*0a70*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0a80*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0a90*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0aa0*/ LDG.E.64 R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea8000c1e1b00 */
/*0ab0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ea8000c1e1b00 */
/*0ac0*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea4000c1e1b00 */
/*0ad0*/ DFMA R14, R14, R16, R18 ; /* 0x000000100e0e722b */
/* 0x004e4e0000000012 */
/*0ae0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0021e8000c101b04 */
/*0af0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b00*/ BSSY B0, 0xbe0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0b10*/ @P5 BRA 0xbd0 ; /* 0x000000b000005947 */
/* 0x000fea0003800000 */
/*0b20*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x001ea8000c1e1b00 */
/*0b30*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ea8000c1e1b00 */
/*0b40*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0b50*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0b60*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e2000c101b04 */
/*0b70*/ @P5 BRA 0xbd0 ; /* 0x0000005000005947 */
/* 0x000fea0003800000 */
/*0b80*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0b90*/ LDG.E.64 R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0ba0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0bb0*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0bc0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0bd0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0be0*/ IADD3 R12, P1, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x001fe20007f3e0ff */
/*0bf0*/ BSSY B0, 0xd40 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*0c00*/ IADD3 R14, P2, R4, 0x20, RZ ; /* 0x00000020040e7810 */
/* 0x000fe40007f5e0ff */
/*0c10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0c20*/ IMAD.X R13, RZ, RZ, R7, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0607 */
/*0c30*/ IADD3 R11, P3, R12, 0x20, RZ ; /* 0x000000200c0b7810 */
/* 0x000fe20007f7e0ff */
/*0c40*/ IMAD.X R15, RZ, RZ, R5, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e0605 */
/*0c50*/ IADD3 R16, P4, R14, 0x20, RZ ; /* 0x000000200e107810 */
/* 0x000fe40007f9e0ff */
/*0c60*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc40007ffe0ff */
/*0c70*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0c80*/ @P5 BRA 0xd30 ; /* 0x000000a000005947 */
/* 0x000fea0003800000 */
/*0c90*/ LDG.E.64 R6, [R6.64+0x20] ; /* 0x0000200406067981 */
/* 0x000ea8000c1e1b00 */
/*0ca0*/ LDG.E.64 R4, [R4.64+0x20] ; /* 0x0000200404047981 */
/* 0x000ea8000c1e1b00 */
/*0cb0*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea4000c1e1b00 */
/*0cc0*/ DFMA R18, R6, R4, R18 ; /* 0x000000040612722b */
/* 0x004e0e0000000012 */
/*0cd0*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0011e8000c101b04 */
/*0ce0*/ LDG.E.64 R20, [R14.64+0x8] ; /* 0x000008040e147981 */
/* 0x000ea8000c1e1b00 */
/*0cf0*/ LDG.E.64 R22, [R12.64+0x8] ; /* 0x000008040c167981 */
/* 0x000ea8000c1e1b00 */
/*0d00*/ LDG.E.64 R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ea4000c1e1b00 */
/*0d10*/ DFMA R20, R20, R22, R24 ; /* 0x000000161414722b */
/* 0x004e4e0000000018 */
/*0d20*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0021e8000c101b04 */
/*0d30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d40*/ BSSY B0, 0xe20 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0d50*/ @P5 BRA 0xe10 ; /* 0x000000b000005947 */
/* 0x000fea0003800000 */
/*0d60*/ LDG.E.64 R4, [R14.64+0x10] ; /* 0x000010040e047981 */
/* 0x000ea8000c1e1b00 */
/*0d70*/ LDG.E.64 R6, [R12.64+0x10] ; /* 0x000010040c067981 */
/* 0x000ea8000c1e1b00 */
/*0d80*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x001ea4000c1e1b00 */
/*0d90*/ DFMA R4, R4, R6, R18 ; /* 0x000000060404722b */
/* 0x004e0e0000000012 */
/*0da0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0011e2000c101b04 */
/*0db0*/ @P5 BRA 0xe10 ; /* 0x0000005000005947 */
/* 0x000fea0003800000 */
/*0dc0*/ LDG.E.64 R4, [R14.64+0x18] ; /* 0x000018040e047981 */
/* 0x001ea8000c1e1b00 */
/*0dd0*/ LDG.E.64 R6, [R12.64+0x18] ; /* 0x000018040c067981 */
/* 0x000ea8000c1e1b00 */
/*0de0*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea4000c1e1b00 */
/*0df0*/ DFMA R4, R4, R6, R18 ; /* 0x000000060404722b */
/* 0x004e0e0000000012 */
/*0e00*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0011e8000c101b04 */
/*0e10*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e20*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*0e30*/ IMAD.X R7, RZ, RZ, R13, P3 ; /* 0x000000ffff077224 */
/* 0x000fe200018e060d */
/*0e40*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0e50*/ IMAD.X R5, RZ, RZ, R15, P4 ; /* 0x000000ffff057224 */
/* 0x001fe400020e060f */
/*0e60*/ IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000b */
/*0e70*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0010 */
/*0e80*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0e90*/ @!P0 BRA 0x10e0 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0ea0*/ ISETP.GE.AND P3, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fd80003f66270 */
/*0eb0*/ BSSY B0, 0xf80 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0ec0*/ @P3 BRA 0xf70 ; /* 0x000000a000003947 */
/* 0x001fea0003800000 */
/*0ed0*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0ee0*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*0ef0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0f00*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0f10*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0f20*/ LDG.E.64 R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea8000c1e1b00 */
/*0f30*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ea8000c1e1b00 */
/*0f40*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea4000c1e1b00 */
/*0f50*/ DFMA R14, R14, R16, R18 ; /* 0x000000100e0e722b */
/* 0x004e4e0000000012 */
/*0f60*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0021e8000c101b04 */
/*0f70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0f80*/ BSSY B0, 0x1060 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0f90*/ @P3 BRA 0x1050 ; /* 0x000000b000003947 */
/* 0x000fea0003800000 */
/*0fa0*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x001ea8000c1e1b00 */
/*0fb0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ea8000c1e1b00 */
/*0fc0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0fd0*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0fe0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e2000c101b04 */
/*0ff0*/ @P3 BRA 0x1050 ; /* 0x0000005000003947 */
/* 0x000fea0003800000 */
/*1000*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x001ea8000c1e1b00 */
/*1010*/ LDG.E.64 R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ea8000c1e1b00 */
/*1020*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*1030*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*1040*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*1050*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*1060*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe40007ffe0ff */
/*1070*/ IADD3 R6, P1, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x000fe40007f3e0ff */
/*1080*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*1090*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fe20007f5e0ff */
/*10a0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*10b0*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc60007ffe0ff */
/*10c0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fcc00010e0605 */
/*10d0*/ @P0 BRA 0xeb0 ; /* 0xfffffdd000000947 */
/* 0x000fea000383ffff */
/*10e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*10f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*1100*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*1110*/ ISETP.GE.AND P3, PT, R0.reuse, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x040fe20003f66270 */
/*1120*/ IMAD R6, R0, c[0x0][0x178], R9 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e0209 */
/*1130*/ IMAD.WIDE R4, R9, R7, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fc800078e0207 */
/*1140*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*1150*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e0004 */
/*1160*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0005 */
/*1170*/ IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0006 */
/*1180*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*1190*/ @!P3 IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff06b224 */
/* 0x000fe200078e000e */
/*11a0*/ @!P3 LDG.E.64 R10, [R2.64] ; /* 0x00000004020ab981 */
/* 0x000ea2000c1e1b00 */
/*11b0*/ @!P3 IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff07b224 */
/* 0x000fe400078e000f */
/*11c0*/ @!P3 IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0cb224 */
/* 0x000fc400078e0000 */
/*11d0*/ @!P3 IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0db224 */
/* 0x000fe400078e0009 */
/*11e0*/ @!P3 LDG.E.64 R6, [R6.64] ; /* 0x000000040606b981 */
/* 0x000ea8000c1e1b00 */
/*11f0*/ @!P3 LDG.E.64 R4, [R12.64] ; /* 0x000000040c04b981 */
/* 0x001ea2000c1e1b00 */
/*1200*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*1210*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*1220*/ IADD3 R14, P1, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe40007f3e0ff */
/*1230*/ IADD3 R0, P2, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc60007f5e0ff */
/*1240*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe400008e060f */
/*1250*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*1260*/ @!P3 DFMA R4, R4, R6, R10 ; /* 0x000000060404b22b */
/* 0x004e0e000000000a */
/*1270*/ @!P3 STG.E.64 [R2.64], R4 ; /* 0x000000040200b986 */
/* 0x0011e2000c101b04 */
/*1280*/ @P0 BRA 0x1190 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*1290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*12a0*/ BRA 0x12a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#define N 4;
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
//__global__ void addKernel(int *c, const int *a, const int *b)
//{
// int i = threadIdx.x;
// c[i] = a[i] + b[i];
//}
__global__ void addKernel(double *a, double *b, double *c,int size)
{
int i = threadIdx.x;
for(int k = 0;k<size; k++)
{
if(i < size)
c[i] += a[i*size+k] * b[k];
}
}
void simple_dgemv(double *A, double *B, double *C,int size)
{
int i,j;
for(i = 0;i < size; i++)
{
double prod = 0;
for(j = 0;j < size; j++)
{
prod += A[i * size + j] * B[j];
}
C[i] = prod;
}
}
//__global__ void MVKernel_gm(double *A, double *X, double *Y,int ARRAY_SIZE)
//{
// //int bx = blockIdx.x;
// //int by = blockIdx.y;
// int tid = threadIdx.x;
// //int ty = threadIdx.y;
// // Calculate the row index of the Pd element and M
// //int Row = bx * BLOCK_SIZE + tx;
// // Calculate the column idenx of Pd and N
// //int Col = bx * BLOCK_SIZE + tx;
//
// double tmpSum = 0;
//
// for (int k = 0; k < ARRAY_SIZE; k++)
// {
// if(tid < ARRAY_SIZE)
// tmpSum += A[tid*ARRAY_SIZE+k] * X[k];
// }
//
// __syncthreads();
//
// if(tid < ARRAY_SIZE)
// Y[tid] = tmpSum;
//
// __syncthreads();
//}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
int ARRAY_SIZE = 5;
int ARRAY_SIZE2 = ARRAY_SIZE*ARRAY_SIZE;
//Host
double *h_a;
double *h_b;
double *h_c;
//Device
double *d_a;
double *d_b;
double *d_c;
//generate the input array on the host
h_a=(double*)malloc(sizeof(double)*ARRAY_SIZE2);
h_b=(double*)malloc(sizeof(double)*ARRAY_SIZE);
h_c=(double*)malloc(sizeof(double)*ARRAY_SIZE);
//inital the h_a, h_b
for(int i = 0;i<ARRAY_SIZE2;i++){
h_a[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_b[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_c[i] = double(0);
}
////print out test
//printf("\nThe vector A is:\n");
//for(int i=0;i<ARRAY_SIZE2;i++){
// printf("%f", h_a[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//printf("\nThe Matrix X is:\n");
//for(int i=0;i<ARRAY_SIZE;i++){
// printf("%f", h_b[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addWithCuda failed!");
// return 1;
//}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
//// cudaDeviceReset must be called before exiting in order for profiling and
//// tracing tools such as Nsight and Visual Profiler to show complete traces.
//cudaStatus = cudaDeviceReset();
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceReset failed!");
// return 1;
//}
//allocate GPU memory
cudaMalloc((void**)&d_a, sizeof(double)*ARRAY_SIZE2);
cudaMalloc((void**)&d_b, sizeof(double)*ARRAY_SIZE);
cudaMalloc((void**)&d_c, sizeof(double)*ARRAY_SIZE);
//transfer the array from Host to device(CPU->GPU)
cudaMemcpy(d_a, h_a, sizeof(double)*ARRAY_SIZE2, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sizeof(double)*ARRAY_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, h_c, sizeof(double)*ARRAY_SIZE, cudaMemcpyHostToDevice);
//Run kernel function calculate the matrix-vector multiplication
printf("\n\nRunning Kernel...\n\n");
//MVKernel_gm<<<1,256>>>(d_a, d_b, d_c, ARRAY_SIZE);//ARRAY_SIZE/256+1, 256
addKernel<<<1, ARRAY_SIZE>>>(d_a,d_b,d_c,ARRAY_SIZE);
//transfer the array from Device to Host(GPU->CPU)
//cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c, d_c, sizeof(double)*ARRAY_SIZE, cudaMemcpyDeviceToHost);
//print out the result array
for(int i = 0; i<ARRAY_SIZE;i++){
printf("%f\n", h_c[i]);
//printf(((i%4)!=3)? "\t" : "\n");
}
//free GPU memory allocation
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
//free Host memory allocation
free(h_a);
free(h_b);
free(h_c);
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
//{
// int *dev_a = 0;
// int *dev_b = 0;
// int *dev_c = 0;
// cudaError_t cudaStatus;
//
// // Choose which GPU to run on, change this on a multi-GPU system.
// cudaStatus = cudaSetDevice(0);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
// }
//
// // Allocate GPU buffers for three vectors (two input, one output) .
// cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// // Copy input vectors from host memory to GPU buffers.
// cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// // Launch a kernel on the GPU with one thread for each element.
// //addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
//
// // Check for any errors launching the kernel
// cudaStatus = cudaGetLastError();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
// }
//
// // cudaDeviceSynchronize waits for the kernel to finish, and returns
// // any errors encountered during the launch.
// cudaStatus = cudaDeviceSynchronize();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
// goto Error;
// }
//
// // Copy output vector from GPU buffer to host memory.
// cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
//Error:
// cudaFree(dev_c);
// cudaFree(dev_a);
// cudaFree(dev_b);
//
//
//
// return cudaStatus;
//} | .file "tmpxft_000f93e1_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12simple_dgemvPdS_S_i
.type _Z12simple_dgemvPdS_S_i, @function
_Z12simple_dgemvPdS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movq %rdx, %r8
movslq %ecx, %rcx
salq $3, %rcx
addq %rcx, %rdx
.L5:
movl $0, %eax
pxor %xmm1, %xmm1
.L6:
movsd (%rdi,%rax), %xmm0
mulsd (%rsi,%rax), %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
cmpq %rcx, %rax
jne .L6
movsd %xmm1, (%r8)
addq $8, %r8
addq %rcx, %rdi
cmpq %rdx, %r8
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z12simple_dgemvPdS_S_i, .-_Z12simple_dgemvPdS_S_i
.globl _Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i
.type _Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i, @function
_Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i, .-_Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i
.globl _Z9addKernelPdS_S_i
.type _Z9addKernelPdS_S_i, @function
_Z9addKernelPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9addKernelPdS_S_i, .-_Z9addKernelPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "\n\nRunning Kernel...\n\n"
.LC6:
.string "%f\n"
.LC7:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $200, %edi
call malloc@PLT
movq %rax, %rbx
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L17:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $25, %rax
jne .L17
movq $0x000000000, 0(%r13)
movq .LC1(%rip), %rax
movq %rax, 8(%r13)
movq .LC2(%rip), %rax
movq %rax, 16(%r13)
movq .LC3(%rip), %rax
movq %rax, 24(%r13)
movq .LC4(%rip), %rax
movq %rax, 32(%r13)
movq $0x000000000, (%r12)
movq $0x000000000, 8(%r12)
movq $0x000000000, 16(%r12)
movq $0x000000000, 24(%r12)
movq $0x000000000, 32(%r12)
leaq 8(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $200, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L18:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rbp
leaq 40(%r12), %r15
leaq .LC6(%rip), %r14
.L19:
movsd 0(%rbp), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbp
cmpq %r15, %rbp
jne .L19
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
leaq .LC7(%rip), %rdi
call system@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $5, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i
jmp .L18
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9addKernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1073741824
.align 8
.LC3:
.long 0
.long 1074266112
.align 8
.LC4:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#define N 4;
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
//__global__ void addKernel(int *c, const int *a, const int *b)
//{
// int i = threadIdx.x;
// c[i] = a[i] + b[i];
//}
__global__ void addKernel(double *a, double *b, double *c,int size)
{
int i = threadIdx.x;
for(int k = 0;k<size; k++)
{
if(i < size)
c[i] += a[i*size+k] * b[k];
}
}
void simple_dgemv(double *A, double *B, double *C,int size)
{
int i,j;
for(i = 0;i < size; i++)
{
double prod = 0;
for(j = 0;j < size; j++)
{
prod += A[i * size + j] * B[j];
}
C[i] = prod;
}
}
//__global__ void MVKernel_gm(double *A, double *X, double *Y,int ARRAY_SIZE)
//{
// //int bx = blockIdx.x;
// //int by = blockIdx.y;
// int tid = threadIdx.x;
// //int ty = threadIdx.y;
// // Calculate the row index of the Pd element and M
// //int Row = bx * BLOCK_SIZE + tx;
// // Calculate the column idenx of Pd and N
// //int Col = bx * BLOCK_SIZE + tx;
//
// double tmpSum = 0;
//
// for (int k = 0; k < ARRAY_SIZE; k++)
// {
// if(tid < ARRAY_SIZE)
// tmpSum += A[tid*ARRAY_SIZE+k] * X[k];
// }
//
// __syncthreads();
//
// if(tid < ARRAY_SIZE)
// Y[tid] = tmpSum;
//
// __syncthreads();
//}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
int ARRAY_SIZE = 5;
int ARRAY_SIZE2 = ARRAY_SIZE*ARRAY_SIZE;
//Host
double *h_a;
double *h_b;
double *h_c;
//Device
double *d_a;
double *d_b;
double *d_c;
//generate the input array on the host
h_a=(double*)malloc(sizeof(double)*ARRAY_SIZE2);
h_b=(double*)malloc(sizeof(double)*ARRAY_SIZE);
h_c=(double*)malloc(sizeof(double)*ARRAY_SIZE);
//inital the h_a, h_b
for(int i = 0;i<ARRAY_SIZE2;i++){
h_a[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_b[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_c[i] = double(0);
}
////print out test
//printf("\nThe vector A is:\n");
//for(int i=0;i<ARRAY_SIZE2;i++){
// printf("%f", h_a[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//printf("\nThe Matrix X is:\n");
//for(int i=0;i<ARRAY_SIZE;i++){
// printf("%f", h_b[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addWithCuda failed!");
// return 1;
//}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
//// cudaDeviceReset must be called before exiting in order for profiling and
//// tracing tools such as Nsight and Visual Profiler to show complete traces.
//cudaStatus = cudaDeviceReset();
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceReset failed!");
// return 1;
//}
//allocate GPU memory
cudaMalloc((void**)&d_a, sizeof(double)*ARRAY_SIZE2);
cudaMalloc((void**)&d_b, sizeof(double)*ARRAY_SIZE);
cudaMalloc((void**)&d_c, sizeof(double)*ARRAY_SIZE);
//transfer the array from Host to device(CPU->GPU)
cudaMemcpy(d_a, h_a, sizeof(double)*ARRAY_SIZE2, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, sizeof(double)*ARRAY_SIZE, cudaMemcpyHostToDevice);
cudaMemcpy(d_c, h_c, sizeof(double)*ARRAY_SIZE, cudaMemcpyHostToDevice);
//Run kernel function calculate the matrix-vector multiplication
printf("\n\nRunning Kernel...\n\n");
//MVKernel_gm<<<1,256>>>(d_a, d_b, d_c, ARRAY_SIZE);//ARRAY_SIZE/256+1, 256
addKernel<<<1, ARRAY_SIZE>>>(d_a,d_b,d_c,ARRAY_SIZE);
//transfer the array from Device to Host(GPU->CPU)
//cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
cudaMemcpy(h_c, d_c, sizeof(double)*ARRAY_SIZE, cudaMemcpyDeviceToHost);
//print out the result array
for(int i = 0; i<ARRAY_SIZE;i++){
printf("%f\n", h_c[i]);
//printf(((i%4)!=3)? "\t" : "\n");
}
//free GPU memory allocation
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
//free Host memory allocation
free(h_a);
free(h_b);
free(h_c);
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
//{
// int *dev_a = 0;
// int *dev_b = 0;
// int *dev_c = 0;
// cudaError_t cudaStatus;
//
// // Choose which GPU to run on, change this on a multi-GPU system.
// cudaStatus = cudaSetDevice(0);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
// }
//
// // Allocate GPU buffers for three vectors (two input, one output) .
// cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// // Copy input vectors from host memory to GPU buffers.
// cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// // Launch a kernel on the GPU with one thread for each element.
// //addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
//
// // Check for any errors launching the kernel
// cudaStatus = cudaGetLastError();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
// }
//
// // cudaDeviceSynchronize waits for the kernel to finish, and returns
// // any errors encountered during the launch.
// cudaStatus = cudaDeviceSynchronize();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
// goto Error;
// }
//
// // Copy output vector from GPU buffer to host memory.
// cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
//Error:
// cudaFree(dev_c);
// cudaFree(dev_a);
// cudaFree(dev_b);
//
//
//
// return cudaStatus;
//} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define N 4;
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
//__global__ void addKernel(int *c, const int *a, const int *b)
//{
// int i = threadIdx.x;
// c[i] = a[i] + b[i];
//}
__global__ void addKernel(double *a, double *b, double *c,int size)
{
int i = threadIdx.x;
for(int k = 0;k<size; k++)
{
if(i < size)
c[i] += a[i*size+k] * b[k];
}
}
void simple_dgemv(double *A, double *B, double *C,int size)
{
int i,j;
for(i = 0;i < size; i++)
{
double prod = 0;
for(j = 0;j < size; j++)
{
prod += A[i * size + j] * B[j];
}
C[i] = prod;
}
}
//__global__ void MVKernel_gm(double *A, double *X, double *Y,int ARRAY_SIZE)
//{
// //int bx = blockIdx.x;
// //int by = blockIdx.y;
// int tid = threadIdx.x;
// //int ty = threadIdx.y;
// // Calculate the row index of the Pd element and M
// //int Row = bx * BLOCK_SIZE + tx;
// // Calculate the column idenx of Pd and N
// //int Col = bx * BLOCK_SIZE + tx;
//
// double tmpSum = 0;
//
// for (int k = 0; k < ARRAY_SIZE; k++)
// {
// if(tid < ARRAY_SIZE)
// tmpSum += A[tid*ARRAY_SIZE+k] * X[k];
// }
//
// __syncthreads();
//
// if(tid < ARRAY_SIZE)
// Y[tid] = tmpSum;
//
// __syncthreads();
//}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
int ARRAY_SIZE = 5;
int ARRAY_SIZE2 = ARRAY_SIZE*ARRAY_SIZE;
//Host
double *h_a;
double *h_b;
double *h_c;
//Device
double *d_a;
double *d_b;
double *d_c;
//generate the input array on the host
h_a=(double*)malloc(sizeof(double)*ARRAY_SIZE2);
h_b=(double*)malloc(sizeof(double)*ARRAY_SIZE);
h_c=(double*)malloc(sizeof(double)*ARRAY_SIZE);
//inital the h_a, h_b
for(int i = 0;i<ARRAY_SIZE2;i++){
h_a[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_b[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_c[i] = double(0);
}
////print out test
//printf("\nThe vector A is:\n");
//for(int i=0;i<ARRAY_SIZE2;i++){
// printf("%f", h_a[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//printf("\nThe Matrix X is:\n");
//for(int i=0;i<ARRAY_SIZE;i++){
// printf("%f", h_b[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addWithCuda failed!");
// return 1;
//}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
//// cudaDeviceReset must be called before exiting in order for profiling and
//// tracing tools such as Nsight and Visual Profiler to show complete traces.
//cudaStatus = cudaDeviceReset();
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceReset failed!");
// return 1;
//}
//allocate GPU memory
hipMalloc((void**)&d_a, sizeof(double)*ARRAY_SIZE2);
hipMalloc((void**)&d_b, sizeof(double)*ARRAY_SIZE);
hipMalloc((void**)&d_c, sizeof(double)*ARRAY_SIZE);
//transfer the array from Host to device(CPU->GPU)
hipMemcpy(d_a, h_a, sizeof(double)*ARRAY_SIZE2, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sizeof(double)*ARRAY_SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_c, h_c, sizeof(double)*ARRAY_SIZE, hipMemcpyHostToDevice);
//Run kernel function calculate the matrix-vector multiplication
printf("\n\nRunning Kernel...\n\n");
//MVKernel_gm<<<1,256>>>(d_a, d_b, d_c, ARRAY_SIZE);//ARRAY_SIZE/256+1, 256
addKernel<<<1, ARRAY_SIZE>>>(d_a,d_b,d_c,ARRAY_SIZE);
//transfer the array from Device to Host(GPU->CPU)
//cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
hipMemcpy(h_c, d_c, sizeof(double)*ARRAY_SIZE, hipMemcpyDeviceToHost);
//print out the result array
for(int i = 0; i<ARRAY_SIZE;i++){
printf("%f\n", h_c[i]);
//printf(((i%4)!=3)? "\t" : "\n");
}
//free GPU memory allocation
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
//free Host memory allocation
free(h_a);
free(h_b);
free(h_c);
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
//{
// int *dev_a = 0;
// int *dev_b = 0;
// int *dev_c = 0;
// cudaError_t cudaStatus;
//
// // Choose which GPU to run on, change this on a multi-GPU system.
// cudaStatus = cudaSetDevice(0);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
// }
//
// // Allocate GPU buffers for three vectors (two input, one output) .
// cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// // Copy input vectors from host memory to GPU buffers.
// cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// // Launch a kernel on the GPU with one thread for each element.
// //addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
//
// // Check for any errors launching the kernel
// cudaStatus = cudaGetLastError();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
// }
//
// // cudaDeviceSynchronize waits for the kernel to finish, and returns
// // any errors encountered during the launch.
// cudaStatus = cudaDeviceSynchronize();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
// goto Error;
// }
//
// // Copy output vector from GPU buffer to host memory.
// cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
//Error:
// cudaFree(dev_c);
// cudaFree(dev_a);
// cudaFree(dev_b);
//
//
//
// return cudaStatus;
//} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define N 4;
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
//__global__ void addKernel(int *c, const int *a, const int *b)
//{
// int i = threadIdx.x;
// c[i] = a[i] + b[i];
//}
__global__ void addKernel(double *a, double *b, double *c,int size)
{
int i = threadIdx.x;
for(int k = 0;k<size; k++)
{
if(i < size)
c[i] += a[i*size+k] * b[k];
}
}
void simple_dgemv(double *A, double *B, double *C,int size)
{
int i,j;
for(i = 0;i < size; i++)
{
double prod = 0;
for(j = 0;j < size; j++)
{
prod += A[i * size + j] * B[j];
}
C[i] = prod;
}
}
//__global__ void MVKernel_gm(double *A, double *X, double *Y,int ARRAY_SIZE)
//{
// //int bx = blockIdx.x;
// //int by = blockIdx.y;
// int tid = threadIdx.x;
// //int ty = threadIdx.y;
// // Calculate the row index of the Pd element and M
// //int Row = bx * BLOCK_SIZE + tx;
// // Calculate the column idenx of Pd and N
// //int Col = bx * BLOCK_SIZE + tx;
//
// double tmpSum = 0;
//
// for (int k = 0; k < ARRAY_SIZE; k++)
// {
// if(tid < ARRAY_SIZE)
// tmpSum += A[tid*ARRAY_SIZE+k] * X[k];
// }
//
// __syncthreads();
//
// if(tid < ARRAY_SIZE)
// Y[tid] = tmpSum;
//
// __syncthreads();
//}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
int ARRAY_SIZE = 5;
int ARRAY_SIZE2 = ARRAY_SIZE*ARRAY_SIZE;
//Host
double *h_a;
double *h_b;
double *h_c;
//Device
double *d_a;
double *d_b;
double *d_c;
//generate the input array on the host
h_a=(double*)malloc(sizeof(double)*ARRAY_SIZE2);
h_b=(double*)malloc(sizeof(double)*ARRAY_SIZE);
h_c=(double*)malloc(sizeof(double)*ARRAY_SIZE);
//inital the h_a, h_b
for(int i = 0;i<ARRAY_SIZE2;i++){
h_a[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_b[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_c[i] = double(0);
}
////print out test
//printf("\nThe vector A is:\n");
//for(int i=0;i<ARRAY_SIZE2;i++){
// printf("%f", h_a[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//printf("\nThe Matrix X is:\n");
//for(int i=0;i<ARRAY_SIZE;i++){
// printf("%f", h_b[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addWithCuda failed!");
// return 1;
//}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
//// cudaDeviceReset must be called before exiting in order for profiling and
//// tracing tools such as Nsight and Visual Profiler to show complete traces.
//cudaStatus = cudaDeviceReset();
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceReset failed!");
// return 1;
//}
//allocate GPU memory
hipMalloc((void**)&d_a, sizeof(double)*ARRAY_SIZE2);
hipMalloc((void**)&d_b, sizeof(double)*ARRAY_SIZE);
hipMalloc((void**)&d_c, sizeof(double)*ARRAY_SIZE);
//transfer the array from Host to device(CPU->GPU)
hipMemcpy(d_a, h_a, sizeof(double)*ARRAY_SIZE2, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sizeof(double)*ARRAY_SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_c, h_c, sizeof(double)*ARRAY_SIZE, hipMemcpyHostToDevice);
//Run kernel function calculate the matrix-vector multiplication
printf("\n\nRunning Kernel...\n\n");
//MVKernel_gm<<<1,256>>>(d_a, d_b, d_c, ARRAY_SIZE);//ARRAY_SIZE/256+1, 256
addKernel<<<1, ARRAY_SIZE>>>(d_a,d_b,d_c,ARRAY_SIZE);
//transfer the array from Device to Host(GPU->CPU)
//cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
hipMemcpy(h_c, d_c, sizeof(double)*ARRAY_SIZE, hipMemcpyDeviceToHost);
//print out the result array
for(int i = 0; i<ARRAY_SIZE;i++){
printf("%f\n", h_c[i]);
//printf(((i%4)!=3)? "\t" : "\n");
}
//free GPU memory allocation
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
//free Host memory allocation
free(h_a);
free(h_b);
free(h_c);
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
//{
// int *dev_a = 0;
// int *dev_b = 0;
// int *dev_c = 0;
// cudaError_t cudaStatus;
//
// // Choose which GPU to run on, change this on a multi-GPU system.
// cudaStatus = cudaSetDevice(0);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
// }
//
// // Allocate GPU buffers for three vectors (two input, one output) .
// cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// // Copy input vectors from host memory to GPU buffers.
// cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// // Launch a kernel on the GPU with one thread for each element.
// //addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
//
// // Check for any errors launching the kernel
// cudaStatus = cudaGetLastError();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
// }
//
// // cudaDeviceSynchronize waits for the kernel to finish, and returns
// // any errors encountered during the launch.
// cudaStatus = cudaDeviceSynchronize();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
// goto Error;
// }
//
// // Copy output vector from GPU buffer to host memory.
// cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
//Error:
// cudaFree(dev_c);
// cudaFree(dev_a);
// cudaFree(dev_b);
//
//
//
// return cudaStatus;
//} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPdS_S_i
.globl _Z9addKernelPdS_S_i
.p2align 8
.type _Z9addKernelPdS_S_i,@function
_Z9addKernelPdS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 3, v0
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_mul_lo_u32 v0, v0, s2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s8, v2
v_add_co_ci_u32_e64 v3, null, s9, 0, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s2, s2, -1
v_add_nc_u32_e32 v0, 1, v0
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[4:5], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s4, v4
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
global_load_b64 v[6:7], v1, s[6:7]
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[8:9], v[2:3], off
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[4:5], v[6:7], v[8:9]
global_store_b64 v[2:3], v[4:5], off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPdS_S_i, .Lfunc_end0-_Z9addKernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z9addKernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#define N 4;
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);
//__global__ void addKernel(int *c, const int *a, const int *b)
//{
// int i = threadIdx.x;
// c[i] = a[i] + b[i];
//}
__global__ void addKernel(double *a, double *b, double *c,int size)
{
int i = threadIdx.x;
for(int k = 0;k<size; k++)
{
if(i < size)
c[i] += a[i*size+k] * b[k];
}
}
void simple_dgemv(double *A, double *B, double *C,int size)
{
int i,j;
for(i = 0;i < size; i++)
{
double prod = 0;
for(j = 0;j < size; j++)
{
prod += A[i * size + j] * B[j];
}
C[i] = prod;
}
}
//__global__ void MVKernel_gm(double *A, double *X, double *Y,int ARRAY_SIZE)
//{
// //int bx = blockIdx.x;
// //int by = blockIdx.y;
// int tid = threadIdx.x;
// //int ty = threadIdx.y;
// // Calculate the row index of the Pd element and M
// //int Row = bx * BLOCK_SIZE + tx;
// // Calculate the column idenx of Pd and N
// //int Col = bx * BLOCK_SIZE + tx;
//
// double tmpSum = 0;
//
// for (int k = 0; k < ARRAY_SIZE; k++)
// {
// if(tid < ARRAY_SIZE)
// tmpSum += A[tid*ARRAY_SIZE+k] * X[k];
// }
//
// __syncthreads();
//
// if(tid < ARRAY_SIZE)
// Y[tid] = tmpSum;
//
// __syncthreads();
//}
int main()
{
const int arraySize = 5;
const int a[arraySize] = { 1, 2, 3, 4, 5 };
const int b[arraySize] = { 10, 20, 30, 40, 50 };
int c[arraySize] = { 0 };
int ARRAY_SIZE = 5;
int ARRAY_SIZE2 = ARRAY_SIZE*ARRAY_SIZE;
//Host
double *h_a;
double *h_b;
double *h_c;
//Device
double *d_a;
double *d_b;
double *d_c;
//generate the input array on the host
h_a=(double*)malloc(sizeof(double)*ARRAY_SIZE2);
h_b=(double*)malloc(sizeof(double)*ARRAY_SIZE);
h_c=(double*)malloc(sizeof(double)*ARRAY_SIZE);
//inital the h_a, h_b
for(int i = 0;i<ARRAY_SIZE2;i++){
h_a[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_b[i] = double(i);
}
for(int i = 0;i<ARRAY_SIZE;i++){
h_c[i] = double(0);
}
////print out test
//printf("\nThe vector A is:\n");
//for(int i=0;i<ARRAY_SIZE2;i++){
// printf("%f", h_a[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//printf("\nThe Matrix X is:\n");
//for(int i=0;i<ARRAY_SIZE;i++){
// printf("%f", h_b[i]);
// printf(((i%4)!=3)? "\t" : "\n");
//}
//// Add vectors in parallel.
//cudaError_t cudaStatus = addWithCuda(c, a, b, arraySize);
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addWithCuda failed!");
// return 1;
//}
//printf("{1,2,3,4,5} + {10,20,30,40,50} = {%d,%d,%d,%d,%d}\n",
// c[0], c[1], c[2], c[3], c[4]);
//// cudaDeviceReset must be called before exiting in order for profiling and
//// tracing tools such as Nsight and Visual Profiler to show complete traces.
//cudaStatus = cudaDeviceReset();
//if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceReset failed!");
// return 1;
//}
//allocate GPU memory
hipMalloc((void**)&d_a, sizeof(double)*ARRAY_SIZE2);
hipMalloc((void**)&d_b, sizeof(double)*ARRAY_SIZE);
hipMalloc((void**)&d_c, sizeof(double)*ARRAY_SIZE);
//transfer the array from Host to device(CPU->GPU)
hipMemcpy(d_a, h_a, sizeof(double)*ARRAY_SIZE2, hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, sizeof(double)*ARRAY_SIZE, hipMemcpyHostToDevice);
hipMemcpy(d_c, h_c, sizeof(double)*ARRAY_SIZE, hipMemcpyHostToDevice);
//Run kernel function calculate the matrix-vector multiplication
printf("\n\nRunning Kernel...\n\n");
//MVKernel_gm<<<1,256>>>(d_a, d_b, d_c, ARRAY_SIZE);//ARRAY_SIZE/256+1, 256
addKernel<<<1, ARRAY_SIZE>>>(d_a,d_b,d_c,ARRAY_SIZE);
//transfer the array from Device to Host(GPU->CPU)
//cudaMemcpy(h_out, d_out, ARRAY_BYTES, cudaMemcpyDeviceToHost);
hipMemcpy(h_c, d_c, sizeof(double)*ARRAY_SIZE, hipMemcpyDeviceToHost);
//print out the result array
for(int i = 0; i<ARRAY_SIZE;i++){
printf("%f\n", h_c[i]);
//printf(((i%4)!=3)? "\t" : "\n");
}
//free GPU memory allocation
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
//free Host memory allocation
free(h_a);
free(h_b);
free(h_c);
system("pause");
return 0;
}
// Helper function for using CUDA to add vectors in parallel.
//cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size)
//{
// int *dev_a = 0;
// int *dev_b = 0;
// int *dev_c = 0;
// cudaError_t cudaStatus;
//
// // Choose which GPU to run on, change this on a multi-GPU system.
// cudaStatus = cudaSetDevice(0);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaSetDevice failed! Do you have a CUDA-capable GPU installed?");
// goto Error;
// }
//
// // Allocate GPU buffers for three vectors (two input, one output) .
// cudaStatus = cudaMalloc((void**)&dev_c, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_a, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// cudaStatus = cudaMalloc((void**)&dev_b, size * sizeof(int));
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMalloc failed!");
// goto Error;
// }
//
// // Copy input vectors from host memory to GPU buffers.
// cudaStatus = cudaMemcpy(dev_a, a, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// cudaStatus = cudaMemcpy(dev_b, b, size * sizeof(int), cudaMemcpyHostToDevice);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
// // Launch a kernel on the GPU with one thread for each element.
// //addKernel<<<1, size>>>(dev_c, dev_a, dev_b);
//
// // Check for any errors launching the kernel
// cudaStatus = cudaGetLastError();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "addKernel launch failed: %s\n", cudaGetErrorString(cudaStatus));
// goto Error;
// }
//
// // cudaDeviceSynchronize waits for the kernel to finish, and returns
// // any errors encountered during the launch.
// cudaStatus = cudaDeviceSynchronize();
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaDeviceSynchronize returned error code %d after launching addKernel!\n", cudaStatus);
// goto Error;
// }
//
// // Copy output vector from GPU buffer to host memory.
// cudaStatus = cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
// if (cudaStatus != cudaSuccess) {
// fprintf(stderr, "cudaMemcpy failed!");
// goto Error;
// }
//
//Error:
// cudaFree(dev_c);
// cudaFree(dev_a);
// cudaFree(dev_b);
//
//
//
// return cudaStatus;
//} | .text
.file "kernel.hip"
.globl _Z24__device_stub__addKernelPdS_S_i # -- Begin function _Z24__device_stub__addKernelPdS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPdS_S_i,@function
_Z24__device_stub__addKernelPdS_S_i: # @_Z24__device_stub__addKernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPdS_S_i, .Lfunc_end0-_Z24__device_stub__addKernelPdS_S_i
.cfi_endproc
# -- End function
.globl _Z12simple_dgemvPdS_S_i # -- Begin function _Z12simple_dgemvPdS_S_i
.p2align 4, 0x90
.type _Z12simple_dgemvPdS_S_i,@function
_Z12simple_dgemvPdS_S_i: # @_Z12simple_dgemvPdS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r8d, %r10d
leaq (%rdi,%r10,8), %r10
xorpd %xmm0, %xmm0
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r10,%r11,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%rsi,%r11,8), %xmm1
addsd %xmm1, %xmm0
incq %r11
cmpq %r11, %rax
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movsd %xmm0, (%rdx,%r9,8)
incq %r9
addl %ecx, %r8d
cmpq %rax, %r9
jne .LBB1_2
.LBB1_5: # %._crit_edge21
retq
.Lfunc_end1:
.size _Z12simple_dgemvPdS_S_i, .Lfunc_end1-_Z12simple_dgemvPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $200, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
incq %rax
cmpq $25, %rax
jne .LBB2_1
# %bb.2: # %.preheader56.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader56
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%rax,8)
incq %rax
cmpq $5, %rax
jne .LBB2_3
# %bb.4: # %.preheader.preheader
xorpd %xmm0, %xmm0
movupd %xmm0, 16(%r15)
movupd %xmm0, (%r15)
movq $0, 32(%r15)
leaq 24(%rsp), %rdi
movl $200, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $200, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $40, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $5, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9addKernelPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $5, %r12
jne .LBB2_7
# %bb.8:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $.L.str.2, %edi
callq system
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPdS_S_i,@object # @_Z9addKernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z9addKernelPdS_S_i
.p2align 3, 0x0
_Z9addKernelPdS_S_i:
.quad _Z24__device_stub__addKernelPdS_S_i
.size _Z9addKernelPdS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "pause"
.size .L.str.2, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPdS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\nRunning Kernel...\n"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addKernelPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff087624 */
/* 0x000fca00078e00ff */
/*0020*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0030*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0050*/ IADD3 R2, R8.reuse, -0x1, RZ ; /* 0xffffffff08027810 */
/* 0x040fe20007ffe0ff */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ LOP3.LUT R8, R8, 0x3, RZ, 0xc0, !PT ; /* 0x0000000308087812 */
/* 0x000fe200078ec0ff */
/*0090*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*00b0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x001fd800078e0207 */
/*00c0*/ @!P0 BRA 0x10e0 ; /* 0x0000101000008947 */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R10, -R8, c[0x0][0x178], RZ ; /* 0x00005e00080a7a10 */
/* 0x000fe20007ffe1ff */
/*00e0*/ IMAD R6, R0, c[0x0][0x178], RZ ; /* 0x00005e0000067a24 */
/* 0x000fe400078e02ff */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fe200078e00ff */
/*0100*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f04270 */
/*0110*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fd000078e0207 */
/*0140*/ @!P0 BRA 0xea0 ; /* 0x00000d5000008947 */
/* 0x000fea0003800000 */
/*0150*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*0160*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0170*/ @!P1 BRA 0xa00 ; /* 0x0000088000009947 */
/* 0x000fea0003800000 */
/*0180*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0190*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fd80003f26270 */
/*01a0*/ BSSY B0, 0x220 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*01b0*/ @P1 BRA 0x210 ; /* 0x0000005000001947 */
/* 0x001fea0003800000 */
/*01c0*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea8000c1e1b00 */
/*01d0*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*01e0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*01f0*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0200*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ BSSY B0, 0x2a0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0230*/ @P1 BRA 0x290 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0240*/ LDG.E.64 R12, [R4.64+0x8] ; /* 0x00000804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0250*/ LDG.E.64 R14, [R6.64+0x8] ; /* 0x00000804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0270*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0280*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0290*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02a0*/ BSSY B0, 0x320 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*02b0*/ @P1 BRA 0x310 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x001ea8000c1e1b00 */
/*02d0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ea8000c1e1b00 */
/*02e0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*02f0*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0300*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ BSSY B0, 0x3a0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0330*/ @P1 BRA 0x390 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0340*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0350*/ LDG.E.64 R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0360*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0370*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0380*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0390*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*03a0*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f26270 */
/*03b0*/ BSSY B0, 0x430 ; /* 0x0000007000007945 */
/* 0x000fd80003800000 */
/*03c0*/ @P1 BRA 0x420 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*03d0*/ LDG.E.64 R12, [R6.64+0x20] ; /* 0x00002004060c7981 */
/* 0x001ea8000c1e1b00 */
/*03e0*/ LDG.E.64 R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000ea8000c1e1b00 */
/*03f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0400*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0410*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0420*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0430*/ BSSY B0, 0x4b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0440*/ @P1 BRA 0x4a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0450*/ LDG.E.64 R12, [R4.64+0x28] ; /* 0x00002804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0460*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0470*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0480*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0490*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*04a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*04b0*/ BSSY B0, 0x530 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*04c0*/ @P1 BRA 0x520 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*04d0*/ LDG.E.64 R12, [R4.64+0x30] ; /* 0x00003004040c7981 */
/* 0x001ea8000c1e1b00 */
/*04e0*/ LDG.E.64 R14, [R6.64+0x30] ; /* 0x00003004060e7981 */
/* 0x000ea8000c1e1b00 */
/*04f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0500*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0510*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0520*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0530*/ BSSY B0, 0x5b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0540*/ @P1 BRA 0x5a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0550*/ LDG.E.64 R12, [R4.64+0x38] ; /* 0x00003804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0560*/ LDG.E.64 R14, [R6.64+0x38] ; /* 0x00003804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0570*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0580*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0590*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*05a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05b0*/ BSSY B0, 0x630 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*05c0*/ @P1 BRA 0x620 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*05d0*/ LDG.E.64 R12, [R6.64+0x40] ; /* 0x00004004060c7981 */
/* 0x001ea8000c1e1b00 */
/*05e0*/ LDG.E.64 R14, [R4.64+0x40] ; /* 0x00004004040e7981 */
/* 0x000ea8000c1e1b00 */
/*05f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0600*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0610*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0620*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0630*/ BSSY B0, 0x6b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0640*/ @P1 BRA 0x6a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0650*/ LDG.E.64 R12, [R4.64+0x48] ; /* 0x00004804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0660*/ LDG.E.64 R14, [R6.64+0x48] ; /* 0x00004804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0670*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0680*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0690*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*06a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06b0*/ BSSY B0, 0x730 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*06c0*/ @P1 BRA 0x720 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*06d0*/ LDG.E.64 R12, [R4.64+0x50] ; /* 0x00005004040c7981 */
/* 0x001ea8000c1e1b00 */
/*06e0*/ LDG.E.64 R14, [R6.64+0x50] ; /* 0x00005004060e7981 */
/* 0x000ea8000c1e1b00 */
/*06f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0700*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0710*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0720*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0730*/ BSSY B0, 0x7b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0740*/ @P1 BRA 0x7a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0750*/ LDG.E.64 R12, [R4.64+0x58] ; /* 0x00005804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0760*/ LDG.E.64 R14, [R6.64+0x58] ; /* 0x00005804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0770*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0780*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0790*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*07a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07b0*/ BSSY B0, 0x830 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*07c0*/ @P1 BRA 0x820 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*07d0*/ LDG.E.64 R12, [R6.64+0x60] ; /* 0x00006004060c7981 */
/* 0x001ea8000c1e1b00 */
/*07e0*/ LDG.E.64 R14, [R4.64+0x60] ; /* 0x00006004040e7981 */
/* 0x000ea8000c1e1b00 */
/*07f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0800*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0810*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0820*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0830*/ BSSY B0, 0x8b0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0840*/ @P1 BRA 0x8a0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0850*/ LDG.E.64 R12, [R4.64+0x68] ; /* 0x00006804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0860*/ LDG.E.64 R14, [R6.64+0x68] ; /* 0x00006804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0870*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0880*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0890*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*08a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08b0*/ BSSY B0, 0x930 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*08c0*/ @P1 BRA 0x920 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*08d0*/ LDG.E.64 R12, [R4.64+0x70] ; /* 0x00007004040c7981 */
/* 0x001ea8000c1e1b00 */
/*08e0*/ LDG.E.64 R14, [R6.64+0x70] ; /* 0x00007004060e7981 */
/* 0x000ea8000c1e1b00 */
/*08f0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0900*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0910*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0920*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0930*/ @!P1 LDG.E.64 R12, [R4.64+0x78] ; /* 0x00007804040c9981 */
/* 0x0010a8000c1e1b00 */
/*0940*/ @!P1 LDG.E.64 R14, [R6.64+0x78] ; /* 0x00007804060e9981 */
/* 0x0002a8000c1e1b00 */
/*0950*/ @!P1 LDG.E.64 R16, [R2.64] ; /* 0x0000000402109981 */
/* 0x000ea2000c1e1b00 */
/*0960*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe40007ffe0ff */
/*0970*/ IADD3 R4, P4, R4, 0x80, RZ ; /* 0x0000008004047810 */
/* 0x001fc40007f9e0ff */
/*0980*/ ISETP.GT.AND P2, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f44270 */
/*0990*/ IADD3 R6, P3, R6, 0x80, RZ ; /* 0x0000008006067810 */
/* 0x002fe20007f7e0ff */
/*09a0*/ IMAD.X R5, RZ, RZ, R5, P4 ; /* 0x000000ffff057224 */
/* 0x000fe200020e0605 */
/*09b0*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fc60007ffe0ff */
/*09c0*/ IMAD.X R7, RZ, RZ, R7, P3 ; /* 0x000000ffff077224 */
/* 0x000fe200018e0607 */
/*09d0*/ @!P1 DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c922b */
/* 0x004e0e0000000010 */
/*09e0*/ @!P1 STG.E.64 [R2.64], R12 ; /* 0x0000000c02009986 */
/* 0x0011e2000c101b04 */
/*09f0*/ @P2 BRA 0x1a0 ; /* 0xfffff7a000002947 */
/* 0x000fea000383ffff */
/*0a00*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*0a10*/ @!P1 BRA 0xe80 ; /* 0x0000046000009947 */
/* 0x000fea0003800000 */
/*0a20*/ ISETP.GE.AND P5, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003fa6270 */
/*0a30*/ BSSY B0, 0xb00 ; /* 0x000000c000007945 */
/* 0x000fd80003800000 */
/*0a40*/ @P5 BRA 0xaf0 ; /* 0x000000a000005947 */
/* 0x000fea0003800000 */
/*0a50*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0a60*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*0a70*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0a80*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0a90*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0aa0*/ LDG.E.64 R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea8000c1e1b00 */
/*0ab0*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ea8000c1e1b00 */
/*0ac0*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea4000c1e1b00 */
/*0ad0*/ DFMA R14, R14, R16, R18 ; /* 0x000000100e0e722b */
/* 0x004e4e0000000012 */
/*0ae0*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0021e8000c101b04 */
/*0af0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0b00*/ BSSY B0, 0xbe0 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0b10*/ @P5 BRA 0xbd0 ; /* 0x000000b000005947 */
/* 0x000fea0003800000 */
/*0b20*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x001ea8000c1e1b00 */
/*0b30*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ea8000c1e1b00 */
/*0b40*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0b50*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0b60*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e2000c101b04 */
/*0b70*/ @P5 BRA 0xbd0 ; /* 0x0000005000005947 */
/* 0x000fea0003800000 */
/*0b80*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x001ea8000c1e1b00 */
/*0b90*/ LDG.E.64 R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ea8000c1e1b00 */
/*0ba0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0bb0*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0bc0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0bd0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0be0*/ IADD3 R12, P1, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x001fe20007f3e0ff */
/*0bf0*/ BSSY B0, 0xd40 ; /* 0x0000014000007945 */
/* 0x000fe20003800000 */
/*0c00*/ IADD3 R14, P2, R4, 0x20, RZ ; /* 0x00000020040e7810 */
/* 0x000fe40007f5e0ff */
/*0c10*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0c20*/ IMAD.X R13, RZ, RZ, R7, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0607 */
/*0c30*/ IADD3 R11, P3, R12, 0x20, RZ ; /* 0x000000200c0b7810 */
/* 0x000fe20007f7e0ff */
/*0c40*/ IMAD.X R15, RZ, RZ, R5, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe200010e0605 */
/*0c50*/ IADD3 R16, P4, R14, 0x20, RZ ; /* 0x000000200e107810 */
/* 0x000fe40007f9e0ff */
/*0c60*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc40007ffe0ff */
/*0c70*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0c80*/ @P5 BRA 0xd30 ; /* 0x000000a000005947 */
/* 0x000fea0003800000 */
/*0c90*/ LDG.E.64 R6, [R6.64+0x20] ; /* 0x0000200406067981 */
/* 0x000ea8000c1e1b00 */
/*0ca0*/ LDG.E.64 R4, [R4.64+0x20] ; /* 0x0000200404047981 */
/* 0x000ea8000c1e1b00 */
/*0cb0*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea4000c1e1b00 */
/*0cc0*/ DFMA R18, R6, R4, R18 ; /* 0x000000040612722b */
/* 0x004e0e0000000012 */
/*0cd0*/ STG.E.64 [R2.64], R18 ; /* 0x0000001202007986 */
/* 0x0011e8000c101b04 */
/*0ce0*/ LDG.E.64 R20, [R14.64+0x8] ; /* 0x000008040e147981 */
/* 0x000ea8000c1e1b00 */
/*0cf0*/ LDG.E.64 R22, [R12.64+0x8] ; /* 0x000008040c167981 */
/* 0x000ea8000c1e1b00 */
/*0d00*/ LDG.E.64 R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000ea4000c1e1b00 */
/*0d10*/ DFMA R20, R20, R22, R24 ; /* 0x000000161414722b */
/* 0x004e4e0000000018 */
/*0d20*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x0021e8000c101b04 */
/*0d30*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0d40*/ BSSY B0, 0xe20 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0d50*/ @P5 BRA 0xe10 ; /* 0x000000b000005947 */
/* 0x000fea0003800000 */
/*0d60*/ LDG.E.64 R4, [R14.64+0x10] ; /* 0x000010040e047981 */
/* 0x000ea8000c1e1b00 */
/*0d70*/ LDG.E.64 R6, [R12.64+0x10] ; /* 0x000010040c067981 */
/* 0x000ea8000c1e1b00 */
/*0d80*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x001ea4000c1e1b00 */
/*0d90*/ DFMA R4, R4, R6, R18 ; /* 0x000000060404722b */
/* 0x004e0e0000000012 */
/*0da0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0011e2000c101b04 */
/*0db0*/ @P5 BRA 0xe10 ; /* 0x0000005000005947 */
/* 0x000fea0003800000 */
/*0dc0*/ LDG.E.64 R4, [R14.64+0x18] ; /* 0x000018040e047981 */
/* 0x001ea8000c1e1b00 */
/*0dd0*/ LDG.E.64 R6, [R12.64+0x18] ; /* 0x000018040c067981 */
/* 0x000ea8000c1e1b00 */
/*0de0*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea4000c1e1b00 */
/*0df0*/ DFMA R4, R4, R6, R18 ; /* 0x000000060404722b */
/* 0x004e0e0000000012 */
/*0e00*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x0011e8000c101b04 */
/*0e10*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0e20*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*0e30*/ IMAD.X R7, RZ, RZ, R13, P3 ; /* 0x000000ffff077224 */
/* 0x000fe200018e060d */
/*0e40*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0e50*/ IMAD.X R5, RZ, RZ, R15, P4 ; /* 0x000000ffff057224 */
/* 0x001fe400020e060f */
/*0e60*/ IMAD.MOV.U32 R6, RZ, RZ, R11 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000b */
/*0e70*/ IMAD.MOV.U32 R4, RZ, RZ, R16 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0010 */
/*0e80*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0e90*/ @!P0 BRA 0x10e0 ; /* 0x0000024000008947 */
/* 0x000fea0003800000 */
/*0ea0*/ ISETP.GE.AND P3, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fd80003f66270 */
/*0eb0*/ BSSY B0, 0xf80 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0ec0*/ @P3 BRA 0xf70 ; /* 0x000000a000003947 */
/* 0x001fea0003800000 */
/*0ed0*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x001ea8000c1e1b00 */
/*0ee0*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ea8000c1e1b00 */
/*0ef0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0f00*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0f10*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*0f20*/ LDG.E.64 R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea8000c1e1b00 */
/*0f30*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ea8000c1e1b00 */
/*0f40*/ LDG.E.64 R18, [R2.64] ; /* 0x0000000402127981 */
/* 0x000ea4000c1e1b00 */
/*0f50*/ DFMA R14, R14, R16, R18 ; /* 0x000000100e0e722b */
/* 0x004e4e0000000012 */
/*0f60*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0021e8000c101b04 */
/*0f70*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0f80*/ BSSY B0, 0x1060 ; /* 0x000000d000007945 */
/* 0x000fe20003800000 */
/*0f90*/ @P3 BRA 0x1050 ; /* 0x000000b000003947 */
/* 0x000fea0003800000 */
/*0fa0*/ LDG.E.64 R12, [R4.64+0x10] ; /* 0x00001004040c7981 */
/* 0x001ea8000c1e1b00 */
/*0fb0*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000ea8000c1e1b00 */
/*0fc0*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*0fd0*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*0fe0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e2000c101b04 */
/*0ff0*/ @P3 BRA 0x1050 ; /* 0x0000005000003947 */
/* 0x000fea0003800000 */
/*1000*/ LDG.E.64 R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x001ea8000c1e1b00 */
/*1010*/ LDG.E.64 R14, [R6.64+0x18] ; /* 0x00001804060e7981 */
/* 0x000ea8000c1e1b00 */
/*1020*/ LDG.E.64 R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000ea4000c1e1b00 */
/*1030*/ DFMA R12, R12, R14, R16 ; /* 0x0000000e0c0c722b */
/* 0x004e0e0000000010 */
/*1040*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0011e8000c101b04 */
/*1050*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*1060*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe40007ffe0ff */
/*1070*/ IADD3 R6, P1, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x000fe40007f3e0ff */
/*1080*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f05270 */
/*1090*/ IADD3 R4, P2, R4, 0x20, RZ ; /* 0x0000002004047810 */
/* 0x000fe20007f5e0ff */
/*10a0*/ IMAD.X R7, RZ, RZ, R7, P1 ; /* 0x000000ffff077224 */
/* 0x000fe200008e0607 */
/*10b0*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fc60007ffe0ff */
/*10c0*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fcc00010e0605 */
/*10d0*/ @P0 BRA 0xeb0 ; /* 0xfffffdd000000947 */
/* 0x000fea000383ffff */
/*10e0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*10f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*1100*/ IMAD.MOV.U32 R7, RZ, RZ, 0x8 ; /* 0x00000008ff077424 */
/* 0x000fe200078e00ff */
/*1110*/ ISETP.GE.AND P3, PT, R0.reuse, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x040fe20003f66270 */
/*1120*/ IMAD R6, R0, c[0x0][0x178], R9 ; /* 0x00005e0000067a24 */
/* 0x000fe400078e0209 */
/*1130*/ IMAD.WIDE R4, R9, R7, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fc800078e0207 */
/*1140*/ IMAD.WIDE R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e0207 */
/*1150*/ IMAD.MOV.U32 R14, RZ, RZ, R4 ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e0004 */
/*1160*/ IMAD.MOV.U32 R15, RZ, RZ, R5 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0005 */
/*1170*/ IMAD.MOV.U32 R0, RZ, RZ, R6 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0006 */
/*1180*/ IMAD.MOV.U32 R9, RZ, RZ, R7 ; /* 0x000000ffff097224 */
/* 0x000fe400078e0007 */
/*1190*/ @!P3 IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff06b224 */
/* 0x000fe200078e000e */
/*11a0*/ @!P3 LDG.E.64 R10, [R2.64] ; /* 0x00000004020ab981 */
/* 0x000ea2000c1e1b00 */
/*11b0*/ @!P3 IMAD.MOV.U32 R7, RZ, RZ, R15 ; /* 0x000000ffff07b224 */
/* 0x000fe400078e000f */
/*11c0*/ @!P3 IMAD.MOV.U32 R12, RZ, RZ, R0 ; /* 0x000000ffff0cb224 */
/* 0x000fc400078e0000 */
/*11d0*/ @!P3 IMAD.MOV.U32 R13, RZ, RZ, R9 ; /* 0x000000ffff0db224 */
/* 0x000fe400078e0009 */
/*11e0*/ @!P3 LDG.E.64 R6, [R6.64] ; /* 0x000000040606b981 */
/* 0x000ea8000c1e1b00 */
/*11f0*/ @!P3 LDG.E.64 R4, [R12.64] ; /* 0x000000040c04b981 */
/* 0x001ea2000c1e1b00 */
/*1200*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*1210*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*1220*/ IADD3 R14, P1, R14, 0x8, RZ ; /* 0x000000080e0e7810 */
/* 0x000fe40007f3e0ff */
/*1230*/ IADD3 R0, P2, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc60007f5e0ff */
/*1240*/ IMAD.X R15, RZ, RZ, R15, P1 ; /* 0x000000ffff0f7224 */
/* 0x000fe400008e060f */
/*1250*/ IMAD.X R9, RZ, RZ, R9, P2 ; /* 0x000000ffff097224 */
/* 0x000fe200010e0609 */
/*1260*/ @!P3 DFMA R4, R4, R6, R10 ; /* 0x000000060404b22b */
/* 0x004e0e000000000a */
/*1270*/ @!P3 STG.E.64 [R2.64], R4 ; /* 0x000000040200b986 */
/* 0x0011e2000c101b04 */
/*1280*/ @P0 BRA 0x1190 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*1290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*12a0*/ BRA 0x12a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPdS_S_i
.globl _Z9addKernelPdS_S_i
.p2align 8
.type _Z9addKernelPdS_S_i,@function
_Z9addKernelPdS_S_i:
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_5
s_clause 0x1
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v2, 3, v0
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_mul_lo_u32 v0, v0, s2
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v2, s0, s8, v2
v_add_co_ci_u32_e64 v3, null, s9, 0, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s2, s2, -1
v_add_nc_u32_e32 v0, 1, v0
s_add_u32 s6, s6, 8
s_addc_u32 s7, s7, 0
s_cmp_eq_u32 s2, 0
s_cbranch_scc1 .LBB0_5
.LBB0_3:
s_and_saveexec_b32 s1, vcc_lo
s_cbranch_execz .LBB0_2
v_lshlrev_b64 v[4:5], 3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s4, v4
v_add_co_ci_u32_e64 v5, s0, s5, v5, s0
global_load_b64 v[6:7], v1, s[6:7]
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[8:9], v[2:3], off
s_waitcnt vmcnt(0)
v_fma_f64 v[4:5], v[4:5], v[6:7], v[8:9]
global_store_b64 v[2:3], v[4:5], off
s_branch .LBB0_2
.LBB0_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 10
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPdS_S_i, .Lfunc_end0-_Z9addKernelPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 12
.sgpr_spill_count: 0
.symbol: _Z9addKernelPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f93e1_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z12simple_dgemvPdS_S_i
.type _Z12simple_dgemvPdS_S_i, @function
_Z12simple_dgemvPdS_S_i:
.LFB2057:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movq %rdx, %r8
movslq %ecx, %rcx
salq $3, %rcx
addq %rcx, %rdx
.L5:
movl $0, %eax
pxor %xmm1, %xmm1
.L6:
movsd (%rdi,%rax), %xmm0
mulsd (%rsi,%rax), %xmm0
addsd %xmm0, %xmm1
addq $8, %rax
cmpq %rcx, %rax
jne .L6
movsd %xmm1, (%r8)
addq $8, %r8
addq %rcx, %rdi
cmpq %rdx, %r8
jne .L5
.L3:
ret
.cfi_endproc
.LFE2057:
.size _Z12simple_dgemvPdS_S_i, .-_Z12simple_dgemvPdS_S_i
.globl _Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i
.type _Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i, @function
_Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L12
.L8:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L13
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L12:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9addKernelPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L8
.L13:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i, .-_Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i
.globl _Z9addKernelPdS_S_i
.type _Z9addKernelPdS_S_i, @function
_Z9addKernelPdS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9addKernelPdS_S_i, .-_Z9addKernelPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC5:
.string "\n\nRunning Kernel...\n\n"
.LC6:
.string "%f\n"
.LC7:
.string "pause"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $200, %edi
call malloc@PLT
movq %rax, %rbx
movl $40, %edi
call malloc@PLT
movq %rax, %r13
movl $40, %edi
call malloc@PLT
movq %rax, %r12
movl $0, %eax
.L17:
pxor %xmm0, %xmm0
cvtsi2sdl %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
addq $1, %rax
cmpq $25, %rax
jne .L17
movq $0x000000000, 0(%r13)
movq .LC1(%rip), %rax
movq %rax, 8(%r13)
movq .LC2(%rip), %rax
movq %rax, 16(%r13)
movq .LC3(%rip), %rax
movq %rax, 24(%r13)
movq .LC4(%rip), %rax
movq %rax, 32(%r13)
movq $0x000000000, (%r12)
movq $0x000000000, 8(%r12)
movq $0x000000000, 16(%r12)
movq $0x000000000, 24(%r12)
movq $0x000000000, 32(%r12)
leaq 8(%rsp), %rdi
movl $200, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $40, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $200, %edx
movq %rbx, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $40, %edx
movq %r12, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $5, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L18:
movl $2, %ecx
movl $40, %edx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rbp
leaq 40(%r12), %r15
leaq .LC6(%rip), %r14
.L19:
movsd 0(%rbp), %xmm0
movq %r14, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbp
cmpq %r15, %rbp
jne .L19
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
leaq .LC7(%rip), %rdi
call system@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L25
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl $5, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z9addKernelPdS_S_iPdS_S_i
jmp .L18
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z9addKernelPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long 0
.long 1072693248
.align 8
.LC2:
.long 0
.long 1073741824
.align 8
.LC3:
.long 0
.long 1074266112
.align 8
.LC4:
.long 0
.long 1074790400
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z24__device_stub__addKernelPdS_S_i # -- Begin function _Z24__device_stub__addKernelPdS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPdS_S_i,@function
_Z24__device_stub__addKernelPdS_S_i: # @_Z24__device_stub__addKernelPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9addKernelPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__addKernelPdS_S_i, .Lfunc_end0-_Z24__device_stub__addKernelPdS_S_i
.cfi_endproc
# -- End function
.globl _Z12simple_dgemvPdS_S_i # -- Begin function _Z12simple_dgemvPdS_S_i
.p2align 4, 0x90
.type _Z12simple_dgemvPdS_S_i,@function
_Z12simple_dgemvPdS_S_i: # @_Z12simple_dgemvPdS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB1_5
# %bb.1: # %.preheader.lr.ph
movl %ecx, %eax
xorl %r8d, %r8d
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %r8d, %r10d
leaq (%rdi,%r10,8), %r10
xorpd %xmm0, %xmm0
xorl %r11d, %r11d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r10,%r11,8), %xmm1 # xmm1 = mem[0],zero
mulsd (%rsi,%r11,8), %xmm1
addsd %xmm1, %xmm0
incq %r11
cmpq %r11, %rax
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
movsd %xmm0, (%rdx,%r9,8)
incq %r9
addl %ecx, %r8d
cmpq %rax, %r9
jne .LBB1_2
.LBB1_5: # %._crit_edge21
retq
.Lfunc_end1:
.size _Z12simple_dgemvPdS_S_i, .Lfunc_end1-_Z12simple_dgemvPdS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $152, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $200, %edi
callq malloc
movq %rax, %rbx
movl $40, %edi
callq malloc
movq %rax, %r14
movl $40, %edi
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rbx,%rax,8)
incq %rax
cmpq $25, %rax
jne .LBB2_1
# %bb.2: # %.preheader56.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_3: # %.preheader56
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%r14,%rax,8)
incq %rax
cmpq $5, %rax
jne .LBB2_3
# %bb.4: # %.preheader.preheader
xorpd %xmm0, %xmm0
movupd %xmm0, 16(%r15)
movupd %xmm0, (%r15)
movq $0, 32(%r15)
leaq 24(%rsp), %rdi
movl $200, %esi
callq hipMalloc
leaq 16(%rsp), %rdi
movl $40, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $40, %esi
callq hipMalloc
movq 24(%rsp), %rdi
movl $200, %edx
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $40, %edx
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movl $40, %edx
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 4(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $5, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z9addKernelPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
movq 8(%rsp), %rsi
movl $40, %edx
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $5, %r12
jne .LBB2_7
# %bb.8:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movl $.L.str.2, %edi
callq system
xorl %eax, %eax
addq $152, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addKernelPdS_S_i,@object # @_Z9addKernelPdS_S_i
.section .rodata,"a",@progbits
.globl _Z9addKernelPdS_S_i
.p2align 3, 0x0
_Z9addKernelPdS_S_i:
.quad _Z24__device_stub__addKernelPdS_S_i
.size _Z9addKernelPdS_S_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%f\n"
.size .L.str.1, 4
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "pause"
.size .L.str.2, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPdS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\n\nRunning Kernel...\n"
.size .Lstr, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cstdio>
__global__ void mykern() {
int idx = threadIdx.x;
__shared__ int array[128];
array[idx] = threadIdx.x;
__syncthreads();
if (idx < 127) {
int temp = array[idx + 1];
__syncthreads();
array[idx] = temp;
__syncthreads();
}
printf("%d %d\n", array[idx], threadIdx.x);
}
int main() {
mykern<<<1, 128>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z6mykernv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0020*/ MOV R8, 0x0 ; /* 0x0000000000087802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fc600078e00ff */
/*0060*/ LDC.64 R8, c[0x4][R8] ; /* 0x0100000008087b82 */
/* 0x000e620000000a00 */
/*0070*/ STS [R3.X4], R3 ; /* 0x0000000303007388 */
/* 0x001fe80000004800 */
/*0080*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0090*/ ISETP.GT.AND P0, PT, R3, 0x7e, PT ; /* 0x0000007e0300780c */
/* 0x000fda0003f04270 */
/*00a0*/ @!P0 WARPSYNC 0xffffffff ; /* 0xffffffff00008948 */
/* 0x000fe20003800000 */
/*00b0*/ @!P0 LDS R0, [R3.X4+0x4] ; /* 0x0000040003008984 */
/* 0x000e280000004800 */
/*00c0*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fec0000010000 */
/*00d0*/ @!P0 STS [R3.X4], R0 ; /* 0x0000000003008388 */
/* 0x001fe80000004800 */
/*00e0*/ @!P0 BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000008b1d */
/* 0x000fe20000010000 */
/*00f0*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0100*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe200000e06ff */
/*0110*/ LDS R2, [R3.X4] ; /* 0x0000000003027984 */
/* 0x000e280000004800 */
/*0120*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0011e60000100a00 */
/*0130*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe40000000000 */
/*0140*/ MOV R11, 0x1b0 ; /* 0x000001b0000b7802 */
/* 0x000fe40000000f00 */
/*0150*/ MOV R20, 0x130 ; /* 0x0000013000147802 */
/* 0x000fe40000000f00 */
/*0160*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0170*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0180*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0190*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*01a0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cstdio>
__global__ void mykern() {
int idx = threadIdx.x;
__shared__ int array[128];
array[idx] = threadIdx.x;
__syncthreads();
if (idx < 127) {
int temp = array[idx + 1];
__syncthreads();
array[idx] = temp;
__syncthreads();
}
printf("%d %d\n", array[idx], threadIdx.x);
}
int main() {
mykern<<<1, 128>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000d8a47_00000000-6_sharedarr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6mykernvv
.type _Z24__device_stub__Z6mykernvv, @function
_Z24__device_stub__Z6mykernvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6mykernv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6mykernvv, .-_Z24__device_stub__Z6mykernvv
.globl _Z6mykernv
.type _Z6mykernv, @function
_Z6mykernv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6mykernvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6mykernv, .-_Z6mykernv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6mykernvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6mykernv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6mykernv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cstdio>
__global__ void mykern() {
int idx = threadIdx.x;
__shared__ int array[128];
array[idx] = threadIdx.x;
__syncthreads();
if (idx < 127) {
int temp = array[idx + 1];
__syncthreads();
array[idx] = temp;
__syncthreads();
}
printf("%d %d\n", array[idx], threadIdx.x);
}
int main() {
mykern<<<1, 128>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <cstdio>
__global__ void mykern() {
int idx = threadIdx.x;
__shared__ int array[128];
array[idx] = threadIdx.x;
__syncthreads();
if (idx < 127) {
int temp = array[idx + 1];
__syncthreads();
array[idx] = temp;
__syncthreads();
}
printf("%d %d\n", array[idx], threadIdx.x);
}
int main() {
mykern<<<1, 128>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
__global__ void mykern() {
int idx = threadIdx.x;
__shared__ int array[128];
array[idx] = threadIdx.x;
__syncthreads();
if (idx < 127) {
int temp = array[idx + 1];
__syncthreads();
array[idx] = temp;
__syncthreads();
}
printf("%d %d\n", array[idx], threadIdx.x);
}
int main() {
mykern<<<1, 128>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "sharedarr.hip"
.globl _Z21__device_stub__mykernv # -- Begin function _Z21__device_stub__mykernv
.p2align 4, 0x90
.type _Z21__device_stub__mykernv,@function
_Z21__device_stub__mykernv: # @_Z21__device_stub__mykernv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6mykernv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__mykernv, .Lfunc_end0-_Z21__device_stub__mykernv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6mykernv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6mykernv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6mykernv,@object # @_Z6mykernv
.section .rodata,"a",@progbits
.globl _Z6mykernv
.p2align 3, 0x0
_Z6mykernv:
.quad _Z21__device_stub__mykernv
.size _Z6mykernv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6mykernv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__mykernv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6mykernv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d8a47_00000000-6_sharedarr.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z6mykernvv
.type _Z24__device_stub__Z6mykernvv, @function
_Z24__device_stub__Z6mykernvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z6mykernv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z6mykernvv, .-_Z24__device_stub__Z6mykernvv
.globl _Z6mykernv
.type _Z6mykernv, @function
_Z6mykernv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z6mykernvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6mykernv, .-_Z6mykernv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $128, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z24__device_stub__Z6mykernvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6mykernv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6mykernv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sharedarr.hip"
.globl _Z21__device_stub__mykernv # -- Begin function _Z21__device_stub__mykernv
.p2align 4, 0x90
.type _Z21__device_stub__mykernv,@function
_Z21__device_stub__mykernv: # @_Z21__device_stub__mykernv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6mykernv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z21__device_stub__mykernv, .Lfunc_end0-_Z21__device_stub__mykernv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 127(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z6mykernv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6mykernv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6mykernv,@object # @_Z6mykernv
.section .rodata,"a",@progbits
.globl _Z6mykernv
.p2align 3, 0x0
_Z6mykernv:
.quad _Z21__device_stub__mykernv
.size _Z6mykernv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6mykernv"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__mykernv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6mykernv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <fstream>
#include <iostream>
#include <string.h>
#include <vector>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
#include <time.h>
#include <cuda.h>
//#include "sha256.h"
#define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word
//define for sha256
#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))
#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))
#define GPUerrchk(ans) { GPUassert((ans), __FILE__, __LINE__); }
//#define numThread 1024*22
typedef struct {
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;
__constant__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};
//__constant__ uchar answer[32];
//==============cuda kernel=====================================
__device__ void sha256_transform(SHA256_CTX *ctx, uchar *data){
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha256(SHA256_CTX *ctx, uchar *data, uchar *hash, int len){
//init sha256 data structure
ctx->datalen = 0;
ctx->bitlen[0] = 0;
ctx->bitlen[1] = 0;
ctx->state[0] = 0x6a09e667;
ctx->state[1] = 0xbb67ae85;
ctx->state[2] = 0x3c6ef372;
ctx->state[3] = 0xa54ff53a;
ctx->state[4] = 0x510e527f;
ctx->state[5] = 0x9b05688c;
ctx->state[6] = 0x1f83d9ab;
ctx->state[7] = 0x5be0cd19;
//update
uint i;
//uint len = 5; //need to fix!!
for (i=0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha256_transform(ctx,ctx->data);
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],512);
ctx->datalen = 0;
}
}
//final
i = ctx->datalen;
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha256_transform(ctx,ctx->data);
memset(ctx->data,0,56);
}
//par here
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],ctx->datalen * 8);
ctx->data[63] = ctx->bitlen[0];
ctx->data[62] = ctx->bitlen[0] >> 8;
ctx->data[61] = ctx->bitlen[0] >> 16;
ctx->data[60] = ctx->bitlen[0] >> 24;
ctx->data[59] = ctx->bitlen[1];
ctx->data[58] = ctx->bitlen[1] >> 8;
ctx->data[57] = ctx->bitlen[1] >> 16;
ctx->data[56] = ctx->bitlen[1] >> 24;
sha256_transform(ctx,ctx->data);
//we can paralized at here
for (i=0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24-i*8)) & 0x000000ff;
hash[i+4] = (ctx->state[1] >> (24-i*8)) & 0x000000ff;
hash[i+8] = (ctx->state[2] >> (24-i*8)) & 0x000000ff;
hash[i+12] = (ctx->state[3] >> (24-i*8)) & 0x000000ff;
hash[i+16] = (ctx->state[4] >> (24-i*8)) & 0x000000ff;
hash[i+20] = (ctx->state[5] >> (24-i*8)) & 0x000000ff;
hash[i+24] = (ctx->state[6] >> (24-i*8)) & 0x000000ff;
hash[i+28] = (ctx->state[7] >> (24-i*8)) & 0x000000ff;
}
}
__device__ void sha256_hash(SHA256_CTX *ctx, uchar *data, uchar *hash, int len, int round){
sha256(ctx, data, hash, len);
while(round > 1){
sha256(ctx, hash, hash, 32);
round --;
}
}
__device__ int my_strcmp(uchar *str_a, uchar *str_b, uint len){
for(int i=0; i<len; i++){
if(str_a[i] != str_b[i])
return false;
}
return true;
}
__global__ void sha256_wrap(uchar *pwarray, uchar *target, int* pwcount, uchar *result){
int idx = threadIdx.x + blockDim.x * blockIdx.x;
uchar* data = (uchar*)malloc(pwcount[idx]*sizeof(uchar));
SHA256_CTX ctx;// = new SHA256_CTX;
uchar hash[32];
int round = 10000, count = 0;
for(int i=0; i<idx; i++){
count += pwcount[i];
}
memcpy(data,&pwarray[count],pwcount[idx]*sizeof(uchar));
sha256_hash(&ctx,data,hash,pwcount[idx],round);
for (int i=0; i<5;i++){
if(my_strcmp(hash,&target[32*i],32))
memcpy(result,data,pwcount[idx]*sizeof(uchar));
}
}
//====================================================================
void print_hash(unsigned char hash[]){
int idx;
for (idx=0; idx < 32; idx++)
printf("%02x",hash[idx]);
printf("\n");
}
void read_hash(char filename[],unsigned char target[5][32]){
FILE *rhash = fopen(filename,"r+");
fread(target[0],1,32,rhash);
fread(target[1],1,32,rhash);
fread(target[2],1,32,rhash);
fread(target[3],1,32,rhash);
fread(target[4],1,32,rhash);
fclose(rhash);
}
void cudasafe(cudaError_t error, char* message){
if(error!=cudaSuccess) { fprintf(stderr,"ERROR: %s : %i\n",message,error); exit(-1);}
}
//============================================================================
int main(int argc, char **argv){
std::string password;
std::vector<std::string> pwarray;
int tot_dict_size = 0;
int dict_size = 55*1024;
int numThread = 55*1024;
uchar target[5][32];
uchar *result = new uchar[32];
//variable for GPU
// uchar *dev_result;
uchar *dev_target;
// uchar *dev_password;
// int *dev_pwcount;
if(argc < 2){
std::cerr << "need load dictionary!! \n";
return 1;
}
//timing program
struct timeval starttime, endtime;
double runTime = 0.0;
gettimeofday(&starttime,NULL);
//read target hash
read_hash(argv[2],target);
//copy hash into cuda (maybe into constant memory?)
// cudaMalloc((void**)&dev_target,32*5*sizeof(uchar));
// for(int i=0;i<5;i++){
// cudaMemcpy((void*)&dev_target[32*i],target[i],32*sizeof(uchar),cudaMemcpyHostToDevice);
// }
//read from dictionary
std::ifstream dict(argv[1]);
if(!dict){
std::cerr << "No such file!! \n";
return 1;
}
while(std::getline(dict, password)){
pwarray.push_back(password);
tot_dict_size++;
}
uchar *pwstring = (uchar*)malloc(dict_size*32*sizeof(uchar));
int *pw_count = (int*)malloc(dict_size*sizeof(int));
//============================================================
for(int lp = 0; lp < tot_dict_size/numThread + 1; lp++){
//devpassword
//variable for GPU
uchar *dev_result;
uchar *dev_password;
int *dev_pwcount;
if(lp == tot_dict_size/numThread && tot_dict_size%numThread != 0){
dict_size = tot_dict_size % numThread;
}
//int *pw_count = (int*)malloc(dict_size*sizeof(int));
int temp_count = 0;
//uchar *pwstring = (uchar*)malloc(dict_size*32*sizeof(uchar));
for(int i=0; i<dict_size; i++){
pw_count[i] = pwarray.at(i+lp*numThread).length();
strcpy((char*)&pwstring[temp_count],pwarray.at(i+lp*numThread).c_str());
temp_count += pw_count[i];
}
cudasafe( cudaMalloc((void**)&dev_password,32*dict_size*sizeof(uchar)), "cudaMalloc");
cudasafe( cudaMemcpy((void*)dev_password,pwstring,32*dict_size*sizeof(uchar),cudaMemcpyHostToDevice), "cudaMemcpy");
cudaMalloc((void**)&dev_pwcount,dict_size*sizeof(int));
cudaMemcpy((void*)dev_pwcount,pw_count,dict_size*sizeof(int),cudaMemcpyHostToDevice);
cudaMalloc((void**)&dev_target,32*5*sizeof(uchar));
for(int i=0;i<5;i++){
cudaMemcpy((void*)&dev_target[32*i],target[i],32*sizeof(uchar),cudaMemcpyHostToDevice);
}
cudaMalloc((void**)&dev_result,32*sizeof(uchar));
cudaMemset(dev_result,0,32*sizeof(uchar));
cudaDeviceSynchronize();
dim3 DimBlock(1024,1);
dim3 DimGrid(55,1);
sha256_wrap <<< DimGrid, DimBlock >>> (dev_password, dev_target, dev_pwcount, dev_result);
cudaDeviceSynchronize();
cudaMemcpy(result,dev_result,32*sizeof(uchar),cudaMemcpyDeviceToHost);
if(strlen((const char*)result)!= 0)
printf("password: %s \n", result);
memset(result, 0, strlen((const char*)result));
cudaDeviceReset();
// cudaFree(dev_result); cudaFree(dev_password); cudaFree(dev_pwcount);
}
gettimeofday(&endtime,NULL);
runTime=1000000*(endtime.tv_sec-starttime.tv_sec)+endtime.tv_usec-starttime.tv_usec;
runTime=runTime/1000;
printf("timing: %f ms \n",runTime);
cudaFree(dev_target);
return 0;
} | .file "tmpxft_00135918_00000000-6_cracker.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4197:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4197:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z16sha256_transformP10SHA256_CTXPh
.type _Z16sha256_transformP10SHA256_CTXPh, @function
_Z16sha256_transformP10SHA256_CTXPh:
.LFB4176:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4176:
.size _Z16sha256_transformP10SHA256_CTXPh, .-_Z16sha256_transformP10SHA256_CTXPh
.globl _Z6sha256P10SHA256_CTXPhS1_i
.type _Z6sha256P10SHA256_CTXPhS1_i, @function
_Z6sha256P10SHA256_CTXPhS1_i:
.LFB4177:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4177:
.size _Z6sha256P10SHA256_CTXPhS1_i, .-_Z6sha256P10SHA256_CTXPhS1_i
.globl _Z11sha256_hashP10SHA256_CTXPhS1_ii
.type _Z11sha256_hashP10SHA256_CTXPhS1_ii, @function
_Z11sha256_hashP10SHA256_CTXPhS1_ii:
.LFB4178:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4178:
.size _Z11sha256_hashP10SHA256_CTXPhS1_ii, .-_Z11sha256_hashP10SHA256_CTXPhS1_ii
.globl _Z9my_strcmpPhS_j
.type _Z9my_strcmpPhS_j, @function
_Z9my_strcmpPhS_j:
.LFB4179:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE4179:
.size _Z9my_strcmpPhS_j, .-_Z9my_strcmpPhS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%02x"
.LC1:
.string "\n"
.text
.globl _Z10print_hashPh
.type _Z10print_hashPh, @function
_Z10print_hashPh:
.LFB4180:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
leaq 32(%rdi), %r12
leaq .LC0(%rip), %rbp
.L12:
movzbl (%rbx), %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %r12, %rbx
jne .L12
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4180:
.size _Z10print_hashPh, .-_Z10print_hashPh
.section .rodata.str1.1
.LC2:
.string "r+"
.text
.globl _Z9read_hashPcPA32_h
.type _Z9read_hashPcPA32_h, @function
_Z9read_hashPcPA32_h:
.LFB4181:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movq %rsi, %rbx
leaq .LC2(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movq %rax, %r8
movl $32, %ecx
movl $1, %edx
movq $-1, %rsi
movq %rbx, %rdi
call __fread_chk@PLT
leaq 32(%rbx), %rdi
movq %rbp, %r8
movl $32, %ecx
movl $1, %edx
movq $-1, %rsi
call __fread_chk@PLT
leaq 64(%rbx), %rdi
movq %rbp, %r8
movl $32, %ecx
movl $1, %edx
movq $-1, %rsi
call __fread_chk@PLT
leaq 96(%rbx), %rdi
movq %rbp, %r8
movl $32, %ecx
movl $1, %edx
movq $-1, %rsi
call __fread_chk@PLT
leaq 128(%rbx), %rdi
movq %rbp, %r8
movl $32, %ecx
movl $1, %edx
movq $-1, %rsi
call __fread_chk@PLT
movq %rbp, %rdi
call fclose@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4181:
.size _Z9read_hashPcPA32_h, .-_Z9read_hashPcPA32_h
.section .rodata.str1.1
.LC3:
.string "ERROR: %s : %i\n"
.text
.globl _Z8cudasafe9cudaErrorPc
.type _Z8cudasafe9cudaErrorPc, @function
_Z8cudasafe9cudaErrorPc:
.LFB4182:
.cfi_startproc
endbr64
testl %edi, %edi
jne .L22
ret
.L22:
subq $8, %rsp
.cfi_def_cfa_offset 16
movl %edi, %r8d
movq %rsi, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $-1, %edi
call exit@PLT
.cfi_endproc
.LFE4182:
.size _Z8cudasafe9cudaErrorPc, .-_Z8cudasafe9cudaErrorPc
.globl _Z37__device_stub__Z11sha256_wrapPhS_PiS_PhS_PiS_
.type _Z37__device_stub__Z11sha256_wrapPhS_PiS_PhS_PiS_, @function
_Z37__device_stub__Z11sha256_wrapPhS_PiS_PhS_PiS_:
.LFB4219:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L27
.L23:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L28
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L27:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11sha256_wrapPhS_PiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L23
.L28:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4219:
.size _Z37__device_stub__Z11sha256_wrapPhS_PiS_PhS_PiS_, .-_Z37__device_stub__Z11sha256_wrapPhS_PiS_PhS_PiS_
.globl _Z11sha256_wrapPhS_PiS_
.type _Z11sha256_wrapPhS_PiS_, @function
_Z11sha256_wrapPhS_PiS_:
.LFB4220:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z11sha256_wrapPhS_PiS_PhS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4220:
.size _Z11sha256_wrapPhS_PiS_, .-_Z11sha256_wrapPhS_PiS_
.section .rodata.str1.1
.LC4:
.string "_Z11sha256_wrapPhS_PiS_"
.LC5:
.string "k"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4222:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z11sha256_wrapPhS_PiS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $256, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL1k(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4222:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED5Ev,comdat
.align 2
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev
.type _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev, @function
_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev:
.LFB4551:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %r12
movq 8(%rdi), %rbp
movq (%rdi), %rbx
cmpq %rbx, %rbp
jne .L36
.L34:
movq (%r12), %rdi
testq %rdi, %rdi
je .L33
movq 16(%r12), %rsi
subq %rdi, %rsi
call _ZdlPvm@PLT
.L33:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
addq $32, %rbx
cmpq %rbx, %rbp
je .L34
.L36:
movq (%rbx), %rdi
leaq 16(%rbx), %rax
cmpq %rax, %rdi
je .L35
movq 16(%rbx), %rax
leaq 1(%rax), %rsi
call _ZdlPvm@PLT
jmp .L35
.cfi_endproc
.LFE4551:
.size _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev, .-_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev
.set _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED2Ev
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag:
.LFB4778:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbx
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
subq %rsi, %rdx
movq %rdx, %rbp
movq %rdx, (%rsp)
cmpq $15, %rdx
ja .L47
movq (%rdi), %rdi
cmpq $1, %rdx
jne .L43
movzbl (%rsi), %eax
movb %al, (%rdi)
.L44:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
movq %rsp, %rsi
movl $0, %edx
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %rdi
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L42:
movq %rbp, %rdx
movq %r12, %rsi
call memcpy@PLT
jmp .L44
.L43:
testq %rdx, %rdx
je .L44
jmp .L42
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4778:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.section .rodata._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_.str1.1,"aMS",@progbits,1
.LC6:
.string "vector::_M_realloc_insert"
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.align 2
.weak _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.type _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, @function
_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_:
.LFB4745:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4745
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdx, 8(%rsp)
movq 8(%rdi), %r13
movq (%rdi), %rbp
movq %r13, %rax
subq %rbp, %rax
sarq $5, %rax
movabsq $288230376151711743, %rdx
cmpq %rdx, %rax
je .L91
movq %rdi, %r12
movq %rsi, %rbx
cmpq %rbp, %r13
movl $1, %edx
cmovne %rax, %rdx
addq %rdx, %rax
jc .L52
movabsq $288230376151711743, %rdx
cmpq %rdx, %rax
cmovbe %rax, %rdx
movq %rdx, (%rsp)
movq %rsi, %r14
subq %rbp, %r14
movl $0, %r15d
testq %rax, %rax
je .L53
jmp .L79
.L91:
leaq .LC6(%rip), %rdi
.LEHB0:
call _ZSt20__throw_length_errorPKc@PLT
.LEHE0:
.L98:
cmpq %rbp, %rbx
je .L82
leaq 16(%rbp), %rax
leaq 16(%rbx), %r8
movq %r15, %rdx
jmp .L63
.L94:
movq -8(%rcx), %r11
leaq 1(%r11), %r9
cmpl $8, %r9d
jnb .L56
testb $4, %r9b
jne .L92
testl %r9d, %r9d
je .L62
movzbl (%rcx), %r10d
movb %r10b, (%rsi)
testb $2, %r9b
je .L62
movl %r9d, %r9d
movzwl -2(%rcx,%r9), %ecx
movw %cx, -2(%rsi,%r9)
jmp .L62
.L92:
movl (%rcx), %r10d
movl %r10d, (%rsi)
movl %r9d, %r9d
movl -4(%rcx,%r9), %ecx
movl %ecx, -4(%rsi,%r9)
jmp .L62
.L56:
movq (%rcx), %r10
movq %r10, (%rsi)
movl %r9d, %r10d
movq -8(%rcx,%r10), %r11
movq %r11, -8(%rsi,%r10)
leaq 8(%rsi), %r10
andq $-8, %r10
subq %r10, %rsi
subq %rsi, %rcx
addl %esi, %r9d
andl $-8, %r9d
cmpl $8, %r9d
jb .L62
andl $-8, %r9d
movl $0, %esi
.L60:
movl %esi, %r11d
movq (%rcx,%r11), %r14
movq %r14, (%r10,%r11)
addl $8, %esi
cmpl %r9d, %esi
jb .L60
.L62:
movq -8(%rdi), %rcx
movq %rcx, 8(%rdx)
addq $32, %rdx
addq $32, %rax
cmpq %rax, %r8
je .L93
.L63:
leaq 16(%rdx), %rsi
movq %rsi, (%rdx)
movq %rax, %rdi
movq -16(%rax), %rcx
cmpq %rcx, %rax
je .L94
movq %rcx, (%rdx)
movq (%rax), %rcx
movq %rcx, 16(%rdx)
jmp .L62
.L93:
movq %rbx, %r14
subq %rbp, %r14
addq %r15, %r14
.L54:
addq $32, %r14
cmpq %r13, %rbx
je .L64
leaq 16(%rbx), %rax
leaq 16(%r13), %rdi
movq %r14, %rdx
jmp .L73
.L82:
movq %r15, %r14
jmp .L54
.L97:
movq -8(%rax), %rsi
addq $1, %rsi
movq %rax, %r11
cmpl $8, %esi
jnb .L66
testb $4, %sil
jne .L95
testl %esi, %esi
je .L72
movzbl (%rax), %r9d
movb %r9b, (%r8)
testb $2, %sil
je .L72
movl %esi, %esi
movzwl -2(%rax,%rsi), %r9d
movw %r9w, -2(%r8,%rsi)
jmp .L72
.L95:
movl (%rax), %r9d
movl %r9d, (%r8)
movl %esi, %esi
movl -4(%rax,%rsi), %r9d
movl %r9d, -4(%r8,%rsi)
jmp .L72
.L66:
movq (%rax), %r9
movq %r9, (%r8)
movl %esi, %r9d
movq -8(%rax,%r9), %r10
movq %r10, -8(%r8,%r9)
leaq 8(%r8), %r10
andq $-8, %r10
subq %r10, %r8
subq %r8, %r11
addl %r8d, %esi
andl $-8, %esi
cmpl $8, %esi
jb .L72
andl $-8, %esi
movl $0, %r8d
movq %rax, 8(%rsp)
.L70:
movl %r8d, %r9d
movq (%r11,%r9), %rax
movq %rax, (%r10,%r9)
addl $8, %r8d
cmpl %esi, %r8d
jb .L70
movq 8(%rsp), %rax
.L72:
movq -8(%rcx), %rcx
movq %rcx, 8(%rdx)
addq $32, %rdx
addq $32, %rax
cmpq %rdi, %rax
je .L96
.L73:
leaq 16(%rdx), %r8
movq %r8, (%rdx)
movq %rax, %rcx
movq -16(%rax), %rsi
cmpq %rax, %rsi
je .L97
movq %rsi, (%rdx)
movq (%rax), %rsi
movq %rsi, 16(%rdx)
jmp .L72
.L96:
subq %rbx, %r13
addq %r13, %r14
.L64:
testq %rbp, %rbp
je .L74
movq 16(%r12), %rsi
subq %rbp, %rsi
movq %rbp, %rdi
call _ZdlPvm@PLT
.L74:
movq %r15, (%r12)
movq %r14, 8(%r12)
movq (%rsp), %rax
salq $5, %rax
addq %r15, %rax
movq %rax, 16(%r12)
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L83:
.cfi_restore_state
endbr64
movq %rax, %rdi
call __cxa_begin_catch@PLT
testq %r15, %r15
jne .L76
movq %r14, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L77:
.LEHB1:
call __cxa_rethrow@PLT
.LEHE1:
.L84:
endbr64
movq %rax, %rbx
call __cxa_end_catch@PLT
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.L76:
movq (%rsp), %rsi
salq $5, %rsi
movq %r15, %rdi
call _ZdlPvm@PLT
jmp .L77
.L52:
movq %rsi, %r14
subq %rbp, %r14
movabsq $288230376151711743, %rax
movq %rax, (%rsp)
.L79:
movq (%rsp), %rdi
salq $5, %rdi
call _Znwm@PLT
.LEHE2:
movq %rax, %r15
.L53:
addq %r15, %r14
leaq 16(%r14), %rax
movq %rax, (%r14)
movq 8(%rsp), %rax
movq (%rax), %rsi
movq %rsi, %rdx
addq 8(%rax), %rdx
movq %r14, %rdi
.LEHB3:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
.LEHE3:
jmp .L98
.cfi_endproc
.LFE4745:
.globl __gxx_personality_v0
.section .gcc_except_table._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"aG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.align 4
.LLSDA4745:
.byte 0xff
.byte 0x9b
.uleb128 .LLSDATT4745-.LLSDATTD4745
.LLSDATTD4745:
.byte 0x1
.uleb128 .LLSDACSE4745-.LLSDACSB4745
.LLSDACSB4745:
.uleb128 .LEHB0-.LFB4745
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4745
.uleb128 .LEHE1-.LEHB1
.uleb128 .L84-.LFB4745
.uleb128 0
.uleb128 .LEHB2-.LFB4745
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.uleb128 .LEHB3-.LFB4745
.uleb128 .LEHE3-.LEHB3
.uleb128 .L83-.LFB4745
.uleb128 0x1
.LLSDACSE4745:
.byte 0x1
.byte 0
.align 4
.long 0
.LLSDATT4745:
.section .text._ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,"axG",@progbits,_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_,comdat
.size _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_, .-_ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
.section .rodata.str1.1
.LC7:
.string "need load dictionary!! \n"
.LC8:
.string "No such file!! \n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC9:
.string "vector::_M_range_check: __n (which is %zu) >= this->size() (which is %zu)"
.section .rodata.str1.1
.LC10:
.string "cudaMalloc"
.LC11:
.string "cudaMemcpy"
.LC12:
.string "password: %s \n"
.LC14:
.string "timing: %f ms \n"
.text
.globl main
.type main, @function
main:
.LFB4183:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4183
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $888, %rsp
.cfi_def_cfa_offset 944
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 872(%rsp)
xorl %eax, %eax
leaq 176(%rsp), %rax
movq %rax, 160(%rsp)
movq $0, 168(%rsp)
movb $0, 176(%rsp)
movq $0, 128(%rsp)
movq $0, 136(%rsp)
movq $0, 144(%rsp)
movl $32, %edi
.LEHB4:
call _Znam@PLT
movq %rax, (%rsp)
cmpl $1, %ebp
jle .L139
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
leaq 192(%rsp), %rsi
movq 16(%rbx), %rdi
call _Z9read_hashPcPA32_h
jmp .L140
.L139:
leaq .LC7(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L141
.L140:
movq 8(%rbx), %rsi
leaq 352(%rsp), %rdi
movl $8, %edx
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEEC1EPKcSt13_Ios_Openmode@PLT
.LEHE4:
movl 640(%rsp), %ebx
andl $5, %ebx
movl %ebx, 40(%rsp)
jne .L102
movq 352(%rsp), %rax
movq -24(%rax), %rax
movq 592(%rsp,%rax), %rbp
testq %rbp, %rbp
je .L103
leaq 160(%rsp), %r12
jmp .L104
.L102:
leaq .LC8(%rip), %rsi
leaq _ZSt4cerr(%rip), %rdi
.LEHB5:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L142
.L146:
addq $32, %rbp
movq %rbp, 136(%rsp)
.L107:
addl $1, %ebx
movq 352(%rsp), %rax
movq -24(%rax), %rax
movq 592(%rsp,%rax), %rbp
testq %rbp, %rbp
je .L103
.L104:
cmpb $0, 56(%rbp)
je .L109
movzbl 67(%rbp), %edx
.L110:
movsbl %dl, %edx
leaq 352(%rsp), %rdi
movq %r12, %rsi
call _ZSt7getlineIcSt11char_traitsIcESaIcEERSt13basic_istreamIT_T0_ES7_RNSt7__cxx1112basic_stringIS4_S5_T1_EES4_@PLT
jmp .L143
.L106:
leaq 128(%rsp), %rdi
movq %r12, %rdx
movq %rbp, %rsi
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EE17_M_realloc_insertIJRKS5_EEEvN9__gnu_cxx17__normal_iteratorIPS5_S7_EEDpOT_
jmp .L107
.L103:
movq 872(%rsp), %rax
subq %fs:40, %rax
jne .L144
call _ZSt16__throw_bad_castv@PLT
.L144:
call __stack_chk_fail@PLT
.L109:
movq %rbp, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq 0(%rbp), %rax
movl $10, %esi
movq %rbp, %rdi
call *48(%rax)
movl %eax, %edx
jmp .L110
.L143:
movq (%rax), %rdx
movq -24(%rdx), %rdx
testb $5, 32(%rax,%rdx)
jne .L145
movq 136(%rsp), %rbp
cmpq 144(%rsp), %rbp
je .L106
leaq 16(%rbp), %rax
movq %rax, 0(%rbp)
movq 160(%rsp), %rsi
movq %rsi, %rdx
addq 168(%rsp), %rdx
movq %rbp, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_M_constructIPcEEvT_S7_St20forward_iterator_tag
jmp .L146
.L145:
movl $1802240, %edi
call malloc@PLT
movq %rax, %r14
movl $225280, %edi
call malloc@PLT
movq %rax, 16(%rsp)
movl $56320, %ecx
movl %ebx, %eax
cltd
idivl %ecx
movl %eax, 12(%rsp)
cmpl $-56319, %ebx
jl .L112
movl %ebx, %eax
cltd
idivl %ecx
movl %edx, 44(%rsp)
movl 40(%rsp), %eax
movl %eax, 8(%rsp)
movl $0, 24(%rsp)
movl $56320, %r13d
leaq 64(%rsp), %rax
movq %rax, 32(%rsp)
jmp .L121
.L150:
movl 44(%rsp), %eax
testl %eax, %eax
cmovne %eax, %r13d
jmp .L113
.L151:
movq 872(%rsp), %rax
subq %fs:40, %rax
jne .L147
movq %rbx, %rsi
leaq .LC9(%rip), %rdi
movl $0, %eax
call _ZSt24__throw_out_of_range_fmtPKcz@PLT
.L130:
endbr64
movq %rax, %rbx
leaq 352(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L123:
leaq 128(%rsp), %rdi
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev
leaq 160(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 872(%rsp), %rax
subq %fs:40, %rax
je .L124
call __stack_chk_fail@PLT
.L147:
call __stack_chk_fail@PLT
.L152:
movl %eax, %edi
leaq .LC10(%rip), %rsi
call _Z8cudasafe9cudaErrorPc
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 64(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
leaq .LC11(%rip), %rsi
call _Z8cudasafe9cudaErrorPc
movslq %r13d, %rbx
salq $2, %rbx
leaq 72(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq 16(%rsp), %rsi
movq 72(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rdi
movl $160, %esi
call cudaMalloc@PLT
movl $0, %ebx
leaq 192(%rsp), %rbp
jmp .L118
.L149:
addq $32, %rbx
cmpq $160, %rbx
je .L148
.L118:
leaq 0(%rbp,%rbx), %rsi
movq %rbx, %rdi
addq 48(%rsp), %rdi
movl $1, %ecx
movl $32, %edx
call cudaMemcpy@PLT
jmp .L149
.L148:
leaq 56(%rsp), %rdi
movl $32, %esi
call cudaMalloc@PLT
movl $32, %edx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
call cudaDeviceSynchronize@PLT
movl $1024, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $55, 112(%rsp)
movl $1, 116(%rsp)
movl $1, 120(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 84(%rsp), %rdx
movl $1, %ecx
movq 112(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L119
movq 56(%rsp), %rcx
movq 72(%rsp), %rdx
movq 48(%rsp), %rsi
movq 64(%rsp), %rdi
call _Z37__device_stub__Z11sha256_wrapPhS_PiS_PhS_PiS_
.L119:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $32, %edx
movq 56(%rsp), %rsi
movq (%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
cmpb $0, (%rbx)
je .L120
movq %rbx, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L120:
movq (%rsp), %rbx
movq %rbx, %rdi
call strlen@PLT
movq %rax, %rdx
movl $32, %ecx
movl $0, %esi
movq %rbx, %rdi
call __memset_chk@PLT
call cudaDeviceReset@PLT
addl $1, 8(%rsp)
movl 8(%rsp), %eax
addl $56320, 24(%rsp)
movl 12(%rsp), %ecx
cmpl %ecx, %eax
jg .L112
.L121:
movl 12(%rsp), %ecx
cmpl %ecx, 8(%rsp)
je .L150
.L113:
testl %r13d, %r13d
jle .L114
movslq 24(%rsp), %rbx
movq 16(%rsp), %rcx
movq %rcx, %rbp
movslq %r13d, %rax
leaq (%rcx,%rax,4), %r15
movl 40(%rsp), %r12d
movl %r13d, 28(%rsp)
.L117:
movq 128(%rsp), %rax
movq 136(%rsp), %rdx
subq %rax, %rdx
sarq $5, %rdx
cmpq %rdx, %rbx
jnb .L151
movq %rbx, %rdx
salq $5, %rdx
addq %rdx, %rax
movq 8(%rax), %r13
movl %r13d, 0(%rbp)
movslq %r12d, %rdi
movl $1802240, %edx
cmpq %rdx, %rdi
cmovnb %rdi, %rdx
subq %rdi, %rdx
movq (%rax), %rsi
addq %r14, %rdi
call __strcpy_chk@PLT
addl %r13d, %r12d
addq $1, %rbx
addq $4, %rbp
cmpq %r15, %rbp
jne .L117
movl 28(%rsp), %r13d
.L114:
movl %r13d, %ebx
sall $5, %ebx
movslq %ebx, %rbx
movq %rbx, %rsi
movq 32(%rsp), %rdi
call cudaMalloc@PLT
jmp .L152
.L112:
leaq 112(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 112(%rsp), %rax
subq 96(%rsp), %rax
imulq $1000000, %rax, %rax
addq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC13(%rip), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
.LEHE5:
jmp .L105
.L142:
movl $1, 40(%rsp)
.L105:
leaq 352(%rsp), %rdi
call _ZNSt14basic_ifstreamIcSt11char_traitsIcEED1Ev@PLT
.L101:
leaq 128(%rsp), %rdi
call _ZNSt6vectorINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEESaIS5_EED1Ev
leaq 160(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 872(%rsp), %rax
subq %fs:40, %rax
jne .L153
movl 40(%rsp), %eax
addq $888, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L141:
.cfi_restore_state
movl $1, 40(%rsp)
jmp .L101
.L129:
endbr64
movq %rax, %rbx
jmp .L123
.L124:
movq %rbx, %rdi
.LEHB6:
call _Unwind_Resume@PLT
.LEHE6:
.L153:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4183:
.section .gcc_except_table,"a",@progbits
.LLSDA4183:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4183-.LLSDACSB4183
.LLSDACSB4183:
.uleb128 .LEHB4-.LFB4183
.uleb128 .LEHE4-.LEHB4
.uleb128 .L129-.LFB4183
.uleb128 0
.uleb128 .LEHB5-.LFB4183
.uleb128 .LEHE5-.LEHB5
.uleb128 .L130-.LFB4183
.uleb128 0
.uleb128 .LEHB6-.LFB4183
.uleb128 .LEHE6-.LEHB6
.uleb128 0
.uleb128 0
.LLSDACSE4183:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL1k
.comm _ZL1k,256,32
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC13:
.long 0
.long 1083129856
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <fstream>
#include <iostream>
#include <string.h>
#include <vector>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
#include <time.h>
#include <cuda.h>
//#include "sha256.h"
#define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word
//define for sha256
#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))
#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))
#define GPUerrchk(ans) { GPUassert((ans), __FILE__, __LINE__); }
//#define numThread 1024*22
typedef struct {
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;
__constant__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};
//__constant__ uchar answer[32];
//==============cuda kernel=====================================
__device__ void sha256_transform(SHA256_CTX *ctx, uchar *data){
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha256(SHA256_CTX *ctx, uchar *data, uchar *hash, int len){
//init sha256 data structure
ctx->datalen = 0;
ctx->bitlen[0] = 0;
ctx->bitlen[1] = 0;
ctx->state[0] = 0x6a09e667;
ctx->state[1] = 0xbb67ae85;
ctx->state[2] = 0x3c6ef372;
ctx->state[3] = 0xa54ff53a;
ctx->state[4] = 0x510e527f;
ctx->state[5] = 0x9b05688c;
ctx->state[6] = 0x1f83d9ab;
ctx->state[7] = 0x5be0cd19;
//update
uint i;
//uint len = 5; //need to fix!!
for (i=0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha256_transform(ctx,ctx->data);
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],512);
ctx->datalen = 0;
}
}
//final
i = ctx->datalen;
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha256_transform(ctx,ctx->data);
memset(ctx->data,0,56);
}
//par here
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],ctx->datalen * 8);
ctx->data[63] = ctx->bitlen[0];
ctx->data[62] = ctx->bitlen[0] >> 8;
ctx->data[61] = ctx->bitlen[0] >> 16;
ctx->data[60] = ctx->bitlen[0] >> 24;
ctx->data[59] = ctx->bitlen[1];
ctx->data[58] = ctx->bitlen[1] >> 8;
ctx->data[57] = ctx->bitlen[1] >> 16;
ctx->data[56] = ctx->bitlen[1] >> 24;
sha256_transform(ctx,ctx->data);
//we can paralized at here
for (i=0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24-i*8)) & 0x000000ff;
hash[i+4] = (ctx->state[1] >> (24-i*8)) & 0x000000ff;
hash[i+8] = (ctx->state[2] >> (24-i*8)) & 0x000000ff;
hash[i+12] = (ctx->state[3] >> (24-i*8)) & 0x000000ff;
hash[i+16] = (ctx->state[4] >> (24-i*8)) & 0x000000ff;
hash[i+20] = (ctx->state[5] >> (24-i*8)) & 0x000000ff;
hash[i+24] = (ctx->state[6] >> (24-i*8)) & 0x000000ff;
hash[i+28] = (ctx->state[7] >> (24-i*8)) & 0x000000ff;
}
}
__device__ void sha256_hash(SHA256_CTX *ctx, uchar *data, uchar *hash, int len, int round){
sha256(ctx, data, hash, len);
while(round > 1){
sha256(ctx, hash, hash, 32);
round --;
}
}
__device__ int my_strcmp(uchar *str_a, uchar *str_b, uint len){
for(int i=0; i<len; i++){
if(str_a[i] != str_b[i])
return false;
}
return true;
}
__global__ void sha256_wrap(uchar *pwarray, uchar *target, int* pwcount, uchar *result){
int idx = threadIdx.x + blockDim.x * blockIdx.x;
uchar* data = (uchar*)malloc(pwcount[idx]*sizeof(uchar));
SHA256_CTX ctx;// = new SHA256_CTX;
uchar hash[32];
int round = 10000, count = 0;
for(int i=0; i<idx; i++){
count += pwcount[i];
}
memcpy(data,&pwarray[count],pwcount[idx]*sizeof(uchar));
sha256_hash(&ctx,data,hash,pwcount[idx],round);
for (int i=0; i<5;i++){
if(my_strcmp(hash,&target[32*i],32))
memcpy(result,data,pwcount[idx]*sizeof(uchar));
}
}
//====================================================================
void print_hash(unsigned char hash[]){
int idx;
for (idx=0; idx < 32; idx++)
printf("%02x",hash[idx]);
printf("\n");
}
void read_hash(char filename[],unsigned char target[5][32]){
FILE *rhash = fopen(filename,"r+");
fread(target[0],1,32,rhash);
fread(target[1],1,32,rhash);
fread(target[2],1,32,rhash);
fread(target[3],1,32,rhash);
fread(target[4],1,32,rhash);
fclose(rhash);
}
void cudasafe(cudaError_t error, char* message){
if(error!=cudaSuccess) { fprintf(stderr,"ERROR: %s : %i\n",message,error); exit(-1);}
}
//============================================================================
int main(int argc, char **argv){
std::string password;
std::vector<std::string> pwarray;
int tot_dict_size = 0;
int dict_size = 55*1024;
int numThread = 55*1024;
uchar target[5][32];
uchar *result = new uchar[32];
//variable for GPU
// uchar *dev_result;
uchar *dev_target;
// uchar *dev_password;
// int *dev_pwcount;
if(argc < 2){
std::cerr << "need load dictionary!! \n";
return 1;
}
//timing program
struct timeval starttime, endtime;
double runTime = 0.0;
gettimeofday(&starttime,NULL);
//read target hash
read_hash(argv[2],target);
//copy hash into cuda (maybe into constant memory?)
// cudaMalloc((void**)&dev_target,32*5*sizeof(uchar));
// for(int i=0;i<5;i++){
// cudaMemcpy((void*)&dev_target[32*i],target[i],32*sizeof(uchar),cudaMemcpyHostToDevice);
// }
//read from dictionary
std::ifstream dict(argv[1]);
if(!dict){
std::cerr << "No such file!! \n";
return 1;
}
while(std::getline(dict, password)){
pwarray.push_back(password);
tot_dict_size++;
}
uchar *pwstring = (uchar*)malloc(dict_size*32*sizeof(uchar));
int *pw_count = (int*)malloc(dict_size*sizeof(int));
//============================================================
for(int lp = 0; lp < tot_dict_size/numThread + 1; lp++){
//devpassword
//variable for GPU
uchar *dev_result;
uchar *dev_password;
int *dev_pwcount;
if(lp == tot_dict_size/numThread && tot_dict_size%numThread != 0){
dict_size = tot_dict_size % numThread;
}
//int *pw_count = (int*)malloc(dict_size*sizeof(int));
int temp_count = 0;
//uchar *pwstring = (uchar*)malloc(dict_size*32*sizeof(uchar));
for(int i=0; i<dict_size; i++){
pw_count[i] = pwarray.at(i+lp*numThread).length();
strcpy((char*)&pwstring[temp_count],pwarray.at(i+lp*numThread).c_str());
temp_count += pw_count[i];
}
cudasafe( cudaMalloc((void**)&dev_password,32*dict_size*sizeof(uchar)), "cudaMalloc");
cudasafe( cudaMemcpy((void*)dev_password,pwstring,32*dict_size*sizeof(uchar),cudaMemcpyHostToDevice), "cudaMemcpy");
cudaMalloc((void**)&dev_pwcount,dict_size*sizeof(int));
cudaMemcpy((void*)dev_pwcount,pw_count,dict_size*sizeof(int),cudaMemcpyHostToDevice);
cudaMalloc((void**)&dev_target,32*5*sizeof(uchar));
for(int i=0;i<5;i++){
cudaMemcpy((void*)&dev_target[32*i],target[i],32*sizeof(uchar),cudaMemcpyHostToDevice);
}
cudaMalloc((void**)&dev_result,32*sizeof(uchar));
cudaMemset(dev_result,0,32*sizeof(uchar));
cudaDeviceSynchronize();
dim3 DimBlock(1024,1);
dim3 DimGrid(55,1);
sha256_wrap <<< DimGrid, DimBlock >>> (dev_password, dev_target, dev_pwcount, dev_result);
cudaDeviceSynchronize();
cudaMemcpy(result,dev_result,32*sizeof(uchar),cudaMemcpyDeviceToHost);
if(strlen((const char*)result)!= 0)
printf("password: %s \n", result);
memset(result, 0, strlen((const char*)result));
cudaDeviceReset();
// cudaFree(dev_result); cudaFree(dev_password); cudaFree(dev_pwcount);
}
gettimeofday(&endtime,NULL);
runTime=1000000*(endtime.tv_sec-starttime.tv_sec)+endtime.tv_usec-starttime.tv_usec;
runTime=runTime/1000;
printf("timing: %f ms \n",runTime);
cudaFree(dev_target);
return 0;
} | #include <stdio.h>
#include <fstream>
#include <iostream>
#include <string.h>
#include <vector>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
//#include "sha256.h"
#define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word
//define for sha256
#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))
#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))
#define GPUerrchk(ans) { GPUassert((ans), __FILE__, __LINE__); }
//#define numThread 1024*22
typedef struct {
uchar data[64];
uint datalen;
uint bitlen[2];
uint state[8];
} SHA256_CTX;
__constant__ uint k[64] = {
0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};
//__constant__ uchar answer[32];
//==============cuda kernel=====================================
__device__ void sha256_transform(SHA256_CTX *ctx, uchar *data){
uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
for (i=0,j=0; i < 16; ++i, j += 4)
m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
for ( ; i < 64; ++i)
m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];
a = ctx->state[0];
b = ctx->state[1];
c = ctx->state[2];
d = ctx->state[3];
e = ctx->state[4];
f = ctx->state[5];
g = ctx->state[6];
h = ctx->state[7];
for (i = 0; i < 64; ++i) {
t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
t2 = EP0(a) + MAJ(a,b,c);
h = g;
g = f;
f = e;
e = d + t1;
d = c;
c = b;
b = a;
a = t1 + t2;
}
ctx->state[0] += a;
ctx->state[1] += b;
ctx->state[2] += c;
ctx->state[3] += d;
ctx->state[4] += e;
ctx->state[5] += f;
ctx->state[6] += g;
ctx->state[7] += h;
}
__device__ void sha256(SHA256_CTX *ctx, uchar *data, uchar *hash, int len){
//init sha256 data structure
ctx->datalen = 0;
ctx->bitlen[0] = 0;
ctx->bitlen[1] = 0;
ctx->state[0] = 0x6a09e667;
ctx->state[1] = 0xbb67ae85;
ctx->state[2] = 0x3c6ef372;
ctx->state[3] = 0xa54ff53a;
ctx->state[4] = 0x510e527f;
ctx->state[5] = 0x9b05688c;
ctx->state[6] = 0x1f83d9ab;
ctx->state[7] = 0x5be0cd19;
//update
uint i;
//uint len = 5; //need to fix!!
for (i=0; i < len; ++i) {
ctx->data[ctx->datalen] = data[i];
ctx->datalen++;
if (ctx->datalen == 64) {
sha256_transform(ctx,ctx->data);
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],512);
ctx->datalen = 0;
}
}
//final
i = ctx->datalen;
if (ctx->datalen < 56) {
ctx->data[i++] = 0x80;
while (i < 56)
ctx->data[i++] = 0x00;
}
else {
ctx->data[i++] = 0x80;
while (i < 64)
ctx->data[i++] = 0x00;
sha256_transform(ctx,ctx->data);
memset(ctx->data,0,56);
}
//par here
DBL_INT_ADD(ctx->bitlen[0],ctx->bitlen[1],ctx->datalen * 8);
ctx->data[63] = ctx->bitlen[0];
ctx->data[62] = ctx->bitlen[0] >> 8;
ctx->data[61] = ctx->bitlen[0] >> 16;
ctx->data[60] = ctx->bitlen[0] >> 24;
ctx->data[59] = ctx->bitlen[1];
ctx->data[58] = ctx->bitlen[1] >> 8;
ctx->data[57] = ctx->bitlen[1] >> 16;
ctx->data[56] = ctx->bitlen[1] >> 24;
sha256_transform(ctx,ctx->data);
//we can paralized at here
for (i=0; i < 4; ++i) {
hash[i] = (ctx->state[0] >> (24-i*8)) & 0x000000ff;
hash[i+4] = (ctx->state[1] >> (24-i*8)) & 0x000000ff;
hash[i+8] = (ctx->state[2] >> (24-i*8)) & 0x000000ff;
hash[i+12] = (ctx->state[3] >> (24-i*8)) & 0x000000ff;
hash[i+16] = (ctx->state[4] >> (24-i*8)) & 0x000000ff;
hash[i+20] = (ctx->state[5] >> (24-i*8)) & 0x000000ff;
hash[i+24] = (ctx->state[6] >> (24-i*8)) & 0x000000ff;
hash[i+28] = (ctx->state[7] >> (24-i*8)) & 0x000000ff;
}
}
__device__ void sha256_hash(SHA256_CTX *ctx, uchar *data, uchar *hash, int len, int round){
sha256(ctx, data, hash, len);
while(round > 1){
sha256(ctx, hash, hash, 32);
round --;
}
}
__device__ int my_strcmp(uchar *str_a, uchar *str_b, uint len){
for(int i=0; i<len; i++){
if(str_a[i] != str_b[i])
return false;
}
return true;
}
__global__ void sha256_wrap(uchar *pwarray, uchar *target, int* pwcount, uchar *result){
int idx = threadIdx.x + blockDim.x * blockIdx.x;
uchar* data = (uchar*)malloc(pwcount[idx]*sizeof(uchar));
SHA256_CTX ctx;// = new SHA256_CTX;
uchar hash[32];
int round = 10000, count = 0;
for(int i=0; i<idx; i++){
count += pwcount[i];
}
memcpy(data,&pwarray[count],pwcount[idx]*sizeof(uchar));
sha256_hash(&ctx,data,hash,pwcount[idx],round);
for (int i=0; i<5;i++){
if(my_strcmp(hash,&target[32*i],32))
memcpy(result,data,pwcount[idx]*sizeof(uchar));
}
}
//====================================================================
void print_hash(unsigned char hash[]){
int idx;
for (idx=0; idx < 32; idx++)
printf("%02x",hash[idx]);
printf("\n");
}
void read_hash(char filename[],unsigned char target[5][32]){
FILE *rhash = fopen(filename,"r+");
fread(target[0],1,32,rhash);
fread(target[1],1,32,rhash);
fread(target[2],1,32,rhash);
fread(target[3],1,32,rhash);
fread(target[4],1,32,rhash);
fclose(rhash);
}
void cudasafe(hipError_t error, char* message){
if(error!=hipSuccess) { fprintf(stderr,"ERROR: %s : %i\n",message,error); exit(-1);}
}
//============================================================================
int main(int argc, char **argv){
std::string password;
std::vector<std::string> pwarray;
int tot_dict_size = 0;
int dict_size = 55*1024;
int numThread = 55*1024;
uchar target[5][32];
uchar *result = new uchar[32];
//variable for GPU
// uchar *dev_result;
uchar *dev_target;
// uchar *dev_password;
// int *dev_pwcount;
if(argc < 2){
std::cerr << "need load dictionary!! \n";
return 1;
}
//timing program
struct timeval starttime, endtime;
double runTime = 0.0;
gettimeofday(&starttime,NULL);
//read target hash
read_hash(argv[2],target);
//copy hash into cuda (maybe into constant memory?)
// cudaMalloc((void**)&dev_target,32*5*sizeof(uchar));
// for(int i=0;i<5;i++){
// cudaMemcpy((void*)&dev_target[32*i],target[i],32*sizeof(uchar),cudaMemcpyHostToDevice);
// }
//read from dictionary
std::ifstream dict(argv[1]);
if(!dict){
std::cerr << "No such file!! \n";
return 1;
}
while(std::getline(dict, password)){
pwarray.push_back(password);
tot_dict_size++;
}
uchar *pwstring = (uchar*)malloc(dict_size*32*sizeof(uchar));
int *pw_count = (int*)malloc(dict_size*sizeof(int));
//============================================================
for(int lp = 0; lp < tot_dict_size/numThread + 1; lp++){
//devpassword
//variable for GPU
uchar *dev_result;
uchar *dev_password;
int *dev_pwcount;
if(lp == tot_dict_size/numThread && tot_dict_size%numThread != 0){
dict_size = tot_dict_size % numThread;
}
//int *pw_count = (int*)malloc(dict_size*sizeof(int));
int temp_count = 0;
//uchar *pwstring = (uchar*)malloc(dict_size*32*sizeof(uchar));
for(int i=0; i<dict_size; i++){
pw_count[i] = pwarray.at(i+lp*numThread).length();
strcpy((char*)&pwstring[temp_count],pwarray.at(i+lp*numThread).c_str());
temp_count += pw_count[i];
}
cudasafe( hipMalloc((void**)&dev_password,32*dict_size*sizeof(uchar)), "hipMalloc");
cudasafe( hipMemcpy((void*)dev_password,pwstring,32*dict_size*sizeof(uchar),hipMemcpyHostToDevice), "hipMemcpy");
hipMalloc((void**)&dev_pwcount,dict_size*sizeof(int));
hipMemcpy((void*)dev_pwcount,pw_count,dict_size*sizeof(int),hipMemcpyHostToDevice);
hipMalloc((void**)&dev_target,32*5*sizeof(uchar));
for(int i=0;i<5;i++){
hipMemcpy((void*)&dev_target[32*i],target[i],32*sizeof(uchar),hipMemcpyHostToDevice);
}
hipMalloc((void**)&dev_result,32*sizeof(uchar));
hipMemset(dev_result,0,32*sizeof(uchar));
hipDeviceSynchronize();
dim3 DimBlock(1024,1);
dim3 DimGrid(55,1);
sha256_wrap <<< DimGrid, DimBlock >>> (dev_password, dev_target, dev_pwcount, dev_result);
hipDeviceSynchronize();
hipMemcpy(result,dev_result,32*sizeof(uchar),hipMemcpyDeviceToHost);
if(strlen((const char*)result)!= 0)
printf("password: %s \n", result);
memset(result, 0, strlen((const char*)result));
hipDeviceReset();
// cudaFree(dev_result); cudaFree(dev_password); cudaFree(dev_pwcount);
}
gettimeofday(&endtime,NULL);
runTime=1000000*(endtime.tv_sec-starttime.tv_sec)+endtime.tv_usec-starttime.tv_usec;
runTime=runTime/1000;
printf("timing: %f ms \n",runTime);
hipFree(dev_target);
return 0;
} |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ int position; //index of the largest value
__device__ int largest; //value of the largest value
int lenString = 593;
int maxNumStrings = 1000000;
int threshold = 2;
__device__ void cuda_select(int *db, int size) {
int my_id = blockDim.x * blockIdx.x + threadIdx.x;
if(my_id < size) {
if(db[2 * my_id] > db[2 * my_id + 1])
db[my_id] = db[2 * my_id];
else
db[my_id] = db[2 * my_id + 1];
}
}
__global__ void select(int *db, int size) {
int height = (int)ceil(log2((double)size));
int i = 0;
for(i = 0; i < height; i++) {
size = (int)ceil((double) size/2);
cuda_select(db, size);
}
largest = db[0];
} | code for sm_80
Function : _Z6selectPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.F64 R4, c[0x0][0x168] ; /* 0x00005a0000047b12 */
/* 0x000e220000201c00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, -0x3ff ; /* 0xfffffc01ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.GT.AND P0, PT, R5, 0xfffff, PT ; /* 0x000fffff0500780c */
/* 0x001fe20003f04270 */
/*0040*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, R5.reuse ; /* 0x000000ffff077224 */
/* 0x100fe400078e0005 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fd000078e0005 */
/*0070*/ @!P0 DMUL R6, R6, 1.80143985094819840000e+16 ; /* 0x4350000006068828 */
/* 0x000e220000000000 */
/*0080*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, -0x435 ; /* 0xfffffbcbff028424 */
/* 0x000fd200078e00ff */
/*0090*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff038224 */
/* 0x001fe400078e0007 */
/*00a0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff048224 */
/* 0x000fc600078e0006 */
/*00b0*/ IADD3 R0, R3, -0x1, RZ ; /* 0xffffffff03007810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R0, 0x7fefffff, PT ; /* 0x7fefffff0000780c */
/* 0x000fe20003f26070 */
/*00d0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fd800078e00ff */
/*00e0*/ @!P1 BRA 0x160 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe200078e00ff */
/*0100*/ FSETP.NEU.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fe20003f0d000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff037424 */
/* 0x000fcc00078e00ff */
/*0120*/ DFMA R2, R6, R2, +INF ; /* 0x7ff000000602742b */
/* 0x000e140000000002 */
/*0130*/ FSEL R4, R2, RZ, P0 ; /* 0x000000ff02047208 */
/* 0x001fe40000000000 */
/*0140*/ FSEL R5, R3, -QNAN , P0 ; /* 0xfff0000003057808 */
/* 0x000fe20000000000 */
/*0150*/ BRA 0x3f0 ; /* 0x0000029000007947 */
/* 0x000fea0003800000 */
/*0160*/ LOP3.LUT R5, R3.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff03057812 */
/* 0x040fe200078ec0ff */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0180*/ LEA.HI R2, R3, R2, RZ, 0xc ; /* 0x0000000203027211 */
/* 0x000fe200078f60ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, 0x3ae80f1e ; /* 0x3ae80f1eff0e7424 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R5, R5, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000005057812 */
/* 0x000fe200078efcff */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3eb1380b ; /* 0x3eb1380bff0f7424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x43300000 ; /* 0x43300000ff037424 */
/* 0x000fe200078e00ff */
/*01d0*/ ISETP.GE.AND P0, PT, R5, 0x3ff6a09f, PT ; /* 0x3ff6a09f0500780c */
/* 0x000fda0003f06270 */
/*01e0*/ @P0 IADD3 R7, R5, -0x100000, RZ ; /* 0xfff0000005070810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc60007ffe0ff */
/*0200*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0007 */
/*0210*/ LOP3.LUT R2, R2, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000002027812 */
/* 0x000fca00078e3cff */
/*0220*/ DADD R12, R4, 1 ; /* 0x3ff00000040c7429 */
/* 0x000e080000000000 */
/*0230*/ DADD R4, R4, -1 ; /* 0xbff0000004047429 */
/* 0x000fe40000000000 */
/*0240*/ MUFU.RCP64H R7, R13 ; /* 0x0000000d00077308 */
/* 0x001e240000001800 */
/*0250*/ DADD R2, R2, c[0x2][0x38] ; /* 0x00800e0002027629 */
/* 0x000fc80000000000 */
/*0260*/ DFMA R8, -R12, R6, 1 ; /* 0x3ff000000c08742b */
/* 0x001e0c0000000106 */
/*0270*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0280*/ DFMA R6, R6, R8, R6 ; /* 0x000000080606722b */
/* 0x001e0c0000000006 */
/*0290*/ DMUL R8, R6, R4 ; /* 0x0000000406087228 */
/* 0x001e0c0000000000 */
/*02a0*/ DFMA R8, R6, R4, R8 ; /* 0x000000040608722b */
/* 0x001e0c0000000008 */
/*02b0*/ DMUL R10, R8, R8 ; /* 0x00000008080a7228 */
/* 0x001e080000000000 */
/*02c0*/ DADD R12, R4, -R8 ; /* 0x00000000040c7229 */
/* 0x000e480000000808 */
/*02d0*/ DFMA R14, R10, R14, c[0x2][0x0] ; /* 0x008000000a0e762b */
/* 0x001e08000000000e */
/*02e0*/ DADD R16, R12, R12 ; /* 0x000000000c107229 */
/* 0x002fc8000000000c */
/*02f0*/ DFMA R14, R10, R14, c[0x2][0x8] ; /* 0x008002000a0e762b */
/* 0x001e08000000000e */
/*0300*/ DFMA R12, R2, c[0x2][0x40], R8 ; /* 0x00801000020c7a2b */
/* 0x000fc80000000008 */
/*0310*/ DFMA R14, R10, R14, c[0x2][0x10] ; /* 0x008004000a0e762b */
/* 0x001e08000000000e */
/*0320*/ DFMA R16, R4, -R8, R16 ; /* 0x800000080410722b */
/* 0x000fc80000000010 */
/*0330*/ DFMA R14, R10, R14, c[0x2][0x18] ; /* 0x008006000a0e762b */
/* 0x001e08000000000e */
/*0340*/ DFMA R4, -R2, c[0x2][0x40], R12 ; /* 0x0080100002047a2b */
/* 0x000fc8000000010c */
/*0350*/ DFMA R14, R10, R14, c[0x2][0x20] ; /* 0x008008000a0e762b */
/* 0x001e08000000000e */
/*0360*/ DMUL R16, R6, R16 ; /* 0x0000001006107228 */
/* 0x000fc80000000000 */
/*0370*/ DFMA R14, R10, R14, c[0x2][0x28] ; /* 0x00800a000a0e762b */
/* 0x001e08000000000e */
/*0380*/ DADD R4, -R8, R4 ; /* 0x0000000008047229 */
/* 0x000fc80000000104 */
/*0390*/ DFMA R14, R10, R14, c[0x2][0x30] ; /* 0x00800c000a0e762b */
/* 0x001e0c000000000e */
/*03a0*/ DMUL R14, R10, R14 ; /* 0x0000000e0a0e7228 */
/* 0x001e0c0000000000 */
/*03b0*/ DFMA R14, R8, R14, R16 ; /* 0x0000000e080e722b */
/* 0x001e0c0000000010 */
/*03c0*/ DADD R4, R14, -R4 ; /* 0x000000000e047229 */
/* 0x001e0c0000000804 */
/*03d0*/ DFMA R4, R2, c[0x2][0x48], R4 ; /* 0x0080120002047a2b */
/* 0x001e0c0000000004 */
/*03e0*/ DADD R4, R12, R4 ; /* 0x000000000c047229 */
/* 0x00104c0000000004 */
/*03f0*/ DMUL R2, R4, c[0x2][0x50] ; /* 0x0080140004027a28 */
/* 0x002e620000000000 */
/*0400*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0410*/ DFMA R2, R4, c[0x2][0x58], R2 ; /* 0x0080160004027a2b */
/* 0x002e4c0000000002 */
/*0420*/ F2I.F64.CEIL R9, R2 ; /* 0x0000000200097311 */
/* 0x002e640000309100 */
/*0430*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x002fda0003f06270 */
/*0440*/ @!P0 BRA 0x960 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*0450*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0460*/ IADD3 R4, R9.reuse, -0x1, RZ ; /* 0xffffffff09047810 */
/* 0x040fe20007ffe0ff */
/*0470*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0480*/ LOP3.LUT R6, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309067812 */
/* 0x000fe200078ec0ff */
/*0490*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*04a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*04b0*/ IMAD R7, R7, c[0x0][0x0], R2 ; /* 0x0000000007077a24 */
/* 0x002fc800078e0202 */
/*04c0*/ IMAD.SHL.U32 R2, R7, 0x2, RZ ; /* 0x0000000207027824 */
/* 0x000fe400078e00ff */
/*04d0*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a07 */
/*04e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*04f0*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fe200078e0202 */
/*0500*/ @!P0 BRA 0x850 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*0510*/ IMAD.IADD R8, R9, 0x1, -R6 ; /* 0x0000000109087824 */
/* 0x000fc800078e0a06 */
/*0520*/ I2F.F64 R10, R0 ; /* 0x00000000000a7312 */
/* 0x001e620000201c00 */
/*0530*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ BSSY B0, 0x6c0 ; /* 0x0000017000007945 */
/* 0x000fe60003800000 */
/*0550*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0560*/ DMUL R10, R10, 0.5 ; /* 0x3fe000000a0a7828 */
/* 0x002e540000000000 */
/*0570*/ F2I.F64.CEIL R10, R10 ; /* 0x0000000a000a7311 */
/* 0x002e700000309100 */
/*0580*/ I2F.F64 R12, R10 ; /* 0x0000000a000c7312 */
/* 0x003e220000201c00 */
/*0590*/ ISETP.GE.AND P4, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x000fe20003f86270 */
/*05a0*/ DMUL R12, R12, 0.5 ; /* 0x3fe000000c0c7828 */
/* 0x001e140000000000 */
/*05b0*/ F2I.F64.CEIL R12, R12 ; /* 0x0000000c000c7311 */
/* 0x001e300000309100 */
/*05c0*/ I2F.F64 R14, R12 ; /* 0x0000000c000e7312 */
/* 0x001e220000201c00 */
/*05d0*/ ISETP.GE.AND P0, PT, R7, R12, PT ; /* 0x0000000c0700720c */
/* 0x000fe20003f06270 */
/*05e0*/ DMUL R14, R14, 0.5 ; /* 0x3fe000000e0e7828 */
/* 0x001e140000000000 */
/*05f0*/ F2I.F64.CEIL R14, R14 ; /* 0x0000000e000e7311 */
/* 0x001e300000309100 */
/*0600*/ I2F.F64 R16, R14 ; /* 0x0000000e00107312 */
/* 0x001e220000201c00 */
/*0610*/ ISETP.GE.AND P1, PT, R7, R14, PT ; /* 0x0000000e0700720c */
/* 0x000fe20003f26270 */
/*0620*/ DMUL R16, R16, 0.5 ; /* 0x3fe0000010107828 */
/* 0x001e0c0000000000 */
/*0630*/ F2I.F64.CEIL R0, R16 ; /* 0x0000001000007311 */
/* 0x001e240000309100 */
/*0640*/ ISETP.GE.AND P3, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x001fe20003f66270 */
/*0650*/ @P4 BRA 0x6b0 ; /* 0x0000005000004947 */
/* 0x000fee0003800000 */
/*0660*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea4000c1e1900 */
/*0680*/ ISETP.GT.AND P4, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x004fda0003f84270 */
/*0690*/ @!P4 STG.E [R4.64], R10 ; /* 0x0000000a0400c986 */
/* 0x0001e8000c101904 */
/*06a0*/ @P4 STG.E [R4.64], R9 ; /* 0x0000000904004986 */
/* 0x0001e4000c101904 */
/*06b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06c0*/ BSSY B0, 0x740 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*06d0*/ @P0 BRA 0x730 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*06e0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea8000c1e1900 */
/*06f0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea4000c1e1900 */
/*0700*/ ISETP.GT.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x004fda0003f04270 */
/*0710*/ @!P0 STG.E [R4.64], R10 ; /* 0x0000000a04008986 */
/* 0x0001e8000c101904 */
/*0720*/ @P0 STG.E [R4.64], R9 ; /* 0x0000000904000986 */
/* 0x0001e4000c101904 */
/*0730*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0740*/ BSSY B0, 0x7c0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0750*/ @P1 BRA 0x7b0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea8000c1e1900 */
/*0770*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea4000c1e1900 */
/*0780*/ ISETP.GT.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x004fda0003f04270 */
/*0790*/ @!P0 STG.E [R4.64], R10 ; /* 0x0000000a04008986 */
/* 0x0001e8000c101904 */
/*07a0*/ @P0 STG.E [R4.64], R9 ; /* 0x0000000904000986 */
/* 0x0001e4000c101904 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ BSSY B0, 0x840 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*07d0*/ @P3 BRA 0x830 ; /* 0x0000005000003947 */
/* 0x000fea0003800000 */
/*07e0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea8000c1e1900 */
/*07f0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea4000c1e1900 */
/*0800*/ ISETP.GT.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x004fda0003f04270 */
/*0810*/ @!P0 STG.E [R4.64], R10 ; /* 0x0000000a04008986 */
/* 0x0001e8000c101904 */
/*0820*/ @P0 STG.E [R4.64], R9 ; /* 0x0000000904000986 */
/* 0x0001e4000c101904 */
/*0830*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0840*/ @P2 BRA 0x520 ; /* 0xfffffcd000002947 */
/* 0x000fea000383ffff */
/*0850*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0860*/ @!P0 BRA 0x960 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0870*/ I2F.F64 R8, R0 ; /* 0x0000000000087312 */
/* 0x001e220000201c00 */
/*0880*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*0890*/ BSSY B0, 0x950 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*08a0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*08b0*/ DMUL R8, R8, 0.5 ; /* 0x3fe0000008087828 */
/* 0x001e0c0000000000 */
/*08c0*/ F2I.F64.CEIL R0, R8 ; /* 0x0000000800007311 */
/* 0x001e240000309100 */
/*08d0*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x001fda0003f06270 */
/*08e0*/ @P0 BRA 0x940 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ea4000c1e1900 */
/*0910*/ ISETP.GT.AND P0, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x004fda0003f04270 */
/*0920*/ @!P0 STG.E [R4.64], R8 ; /* 0x0000000804008986 */
/* 0x0001e8000c101904 */
/*0930*/ @P0 STG.E [R4.64], R9 ; /* 0x0000000904000986 */
/* 0x0001e4000c101904 */
/*0940*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0950*/ @P1 BRA 0x870 ; /* 0xffffff1000001947 */
/* 0x000fea000383ffff */
/*0960*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0970*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fca00078e00ff */
/*0980*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x001fe400078e00ff */
/*09a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fca00078e00ff */
/*09b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*09c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09d0*/ BRA 0x9d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ int position; //index of the largest value
__device__ int largest; //value of the largest value
int lenString = 593;
int maxNumStrings = 1000000;
int threshold = 2;
__device__ void cuda_select(int *db, int size) {
int my_id = blockDim.x * blockIdx.x + threadIdx.x;
if(my_id < size) {
if(db[2 * my_id] > db[2 * my_id + 1])
db[my_id] = db[2 * my_id];
else
db[my_id] = db[2 * my_id + 1];
}
}
__global__ void select(int *db, int size) {
int height = (int)ceil(log2((double)size));
int i = 0;
for(i = 0; i < height; i++) {
size = (int)ceil((double) size/2);
cuda_select(db, size);
}
largest = db[0];
} | .file "tmpxft_001198b1_00000000-6_select.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11cuda_selectPii
.type _Z11cuda_selectPii, @function
_Z11cuda_selectPii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z11cuda_selectPii, .-_Z11cuda_selectPii
.globl _Z26__device_stub__Z6selectPiiPii
.type _Z26__device_stub__Z6selectPiiPii, @function
_Z26__device_stub__Z6selectPiiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6selectPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z26__device_stub__Z6selectPiiPii, .-_Z26__device_stub__Z6selectPiiPii
.globl _Z6selectPii
.type _Z6selectPii, @function
_Z6selectPii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6selectPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6selectPii, .-_Z6selectPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6selectPii"
.LC1:
.string "position"
.LC2:
.string "largest"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6selectPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8position(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7largest(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl threshold
.data
.align 4
.type threshold, @object
.size threshold, 4
threshold:
.long 2
.globl maxNumStrings
.align 4
.type maxNumStrings, @object
.size maxNumStrings, 4
maxNumStrings:
.long 1000000
.globl lenString
.align 4
.type lenString, @object
.size lenString, 4
lenString:
.long 593
.local _ZL7largest
.comm _ZL7largest,4,4
.local _ZL8position
.comm _ZL8position,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ int position; //index of the largest value
__device__ int largest; //value of the largest value
int lenString = 593;
int maxNumStrings = 1000000;
int threshold = 2;
__device__ void cuda_select(int *db, int size) {
int my_id = blockDim.x * blockIdx.x + threadIdx.x;
if(my_id < size) {
if(db[2 * my_id] > db[2 * my_id + 1])
db[my_id] = db[2 * my_id];
else
db[my_id] = db[2 * my_id + 1];
}
}
__global__ void select(int *db, int size) {
int height = (int)ceil(log2((double)size));
int i = 0;
for(i = 0; i < height; i++) {
size = (int)ceil((double) size/2);
cuda_select(db, size);
}
largest = db[0];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int position; //index of the largest value
__device__ int largest; //value of the largest value
int lenString = 593;
int maxNumStrings = 1000000;
int threshold = 2;
__device__ void cuda_select(int *db, int size) {
int my_id = blockDim.x * blockIdx.x + threadIdx.x;
if(my_id < size) {
if(db[2 * my_id] > db[2 * my_id + 1])
db[my_id] = db[2 * my_id];
else
db[my_id] = db[2 * my_id + 1];
}
}
__global__ void select(int *db, int size) {
int height = (int)ceil(log2((double)size));
int i = 0;
for(i = 0; i < height; i++) {
size = (int)ceil((double) size/2);
cuda_select(db, size);
}
largest = db[0];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int position; //index of the largest value
__device__ int largest; //value of the largest value
int lenString = 593;
int maxNumStrings = 1000000;
int threshold = 2;
__device__ void cuda_select(int *db, int size) {
int my_id = blockDim.x * blockIdx.x + threadIdx.x;
if(my_id < size) {
if(db[2 * my_id] > db[2 * my_id + 1])
db[my_id] = db[2 * my_id];
else
db[my_id] = db[2 * my_id + 1];
}
}
__global__ void select(int *db, int size) {
int height = (int)ceil(log2((double)size));
int i = 0;
for(i = 0; i < height; i++) {
size = (int)ceil((double) size/2);
cuda_select(db, size);
}
largest = db[0];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6selectPii
.globl _Z6selectPii
.p2align 8
.type _Z6selectPii,@function
_Z6selectPii:
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s3, 0x3fe55555
s_mov_b32 s2, 0x55555555
s_mov_b32 s7, 0x3fc38538
s_mov_b32 s6, 0x6b47b09a
s_mov_b32 s9, 0x3fc3ab76
s_mov_b32 s8, 0xbf559e2b
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[1:2], s4
s_cmp_gt_i32 s4, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e32 v[3:4], v[1:2]
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[3:4]
s_mov_b32 s2, 0x55555780
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], v5
v_add_f64 v[5:6], v[3:4], 1.0
v_add_f64 v[11:12], v[3:4], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[5:6]
v_add_f64 v[13:14], v[5:6], -1.0
v_add_f64 v[3:4], v[3:4], -v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
v_mul_f64 v[9:10], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[5:6], v[9:10]
v_fma_f64 v[5:6], v[9:10], v[5:6], -v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[9:10], v[3:4], v[5:6]
v_add_f64 v[5:6], v[15:16], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[11:12], -v[5:6]
v_add_f64 v[15:16], v[5:6], -v[15:16]
v_add_f64 v[11:12], v[11:12], -v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[15:16], -v[3:4]
v_add_f64 v[5:6], v[11:12], -v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_f64 v[3:4], v[13:14], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[7:8], v[3:4]
v_add_f64 v[5:6], v[9:10], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[5:6], v[5:6]
v_fma_f64 v[11:12], v[7:8], s[8:9], s[6:7]
s_mov_b32 s7, 0x3fc7474d
s_mov_b32 s6, 0xd7f4df2e
v_mul_f64 v[13:14], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[6:7]
s_mov_b32 s7, 0x3fcc71c0
s_mov_b32 s6, 0x16291751
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[6:7]
s_mov_b32 s7, 0x3fd24924
s_mov_b32 s6, 0x9b27acf1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[6:7]
s_mov_b32 s7, 0x3fd99999
s_mov_b32 s6, 0x998ef7b6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[7:8], v[7:8], v[11:12], s[2:3]
v_ldexp_f64 v[11:12], v[5:6], 1
v_add_f64 v[5:6], v[5:6], -v[9:10]
s_mov_b32 s3, 0x3ff71547
s_mov_b32 s2, 0x652b82fe
v_mul_f64 v[7:8], v[13:14], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[3:4], -v[5:6]
v_add_f64 v[9:10], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[3:4], v[3:4], 1
v_add_f64 v[5:6], v[9:10], -v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[7:8], -v[5:6]
v_add_f64 v[3:4], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[9:10], v[3:4]
v_add_f64 v[7:8], v[5:6], -v[9:10]
v_mul_f64 v[9:10], v[5:6], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[3:4], -v[7:8]
v_fma_f64 v[7:8], v[5:6], s[2:3], -v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[3:4], v[3:4], s[2:3], v[7:8]
v_frexp_exp_i32_f64_e32 v7, v[1:2]
s_mov_b32 s3, 0x3c7777d0
s_mov_b32 s2, 0xffda0d24
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[1:2], v[5:6], s[2:3], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_lg_u32 s4, 0
v_cvt_f64_i32_e32 v[3:4], v3
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[9:10], v[1:2]
v_add_f64 v[7:8], v[5:6], v[3:4]
v_add_f64 v[9:10], v[5:6], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[7:8], -v[3:4]
v_add_f64 v[1:2], v[1:2], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[11:12], -v[7:8]
v_add_f64 v[5:6], v[5:6], -v[11:12]
v_add_f64 v[3:4], v[13:14], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[5:6], v[3:4]
v_add_f64 v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[7:8], v[1:2]
v_cndmask_b32_e32 v2, 0x7ff80000, v2, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0xfff00000, v2, s2
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ceil_f64_e32 v[1:2], v[1:2]
v_cvt_i32_f64_e32 v8, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 1, v8
s_cbranch_vccnz .LBB0_8
s_load_b32 s0, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_dual_mov_b32 v0, s4 :: v_dual_lshlrev_b32 v3, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v5, 1, v3
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[9:10], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[11:12], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v9
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v8, -1, v8
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_cbranch_vccz .LBB0_8
.LBB0_3:
v_cvt_f64_i32_e32 v[9:10], v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[9:10], 0.5
v_ceil_f64_e32 v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v0, v[9:10]
v_cmpx_lt_i32_e64 v1, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v9, v[4:5], off
global_load_b32 v10, v[6:7], off
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_le_i32_e64 v9, v10
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_6
global_store_b32 v[2:3], v10, off
.LBB0_6:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_2
global_store_b32 v[2:3], v9, off
s_branch .LBB0_2
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v0, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, largest@rel32@lo+4
s_addc_u32 s1, s1, largest@rel32@hi+12
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6selectPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6selectPii, .Lfunc_end0-_Z6selectPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected position
.type position,@object
.section .bss,"aw",@nobits
.globl position
.p2align 2, 0x0
position:
.long 0
.size position, 4
.protected largest
.type largest,@object
.globl largest
.p2align 2, 0x0
largest:
.long 0
.size largest, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym largest
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6selectPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6selectPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ int position; //index of the largest value
__device__ int largest; //value of the largest value
int lenString = 593;
int maxNumStrings = 1000000;
int threshold = 2;
__device__ void cuda_select(int *db, int size) {
int my_id = blockDim.x * blockIdx.x + threadIdx.x;
if(my_id < size) {
if(db[2 * my_id] > db[2 * my_id + 1])
db[my_id] = db[2 * my_id];
else
db[my_id] = db[2 * my_id + 1];
}
}
__global__ void select(int *db, int size) {
int height = (int)ceil(log2((double)size));
int i = 0;
for(i = 0; i < height; i++) {
size = (int)ceil((double) size/2);
cuda_select(db, size);
}
largest = db[0];
} | .text
.file "select.hip"
.globl _Z21__device_stub__selectPii # -- Begin function _Z21__device_stub__selectPii
.p2align 4, 0x90
.type _Z21__device_stub__selectPii,@function
_Z21__device_stub__selectPii: # @_Z21__device_stub__selectPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6selectPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__selectPii, .Lfunc_end0-_Z21__device_stub__selectPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6selectPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $position, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $largest, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type position,@object # @position
.local position
.comm position,4,4
.type largest,@object # @largest
.local largest
.comm largest,4,4
.type lenString,@object # @lenString
.data
.globl lenString
.p2align 2, 0x0
lenString:
.long 593 # 0x251
.size lenString, 4
.type maxNumStrings,@object # @maxNumStrings
.globl maxNumStrings
.p2align 2, 0x0
maxNumStrings:
.long 1000000 # 0xf4240
.size maxNumStrings, 4
.type threshold,@object # @threshold
.globl threshold
.p2align 2, 0x0
threshold:
.long 2 # 0x2
.size threshold, 4
.type _Z6selectPii,@object # @_Z6selectPii
.section .rodata,"a",@progbits
.globl _Z6selectPii
.p2align 3, 0x0
_Z6selectPii:
.quad _Z21__device_stub__selectPii
.size _Z6selectPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6selectPii"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "position"
.size .L__unnamed_2, 9
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "largest"
.size .L__unnamed_3, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__selectPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym position
.addrsig_sym largest
.addrsig_sym _Z6selectPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6selectPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ I2F.F64 R4, c[0x0][0x168] ; /* 0x00005a0000047b12 */
/* 0x000e220000201c00 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, -0x3ff ; /* 0xfffffc01ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ISETP.GT.AND P0, PT, R5, 0xfffff, PT ; /* 0x000fffff0500780c */
/* 0x001fe20003f04270 */
/*0040*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0004 */
/*0050*/ IMAD.MOV.U32 R7, RZ, RZ, R5.reuse ; /* 0x000000ffff077224 */
/* 0x100fe400078e0005 */
/*0060*/ IMAD.MOV.U32 R3, RZ, RZ, R5 ; /* 0x000000ffff037224 */
/* 0x000fd000078e0005 */
/*0070*/ @!P0 DMUL R6, R6, 1.80143985094819840000e+16 ; /* 0x4350000006068828 */
/* 0x000e220000000000 */
/*0080*/ @!P0 IMAD.MOV.U32 R2, RZ, RZ, -0x435 ; /* 0xfffffbcbff028424 */
/* 0x000fd200078e00ff */
/*0090*/ @!P0 IMAD.MOV.U32 R3, RZ, RZ, R7 ; /* 0x000000ffff038224 */
/* 0x001fe400078e0007 */
/*00a0*/ @!P0 IMAD.MOV.U32 R4, RZ, RZ, R6 ; /* 0x000000ffff048224 */
/* 0x000fc600078e0006 */
/*00b0*/ IADD3 R0, R3, -0x1, RZ ; /* 0xffffffff03007810 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R0, 0x7fefffff, PT ; /* 0x7fefffff0000780c */
/* 0x000fe20003f26070 */
/*00d0*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fd800078e00ff */
/*00e0*/ @!P1 BRA 0x160 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*00f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x0 ; /* 0x00000000ff027424 */
/* 0x000fe200078e00ff */
/*0100*/ FSETP.NEU.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fe20003f0d000 */
/*0110*/ IMAD.MOV.U32 R3, RZ, RZ, 0x7ff00000 ; /* 0x7ff00000ff037424 */
/* 0x000fcc00078e00ff */
/*0120*/ DFMA R2, R6, R2, +INF ; /* 0x7ff000000602742b */
/* 0x000e140000000002 */
/*0130*/ FSEL R4, R2, RZ, P0 ; /* 0x000000ff02047208 */
/* 0x001fe40000000000 */
/*0140*/ FSEL R5, R3, -QNAN , P0 ; /* 0xfff0000003057808 */
/* 0x000fe20000000000 */
/*0150*/ BRA 0x3f0 ; /* 0x0000029000007947 */
/* 0x000fea0003800000 */
/*0160*/ LOP3.LUT R5, R3.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff03057812 */
/* 0x040fe200078ec0ff */
/*0170*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe200078e00ff */
/*0180*/ LEA.HI R2, R3, R2, RZ, 0xc ; /* 0x0000000203027211 */
/* 0x000fe200078f60ff */
/*0190*/ IMAD.MOV.U32 R14, RZ, RZ, 0x3ae80f1e ; /* 0x3ae80f1eff0e7424 */
/* 0x000fe200078e00ff */
/*01a0*/ LOP3.LUT R5, R5, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000005057812 */
/* 0x000fe200078efcff */
/*01b0*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3eb1380b ; /* 0x3eb1380bff0f7424 */
/* 0x000fe400078e00ff */
/*01c0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x43300000 ; /* 0x43300000ff037424 */
/* 0x000fe200078e00ff */
/*01d0*/ ISETP.GE.AND P0, PT, R5, 0x3ff6a09f, PT ; /* 0x3ff6a09f0500780c */
/* 0x000fda0003f06270 */
/*01e0*/ @P0 IADD3 R7, R5, -0x100000, RZ ; /* 0xfff0000005070810 */
/* 0x000fe40007ffe0ff */
/*01f0*/ @P0 IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102020810 */
/* 0x000fc60007ffe0ff */
/*0200*/ @P0 IMAD.MOV.U32 R5, RZ, RZ, R7 ; /* 0x000000ffff050224 */
/* 0x000fe200078e0007 */
/*0210*/ LOP3.LUT R2, R2, 0x80000000, RZ, 0x3c, !PT ; /* 0x8000000002027812 */
/* 0x000fca00078e3cff */
/*0220*/ DADD R12, R4, 1 ; /* 0x3ff00000040c7429 */
/* 0x000e080000000000 */
/*0230*/ DADD R4, R4, -1 ; /* 0xbff0000004047429 */
/* 0x000fe40000000000 */
/*0240*/ MUFU.RCP64H R7, R13 ; /* 0x0000000d00077308 */
/* 0x001e240000001800 */
/*0250*/ DADD R2, R2, c[0x2][0x38] ; /* 0x00800e0002027629 */
/* 0x000fc80000000000 */
/*0260*/ DFMA R8, -R12, R6, 1 ; /* 0x3ff000000c08742b */
/* 0x001e0c0000000106 */
/*0270*/ DFMA R8, R8, R8, R8 ; /* 0x000000080808722b */
/* 0x001e0c0000000008 */
/*0280*/ DFMA R6, R6, R8, R6 ; /* 0x000000080606722b */
/* 0x001e0c0000000006 */
/*0290*/ DMUL R8, R6, R4 ; /* 0x0000000406087228 */
/* 0x001e0c0000000000 */
/*02a0*/ DFMA R8, R6, R4, R8 ; /* 0x000000040608722b */
/* 0x001e0c0000000008 */
/*02b0*/ DMUL R10, R8, R8 ; /* 0x00000008080a7228 */
/* 0x001e080000000000 */
/*02c0*/ DADD R12, R4, -R8 ; /* 0x00000000040c7229 */
/* 0x000e480000000808 */
/*02d0*/ DFMA R14, R10, R14, c[0x2][0x0] ; /* 0x008000000a0e762b */
/* 0x001e08000000000e */
/*02e0*/ DADD R16, R12, R12 ; /* 0x000000000c107229 */
/* 0x002fc8000000000c */
/*02f0*/ DFMA R14, R10, R14, c[0x2][0x8] ; /* 0x008002000a0e762b */
/* 0x001e08000000000e */
/*0300*/ DFMA R12, R2, c[0x2][0x40], R8 ; /* 0x00801000020c7a2b */
/* 0x000fc80000000008 */
/*0310*/ DFMA R14, R10, R14, c[0x2][0x10] ; /* 0x008004000a0e762b */
/* 0x001e08000000000e */
/*0320*/ DFMA R16, R4, -R8, R16 ; /* 0x800000080410722b */
/* 0x000fc80000000010 */
/*0330*/ DFMA R14, R10, R14, c[0x2][0x18] ; /* 0x008006000a0e762b */
/* 0x001e08000000000e */
/*0340*/ DFMA R4, -R2, c[0x2][0x40], R12 ; /* 0x0080100002047a2b */
/* 0x000fc8000000010c */
/*0350*/ DFMA R14, R10, R14, c[0x2][0x20] ; /* 0x008008000a0e762b */
/* 0x001e08000000000e */
/*0360*/ DMUL R16, R6, R16 ; /* 0x0000001006107228 */
/* 0x000fc80000000000 */
/*0370*/ DFMA R14, R10, R14, c[0x2][0x28] ; /* 0x00800a000a0e762b */
/* 0x001e08000000000e */
/*0380*/ DADD R4, -R8, R4 ; /* 0x0000000008047229 */
/* 0x000fc80000000104 */
/*0390*/ DFMA R14, R10, R14, c[0x2][0x30] ; /* 0x00800c000a0e762b */
/* 0x001e0c000000000e */
/*03a0*/ DMUL R14, R10, R14 ; /* 0x0000000e0a0e7228 */
/* 0x001e0c0000000000 */
/*03b0*/ DFMA R14, R8, R14, R16 ; /* 0x0000000e080e722b */
/* 0x001e0c0000000010 */
/*03c0*/ DADD R4, R14, -R4 ; /* 0x000000000e047229 */
/* 0x001e0c0000000804 */
/*03d0*/ DFMA R4, R2, c[0x2][0x48], R4 ; /* 0x0080120002047a2b */
/* 0x001e0c0000000004 */
/*03e0*/ DADD R4, R12, R4 ; /* 0x000000000c047229 */
/* 0x00104c0000000004 */
/*03f0*/ DMUL R2, R4, c[0x2][0x50] ; /* 0x0080140004027a28 */
/* 0x002e620000000000 */
/*0400*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fca0000000a00 */
/*0410*/ DFMA R2, R4, c[0x2][0x58], R2 ; /* 0x0080160004027a2b */
/* 0x002e4c0000000002 */
/*0420*/ F2I.F64.CEIL R9, R2 ; /* 0x0000000200097311 */
/* 0x002e640000309100 */
/*0430*/ ISETP.GE.AND P0, PT, R9, 0x1, PT ; /* 0x000000010900780c */
/* 0x002fda0003f06270 */
/*0440*/ @!P0 BRA 0x960 ; /* 0x0000051000008947 */
/* 0x000fea0003800000 */
/*0450*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e620000002500 */
/*0460*/ IADD3 R4, R9.reuse, -0x1, RZ ; /* 0xffffffff09047810 */
/* 0x040fe20007ffe0ff */
/*0470*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0480*/ LOP3.LUT R6, R9, 0x3, RZ, 0xc0, !PT ; /* 0x0000000309067812 */
/* 0x000fe200078ec0ff */
/*0490*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*04a0*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*04b0*/ IMAD R7, R7, c[0x0][0x0], R2 ; /* 0x0000000007077a24 */
/* 0x002fc800078e0202 */
/*04c0*/ IMAD.SHL.U32 R2, R7, 0x2, RZ ; /* 0x0000000207027824 */
/* 0x000fe400078e00ff */
/*04d0*/ IMAD.MOV R5, RZ, RZ, -R7 ; /* 0x000000ffff057224 */
/* 0x000fe400078e0a07 */
/*04e0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fcc00078e0203 */
/*04f0*/ IMAD.WIDE R4, R5, 0x4, R2 ; /* 0x0000000405047825 */
/* 0x000fe200078e0202 */
/*0500*/ @!P0 BRA 0x850 ; /* 0x0000034000008947 */
/* 0x000fea0003800000 */
/*0510*/ IMAD.IADD R8, R9, 0x1, -R6 ; /* 0x0000000109087824 */
/* 0x000fc800078e0a06 */
/*0520*/ I2F.F64 R10, R0 ; /* 0x00000000000a7312 */
/* 0x001e620000201c00 */
/*0530*/ IADD3 R8, R8, -0x4, RZ ; /* 0xfffffffc08087810 */
/* 0x000fe20007ffe0ff */
/*0540*/ BSSY B0, 0x6c0 ; /* 0x0000017000007945 */
/* 0x000fe60003800000 */
/*0550*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*0560*/ DMUL R10, R10, 0.5 ; /* 0x3fe000000a0a7828 */
/* 0x002e540000000000 */
/*0570*/ F2I.F64.CEIL R10, R10 ; /* 0x0000000a000a7311 */
/* 0x002e700000309100 */
/*0580*/ I2F.F64 R12, R10 ; /* 0x0000000a000c7312 */
/* 0x003e220000201c00 */
/*0590*/ ISETP.GE.AND P4, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x000fe20003f86270 */
/*05a0*/ DMUL R12, R12, 0.5 ; /* 0x3fe000000c0c7828 */
/* 0x001e140000000000 */
/*05b0*/ F2I.F64.CEIL R12, R12 ; /* 0x0000000c000c7311 */
/* 0x001e300000309100 */
/*05c0*/ I2F.F64 R14, R12 ; /* 0x0000000c000e7312 */
/* 0x001e220000201c00 */
/*05d0*/ ISETP.GE.AND P0, PT, R7, R12, PT ; /* 0x0000000c0700720c */
/* 0x000fe20003f06270 */
/*05e0*/ DMUL R14, R14, 0.5 ; /* 0x3fe000000e0e7828 */
/* 0x001e140000000000 */
/*05f0*/ F2I.F64.CEIL R14, R14 ; /* 0x0000000e000e7311 */
/* 0x001e300000309100 */
/*0600*/ I2F.F64 R16, R14 ; /* 0x0000000e00107312 */
/* 0x001e220000201c00 */
/*0610*/ ISETP.GE.AND P1, PT, R7, R14, PT ; /* 0x0000000e0700720c */
/* 0x000fe20003f26270 */
/*0620*/ DMUL R16, R16, 0.5 ; /* 0x3fe0000010107828 */
/* 0x001e0c0000000000 */
/*0630*/ F2I.F64.CEIL R0, R16 ; /* 0x0000001000007311 */
/* 0x001e240000309100 */
/*0640*/ ISETP.GE.AND P3, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x001fe20003f66270 */
/*0650*/ @P4 BRA 0x6b0 ; /* 0x0000005000004947 */
/* 0x000fee0003800000 */
/*0660*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0670*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea4000c1e1900 */
/*0680*/ ISETP.GT.AND P4, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x004fda0003f84270 */
/*0690*/ @!P4 STG.E [R4.64], R10 ; /* 0x0000000a0400c986 */
/* 0x0001e8000c101904 */
/*06a0*/ @P4 STG.E [R4.64], R9 ; /* 0x0000000904004986 */
/* 0x0001e4000c101904 */
/*06b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06c0*/ BSSY B0, 0x740 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*06d0*/ @P0 BRA 0x730 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*06e0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea8000c1e1900 */
/*06f0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea4000c1e1900 */
/*0700*/ ISETP.GT.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x004fda0003f04270 */
/*0710*/ @!P0 STG.E [R4.64], R10 ; /* 0x0000000a04008986 */
/* 0x0001e8000c101904 */
/*0720*/ @P0 STG.E [R4.64], R9 ; /* 0x0000000904000986 */
/* 0x0001e4000c101904 */
/*0730*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0740*/ BSSY B0, 0x7c0 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*0750*/ @P1 BRA 0x7b0 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*0760*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea8000c1e1900 */
/*0770*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea4000c1e1900 */
/*0780*/ ISETP.GT.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x004fda0003f04270 */
/*0790*/ @!P0 STG.E [R4.64], R10 ; /* 0x0000000a04008986 */
/* 0x0001e8000c101904 */
/*07a0*/ @P0 STG.E [R4.64], R9 ; /* 0x0000000904000986 */
/* 0x0001e4000c101904 */
/*07b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*07c0*/ BSSY B0, 0x840 ; /* 0x0000007000007945 */
/* 0x000fe20003800000 */
/*07d0*/ @P3 BRA 0x830 ; /* 0x0000005000003947 */
/* 0x000fea0003800000 */
/*07e0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x001ea8000c1e1900 */
/*07f0*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea4000c1e1900 */
/*0800*/ ISETP.GT.AND P0, PT, R9, R10, PT ; /* 0x0000000a0900720c */
/* 0x004fda0003f04270 */
/*0810*/ @!P0 STG.E [R4.64], R10 ; /* 0x0000000a04008986 */
/* 0x0001e8000c101904 */
/*0820*/ @P0 STG.E [R4.64], R9 ; /* 0x0000000904000986 */
/* 0x0001e4000c101904 */
/*0830*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0840*/ @P2 BRA 0x520 ; /* 0xfffffcd000002947 */
/* 0x000fea000383ffff */
/*0850*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0860*/ @!P0 BRA 0x960 ; /* 0x000000f000008947 */
/* 0x000fea0003800000 */
/*0870*/ I2F.F64 R8, R0 ; /* 0x0000000000087312 */
/* 0x001e220000201c00 */
/*0880*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*0890*/ BSSY B0, 0x950 ; /* 0x000000b000007945 */
/* 0x000fe60003800000 */
/*08a0*/ ISETP.NE.AND P1, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f25270 */
/*08b0*/ DMUL R8, R8, 0.5 ; /* 0x3fe0000008087828 */
/* 0x001e0c0000000000 */
/*08c0*/ F2I.F64.CEIL R0, R8 ; /* 0x0000000800007311 */
/* 0x001e240000309100 */
/*08d0*/ ISETP.GE.AND P0, PT, R7, R0, PT ; /* 0x000000000700720c */
/* 0x001fda0003f06270 */
/*08e0*/ @P0 BRA 0x940 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*08f0*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000ea8000c1e1900 */
/*0900*/ LDG.E R8, [R2.64+0x4] ; /* 0x0000040402087981 */
/* 0x000ea4000c1e1900 */
/*0910*/ ISETP.GT.AND P0, PT, R9, R8, PT ; /* 0x000000080900720c */
/* 0x004fda0003f04270 */
/*0920*/ @!P0 STG.E [R4.64], R8 ; /* 0x0000000804008986 */
/* 0x0001e8000c101904 */
/*0930*/ @P0 STG.E [R4.64], R9 ; /* 0x0000000904000986 */
/* 0x0001e4000c101904 */
/*0940*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0950*/ @P1 BRA 0x870 ; /* 0xffffff1000001947 */
/* 0x000fea000383ffff */
/*0960*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0970*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fca00078e00ff */
/*0980*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0990*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x001fe400078e00ff */
/*09a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fca00078e00ff */
/*09b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*09c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*09d0*/ BRA 0x9d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6selectPii
.globl _Z6selectPii
.p2align 8
.type _Z6selectPii,@function
_Z6selectPii:
s_load_b32 s4, s[0:1], 0x8
s_mov_b32 s3, 0x3fe55555
s_mov_b32 s2, 0x55555555
s_mov_b32 s7, 0x3fc38538
s_mov_b32 s6, 0x6b47b09a
s_mov_b32 s9, 0x3fc3ab76
s_mov_b32 s8, 0xbf559e2b
s_waitcnt lgkmcnt(0)
v_cvt_f64_i32_e32 v[1:2], s4
s_cmp_gt_i32 s4, -1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f64_e32 v[3:4], v[1:2]
v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[3:4]
s_mov_b32 s2, 0x55555780
v_cndmask_b32_e64 v5, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f64 v[3:4], v[3:4], v5
v_add_f64 v[5:6], v[3:4], 1.0
v_add_f64 v[11:12], v[3:4], -1.0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[7:8], v[5:6]
v_add_f64 v[13:14], v[5:6], -1.0
v_add_f64 v[3:4], v[3:4], -v[13:14]
s_waitcnt_depctr 0xfff
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[9:10], v[7:8], v[7:8]
v_mul_f64 v[9:10], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[15:16], v[5:6], v[9:10]
v_fma_f64 v[5:6], v[9:10], v[5:6], -v[15:16]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[9:10], v[3:4], v[5:6]
v_add_f64 v[5:6], v[15:16], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[11:12], -v[5:6]
v_add_f64 v[15:16], v[5:6], -v[15:16]
v_add_f64 v[11:12], v[11:12], -v[13:14]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[15:16], -v[3:4]
v_add_f64 v[5:6], v[11:12], -v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[3:4], v[5:6]
v_add_f64 v[3:4], v[13:14], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[7:8], v[3:4]
v_add_f64 v[5:6], v[9:10], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[7:8], v[5:6], v[5:6]
v_fma_f64 v[11:12], v[7:8], s[8:9], s[6:7]
s_mov_b32 s7, 0x3fc7474d
s_mov_b32 s6, 0xd7f4df2e
v_mul_f64 v[13:14], v[5:6], v[7:8]
s_delay_alu instid0(VALU_DEP_2)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[6:7]
s_mov_b32 s7, 0x3fcc71c0
s_mov_b32 s6, 0x16291751
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[6:7]
s_mov_b32 s7, 0x3fd24924
s_mov_b32 s6, 0x9b27acf1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[6:7]
s_mov_b32 s7, 0x3fd99999
s_mov_b32 s6, 0x998ef7b6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_fma_f64 v[11:12], v[7:8], v[11:12], s[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
v_fma_f64 v[7:8], v[7:8], v[11:12], s[2:3]
v_ldexp_f64 v[11:12], v[5:6], 1
v_add_f64 v[5:6], v[5:6], -v[9:10]
s_mov_b32 s3, 0x3ff71547
s_mov_b32 s2, 0x652b82fe
v_mul_f64 v[7:8], v[13:14], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[3:4], -v[5:6]
v_add_f64 v[9:10], v[11:12], v[7:8]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ldexp_f64 v[3:4], v[3:4], 1
v_add_f64 v[5:6], v[9:10], -v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[7:8], -v[5:6]
v_add_f64 v[3:4], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[9:10], v[3:4]
v_add_f64 v[7:8], v[5:6], -v[9:10]
v_mul_f64 v[9:10], v[5:6], s[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[3:4], v[3:4], -v[7:8]
v_fma_f64 v[7:8], v[5:6], s[2:3], -v[9:10]
s_delay_alu instid0(VALU_DEP_1)
v_fma_f64 v[3:4], v[3:4], s[2:3], v[7:8]
v_frexp_exp_i32_f64_e32 v7, v[1:2]
s_mov_b32 s3, 0x3c7777d0
s_mov_b32 s2, 0xffda0d24
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_fma_f64 v[1:2], v[5:6], s[2:3], v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
s_cselect_b32 vcc_lo, -1, 0
s_cmp_lg_u32 s4, 0
v_cvt_f64_i32_e32 v[3:4], v3
s_cselect_b32 s2, -1, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[9:10], v[1:2]
v_add_f64 v[7:8], v[5:6], v[3:4]
v_add_f64 v[9:10], v[5:6], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f64 v[11:12], v[7:8], -v[3:4]
v_add_f64 v[1:2], v[1:2], -v[9:10]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f64 v[13:14], v[11:12], -v[7:8]
v_add_f64 v[5:6], v[5:6], -v[11:12]
v_add_f64 v[3:4], v[13:14], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[5:6], v[3:4]
v_add_f64 v[1:2], v[1:2], v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[1:2], v[7:8], v[1:2]
v_cndmask_b32_e32 v2, 0x7ff80000, v2, vcc_lo
s_and_b32 vcc_lo, s2, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v1, 0, v1, vcc_lo
v_cndmask_b32_e64 v2, 0xfff00000, v2, s2
s_load_b64 s[2:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ceil_f64_e32 v[1:2], v[1:2]
v_cvt_i32_f64_e32 v8, v[1:2]
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_i32_e32 vcc_lo, 1, v8
s_cbranch_vccnz .LBB0_8
s_load_b32 s0, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s0, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_dual_mov_b32 v0, s4 :: v_dual_lshlrev_b32 v3, 1, v1
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_or_b32_e32 v5, 1, v3
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[9:10], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[11:12], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s2, v9
v_lshlrev_b64 v[6:7], 2, v[5:6]
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v12, vcc_lo
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v8, -1, v8
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ne_u32_e32 vcc_lo, 0, v8
s_cbranch_vccz .LBB0_8
.LBB0_3:
v_cvt_f64_i32_e32 v[9:10], v0
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[9:10], v[9:10], 0.5
v_ceil_f64_e32 v[9:10], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_i32_f64_e32 v0, v[9:10]
v_cmpx_lt_i32_e64 v1, v0
s_cbranch_execz .LBB0_2
s_clause 0x1
global_load_b32 v9, v[4:5], off
global_load_b32 v10, v[6:7], off
s_mov_b32 s1, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_le_i32_e64 v9, v10
s_xor_b32 s1, exec_lo, s1
s_cbranch_execz .LBB0_6
global_store_b32 v[2:3], v10, off
.LBB0_6:
s_and_not1_saveexec_b32 s1, s1
s_cbranch_execz .LBB0_2
global_store_b32 v[2:3], v9, off
s_branch .LBB0_2
.LBB0_8:
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v0, 0
s_getpc_b64 s[0:1]
s_add_u32 s0, s0, largest@rel32@lo+4
s_addc_u32 s1, s1, largest@rel32@hi+12
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[2:3]
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6selectPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6selectPii, .Lfunc_end0-_Z6selectPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected position
.type position,@object
.section .bss,"aw",@nobits
.globl position
.p2align 2, 0x0
position:
.long 0
.size position, 4
.protected largest
.type largest,@object
.globl largest
.p2align 2, 0x0
largest:
.long 0
.size largest, 4
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym largest
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6selectPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6selectPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001198b1_00000000-6_select.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11cuda_selectPii
.type _Z11cuda_selectPii, @function
_Z11cuda_selectPii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z11cuda_selectPii, .-_Z11cuda_selectPii
.globl _Z26__device_stub__Z6selectPiiPii
.type _Z26__device_stub__Z6selectPiiPii, @function
_Z26__device_stub__Z6selectPiiPii:
.LFB2052:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z6selectPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z26__device_stub__Z6selectPiiPii, .-_Z26__device_stub__Z6selectPiiPii
.globl _Z6selectPii
.type _Z6selectPii, @function
_Z6selectPii:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z6selectPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z6selectPii, .-_Z6selectPii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z6selectPii"
.LC1:
.string "position"
.LC2:
.string "largest"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z6selectPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL8position(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $4, %r9d
movl $0, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7largest(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl threshold
.data
.align 4
.type threshold, @object
.size threshold, 4
threshold:
.long 2
.globl maxNumStrings
.align 4
.type maxNumStrings, @object
.size maxNumStrings, 4
maxNumStrings:
.long 1000000
.globl lenString
.align 4
.type lenString, @object
.size lenString, 4
lenString:
.long 593
.local _ZL7largest
.comm _ZL7largest,4,4
.local _ZL8position
.comm _ZL8position,4,4
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "select.hip"
.globl _Z21__device_stub__selectPii # -- Begin function _Z21__device_stub__selectPii
.p2align 4, 0x90
.type _Z21__device_stub__selectPii,@function
_Z21__device_stub__selectPii: # @_Z21__device_stub__selectPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z6selectPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z21__device_stub__selectPii, .Lfunc_end0-_Z21__device_stub__selectPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
subq $32, %rsp
.cfi_adjust_cfa_offset 32
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6selectPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
addq $32, %rsp
.cfi_adjust_cfa_offset -32
movl $position, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $largest, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $4, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $0
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type position,@object # @position
.local position
.comm position,4,4
.type largest,@object # @largest
.local largest
.comm largest,4,4
.type lenString,@object # @lenString
.data
.globl lenString
.p2align 2, 0x0
lenString:
.long 593 # 0x251
.size lenString, 4
.type maxNumStrings,@object # @maxNumStrings
.globl maxNumStrings
.p2align 2, 0x0
maxNumStrings:
.long 1000000 # 0xf4240
.size maxNumStrings, 4
.type threshold,@object # @threshold
.globl threshold
.p2align 2, 0x0
threshold:
.long 2 # 0x2
.size threshold, 4
.type _Z6selectPii,@object # @_Z6selectPii
.section .rodata,"a",@progbits
.globl _Z6selectPii
.p2align 3, 0x0
_Z6selectPii:
.quad _Z21__device_stub__selectPii
.size _Z6selectPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z6selectPii"
.size .L__unnamed_1, 13
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "position"
.size .L__unnamed_2, 9
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "largest"
.size .L__unnamed_3, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__selectPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym position
.addrsig_sym largest
.addrsig_sym _Z6selectPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #pragma region License
/*
The MIT License
Copyright (c) 2009 Sky Morey
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
#pragma endregion
#pragma once
/*
#include <cuda.h>;
#include "Core.h";
#include "System\cuFalloc.cu"
using namespace System;
template class TreeSet<int>;
__device__ int system_COMPARE(unsigned __int32 shard, void* x, void* y)
{
int a = *((int*)x);
int b = *((int*)y);
return (a < b ? -1 : (a > b ? 1 : 0));
}
__global__ void TestTreeSet(fallocDeviceHeap* deviceHeap)
{
fallocInit(deviceHeap);
fallocContext* ctx = fallocCreateCtx(deviceHeap);
fallocContext* stack = fallocCreateCtx(deviceHeap);
falloc(stack, 70, false);
//
TreeSet<int> treeSet; treeSet.xtor(0, ctx);
treeSet.Add(5);
treeSet.Add(3);
treeSet.Add(1);
treeSet.Add(2);
treeSet.Add(7);
treeSet.Add(10);
//
treeSet.EnumeratorBegin(stack);
while (treeSet.EnumeratorMoveNext(stack))
cuPrintf("%d\n", treeSet.Current);
treeSet.EnumeratorEnd(stack);
//
fallocDisposeCtx(stack);
fallocDisposeCtx(ctx);
}
int main()
{
cudaFallocHeap heap = cudaFallocInit(2048);
cudaPrintfInit(256000);
// test
TestTreeSet<<<1, 1>>>(heap.deviceHeap);
// free and exit
cudaPrintfDisplay(stdout, true); cudaPrintfEnd();
cudaFallocEnd(heap);
printf("\ndone.\n"); scanf_s("%c");
return 0;
}
*/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #pragma region License
/*
The MIT License
Copyright (c) 2009 Sky Morey
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
#pragma endregion
#pragma once
/*
#include <cuda.h>;
#include "Core.h";
#include "System\cuFalloc.cu"
using namespace System;
template class TreeSet<int>;
__device__ int system_COMPARE(unsigned __int32 shard, void* x, void* y)
{
int a = *((int*)x);
int b = *((int*)y);
return (a < b ? -1 : (a > b ? 1 : 0));
}
__global__ void TestTreeSet(fallocDeviceHeap* deviceHeap)
{
fallocInit(deviceHeap);
fallocContext* ctx = fallocCreateCtx(deviceHeap);
fallocContext* stack = fallocCreateCtx(deviceHeap);
falloc(stack, 70, false);
//
TreeSet<int> treeSet; treeSet.xtor(0, ctx);
treeSet.Add(5);
treeSet.Add(3);
treeSet.Add(1);
treeSet.Add(2);
treeSet.Add(7);
treeSet.Add(10);
//
treeSet.EnumeratorBegin(stack);
while (treeSet.EnumeratorMoveNext(stack))
cuPrintf("%d\n", treeSet.Current);
treeSet.EnumeratorEnd(stack);
//
fallocDisposeCtx(stack);
fallocDisposeCtx(ctx);
}
int main()
{
cudaFallocHeap heap = cudaFallocInit(2048);
cudaPrintfInit(256000);
// test
TestTreeSet<<<1, 1>>>(heap.deviceHeap);
// free and exit
cudaPrintfDisplay(stdout, true); cudaPrintfEnd();
cudaFallocEnd(heap);
printf("\ndone.\n"); scanf_s("%c");
return 0;
}
*/ | .file "tmpxft_000be91f_00000000-6_TestTreeSet.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #pragma region License
/*
The MIT License
Copyright (c) 2009 Sky Morey
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
#pragma endregion
#pragma once
/*
#include <cuda.h>;
#include "Core.h";
#include "System\cuFalloc.cu"
using namespace System;
template class TreeSet<int>;
__device__ int system_COMPARE(unsigned __int32 shard, void* x, void* y)
{
int a = *((int*)x);
int b = *((int*)y);
return (a < b ? -1 : (a > b ? 1 : 0));
}
__global__ void TestTreeSet(fallocDeviceHeap* deviceHeap)
{
fallocInit(deviceHeap);
fallocContext* ctx = fallocCreateCtx(deviceHeap);
fallocContext* stack = fallocCreateCtx(deviceHeap);
falloc(stack, 70, false);
//
TreeSet<int> treeSet; treeSet.xtor(0, ctx);
treeSet.Add(5);
treeSet.Add(3);
treeSet.Add(1);
treeSet.Add(2);
treeSet.Add(7);
treeSet.Add(10);
//
treeSet.EnumeratorBegin(stack);
while (treeSet.EnumeratorMoveNext(stack))
cuPrintf("%d\n", treeSet.Current);
treeSet.EnumeratorEnd(stack);
//
fallocDisposeCtx(stack);
fallocDisposeCtx(ctx);
}
int main()
{
cudaFallocHeap heap = cudaFallocInit(2048);
cudaPrintfInit(256000);
// test
TestTreeSet<<<1, 1>>>(heap.deviceHeap);
// free and exit
cudaPrintfDisplay(stdout, true); cudaPrintfEnd();
cudaFallocEnd(heap);
printf("\ndone.\n"); scanf_s("%c");
return 0;
}
*/ | #pragma region License
/*
The MIT License
Copyright (c) 2009 Sky Morey
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
#pragma endregion
#pragma once
#include <hip/hip_runtime.h>
/*
#include <cuda.h>;
#include "Core.h";
#include "System\cuFalloc.cu"
using namespace System;
template class TreeSet<int>;
__device__ int system_COMPARE(unsigned __int32 shard, void* x, void* y)
{
int a = *((int*)x);
int b = *((int*)y);
return (a < b ? -1 : (a > b ? 1 : 0));
}
__global__ void TestTreeSet(fallocDeviceHeap* deviceHeap)
{
fallocInit(deviceHeap);
fallocContext* ctx = fallocCreateCtx(deviceHeap);
fallocContext* stack = fallocCreateCtx(deviceHeap);
falloc(stack, 70, false);
//
TreeSet<int> treeSet; treeSet.xtor(0, ctx);
treeSet.Add(5);
treeSet.Add(3);
treeSet.Add(1);
treeSet.Add(2);
treeSet.Add(7);
treeSet.Add(10);
//
treeSet.EnumeratorBegin(stack);
while (treeSet.EnumeratorMoveNext(stack))
cuPrintf("%d\n", treeSet.Current);
treeSet.EnumeratorEnd(stack);
//
fallocDisposeCtx(stack);
fallocDisposeCtx(ctx);
}
int main()
{
cudaFallocHeap heap = cudaFallocInit(2048);
cudaPrintfInit(256000);
// test
TestTreeSet<<<1, 1>>>(heap.deviceHeap);
// free and exit
cudaPrintfDisplay(stdout, true); cudaPrintfEnd();
cudaFallocEnd(heap);
printf("\ndone.\n"); scanf_s("%c");
return 0;
}
*/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #pragma region License
/*
The MIT License
Copyright (c) 2009 Sky Morey
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
#pragma endregion
#pragma once
#include <hip/hip_runtime.h>
/*
#include <cuda.h>;
#include "Core.h";
#include "System\cuFalloc.cu"
using namespace System;
template class TreeSet<int>;
__device__ int system_COMPARE(unsigned __int32 shard, void* x, void* y)
{
int a = *((int*)x);
int b = *((int*)y);
return (a < b ? -1 : (a > b ? 1 : 0));
}
__global__ void TestTreeSet(fallocDeviceHeap* deviceHeap)
{
fallocInit(deviceHeap);
fallocContext* ctx = fallocCreateCtx(deviceHeap);
fallocContext* stack = fallocCreateCtx(deviceHeap);
falloc(stack, 70, false);
//
TreeSet<int> treeSet; treeSet.xtor(0, ctx);
treeSet.Add(5);
treeSet.Add(3);
treeSet.Add(1);
treeSet.Add(2);
treeSet.Add(7);
treeSet.Add(10);
//
treeSet.EnumeratorBegin(stack);
while (treeSet.EnumeratorMoveNext(stack))
cuPrintf("%d\n", treeSet.Current);
treeSet.EnumeratorEnd(stack);
//
fallocDisposeCtx(stack);
fallocDisposeCtx(ctx);
}
int main()
{
cudaFallocHeap heap = cudaFallocInit(2048);
cudaPrintfInit(256000);
// test
TestTreeSet<<<1, 1>>>(heap.deviceHeap);
// free and exit
cudaPrintfDisplay(stdout, true); cudaPrintfEnd();
cudaFallocEnd(heap);
printf("\ndone.\n"); scanf_s("%c");
return 0;
}
*/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #pragma region License
/*
The MIT License
Copyright (c) 2009 Sky Morey
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
#pragma endregion
#pragma once
#include <hip/hip_runtime.h>
/*
#include <cuda.h>;
#include "Core.h";
#include "System\cuFalloc.cu"
using namespace System;
template class TreeSet<int>;
__device__ int system_COMPARE(unsigned __int32 shard, void* x, void* y)
{
int a = *((int*)x);
int b = *((int*)y);
return (a < b ? -1 : (a > b ? 1 : 0));
}
__global__ void TestTreeSet(fallocDeviceHeap* deviceHeap)
{
fallocInit(deviceHeap);
fallocContext* ctx = fallocCreateCtx(deviceHeap);
fallocContext* stack = fallocCreateCtx(deviceHeap);
falloc(stack, 70, false);
//
TreeSet<int> treeSet; treeSet.xtor(0, ctx);
treeSet.Add(5);
treeSet.Add(3);
treeSet.Add(1);
treeSet.Add(2);
treeSet.Add(7);
treeSet.Add(10);
//
treeSet.EnumeratorBegin(stack);
while (treeSet.EnumeratorMoveNext(stack))
cuPrintf("%d\n", treeSet.Current);
treeSet.EnumeratorEnd(stack);
//
fallocDisposeCtx(stack);
fallocDisposeCtx(ctx);
}
int main()
{
cudaFallocHeap heap = cudaFallocInit(2048);
cudaPrintfInit(256000);
// test
TestTreeSet<<<1, 1>>>(heap.deviceHeap);
// free and exit
cudaPrintfDisplay(stdout, true); cudaPrintfEnd();
cudaFallocEnd(heap);
printf("\ndone.\n"); scanf_s("%c");
return 0;
}
*/ | .text
.file "TestTreeSet.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000be91f_00000000-6_TestTreeSet.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "TestTreeSet.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // Version single file
#include <stdlib.h>
#include <stdio.h>
// Pour pouvoir experimenter les performances avec les différents types
// FMT Permet d'avoir un % adapté pour le printf et donc de pas avoir de warning
#define TYPE int
#define FMT "d"
typedef struct
{
int x ;
int y ;
} Point ;
__global__ void PathBig(TYPE * CudaVecteurA, TYPE * CudaVecteurB, int sizeA , int sizeB, int * CudaDiagBx, int * CudaDiagAy, int nbthread, int NbWindows)
{
//Initialisation diagolane
CudaDiagBx[0] = CudaDiagAy[0] = 0 ;
CudaDiagBx[NbWindows] = sizeB ;
CudaDiagAy[NbWindows] = sizeA ;
int nth = threadIdx.x; // On explore le nth diagonale
Point K, P, Q ;
int px , py ;
TYPE * A = CudaVecteurA ;
TYPE * B = CudaVecteurB ;
int offset ;
int numDiag = (nth+1) * nbthread -1 ; // Les tableaux vont de 0 à N-1
if (numDiag > sizeA)
{
K.x = numDiag - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = numDiag - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = numDiag ;
P.x = numDiag ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
px = Q.x ; py = Q.y ;
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ // v = A[Q.y] ;
py ++ ;
}
else
{ // v = B[Q.x] ;
px ++ ;
}
// printf("Analyse Diagonale Point de Sortie ref %d - M %" FMT " Q (A Q.y %d) (B Q.x %d) rv.x %d rv.y %d\n",i,v,Q.y,Q.x,rv->x,rv->y) ;
CudaDiagBx[nth+1] = px ; CudaDiagAy[nth+1] = py ;
break ; // Pour simuler passage au thread suivant
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
} // End of PathBig
__global__ void MergeBig_k(TYPE * CudaVecteurA, TYPE * CudaVecteurB, TYPE * CudaVecteurC, int * CudaDiagAy, int * CudaDiagBx , int nbthread)
{
// int i = threadIdx.x ; // On renge le Ieme element
int i = blockIdx.x * blockDim.x + threadIdx.x; // On range le ieme elet
int diag = (i / nbthread) ; // Dans quel fenêtre est-il ?
int indC = nbthread * diag ;
TYPE *A = CudaVecteurA+CudaDiagAy[diag] ;
TYPE *B = CudaVecteurB+CudaDiagBx[diag] ;
TYPE *M = CudaVecteurC + indC ;
int sizeA = CudaDiagAy[diag+1]-CudaDiagAy[diag] ;
int sizeB = CudaDiagBx[diag+1]-CudaDiagBx[diag] ;
Point K, P, Q;
int offset ;
i = i % nbthread ; // On recadre i dans le nouvel espace
if (i >= (sizeA + sizeB)) { return ; } // On gère les ébordements
if (i > sizeA)
{
K.x = i - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = i - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = i ;
P.x = i ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ M[i] = A[Q.y] ; }
else
{ M[i] = B[Q.x] ; }
break ;
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
}
int check(char * msg, int Nb, TYPE * pto)
{
TYPE * pt1 = pto ;
TYPE * pt2 = pto + 1 ;
int i ;
for (i = 0 ; i < Nb-1 ; i ++)
{
if (*pt1 > *pt2)
{ printf("Check %s pour %d - Erreur en position %d %" FMT " > %" FMT " \n", msg, Nb, i, *pt1, *pt2) ;
return i ;
}
pt1 ++ ; pt2 ++ ;
}
printf("Premiere valeur de %s = %" FMT ", deuxième valeur = %" FMT ", troisième valeur = %" FMT " \n", msg, pto[0], pto[1], pto[2]);
printf("Check %s pour %d est OK \n", msg, Nb) ;
return 0 ;
}
void Affiche(char * tabMsg, TYPE * ptBuffer, int NB)
{
TYPE * pt = ptBuffer ;
for ( int k = 0 ; k < NB ; k++ , pt ++)
{ printf(" - %s[%03d] = %6" FMT, tabMsg, k , *pt) ;
if ((k % 5) == (4))
{ printf("\n") ; }
}
printf("\n") ;
}
int main(int argc, char ** argv)
{
//déclaration
int sizeA = 1600;
int sizeB = 1000 ;
int sizeM = sizeA + sizeB ;
TYPE* A;
TYPE* B ;
TYPE* M;
float m1;
cudaEvent_t Start; cudaEvent_t Stop; cudaEventCreate(&Start) ; cudaEventCreate(&Stop) ;
//allocation
if ((A = (TYPE *) malloc(sizeA * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurA\n") ; exit (1) ; }
if ((B= (TYPE *) malloc(sizeB * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurB\n") ; exit (1) ; }
if ((M= (TYPE *) malloc(sizeM * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurM\n") ; exit (1) ; }
//initialisation
srand(1925);
A[0] = B[0] = rand()%100;
for (int i =1; i<sizeA; i++)
{
A[i]=A[i-1]+rand()%100;
}
for (int i =1; i<sizeB; i++)
{
B[i]=B[i-1]+rand()%100;
}
//Declarations
cudaError_t errCuda;
TYPE * CudaVecteurA = NULL ;
TYPE * CudaVecteurB = NULL ;
TYPE * CudaVecteurM = NULL ;
int nbthread = 512; // a verifier
int NbDiagonale = (sizeA + sizeB) / nbthread ;
int NbWindows = NbDiagonale ;
NbWindows += (((sizeA + sizeB) % nbthread) == 0)?0:1 ; // si (SizeA + SizeB) % nbthread == 0 alors nbWindows = 0 sinon = 1
int * CudaDiagBx = NULL ;
int * CudaDiagAy = NULL ;
//Allocation
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaVecteurA, sizeA * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurA - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout) ; exit (1) ; } // cleanup a rajouter pour plus propre
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaVecteurB, sizeB * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurB - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; } // cleanup a rajouter pour plus propre
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaVecteurM, sizeM * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurM - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaDiagBx, (NbWindows + 1) * sizeof(int))))
{ printf("PB allocation CudaDiagBx - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaDiagAy, (NbWindows + 1)* sizeof(int))))
{ printf("PB allocation CudaDiagAy - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (cudaSuccess != cudaMemcpy(CudaVecteurA, A, sizeA * sizeof(TYPE), cudaMemcpyHostToDevice))
{ printf("PB copie host A -> cuda A \n") ; fflush(stdout); exit(2) ; }
if (cudaSuccess != cudaMemcpy(CudaVecteurB, B, sizeB * sizeof(TYPE), cudaMemcpyHostToDevice))
{ printf("PB copie host B -> cuda B \n") ; fflush(stdout); exit(2) ; }
cudaEventRecord(Start);
PathBig<<<1,NbDiagonale>>>(CudaVecteurA, CudaVecteurB, sizeA , sizeB, CudaDiagBx, CudaDiagAy, nbthread,NbWindows) ;
int nbBlock = (sizeA+sizeB) / 1024 ;
nbBlock += ((sizeA+sizeB) % 1024)?1:0 ;
if (sizeM <1024)
{
printf("La fonction MergeBig ne peut pas être prise en compte car sizeA+sizeB <1024");
exit(2);
}
else { MergeBig_k<<<nbBlock,1024>>> (CudaVecteurA, CudaVecteurB, CudaVecteurM, CudaDiagAy, CudaDiagBx, nbthread) ;}
if (cudaSuccess != cudaMemcpy(M, CudaVecteurM, sizeM * sizeof(TYPE), cudaMemcpyDeviceToHost))
{ printf("PB copie cuda M -> host M \n") ; fflush(stdout); exit(2) ; }
cudaEventRecord(Stop) ;
check((char *)"Check tableau M après", sizeM, M);
cudaEventElapsedTime(&m1, Start, Stop) ;
printf("Duree %f s\n",m1/1000) ;
//Affiche ("Tableau M", M, sizeM);
//Free
if (M != NULL ){ free(M); }
if (A != NULL) { free(A) ; }
if (B != NULL) { free(B) ; }
if (CudaVecteurA != NULL) { cudaFree(CudaVecteurA) ; CudaVecteurA = NULL ; }
if (CudaVecteurB != NULL) { cudaFree(CudaVecteurB) ; CudaVecteurB = NULL ; }
if (CudaVecteurM != NULL) { cudaFree(CudaVecteurM) ; CudaVecteurM = NULL ; }
if (CudaDiagAy != NULL) { cudaFree(CudaDiagAy) ; CudaDiagAy = NULL ; }
if (CudaDiagBx != NULL) { cudaFree(CudaDiagBx) ; CudaDiagBx = NULL ; }
return 0 ;
} | code for sm_80
Function : _Z10MergeBig_kPiS_S_S_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IABS R5, c[0x0][0x188] ; /* 0x0000620000057a13 */
/* 0x000fe20000000000 */
/*0020*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ I2F.RP R0, R5 ; /* 0x0000000500007306 */
/* 0x000e620000209400 */
/*0050*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e2e0000002100 */
/*0060*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x002e620000001000 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R4 ; /* 0x0000000007077a24 */
/* 0x001fe200078e0204 */
/*0080*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x002fc80007ffe0ff */
/*0090*/ IABS R0, R7 ; /* 0x0000000700007213 */
/* 0x000fe40000000000 */
/*00a0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x000064000021f000 */
/*00b0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00c0*/ IMAD.MOV R6, RZ, RZ, -R3 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a03 */
/*00d0*/ IMAD R9, R6, R5, RZ ; /* 0x0000000506097224 */
/* 0x000fc800078e02ff */
/*00e0*/ IMAD.HI.U32 R3, R3, R9, R2 ; /* 0x0000000903037227 */
/* 0x000fcc00078e0002 */
/*00f0*/ IMAD.HI.U32 R3, R3, R0, RZ ; /* 0x0000000003037227 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD.MOV R4, RZ, RZ, -R3 ; /* 0x000000ffff047224 */
/* 0x000fc800078e0a03 */
/*0110*/ IMAD R0, R5, R4, R0 ; /* 0x0000000405007224 */
/* 0x000fca00078e0200 */
/*0120*/ ISETP.GT.U32.AND P2, PT, R5, R0, PT ; /* 0x000000000500720c */
/* 0x000fda0003f44070 */
/*0130*/ @!P2 IMAD.IADD R0, R0, 0x1, -R5 ; /* 0x000000010000a824 */
/* 0x000fe200078e0a05 */
/*0140*/ @!P2 IADD3 R3, R3, 0x1, RZ ; /* 0x000000010303a810 */
/* 0x000fe40007ffe0ff */
/*0150*/ ISETP.NE.AND P2, PT, RZ, c[0x0][0x188], PT ; /* 0x00006200ff007a0c */
/* 0x000fe40003f45270 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R0, R5, PT ; /* 0x000000050000720c */
/* 0x000fe20003f06070 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0180*/ LOP3.LUT R0, R7, c[0x0][0x188], RZ, 0x3c, !PT ; /* 0x0000620007007a12 */
/* 0x000fc800078e3cff */
/*0190*/ ISETP.GE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fce0003f26270 */
/*01a0*/ @P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103030810 */
/* 0x000fca0007ffe0ff */
/*01b0*/ IMAD.MOV.U32 R10, RZ, RZ, R3 ; /* 0x000000ffff0a7224 */
/* 0x000fc800078e0003 */
/*01c0*/ @!P1 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0a9224 */
/* 0x000fe200078e0a0a */
/*01d0*/ @!P2 LOP3.LUT R10, RZ, c[0x0][0x188], RZ, 0x33, !PT ; /* 0x00006200ff0aaa12 */
/* 0x000fca00078e33ff */
/*01e0*/ IMAD.WIDE R2, R10, R5, c[0x0][0x178] ; /* 0x00005e000a027625 */
/* 0x000fc800078e0205 */
/*01f0*/ IMAD.WIDE R4, R10.reuse, R5, c[0x0][0x180] ; /* 0x000060000a047625 */
/* 0x040fe200078e0205 */
/*0200*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0210*/ LDG.E R9, [R2.64+0x4] ; /* 0x0000040402097981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee8000c1e1900 */
/*0230*/ LDG.E R11, [R4.64+0x4] ; /* 0x00000404040b7981 */
/* 0x000ee2000c1e1900 */
/*0240*/ IMAD R10, R10, c[0x0][0x188], RZ ; /* 0x000062000a0a7a24 */
/* 0x000fc800078e02ff */
/*0250*/ IMAD.IADD R14, R7, 0x1, -R10 ; /* 0x00000001070e7824 */
/* 0x000fe400078e0a0a */
/*0260*/ IMAD.IADD R9, R9, 0x1, -R0 ; /* 0x0000000109097824 */
/* 0x004fe400078e0a00 */
/*0270*/ IMAD.IADD R12, R11, 0x1, -R8 ; /* 0x000000010b0c7824 */
/* 0x008fc800078e0a08 */
/*0280*/ IMAD.IADD R7, R9, 0x1, R12 ; /* 0x0000000109077824 */
/* 0x000fca00078e020c */
/*0290*/ ISETP.GE.AND P0, PT, R14, R7, PT ; /* 0x000000070e00720c */
/* 0x000fda0003f06270 */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*02b0*/ IMAD.IADD R15, R14, 0x1, -R9 ; /* 0x000000010e0f7824 */
/* 0x000fe200078e0a09 */
/*02c0*/ BSSY B1, 0x620 ; /* 0x0000035000017945 */
/* 0x000fe20003800000 */
/*02d0*/ SHF.R.S32.HI R11, RZ, 0x1f, R0 ; /* 0x0000001fff0b7819 */
/* 0x000fe40000011400 */
/*02e0*/ IMNMX R18, R9, R14, PT ; /* 0x0000000e09127217 */
/* 0x000fe40003800200 */
/*02f0*/ IMNMX R15, RZ, R15, !PT ; /* 0x0000000fff0f7217 */
/* 0x000fe40007800200 */
/*0300*/ SHF.R.S32.HI R13, RZ, 0x1f, R10 ; /* 0x0000001fff0d7819 */
/* 0x000fe4000001140a */
/*0310*/ SHF.R.S32.HI R17, RZ, 0x1f, R8 ; /* 0x0000001fff117819 */
/* 0x000fe20000011408 */
/*0320*/ IMAD.MOV.U32 R20, RZ, RZ, R15 ; /* 0x000000ffff147224 */
/* 0x000fca00078e000f */
/*0330*/ BSSY B2, 0x530 ; /* 0x000001f000027945 */
/* 0x000fe40003800000 */
/*0340*/ IMAD.IADD R2, R18, 0x1, -R15 ; /* 0x0000000112027824 */
/* 0x000fe200078e0a0f */
/*0350*/ BSSY B0, 0x500 ; /* 0x000001a000007945 */
/* 0x000fe80003800000 */
/*0360*/ IABS R2, R2 ; /* 0x0000000200027213 */
/* 0x000fc80000000000 */
/*0370*/ LEA.HI R2, R2, R2, RZ, 0x1 ; /* 0x0000000202027211 */
/* 0x000fc800078f08ff */
/*0380*/ SHF.R.S32.HI R3, RZ, 0x1, R2 ; /* 0x00000001ff037819 */
/* 0x000fca0000011402 */
/*0390*/ IMAD.IADD R19, R20, 0x1, R3.reuse ; /* 0x0000000114137824 */
/* 0x100fe400078e0203 */
/*03a0*/ IMAD.IADD R16, R18, 0x1, -R3 ; /* 0x0000000112107824 */
/* 0x000fc600078e0a03 */
/*03b0*/ ISETP.GT.AND P0, PT, R19, R12, PT ; /* 0x0000000c1300720c */
/* 0x000fc80003f04270 */
/*03c0*/ ISETP.LT.OR P0, PT, R16, RZ, P0 ; /* 0x000000ff1000720c */
/* 0x000fda0000701670 */
/*03d0*/ @P0 BRA 0x4f0 ; /* 0x0000011000000947 */
/* 0x000fea0003800000 */
/*03e0*/ ISETP.NE.AND P0, PT, R19.reuse, RZ, PT ; /* 0x000000ff1300720c */
/* 0x040fe40003f05270 */
/*03f0*/ IADD3 R3, P2, R0, R16, RZ ; /* 0x0000001000037210 */
/* 0x000fe40007f5e0ff */
/*0400*/ ISETP.EQ.OR P0, PT, R16, R9, !P0 ; /* 0x000000091000720c */
/* 0x000fe40004702670 */
/*0410*/ IADD3 R5, P1, R8, R19, RZ ; /* 0x0000001308057210 */
/* 0x000fe40007f3e0ff */
/*0420*/ LEA.HI.X.SX32 R22, R16, R11, 0x1, P2 ; /* 0x0000000b10167211 */
/* 0x000fe400010f0eff */
/*0430*/ LEA.HI.X.SX32 R6, R19, R17, 0x1, P1 ; /* 0x0000001113067211 */
/* 0x000fc400008f0eff */
/*0440*/ LEA R2, P2, R3, c[0x0][0x160], 0x2 ; /* 0x0000580003027a11 */
/* 0x000fe400078410ff */
/*0450*/ LEA R4, P1, R5, c[0x0][0x168], 0x2 ; /* 0x00005a0005047a11 */
/* 0x000fe400078210ff */
/*0460*/ LEA.HI.X R3, R3, c[0x0][0x164], R22, 0x2, P2 ; /* 0x0000590003037a11 */
/* 0x000fe200010f1416 */
/*0470*/ @P0 BREAK B0 ; /* 0x0000000000000942 */
/* 0x000fe20003800000 */
/*0480*/ LEA.HI.X R5, R5, c[0x0][0x16c], R6, 0x2, P1 ; /* 0x00005b0005057a11 */
/* 0x000fe200008f1406 */
/*0490*/ @P0 BRA 0x520 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*04a0*/ LDG.E R6, [R2.64] ; /* 0x0000000402067981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R7, [R4.64+-0x4] ; /* 0xfffffc0404077981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ ISETP.GT.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x004fda0003f04270 */
/*04d0*/ @P0 BREAK B0 ; /* 0x0000000000000942 */
/* 0x000fe20003800000 */
/*04e0*/ @P0 BRA 0x520 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*04f0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0500*/ IADD3 R15, R16, 0x1, RZ ; /* 0x00000001100f7810 */
/* 0x000fe20007ffe0ff */
/*0510*/ BRA 0x340 ; /* 0xfffffe2000007947 */
/* 0x000fea000383ffff */
/*0520*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0530*/ ISETP.NE.AND P0, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fe40003f05270 */
/*0540*/ ISETP.NE.AND P1, PT, R19.reuse, R12.reuse, PT ; /* 0x0000000c1300720c */
/* 0x0c0fe40003f25270 */
/*0550*/ ISETP.EQ.OR P0, PT, R19, R12, !P0 ; /* 0x0000000c1300720c */
/* 0x000fda0004702670 */
/*0560*/ @P0 BRA 0x610 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0570*/ IADD3 R18, R16, -0x1, RZ ; /* 0xffffffff10127810 */
/* 0x000fc80007ffe0ff */
/*0580*/ IADD3 R7, P0, R0, R18, RZ ; /* 0x0000001200077210 */
/* 0x000fc80007f1e0ff */
/*0590*/ LEA.HI.X.SX32 R20, R18, R11, 0x1, P0 ; /* 0x0000000b12147211 */
/* 0x000fe400000f0eff */
/*05a0*/ LEA R6, P0, R7, c[0x0][0x160], 0x2 ; /* 0x0000580007067a11 */
/* 0x000fc800078010ff */
/*05b0*/ LEA.HI.X R7, R7, c[0x0][0x164], R20, 0x2, P0 ; /* 0x0000590007077a11 */
/* 0x000fe400000f1414 */
/*05c0*/ LDG.E R20, [R4.64] ; /* 0x0000000404147981 */
/* 0x000ea8000c1e1900 */
/*05d0*/ LDG.E R7, [R6.64] ; /* 0x0000000406077981 */
/* 0x000ea4000c1e1900 */
/*05e0*/ ISETP.GT.AND P0, PT, R7, R20, PT ; /* 0x000000140700720c */
/* 0x004fda0003f04270 */
/*05f0*/ @P0 IADD3 R20, R19, 0x1, RZ ; /* 0x0000000113140810 */
/* 0x000fe20007ffe0ff */
/*0600*/ @P0 BRA 0x330 ; /* 0xfffffd2000000947 */
/* 0x000fea000383ffff */
/*0610*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0620*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0630*/ IADD3 R10, P0, R10, R14, RZ ; /* 0x0000000e0a0a7210 */
/* 0x000fe20007f1e0ff */
/*0640*/ BSSY B1, 0x700 ; /* 0x000000b000017945 */
/* 0x000fe60003800000 */
/*0650*/ LEA.HI.X.SX32 R13, R14, R13, 0x1, P0 ; /* 0x0000000d0e0d7211 */
/* 0x000fe400000f0eff */
/*0660*/ ISETP.GE.AND P0, PT, R16, R9, PT ; /* 0x000000091000720c */
/* 0x000fe40003f06270 */
/*0670*/ LEA R6, P2, R10, c[0x0][0x170], 0x2 ; /* 0x00005c000a067a11 */
/* 0x000fc800078410ff */
/*0680*/ LEA.HI.X R7, R10, c[0x0][0x174], R13, 0x2, P2 ; /* 0x00005d000a077a11 */
/* 0x000fce00010f140d */
/*0690*/ @P0 BRA 0x6f0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*06a0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000162000c1e1900 */
/*06b0*/ @!P1 BRA 0x730 ; /* 0x0000007000009947 */
/* 0x000fea0003800000 */
/*06c0*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea4000c1e1900 */
/*06d0*/ ISETP.GT.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x024fda0003f04270 */
/*06e0*/ @!P0 BRA 0x730 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*06f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0700*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0710*/ STG.E [R6.64], R5 ; /* 0x0000000506007986 */
/* 0x004fe2000c101904 */
/*0720*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0730*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x020fe2000c101904 */
/*0740*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0750*/ BRA 0x750; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7PathBigPiS_iiS_S_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x18c] ; /* 0x00006300ff087624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fe200078e00ff */
/*0050*/ MOV R15, c[0x0][0x170] ; /* 0x00005c00000f7a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x180] ; /* 0x00006000ff027624 */
/* 0x000fe200078e00ff */
/*0070*/ BSSY B1, 0x410 ; /* 0x0000039000017945 */
/* 0x000fe20003800000 */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff037624 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe400078e00ff */
/*00a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff057624 */
/* 0x000fe200078e00ff */
/*00b0*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0003e2000c101904 */
/*00c0*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff0d7624 */
/* 0x000fc400078e00ff */
/*00d0*/ IMAD.WIDE R6, R8.reuse, R9.reuse, c[0x0][0x178] ; /* 0x00005e0008067625 */
/* 0x0c0fe200078e0209 */
/*00e0*/ STG.E [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x0003e6000c101904 */
/*00f0*/ IMAD.WIDE R8, R8, R9, c[0x0][0x180] ; /* 0x0000600008087625 */
/* 0x000fe200078e0209 */
/*0100*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x0003e6000c101904 */
/*0110*/ IMAD.MOV.U32 R11, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff0b7624 */
/* 0x000fe200078e00ff */
/*0120*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0003e2000c101904 */
/*0130*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x001fca0007ffe0ff */
/*0140*/ IMAD R10, R0, R11, -0x1 ; /* 0xffffffff000a7424 */
/* 0x000fca00078e020b */
/*0150*/ IADD3 R11, R10.reuse, -c[0x0][0x170], RZ ; /* 0x80005c000a0b7a10 */
/* 0x040fe40007ffe0ff */
/*0160*/ IMNMX R10, R10, c[0x0][0x170], PT ; /* 0x00005c000a0a7a17 */
/* 0x000fe40003800200 */
/*0170*/ IMNMX R11, RZ, R11, !PT ; /* 0x0000000bff0b7217 */
/* 0x000fca0007800200 */
/*0180*/ IMAD.MOV.U32 R12, RZ, RZ, R11 ; /* 0x000000ffff0c7224 */
/* 0x002fca00078e000b */
/*0190*/ BSSY B2, 0x350 ; /* 0x000001b000027945 */
/* 0x000fe40003800000 */
/*01a0*/ IMAD.IADD R2, R10, 0x1, -R11 ; /* 0x000000010a027824 */
/* 0x000fe200078e0a0b */
/*01b0*/ BSSY B0, 0x320 ; /* 0x0000016000007945 */
/* 0x000fe80003800000 */
/*01c0*/ IABS R2, R2 ; /* 0x0000000200027213 */
/* 0x000fc80000000000 */
/*01d0*/ LEA.HI R2, R2, R2, RZ, 0x1 ; /* 0x0000000202027211 */
/* 0x000fc800078f08ff */
/*01e0*/ SHF.R.S32.HI R9, RZ, 0x1, R2 ; /* 0x00000001ff097819 */
/* 0x000fca0000011402 */
/*01f0*/ IMAD.IADD R2, R12, 0x1, R9 ; /* 0x000000010c027824 */
/* 0x000fe200078e0209 */
/*0200*/ IADD3 R9, R10, -R9, RZ ; /* 0x800000090a097210 */
/* 0x000fc80007ffe0ff */
/*0210*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x174], PT ; /* 0x00005d0002007a0c */
/* 0x000fc80003f04270 */
/*0220*/ ISETP.LT.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000701670 */
/*0230*/ @P0 BRA 0x310 ; /* 0x000000d000000947 */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0002 */
/*0250*/ IMAD.MOV.U32 R15, RZ, RZ, 0x4 ; /* 0x00000004ff0f7424 */
/* 0x000fc600078e00ff */
/*0260*/ ISETP.NE.AND P0, PT, R13, RZ, PT ; /* 0x000000ff0d00720c */
/* 0x000fe20003f05270 */
/*0270*/ IMAD.WIDE R6, R9, R15, c[0x0][0x160] ; /* 0x0000580009067625 */
/* 0x000fc600078e020f */
/*0280*/ ISETP.EQ.OR P0, PT, R9, c[0x0][0x170], !P0 ; /* 0x00005c0009007a0c */
/* 0x000fe20004702670 */
/*0290*/ IMAD.WIDE R2, R13, R15, c[0x0][0x168] ; /* 0x00005a000d027625 */
/* 0x000fd800078e020f */
/*02a0*/ @P0 BREAK B0 ; /* 0x0000000000000942 */
/* 0x000fe20003800000 */
/*02b0*/ @P0 BRA 0x340 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*02c0*/ LDG.E R4, [R6.64] ; /* 0x0000000406047981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R5, [R2.64+-0x4] ; /* 0xfffffc0402057981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ ISETP.GT.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x004fda0003f04270 */
/*02f0*/ @P0 BREAK B0 ; /* 0x0000000000000942 */
/* 0x000fe20003800000 */
/*0300*/ @P0 BRA 0x340 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0310*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0320*/ IADD3 R11, R9, 0x1, RZ ; /* 0x00000001090b7810 */
/* 0x000fe20007ffe0ff */
/*0330*/ BRA 0x1a0 ; /* 0xfffffe6000007947 */
/* 0x000fea000383ffff */
/*0340*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0350*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0360*/ ISETP.NE.AND P1, PT, R13.reuse, c[0x0][0x174], PT ; /* 0x00005d000d007a0c */
/* 0x040fe40003f25270 */
/*0370*/ ISETP.EQ.OR P0, PT, R13, c[0x0][0x174], !P0 ; /* 0x00005d000d007a0c */
/* 0x000fda0004702670 */
/*0380*/ @P0 BRA 0x400 ; /* 0x0000007000000947 */
/* 0x000fea0003800000 */
/*0390*/ IADD3 R10, R9, -0x1, RZ ; /* 0xffffffff090a7810 */
/* 0x000fe20007ffe0ff */
/*03a0*/ LDG.E R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ea8000c1e1900 */
/*03b0*/ IMAD.WIDE R4, R10, R15, c[0x0][0x160] ; /* 0x000058000a047625 */
/* 0x000fcc00078e020f */
/*03c0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ ISETP.GT.AND P0, PT, R5, R8, PT ; /* 0x000000080500720c */
/* 0x004fda0003f04270 */
/*03e0*/ @P0 IADD3 R12, R13, 0x1, RZ ; /* 0x000000010d0c0810 */
/* 0x000fe20007ffe0ff */
/*03f0*/ @P0 BRA 0x190 ; /* 0xfffffd9000000947 */
/* 0x000fea000383ffff */
/*0400*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0410*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0420*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x170], PT ; /* 0x00005c0009007a0c */
/* 0x000fe20003f06270 */
/*0430*/ BSSY B1, 0x4e0 ; /* 0x000000a000017945 */
/* 0x000fd80003800000 */
/*0440*/ @P0 BRA 0x4a0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0450*/ @!P1 BRA 0x4c0 ; /* 0x0000006000009947 */
/* 0x000fea0003800000 */
/*0460*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1900 */
/*0470*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea4000c1e1900 */
/*0480*/ ISETP.GT.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x004fda0003f04270 */
/*0490*/ @!P0 BRA 0x4c0 ; /* 0x0000002000008947 */
/* 0x000fea0003800000 */
/*04a0*/ IADD3 R13, R13, 0x1, RZ ; /* 0x000000010d0d7810 */
/* 0x000fe20007ffe0ff */
/*04b0*/ BRA 0x4d0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*04c0*/ IADD3 R9, R9, 0x1, RZ ; /* 0x0000000109097810 */
/* 0x000fe40007ffe0ff */
/*04d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04e0*/ IMAD.WIDE R2, R0, R15, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fc800078e020f */
/*04f0*/ IMAD.WIDE R4, R0, R15, c[0x0][0x180] ; /* 0x0000600000047625 */
/* 0x000fe200078e020f */
/*0500*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x000fe8000c101904 */
/*0510*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x000fe2000c101904 */
/*0520*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0530*/ BRA 0x530; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // Version single file
#include <stdlib.h>
#include <stdio.h>
// Pour pouvoir experimenter les performances avec les différents types
// FMT Permet d'avoir un % adapté pour le printf et donc de pas avoir de warning
#define TYPE int
#define FMT "d"
typedef struct
{
int x ;
int y ;
} Point ;
__global__ void PathBig(TYPE * CudaVecteurA, TYPE * CudaVecteurB, int sizeA , int sizeB, int * CudaDiagBx, int * CudaDiagAy, int nbthread, int NbWindows)
{
//Initialisation diagolane
CudaDiagBx[0] = CudaDiagAy[0] = 0 ;
CudaDiagBx[NbWindows] = sizeB ;
CudaDiagAy[NbWindows] = sizeA ;
int nth = threadIdx.x; // On explore le nth diagonale
Point K, P, Q ;
int px , py ;
TYPE * A = CudaVecteurA ;
TYPE * B = CudaVecteurB ;
int offset ;
int numDiag = (nth+1) * nbthread -1 ; // Les tableaux vont de 0 à N-1
if (numDiag > sizeA)
{
K.x = numDiag - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = numDiag - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = numDiag ;
P.x = numDiag ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
px = Q.x ; py = Q.y ;
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ // v = A[Q.y] ;
py ++ ;
}
else
{ // v = B[Q.x] ;
px ++ ;
}
// printf("Analyse Diagonale Point de Sortie ref %d - M %" FMT " Q (A Q.y %d) (B Q.x %d) rv.x %d rv.y %d\n",i,v,Q.y,Q.x,rv->x,rv->y) ;
CudaDiagBx[nth+1] = px ; CudaDiagAy[nth+1] = py ;
break ; // Pour simuler passage au thread suivant
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
} // End of PathBig
__global__ void MergeBig_k(TYPE * CudaVecteurA, TYPE * CudaVecteurB, TYPE * CudaVecteurC, int * CudaDiagAy, int * CudaDiagBx , int nbthread)
{
// int i = threadIdx.x ; // On renge le Ieme element
int i = blockIdx.x * blockDim.x + threadIdx.x; // On range le ieme elet
int diag = (i / nbthread) ; // Dans quel fenêtre est-il ?
int indC = nbthread * diag ;
TYPE *A = CudaVecteurA+CudaDiagAy[diag] ;
TYPE *B = CudaVecteurB+CudaDiagBx[diag] ;
TYPE *M = CudaVecteurC + indC ;
int sizeA = CudaDiagAy[diag+1]-CudaDiagAy[diag] ;
int sizeB = CudaDiagBx[diag+1]-CudaDiagBx[diag] ;
Point K, P, Q;
int offset ;
i = i % nbthread ; // On recadre i dans le nouvel espace
if (i >= (sizeA + sizeB)) { return ; } // On gère les ébordements
if (i > sizeA)
{
K.x = i - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = i - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = i ;
P.x = i ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ M[i] = A[Q.y] ; }
else
{ M[i] = B[Q.x] ; }
break ;
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
}
int check(char * msg, int Nb, TYPE * pto)
{
TYPE * pt1 = pto ;
TYPE * pt2 = pto + 1 ;
int i ;
for (i = 0 ; i < Nb-1 ; i ++)
{
if (*pt1 > *pt2)
{ printf("Check %s pour %d - Erreur en position %d %" FMT " > %" FMT " \n", msg, Nb, i, *pt1, *pt2) ;
return i ;
}
pt1 ++ ; pt2 ++ ;
}
printf("Premiere valeur de %s = %" FMT ", deuxième valeur = %" FMT ", troisième valeur = %" FMT " \n", msg, pto[0], pto[1], pto[2]);
printf("Check %s pour %d est OK \n", msg, Nb) ;
return 0 ;
}
void Affiche(char * tabMsg, TYPE * ptBuffer, int NB)
{
TYPE * pt = ptBuffer ;
for ( int k = 0 ; k < NB ; k++ , pt ++)
{ printf(" - %s[%03d] = %6" FMT, tabMsg, k , *pt) ;
if ((k % 5) == (4))
{ printf("\n") ; }
}
printf("\n") ;
}
int main(int argc, char ** argv)
{
//déclaration
int sizeA = 1600;
int sizeB = 1000 ;
int sizeM = sizeA + sizeB ;
TYPE* A;
TYPE* B ;
TYPE* M;
float m1;
cudaEvent_t Start; cudaEvent_t Stop; cudaEventCreate(&Start) ; cudaEventCreate(&Stop) ;
//allocation
if ((A = (TYPE *) malloc(sizeA * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurA\n") ; exit (1) ; }
if ((B= (TYPE *) malloc(sizeB * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurB\n") ; exit (1) ; }
if ((M= (TYPE *) malloc(sizeM * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurM\n") ; exit (1) ; }
//initialisation
srand(1925);
A[0] = B[0] = rand()%100;
for (int i =1; i<sizeA; i++)
{
A[i]=A[i-1]+rand()%100;
}
for (int i =1; i<sizeB; i++)
{
B[i]=B[i-1]+rand()%100;
}
//Declarations
cudaError_t errCuda;
TYPE * CudaVecteurA = NULL ;
TYPE * CudaVecteurB = NULL ;
TYPE * CudaVecteurM = NULL ;
int nbthread = 512; // a verifier
int NbDiagonale = (sizeA + sizeB) / nbthread ;
int NbWindows = NbDiagonale ;
NbWindows += (((sizeA + sizeB) % nbthread) == 0)?0:1 ; // si (SizeA + SizeB) % nbthread == 0 alors nbWindows = 0 sinon = 1
int * CudaDiagBx = NULL ;
int * CudaDiagAy = NULL ;
//Allocation
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaVecteurA, sizeA * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurA - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout) ; exit (1) ; } // cleanup a rajouter pour plus propre
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaVecteurB, sizeB * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurB - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; } // cleanup a rajouter pour plus propre
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaVecteurM, sizeM * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurM - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaDiagBx, (NbWindows + 1) * sizeof(int))))
{ printf("PB allocation CudaDiagBx - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaDiagAy, (NbWindows + 1)* sizeof(int))))
{ printf("PB allocation CudaDiagAy - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (cudaSuccess != cudaMemcpy(CudaVecteurA, A, sizeA * sizeof(TYPE), cudaMemcpyHostToDevice))
{ printf("PB copie host A -> cuda A \n") ; fflush(stdout); exit(2) ; }
if (cudaSuccess != cudaMemcpy(CudaVecteurB, B, sizeB * sizeof(TYPE), cudaMemcpyHostToDevice))
{ printf("PB copie host B -> cuda B \n") ; fflush(stdout); exit(2) ; }
cudaEventRecord(Start);
PathBig<<<1,NbDiagonale>>>(CudaVecteurA, CudaVecteurB, sizeA , sizeB, CudaDiagBx, CudaDiagAy, nbthread,NbWindows) ;
int nbBlock = (sizeA+sizeB) / 1024 ;
nbBlock += ((sizeA+sizeB) % 1024)?1:0 ;
if (sizeM <1024)
{
printf("La fonction MergeBig ne peut pas être prise en compte car sizeA+sizeB <1024");
exit(2);
}
else { MergeBig_k<<<nbBlock,1024>>> (CudaVecteurA, CudaVecteurB, CudaVecteurM, CudaDiagAy, CudaDiagBx, nbthread) ;}
if (cudaSuccess != cudaMemcpy(M, CudaVecteurM, sizeM * sizeof(TYPE), cudaMemcpyDeviceToHost))
{ printf("PB copie cuda M -> host M \n") ; fflush(stdout); exit(2) ; }
cudaEventRecord(Stop) ;
check((char *)"Check tableau M après", sizeM, M);
cudaEventElapsedTime(&m1, Start, Stop) ;
printf("Duree %f s\n",m1/1000) ;
//Affiche ("Tableau M", M, sizeM);
//Free
if (M != NULL ){ free(M); }
if (A != NULL) { free(A) ; }
if (B != NULL) { free(B) ; }
if (CudaVecteurA != NULL) { cudaFree(CudaVecteurA) ; CudaVecteurA = NULL ; }
if (CudaVecteurB != NULL) { cudaFree(CudaVecteurB) ; CudaVecteurB = NULL ; }
if (CudaVecteurM != NULL) { cudaFree(CudaVecteurM) ; CudaVecteurM = NULL ; }
if (CudaDiagAy != NULL) { cudaFree(CudaDiagAy) ; CudaDiagAy = NULL ; }
if (CudaDiagBx != NULL) { cudaFree(CudaDiagBx) ; CudaDiagBx = NULL ; }
return 0 ;
} | .file "tmpxft_000f4cf6_00000000-6_question2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Check %s pour %d - Erreur en position %d %d > %d \n"
.align 8
.LC1:
.string "Premiere valeur de %s = %d, deuxi\303\250me valeur = %d, troisi\303\250me valeur = %d \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Check %s pour %d est OK \n"
.text
.globl _Z5checkPciPi
.type _Z5checkPciPi, @function
_Z5checkPciPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %ebx
cmpl $1, %esi
jle .L4
leal -1(%rsi), %ecx
movl $0, %r8d
.L7:
movl (%rdx,%r8,4), %r9d
movl 4(%rdx,%r8,4), %eax
cmpl %eax, %r9d
jg .L10
addq $1, %r8
cmpq %rcx, %r8
jne .L7
.L4:
movl (%rdx), %ecx
movl 8(%rdx), %r9d
movl 4(%rdx), %r8d
movq %rbp, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movq %rbp, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
.L3:
movl %r12d, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %r8d, %r12d
subq $8, %rsp
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
movl %ebx, %ecx
movq %rbp, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 32
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z5checkPciPi, .-_Z5checkPciPi
.section .rodata.str1.1
.LC3:
.string " - %s[%03d] = %6d"
.LC4:
.string "\n"
.text
.globl _Z7AffichePcPii
.type _Z7AffichePcPii, @function
_Z7AffichePcPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
testl %edx, %edx
jle .L12
movq %rdi, %r12
movq %rsi, %r13
movslq %edx, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r14
leaq .LC4(%rip), %r15
jmp .L14
.L13:
addq $1, %rbx
cmpq %rbp, %rbx
je .L12
.L14:
movl %ebx, %ecx
movl 0(%r13,%rbx,4), %r8d
movq %r12, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %edx
movl %ebx, %eax
subl %edx, %eax
cmpl $4, %eax
jne .L13
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L12:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7AffichePcPii, .-_Z7AffichePcPii
.globl _Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii
.type _Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii, @function
_Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7PathBigPiS_iiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii, .-_Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii
.globl _Z7PathBigPiS_iiS_S_ii
.type _Z7PathBigPiS_iiS_S_ii, @function
_Z7PathBigPiS_iiS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7PathBigPiS_iiS_S_ii, .-_Z7PathBigPiS_iiS_S_ii
.globl _Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i
.type _Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i, @function
_Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10MergeBig_kPiS_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i, .-_Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i
.globl _Z10MergeBig_kPiS_S_S_S_i
.type _Z10MergeBig_kPiS_S_S_S_i, @function
_Z10MergeBig_kPiS_S_S_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10MergeBig_kPiS_S_S_S_i, .-_Z10MergeBig_kPiS_S_S_S_i
.section .rodata.str1.1
.LC5:
.string "PB allocation VecteurA\n"
.LC6:
.string "PB allocation VecteurB\n"
.LC7:
.string "PB allocation VecteurM\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "PB allocation CudaVecteurA - %d - %s \n"
.align 8
.LC9:
.string "PB allocation CudaVecteurB - %d - %s \n"
.align 8
.LC10:
.string "PB allocation CudaVecteurM - %d - %s \n"
.align 8
.LC11:
.string "PB allocation CudaDiagBx - %d - %s \n"
.align 8
.LC12:
.string "PB allocation CudaDiagAy - %d - %s \n"
.section .rodata.str1.1
.LC13:
.string "PB copie host A -> cuda A \n"
.LC14:
.string "PB copie host B -> cuda B \n"
.LC15:
.string "PB copie cuda M -> host M \n"
.LC16:
.string "Check tableau M apr\303\250s"
.LC18:
.string "Duree %f s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $6400, %edi
call malloc@PLT
testq %rax, %rax
je .L58
movq %rax, %r13
movl $4000, %edi
call malloc@PLT
movq %rax, %r14
testq %rax, %rax
je .L59
movl $10400, %edi
call malloc@PLT
movq %rax, %r15
testq %rax, %rax
je .L60
movl $1925, %edi
call srand@PLT
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %ecx
subl %ecx, %eax
movl %eax, (%r14)
movl %eax, 0(%r13)
movq %r13, %rbx
leaq 6396(%r13), %r12
.L37:
movl (%rbx), %ebp
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl %ebp, %eax
movl %eax, 4(%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L37
movq %r14, %rbx
leaq 3996(%r14), %r12
.L38:
movl (%rbx), %ebp
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl %ebp, %eax
movl %eax, 4(%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L38
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
leaq 24(%rsp), %rdi
movl $6400, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L61
leaq 32(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L62
leaq 40(%rsp), %rdi
movl $10400, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
leaq 48(%rsp), %rdi
movl $28, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L64
leaq 56(%rsp), %rdi
movl $28, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L65
movl $1, %ecx
movl $6400, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L66
movl $1, %ecx
movl $4000, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L67
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $5, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L46:
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $3, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L47:
movl $2, %ecx
movl $10400, %edx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L70
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq %r15, %rdx
movl $2600, %esi
leaq .LC16(%rip), %rdi
call _Z5checkPciPi
leaq 76(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 76(%rsp), %xmm0
divss .LC17(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .L49
call cudaFree@PLT
movq $0, 24(%rsp)
.L49:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .L50
call cudaFree@PLT
movq $0, 32(%rsp)
.L50:
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .L51
call cudaFree@PLT
movq $0, 40(%rsp)
.L51:
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .L52
call cudaFree@PLT
movq $0, 56(%rsp)
.L52:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .L53
call cudaFree@PLT
.L53:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L71
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $1, %edi
call exit@PLT
.L62:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $1, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $1, %edi
call exit@PLT
.L64:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $1, %edi
call exit@PLT
.L65:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $1, %edi
call exit@PLT
.L66:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $2, %edi
call exit@PLT
.L67:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $2, %edi
call exit@PLT
.L68:
pushq $6
.cfi_def_cfa_offset 168
pushq $512
.cfi_def_cfa_offset 176
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movl $1000, %ecx
movl $1600, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L46
.L69:
movl $512, %r9d
movq 48(%rsp), %r8
movq 56(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i
jmp .L47
.L70:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $2, %edi
call exit@PLT
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z10MergeBig_kPiS_S_S_S_i"
.LC20:
.string "_Z7PathBigPiS_iiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z10MergeBig_kPiS_S_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z7PathBigPiS_iiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // Version single file
#include <stdlib.h>
#include <stdio.h>
// Pour pouvoir experimenter les performances avec les différents types
// FMT Permet d'avoir un % adapté pour le printf et donc de pas avoir de warning
#define TYPE int
#define FMT "d"
typedef struct
{
int x ;
int y ;
} Point ;
__global__ void PathBig(TYPE * CudaVecteurA, TYPE * CudaVecteurB, int sizeA , int sizeB, int * CudaDiagBx, int * CudaDiagAy, int nbthread, int NbWindows)
{
//Initialisation diagolane
CudaDiagBx[0] = CudaDiagAy[0] = 0 ;
CudaDiagBx[NbWindows] = sizeB ;
CudaDiagAy[NbWindows] = sizeA ;
int nth = threadIdx.x; // On explore le nth diagonale
Point K, P, Q ;
int px , py ;
TYPE * A = CudaVecteurA ;
TYPE * B = CudaVecteurB ;
int offset ;
int numDiag = (nth+1) * nbthread -1 ; // Les tableaux vont de 0 à N-1
if (numDiag > sizeA)
{
K.x = numDiag - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = numDiag - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = numDiag ;
P.x = numDiag ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
px = Q.x ; py = Q.y ;
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ // v = A[Q.y] ;
py ++ ;
}
else
{ // v = B[Q.x] ;
px ++ ;
}
// printf("Analyse Diagonale Point de Sortie ref %d - M %" FMT " Q (A Q.y %d) (B Q.x %d) rv.x %d rv.y %d\n",i,v,Q.y,Q.x,rv->x,rv->y) ;
CudaDiagBx[nth+1] = px ; CudaDiagAy[nth+1] = py ;
break ; // Pour simuler passage au thread suivant
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
} // End of PathBig
__global__ void MergeBig_k(TYPE * CudaVecteurA, TYPE * CudaVecteurB, TYPE * CudaVecteurC, int * CudaDiagAy, int * CudaDiagBx , int nbthread)
{
// int i = threadIdx.x ; // On renge le Ieme element
int i = blockIdx.x * blockDim.x + threadIdx.x; // On range le ieme elet
int diag = (i / nbthread) ; // Dans quel fenêtre est-il ?
int indC = nbthread * diag ;
TYPE *A = CudaVecteurA+CudaDiagAy[diag] ;
TYPE *B = CudaVecteurB+CudaDiagBx[diag] ;
TYPE *M = CudaVecteurC + indC ;
int sizeA = CudaDiagAy[diag+1]-CudaDiagAy[diag] ;
int sizeB = CudaDiagBx[diag+1]-CudaDiagBx[diag] ;
Point K, P, Q;
int offset ;
i = i % nbthread ; // On recadre i dans le nouvel espace
if (i >= (sizeA + sizeB)) { return ; } // On gère les ébordements
if (i > sizeA)
{
K.x = i - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = i - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = i ;
P.x = i ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ M[i] = A[Q.y] ; }
else
{ M[i] = B[Q.x] ; }
break ;
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
}
int check(char * msg, int Nb, TYPE * pto)
{
TYPE * pt1 = pto ;
TYPE * pt2 = pto + 1 ;
int i ;
for (i = 0 ; i < Nb-1 ; i ++)
{
if (*pt1 > *pt2)
{ printf("Check %s pour %d - Erreur en position %d %" FMT " > %" FMT " \n", msg, Nb, i, *pt1, *pt2) ;
return i ;
}
pt1 ++ ; pt2 ++ ;
}
printf("Premiere valeur de %s = %" FMT ", deuxième valeur = %" FMT ", troisième valeur = %" FMT " \n", msg, pto[0], pto[1], pto[2]);
printf("Check %s pour %d est OK \n", msg, Nb) ;
return 0 ;
}
void Affiche(char * tabMsg, TYPE * ptBuffer, int NB)
{
TYPE * pt = ptBuffer ;
for ( int k = 0 ; k < NB ; k++ , pt ++)
{ printf(" - %s[%03d] = %6" FMT, tabMsg, k , *pt) ;
if ((k % 5) == (4))
{ printf("\n") ; }
}
printf("\n") ;
}
int main(int argc, char ** argv)
{
//déclaration
int sizeA = 1600;
int sizeB = 1000 ;
int sizeM = sizeA + sizeB ;
TYPE* A;
TYPE* B ;
TYPE* M;
float m1;
cudaEvent_t Start; cudaEvent_t Stop; cudaEventCreate(&Start) ; cudaEventCreate(&Stop) ;
//allocation
if ((A = (TYPE *) malloc(sizeA * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurA\n") ; exit (1) ; }
if ((B= (TYPE *) malloc(sizeB * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurB\n") ; exit (1) ; }
if ((M= (TYPE *) malloc(sizeM * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurM\n") ; exit (1) ; }
//initialisation
srand(1925);
A[0] = B[0] = rand()%100;
for (int i =1; i<sizeA; i++)
{
A[i]=A[i-1]+rand()%100;
}
for (int i =1; i<sizeB; i++)
{
B[i]=B[i-1]+rand()%100;
}
//Declarations
cudaError_t errCuda;
TYPE * CudaVecteurA = NULL ;
TYPE * CudaVecteurB = NULL ;
TYPE * CudaVecteurM = NULL ;
int nbthread = 512; // a verifier
int NbDiagonale = (sizeA + sizeB) / nbthread ;
int NbWindows = NbDiagonale ;
NbWindows += (((sizeA + sizeB) % nbthread) == 0)?0:1 ; // si (SizeA + SizeB) % nbthread == 0 alors nbWindows = 0 sinon = 1
int * CudaDiagBx = NULL ;
int * CudaDiagAy = NULL ;
//Allocation
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaVecteurA, sizeA * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurA - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout) ; exit (1) ; } // cleanup a rajouter pour plus propre
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaVecteurB, sizeB * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurB - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; } // cleanup a rajouter pour plus propre
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaVecteurM, sizeM * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurM - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaDiagBx, (NbWindows + 1) * sizeof(int))))
{ printf("PB allocation CudaDiagBx - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (cudaSuccess != (errCuda = cudaMalloc((void**)&CudaDiagAy, (NbWindows + 1)* sizeof(int))))
{ printf("PB allocation CudaDiagAy - %d - %s \n",errCuda,cudaGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (cudaSuccess != cudaMemcpy(CudaVecteurA, A, sizeA * sizeof(TYPE), cudaMemcpyHostToDevice))
{ printf("PB copie host A -> cuda A \n") ; fflush(stdout); exit(2) ; }
if (cudaSuccess != cudaMemcpy(CudaVecteurB, B, sizeB * sizeof(TYPE), cudaMemcpyHostToDevice))
{ printf("PB copie host B -> cuda B \n") ; fflush(stdout); exit(2) ; }
cudaEventRecord(Start);
PathBig<<<1,NbDiagonale>>>(CudaVecteurA, CudaVecteurB, sizeA , sizeB, CudaDiagBx, CudaDiagAy, nbthread,NbWindows) ;
int nbBlock = (sizeA+sizeB) / 1024 ;
nbBlock += ((sizeA+sizeB) % 1024)?1:0 ;
if (sizeM <1024)
{
printf("La fonction MergeBig ne peut pas être prise en compte car sizeA+sizeB <1024");
exit(2);
}
else { MergeBig_k<<<nbBlock,1024>>> (CudaVecteurA, CudaVecteurB, CudaVecteurM, CudaDiagAy, CudaDiagBx, nbthread) ;}
if (cudaSuccess != cudaMemcpy(M, CudaVecteurM, sizeM * sizeof(TYPE), cudaMemcpyDeviceToHost))
{ printf("PB copie cuda M -> host M \n") ; fflush(stdout); exit(2) ; }
cudaEventRecord(Stop) ;
check((char *)"Check tableau M après", sizeM, M);
cudaEventElapsedTime(&m1, Start, Stop) ;
printf("Duree %f s\n",m1/1000) ;
//Affiche ("Tableau M", M, sizeM);
//Free
if (M != NULL ){ free(M); }
if (A != NULL) { free(A) ; }
if (B != NULL) { free(B) ; }
if (CudaVecteurA != NULL) { cudaFree(CudaVecteurA) ; CudaVecteurA = NULL ; }
if (CudaVecteurB != NULL) { cudaFree(CudaVecteurB) ; CudaVecteurB = NULL ; }
if (CudaVecteurM != NULL) { cudaFree(CudaVecteurM) ; CudaVecteurM = NULL ; }
if (CudaDiagAy != NULL) { cudaFree(CudaDiagAy) ; CudaDiagAy = NULL ; }
if (CudaDiagBx != NULL) { cudaFree(CudaDiagBx) ; CudaDiagBx = NULL ; }
return 0 ;
} | // Version single file
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// Pour pouvoir experimenter les performances avec les différents types
// FMT Permet d'avoir un % adapté pour le printf et donc de pas avoir de warning
#define TYPE int
#define FMT "d"
typedef struct
{
int x ;
int y ;
} Point ;
__global__ void PathBig(TYPE * CudaVecteurA, TYPE * CudaVecteurB, int sizeA , int sizeB, int * CudaDiagBx, int * CudaDiagAy, int nbthread, int NbWindows)
{
//Initialisation diagolane
CudaDiagBx[0] = CudaDiagAy[0] = 0 ;
CudaDiagBx[NbWindows] = sizeB ;
CudaDiagAy[NbWindows] = sizeA ;
int nth = threadIdx.x; // On explore le nth diagonale
Point K, P, Q ;
int px , py ;
TYPE * A = CudaVecteurA ;
TYPE * B = CudaVecteurB ;
int offset ;
int numDiag = (nth+1) * nbthread -1 ; // Les tableaux vont de 0 à N-1
if (numDiag > sizeA)
{
K.x = numDiag - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = numDiag - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = numDiag ;
P.x = numDiag ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
px = Q.x ; py = Q.y ;
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ // v = A[Q.y] ;
py ++ ;
}
else
{ // v = B[Q.x] ;
px ++ ;
}
// printf("Analyse Diagonale Point de Sortie ref %d - M %" FMT " Q (A Q.y %d) (B Q.x %d) rv.x %d rv.y %d\n",i,v,Q.y,Q.x,rv->x,rv->y) ;
CudaDiagBx[nth+1] = px ; CudaDiagAy[nth+1] = py ;
break ; // Pour simuler passage au thread suivant
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
} // End of PathBig
__global__ void MergeBig_k(TYPE * CudaVecteurA, TYPE * CudaVecteurB, TYPE * CudaVecteurC, int * CudaDiagAy, int * CudaDiagBx , int nbthread)
{
// int i = threadIdx.x ; // On renge le Ieme element
int i = blockIdx.x * blockDim.x + threadIdx.x; // On range le ieme elet
int diag = (i / nbthread) ; // Dans quel fenêtre est-il ?
int indC = nbthread * diag ;
TYPE *A = CudaVecteurA+CudaDiagAy[diag] ;
TYPE *B = CudaVecteurB+CudaDiagBx[diag] ;
TYPE *M = CudaVecteurC + indC ;
int sizeA = CudaDiagAy[diag+1]-CudaDiagAy[diag] ;
int sizeB = CudaDiagBx[diag+1]-CudaDiagBx[diag] ;
Point K, P, Q;
int offset ;
i = i % nbthread ; // On recadre i dans le nouvel espace
if (i >= (sizeA + sizeB)) { return ; } // On gère les ébordements
if (i > sizeA)
{
K.x = i - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = i - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = i ;
P.x = i ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ M[i] = A[Q.y] ; }
else
{ M[i] = B[Q.x] ; }
break ;
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
}
int check(char * msg, int Nb, TYPE * pto)
{
TYPE * pt1 = pto ;
TYPE * pt2 = pto + 1 ;
int i ;
for (i = 0 ; i < Nb-1 ; i ++)
{
if (*pt1 > *pt2)
{ printf("Check %s pour %d - Erreur en position %d %" FMT " > %" FMT " \n", msg, Nb, i, *pt1, *pt2) ;
return i ;
}
pt1 ++ ; pt2 ++ ;
}
printf("Premiere valeur de %s = %" FMT ", deuxième valeur = %" FMT ", troisième valeur = %" FMT " \n", msg, pto[0], pto[1], pto[2]);
printf("Check %s pour %d est OK \n", msg, Nb) ;
return 0 ;
}
void Affiche(char * tabMsg, TYPE * ptBuffer, int NB)
{
TYPE * pt = ptBuffer ;
for ( int k = 0 ; k < NB ; k++ , pt ++)
{ printf(" - %s[%03d] = %6" FMT, tabMsg, k , *pt) ;
if ((k % 5) == (4))
{ printf("\n") ; }
}
printf("\n") ;
}
int main(int argc, char ** argv)
{
//déclaration
int sizeA = 1600;
int sizeB = 1000 ;
int sizeM = sizeA + sizeB ;
TYPE* A;
TYPE* B ;
TYPE* M;
float m1;
hipEvent_t Start; hipEvent_t Stop; hipEventCreate(&Start) ; hipEventCreate(&Stop) ;
//allocation
if ((A = (TYPE *) malloc(sizeA * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurA\n") ; exit (1) ; }
if ((B= (TYPE *) malloc(sizeB * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurB\n") ; exit (1) ; }
if ((M= (TYPE *) malloc(sizeM * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurM\n") ; exit (1) ; }
//initialisation
srand(1925);
A[0] = B[0] = rand()%100;
for (int i =1; i<sizeA; i++)
{
A[i]=A[i-1]+rand()%100;
}
for (int i =1; i<sizeB; i++)
{
B[i]=B[i-1]+rand()%100;
}
//Declarations
hipError_t errCuda;
TYPE * CudaVecteurA = NULL ;
TYPE * CudaVecteurB = NULL ;
TYPE * CudaVecteurM = NULL ;
int nbthread = 512; // a verifier
int NbDiagonale = (sizeA + sizeB) / nbthread ;
int NbWindows = NbDiagonale ;
NbWindows += (((sizeA + sizeB) % nbthread) == 0)?0:1 ; // si (SizeA + SizeB) % nbthread == 0 alors nbWindows = 0 sinon = 1
int * CudaDiagBx = NULL ;
int * CudaDiagAy = NULL ;
//Allocation
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaVecteurA, sizeA * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurA - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout) ; exit (1) ; } // cleanup a rajouter pour plus propre
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaVecteurB, sizeB * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurB - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; } // cleanup a rajouter pour plus propre
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaVecteurM, sizeM * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurM - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaDiagBx, (NbWindows + 1) * sizeof(int))))
{ printf("PB allocation CudaDiagBx - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaDiagAy, (NbWindows + 1)* sizeof(int))))
{ printf("PB allocation CudaDiagAy - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (hipSuccess != hipMemcpy(CudaVecteurA, A, sizeA * sizeof(TYPE), hipMemcpyHostToDevice))
{ printf("PB copie host A -> cuda A \n") ; fflush(stdout); exit(2) ; }
if (hipSuccess != hipMemcpy(CudaVecteurB, B, sizeB * sizeof(TYPE), hipMemcpyHostToDevice))
{ printf("PB copie host B -> cuda B \n") ; fflush(stdout); exit(2) ; }
hipEventRecord(Start);
PathBig<<<1,NbDiagonale>>>(CudaVecteurA, CudaVecteurB, sizeA , sizeB, CudaDiagBx, CudaDiagAy, nbthread,NbWindows) ;
int nbBlock = (sizeA+sizeB) / 1024 ;
nbBlock += ((sizeA+sizeB) % 1024)?1:0 ;
if (sizeM <1024)
{
printf("La fonction MergeBig ne peut pas être prise en compte car sizeA+sizeB <1024");
exit(2);
}
else { MergeBig_k<<<nbBlock,1024>>> (CudaVecteurA, CudaVecteurB, CudaVecteurM, CudaDiagAy, CudaDiagBx, nbthread) ;}
if (hipSuccess != hipMemcpy(M, CudaVecteurM, sizeM * sizeof(TYPE), hipMemcpyDeviceToHost))
{ printf("PB copie cuda M -> host M \n") ; fflush(stdout); exit(2) ; }
hipEventRecord(Stop) ;
check((char *)"Check tableau M après", sizeM, M);
hipEventElapsedTime(&m1, Start, Stop) ;
printf("Duree %f s\n",m1/1000) ;
//Affiche ("Tableau M", M, sizeM);
//Free
if (M != NULL ){ free(M); }
if (A != NULL) { free(A) ; }
if (B != NULL) { free(B) ; }
if (CudaVecteurA != NULL) { hipFree(CudaVecteurA) ; CudaVecteurA = NULL ; }
if (CudaVecteurB != NULL) { hipFree(CudaVecteurB) ; CudaVecteurB = NULL ; }
if (CudaVecteurM != NULL) { hipFree(CudaVecteurM) ; CudaVecteurM = NULL ; }
if (CudaDiagAy != NULL) { hipFree(CudaDiagAy) ; CudaDiagAy = NULL ; }
if (CudaDiagBx != NULL) { hipFree(CudaDiagBx) ; CudaDiagBx = NULL ; }
return 0 ;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // Version single file
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// Pour pouvoir experimenter les performances avec les différents types
// FMT Permet d'avoir un % adapté pour le printf et donc de pas avoir de warning
#define TYPE int
#define FMT "d"
typedef struct
{
int x ;
int y ;
} Point ;
__global__ void PathBig(TYPE * CudaVecteurA, TYPE * CudaVecteurB, int sizeA , int sizeB, int * CudaDiagBx, int * CudaDiagAy, int nbthread, int NbWindows)
{
//Initialisation diagolane
CudaDiagBx[0] = CudaDiagAy[0] = 0 ;
CudaDiagBx[NbWindows] = sizeB ;
CudaDiagAy[NbWindows] = sizeA ;
int nth = threadIdx.x; // On explore le nth diagonale
Point K, P, Q ;
int px , py ;
TYPE * A = CudaVecteurA ;
TYPE * B = CudaVecteurB ;
int offset ;
int numDiag = (nth+1) * nbthread -1 ; // Les tableaux vont de 0 à N-1
if (numDiag > sizeA)
{
K.x = numDiag - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = numDiag - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = numDiag ;
P.x = numDiag ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
px = Q.x ; py = Q.y ;
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ // v = A[Q.y] ;
py ++ ;
}
else
{ // v = B[Q.x] ;
px ++ ;
}
// printf("Analyse Diagonale Point de Sortie ref %d - M %" FMT " Q (A Q.y %d) (B Q.x %d) rv.x %d rv.y %d\n",i,v,Q.y,Q.x,rv->x,rv->y) ;
CudaDiagBx[nth+1] = px ; CudaDiagAy[nth+1] = py ;
break ; // Pour simuler passage au thread suivant
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
} // End of PathBig
__global__ void MergeBig_k(TYPE * CudaVecteurA, TYPE * CudaVecteurB, TYPE * CudaVecteurC, int * CudaDiagAy, int * CudaDiagBx , int nbthread)
{
// int i = threadIdx.x ; // On renge le Ieme element
int i = blockIdx.x * blockDim.x + threadIdx.x; // On range le ieme elet
int diag = (i / nbthread) ; // Dans quel fenêtre est-il ?
int indC = nbthread * diag ;
TYPE *A = CudaVecteurA+CudaDiagAy[diag] ;
TYPE *B = CudaVecteurB+CudaDiagBx[diag] ;
TYPE *M = CudaVecteurC + indC ;
int sizeA = CudaDiagAy[diag+1]-CudaDiagAy[diag] ;
int sizeB = CudaDiagBx[diag+1]-CudaDiagBx[diag] ;
Point K, P, Q;
int offset ;
i = i % nbthread ; // On recadre i dans le nouvel espace
if (i >= (sizeA + sizeB)) { return ; } // On gère les ébordements
if (i > sizeA)
{
K.x = i - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = i - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = i ;
P.x = i ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ M[i] = A[Q.y] ; }
else
{ M[i] = B[Q.x] ; }
break ;
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
}
int check(char * msg, int Nb, TYPE * pto)
{
TYPE * pt1 = pto ;
TYPE * pt2 = pto + 1 ;
int i ;
for (i = 0 ; i < Nb-1 ; i ++)
{
if (*pt1 > *pt2)
{ printf("Check %s pour %d - Erreur en position %d %" FMT " > %" FMT " \n", msg, Nb, i, *pt1, *pt2) ;
return i ;
}
pt1 ++ ; pt2 ++ ;
}
printf("Premiere valeur de %s = %" FMT ", deuxième valeur = %" FMT ", troisième valeur = %" FMT " \n", msg, pto[0], pto[1], pto[2]);
printf("Check %s pour %d est OK \n", msg, Nb) ;
return 0 ;
}
void Affiche(char * tabMsg, TYPE * ptBuffer, int NB)
{
TYPE * pt = ptBuffer ;
for ( int k = 0 ; k < NB ; k++ , pt ++)
{ printf(" - %s[%03d] = %6" FMT, tabMsg, k , *pt) ;
if ((k % 5) == (4))
{ printf("\n") ; }
}
printf("\n") ;
}
int main(int argc, char ** argv)
{
//déclaration
int sizeA = 1600;
int sizeB = 1000 ;
int sizeM = sizeA + sizeB ;
TYPE* A;
TYPE* B ;
TYPE* M;
float m1;
hipEvent_t Start; hipEvent_t Stop; hipEventCreate(&Start) ; hipEventCreate(&Stop) ;
//allocation
if ((A = (TYPE *) malloc(sizeA * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurA\n") ; exit (1) ; }
if ((B= (TYPE *) malloc(sizeB * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurB\n") ; exit (1) ; }
if ((M= (TYPE *) malloc(sizeM * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurM\n") ; exit (1) ; }
//initialisation
srand(1925);
A[0] = B[0] = rand()%100;
for (int i =1; i<sizeA; i++)
{
A[i]=A[i-1]+rand()%100;
}
for (int i =1; i<sizeB; i++)
{
B[i]=B[i-1]+rand()%100;
}
//Declarations
hipError_t errCuda;
TYPE * CudaVecteurA = NULL ;
TYPE * CudaVecteurB = NULL ;
TYPE * CudaVecteurM = NULL ;
int nbthread = 512; // a verifier
int NbDiagonale = (sizeA + sizeB) / nbthread ;
int NbWindows = NbDiagonale ;
NbWindows += (((sizeA + sizeB) % nbthread) == 0)?0:1 ; // si (SizeA + SizeB) % nbthread == 0 alors nbWindows = 0 sinon = 1
int * CudaDiagBx = NULL ;
int * CudaDiagAy = NULL ;
//Allocation
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaVecteurA, sizeA * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurA - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout) ; exit (1) ; } // cleanup a rajouter pour plus propre
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaVecteurB, sizeB * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurB - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; } // cleanup a rajouter pour plus propre
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaVecteurM, sizeM * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurM - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaDiagBx, (NbWindows + 1) * sizeof(int))))
{ printf("PB allocation CudaDiagBx - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaDiagAy, (NbWindows + 1)* sizeof(int))))
{ printf("PB allocation CudaDiagAy - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (hipSuccess != hipMemcpy(CudaVecteurA, A, sizeA * sizeof(TYPE), hipMemcpyHostToDevice))
{ printf("PB copie host A -> cuda A \n") ; fflush(stdout); exit(2) ; }
if (hipSuccess != hipMemcpy(CudaVecteurB, B, sizeB * sizeof(TYPE), hipMemcpyHostToDevice))
{ printf("PB copie host B -> cuda B \n") ; fflush(stdout); exit(2) ; }
hipEventRecord(Start);
PathBig<<<1,NbDiagonale>>>(CudaVecteurA, CudaVecteurB, sizeA , sizeB, CudaDiagBx, CudaDiagAy, nbthread,NbWindows) ;
int nbBlock = (sizeA+sizeB) / 1024 ;
nbBlock += ((sizeA+sizeB) % 1024)?1:0 ;
if (sizeM <1024)
{
printf("La fonction MergeBig ne peut pas être prise en compte car sizeA+sizeB <1024");
exit(2);
}
else { MergeBig_k<<<nbBlock,1024>>> (CudaVecteurA, CudaVecteurB, CudaVecteurM, CudaDiagAy, CudaDiagBx, nbthread) ;}
if (hipSuccess != hipMemcpy(M, CudaVecteurM, sizeM * sizeof(TYPE), hipMemcpyDeviceToHost))
{ printf("PB copie cuda M -> host M \n") ; fflush(stdout); exit(2) ; }
hipEventRecord(Stop) ;
check((char *)"Check tableau M après", sizeM, M);
hipEventElapsedTime(&m1, Start, Stop) ;
printf("Duree %f s\n",m1/1000) ;
//Affiche ("Tableau M", M, sizeM);
//Free
if (M != NULL ){ free(M); }
if (A != NULL) { free(A) ; }
if (B != NULL) { free(B) ; }
if (CudaVecteurA != NULL) { hipFree(CudaVecteurA) ; CudaVecteurA = NULL ; }
if (CudaVecteurB != NULL) { hipFree(CudaVecteurB) ; CudaVecteurB = NULL ; }
if (CudaVecteurM != NULL) { hipFree(CudaVecteurM) ; CudaVecteurM = NULL ; }
if (CudaDiagAy != NULL) { hipFree(CudaDiagAy) ; CudaDiagAy = NULL ; }
if (CudaDiagBx != NULL) { hipFree(CudaDiagBx) ; CudaDiagBx = NULL ; }
return 0 ;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7PathBigPiS_iiS_S_ii
.globl _Z7PathBigPiS_iiS_S_ii
.p2align 8
.type _Z7PathBigPiS_iiS_S_ii,@function
_Z7PathBigPiS_iiS_S_ii:
s_clause 0x1
s_load_b128 s[12:15], s[0:1], 0x20
s_load_b256 s[4:11], s[0:1], 0x0
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v6, 1, v0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v6, s14, -1
s_ashr_i32 s1, s15, 31
s_mov_b32 s0, s15
v_mov_b32_e32 v1, s9
s_lshl_b64 s[0:1], s[0:1], 2
global_store_b32 v5, v5, s[12:13]
s_add_u32 s2, s10, s0
v_subrev_nc_u32_e32 v2, s8, v0
v_cmp_lt_i32_e32 vcc_lo, s8, v0
s_addc_u32 s3, s11, s1
s_add_u32 s0, s12, s0
s_addc_u32 s1, s13, s1
s_add_u32 s14, s6, -4
v_dual_cndmask_b32 v7, 0, v2 :: v_dual_mov_b32 v2, s8
s_clause 0x1
global_store_b32 v5, v5, s[10:11]
global_store_b32 v5, v1, s[2:3]
v_min_i32_e32 v1, s8, v0
s_addc_u32 s16, s7, -1
v_mov_b32_e32 v8, v7
s_mov_b32 s15, 0
global_store_b32 v5, v2, s[0:1]
s_branch .LBB0_2
.LBB0_1:
s_or_b32 exec_lo, exec_lo, s18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, exec_lo, s1
s_or_b32 s15, s1, s15
s_and_not1_b32 s1, s3, exec_lo
s_and_b32 s0, s0, exec_lo
s_and_not1_b32 s2, s2, exec_lo
s_and_b32 s17, s17, exec_lo
s_or_b32 s3, s1, s0
s_or_b32 s2, s2, s17
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execz .LBB0_16
.LBB0_2:
v_mov_b32_e32 v9, v1
s_mov_b32 s18, 0
s_branch .LBB0_7
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s26
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s0, s25, exec_lo
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s26, exec_lo, -1
s_and_b32 s25, vcc_lo, exec_lo
s_or_not1_b32 s1, s0, exec_lo
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s24
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s0, s20, exec_lo
s_and_b32 s20, s26, exec_lo
s_and_not1_b32 s19, s19, exec_lo
s_or_b32 s20, s0, s20
s_and_not1_b32 s0, s22, exec_lo
s_and_b32 s22, s25, exec_lo
s_and_b32 s1, s1, exec_lo
s_or_b32 s22, s0, s22
s_or_b32 s19, s19, s1
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s23
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s0, exec_lo, s19
v_mov_b32_e32 v1, v9
s_or_b32 s18, s0, s18
v_mov_b32_e32 v9, v4
s_and_not1_b32 s0, s21, exec_lo
s_and_b32 s1, s20, exec_lo
s_and_not1_b32 s17, s17, exec_lo
s_and_b32 s23, s22, exec_lo
s_or_b32 s21, s0, s1
s_or_b32 s17, s17, s23
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB0_14
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v9, v7
s_or_b32 s20, s20, exec_lo
s_and_not1_b32 s22, s22, exec_lo
s_or_b32 s19, s19, exec_lo
v_sub_nc_u32_e32 v1, 0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v0, v0, v1
v_lshrrev_b32_e32 v1, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v0, v9, v1
v_add_nc_u32_e32 v2, v1, v8
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s0, s9, v2
s_and_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s23, s0
s_cbranch_execz .LBB0_6
v_cmp_eq_u32_e32 vcc_lo, s8, v0
v_cmp_eq_u32_e64 s0, 0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s0, vcc_lo, s0
s_xor_b32 s24, s0, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s1, s24
s_cbranch_execz .LBB0_10
v_mov_b32_e32 v1, v5
v_ashrrev_i32_e32 v3, 31, v2
s_and_not1_b32 s0, s0, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[0:1]
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s14, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s16, v4, vcc_lo
global_load_b32 v1, v[10:11], off
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v3
s_and_b32 s24, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s0, s0, s24
.LBB0_10:
s_or_b32 exec_lo, exec_lo, s1
s_mov_b32 s1, -1
s_mov_b32 s26, -1
s_and_saveexec_b32 s24, s0
s_cbranch_execz .LBB0_5
v_cmp_ne_u32_e64 s0, s9, v2
v_cmp_ne_u32_e64 s1, 0, v0
v_cmp_eq_u32_e32 vcc_lo, s9, v2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s25, s0, s1
s_mov_b32 s0, -1
s_and_saveexec_b32 s1, s25
s_cbranch_execz .LBB0_4
v_add_nc_u32_e32 v4, -1, v0
v_ashrrev_i32_e32 v3, 31, v2
s_mov_b32 s25, -1
s_mov_b32 s26, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[10:11], 2, v[4:5]
v_lshlrev_b64 v[12:13], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v10, s0, s4, v10
v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v12, s0, s6, v12
v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
global_load_b32 v1, v[10:11], off
global_load_b32 v3, v[12:13], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v1, v3
s_cbranch_execz .LBB0_3
v_add_nc_u32_e32 v8, 1, v2
s_xor_b32 s25, exec_lo, -1
s_branch .LBB0_3
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s18
s_mov_b32 s1, -1
s_xor_b32 s0, s17, -1
s_and_saveexec_b32 s18, s21
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s18, exec_lo, s18
s_cbranch_execz .LBB0_1
v_add_nc_u32_e32 v7, 1, v0
s_xor_b32 s1, exec_lo, -1
s_branch .LBB0_1
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s15
v_cmp_gt_i32_e32 vcc_lo, s8, v0
s_mov_b32 s8, -1
s_mov_b32 s1, 0
s_and_saveexec_b32 s0, vcc_lo
s_cbranch_execz .LBB0_20
s_mov_b32 s8, 0
s_and_saveexec_b32 s1, s3
s_cbranch_execz .LBB0_19
v_mov_b32_e32 v1, 0
v_ashrrev_i32_e32 v3, 31, v2
s_or_b32 s2, s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[0:1]
v_lshlrev_b64 v[7:8], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v3, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b32 v1, v[3:4], off
global_load_b32 v3, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v1, v3
s_and_b32 s8, vcc_lo, exec_lo
.LBB0_19:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s1, s2, exec_lo
s_or_not1_b32 s8, s8, exec_lo
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s8
v_add_nc_u32_e32 v1, 1, v2
s_and_not1_b32 s1, s1, exec_lo
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s1
v_dual_mov_b32 v1, v2 :: v_dual_add_nc_u32 v0, 1, v0
s_or_b32 exec_lo, exec_lo, s0
v_lshlrev_b32_e32 v2, 2, v6
s_clause 0x1
global_store_b32 v2, v1, s[10:11]
global_store_b32 v2, v0, s[12:13]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7PathBigPiS_iiS_S_ii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 48
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 27
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7PathBigPiS_iiS_S_ii, .Lfunc_end0-_Z7PathBigPiS_iiS_S_ii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10MergeBig_kPiS_S_S_S_i
.globl _Z10MergeBig_kPiS_S_S_S_i
.p2align 8
.type _Z10MergeBig_kPiS_S_S_S_i,@function
_Z10MergeBig_kPiS_S_S_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x28
s_load_b32 s3, s[0:1], 0x3c
s_waitcnt lgkmcnt(0)
s_ashr_i32 s4, s2, 31
s_and_b32 s3, s3, 0xffff
s_add_i32 s5, s2, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s5, s5, s4
v_cvt_f32_u32_e32 v1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v1, 0x4f7ffffe, v1
v_cvt_u32_f32_e32 v3, v1
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_sub_i32 s3, 0, s5
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s3, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_mul_hi_u32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v1, v2
v_xor_b32_e32 v4, v4, v2
v_xor_b32_e32 v2, s4, v2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v3, v0
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v3, v0, s5
v_sub_nc_u32_e32 v3, v4, v3
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v5, s5, v3
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s5, v3
v_add_nc_u32_e32 v4, 1, v0
s_load_b128 s[4:7], s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
v_xor_b32_e32 v0, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v0, v2
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, v3, 4
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v4, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v4, vcc_lo
v_add_co_u32 v9, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v12, vcc_lo
v_add_co_u32 v11, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
global_load_b32 v3, v[5:6], off
global_load_b32 v5, v[7:8], off
global_load_b32 v4, v[9:10], off
global_load_b32 v6, v[11:12], off
v_mul_lo_u32 v0, v2, s2
s_mov_b32 s5, 0
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v1, v0
s_waitcnt vmcnt(1)
v_sub_nc_u32_e32 v12, v4, v3
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v13, v6, v5
v_add_nc_u32_e32 v1, v13, v12
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v2, v1
s_cbranch_execz .LBB1_26
s_load_b128 s[8:11], s[0:1], 0x0
v_ashrrev_i32_e32 v6, 31, v5
v_ashrrev_i32_e32 v4, 31, v3
v_sub_nc_u32_e32 v1, v2, v12
v_cmp_gt_i32_e32 vcc_lo, v2, v12
v_min_i32_e32 v19, v2, v12
v_lshlrev_b64 v[5:6], 2, v[5:6]
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_cndmask_b32_e32 v16, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v17, v16
s_waitcnt lgkmcnt(0)
v_add_co_u32 v10, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v11, vcc_lo, s11, v6, vcc_lo
v_add_co_u32 v1, vcc_lo, s8, v3
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v14, vcc_lo, v10, -4
v_add_co_ci_u32_e32 v15, vcc_lo, -1, v11, vcc_lo
s_branch .LBB1_3
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s3, exec_lo, s3
s_or_b32 s5, s3, s5
s_and_not1_b32 s3, s6, exec_lo
s_and_b32 s2, s2, exec_lo
s_and_not1_b32 s4, s4, exec_lo
s_and_b32 s7, s7, exec_lo
s_or_b32 s6, s3, s2
s_or_b32 s4, s4, s7
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execz .LBB1_17
.LBB1_3:
v_mov_b32_e32 v18, v19
s_mov_b32 s8, 0
s_branch .LBB1_8
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s2, s15, exec_lo
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s16, exec_lo, -1
s_and_b32 s15, vcc_lo, exec_lo
s_or_not1_b32 s3, s2, exec_lo
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s14
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 s2, s10, exec_lo
s_and_b32 s10, s16, exec_lo
s_and_not1_b32 s9, s9, exec_lo
s_or_b32 s10, s2, s10
s_and_not1_b32 s2, s12, exec_lo
s_and_b32 s12, s15, exec_lo
s_and_b32 s3, s3, exec_lo
s_or_b32 s12, s2, s12
s_or_b32 s9, s9, s3
.LBB1_7:
s_or_b32 exec_lo, exec_lo, s13
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s2, exec_lo, s9
v_dual_mov_b32 v19, v18 :: v_dual_mov_b32 v18, v7
s_or_b32 s8, s2, s8
s_and_not1_b32 s2, s11, exec_lo
s_and_b32 s3, s10, exec_lo
s_and_not1_b32 s7, s7, exec_lo
s_and_b32 s13, s12, exec_lo
s_or_b32 s11, s2, s3
s_or_b32 s7, s7, s13
s_and_not1_b32 exec_lo, exec_lo, s8
s_cbranch_execz .LBB1_15
.LBB1_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v18, v16
s_or_b32 s10, s10, exec_lo
s_and_not1_b32 s12, s12, exec_lo
s_or_b32 s9, s9, exec_lo
v_sub_nc_u32_e32 v4, 0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v3, v3, v4
v_lshrrev_b32_e32 v7, 1, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v3, v18, v7
v_add_nc_u32_e32 v5, v7, v17
v_cmp_lt_i32_e32 vcc_lo, -1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_le_i32_e64 s2, v5, v13
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s13, s2
s_cbranch_execz .LBB1_7
v_cmp_eq_u32_e32 vcc_lo, v3, v12
v_cmp_eq_u32_e64 s2, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_xor_b32 s14, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s14
s_cbranch_execz .LBB1_11
v_mov_b32_e32 v4, v8
v_ashrrev_i32_e32 v6, 31, v5
s_and_not1_b32 s2, s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[19:20], 2, v[3:4]
v_lshlrev_b64 v[21:22], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v19, vcc_lo, v1, v19
v_add_co_ci_u32_e32 v20, vcc_lo, v9, v20, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v21, vcc_lo, v14, v21
v_add_co_ci_u32_e32 v22, vcc_lo, v15, v22, vcc_lo
global_load_b32 v4, v[19:20], off
global_load_b32 v6, v[21:22], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v6
s_and_b32 s14, vcc_lo, exec_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 s2, s2, s14
.LBB1_11:
s_or_b32 exec_lo, exec_lo, s3
s_mov_b32 s3, -1
s_mov_b32 s16, -1
s_and_saveexec_b32 s14, s2
s_cbranch_execz .LBB1_6
v_cmp_ne_u32_e64 s2, v5, v13
v_cmp_ne_u32_e64 s3, v18, v7
v_cmp_eq_u32_e32 vcc_lo, v5, v13
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 s15, s3, s2
s_mov_b32 s2, -1
s_and_saveexec_b32 s3, s15
s_cbranch_execz .LBB1_5
v_add_nc_u32_e32 v7, -1, v3
v_ashrrev_i32_e32 v6, 31, v5
s_mov_b32 s15, -1
s_mov_b32 s16, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[19:20], 2, v[7:8]
v_lshlrev_b64 v[21:22], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v19, s2, v1, v19
v_add_co_ci_u32_e64 v20, s2, v9, v20, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v21, s2, v10, v21
v_add_co_ci_u32_e64 v22, s2, v11, v22, s2
global_load_b32 v4, v[19:20], off
global_load_b32 v6, v[21:22], off
s_waitcnt vmcnt(0)
v_cmpx_gt_i32_e64 v4, v6
s_cbranch_execz .LBB1_4
v_add_nc_u32_e32 v17, 1, v5
s_xor_b32 s15, exec_lo, -1
s_branch .LBB1_4
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s8
s_mov_b32 s3, -1
s_xor_b32 s2, s7, -1
s_and_saveexec_b32 s8, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s8, exec_lo, s8
s_cbranch_execz .LBB1_2
v_add_nc_u32_e32 v16, 1, v3
s_xor_b32 s3, exec_lo, -1
s_branch .LBB1_2
.LBB1_17:
s_or_b32 exec_lo, exec_lo, s5
s_mov_b32 s5, -1
s_mov_b32 s3, 0
s_mov_b32 s2, exec_lo
v_cmpx_lt_i32_e64 v3, v12
s_cbranch_execz .LBB1_21
s_mov_b32 s5, 0
s_and_saveexec_b32 s3, s6
s_cbranch_execz .LBB1_20
v_mov_b32_e32 v4, 0
v_ashrrev_i32_e32 v6, 31, v5
s_or_b32 s4, s4, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[7:8], 2, v[3:4]
v_lshlrev_b64 v[12:13], 2, v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v1, v7
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v12, vcc_lo, v10, v12
v_add_co_ci_u32_e32 v13, vcc_lo, v11, v13, vcc_lo
global_load_b32 v4, v[6:7], off
global_load_b32 v6, v[12:13], off
s_waitcnt vmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, v4, v6
s_and_b32 s5, vcc_lo, exec_lo
.LBB1_20:
s_or_b32 exec_lo, exec_lo, s3
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 s3, s4, exec_lo
s_or_not1_b32 s5, s5, exec_lo
.LBB1_21:
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s5
v_ashrrev_i32_e32 v6, 31, v5
s_and_not1_b32 s3, s3, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[5:6]
v_add_co_u32 v6, vcc_lo, v10, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, v11, v5, vcc_lo
s_or_b32 exec_lo, exec_lo, s2
s_and_saveexec_b32 s2, s3
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v6, vcc_lo, v1, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, v9, v4, vcc_lo
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v4, v[6:7], off
s_load_b64 s[0:1], s[0:1], 0x10
v_ashrrev_i32_e32 v1, 31, v0
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, v2
v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v4, off
.LBB1_26:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10MergeBig_kPiS_S_S_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 23
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10MergeBig_kPiS_S_S_S_i, .Lfunc_end1-_Z10MergeBig_kPiS_S_S_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 44
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 48
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7PathBigPiS_iiS_S_ii
.private_segment_fixed_size: 0
.sgpr_count: 29
.sgpr_spill_count: 0
.symbol: _Z7PathBigPiS_iiS_S_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10MergeBig_kPiS_S_S_S_i
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z10MergeBig_kPiS_S_S_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 23
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // Version single file
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
// Pour pouvoir experimenter les performances avec les différents types
// FMT Permet d'avoir un % adapté pour le printf et donc de pas avoir de warning
#define TYPE int
#define FMT "d"
typedef struct
{
int x ;
int y ;
} Point ;
__global__ void PathBig(TYPE * CudaVecteurA, TYPE * CudaVecteurB, int sizeA , int sizeB, int * CudaDiagBx, int * CudaDiagAy, int nbthread, int NbWindows)
{
//Initialisation diagolane
CudaDiagBx[0] = CudaDiagAy[0] = 0 ;
CudaDiagBx[NbWindows] = sizeB ;
CudaDiagAy[NbWindows] = sizeA ;
int nth = threadIdx.x; // On explore le nth diagonale
Point K, P, Q ;
int px , py ;
TYPE * A = CudaVecteurA ;
TYPE * B = CudaVecteurB ;
int offset ;
int numDiag = (nth+1) * nbthread -1 ; // Les tableaux vont de 0 à N-1
if (numDiag > sizeA)
{
K.x = numDiag - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = numDiag - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = numDiag ;
P.x = numDiag ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
px = Q.x ; py = Q.y ;
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ // v = A[Q.y] ;
py ++ ;
}
else
{ // v = B[Q.x] ;
px ++ ;
}
// printf("Analyse Diagonale Point de Sortie ref %d - M %" FMT " Q (A Q.y %d) (B Q.x %d) rv.x %d rv.y %d\n",i,v,Q.y,Q.x,rv->x,rv->y) ;
CudaDiagBx[nth+1] = px ; CudaDiagAy[nth+1] = py ;
break ; // Pour simuler passage au thread suivant
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
} // End of PathBig
__global__ void MergeBig_k(TYPE * CudaVecteurA, TYPE * CudaVecteurB, TYPE * CudaVecteurC, int * CudaDiagAy, int * CudaDiagBx , int nbthread)
{
// int i = threadIdx.x ; // On renge le Ieme element
int i = blockIdx.x * blockDim.x + threadIdx.x; // On range le ieme elet
int diag = (i / nbthread) ; // Dans quel fenêtre est-il ?
int indC = nbthread * diag ;
TYPE *A = CudaVecteurA+CudaDiagAy[diag] ;
TYPE *B = CudaVecteurB+CudaDiagBx[diag] ;
TYPE *M = CudaVecteurC + indC ;
int sizeA = CudaDiagAy[diag+1]-CudaDiagAy[diag] ;
int sizeB = CudaDiagBx[diag+1]-CudaDiagBx[diag] ;
Point K, P, Q;
int offset ;
i = i % nbthread ; // On recadre i dans le nouvel espace
if (i >= (sizeA + sizeB)) { return ; } // On gère les ébordements
if (i > sizeA)
{
K.x = i - sizeA ; K.y = sizeA ;
P.x = sizeA ; P.y = i - sizeA ;
}
else // x ~ horizontal
{
K.x = 0 ; K.y = i ;
P.x = i ; P.y = 0 ;
}
while (1)
{
offset = abs(K.y - P.y) / 2 ;
Q.x = K.x + offset ; Q.y = K.y - offset ;
if ( (Q.y >= 0) && (Q.x <= sizeB) &&
( (Q.y == sizeA) || (Q.x == 0) || (A[Q.y] > B[Q.x -1])) )
{
if ((Q.x == sizeB) || (Q.y == 0) || (A[Q.y-1] <= B[Q.x]))
{
if ((Q.y < sizeA) && ((Q.x == sizeB) || (A[Q.y] <= B[Q.x])))
{ M[i] = A[Q.y] ; }
else
{ M[i] = B[Q.x] ; }
break ;
}
else
{ K.x = Q.x + 1 ; K.y = Q.y - 1 ; }
}
else
{ P.x = Q.x -1 ; P.y = Q.y + 1 ; }
}
}
int check(char * msg, int Nb, TYPE * pto)
{
TYPE * pt1 = pto ;
TYPE * pt2 = pto + 1 ;
int i ;
for (i = 0 ; i < Nb-1 ; i ++)
{
if (*pt1 > *pt2)
{ printf("Check %s pour %d - Erreur en position %d %" FMT " > %" FMT " \n", msg, Nb, i, *pt1, *pt2) ;
return i ;
}
pt1 ++ ; pt2 ++ ;
}
printf("Premiere valeur de %s = %" FMT ", deuxième valeur = %" FMT ", troisième valeur = %" FMT " \n", msg, pto[0], pto[1], pto[2]);
printf("Check %s pour %d est OK \n", msg, Nb) ;
return 0 ;
}
void Affiche(char * tabMsg, TYPE * ptBuffer, int NB)
{
TYPE * pt = ptBuffer ;
for ( int k = 0 ; k < NB ; k++ , pt ++)
{ printf(" - %s[%03d] = %6" FMT, tabMsg, k , *pt) ;
if ((k % 5) == (4))
{ printf("\n") ; }
}
printf("\n") ;
}
int main(int argc, char ** argv)
{
//déclaration
int sizeA = 1600;
int sizeB = 1000 ;
int sizeM = sizeA + sizeB ;
TYPE* A;
TYPE* B ;
TYPE* M;
float m1;
hipEvent_t Start; hipEvent_t Stop; hipEventCreate(&Start) ; hipEventCreate(&Stop) ;
//allocation
if ((A = (TYPE *) malloc(sizeA * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurA\n") ; exit (1) ; }
if ((B= (TYPE *) malloc(sizeB * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurB\n") ; exit (1) ; }
if ((M= (TYPE *) malloc(sizeM * sizeof(TYPE))) == NULL)
{ printf("PB allocation VecteurM\n") ; exit (1) ; }
//initialisation
srand(1925);
A[0] = B[0] = rand()%100;
for (int i =1; i<sizeA; i++)
{
A[i]=A[i-1]+rand()%100;
}
for (int i =1; i<sizeB; i++)
{
B[i]=B[i-1]+rand()%100;
}
//Declarations
hipError_t errCuda;
TYPE * CudaVecteurA = NULL ;
TYPE * CudaVecteurB = NULL ;
TYPE * CudaVecteurM = NULL ;
int nbthread = 512; // a verifier
int NbDiagonale = (sizeA + sizeB) / nbthread ;
int NbWindows = NbDiagonale ;
NbWindows += (((sizeA + sizeB) % nbthread) == 0)?0:1 ; // si (SizeA + SizeB) % nbthread == 0 alors nbWindows = 0 sinon = 1
int * CudaDiagBx = NULL ;
int * CudaDiagAy = NULL ;
//Allocation
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaVecteurA, sizeA * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurA - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout) ; exit (1) ; } // cleanup a rajouter pour plus propre
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaVecteurB, sizeB * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurB - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; } // cleanup a rajouter pour plus propre
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaVecteurM, sizeM * sizeof(TYPE))))
{ printf("PB allocation CudaVecteurM - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaDiagBx, (NbWindows + 1) * sizeof(int))))
{ printf("PB allocation CudaDiagBx - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (hipSuccess != (errCuda = hipMalloc((void**)&CudaDiagAy, (NbWindows + 1)* sizeof(int))))
{ printf("PB allocation CudaDiagAy - %d - %s \n",errCuda,hipGetErrorName(errCuda)) ; fflush(stdout); exit (1) ; }
if (hipSuccess != hipMemcpy(CudaVecteurA, A, sizeA * sizeof(TYPE), hipMemcpyHostToDevice))
{ printf("PB copie host A -> cuda A \n") ; fflush(stdout); exit(2) ; }
if (hipSuccess != hipMemcpy(CudaVecteurB, B, sizeB * sizeof(TYPE), hipMemcpyHostToDevice))
{ printf("PB copie host B -> cuda B \n") ; fflush(stdout); exit(2) ; }
hipEventRecord(Start);
PathBig<<<1,NbDiagonale>>>(CudaVecteurA, CudaVecteurB, sizeA , sizeB, CudaDiagBx, CudaDiagAy, nbthread,NbWindows) ;
int nbBlock = (sizeA+sizeB) / 1024 ;
nbBlock += ((sizeA+sizeB) % 1024)?1:0 ;
if (sizeM <1024)
{
printf("La fonction MergeBig ne peut pas être prise en compte car sizeA+sizeB <1024");
exit(2);
}
else { MergeBig_k<<<nbBlock,1024>>> (CudaVecteurA, CudaVecteurB, CudaVecteurM, CudaDiagAy, CudaDiagBx, nbthread) ;}
if (hipSuccess != hipMemcpy(M, CudaVecteurM, sizeM * sizeof(TYPE), hipMemcpyDeviceToHost))
{ printf("PB copie cuda M -> host M \n") ; fflush(stdout); exit(2) ; }
hipEventRecord(Stop) ;
check((char *)"Check tableau M après", sizeM, M);
hipEventElapsedTime(&m1, Start, Stop) ;
printf("Duree %f s\n",m1/1000) ;
//Affiche ("Tableau M", M, sizeM);
//Free
if (M != NULL ){ free(M); }
if (A != NULL) { free(A) ; }
if (B != NULL) { free(B) ; }
if (CudaVecteurA != NULL) { hipFree(CudaVecteurA) ; CudaVecteurA = NULL ; }
if (CudaVecteurB != NULL) { hipFree(CudaVecteurB) ; CudaVecteurB = NULL ; }
if (CudaVecteurM != NULL) { hipFree(CudaVecteurM) ; CudaVecteurM = NULL ; }
if (CudaDiagAy != NULL) { hipFree(CudaDiagAy) ; CudaDiagAy = NULL ; }
if (CudaDiagBx != NULL) { hipFree(CudaDiagBx) ; CudaDiagBx = NULL ; }
return 0 ;
} | .text
.file "question2.hip"
.globl _Z22__device_stub__PathBigPiS_iiS_S_ii # -- Begin function _Z22__device_stub__PathBigPiS_iiS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__PathBigPiS_iiS_S_ii,@function
_Z22__device_stub__PathBigPiS_iiS_S_ii: # @_Z22__device_stub__PathBigPiS_iiS_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7PathBigPiS_iiS_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z22__device_stub__PathBigPiS_iiS_S_ii, .Lfunc_end0-_Z22__device_stub__PathBigPiS_iiS_S_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__MergeBig_kPiS_S_S_S_i # -- Begin function _Z25__device_stub__MergeBig_kPiS_S_S_S_i
.p2align 4, 0x90
.type _Z25__device_stub__MergeBig_kPiS_S_S_S_i,@function
_Z25__device_stub__MergeBig_kPiS_S_S_S_i: # @_Z25__device_stub__MergeBig_kPiS_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10MergeBig_kPiS_S_S_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z25__device_stub__MergeBig_kPiS_S_S_S_i, .Lfunc_end1-_Z25__device_stub__MergeBig_kPiS_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z5checkPciPi # -- Begin function _Z5checkPciPi
.p2align 4, 0x90
.type _Z5checkPciPi,@function
_Z5checkPciPi: # @_Z5checkPciPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %r14d
movq %rdi, %r15
cmpl $2, %esi
jl .LBB2_5
# %bb.1: # %.lr.ph.preheader
leal -1(%r14), %eax
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdx,%rbx,4), %r8d
movl 4(%rdx,%rbx,4), %r9d
cmpl %r9d, %r8d
jg .LBB2_3
# %bb.4: # in Loop: Header=BB2_2 Depth=1
incq %rbx
cmpl %ebx, %eax
jne .LBB2_2
.LBB2_5: # %._crit_edge
movl (%rdx), %eax
movl 4(%rdx), %ecx
movl 8(%rdx), %r8d
xorl %ebx, %ebx
movl $.L.str.1, %edi
movq %r15, %rsi
movl %eax, %edx
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %r15, %rsi
movl %r14d, %edx
xorl %eax, %eax
callq printf
jmp .LBB2_6
.LBB2_3:
movl $.L.str, %edi
movq %r15, %rsi
movl %r14d, %edx
movl %ebx, %ecx
xorl %eax, %eax
callq printf
.LBB2_6:
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5checkPciPi, .Lfunc_end2-_Z5checkPciPi
.cfi_endproc
# -- End function
.globl _Z7AffichePcPii # -- Begin function _Z7AffichePcPii
.p2align 4, 0x90
.type _Z7AffichePcPii,@function
_Z7AffichePcPii: # @_Z7AffichePcPii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_6
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movl %edx, %r12d
movabsq $-3689348814741910323, %r13 # imm = 0xCCCCCCCCCCCCCCCD
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
incq %r15
cmpl %r15d, %r12d
je .LBB3_5
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r15, %rax
mulq %r13
shrq $2, %rdx
leal (%rdx,%rdx,4), %ebp
addl $4, %ebp
movl (%rbx,%r15,4), %ecx
movl $.L.str.3, %edi
movq %r14, %rsi
movl %r15d, %edx
xorl %eax, %eax
callq printf
cmpl %r15d, %ebp
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_4
.LBB3_5:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB3_6: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z7AffichePcPii, .Lfunc_end3-_Z7AffichePcPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $224, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 152(%rsp), %rdi
callq hipEventCreate
leaq 144(%rsp), %rdi
callq hipEventCreate
movl $6400, %edi # imm = 0x1900
callq malloc
testq %rax, %rax
je .LBB4_1
# %bb.3:
movq %rax, %rbx
movl $4000, %edi # imm = 0xFA0
callq malloc
testq %rax, %rax
je .LBB4_4
# %bb.5:
movq %rax, %r14
movl $10400, %edi # imm = 0x28A0
callq malloc
testq %rax, %rax
je .LBB4_6
# %bb.7:
movq %rax, %r15
movl $1925, %edi # imm = 0x785
callq srand
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14)
movl %eax, (%rbx)
movl $1, %r12d
.p2align 4, 0x90
.LBB4_8: # =>This Inner Loop Header: Depth=1
movl -4(%rbx,%r12,4), %ebp
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
addl %ebp, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $1600, %r12 # imm = 0x640
jne .LBB4_8
# %bb.9: # %.preheader.preheader
movl $1, %r12d
.p2align 4, 0x90
.LBB4_10: # %.preheader
# =>This Inner Loop Header: Depth=1
movl -4(%r14,%r12,4), %ebp
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
addl %ebp, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB4_10
# %bb.11:
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, 40(%rsp)
movq $0, 32(%rsp)
movq $0, 24(%rsp)
leaq 16(%rsp), %rdi
movl $6400, %esi # imm = 0x1900
callq hipMalloc
testl %eax, %eax
jne .LBB4_12
# %bb.14:
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
testl %eax, %eax
jne .LBB4_15
# %bb.16:
leaq 40(%rsp), %rdi
movl $10400, %esi # imm = 0x28A0
callq hipMalloc
testl %eax, %eax
jne .LBB4_17
# %bb.18:
leaq 32(%rsp), %rdi
movl $28, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_19
# %bb.20:
leaq 24(%rsp), %rdi
movl $28, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_21
# %bb.22:
movq 16(%rsp), %rdi
movl $6400, %edx # imm = 0x1900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_23
# %bb.25:
movq 8(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_26
# %bb.27:
movabsq $4294967297, %r12 # imm = 0x100000001
movq 152(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 4(%r12), %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_29
# %bb.28:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl $1600, 48(%rsp) # imm = 0x640
movl $1000, 4(%rsp) # imm = 0x3E8
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
movl $512, 140(%rsp) # imm = 0x200
movl $6, 136(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
leaq 112(%rsp), %rax
movq %rax, 192(%rsp)
leaq 104(%rsp), %rax
movq %rax, 200(%rsp)
leaq 140(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rax
movq %rax, 216(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z7PathBigPiS_iiS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_29:
leaq 2(%r12), %rdi
addq $1023, %r12 # imm = 0x3FF
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_31
# %bb.30:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 40(%rsp), %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
movq %rdi, 96(%rsp)
movl $512, 4(%rsp) # imm = 0x200
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z10MergeBig_kPiS_S_S_S_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_31:
movq 40(%rsp), %rsi
movl $10400, %edx # imm = 0x28A0
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_32
# %bb.33:
movq 144(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB4_34: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %r8d
movl 4(%r15,%r12,4), %r9d
cmpl %r9d, %r8d
jg .LBB4_35
# %bb.36: # in Loop: Header=BB4_34 Depth=1
incq %r12
cmpl $2599, %r12d # imm = 0xA27
jne .LBB4_34
# %bb.37: # %._crit_edge.i
movl (%r15), %edx
movl 4(%r15), %ecx
movl 8(%r15), %r8d
movl $.L.str.1, %edi
movl $.L.str.17, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $.L.str.17, %esi
movl $2600, %edx # imm = 0xA28
xorl %eax, %eax
callq printf
jmp .LBB4_38
.LBB4_35:
movl $.L.str, %edi
movl $.L.str.17, %esi
movl $2600, %edx # imm = 0xA28
movl %r12d, %ecx
xorl %eax, %eax
callq printf
.LBB4_38: # %_Z5checkPciPi.exit
movq 152(%rsp), %rsi
movq 144(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_40
# %bb.39:
callq hipFree
movq $0, 16(%rsp)
.LBB4_40:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_42
# %bb.41:
callq hipFree
movq $0, 8(%rsp)
.LBB4_42:
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_44
# %bb.43:
callq hipFree
movq $0, 40(%rsp)
.LBB4_44:
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_46
# %bb.45:
callq hipFree
movq $0, 24(%rsp)
.LBB4_46:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_48
# %bb.47:
callq hipFree
movq $0, 32(%rsp)
.LBB4_48:
xorl %eax, %eax
addq $224, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 272
movl $.Lstr.5, %edi
jmp .LBB4_2
.LBB4_4:
movl $.Lstr.4, %edi
jmp .LBB4_2
.LBB4_6:
movl $.Lstr.3, %edi
.LBB4_2:
callq puts@PLT
movl $1, %edi
callq exit
.LBB4_12:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorName
movl $.L.str.8, %edi
jmp .LBB4_13
.LBB4_15:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorName
movl $.L.str.9, %edi
jmp .LBB4_13
.LBB4_17:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorName
movl $.L.str.10, %edi
jmp .LBB4_13
.LBB4_19:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorName
movl $.L.str.11, %edi
jmp .LBB4_13
.LBB4_21:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorName
movl $.L.str.12, %edi
.LBB4_13:
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movq stdout(%rip), %rdi
callq fflush
movl $1, %edi
callq exit
.LBB4_23:
movl $.Lstr.2, %edi
jmp .LBB4_24
.LBB4_26:
movl $.Lstr.1, %edi
jmp .LBB4_24
.LBB4_32:
movl $.Lstr, %edi
.LBB4_24:
callq puts@PLT
movq stdout(%rip), %rdi
callq fflush
movl $2, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7PathBigPiS_iiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10MergeBig_kPiS_S_S_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7PathBigPiS_iiS_S_ii,@object # @_Z7PathBigPiS_iiS_S_ii
.section .rodata,"a",@progbits
.globl _Z7PathBigPiS_iiS_S_ii
.p2align 3, 0x0
_Z7PathBigPiS_iiS_S_ii:
.quad _Z22__device_stub__PathBigPiS_iiS_S_ii
.size _Z7PathBigPiS_iiS_S_ii, 8
.type _Z10MergeBig_kPiS_S_S_S_i,@object # @_Z10MergeBig_kPiS_S_S_S_i
.globl _Z10MergeBig_kPiS_S_S_S_i
.p2align 3, 0x0
_Z10MergeBig_kPiS_S_S_S_i:
.quad _Z25__device_stub__MergeBig_kPiS_S_S_S_i
.size _Z10MergeBig_kPiS_S_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Check %s pour %d - Erreur en position %d %d > %d \n"
.size .L.str, 51
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Premiere valeur de %s = %d, deuxi\303\250me valeur = %d, troisi\303\250me valeur = %d \n"
.size .L.str.1, 76
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Check %s pour %d est OK \n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " - %s[%03d] = %6d"
.size .L.str.3, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "PB allocation CudaVecteurA - %d - %s \n"
.size .L.str.8, 39
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "PB allocation CudaVecteurB - %d - %s \n"
.size .L.str.9, 39
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "PB allocation CudaVecteurM - %d - %s \n"
.size .L.str.10, 39
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "PB allocation CudaDiagBx - %d - %s \n"
.size .L.str.11, 37
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "PB allocation CudaDiagAy - %d - %s \n"
.size .L.str.12, 37
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Check tableau M apr\303\250s"
.size .L.str.17, 23
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Duree %f s\n"
.size .L.str.18, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7PathBigPiS_iiS_S_ii"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10MergeBig_kPiS_S_S_S_i"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "PB copie cuda M -> host M "
.size .Lstr, 27
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "PB copie host B -> cuda B "
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "PB copie host A -> cuda A "
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "PB allocation VecteurM"
.size .Lstr.3, 23
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "PB allocation VecteurB"
.size .Lstr.4, 23
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "PB allocation VecteurA"
.size .Lstr.5, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__PathBigPiS_iiS_S_ii
.addrsig_sym _Z25__device_stub__MergeBig_kPiS_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7PathBigPiS_iiS_S_ii
.addrsig_sym _Z10MergeBig_kPiS_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f4cf6_00000000-6_question2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Check %s pour %d - Erreur en position %d %d > %d \n"
.align 8
.LC1:
.string "Premiere valeur de %s = %d, deuxi\303\250me valeur = %d, troisi\303\250me valeur = %d \n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Check %s pour %d est OK \n"
.text
.globl _Z5checkPciPi
.type _Z5checkPciPi, @function
_Z5checkPciPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbp
movl %esi, %ebx
cmpl $1, %esi
jle .L4
leal -1(%rsi), %ecx
movl $0, %r8d
.L7:
movl (%rdx,%r8,4), %r9d
movl 4(%rdx,%r8,4), %eax
cmpl %eax, %r9d
jg .L10
addq $1, %r8
cmpq %rcx, %r8
jne .L7
.L4:
movl (%rdx), %ecx
movl 8(%rdx), %r9d
movl 4(%rdx), %r8d
movq %rbp, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %ecx
movq %rbp, %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r12d
.L3:
movl %r12d, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
movl %r8d, %r12d
subq $8, %rsp
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
movl %ebx, %ecx
movq %rbp, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 32
jmp .L3
.cfi_endproc
.LFE2057:
.size _Z5checkPciPi, .-_Z5checkPciPi
.section .rodata.str1.1
.LC3:
.string " - %s[%03d] = %6d"
.LC4:
.string "\n"
.text
.globl _Z7AffichePcPii
.type _Z7AffichePcPii, @function
_Z7AffichePcPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
testl %edx, %edx
jle .L12
movq %rdi, %r12
movq %rsi, %r13
movslq %edx, %rbp
movl $0, %ebx
leaq .LC3(%rip), %r14
leaq .LC4(%rip), %r15
jmp .L14
.L13:
addq $1, %rbx
cmpq %rbp, %rbx
je .L12
.L14:
movl %ebx, %ecx
movl 0(%r13,%rbx,4), %r8d
movq %r12, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movslq %ebx, %rax
imulq $1717986919, %rax, %rax
sarq $33, %rax
movl %ebx, %edx
sarl $31, %edx
subl %edx, %eax
leal (%rax,%rax,4), %edx
movl %ebx, %eax
subl %edx, %eax
cmpl $4, %eax
jne .L13
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.L12:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z7AffichePcPii, .-_Z7AffichePcPii
.globl _Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii
.type _Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii, @function
_Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii:
.LFB2084:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movq %r8, 16(%rsp)
movq %r9, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L22
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7PathBigPiS_iiS_S_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii, .-_Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii
.globl _Z7PathBigPiS_iiS_S_ii
.type _Z7PathBigPiS_iiS_S_ii, @function
_Z7PathBigPiS_iiS_S_ii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z7PathBigPiS_iiS_S_ii, .-_Z7PathBigPiS_iiS_S_ii
.globl _Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i
.type _Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i, @function
_Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L29
.L25:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L30
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z10MergeBig_kPiS_S_S_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L25
.L30:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i, .-_Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i
.globl _Z10MergeBig_kPiS_S_S_S_i
.type _Z10MergeBig_kPiS_S_S_S_i, @function
_Z10MergeBig_kPiS_S_S_S_i:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10MergeBig_kPiS_S_S_S_i, .-_Z10MergeBig_kPiS_S_S_S_i
.section .rodata.str1.1
.LC5:
.string "PB allocation VecteurA\n"
.LC6:
.string "PB allocation VecteurB\n"
.LC7:
.string "PB allocation VecteurM\n"
.section .rodata.str1.8
.align 8
.LC8:
.string "PB allocation CudaVecteurA - %d - %s \n"
.align 8
.LC9:
.string "PB allocation CudaVecteurB - %d - %s \n"
.align 8
.LC10:
.string "PB allocation CudaVecteurM - %d - %s \n"
.align 8
.LC11:
.string "PB allocation CudaDiagBx - %d - %s \n"
.align 8
.LC12:
.string "PB allocation CudaDiagAy - %d - %s \n"
.section .rodata.str1.1
.LC13:
.string "PB copie host A -> cuda A \n"
.LC14:
.string "PB copie host B -> cuda B \n"
.LC15:
.string "PB copie cuda M -> host M \n"
.LC16:
.string "Check tableau M apr\303\250s"
.LC18:
.string "Duree %f s\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
call cudaEventCreate@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
movl $6400, %edi
call malloc@PLT
testq %rax, %rax
je .L58
movq %rax, %r13
movl $4000, %edi
call malloc@PLT
movq %rax, %r14
testq %rax, %rax
je .L59
movl $10400, %edi
call malloc@PLT
movq %rax, %r15
testq %rax, %rax
je .L60
movl $1925, %edi
call srand@PLT
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %ecx
subl %ecx, %eax
movl %eax, (%r14)
movl %eax, 0(%r13)
movq %r13, %rbx
leaq 6396(%r13), %r12
.L37:
movl (%rbx), %ebp
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl %ebp, %eax
movl %eax, 4(%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L37
movq %r14, %rbx
leaq 3996(%r14), %r12
.L38:
movl (%rbx), %ebp
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
addl %ebp, %eax
movl %eax, 4(%rbx)
addq $4, %rbx
cmpq %r12, %rbx
jne .L38
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movq $0, 48(%rsp)
movq $0, 56(%rsp)
leaq 24(%rsp), %rdi
movl $6400, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L61
leaq 32(%rsp), %rdi
movl $4000, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L62
leaq 40(%rsp), %rdi
movl $10400, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L63
leaq 48(%rsp), %rdi
movl $28, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L64
leaq 56(%rsp), %rdi
movl $28, %esi
call cudaMalloc@PLT
movl %eax, %ebx
testl %eax, %eax
jne .L65
movl $1, %ecx
movl $6400, %edx
movq %r13, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L66
movl $1, %ecx
movl $4000, %edx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L67
movl $0, %esi
movq 8(%rsp), %rdi
call cudaEventRecord@PLT
movl $5, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L68
.L46:
movl $1024, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $3, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 76(%rsp), %rdx
movl $1, %ecx
movq 64(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L69
.L47:
movl $2, %ecx
movl $10400, %edx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L70
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movq %r15, %rdx
movl $2600, %esi
leaq .LC16(%rip), %rdi
call _Z5checkPciPi
leaq 76(%rsp), %rdi
movq 16(%rsp), %rdx
movq 8(%rsp), %rsi
call cudaEventElapsedTime@PLT
movss 76(%rsp), %xmm0
divss .LC17(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC18(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %r15, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .L49
call cudaFree@PLT
movq $0, 24(%rsp)
.L49:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .L50
call cudaFree@PLT
movq $0, 32(%rsp)
.L50:
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .L51
call cudaFree@PLT
movq $0, 40(%rsp)
.L51:
movq 56(%rsp), %rdi
testq %rdi, %rdi
je .L52
call cudaFree@PLT
movq $0, 56(%rsp)
.L52:
movq 48(%rsp), %rdi
testq %rdi, %rdi
je .L53
call cudaFree@PLT
.L53:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L71
movl $0, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L58:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L60:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L61:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $1, %edi
call exit@PLT
.L62:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $1, %edi
call exit@PLT
.L63:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $1, %edi
call exit@PLT
.L64:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $1, %edi
call exit@PLT
.L65:
movl %eax, %edi
call cudaGetErrorName@PLT
movq %rax, %rcx
movl %ebx, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $1, %edi
call exit@PLT
.L66:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $2, %edi
call exit@PLT
.L67:
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $2, %edi
call exit@PLT
.L68:
pushq $6
.cfi_def_cfa_offset 168
pushq $512
.cfi_def_cfa_offset 176
movq 72(%rsp), %r9
movq 64(%rsp), %r8
movl $1000, %ecx
movl $1600, %edx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z36__device_stub__Z7PathBigPiS_iiS_S_iiPiS_iiS_S_ii
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L46
.L69:
movl $512, %r9d
movq 48(%rsp), %r8
movq 56(%rsp), %rcx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z39__device_stub__Z10MergeBig_kPiS_S_S_S_iPiS_S_S_S_i
jmp .L47
.L70:
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq stdout(%rip), %rdi
call fflush@PLT
movl $2, %edi
call exit@PLT
.L71:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC19:
.string "_Z10MergeBig_kPiS_S_S_S_i"
.LC20:
.string "_Z7PathBigPiS_iiS_S_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z10MergeBig_kPiS_S_S_S_i(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z7PathBigPiS_iiS_S_ii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC17:
.long 1148846080
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "question2.hip"
.globl _Z22__device_stub__PathBigPiS_iiS_S_ii # -- Begin function _Z22__device_stub__PathBigPiS_iiS_S_ii
.p2align 4, 0x90
.type _Z22__device_stub__PathBigPiS_iiS_S_ii,@function
_Z22__device_stub__PathBigPiS_iiS_S_ii: # @_Z22__device_stub__PathBigPiS_iiS_S_ii
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, 72(%rsp)
movq %r9, 64(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 72(%rsp), %rax
movq %rax, 128(%rsp)
leaq 64(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7PathBigPiS_iiS_S_ii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z22__device_stub__PathBigPiS_iiS_S_ii, .Lfunc_end0-_Z22__device_stub__PathBigPiS_iiS_S_ii
.cfi_endproc
# -- End function
.globl _Z25__device_stub__MergeBig_kPiS_S_S_S_i # -- Begin function _Z25__device_stub__MergeBig_kPiS_S_S_S_i
.p2align 4, 0x90
.type _Z25__device_stub__MergeBig_kPiS_S_S_S_i,@function
_Z25__device_stub__MergeBig_kPiS_S_S_S_i: # @_Z25__device_stub__MergeBig_kPiS_S_S_S_i
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10MergeBig_kPiS_S_S_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z25__device_stub__MergeBig_kPiS_S_S_S_i, .Lfunc_end1-_Z25__device_stub__MergeBig_kPiS_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z5checkPciPi # -- Begin function _Z5checkPciPi
.p2align 4, 0x90
.type _Z5checkPciPi,@function
_Z5checkPciPi: # @_Z5checkPciPi
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl %esi, %r14d
movq %rdi, %r15
cmpl $2, %esi
jl .LBB2_5
# %bb.1: # %.lr.ph.preheader
leal -1(%r14), %eax
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB2_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rdx,%rbx,4), %r8d
movl 4(%rdx,%rbx,4), %r9d
cmpl %r9d, %r8d
jg .LBB2_3
# %bb.4: # in Loop: Header=BB2_2 Depth=1
incq %rbx
cmpl %ebx, %eax
jne .LBB2_2
.LBB2_5: # %._crit_edge
movl (%rdx), %eax
movl 4(%rdx), %ecx
movl 8(%rdx), %r8d
xorl %ebx, %ebx
movl $.L.str.1, %edi
movq %r15, %rsi
movl %eax, %edx
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movq %r15, %rsi
movl %r14d, %edx
xorl %eax, %eax
callq printf
jmp .LBB2_6
.LBB2_3:
movl $.L.str, %edi
movq %r15, %rsi
movl %r14d, %edx
movl %ebx, %ecx
xorl %eax, %eax
callq printf
.LBB2_6:
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z5checkPciPi, .Lfunc_end2-_Z5checkPciPi
.cfi_endproc
# -- End function
.globl _Z7AffichePcPii # -- Begin function _Z7AffichePcPii
.p2align 4, 0x90
.type _Z7AffichePcPii,@function
_Z7AffichePcPii: # @_Z7AffichePcPii
.cfi_startproc
# %bb.0:
testl %edx, %edx
jle .LBB3_6
# %bb.1: # %.lr.ph.preheader
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
pushq %rax
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movq %rdi, %r14
movl %edx, %r12d
movabsq $-3689348814741910323, %r13 # imm = 0xCCCCCCCCCCCCCCCD
xorl %r15d, %r15d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_4: # in Loop: Header=BB3_2 Depth=1
incq %r15
cmpl %r15d, %r12d
je .LBB3_5
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq %r15, %rax
mulq %r13
shrq $2, %rdx
leal (%rdx,%rdx,4), %ebp
addl $4, %ebp
movl (%rbx,%r15,4), %ecx
movl $.L.str.3, %edi
movq %r14, %rsi
movl %r15d, %edx
xorl %eax, %eax
callq printf
cmpl %r15d, %ebp
jne .LBB3_4
# %bb.3: # in Loop: Header=BB3_2 Depth=1
movl $10, %edi
callq putchar@PLT
jmp .LBB3_4
.LBB3_5:
addq $8, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB3_6: # %._crit_edge
movl $10, %edi
jmp putchar@PLT # TAILCALL
.Lfunc_end3:
.size _Z7AffichePcPii, .Lfunc_end3-_Z7AffichePcPii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x447a0000 # float 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $224, %rsp
.cfi_def_cfa_offset 272
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 152(%rsp), %rdi
callq hipEventCreate
leaq 144(%rsp), %rdi
callq hipEventCreate
movl $6400, %edi # imm = 0x1900
callq malloc
testq %rax, %rax
je .LBB4_1
# %bb.3:
movq %rax, %rbx
movl $4000, %edi # imm = 0xFA0
callq malloc
testq %rax, %rax
je .LBB4_4
# %bb.5:
movq %rax, %r14
movl $10400, %edi # imm = 0x28A0
callq malloc
testq %rax, %rax
je .LBB4_6
# %bb.7:
movq %rax, %r15
movl $1925, %edi # imm = 0x785
callq srand
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
movl %eax, (%r14)
movl %eax, (%rbx)
movl $1, %r12d
.p2align 4, 0x90
.LBB4_8: # =>This Inner Loop Header: Depth=1
movl -4(%rbx,%r12,4), %ebp
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
addl %ebp, %eax
movl %eax, (%rbx,%r12,4)
incq %r12
cmpq $1600, %r12 # imm = 0x640
jne .LBB4_8
# %bb.9: # %.preheader.preheader
movl $1, %r12d
.p2align 4, 0x90
.LBB4_10: # %.preheader
# =>This Inner Loop Header: Depth=1
movl -4(%r14,%r12,4), %ebp
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
addl %ebp, %eax
movl %eax, (%r14,%r12,4)
incq %r12
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB4_10
# %bb.11:
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movq $0, 40(%rsp)
movq $0, 32(%rsp)
movq $0, 24(%rsp)
leaq 16(%rsp), %rdi
movl $6400, %esi # imm = 0x1900
callq hipMalloc
testl %eax, %eax
jne .LBB4_12
# %bb.14:
leaq 8(%rsp), %rdi
movl $4000, %esi # imm = 0xFA0
callq hipMalloc
testl %eax, %eax
jne .LBB4_15
# %bb.16:
leaq 40(%rsp), %rdi
movl $10400, %esi # imm = 0x28A0
callq hipMalloc
testl %eax, %eax
jne .LBB4_17
# %bb.18:
leaq 32(%rsp), %rdi
movl $28, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_19
# %bb.20:
leaq 24(%rsp), %rdi
movl $28, %esi
callq hipMalloc
testl %eax, %eax
jne .LBB4_21
# %bb.22:
movq 16(%rsp), %rdi
movl $6400, %edx # imm = 0x1900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_23
# %bb.25:
movq 8(%rsp), %rdi
movl $4000, %edx # imm = 0xFA0
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_26
# %bb.27:
movabsq $4294967297, %r12 # imm = 0x100000001
movq 152(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 4(%r12), %rdx
movq %r12, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_29
# %bb.28:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 32(%rsp), %rdx
movq 24(%rsp), %rsi
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl $1600, 48(%rsp) # imm = 0x640
movl $1000, 4(%rsp) # imm = 0x3E8
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
movl $512, 140(%rsp) # imm = 0x200
movl $6, 136(%rsp)
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 48(%rsp), %rax
movq %rax, 176(%rsp)
leaq 4(%rsp), %rax
movq %rax, 184(%rsp)
leaq 112(%rsp), %rax
movq %rax, 192(%rsp)
leaq 104(%rsp), %rax
movq %rax, 200(%rsp)
leaq 140(%rsp), %rax
movq %rax, 208(%rsp)
leaq 136(%rsp), %rax
movq %rax, 216(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z7PathBigPiS_iiS_S_ii, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_29:
leaq 2(%r12), %rdi
addq $1023, %r12 # imm = 0x3FF
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_31
# %bb.30:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 40(%rsp), %rdx
movq 24(%rsp), %rsi
movq 32(%rsp), %rdi
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movq %rdx, 112(%rsp)
movq %rsi, 104(%rsp)
movq %rdi, 96(%rsp)
movl $512, 4(%rsp) # imm = 0x200
leaq 128(%rsp), %rax
movq %rax, 160(%rsp)
leaq 120(%rsp), %rax
movq %rax, 168(%rsp)
leaq 112(%rsp), %rax
movq %rax, 176(%rsp)
leaq 104(%rsp), %rax
movq %rax, 184(%rsp)
leaq 96(%rsp), %rax
movq %rax, 192(%rsp)
leaq 4(%rsp), %rax
movq %rax, 200(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 160(%rsp), %r9
movl $_Z10MergeBig_kPiS_S_S_S_i, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_31:
movq 40(%rsp), %rsi
movl $10400, %edx # imm = 0x28A0
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB4_32
# %bb.33:
movq 144(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
.p2align 4, 0x90
.LBB4_34: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r15,%r12,4), %r8d
movl 4(%r15,%r12,4), %r9d
cmpl %r9d, %r8d
jg .LBB4_35
# %bb.36: # in Loop: Header=BB4_34 Depth=1
incq %r12
cmpl $2599, %r12d # imm = 0xA27
jne .LBB4_34
# %bb.37: # %._crit_edge.i
movl (%r15), %edx
movl 4(%r15), %ecx
movl 8(%r15), %r8d
movl $.L.str.1, %edi
movl $.L.str.17, %esi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl $.L.str.17, %esi
movl $2600, %edx # imm = 0xA28
xorl %eax, %eax
callq printf
jmp .LBB4_38
.LBB4_35:
movl $.L.str, %edi
movl $.L.str.17, %esi
movl $2600, %edx # imm = 0xA28
movl %r12d, %ecx
xorl %eax, %eax
callq printf
.LBB4_38: # %_Z5checkPciPi.exit
movq 152(%rsp), %rsi
movq 144(%rsp), %rdx
leaq 160(%rsp), %rdi
callq hipEventElapsedTime
movss 160(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI4_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.18, %edi
movb $1, %al
callq printf
movq %r15, %rdi
callq free
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 16(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_40
# %bb.39:
callq hipFree
movq $0, 16(%rsp)
.LBB4_40:
movq 8(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_42
# %bb.41:
callq hipFree
movq $0, 8(%rsp)
.LBB4_42:
movq 40(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_44
# %bb.43:
callq hipFree
movq $0, 40(%rsp)
.LBB4_44:
movq 24(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_46
# %bb.45:
callq hipFree
movq $0, 24(%rsp)
.LBB4_46:
movq 32(%rsp), %rdi
testq %rdi, %rdi
je .LBB4_48
# %bb.47:
callq hipFree
movq $0, 32(%rsp)
.LBB4_48:
xorl %eax, %eax
addq $224, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB4_1:
.cfi_def_cfa_offset 272
movl $.Lstr.5, %edi
jmp .LBB4_2
.LBB4_4:
movl $.Lstr.4, %edi
jmp .LBB4_2
.LBB4_6:
movl $.Lstr.3, %edi
.LBB4_2:
callq puts@PLT
movl $1, %edi
callq exit
.LBB4_12:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorName
movl $.L.str.8, %edi
jmp .LBB4_13
.LBB4_15:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorName
movl $.L.str.9, %edi
jmp .LBB4_13
.LBB4_17:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorName
movl $.L.str.10, %edi
jmp .LBB4_13
.LBB4_19:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorName
movl $.L.str.11, %edi
jmp .LBB4_13
.LBB4_21:
movl %eax, %edi
movl %eax, %ebx
callq hipGetErrorName
movl $.L.str.12, %edi
.LBB4_13:
movl %ebx, %esi
movq %rax, %rdx
xorl %eax, %eax
callq printf
movq stdout(%rip), %rdi
callq fflush
movl $1, %edi
callq exit
.LBB4_23:
movl $.Lstr.2, %edi
jmp .LBB4_24
.LBB4_26:
movl $.Lstr.1, %edi
jmp .LBB4_24
.LBB4_32:
movl $.Lstr, %edi
.LBB4_24:
callq puts@PLT
movq stdout(%rip), %rdi
callq fflush
movl $2, %edi
callq exit
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7PathBigPiS_iiS_S_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10MergeBig_kPiS_S_S_S_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7PathBigPiS_iiS_S_ii,@object # @_Z7PathBigPiS_iiS_S_ii
.section .rodata,"a",@progbits
.globl _Z7PathBigPiS_iiS_S_ii
.p2align 3, 0x0
_Z7PathBigPiS_iiS_S_ii:
.quad _Z22__device_stub__PathBigPiS_iiS_S_ii
.size _Z7PathBigPiS_iiS_S_ii, 8
.type _Z10MergeBig_kPiS_S_S_S_i,@object # @_Z10MergeBig_kPiS_S_S_S_i
.globl _Z10MergeBig_kPiS_S_S_S_i
.p2align 3, 0x0
_Z10MergeBig_kPiS_S_S_S_i:
.quad _Z25__device_stub__MergeBig_kPiS_S_S_S_i
.size _Z10MergeBig_kPiS_S_S_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Check %s pour %d - Erreur en position %d %d > %d \n"
.size .L.str, 51
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Premiere valeur de %s = %d, deuxi\303\250me valeur = %d, troisi\303\250me valeur = %d \n"
.size .L.str.1, 76
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Check %s pour %d est OK \n"
.size .L.str.2, 26
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " - %s[%03d] = %6d"
.size .L.str.3, 18
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "PB allocation CudaVecteurA - %d - %s \n"
.size .L.str.8, 39
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "PB allocation CudaVecteurB - %d - %s \n"
.size .L.str.9, 39
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "PB allocation CudaVecteurM - %d - %s \n"
.size .L.str.10, 39
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "PB allocation CudaDiagBx - %d - %s \n"
.size .L.str.11, 37
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "PB allocation CudaDiagAy - %d - %s \n"
.size .L.str.12, 37
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "Check tableau M apr\303\250s"
.size .L.str.17, 23
.type .L.str.18,@object # @.str.18
.L.str.18:
.asciz "Duree %f s\n"
.size .L.str.18, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7PathBigPiS_iiS_S_ii"
.size .L__unnamed_1, 23
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10MergeBig_kPiS_S_S_S_i"
.size .L__unnamed_2, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "PB copie cuda M -> host M "
.size .Lstr, 27
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "PB copie host B -> cuda B "
.size .Lstr.1, 27
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "PB copie host A -> cuda A "
.size .Lstr.2, 27
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "PB allocation VecteurM"
.size .Lstr.3, 23
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "PB allocation VecteurB"
.size .Lstr.4, 23
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "PB allocation VecteurA"
.size .Lstr.5, 23
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__PathBigPiS_iiS_S_ii
.addrsig_sym _Z25__device_stub__MergeBig_kPiS_S_S_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7PathBigPiS_iiS_S_ii
.addrsig_sym _Z10MergeBig_kPiS_S_S_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*******************************************************************************
*
* probe a comuter for basic info about processing cores and GPU
*
* compile with:
*
* nvcc probe2.cu -L/usr/local/cuda/lib64 -I/usr/local/cuda-10.2/targets/x86_64-linux/include -lcuda -lcudart
*
* (in .tcshrc, please have:)
* set path = ($path /usr/local/cuda-10.1/bin ./)
* setenv LD_LIBRARY_PATH /usr/local/lib:/usr/local/cuda-10.1/lib64
*
*******************************************************************************/
#include <stdio.h>
#include <thread>
#include "cuda_runtime.h"
using namespace std;
/******************************************************************************/
int main(int argc, char *argv[]){
unsigned int numCores = std::thread::hardware_concurrency();
cudaError_t err;
err = cudaDeviceReset();
cudaDeviceProp prop;
int count;
err = cudaGetDeviceCount(&count);
if(err != cudaSuccess){
printf("problem getting device count = %s\n", cudaGetErrorString(err));
return 1;
}
printf("number of GPU devices: %d\n\n", count);
printf("*********Num CPU cores on this machine: %d\n*********", numCores);
for (int i = 0; i< count; i++){
printf("************ GPU Device: %d ************\n\n", i);
err = cudaGetDeviceProperties(&prop, i);
if(err != cudaSuccess){
printf("problem getting device properties = %s\n", cudaGetErrorString(err));
return 1;
}
printf("\tName: %s\n", prop.name);
printf("\tTotal global mem: %ld\n", prop.totalGlobalMem );
printf("\tTotal constant Mem: %ld\n", prop.totalConstMem );
printf( "\tMultiprocessor count: %d\n", prop.multiProcessorCount );
printf( "\tShared mem per processor: %ld\n", prop.sharedMemPerBlock );
printf( "\tMax threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "\tMax block dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0],
prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "\tMax grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0],
prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("\n");
}
return 0;
}
/******************************************************************************/ | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*******************************************************************************
*
* probe a comuter for basic info about processing cores and GPU
*
* compile with:
*
* nvcc probe2.cu -L/usr/local/cuda/lib64 -I/usr/local/cuda-10.2/targets/x86_64-linux/include -lcuda -lcudart
*
* (in .tcshrc, please have:)
* set path = ($path /usr/local/cuda-10.1/bin ./)
* setenv LD_LIBRARY_PATH /usr/local/lib:/usr/local/cuda-10.1/lib64
*
*******************************************************************************/
#include <stdio.h>
#include <thread>
#include "cuda_runtime.h"
using namespace std;
/******************************************************************************/
int main(int argc, char *argv[]){
unsigned int numCores = std::thread::hardware_concurrency();
cudaError_t err;
err = cudaDeviceReset();
cudaDeviceProp prop;
int count;
err = cudaGetDeviceCount(&count);
if(err != cudaSuccess){
printf("problem getting device count = %s\n", cudaGetErrorString(err));
return 1;
}
printf("number of GPU devices: %d\n\n", count);
printf("*********Num CPU cores on this machine: %d\n*********", numCores);
for (int i = 0; i< count; i++){
printf("************ GPU Device: %d ************\n\n", i);
err = cudaGetDeviceProperties(&prop, i);
if(err != cudaSuccess){
printf("problem getting device properties = %s\n", cudaGetErrorString(err));
return 1;
}
printf("\tName: %s\n", prop.name);
printf("\tTotal global mem: %ld\n", prop.totalGlobalMem );
printf("\tTotal constant Mem: %ld\n", prop.totalConstMem );
printf( "\tMultiprocessor count: %d\n", prop.multiProcessorCount );
printf( "\tShared mem per processor: %ld\n", prop.sharedMemPerBlock );
printf( "\tMax threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "\tMax block dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0],
prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "\tMax grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0],
prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("\n");
}
return 0;
}
/******************************************************************************/ | .file "tmpxft_001aa8a5_00000000-6_getInfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2684:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2684:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "problem getting device count = %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "number of GPU devices: %d\n\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "*********Num CPU cores on this machine: %d\n*********"
.align 8
.LC3:
.string "************ GPU Device: %d ************\n\n"
.align 8
.LC4:
.string "problem getting device properties = %s\n"
.section .rodata.str1.1
.LC5:
.string "\tName: %s\n"
.LC6:
.string "\tTotal global mem: %ld\n"
.LC7:
.string "\tTotal constant Mem: %ld\n"
.LC8:
.string "\tMultiprocessor count: %d\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "\tShared mem per processor: %ld\n"
.section .rodata.str1.1
.LC10:
.string "\tMax threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "\tMax block dimensions: (%d, %d, %d)\n"
.align 8
.LC12:
.string "\tMax grid dimensions: (%d, %d, %d)\n"
.section .rodata.str1.1
.LC13:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2681:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
call _ZNSt6thread20hardware_concurrencyEv@PLT
movl %eax, %ebx
call cudaDeviceReset@PLT
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L9
movl $0, %ebx
leaq .LC3(%rip), %rbp
leaq .LC5(%rip), %r14
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r12
.L7:
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L13
leaq 16(%rsp), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L7
movl $0, %eax
jmp .L3
.L12:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L14
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.L9:
movl $0, %eax
jmp .L3
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2681:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2707:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*******************************************************************************
*
* probe a comuter for basic info about processing cores and GPU
*
* compile with:
*
* nvcc probe2.cu -L/usr/local/cuda/lib64 -I/usr/local/cuda-10.2/targets/x86_64-linux/include -lcuda -lcudart
*
* (in .tcshrc, please have:)
* set path = ($path /usr/local/cuda-10.1/bin ./)
* setenv LD_LIBRARY_PATH /usr/local/lib:/usr/local/cuda-10.1/lib64
*
*******************************************************************************/
#include <stdio.h>
#include <thread>
#include "cuda_runtime.h"
using namespace std;
/******************************************************************************/
int main(int argc, char *argv[]){
unsigned int numCores = std::thread::hardware_concurrency();
cudaError_t err;
err = cudaDeviceReset();
cudaDeviceProp prop;
int count;
err = cudaGetDeviceCount(&count);
if(err != cudaSuccess){
printf("problem getting device count = %s\n", cudaGetErrorString(err));
return 1;
}
printf("number of GPU devices: %d\n\n", count);
printf("*********Num CPU cores on this machine: %d\n*********", numCores);
for (int i = 0; i< count; i++){
printf("************ GPU Device: %d ************\n\n", i);
err = cudaGetDeviceProperties(&prop, i);
if(err != cudaSuccess){
printf("problem getting device properties = %s\n", cudaGetErrorString(err));
return 1;
}
printf("\tName: %s\n", prop.name);
printf("\tTotal global mem: %ld\n", prop.totalGlobalMem );
printf("\tTotal constant Mem: %ld\n", prop.totalConstMem );
printf( "\tMultiprocessor count: %d\n", prop.multiProcessorCount );
printf( "\tShared mem per processor: %ld\n", prop.sharedMemPerBlock );
printf( "\tMax threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "\tMax block dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0],
prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "\tMax grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0],
prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("\n");
}
return 0;
}
/******************************************************************************/ | /*******************************************************************************
*
* probe a comuter for basic info about processing cores and GPU
*
* compile with:
*
* nvcc probe2.cu -L/usr/local/cuda/lib64 -I/usr/local/cuda-10.2/targets/x86_64-linux/include -lcuda -lcudart
*
* (in .tcshrc, please have:)
* set path = ($path /usr/local/cuda-10.1/bin ./)
* setenv LD_LIBRARY_PATH /usr/local/lib:/usr/local/cuda-10.1/lib64
*
*******************************************************************************/
#include <stdio.h>
#include <thread>
#include "hip/hip_runtime.h"
using namespace std;
/******************************************************************************/
int main(int argc, char *argv[]){
unsigned int numCores = std::thread::hardware_concurrency();
hipError_t err;
err = hipDeviceReset();
hipDeviceProp_t prop;
int count;
err = hipGetDeviceCount(&count);
if(err != hipSuccess){
printf("problem getting device count = %s\n", hipGetErrorString(err));
return 1;
}
printf("number of GPU devices: %d\n\n", count);
printf("*********Num CPU cores on this machine: %d\n*********", numCores);
for (int i = 0; i< count; i++){
printf("************ GPU Device: %d ************\n\n", i);
err = hipGetDeviceProperties(&prop, i);
if(err != hipSuccess){
printf("problem getting device properties = %s\n", hipGetErrorString(err));
return 1;
}
printf("\tName: %s\n", prop.name);
printf("\tTotal global mem: %ld\n", prop.totalGlobalMem );
printf("\tTotal constant Mem: %ld\n", prop.totalConstMem );
printf( "\tMultiprocessor count: %d\n", prop.multiProcessorCount );
printf( "\tShared mem per processor: %ld\n", prop.sharedMemPerBlock );
printf( "\tMax threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "\tMax block dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0],
prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "\tMax grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0],
prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("\n");
}
return 0;
}
/******************************************************************************/ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*******************************************************************************
*
* probe a comuter for basic info about processing cores and GPU
*
* compile with:
*
* nvcc probe2.cu -L/usr/local/cuda/lib64 -I/usr/local/cuda-10.2/targets/x86_64-linux/include -lcuda -lcudart
*
* (in .tcshrc, please have:)
* set path = ($path /usr/local/cuda-10.1/bin ./)
* setenv LD_LIBRARY_PATH /usr/local/lib:/usr/local/cuda-10.1/lib64
*
*******************************************************************************/
#include <stdio.h>
#include <thread>
#include "hip/hip_runtime.h"
using namespace std;
/******************************************************************************/
int main(int argc, char *argv[]){
unsigned int numCores = std::thread::hardware_concurrency();
hipError_t err;
err = hipDeviceReset();
hipDeviceProp_t prop;
int count;
err = hipGetDeviceCount(&count);
if(err != hipSuccess){
printf("problem getting device count = %s\n", hipGetErrorString(err));
return 1;
}
printf("number of GPU devices: %d\n\n", count);
printf("*********Num CPU cores on this machine: %d\n*********", numCores);
for (int i = 0; i< count; i++){
printf("************ GPU Device: %d ************\n\n", i);
err = hipGetDeviceProperties(&prop, i);
if(err != hipSuccess){
printf("problem getting device properties = %s\n", hipGetErrorString(err));
return 1;
}
printf("\tName: %s\n", prop.name);
printf("\tTotal global mem: %ld\n", prop.totalGlobalMem );
printf("\tTotal constant Mem: %ld\n", prop.totalConstMem );
printf( "\tMultiprocessor count: %d\n", prop.multiProcessorCount );
printf( "\tShared mem per processor: %ld\n", prop.sharedMemPerBlock );
printf( "\tMax threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "\tMax block dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0],
prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "\tMax grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0],
prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("\n");
}
return 0;
}
/******************************************************************************/ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*******************************************************************************
*
* probe a comuter for basic info about processing cores and GPU
*
* compile with:
*
* nvcc probe2.cu -L/usr/local/cuda/lib64 -I/usr/local/cuda-10.2/targets/x86_64-linux/include -lcuda -lcudart
*
* (in .tcshrc, please have:)
* set path = ($path /usr/local/cuda-10.1/bin ./)
* setenv LD_LIBRARY_PATH /usr/local/lib:/usr/local/cuda-10.1/lib64
*
*******************************************************************************/
#include <stdio.h>
#include <thread>
#include "hip/hip_runtime.h"
using namespace std;
/******************************************************************************/
int main(int argc, char *argv[]){
unsigned int numCores = std::thread::hardware_concurrency();
hipError_t err;
err = hipDeviceReset();
hipDeviceProp_t prop;
int count;
err = hipGetDeviceCount(&count);
if(err != hipSuccess){
printf("problem getting device count = %s\n", hipGetErrorString(err));
return 1;
}
printf("number of GPU devices: %d\n\n", count);
printf("*********Num CPU cores on this machine: %d\n*********", numCores);
for (int i = 0; i< count; i++){
printf("************ GPU Device: %d ************\n\n", i);
err = hipGetDeviceProperties(&prop, i);
if(err != hipSuccess){
printf("problem getting device properties = %s\n", hipGetErrorString(err));
return 1;
}
printf("\tName: %s\n", prop.name);
printf("\tTotal global mem: %ld\n", prop.totalGlobalMem );
printf("\tTotal constant Mem: %ld\n", prop.totalConstMem );
printf( "\tMultiprocessor count: %d\n", prop.multiProcessorCount );
printf( "\tShared mem per processor: %ld\n", prop.sharedMemPerBlock );
printf( "\tMax threads per block: %d\n", prop.maxThreadsPerBlock );
printf( "\tMax block dimensions: (%d, %d, %d)\n",
prop.maxThreadsDim[0],
prop.maxThreadsDim[1],
prop.maxThreadsDim[2]);
printf( "\tMax grid dimensions: (%d, %d, %d)\n",
prop.maxGridSize[0],
prop.maxGridSize[1],
prop.maxGridSize[2]);
printf("\n");
}
return 0;
}
/******************************************************************************/ | .text
.file "getInfo.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
callq _ZNSt6thread20hardware_concurrencyEv
movl %eax, %ebx
callq hipDeviceReset
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %ebx
.LBB0_6: # %.loopexit.sink.split
movl %eax, %edi
callq hipGetErrorString
movq %rbx, %rdi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %ebp
.LBB0_7: # %.loopexit
movl %ebp, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 1520
movl 12(%rsp), %esi
xorl %ebp, %ebp
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB0_7
# %bb.3: # %.lr.ph
leaq 16(%rsp), %rbx
xorl %r14d, %r14d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_4: # =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %r14d, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_5
# %bb.8: # in Loop: Header=BB0_4 Depth=1
movl $.L.str.5, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 368(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 404(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %r14d
cmpl 12(%rsp), %r14d
jl .LBB0_4
jmp .LBB0_7
.LBB0_5:
movl $.L.str.4, %ebx
jmp .LBB0_6
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "problem getting device count = %s\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "number of GPU devices: %d\n\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "*********Num CPU cores on this machine: %d\n*********"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "************ GPU Device: %d ************\n\n"
.size .L.str.3, 43
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "problem getting device properties = %s\n"
.size .L.str.4, 40
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\tName: %s\n"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\tTotal global mem: %ld\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tTotal constant Mem: %ld\n"
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tMultiprocessor count: %d\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\tShared mem per processor: %ld\n"
.size .L.str.9, 32
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\tMax threads per block: %d\n"
.size .L.str.10, 28
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\tMax block dimensions: (%d, %d, %d)\n"
.size .L.str.11, 37
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\tMax grid dimensions: (%d, %d, %d)\n"
.size .L.str.12, 36
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001aa8a5_00000000-6_getInfo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2684:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2684:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "problem getting device count = %s\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "number of GPU devices: %d\n\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "*********Num CPU cores on this machine: %d\n*********"
.align 8
.LC3:
.string "************ GPU Device: %d ************\n\n"
.align 8
.LC4:
.string "problem getting device properties = %s\n"
.section .rodata.str1.1
.LC5:
.string "\tName: %s\n"
.LC6:
.string "\tTotal global mem: %ld\n"
.LC7:
.string "\tTotal constant Mem: %ld\n"
.LC8:
.string "\tMultiprocessor count: %d\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "\tShared mem per processor: %ld\n"
.section .rodata.str1.1
.LC10:
.string "\tMax threads per block: %d\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "\tMax block dimensions: (%d, %d, %d)\n"
.align 8
.LC12:
.string "\tMax grid dimensions: (%d, %d, %d)\n"
.section .rodata.str1.1
.LC13:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2681:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $1056, %rsp
.cfi_def_cfa_offset 1104
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
call _ZNSt6thread20hardware_concurrencyEv@PLT
movl %eax, %ebx
call cudaDeviceReset@PLT
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
testl %eax, %eax
jne .L12
movl 12(%rsp), %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %edx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, 12(%rsp)
jle .L9
movl $0, %ebx
leaq .LC3(%rip), %rbp
leaq .LC5(%rip), %r14
leaq .LC6(%rip), %r13
leaq .LC7(%rip), %r12
.L7:
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
jne .L13
leaq 16(%rsp), %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 304(%rsp), %rdx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 368(%rsp), %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 404(%rsp), %edx
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 312(%rsp), %rdx
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 336(%rsp), %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 348(%rsp), %r8d
movl 344(%rsp), %ecx
movl 340(%rsp), %edx
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 360(%rsp), %r8d
movl 356(%rsp), %ecx
movl 352(%rsp), %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jg .L7
movl $0, %eax
jmp .L3
.L12:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L14
addq $1056, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L13:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %eax
jmp .L3
.L9:
movl $0, %eax
jmp .L3
.L14:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2681:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2707:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2707:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "getInfo.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
callq _ZNSt6thread20hardware_concurrencyEv
movl %eax, %ebx
callq hipDeviceReset
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
testl %eax, %eax
je .LBB0_2
# %bb.1:
movl $.L.str, %ebx
.LBB0_6: # %.loopexit.sink.split
movl %eax, %edi
callq hipGetErrorString
movq %rbx, %rdi
movq %rax, %rsi
xorl %eax, %eax
callq printf
movl $1, %ebp
.LBB0_7: # %.loopexit
movl %ebp, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_2:
.cfi_def_cfa_offset 1520
movl 12(%rsp), %esi
xorl %ebp, %ebp
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $.L.str.2, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
cmpl $0, 12(%rsp)
jle .LBB0_7
# %bb.3: # %.lr.ph
leaq 16(%rsp), %rbx
xorl %r14d, %r14d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_4: # =>This Inner Loop Header: Depth=1
movl $.L.str.3, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
movq %rbx, %rdi
movl %r14d, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB0_5
# %bb.8: # in Loop: Header=BB0_4 Depth=1
movl $.L.str.5, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movq 304(%rsp), %rsi
movl $.L.str.6, %edi
xorl %eax, %eax
callq printf
movq 368(%rsp), %rsi
movl $.L.str.7, %edi
xorl %eax, %eax
callq printf
movl 404(%rsp), %esi
movl $.L.str.8, %edi
xorl %eax, %eax
callq printf
movq 312(%rsp), %rsi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl 336(%rsp), %esi
movl $.L.str.10, %edi
xorl %eax, %eax
callq printf
movl 340(%rsp), %esi
movl 344(%rsp), %edx
movl 348(%rsp), %ecx
movl $.L.str.11, %edi
xorl %eax, %eax
callq printf
movl 352(%rsp), %esi
movl 356(%rsp), %edx
movl 360(%rsp), %ecx
movl $.L.str.12, %edi
xorl %eax, %eax
callq printf
movl $10, %edi
callq putchar@PLT
incl %r14d
cmpl 12(%rsp), %r14d
jl .LBB0_4
jmp .LBB0_7
.LBB0_5:
movl $.L.str.4, %ebx
jmp .LBB0_6
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "problem getting device count = %s\n"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "number of GPU devices: %d\n\n"
.size .L.str.1, 28
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "*********Num CPU cores on this machine: %d\n*********"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "************ GPU Device: %d ************\n\n"
.size .L.str.3, 43
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "problem getting device properties = %s\n"
.size .L.str.4, 40
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\tName: %s\n"
.size .L.str.5, 11
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "\tTotal global mem: %ld\n"
.size .L.str.6, 24
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "\tTotal constant Mem: %ld\n"
.size .L.str.7, 26
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "\tMultiprocessor count: %d\n"
.size .L.str.8, 27
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\tShared mem per processor: %ld\n"
.size .L.str.9, 32
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "\tMax threads per block: %d\n"
.size .L.str.10, 28
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "\tMax block dimensions: (%d, %d, %d)\n"
.size .L.str.11, 37
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "\tMax grid dimensions: (%d, %d, %d)\n"
.size .L.str.12, 36
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ inline float sigmoid(float x) {
return 1.0f / (1.0f + __expf(-x));
}
__global__ void kApplySigmoid(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = sigmoid(mat[i]);
} | code for sm_80
Function : _Z13kApplySigmoidPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fc800078e00ff */
/*0080*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B0, 0x220 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*00c0*/ FMUL R3, R4, -1.4426950216293334961 ; /* 0xbfb8aa3b04037820 */
/* 0x004fca0000400000 */
/*00d0*/ FSETP.GEU.AND P0, PT, R3, -126, PT ; /* 0xc2fc00000300780b */
/* 0x000fda0003f0e000 */
/*00e0*/ @!P0 FMUL R3, R3, 0.5 ; /* 0x3f00000003038820 */
/* 0x000fc80000400000 */
/*00f0*/ MUFU.EX2 R2, R3 ; /* 0x0000000300027308 */
/* 0x000e240000000800 */
/*0100*/ @!P0 FMUL R2, R2, R2 ; /* 0x0000000202028220 */
/* 0x001fc80000400000 */
/*0110*/ FADD R8, R2, 1 ; /* 0x3f80000002087421 */
/* 0x000fe40000000000 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, R0.reuse ; /* 0x000000ffff027224 */
/* 0x100fe400078e0000 */
/*0130*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fe200078e0200 */
/*0140*/ IADD3 R6, R8, 0x1800000, RZ ; /* 0x0180000008067810 */
/* 0x000fc80007ffe0ff */
/*0150*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000006067812 */
/* 0x000fe400078ec0ff */
/*0160*/ ISETP.GE.U32.AND P3, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f66070 */
/*0170*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ffffff, PT ; /* 0x01ffffff0600780c */
/* 0x000fda0003f04070 */
/*0180*/ @P0 BRA 0x1d0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0190*/ MOV R4, 0x1b0 ; /* 0x000001b000047802 */
/* 0x000fe40000000f00 */
/*01a0*/ CALL.REL.NOINC 0x270 ; /* 0x000000c000007944 */
/* 0x000fea0003c00000 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0003 */
/*01c0*/ BRA 0x210 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*01d0*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x000e240000001000 */
/*01e0*/ FFMA R3, R8, R5, -1 ; /* 0xbf80000008037423 */
/* 0x001fc80000000005 */
/*01f0*/ FADD.FTZ R4, -R3, -RZ ; /* 0x800000ff03047221 */
/* 0x000fc80000010100 */
/*0200*/ FFMA R5, R5, R4, R5 ; /* 0x0000000405057223 */
/* 0x000fe40000000005 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0230*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0003 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*0250*/ @!P3 BRA 0x70 ; /* 0xfffffe100000b947 */
/* 0x000fea000383ffff */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ IMAD.SHL.U32 R3, R8, 0x2, RZ ; /* 0x0000000208037824 */
/* 0x000fe200078e00ff */
/*0280*/ BSSY B1, 0x5a0 ; /* 0x0000031000017945 */
/* 0x000fe80003800000 */
/*0290*/ SHF.R.U32.HI R10, RZ, 0x18, R3 ; /* 0x00000018ff0a7819 */
/* 0x000fe20000011603 */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0008 */
/*02b0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*02c0*/ @P0 BRA 0x370 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.SHL.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057824 */
/* 0x000fca00078e00ff */
/*02e0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*02f0*/ @P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003060823 */
/* 0x000fe200000000ff */
/*0300*/ @!P0 MUFU.RCP R5, R3 ; /* 0x0000000300058308 */
/* 0x000ff00000001000 */
/*0310*/ @P0 MUFU.RCP R7, R6 ; /* 0x0000000600070308 */
/* 0x000e240000001000 */
/*0320*/ @P0 FFMA R8, R6, R7, -1 ; /* 0xbf80000006080423 */
/* 0x001fc80000000007 */
/*0330*/ @P0 FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08080221 */
/* 0x000fc80000010100 */
/*0340*/ @P0 FFMA R8, R7, R8, R7 ; /* 0x0000000807080223 */
/* 0x000fc80000000007 */
/*0350*/ @P0 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008050823 */
/* 0x000fe200000000ff */
/*0360*/ BRA 0x590 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R12, R10, -0xfd, RZ ; /* 0xffffff030a0c7810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GT.U32.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f04070 */
/*0390*/ @P0 BRA 0x580 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*03a0*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe400078ec0ff */
/*03b0*/ MOV R9, 0x3 ; /* 0x0000000300097802 */
/* 0x000fe40000000f00 */
/*03c0*/ LOP3.LUT R5, R5, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000005057812 */
/* 0x000fe400078efcff */
/*03d0*/ SHF.L.U32 R9, R9, R12, RZ ; /* 0x0000000c09097219 */
/* 0x000fe400000006ff */
/*03e0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e240000001000 */
/*03f0*/ FFMA R7, R5, R6, -1 ; /* 0xbf80000005077423 */
/* 0x001fc80000000006 */
/*0400*/ FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07077221 */
/* 0x000fc80000010100 */
/*0410*/ FFMA.RM R8, R6.reuse, R7.reuse, R6.reuse ; /* 0x0000000706087223 */
/* 0x1c0fe40000004006 */
/*0420*/ FFMA.RP R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc60000008006 */
/*0430*/ LOP3.LUT R6, R8.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08067812 */
/* 0x040fe400078ec0ff */
/*0440*/ FSETP.NEU.FTZ.AND P0, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x000fe40003f1d000 */
/*0450*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0460*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*0470*/ LOP3.LUT R9, R9, R6, RZ, 0xc0, !PT ; /* 0x0000000609097212 */
/* 0x000fc600078ec0ff */
/*0480*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*0490*/ SHF.R.U32.HI R9, RZ, R12, R9 ; /* 0x0000000cff097219 */
/* 0x000fc80000011609 */
/*04a0*/ LOP3.LUT P1, RZ, R7, R12, R6, 0xf8, !PT ; /* 0x0000000c07ff7212 */
/* 0x000fe4000782f806 */
/*04b0*/ LOP3.LUT P0, RZ, R9.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109ff7812 */
/* 0x040fe4000780c0ff */
/*04c0*/ LOP3.LUT P2, RZ, R9, 0x2, RZ, 0xc0, !PT ; /* 0x0000000209ff7812 */
/* 0x000fc8000784c0ff */
/*04d0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*04e0*/ LOP3.LUT P1, RZ, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03ff7812 */
/* 0x000fe4000782c0ff */
/*04f0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0500*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a05 */
/*0510*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f06270 */
/*0520*/ IADD3 R5, R10, -0xfc, RZ ; /* 0xffffff040a057810 */
/* 0x000fc80007ffe0ff */
/*0530*/ SHF.R.U32.HI R6, RZ, R5, R6 ; /* 0x00000005ff067219 */
/* 0x000fce0000011606 */
/*0540*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fca0007ffe0ff */
/*0550*/ @!P1 IMAD.SHL.U32 R6, R6, 0x2, RZ ; /* 0x0000000206069824 */
/* 0x000fca00078e00ff */
/*0560*/ LOP3.LUT R5, R6, 0x80000000, R3, 0xf8, !PT ; /* 0x8000000006057812 */
/* 0x000fe200078ef803 */
/*0570*/ BRA 0x590 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0580*/ MUFU.RCP R5, R3 ; /* 0x0000000300057308 */
/* 0x0000640000001000 */
/*0590*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05a0*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x003fe20000000f00 */
/*05b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*05c0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffa3004007950 */
/* 0x000fea0003c3ffff */
/*05d0*/ BRA 0x5d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ inline float sigmoid(float x) {
return 1.0f / (1.0f + __expf(-x));
}
__global__ void kApplySigmoid(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = sigmoid(mat[i]);
} | .file "tmpxft_0012ed47_00000000-6_kApplySigmoid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j
.type _Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j, @function
_Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kApplySigmoidPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j, .-_Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j
.globl _Z13kApplySigmoidPfS_j
.type _Z13kApplySigmoidPfS_j, @function
_Z13kApplySigmoidPfS_j:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13kApplySigmoidPfS_j, .-_Z13kApplySigmoidPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kApplySigmoidPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kApplySigmoidPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ inline float sigmoid(float x) {
return 1.0f / (1.0f + __expf(-x));
}
__global__ void kApplySigmoid(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = sigmoid(mat[i]);
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ inline float sigmoid(float x) {
return 1.0f / (1.0f + __expf(-x));
}
__global__ void kApplySigmoid(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = sigmoid(mat[i]);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ inline float sigmoid(float x) {
return 1.0f / (1.0f + __expf(-x));
}
__global__ void kApplySigmoid(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = sigmoid(mat[i]);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kApplySigmoidPfS_j
.globl _Z13kApplySigmoidPfS_j
.p2align 8
.type _Z13kApplySigmoidPfS_j,@function
_Z13kApplySigmoidPfS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s0, s8, v1
global_load_b32 v0, v[5:6], off
s_or_b32 s2, s0, s2
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, 0xbfb8aa3b, v0
v_exp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_add_f32_e32 v0, 1.0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v0, v0, 1.0
v_div_scale_f32 v7, vcc_lo, 1.0, v0, 1.0
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v6
v_mul_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v8, v7
v_fmac_f32_e32 v8, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v7
v_div_fmas_f32 v5, v5, v6, v8
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v0, v5, v0, 1.0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kApplySigmoidPfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kApplySigmoidPfS_j, .Lfunc_end0-_Z13kApplySigmoidPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kApplySigmoidPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kApplySigmoidPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ inline float sigmoid(float x) {
return 1.0f / (1.0f + __expf(-x));
}
__global__ void kApplySigmoid(float* mat, float* target, unsigned int len) {
const unsigned int idx = blockIdx.x * blockDim.x + threadIdx.x;
const unsigned int numThreads = blockDim.x * gridDim.x;
for (unsigned int i = idx; i < len; i += numThreads) target[i] = sigmoid(mat[i]);
} | .text
.file "kApplySigmoid.hip"
.globl _Z28__device_stub__kApplySigmoidPfS_j # -- Begin function _Z28__device_stub__kApplySigmoidPfS_j
.p2align 4, 0x90
.type _Z28__device_stub__kApplySigmoidPfS_j,@function
_Z28__device_stub__kApplySigmoidPfS_j: # @_Z28__device_stub__kApplySigmoidPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kApplySigmoidPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__kApplySigmoidPfS_j, .Lfunc_end0-_Z28__device_stub__kApplySigmoidPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kApplySigmoidPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kApplySigmoidPfS_j,@object # @_Z13kApplySigmoidPfS_j
.section .rodata,"a",@progbits
.globl _Z13kApplySigmoidPfS_j
.p2align 3, 0x0
_Z13kApplySigmoidPfS_j:
.quad _Z28__device_stub__kApplySigmoidPfS_j
.size _Z13kApplySigmoidPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kApplySigmoidPfS_j"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kApplySigmoidPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kApplySigmoidPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13kApplySigmoidPfS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x001fc800078e00ff */
/*0080*/ IMAD.WIDE.U32 R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff077624 */
/* 0x000fe200078e00ff */
/*00b0*/ BSSY B0, 0x220 ; /* 0x0000016000007945 */
/* 0x000fe20003800000 */
/*00c0*/ FMUL R3, R4, -1.4426950216293334961 ; /* 0xbfb8aa3b04037820 */
/* 0x004fca0000400000 */
/*00d0*/ FSETP.GEU.AND P0, PT, R3, -126, PT ; /* 0xc2fc00000300780b */
/* 0x000fda0003f0e000 */
/*00e0*/ @!P0 FMUL R3, R3, 0.5 ; /* 0x3f00000003038820 */
/* 0x000fc80000400000 */
/*00f0*/ MUFU.EX2 R2, R3 ; /* 0x0000000300027308 */
/* 0x000e240000000800 */
/*0100*/ @!P0 FMUL R2, R2, R2 ; /* 0x0000000202028220 */
/* 0x001fc80000400000 */
/*0110*/ FADD R8, R2, 1 ; /* 0x3f80000002087421 */
/* 0x000fe40000000000 */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, R0.reuse ; /* 0x000000ffff027224 */
/* 0x100fe400078e0000 */
/*0130*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fe200078e0200 */
/*0140*/ IADD3 R6, R8, 0x1800000, RZ ; /* 0x0180000008067810 */
/* 0x000fc80007ffe0ff */
/*0150*/ LOP3.LUT R6, R6, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000006067812 */
/* 0x000fe400078ec0ff */
/*0160*/ ISETP.GE.U32.AND P3, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f66070 */
/*0170*/ ISETP.GT.U32.AND P0, PT, R6, 0x1ffffff, PT ; /* 0x01ffffff0600780c */
/* 0x000fda0003f04070 */
/*0180*/ @P0 BRA 0x1d0 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0190*/ MOV R4, 0x1b0 ; /* 0x000001b000047802 */
/* 0x000fe40000000f00 */
/*01a0*/ CALL.REL.NOINC 0x270 ; /* 0x000000c000007944 */
/* 0x000fea0003c00000 */
/*01b0*/ IMAD.MOV.U32 R5, RZ, RZ, R3 ; /* 0x000000ffff057224 */
/* 0x000fe200078e0003 */
/*01c0*/ BRA 0x210 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*01d0*/ MUFU.RCP R5, R8 ; /* 0x0000000800057308 */
/* 0x000e240000001000 */
/*01e0*/ FFMA R3, R8, R5, -1 ; /* 0xbf80000008037423 */
/* 0x001fc80000000005 */
/*01f0*/ FADD.FTZ R4, -R3, -RZ ; /* 0x800000ff03047221 */
/* 0x000fc80000010100 */
/*0200*/ FFMA R5, R5, R4, R5 ; /* 0x0000000405057223 */
/* 0x000fe40000000005 */
/*0210*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0220*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*0230*/ IMAD.WIDE.U32 R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0003 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e2000c101904 */
/*0250*/ @!P3 BRA 0x70 ; /* 0xfffffe100000b947 */
/* 0x000fea000383ffff */
/*0260*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0270*/ IMAD.SHL.U32 R3, R8, 0x2, RZ ; /* 0x0000000208037824 */
/* 0x000fe200078e00ff */
/*0280*/ BSSY B1, 0x5a0 ; /* 0x0000031000017945 */
/* 0x000fe80003800000 */
/*0290*/ SHF.R.U32.HI R10, RZ, 0x18, R3 ; /* 0x00000018ff0a7819 */
/* 0x000fe20000011603 */
/*02a0*/ IMAD.MOV.U32 R3, RZ, RZ, R8 ; /* 0x000000ffff037224 */
/* 0x000fc600078e0008 */
/*02b0*/ ISETP.NE.U32.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f05070 */
/*02c0*/ @P0 BRA 0x370 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*02d0*/ IMAD.SHL.U32 R5, R3, 0x2, RZ ; /* 0x0000000203057824 */
/* 0x000fca00078e00ff */
/*02e0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*02f0*/ @P0 FFMA R6, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003060823 */
/* 0x000fe200000000ff */
/*0300*/ @!P0 MUFU.RCP R5, R3 ; /* 0x0000000300058308 */
/* 0x000ff00000001000 */
/*0310*/ @P0 MUFU.RCP R7, R6 ; /* 0x0000000600070308 */
/* 0x000e240000001000 */
/*0320*/ @P0 FFMA R8, R6, R7, -1 ; /* 0xbf80000006080423 */
/* 0x001fc80000000007 */
/*0330*/ @P0 FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08080221 */
/* 0x000fc80000010100 */
/*0340*/ @P0 FFMA R8, R7, R8, R7 ; /* 0x0000000807080223 */
/* 0x000fc80000000007 */
/*0350*/ @P0 FFMA R5, R8, 1.84467440737095516160e+19, RZ ; /* 0x5f80000008050823 */
/* 0x000fe200000000ff */
/*0360*/ BRA 0x590 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R12, R10, -0xfd, RZ ; /* 0xffffff030a0c7810 */
/* 0x000fc80007ffe0ff */
/*0380*/ ISETP.GT.U32.AND P0, PT, R12, 0x1, PT ; /* 0x000000010c00780c */
/* 0x000fda0003f04070 */
/*0390*/ @P0 BRA 0x580 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*03a0*/ LOP3.LUT R5, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03057812 */
/* 0x000fe400078ec0ff */
/*03b0*/ MOV R9, 0x3 ; /* 0x0000000300097802 */
/* 0x000fe40000000f00 */
/*03c0*/ LOP3.LUT R5, R5, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000005057812 */
/* 0x000fe400078efcff */
/*03d0*/ SHF.L.U32 R9, R9, R12, RZ ; /* 0x0000000c09097219 */
/* 0x000fe400000006ff */
/*03e0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e240000001000 */
/*03f0*/ FFMA R7, R5, R6, -1 ; /* 0xbf80000005077423 */
/* 0x001fc80000000006 */
/*0400*/ FADD.FTZ R7, -R7, -RZ ; /* 0x800000ff07077221 */
/* 0x000fc80000010100 */
/*0410*/ FFMA.RM R8, R6.reuse, R7.reuse, R6.reuse ; /* 0x0000000706087223 */
/* 0x1c0fe40000004006 */
/*0420*/ FFMA.RP R7, R6, R7, R6 ; /* 0x0000000706077223 */
/* 0x000fc60000008006 */
/*0430*/ LOP3.LUT R6, R8.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff08067812 */
/* 0x040fe400078ec0ff */
/*0440*/ FSETP.NEU.FTZ.AND P0, PT, R8, R7, PT ; /* 0x000000070800720b */
/* 0x000fe40003f1d000 */
/*0450*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0460*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*0470*/ LOP3.LUT R9, R9, R6, RZ, 0xc0, !PT ; /* 0x0000000609097212 */
/* 0x000fc600078ec0ff */
/*0480*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*0490*/ SHF.R.U32.HI R9, RZ, R12, R9 ; /* 0x0000000cff097219 */
/* 0x000fc80000011609 */
/*04a0*/ LOP3.LUT P1, RZ, R7, R12, R6, 0xf8, !PT ; /* 0x0000000c07ff7212 */
/* 0x000fe4000782f806 */
/*04b0*/ LOP3.LUT P0, RZ, R9.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000109ff7812 */
/* 0x040fe4000780c0ff */
/*04c0*/ LOP3.LUT P2, RZ, R9, 0x2, RZ, 0xc0, !PT ; /* 0x0000000209ff7812 */
/* 0x000fc8000784c0ff */
/*04d0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*04e0*/ LOP3.LUT P1, RZ, R3, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff03ff7812 */
/* 0x000fe4000782c0ff */
/*04f0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*0500*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a05 */
/*0510*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe40003f06270 */
/*0520*/ IADD3 R5, R10, -0xfc, RZ ; /* 0xffffff040a057810 */
/* 0x000fc80007ffe0ff */
/*0530*/ SHF.R.U32.HI R6, RZ, R5, R6 ; /* 0x00000005ff067219 */
/* 0x000fce0000011606 */
/*0540*/ @!P0 IADD3 R6, R6, 0x1, RZ ; /* 0x0000000106068810 */
/* 0x000fca0007ffe0ff */
/*0550*/ @!P1 IMAD.SHL.U32 R6, R6, 0x2, RZ ; /* 0x0000000206069824 */
/* 0x000fca00078e00ff */
/*0560*/ LOP3.LUT R5, R6, 0x80000000, R3, 0xf8, !PT ; /* 0x8000000006057812 */
/* 0x000fe200078ef803 */
/*0570*/ BRA 0x590 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0580*/ MUFU.RCP R5, R3 ; /* 0x0000000300057308 */
/* 0x0000640000001000 */
/*0590*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*05a0*/ MOV R3, R5 ; /* 0x0000000500037202 */
/* 0x003fe20000000f00 */
/*05b0*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*05c0*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffa3004007950 */
/* 0x000fea0003c3ffff */
/*05d0*/ BRA 0x5d0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0600*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0610*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0620*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0630*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0640*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0650*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0660*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0670*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13kApplySigmoidPfS_j
.globl _Z13kApplySigmoidPfS_j
.p2align 8
.type _Z13kApplySigmoidPfS_j,@function
_Z13kApplySigmoidPfS_j:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s4, 0xffff
s_mov_b32 s4, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_2:
v_lshlrev_b64 v[3:4], 2, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cmp_le_u32_e64 s0, s8, v1
global_load_b32 v0, v[5:6], off
s_or_b32 s2, s0, s2
s_waitcnt vmcnt(0)
v_mul_f32_e32 v0, 0xbfb8aa3b, v0
v_exp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_add_f32_e32 v0, 1.0, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_div_scale_f32 v5, null, v0, v0, 1.0
v_div_scale_f32 v7, vcc_lo, 1.0, v0, 1.0
v_rcp_f32_e32 v6, v5
s_waitcnt_depctr 0xfff
v_fma_f32 v8, -v5, v6, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v6
v_mul_f32_e32 v8, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v9, -v5, v8, v7
v_fmac_f32_e32 v8, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, -v5, v8, v7
v_div_fmas_f32 v5, v5, v6, v8
v_add_co_u32 v3, vcc_lo, s6, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_div_fixup_f32 v0, v5, v0, 1.0
global_store_b32 v[3:4], v0, off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13kApplySigmoidPfS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13kApplySigmoidPfS_j, .Lfunc_end0-_Z13kApplySigmoidPfS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13kApplySigmoidPfS_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13kApplySigmoidPfS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012ed47_00000000-6_kApplySigmoid.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j
.type _Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j, @function
_Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j:
.LFB2052:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13kApplySigmoidPfS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j, .-_Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j
.globl _Z13kApplySigmoidPfS_j
.type _Z13kApplySigmoidPfS_j, @function
_Z13kApplySigmoidPfS_j:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13kApplySigmoidPfS_jPfS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z13kApplySigmoidPfS_j, .-_Z13kApplySigmoidPfS_j
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13kApplySigmoidPfS_j"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kApplySigmoidPfS_j(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kApplySigmoid.hip"
.globl _Z28__device_stub__kApplySigmoidPfS_j # -- Begin function _Z28__device_stub__kApplySigmoidPfS_j
.p2align 4, 0x90
.type _Z28__device_stub__kApplySigmoidPfS_j,@function
_Z28__device_stub__kApplySigmoidPfS_j: # @_Z28__device_stub__kApplySigmoidPfS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13kApplySigmoidPfS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z28__device_stub__kApplySigmoidPfS_j, .Lfunc_end0-_Z28__device_stub__kApplySigmoidPfS_j
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kApplySigmoidPfS_j, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kApplySigmoidPfS_j,@object # @_Z13kApplySigmoidPfS_j
.section .rodata,"a",@progbits
.globl _Z13kApplySigmoidPfS_j
.p2align 3, 0x0
_Z13kApplySigmoidPfS_j:
.quad _Z28__device_stub__kApplySigmoidPfS_j
.size _Z13kApplySigmoidPfS_j, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13kApplySigmoidPfS_j"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kApplySigmoidPfS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kApplySigmoidPfS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void ScaleDownDense(float *d_Result, float *d_Data, int width, int pitch, int height, int newpitch)
{
#define BW (SCALEDOWN_W+4)
#define BH (SCALEDOWN_H+4)
#define W2 (SCALEDOWN_W/2)
#define H2 (SCALEDOWN_H/2)
__shared__ float irows[BH*BW];
__shared__ float brows[BH*W2];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int xp = blockIdx.x*SCALEDOWN_W + tx;
const int yp = blockIdx.y*SCALEDOWN_H + ty;
const int xl = min(width-1, max(0, xp-2));
const int yl = min(height-1, max(0, yp-2));
const float k0 = d_ScaleDownKernel[0];
const float k1 = d_ScaleDownKernel[1];
const float k2 = d_ScaleDownKernel[2];
if (xp<(width+4) && yp<(height+4))
irows[BW*ty + tx] = d_Data[yl*pitch + xl];
__syncthreads();
if (yp<(height+4) && tx<W2) {
float *ptr = &irows[BW*ty + 2*tx];
brows[W2*ty + tx] = k0*(ptr[0] + ptr[4]) + k1*(ptr[1] + ptr[3]) + k2*ptr[2];
}
__syncthreads();
const int xs = blockIdx.x*W2 + tx;
const int ys = blockIdx.y*H2 + ty;
if (tx<W2 && ty<H2 && xs<(width/2) && ys<(height/2)) {
float *ptr = &brows[W2*(ty*2) + tx];
d_Result[ys*newpitch + xs] = k0*(ptr[0] + ptr[4*W2]) + k1*(ptr[1*W2] + ptr[3*W2]) + k2*ptr[2*W2];
}
} | code for sm_80
Function : _Z14ScaleDownDensePfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e240000002200 */
/*0050*/ IADD3 R8, R2.reuse, c[0x0][0x178], RZ ; /* 0x00005e0002087a10 */
/* 0x040fe40007ffe0ff */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0070*/ IADD3 R9, R2, c[0x0][0x170], RZ ; /* 0x00005c0002097a10 */
/* 0x000fc60007ffe0ff */
/*0080*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0090*/ LEA R7, R5, R0, 0x4 ; /* 0x0000000005077211 */
/* 0x001fc800078e20ff */
/*00a0*/ ISETP.GE.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R6, R4, 0x40, R3 ; /* 0x0000004004067824 */
/* 0x002fca00078e0203 */
/*00c0*/ ISETP.GE.OR P1, PT, R6, R9, P0 ; /* 0x000000090600720c */
/* 0x000fda0000726670 */
/*00d0*/ @!P1 IADD3 R6, R6, -0x2, RZ ; /* 0xfffffffe06069810 */
/* 0x000fe40007ffe0ff */
/*00e0*/ @!P1 MOV R9, 0x1 ; /* 0x0000000100099802 */
/* 0x000fe40000000f00 */
/*00f0*/ @!P1 IADD3 R7, R7, -0x2, RZ ; /* 0xfffffffe07079810 */
/* 0x000fe40007ffe0ff */
/*0100*/ @!P1 IMNMX R8, RZ, R6, !PT ; /* 0x00000006ff089217 */
/* 0x000fe40007800200 */
/*0110*/ @!P1 IADD3 R6, -R9, c[0x0][0x178], RZ ; /* 0x00005e0009069a10 */
/* 0x000fe40007ffe1ff */
/*0120*/ @!P1 IMNMX R7, RZ, R7, !PT ; /* 0x00000007ff079217 */
/* 0x000fc40007800200 */
/*0130*/ @!P1 IADD3 R9, -R9, c[0x0][0x170], RZ ; /* 0x00005c0009099a10 */
/* 0x000fe40007ffe1ff */
/*0140*/ @!P1 IMNMX R6, R7, R6, PT ; /* 0x0000000607069217 */
/* 0x000fe40003800200 */
/*0150*/ @!P1 IMNMX R9, R8, R9, PT ; /* 0x0000000908099217 */
/* 0x000fca0003800200 */
/*0160*/ @!P1 IMAD R9, R6, c[0x0][0x174], R9 ; /* 0x00005d0006099a24 */
/* 0x000fc800078e0209 */
/*0170*/ @!P1 IMAD.WIDE R8, R9, R2, c[0x0][0x168] ; /* 0x00005a0009089625 */
/* 0x000fcc00078e0202 */
/*0180*/ @!P1 LDG.E R8, [R8.64] ; /* 0x0000000a08089981 */
/* 0x0000a2000c1e1900 */
/*0190*/ @!P1 IMAD R11, R0, 0x44, R3 ; /* 0x00000044000b9824 */
/* 0x000fe200078e0203 */
/*01a0*/ ISETP.GT.OR P0, PT, R3, 0x1f, P0 ; /* 0x0000001f0300780c */
/* 0x000fe20000704670 */
/*01b0*/ UMOV UR8, 0x2 ; /* 0x0000000200087882 */
/* 0x000fe20000000000 */
/*01c0*/ LEA R4, R4, R3, 0x5 ; /* 0x0000000304047211 */
/* 0x000fe200078e28ff */
/*01d0*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*01e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*01f0*/ UIMAD.WIDE.U32 UR4, UR8, UR5, UR4 ; /* 0x00000005080472a5 */
/* 0x000fe2000f8e0004 */
/*0200*/ IMAD R9, R5, 0x8, R0 ; /* 0x0000000805097824 */
/* 0x001fe200078e0200 */
/*0210*/ ULDC UR7, c[0x0][0x178] ; /* 0x00005e0000077ab9 */
/* 0x000fc40000000800 */
/*0220*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe40008000000 */
/*0230*/ @!P0 IMAD R10, R0.reuse, 0x22, R3 ; /* 0x00000022000a8824 */
/* 0x040fe200078e0203 */
/*0240*/ @!P0 LEA R5, R0, R3, 0x5 ; /* 0x0000000300058211 */
/* 0x000fe200078e28ff */
/*0250*/ UIMAD.WIDE.U32 UR6, UR8, UR7, UR6 ; /* 0x00000007080672a5 */
/* 0x000fe4000f8e0006 */
/*0260*/ @!P0 IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a8824 */
/* 0x000fe200078e00ff */
/*0270*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe40008011405 */
/*0280*/ USHF.R.S32.HI UR7, URZ, 0x1, UR7 ; /* 0x000000013f077899 */
/* 0x000fe20008011407 */
/*0290*/ @!P1 STS [R11.X4], R8 ; /* 0x000000080b009388 */
/* 0x004fe80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02b0*/ ISETP.GT.AND P1, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fc80003f24270 */
/*02c0*/ ISETP.GT.OR P1, PT, R0, 0x7, P1 ; /* 0x000000070000780c */
/* 0x000fc80000f24670 */
/*02d0*/ ISETP.GE.OR P1, PT, R4, UR5, P1 ; /* 0x0000000504007c0c */
/* 0x000fc80008f26670 */
/*02e0*/ ISETP.GE.OR P1, PT, R9, UR7, P1 ; /* 0x0000000709007c0c */
/* 0x000fe20008f26670 */
/*02f0*/ @!P0 LDS.64 R14, [R10.X4] ; /* 0x000000000a0e8984 */
/* 0x000fe80000004a00 */
/*0300*/ @!P0 LDS.64 R6, [R10.X4+0x8] ; /* 0x000008000a068984 */
/* 0x000e280000004a00 */
/*0310*/ @!P0 LDS R12, [R10.X4+0x10] ; /* 0x000010000a0c8984 */
/* 0x000e620000004800 */
/*0320*/ @!P0 FADD R7, R7, R15 ; /* 0x0000000f07078221 */
/* 0x001fc40000000000 */
/*0330*/ @!P0 FADD R12, R12, R14 ; /* 0x0000000e0c0c8221 */
/* 0x002fe40000000000 */
/*0340*/ @!P0 FMUL R7, R7, c[0x3][0x4] ; /* 0x00c0010007078a20 */
/* 0x000fc80000400000 */
/*0350*/ @!P0 FFMA R7, R12, c[0x3][0x0], R7 ; /* 0x00c000000c078a23 */
/* 0x000fc80000000007 */
/*0360*/ @!P0 FFMA R6, R6, c[0x3][0x8], R7 ; /* 0x00c0020006068a23 */
/* 0x000fca0000000007 */
/*0370*/ @!P0 STS [R5.X4+0x1540], R6 ; /* 0x0015400605008388 */
/* 0x0001e80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*03a0*/ LEA R0, R0, R3, 0x6 ; /* 0x0000000300007211 */
/* 0x001fe200078e30ff */
/*03b0*/ IMAD R9, R9, c[0x0][0x17c], R4 ; /* 0x00005f0009097a24 */
/* 0x000fc800078e0204 */
/*03c0*/ LDS R5, [R0.X4+0x16c0] ; /* 0x0016c00000057984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R8, [R0.X4+0x15c0] ; /* 0x0015c00000087984 */
/* 0x000e280000004800 */
/*03e0*/ LDS R3, [R0.X4+0x1740] ; /* 0x0017400000037984 */
/* 0x000fe80000004800 */
/*03f0*/ LDS R6, [R0.X4+0x1540] ; /* 0x0015400000067984 */
/* 0x000e680000004800 */
/*0400*/ LDS R7, [R0.X4+0x1640] ; /* 0x0016400000077984 */
/* 0x000ea20000004800 */
/*0410*/ FADD R5, R5, R8 ; /* 0x0000000805057221 */
/* 0x001fc40000000000 */
/*0420*/ FADD R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x002fe40000000000 */
/*0430*/ FMUL R6, R5, c[0x3][0x4] ; /* 0x00c0010005067a20 */
/* 0x000fc80000400000 */
/*0440*/ FFMA R6, R3, c[0x3][0x0], R6 ; /* 0x00c0000003067a23 */
/* 0x000fe40000000006 */
/*0450*/ IMAD.WIDE R2, R9, R2, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x000fc800078e0202 */
/*0460*/ FFMA R7, R7, c[0x3][0x8], R6 ; /* 0x00c0020007077a23 */
/* 0x004fca0000000006 */
/*0470*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c10190a */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void ScaleDownDense(float *d_Result, float *d_Data, int width, int pitch, int height, int newpitch)
{
#define BW (SCALEDOWN_W+4)
#define BH (SCALEDOWN_H+4)
#define W2 (SCALEDOWN_W/2)
#define H2 (SCALEDOWN_H/2)
__shared__ float irows[BH*BW];
__shared__ float brows[BH*W2];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int xp = blockIdx.x*SCALEDOWN_W + tx;
const int yp = blockIdx.y*SCALEDOWN_H + ty;
const int xl = min(width-1, max(0, xp-2));
const int yl = min(height-1, max(0, yp-2));
const float k0 = d_ScaleDownKernel[0];
const float k1 = d_ScaleDownKernel[1];
const float k2 = d_ScaleDownKernel[2];
if (xp<(width+4) && yp<(height+4))
irows[BW*ty + tx] = d_Data[yl*pitch + xl];
__syncthreads();
if (yp<(height+4) && tx<W2) {
float *ptr = &irows[BW*ty + 2*tx];
brows[W2*ty + tx] = k0*(ptr[0] + ptr[4]) + k1*(ptr[1] + ptr[3]) + k2*ptr[2];
}
__syncthreads();
const int xs = blockIdx.x*W2 + tx;
const int ys = blockIdx.y*H2 + ty;
if (tx<W2 && ty<H2 && xs<(width/2) && ys<(height/2)) {
float *ptr = &brows[W2*(ty*2) + tx];
d_Result[ys*newpitch + xs] = k0*(ptr[0] + ptr[4*W2]) + k1*(ptr[1*W2] + ptr[3*W2]) + k2*ptr[2*W2];
}
} | .file "tmpxft_000f375f_00000000-6_ScaleDownDense.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii
.type _Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii, @function
_Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14ScaleDownDensePfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii, .-_Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii
.globl _Z14ScaleDownDensePfS_iiii
.type _Z14ScaleDownDensePfS_iiii, @function
_Z14ScaleDownDensePfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14ScaleDownDensePfS_iiii, .-_Z14ScaleDownDensePfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14ScaleDownDensePfS_iiii"
.LC1:
.string "d_ScaleDownKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14ScaleDownDensePfS_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17d_ScaleDownKernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17d_ScaleDownKernel
.comm _ZL17d_ScaleDownKernel,20,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void ScaleDownDense(float *d_Result, float *d_Data, int width, int pitch, int height, int newpitch)
{
#define BW (SCALEDOWN_W+4)
#define BH (SCALEDOWN_H+4)
#define W2 (SCALEDOWN_W/2)
#define H2 (SCALEDOWN_H/2)
__shared__ float irows[BH*BW];
__shared__ float brows[BH*W2];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int xp = blockIdx.x*SCALEDOWN_W + tx;
const int yp = blockIdx.y*SCALEDOWN_H + ty;
const int xl = min(width-1, max(0, xp-2));
const int yl = min(height-1, max(0, yp-2));
const float k0 = d_ScaleDownKernel[0];
const float k1 = d_ScaleDownKernel[1];
const float k2 = d_ScaleDownKernel[2];
if (xp<(width+4) && yp<(height+4))
irows[BW*ty + tx] = d_Data[yl*pitch + xl];
__syncthreads();
if (yp<(height+4) && tx<W2) {
float *ptr = &irows[BW*ty + 2*tx];
brows[W2*ty + tx] = k0*(ptr[0] + ptr[4]) + k1*(ptr[1] + ptr[3]) + k2*ptr[2];
}
__syncthreads();
const int xs = blockIdx.x*W2 + tx;
const int ys = blockIdx.y*H2 + ty;
if (tx<W2 && ty<H2 && xs<(width/2) && ys<(height/2)) {
float *ptr = &brows[W2*(ty*2) + tx];
d_Result[ys*newpitch + xs] = k0*(ptr[0] + ptr[4*W2]) + k1*(ptr[1*W2] + ptr[3*W2]) + k2*ptr[2*W2];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ScaleDownDense(float *d_Result, float *d_Data, int width, int pitch, int height, int newpitch)
{
#define BW (SCALEDOWN_W+4)
#define BH (SCALEDOWN_H+4)
#define W2 (SCALEDOWN_W/2)
#define H2 (SCALEDOWN_H/2)
__shared__ float irows[BH*BW];
__shared__ float brows[BH*W2];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int xp = blockIdx.x*SCALEDOWN_W + tx;
const int yp = blockIdx.y*SCALEDOWN_H + ty;
const int xl = min(width-1, max(0, xp-2));
const int yl = min(height-1, max(0, yp-2));
const float k0 = d_ScaleDownKernel[0];
const float k1 = d_ScaleDownKernel[1];
const float k2 = d_ScaleDownKernel[2];
if (xp<(width+4) && yp<(height+4))
irows[BW*ty + tx] = d_Data[yl*pitch + xl];
__syncthreads();
if (yp<(height+4) && tx<W2) {
float *ptr = &irows[BW*ty + 2*tx];
brows[W2*ty + tx] = k0*(ptr[0] + ptr[4]) + k1*(ptr[1] + ptr[3]) + k2*ptr[2];
}
__syncthreads();
const int xs = blockIdx.x*W2 + tx;
const int ys = blockIdx.y*H2 + ty;
if (tx<W2 && ty<H2 && xs<(width/2) && ys<(height/2)) {
float *ptr = &brows[W2*(ty*2) + tx];
d_Result[ys*newpitch + xs] = k0*(ptr[0] + ptr[4*W2]) + k1*(ptr[1*W2] + ptr[3*W2]) + k2*ptr[2*W2];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ScaleDownDense(float *d_Result, float *d_Data, int width, int pitch, int height, int newpitch)
{
#define BW (SCALEDOWN_W+4)
#define BH (SCALEDOWN_H+4)
#define W2 (SCALEDOWN_W/2)
#define H2 (SCALEDOWN_H/2)
__shared__ float irows[BH*BW];
__shared__ float brows[BH*W2];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int xp = blockIdx.x*SCALEDOWN_W + tx;
const int yp = blockIdx.y*SCALEDOWN_H + ty;
const int xl = min(width-1, max(0, xp-2));
const int yl = min(height-1, max(0, yp-2));
const float k0 = d_ScaleDownKernel[0];
const float k1 = d_ScaleDownKernel[1];
const float k2 = d_ScaleDownKernel[2];
if (xp<(width+4) && yp<(height+4))
irows[BW*ty + tx] = d_Data[yl*pitch + xl];
__syncthreads();
if (yp<(height+4) && tx<W2) {
float *ptr = &irows[BW*ty + 2*tx];
brows[W2*ty + tx] = k0*(ptr[0] + ptr[4]) + k1*(ptr[1] + ptr[3]) + k2*ptr[2];
}
__syncthreads();
const int xs = blockIdx.x*W2 + tx;
const int ys = blockIdx.y*H2 + ty;
if (tx<W2 && ty<H2 && xs<(width/2) && ys<(height/2)) {
float *ptr = &brows[W2*(ty*2) + tx];
d_Result[ys*newpitch + xs] = k0*(ptr[0] + ptr[4*W2]) + k1*(ptr[1*W2] + ptr[3*W2]) + k2*ptr[2*W2];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14ScaleDownDensePfS_iiii
.globl _Z14ScaleDownDensePfS_iiii
.p2align 8
.type _Z14ScaleDownDensePfS_iiii,@function
_Z14ScaleDownDensePfS_iiii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s10, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_ScaleDownKernel@rel32@lo+4
s_addc_u32 s5, s5, d_ScaleDownKernel@rel32@hi+12
v_lshl_add_u32 v0, s14, 6, v1
v_lshl_add_u32 v3, s15, 4, v2
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, 4
s_add_i32 s6, s10, 4
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s6, v3
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_ScaleDownKernel@rel32@lo+8
s_addc_u32 s7, s7, d_ScaleDownKernel@rel32@hi+16
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, d_ScaleDownKernel@rel32@lo+12
s_addc_u32 s9, s9, d_ScaleDownKernel@rel32@hi+20
s_and_b32 s12, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s11, s12
s_cbranch_execz .LBB0_2
s_load_b32 s16, s[0:1], 0x14
v_max_i32_e32 v3, 2, v3
v_max_i32_e32 v0, 2, v0
s_add_i32 s12, s10, -1
s_add_i32 s13, s3, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, -2, v3
v_add_nc_u32_e32 v0, -2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_i32_e32 v5, s12, v3
v_min_i32_e32 v0, s13, v0
s_load_b64 s[12:13], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, s16, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s12, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_mul_u32_u24_e32 v3, 0x44, v2
v_add_lshl_u32 v3, v3, v1, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v0
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
s_clause 0x2
s_load_b32 s11, s[4:5], 0x0
s_load_b32 s6, s[6:7], 0x0
s_load_b32 s5, s[8:9], 0x0
v_cmp_gt_u32_e32 vcc_lo, 32, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s4, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s4
s_cbranch_execz .LBB0_4
v_mul_u32_u24_e32 v0, 0x44, v2
v_lshlrev_b32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v0, v0, v3, 2
ds_load_2addr_b32 v[3:4], v0 offset1:1
ds_load_2addr_b32 v[5:6], v0 offset0:2 offset1:3
ds_load_b32 v0, v0 offset:16
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v4, v4, v6
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, s6, v4
v_dual_fmac_f32 v3, s11, v0 :: v_dual_lshlrev_b32 v0, 5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v3, s5, v5
v_add_lshl_u32 v0, v0, v1, 2
ds_store_b32 v0, v3 offset:5440
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_lshr_b32 s2, s3, 31
s_lshr_b32 s4, s10, 31
v_lshl_add_u32 v0, s14, 5, v1
v_lshl_add_u32 v3, s15, 3, v2
s_add_i32 s3, s3, s2
s_add_i32 s10, s10, s4
s_ashr_i32 s2, s3, 1
s_ashr_i32 s3, s10, 1
v_cmp_gt_i32_e64 s2, s2, v0
v_cmp_gt_i32_e64 s3, s3, v3
v_cmp_gt_u32_e64 s4, 8, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v2, 6, v2
s_movk_i32 s2, 0x1400
s_movk_i32 s3, 0x1400
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v6, v2, v1, 2
v_add_nc_u32_e32 v1, s2, v6
v_add_nc_u32_e32 v4, s3, v6
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
ds_load_2addr_b32 v[1:2], v1 offset0:80 offset1:112
ds_load_2addr_b32 v[4:5], v4 offset0:144 offset1:176
ds_load_b32 v8, v6 offset:5952
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v3, s2, v[0:1]
v_dual_add_f32 v0, v2, v5 :: v_dual_add_f32 v1, v1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v2, s6, v0
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, s11, v1
v_lshlrev_b64 v[0:1], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, s5, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14ScaleDownDensePfS_iiii
.amdhsa_group_segment_fixed_size 8000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14ScaleDownDensePfS_iiii, .Lfunc_end0-_Z14ScaleDownDensePfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_ScaleDownKernel
.type d_ScaleDownKernel,@object
.section .bss,"aw",@nobits
.globl d_ScaleDownKernel
.p2align 4, 0x0
d_ScaleDownKernel:
.zero 20
.size d_ScaleDownKernel, 20
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_ScaleDownKernel
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8000
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14ScaleDownDensePfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z14ScaleDownDensePfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void ScaleDownDense(float *d_Result, float *d_Data, int width, int pitch, int height, int newpitch)
{
#define BW (SCALEDOWN_W+4)
#define BH (SCALEDOWN_H+4)
#define W2 (SCALEDOWN_W/2)
#define H2 (SCALEDOWN_H/2)
__shared__ float irows[BH*BW];
__shared__ float brows[BH*W2];
const int tx = threadIdx.x;
const int ty = threadIdx.y;
const int xp = blockIdx.x*SCALEDOWN_W + tx;
const int yp = blockIdx.y*SCALEDOWN_H + ty;
const int xl = min(width-1, max(0, xp-2));
const int yl = min(height-1, max(0, yp-2));
const float k0 = d_ScaleDownKernel[0];
const float k1 = d_ScaleDownKernel[1];
const float k2 = d_ScaleDownKernel[2];
if (xp<(width+4) && yp<(height+4))
irows[BW*ty + tx] = d_Data[yl*pitch + xl];
__syncthreads();
if (yp<(height+4) && tx<W2) {
float *ptr = &irows[BW*ty + 2*tx];
brows[W2*ty + tx] = k0*(ptr[0] + ptr[4]) + k1*(ptr[1] + ptr[3]) + k2*ptr[2];
}
__syncthreads();
const int xs = blockIdx.x*W2 + tx;
const int ys = blockIdx.y*H2 + ty;
if (tx<W2 && ty<H2 && xs<(width/2) && ys<(height/2)) {
float *ptr = &brows[W2*(ty*2) + tx];
d_Result[ys*newpitch + xs] = k0*(ptr[0] + ptr[4*W2]) + k1*(ptr[1*W2] + ptr[3*W2]) + k2*ptr[2*W2];
}
} | .text
.file "ScaleDownDense.hip"
.globl _Z29__device_stub__ScaleDownDensePfS_iiii # -- Begin function _Z29__device_stub__ScaleDownDensePfS_iiii
.p2align 4, 0x90
.type _Z29__device_stub__ScaleDownDensePfS_iiii,@function
_Z29__device_stub__ScaleDownDensePfS_iiii: # @_Z29__device_stub__ScaleDownDensePfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14ScaleDownDensePfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z29__device_stub__ScaleDownDensePfS_iiii, .Lfunc_end0-_Z29__device_stub__ScaleDownDensePfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14ScaleDownDensePfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_ScaleDownKernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_ScaleDownKernel,@object # @d_ScaleDownKernel
.local d_ScaleDownKernel
.comm d_ScaleDownKernel,20,16
.type _Z14ScaleDownDensePfS_iiii,@object # @_Z14ScaleDownDensePfS_iiii
.section .rodata,"a",@progbits
.globl _Z14ScaleDownDensePfS_iiii
.p2align 3, 0x0
_Z14ScaleDownDensePfS_iiii:
.quad _Z29__device_stub__ScaleDownDensePfS_iiii
.size _Z14ScaleDownDensePfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14ScaleDownDensePfS_iiii"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_ScaleDownKernel"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__ScaleDownDensePfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_ScaleDownKernel
.addrsig_sym _Z14ScaleDownDensePfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14ScaleDownDensePfS_iiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R5, SR_CTAID.Y ; /* 0x0000000000057919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR10, c[0x0][0x118] ; /* 0x00004600000a7ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e240000002200 */
/*0050*/ IADD3 R8, R2.reuse, c[0x0][0x178], RZ ; /* 0x00005e0002087a10 */
/* 0x040fe40007ffe0ff */
/*0060*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0070*/ IADD3 R9, R2, c[0x0][0x170], RZ ; /* 0x00005c0002097a10 */
/* 0x000fc60007ffe0ff */
/*0080*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e620000002500 */
/*0090*/ LEA R7, R5, R0, 0x4 ; /* 0x0000000005077211 */
/* 0x001fc800078e20ff */
/*00a0*/ ISETP.GE.AND P0, PT, R7, R8, PT ; /* 0x000000080700720c */
/* 0x000fe20003f06270 */
/*00b0*/ IMAD R6, R4, 0x40, R3 ; /* 0x0000004004067824 */
/* 0x002fca00078e0203 */
/*00c0*/ ISETP.GE.OR P1, PT, R6, R9, P0 ; /* 0x000000090600720c */
/* 0x000fda0000726670 */
/*00d0*/ @!P1 IADD3 R6, R6, -0x2, RZ ; /* 0xfffffffe06069810 */
/* 0x000fe40007ffe0ff */
/*00e0*/ @!P1 MOV R9, 0x1 ; /* 0x0000000100099802 */
/* 0x000fe40000000f00 */
/*00f0*/ @!P1 IADD3 R7, R7, -0x2, RZ ; /* 0xfffffffe07079810 */
/* 0x000fe40007ffe0ff */
/*0100*/ @!P1 IMNMX R8, RZ, R6, !PT ; /* 0x00000006ff089217 */
/* 0x000fe40007800200 */
/*0110*/ @!P1 IADD3 R6, -R9, c[0x0][0x178], RZ ; /* 0x00005e0009069a10 */
/* 0x000fe40007ffe1ff */
/*0120*/ @!P1 IMNMX R7, RZ, R7, !PT ; /* 0x00000007ff079217 */
/* 0x000fc40007800200 */
/*0130*/ @!P1 IADD3 R9, -R9, c[0x0][0x170], RZ ; /* 0x00005c0009099a10 */
/* 0x000fe40007ffe1ff */
/*0140*/ @!P1 IMNMX R6, R7, R6, PT ; /* 0x0000000607069217 */
/* 0x000fe40003800200 */
/*0150*/ @!P1 IMNMX R9, R8, R9, PT ; /* 0x0000000908099217 */
/* 0x000fca0003800200 */
/*0160*/ @!P1 IMAD R9, R6, c[0x0][0x174], R9 ; /* 0x00005d0006099a24 */
/* 0x000fc800078e0209 */
/*0170*/ @!P1 IMAD.WIDE R8, R9, R2, c[0x0][0x168] ; /* 0x00005a0009089625 */
/* 0x000fcc00078e0202 */
/*0180*/ @!P1 LDG.E R8, [R8.64] ; /* 0x0000000a08089981 */
/* 0x0000a2000c1e1900 */
/*0190*/ @!P1 IMAD R11, R0, 0x44, R3 ; /* 0x00000044000b9824 */
/* 0x000fe200078e0203 */
/*01a0*/ ISETP.GT.OR P0, PT, R3, 0x1f, P0 ; /* 0x0000001f0300780c */
/* 0x000fe20000704670 */
/*01b0*/ UMOV UR8, 0x2 ; /* 0x0000000200087882 */
/* 0x000fe20000000000 */
/*01c0*/ LEA R4, R4, R3, 0x5 ; /* 0x0000000304047211 */
/* 0x000fe200078e28ff */
/*01d0*/ ULDC UR5, c[0x0][0x170] ; /* 0x00005c0000057ab9 */
/* 0x000fe40000000800 */
/*01e0*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*01f0*/ UIMAD.WIDE.U32 UR4, UR8, UR5, UR4 ; /* 0x00000005080472a5 */
/* 0x000fe2000f8e0004 */
/*0200*/ IMAD R9, R5, 0x8, R0 ; /* 0x0000000805097824 */
/* 0x001fe200078e0200 */
/*0210*/ ULDC UR7, c[0x0][0x178] ; /* 0x00005e0000077ab9 */
/* 0x000fc40000000800 */
/*0220*/ UMOV UR6, URZ ; /* 0x0000003f00067c82 */
/* 0x000fe40008000000 */
/*0230*/ @!P0 IMAD R10, R0.reuse, 0x22, R3 ; /* 0x00000022000a8824 */
/* 0x040fe200078e0203 */
/*0240*/ @!P0 LEA R5, R0, R3, 0x5 ; /* 0x0000000300058211 */
/* 0x000fe200078e28ff */
/*0250*/ UIMAD.WIDE.U32 UR6, UR8, UR7, UR6 ; /* 0x00000007080672a5 */
/* 0x000fe4000f8e0006 */
/*0260*/ @!P0 IMAD.SHL.U32 R10, R10, 0x2, RZ ; /* 0x000000020a0a8824 */
/* 0x000fe200078e00ff */
/*0270*/ USHF.R.S32.HI UR5, URZ, 0x1, UR5 ; /* 0x000000013f057899 */
/* 0x000fe40008011405 */
/*0280*/ USHF.R.S32.HI UR7, URZ, 0x1, UR7 ; /* 0x000000013f077899 */
/* 0x000fe20008011407 */
/*0290*/ @!P1 STS [R11.X4], R8 ; /* 0x000000080b009388 */
/* 0x004fe80000004800 */
/*02a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*02b0*/ ISETP.GT.AND P1, PT, R3, 0x1f, PT ; /* 0x0000001f0300780c */
/* 0x000fc80003f24270 */
/*02c0*/ ISETP.GT.OR P1, PT, R0, 0x7, P1 ; /* 0x000000070000780c */
/* 0x000fc80000f24670 */
/*02d0*/ ISETP.GE.OR P1, PT, R4, UR5, P1 ; /* 0x0000000504007c0c */
/* 0x000fc80008f26670 */
/*02e0*/ ISETP.GE.OR P1, PT, R9, UR7, P1 ; /* 0x0000000709007c0c */
/* 0x000fe20008f26670 */
/*02f0*/ @!P0 LDS.64 R14, [R10.X4] ; /* 0x000000000a0e8984 */
/* 0x000fe80000004a00 */
/*0300*/ @!P0 LDS.64 R6, [R10.X4+0x8] ; /* 0x000008000a068984 */
/* 0x000e280000004a00 */
/*0310*/ @!P0 LDS R12, [R10.X4+0x10] ; /* 0x000010000a0c8984 */
/* 0x000e620000004800 */
/*0320*/ @!P0 FADD R7, R7, R15 ; /* 0x0000000f07078221 */
/* 0x001fc40000000000 */
/*0330*/ @!P0 FADD R12, R12, R14 ; /* 0x0000000e0c0c8221 */
/* 0x002fe40000000000 */
/*0340*/ @!P0 FMUL R7, R7, c[0x3][0x4] ; /* 0x00c0010007078a20 */
/* 0x000fc80000400000 */
/*0350*/ @!P0 FFMA R7, R12, c[0x3][0x0], R7 ; /* 0x00c000000c078a23 */
/* 0x000fc80000000007 */
/*0360*/ @!P0 FFMA R6, R6, c[0x3][0x8], R7 ; /* 0x00c0020006068a23 */
/* 0x000fca0000000007 */
/*0370*/ @!P0 STS [R5.X4+0x1540], R6 ; /* 0x0015400605008388 */
/* 0x0001e80000004800 */
/*0380*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0390*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*03a0*/ LEA R0, R0, R3, 0x6 ; /* 0x0000000300007211 */
/* 0x001fe200078e30ff */
/*03b0*/ IMAD R9, R9, c[0x0][0x17c], R4 ; /* 0x00005f0009097a24 */
/* 0x000fc800078e0204 */
/*03c0*/ LDS R5, [R0.X4+0x16c0] ; /* 0x0016c00000057984 */
/* 0x000fe80000004800 */
/*03d0*/ LDS R8, [R0.X4+0x15c0] ; /* 0x0015c00000087984 */
/* 0x000e280000004800 */
/*03e0*/ LDS R3, [R0.X4+0x1740] ; /* 0x0017400000037984 */
/* 0x000fe80000004800 */
/*03f0*/ LDS R6, [R0.X4+0x1540] ; /* 0x0015400000067984 */
/* 0x000e680000004800 */
/*0400*/ LDS R7, [R0.X4+0x1640] ; /* 0x0016400000077984 */
/* 0x000ea20000004800 */
/*0410*/ FADD R5, R5, R8 ; /* 0x0000000805057221 */
/* 0x001fc40000000000 */
/*0420*/ FADD R3, R3, R6 ; /* 0x0000000603037221 */
/* 0x002fe40000000000 */
/*0430*/ FMUL R6, R5, c[0x3][0x4] ; /* 0x00c0010005067a20 */
/* 0x000fc80000400000 */
/*0440*/ FFMA R6, R3, c[0x3][0x0], R6 ; /* 0x00c0000003067a23 */
/* 0x000fe40000000006 */
/*0450*/ IMAD.WIDE R2, R9, R2, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x000fc800078e0202 */
/*0460*/ FFMA R7, R7, c[0x3][0x8], R6 ; /* 0x00c0020007077a23 */
/* 0x004fca0000000006 */
/*0470*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c10190a */
/*0480*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0490*/ BRA 0x490; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*04a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*04f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0500*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0510*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0520*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14ScaleDownDensePfS_iiii
.globl _Z14ScaleDownDensePfS_iiii
.p2align 8
.type _Z14ScaleDownDensePfS_iiii,@function
_Z14ScaleDownDensePfS_iiii:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x10
s_load_b32 s10, s[0:1], 0x18
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v2, v0, 10, 10
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, d_ScaleDownKernel@rel32@lo+4
s_addc_u32 s5, s5, d_ScaleDownKernel@rel32@hi+12
v_lshl_add_u32 v0, s14, 6, v1
v_lshl_add_u32 v3, s15, 4, v2
s_waitcnt lgkmcnt(0)
s_add_i32 s2, s3, 4
s_add_i32 s6, s10, 4
v_cmp_gt_i32_e32 vcc_lo, s2, v0
v_cmp_gt_i32_e64 s2, s6, v3
s_getpc_b64 s[6:7]
s_add_u32 s6, s6, d_ScaleDownKernel@rel32@lo+8
s_addc_u32 s7, s7, d_ScaleDownKernel@rel32@hi+16
s_getpc_b64 s[8:9]
s_add_u32 s8, s8, d_ScaleDownKernel@rel32@lo+12
s_addc_u32 s9, s9, d_ScaleDownKernel@rel32@hi+20
s_and_b32 s12, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s11, s12
s_cbranch_execz .LBB0_2
s_load_b32 s16, s[0:1], 0x14
v_max_i32_e32 v3, 2, v3
v_max_i32_e32 v0, 2, v0
s_add_i32 s12, s10, -1
s_add_i32 s13, s3, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v3, -2, v3
v_add_nc_u32_e32 v0, -2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_min_i32_e32 v5, s12, v3
v_min_i32_e32 v0, s13, v0
s_load_b64 s[12:13], s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v5, s16, v[0:1]
v_ashrrev_i32_e32 v4, 31, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
v_add_co_u32 v3, vcc_lo, s12, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v4, vcc_lo, s13, v4, vcc_lo
global_load_b32 v0, v[3:4], off
v_mul_u32_u24_e32 v3, 0x44, v2
v_add_lshl_u32 v3, v3, v1, 2
s_waitcnt vmcnt(0)
ds_store_b32 v3, v0
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s11
s_clause 0x2
s_load_b32 s11, s[4:5], 0x0
s_load_b32 s6, s[6:7], 0x0
s_load_b32 s5, s[8:9], 0x0
v_cmp_gt_u32_e32 vcc_lo, 32, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s4, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s2, s4
s_cbranch_execz .LBB0_4
v_mul_u32_u24_e32 v0, 0x44, v2
v_lshlrev_b32_e32 v3, 1, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_lshl_u32 v0, v0, v3, 2
ds_load_2addr_b32 v[3:4], v0 offset1:1
ds_load_2addr_b32 v[5:6], v0 offset0:2 offset1:3
ds_load_b32 v0, v0 offset:16
s_waitcnt lgkmcnt(1)
v_add_f32_e32 v4, v4, v6
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v0, v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v3, s6, v4
v_dual_fmac_f32 v3, s11, v0 :: v_dual_lshlrev_b32 v0, 5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v3, s5, v5
v_add_lshl_u32 v0, v0, v1, 2
ds_store_b32 v0, v3 offset:5440
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s2
s_lshr_b32 s2, s3, 31
s_lshr_b32 s4, s10, 31
v_lshl_add_u32 v0, s14, 5, v1
v_lshl_add_u32 v3, s15, 3, v2
s_add_i32 s3, s3, s2
s_add_i32 s10, s10, s4
s_ashr_i32 s2, s3, 1
s_ashr_i32 s3, s10, 1
v_cmp_gt_i32_e64 s2, s2, v0
v_cmp_gt_i32_e64 s3, s3, v3
v_cmp_gt_u32_e64 s4, 8, v2
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s2, s2, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
v_lshlrev_b32_e32 v2, 6, v2
s_movk_i32 s2, 0x1400
s_movk_i32 s3, 0x1400
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_lshl_u32 v6, v2, v1, 2
v_add_nc_u32_e32 v1, s2, v6
v_add_nc_u32_e32 v4, s3, v6
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b64 s[0:1], s[0:1], 0x0
ds_load_2addr_b32 v[1:2], v1 offset0:80 offset1:112
ds_load_2addr_b32 v[4:5], v4 offset0:144 offset1:176
ds_load_b32 v8, v6 offset:5952
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[6:7], null, v3, s2, v[0:1]
v_dual_add_f32 v0, v2, v5 :: v_dual_add_f32 v1, v1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v2, s6, v0
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, s11, v1
v_lshlrev_b64 v[0:1], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, s5, v4
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14ScaleDownDensePfS_iiii
.amdhsa_group_segment_fixed_size 8000
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 17
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14ScaleDownDensePfS_iiii, .Lfunc_end0-_Z14ScaleDownDensePfS_iiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected d_ScaleDownKernel
.type d_ScaleDownKernel,@object
.section .bss,"aw",@nobits
.globl d_ScaleDownKernel
.p2align 4, 0x0
d_ScaleDownKernel:
.zero 20
.size d_ScaleDownKernel, 20
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym d_ScaleDownKernel
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8000
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14ScaleDownDensePfS_iiii
.private_segment_fixed_size: 0
.sgpr_count: 19
.sgpr_spill_count: 0
.symbol: _Z14ScaleDownDensePfS_iiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f375f_00000000-6_ScaleDownDense.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii
.type _Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii, @function
_Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14ScaleDownDensePfS_iiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii, .-_Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii
.globl _Z14ScaleDownDensePfS_iiii
.type _Z14ScaleDownDensePfS_iiii, @function
_Z14ScaleDownDensePfS_iiii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z14ScaleDownDensePfS_iiiiPfS_iiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14ScaleDownDensePfS_iiii, .-_Z14ScaleDownDensePfS_iiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14ScaleDownDensePfS_iiii"
.LC1:
.string "d_ScaleDownKernel"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14ScaleDownDensePfS_iiii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $20, %r9d
movl $0, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17d_ScaleDownKernel(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17d_ScaleDownKernel
.comm _ZL17d_ScaleDownKernel,20,16
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ScaleDownDense.hip"
.globl _Z29__device_stub__ScaleDownDensePfS_iiii # -- Begin function _Z29__device_stub__ScaleDownDensePfS_iiii
.p2align 4, 0x90
.type _Z29__device_stub__ScaleDownDensePfS_iiii,@function
_Z29__device_stub__ScaleDownDensePfS_iiii: # @_Z29__device_stub__ScaleDownDensePfS_iiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14ScaleDownDensePfS_iiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z29__device_stub__ScaleDownDensePfS_iiii, .Lfunc_end0-_Z29__device_stub__ScaleDownDensePfS_iiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14ScaleDownDensePfS_iiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $0, 8(%rsp)
movl $1, (%rsp)
movl $d_ScaleDownKernel, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $20, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
callq __hipRegisterVar
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type d_ScaleDownKernel,@object # @d_ScaleDownKernel
.local d_ScaleDownKernel
.comm d_ScaleDownKernel,20,16
.type _Z14ScaleDownDensePfS_iiii,@object # @_Z14ScaleDownDensePfS_iiii
.section .rodata,"a",@progbits
.globl _Z14ScaleDownDensePfS_iiii
.p2align 3, 0x0
_Z14ScaleDownDensePfS_iiii:
.quad _Z29__device_stub__ScaleDownDensePfS_iiii
.size _Z14ScaleDownDensePfS_iiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14ScaleDownDensePfS_iiii"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "d_ScaleDownKernel"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__ScaleDownDensePfS_iiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym d_ScaleDownKernel
.addrsig_sym _Z14ScaleDownDensePfS_iiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <vector>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addShared(int * v0, std::size_t size){
extern __shared__ int v0tmp[];
auto tid = blockIdx.x * blockDim.x + threadIdx.x;
v0tmp[tid] = v0[tid];
__syncthreads();
if(tid>0 && tid<size - 1){
v0tmp[tid] += v0tmp[tid-1] + v0tmp[tid+1];
v0[tid] = v0tmp[tid];
}
}
int main(int argc, char const *argv[]) {
std::size_t size = 1024;
std::vector<int> v0(size);
int * v0_d = nullptr;
for(std::size_t i = 0; i < v0.size(); i++){
v0[i] = 1;
}
cudaMalloc(&v0_d, v0.size() * sizeof(int));
cudaMemcpy(v0_d,v0.data(),v0.size() * sizeof(int),cudaMemcpyHostToDevice);
addShared<<<1,1024, 1024 * sizeof(int) >>>(v0_d,v0.size());
cudaDeviceSynchronize();
cudaMemcpy(v0.data(),v0_d,v0.size() * sizeof(int),cudaMemcpyDeviceToHost);
for(std::size_t i = 0; i < v0.size(); i++){
printf("%d\n",v0[i] );
}
cudaFree(v0_d);
return 1;
} | code for sm_80
Function : _Z9addSharedPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0060*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0005 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000802057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ UIADD3 UR4, UP0, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fc8000ff1e13f */
/*00b0*/ UIADD3.X UR5, UR7, -0x1, URZ, UP0, !UPT ; /* 0xffffffff07057890 */
/* 0x000fe400087fe43f */
/*00c0*/ ISETP.LT.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc8000bf01070 */
/*00d0*/ IMAD.U32 R4, RZ, RZ, UR5 ; /* 0x00000005ff047e24 */
/* 0x000fca000f8e00ff */
/*00e0*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fc80003f04100 */
/*00f0*/ ISETP.EQ.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fe20004702670 */
/*0100*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0041e80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0120*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0130*/ LDS R4, [R0.X4+0x4] ; /* 0x0000040000047984 */
/* 0x001fe80000004800 */
/*0140*/ LDS R5, [R0.X4+-0x4] ; /* 0xfffffc0000057984 */
/* 0x000fe80000004800 */
/*0150*/ LDS R6, [R0.X4] ; /* 0x0000000000067984 */
/* 0x000e240000004800 */
/*0160*/ IADD3 R5, R6, R4, R5 ; /* 0x0000000406057210 */
/* 0x001fca0007ffe005 */
/*0170*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101908 */
/*0180*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x000fe20000004800 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include <vector>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addShared(int * v0, std::size_t size){
extern __shared__ int v0tmp[];
auto tid = blockIdx.x * blockDim.x + threadIdx.x;
v0tmp[tid] = v0[tid];
__syncthreads();
if(tid>0 && tid<size - 1){
v0tmp[tid] += v0tmp[tid-1] + v0tmp[tid+1];
v0[tid] = v0tmp[tid];
}
}
int main(int argc, char const *argv[]) {
std::size_t size = 1024;
std::vector<int> v0(size);
int * v0_d = nullptr;
for(std::size_t i = 0; i < v0.size(); i++){
v0[i] = 1;
}
cudaMalloc(&v0_d, v0.size() * sizeof(int));
cudaMemcpy(v0_d,v0.data(),v0.size() * sizeof(int),cudaMemcpyHostToDevice);
addShared<<<1,1024, 1024 * sizeof(int) >>>(v0_d,v0.size());
cudaDeviceSynchronize();
cudaMemcpy(v0.data(),v0_d,v0.size() * sizeof(int),cudaMemcpyDeviceToHost);
for(std::size_t i = 0; i < v0.size(); i++){
printf("%d\n",v0[i] );
}
cudaFree(v0_d);
return 1;
} | .file "tmpxft_0018eae0_00000000-6_addShared.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9addSharedPimPim
.type _Z29__device_stub__Z9addSharedPimPim, @function
_Z29__device_stub__Z9addSharedPimPim:
.LFB4057:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addSharedPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z29__device_stub__Z9addSharedPimPim, .-_Z29__device_stub__Z9addSharedPimPim
.globl _Z9addSharedPim
.type _Z9addSharedPim, @function
_Z9addSharedPim:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9addSharedPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z9addSharedPim, .-_Z9addSharedPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4096, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %r12
leaq 4096(%rax), %rdx
movl $0, (%rax)
leaq 4(%rax), %rax
.L12:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq $0, 8(%rsp)
movq %r12, %rbx
leaq 4096(%r12), %rbp
movq %r12, %rax
.L13:
movl $1, (%rax)
addq $4, %rax
cmpq %rax, %rbp
jne .L13
leaq 8(%rsp), %rdi
movl $4096, %esi
.LEHB1:
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl $1024, %esi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z9addSharedPimPim
.L14:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %r13
jmp .L15
.L26:
addq $4, %rbx
cmpq %rbp, %rbx
je .L25
.L15:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L25:
movq 8(%rsp), %rdi
call cudaFree@PLT
.LEHE1:
movl $4096, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $1, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
endbr64
movq %rax, %rbx
movl $4096, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L19-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9addSharedPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addSharedPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <vector>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addShared(int * v0, std::size_t size){
extern __shared__ int v0tmp[];
auto tid = blockIdx.x * blockDim.x + threadIdx.x;
v0tmp[tid] = v0[tid];
__syncthreads();
if(tid>0 && tid<size - 1){
v0tmp[tid] += v0tmp[tid-1] + v0tmp[tid+1];
v0[tid] = v0tmp[tid];
}
}
int main(int argc, char const *argv[]) {
std::size_t size = 1024;
std::vector<int> v0(size);
int * v0_d = nullptr;
for(std::size_t i = 0; i < v0.size(); i++){
v0[i] = 1;
}
cudaMalloc(&v0_d, v0.size() * sizeof(int));
cudaMemcpy(v0_d,v0.data(),v0.size() * sizeof(int),cudaMemcpyHostToDevice);
addShared<<<1,1024, 1024 * sizeof(int) >>>(v0_d,v0.size());
cudaDeviceSynchronize();
cudaMemcpy(v0.data(),v0_d,v0.size() * sizeof(int),cudaMemcpyDeviceToHost);
for(std::size_t i = 0; i < v0.size(); i++){
printf("%d\n",v0[i] );
}
cudaFree(v0_d);
return 1;
} | #include <iostream>
#include <vector>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addShared(int * v0, std::size_t size){
extern __shared__ int v0tmp[];
auto tid = blockIdx.x * blockDim.x + threadIdx.x;
v0tmp[tid] = v0[tid];
__syncthreads();
if(tid>0 && tid<size - 1){
v0tmp[tid] += v0tmp[tid-1] + v0tmp[tid+1];
v0[tid] = v0tmp[tid];
}
}
int main(int argc, char const *argv[]) {
std::size_t size = 1024;
std::vector<int> v0(size);
int * v0_d = nullptr;
for(std::size_t i = 0; i < v0.size(); i++){
v0[i] = 1;
}
hipMalloc(&v0_d, v0.size() * sizeof(int));
hipMemcpy(v0_d,v0.data(),v0.size() * sizeof(int),hipMemcpyHostToDevice);
addShared<<<1,1024, 1024 * sizeof(int) >>>(v0_d,v0.size());
hipDeviceSynchronize();
hipMemcpy(v0.data(),v0_d,v0.size() * sizeof(int),hipMemcpyDeviceToHost);
for(std::size_t i = 0; i < v0.size(); i++){
printf("%d\n",v0[i] );
}
hipFree(v0_d);
return 1;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <vector>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addShared(int * v0, std::size_t size){
extern __shared__ int v0tmp[];
auto tid = blockIdx.x * blockDim.x + threadIdx.x;
v0tmp[tid] = v0[tid];
__syncthreads();
if(tid>0 && tid<size - 1){
v0tmp[tid] += v0tmp[tid-1] + v0tmp[tid+1];
v0[tid] = v0tmp[tid];
}
}
int main(int argc, char const *argv[]) {
std::size_t size = 1024;
std::vector<int> v0(size);
int * v0_d = nullptr;
for(std::size_t i = 0; i < v0.size(); i++){
v0[i] = 1;
}
hipMalloc(&v0_d, v0.size() * sizeof(int));
hipMemcpy(v0_d,v0.data(),v0.size() * sizeof(int),hipMemcpyHostToDevice);
addShared<<<1,1024, 1024 * sizeof(int) >>>(v0_d,v0.size());
hipDeviceSynchronize();
hipMemcpy(v0.data(),v0_d,v0.size() * sizeof(int),hipMemcpyDeviceToHost);
for(std::size_t i = 0; i < v0.size(); i++){
printf("%d\n",v0[i] );
}
hipFree(v0_d);
return 1;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addSharedPim
.globl _Z9addSharedPim
.p2align 8
.type _Z9addSharedPim,@function
_Z9addSharedPim:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_u32 s0, s2, -1
s_addc_u32 s1, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[2:3]
global_load_b32 v4, v[0:1], off
v_cmp_ne_u32_e64 s0, 0, v2
v_lshl_add_u32 v2, v2, 2, 0
s_and_b32 s0, s0, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v5, -4, v2
ds_load_2addr_b32 v[3:4], v2 offset1:1
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_add3_u32 v3, v4, v5, v3
ds_store_b32 v2, v3
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addSharedPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addSharedPim, .Lfunc_end0-_Z9addSharedPim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addSharedPim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addSharedPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <iostream>
#include <vector>
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__ void addShared(int * v0, std::size_t size){
extern __shared__ int v0tmp[];
auto tid = blockIdx.x * blockDim.x + threadIdx.x;
v0tmp[tid] = v0[tid];
__syncthreads();
if(tid>0 && tid<size - 1){
v0tmp[tid] += v0tmp[tid-1] + v0tmp[tid+1];
v0[tid] = v0tmp[tid];
}
}
int main(int argc, char const *argv[]) {
std::size_t size = 1024;
std::vector<int> v0(size);
int * v0_d = nullptr;
for(std::size_t i = 0; i < v0.size(); i++){
v0[i] = 1;
}
hipMalloc(&v0_d, v0.size() * sizeof(int));
hipMemcpy(v0_d,v0.data(),v0.size() * sizeof(int),hipMemcpyHostToDevice);
addShared<<<1,1024, 1024 * sizeof(int) >>>(v0_d,v0.size());
hipDeviceSynchronize();
hipMemcpy(v0.data(),v0_d,v0.size() * sizeof(int),hipMemcpyDeviceToHost);
for(std::size_t i = 0; i < v0.size(); i++){
printf("%d\n",v0[i] );
}
hipFree(v0_d);
return 1;
} | .text
.file "addShared.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addSharedPim # -- Begin function _Z24__device_stub__addSharedPim
.p2align 4, 0x90
.type _Z24__device_stub__addSharedPim,@function
_Z24__device_stub__addSharedPim: # @_Z24__device_stub__addSharedPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addSharedPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__addSharedPim, .Lfunc_end0-_Z24__device_stub__addSharedPim
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
.cfi_escape 0x2e, 0x00
movl $4096, %edi # imm = 0x1000
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
xorl %r14d, %r14d
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq $0, 8(%rsp)
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%r14,4)
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB1_1
# %bb.2:
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
.Ltmp1:
# %bb.3: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movq 8(%rsp), %rdi
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp3:
# %bb.4:
.Ltmp4:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp5:
# %bb.5:
testl %eax, %eax
jne .LBB1_8
# %bb.6:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq $1024, 64(%rsp) # imm = 0x400
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp7:
# %bb.7: # %.noexc
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
.Ltmp8:
.cfi_escape 0x2e, 0x10
leaq 80(%rsp), %r9
movl $_Z9addSharedPim, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp9:
.LBB1_8:
.Ltmp10:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp11:
# %bb.9:
movq 8(%rsp), %rsi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.10: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB1_11
# %bb.12:
movq 8(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp15:
# %bb.13: # %_ZNSt6vectorIiSaIiEED2Ev.exit17
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
movl $1, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_14: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.cfi_def_cfa_offset 128
.Ltmp16:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp15-.Ltmp0 # Call between .Ltmp0 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end1-.Ltmp15 # Call between .Ltmp15 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addSharedPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addSharedPim,@object # @_Z9addSharedPim
.section .rodata,"a",@progbits
.globl _Z9addSharedPim
.p2align 3, 0x0
_Z9addSharedPim:
.quad _Z24__device_stub__addSharedPim
.size _Z9addSharedPim, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addSharedPim"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addSharedPim
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9addSharedPim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9addSharedPim
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR8, c[0x0][0x118] ; /* 0x0000460000087ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe40000000000 */
/*0060*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD.WIDE.U32 R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0005 */
/*0090*/ LDG.E R5, [R2.64] ; /* 0x0000000802057981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ UIADD3 UR4, UP0, -UR4, UR6, URZ ; /* 0x0000000604047290 */
/* 0x000fc8000ff1e13f */
/*00b0*/ UIADD3.X UR5, UR7, -0x1, URZ, UP0, !UPT ; /* 0xffffffff07057890 */
/* 0x000fe400087fe43f */
/*00c0*/ ISETP.LT.U32.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fc8000bf01070 */
/*00d0*/ IMAD.U32 R4, RZ, RZ, UR5 ; /* 0x00000005ff047e24 */
/* 0x000fca000f8e00ff */
/*00e0*/ ISETP.GT.U32.AND.EX P0, PT, R4, RZ, PT, P0 ; /* 0x000000ff0400720c */
/* 0x000fc80003f04100 */
/*00f0*/ ISETP.EQ.OR P0, PT, R0, RZ, !P0 ; /* 0x000000ff0000720c */
/* 0x000fe20004702670 */
/*0100*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x0041e80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000ff00000010000 */
/*0120*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0130*/ LDS R4, [R0.X4+0x4] ; /* 0x0000040000047984 */
/* 0x001fe80000004800 */
/*0140*/ LDS R5, [R0.X4+-0x4] ; /* 0xfffffc0000057984 */
/* 0x000fe80000004800 */
/*0150*/ LDS R6, [R0.X4] ; /* 0x0000000000067984 */
/* 0x000e240000004800 */
/*0160*/ IADD3 R5, R6, R4, R5 ; /* 0x0000000406057210 */
/* 0x001fca0007ffe005 */
/*0170*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101908 */
/*0180*/ STS [R0.X4], R5 ; /* 0x0000000500007388 */
/* 0x000fe20000004800 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addSharedPim
.globl _Z9addSharedPim
.p2align 8
.type _Z9addSharedPim,@function
_Z9addSharedPim:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[0:1]
v_mov_b32_e32 v3, 0
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_add_u32 s0, s2, -1
s_addc_u32 s1, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[2:3]
global_load_b32 v4, v[0:1], off
v_cmp_ne_u32_e64 s0, 0, v2
v_lshl_add_u32 v2, v2, 2, 0
s_and_b32 s0, s0, vcc_lo
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_add_nc_u32_e32 v5, -4, v2
ds_load_2addr_b32 v[3:4], v2 offset1:1
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_add3_u32 v3, v4, v5, v3
ds_store_b32 v2, v3
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addSharedPim
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addSharedPim, .Lfunc_end0-_Z9addSharedPim
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
- .offset: 136
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addSharedPim
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9addSharedPim.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0018eae0_00000000-6_addShared.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4035:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4035:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z9addSharedPimPim
.type _Z29__device_stub__Z9addSharedPimPim, @function
_Z29__device_stub__Z9addSharedPimPim:
.LFB4057:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addSharedPim(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4057:
.size _Z29__device_stub__Z9addSharedPimPim, .-_Z29__device_stub__Z9addSharedPimPim
.globl _Z9addSharedPim
.type _Z9addSharedPim, @function
_Z9addSharedPim:
.LFB4058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z9addSharedPimPim
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4058:
.size _Z9addSharedPim, .-_Z9addSharedPim
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "%d\n"
.text
.globl main
.type main, @function
main:
.LFB4032:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA4032
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl $4096, %edi
.LEHB0:
call _Znwm@PLT
.LEHE0:
movq %rax, %r12
leaq 4096(%rax), %rdx
movl $0, (%rax)
leaq 4(%rax), %rax
.L12:
movl $0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L12
movq $0, 8(%rsp)
movq %r12, %rbx
leaq 4096(%r12), %rbp
movq %r12, %rax
.L13:
movl $1, (%rax)
addq $4, %rax
cmpq %rax, %rbp
jne .L13
leaq 8(%rsp), %rdi
movl $4096, %esi
.LEHB1:
call cudaMalloc@PLT
movl $1, %ecx
movl $4096, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $0, %r9d
movl $4096, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L14
movl $1024, %esi
movq 8(%rsp), %rdi
call _Z29__device_stub__Z9addSharedPimPim
.L14:
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movl $4096, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %r13
jmp .L15
.L26:
addq $4, %rbx
cmpq %rbp, %rbx
je .L25
.L15:
movl (%rbx), %edx
movq %r13, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L26
.L25:
movq 8(%rsp), %rdi
call cudaFree@PLT
.LEHE1:
movl $4096, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L27
movl $1, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
endbr64
movq %rax, %rbx
movl $4096, %esi
movq %r12, %rdi
call _ZdlPvm@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
je .L17
call __stack_chk_fail@PLT
.L17:
movq %rbx, %rdi
.LEHB2:
call _Unwind_Resume@PLT
.LEHE2:
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4032:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA4032:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE4032-.LLSDACSB4032
.LLSDACSB4032:
.uleb128 .LEHB0-.LFB4032
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB4032
.uleb128 .LEHE1-.LEHB1
.uleb128 .L19-.LFB4032
.uleb128 0
.uleb128 .LEHB2-.LFB4032
.uleb128 .LEHE2-.LEHB2
.uleb128 0
.uleb128 0
.LLSDACSE4032:
.text
.size main, .-main
.section .rodata.str1.1
.LC1:
.string "_Z9addSharedPim"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addSharedPim(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "addShared.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__addSharedPim # -- Begin function _Z24__device_stub__addSharedPim
.p2align 4, 0x90
.type _Z24__device_stub__addSharedPim,@function
_Z24__device_stub__addSharedPim: # @_Z24__device_stub__addSharedPim
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addSharedPim, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__addSharedPim, .Lfunc_end0-_Z24__device_stub__addSharedPim
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt6vectorIiSaIiEEC2EmRKS0_.exit
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
.cfi_escape 0x2e, 0x00
movl $4096, %edi # imm = 0x1000
callq _Znwm
movq %rax, %rbx
.cfi_escape 0x2e, 0x00
xorl %r14d, %r14d
movl $4096, %edx # imm = 0x1000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
movq $0, 8(%rsp)
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movl $1, (%rbx,%r14,4)
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB1_1
# %bb.2:
.Ltmp0:
.cfi_escape 0x2e, 0x00
leaq 8(%rsp), %rdi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
.Ltmp1:
# %bb.3: # %_ZL9hipMallocIiE10hipError_tPPT_m.exit
movq 8(%rsp), %rdi
.Ltmp2:
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
.Ltmp3:
# %bb.4:
.Ltmp4:
.cfi_escape 0x2e, 0x00
movabsq $4294967297, %rdi # imm = 0x100000001
movabsq $4294968320, %rdx # imm = 0x100000400
movl $4096, %r8d # imm = 0x1000
movl $1, %esi
movl $1, %ecx
xorl %r9d, %r9d
callq __hipPushCallConfiguration
.Ltmp5:
# %bb.5:
testl %eax, %eax
jne .LBB1_8
# %bb.6:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq $1024, 64(%rsp) # imm = 0x400
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
.Ltmp6:
.cfi_escape 0x2e, 0x00
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
.Ltmp7:
# %bb.7: # %.noexc
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
.Ltmp8:
.cfi_escape 0x2e, 0x10
leaq 80(%rsp), %r9
movl $_Z9addSharedPim, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.Ltmp9:
.LBB1_8:
.Ltmp10:
.cfi_escape 0x2e, 0x00
callq hipDeviceSynchronize
.Ltmp11:
# %bb.9:
movq 8(%rsp), %rsi
.Ltmp12:
.cfi_escape 0x2e, 0x00
movl $4096, %edx # imm = 0x1000
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
.Ltmp13:
# %bb.10: # %.preheader.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB1_11: # %.preheader
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
.cfi_escape 0x2e, 0x00
movl $.L.str, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $1024, %r14 # imm = 0x400
jne .LBB1_11
# %bb.12:
movq 8(%rsp), %rdi
.Ltmp14:
.cfi_escape 0x2e, 0x00
callq hipFree
.Ltmp15:
# %bb.13: # %_ZNSt6vectorIiSaIiEED2Ev.exit17
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
movl $1, %eax
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB1_14: # %_ZNSt6vectorIiSaIiEED2Ev.exit
.cfi_def_cfa_offset 128
.Ltmp16:
movq %rax, %r14
.cfi_escape 0x2e, 0x00
movq %rbx, %rdi
callq _ZdlPv
.cfi_escape 0x2e, 0x00
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table1:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Lfunc_begin0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp0-.Lfunc_begin0 # Call between .Lfunc_begin0 and .Ltmp0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp15-.Ltmp0 # Call between .Ltmp0 and .Ltmp15
.uleb128 .Ltmp16-.Lfunc_begin0 # jumps to .Ltmp16
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Lfunc_end1-.Ltmp15 # Call between .Ltmp15 and .Lfunc_end1
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addSharedPim, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9addSharedPim,@object # @_Z9addSharedPim
.section .rodata,"a",@progbits
.globl _Z9addSharedPim
.p2align 3, 0x0
_Z9addSharedPim:
.quad _Z24__device_stub__addSharedPim
.size _Z9addSharedPim, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%d\n"
.size .L.str, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addSharedPim"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addSharedPim
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Unwind_Resume
.addrsig_sym _Z9addSharedPim
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cstdio>
#include <ctime>
#include <iostream>
#define TILE_WIDTH 32
#define H 100000
#define W 100000
using namespace std;
void foo(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
v[i * W + j] = 2;
}
}
}
void mult(float* A, float* B, float* C) {
int aux = 0;
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
aux = 0;
for (int k = 0; k < W; k++) aux += A[i * W + k] * B[k * W + j];
C[i * W + j] = aux;
}
}
}
void mostrar(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
cout << v[i * W + j] << " ";
}
cout << endl;
}
}
__global__ void multMat(float* d_A, float* d_B, float* d_C) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
int Pvalue = 0;
for (size_t phase = 0; phase < W / TILE_WIDTH; phase++) {
ds_A[ty][tx] = d_A[row * W + phase * TILE_WIDTH + tx];
ds_B[ty][tx] = d_B[(phase * TILE_WIDTH + ty) * W + col];
__syncthreads();
for (int k = 0; k < W; k++) {
Pvalue += ds_A[ty][k] * ds_B[k][tx];
}
__syncthreads();
}
d_C[col * W + row] = Pvalue;
}
int main() {
float* A = new float[H * W];
float* B = new float[H * W];
float* C = new float[H * W];
float* D = new float[H * W];
foo(A);
foo(B);
// {
// clock_t start = clock();
//
// mult(A, B, C);
//
// clock_t end = clock();
// double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
// printf("Tiempo invertido CPU = %lf s\n", cpu_time_used);
// }
float *d_A, *d_B, *d_D;
float blockSize = TILE_WIDTH;
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(ceil(W / float(blockSize)), ceil(H / float(blockSize)), 1);
cudaMalloc((void**)&d_A, sizeof(float) * H * W);
cudaMalloc((void**)&d_B, sizeof(float) * H * W);
cudaMalloc((void**)&d_D, sizeof(float) * H * W);
{
clock_t start = clock();
cudaMemcpy(d_A, A, sizeof(float) * H * W, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, sizeof(float) * H * W, cudaMemcpyHostToDevice);
multMat<<<dimGrid, dimBlock>>>(d_A, d_B, d_D);
cudaMemcpy(D, d_D, sizeof(float) * H * W, cudaMemcpyDeviceToHost);
clock_t end = clock();
double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
std::cout << "Tiempo invertido GPU = " << cpu_time_used << "s\n";
}
delete A;
delete B;
delete C;
delete D;
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_D);
} | code for sm_80
Function : _Z7multMatPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0070*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0090*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000ea20000002500 */
/*00a0*/ IMAD R13, R13, c[0x0][0x4], R0 ; /* 0x000001000d0d7a24 */
/* 0x001fe200078e0200 */
/*00b0*/ LEA R15, R0, 0x20, 0x7 ; /* 0x00000020000f7811 */
/* 0x000fc600078e38ff */
/*00c0*/ IMAD R12, R13, 0x186a0, RZ ; /* 0x000186a00d0c7824 */
/* 0x000fe200078e02ff */
/*00d0*/ SHF.R.S32.HI R5, RZ, 0x1f, R3.reuse ; /* 0x0000001fff057819 */
/* 0x102fe20000011403 */
/*00e0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x004fc600078e0203 */
/*00f0*/ IADD3 R21, P0, R12.reuse, R3, RZ ; /* 0x000000030c157210 */
/* 0x040fe40007f1e0ff */
/*0100*/ SHF.L.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037819 */
/* 0x000fe400000006ff */
/*0110*/ LEA.HI.X.SX32 R12, R12, R5, 0x1, P0 ; /* 0x000000050c0c7211 */
/* 0x000fe400000f0eff */
/*0120*/ IADD3 R14, R3, 0x1400, RZ ; /* 0x00001400030e7810 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD R16, R0, 0x80, R3 ; /* 0x0000008000107824 */
/* 0x000fe200078e0203 */
/*0140*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0150*/ USHF.L.U32 UR8, UR4, 0x5, URZ ; /* 0x0000000504087899 */
/* 0x000fe4000800063f */
/*0160*/ USHF.L.U64.HI UR9, UR4, 0x5, UR5 ; /* 0x0000000504097899 */
/* 0x000fc80008010205 */
/*0170*/ IADD3 R9, P0, R0, UR8, RZ ; /* 0x0000000800097c10 */
/* 0x000fc8000ff1e0ff */
/*0180*/ LEA.HI.X.SX32 R4, R0, UR9, 0x1, P0 ; /* 0x0000000900047c11 */
/* 0x000fe200080f0eff */
/*0190*/ IMAD.WIDE.U32 R8, R9, 0x186a0, R2 ; /* 0x000186a009087825 */
/* 0x000fe200078e0002 */
/*01a0*/ IADD3 R7, P0, R21, UR8, RZ ; /* 0x0000000815077c10 */
/* 0x000fc6000ff1e0ff */
/*01b0*/ IMAD R5, R4, 0x186a0, RZ ; /* 0x000186a004057824 */
/* 0x000fe200078e02ff */
/*01c0*/ IADD3.X R18, R12, UR9, RZ, P0, !PT ; /* 0x000000090c127c10 */
/* 0x000fe400087fe4ff */
/*01d0*/ LEA R10, P0, R7, c[0x0][0x160], 0x2 ; /* 0x00005800070a7a11 */
/* 0x000fe400078010ff */
/*01e0*/ LEA R4, P1, R8.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0008047a11 */
/* 0x040fe400078210ff */
/*01f0*/ IADD3 R5, R9, R5, RZ ; /* 0x0000000509057210 */
/* 0x000fe40007ffe0ff */
/*0200*/ LEA.HI.X R11, R7, c[0x0][0x164], R18, 0x2, P0 ; /* 0x00005900070b7a11 */
/* 0x000fe400000f1412 */
/*0210*/ LEA.HI.X R5, R8, c[0x0][0x16c], R5, 0x2, P1 ; /* 0x00005b0008057a11 */
/* 0x000fc800008f1405 */
/*0220*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ee2000c1e1900 */
/*0240*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R19, RZ, RZ, R15 ; /* 0x000000ffff137224 */
/* 0x000fe200078e000f */
/*0260*/ MOV R18, 0x400 ; /* 0x0000040000127802 */
/* 0x000fe40000000f00 */
/*0270*/ ISETP.GE.U32.AND P1, PT, R17, 0xc35, PT ; /* 0x00000c351100780c */
/* 0x000fe40003f26070 */
/*0280*/ MOV R20, R14 ; /* 0x0000000e00147202 */
/* 0x000fe20000000f00 */
/*0290*/ STS [R16], R11 ; /* 0x0000000b10007388 */
/* 0x0051e80000000800 */
/*02a0*/ STS [R16+0x1000], R5 ; /* 0x0010000510007388 */
/* 0x0081e80000000800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ LDS R5, [R20+-0x400] ; /* 0xfffc000014057984 */
/* 0x001fe20000000800 */
/*02d0*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e220000201400 */
/*02e0*/ IADD3 R18, R18, 0x800, RZ ; /* 0x0000080012127810 */
/* 0x000fc40007ffe0ff */
/*02f0*/ LDS.128 R8, [R19+-0x20] ; /* 0xffffe00013087984 */
/* 0x000e240000000c00 */
/*0300*/ ISETP.NE.AND P0, PT, R18, 0xc35400, PT ; /* 0x00c354001200780c */
/* 0x000fe40003f05270 */
/*0310*/ LDS R4, [R20+-0x380] ; /* 0xfffc800014047984 */
/* 0x000e680000000800 */
/*0320*/ LDS R7, [R20+-0x300] ; /* 0xfffd000014077984 */
/* 0x000ea80000000800 */
/*0330*/ LDS R22, [R20+-0x280] ; /* 0xfffd800014167984 */
/* 0x000ee80000000800 */
/*0340*/ LDS R25, [R20+-0x200] ; /* 0xfffe000014197984 */
/* 0x000fe20000000800 */
/*0350*/ FFMA R5, R5, R8, R6 ; /* 0x0000000805057223 */
/* 0x001fc80000000006 */
/*0360*/ F2I.TRUNC.NTZ R8, R5 ; /* 0x0000000500087305 */
/* 0x000e30000020f100 */
/*0370*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x001e640000201400 */
/*0380*/ FFMA R9, R4, R9, R8 ; /* 0x0000000904097223 */
/* 0x002fcc0000000008 */
/*0390*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*03a0*/ I2F R4, R9 ; /* 0x0000000900047306 */
/* 0x0010a40000201400 */
/*03b0*/ LDS R9, [R20+-0x100] ; /* 0xffff000014097984 */
/* 0x001fe20000000800 */
/*03c0*/ FFMA R10, R7, R10, R4 ; /* 0x0000000a070a7223 */
/* 0x004fc60000000004 */
/*03d0*/ LDS.128 R4, [R19+-0x10] ; /* 0xfffff00013047984 */
/* 0x000e260000000c00 */
/*03e0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e70000020f100 */
/*03f0*/ I2F R23, R10 ; /* 0x0000000a00177306 */
/* 0x002ee40000201400 */
/*0400*/ FFMA R11, R22, R11, R23 ; /* 0x0000000b160b7223 */
/* 0x008fc40000000017 */
/*0410*/ LDS R22, [R20+-0x180] ; /* 0xfffe800014167984 */
/* 0x000e680000000800 */
/*0420*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000eb0000020f100 */
/*0430*/ I2F R8, R11 ; /* 0x0000000b00087306 */
/* 0x004e240000201400 */
/*0440*/ FFMA R4, R25, R4, R8 ; /* 0x0000000419047223 */
/* 0x001fc40000000008 */
/*0450*/ LDS R25, [R20] ; /* 0x0000000014197984 */
/* 0x000fe80000000800 */
/*0460*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*0470*/ I2F R8, R4 ; /* 0x0000000400087306 */
/* 0x001e640000201400 */
/*0480*/ FFMA R5, R22, R5, R8 ; /* 0x0000000516057223 */
/* 0x002fc40000000008 */
/*0490*/ LDS R22, [R20+-0x80] ; /* 0xffff800014167984 */
/* 0x000e280000000800 */
/*04a0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e70000020f100 */
/*04b0*/ I2F R8, R5 ; /* 0x0000000500087306 */
/* 0x0022a40000201400 */
/*04c0*/ LDS R5, [R20+0x100] ; /* 0x0001000014057984 */
/* 0x002fe20000000800 */
/*04d0*/ FFMA R6, R9, R6, R8 ; /* 0x0000000609067223 */
/* 0x004fc60000000008 */
/*04e0*/ LDS.128 R8, [R19] ; /* 0x0000000013087984 */
/* 0x000e660000000c00 */
/*04f0*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000eb0000020f100 */
/*0500*/ I2F R23, R6 ; /* 0x0000000600177306 */
/* 0x004e240000201400 */
/*0510*/ FFMA R7, R22, R7, R23 ; /* 0x0000000716077223 */
/* 0x001fc40000000017 */
/*0520*/ LDS R22, [R20+0x80] ; /* 0x0000800014167984 */
/* 0x000e280000000800 */
/*0530*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000eb0000020f100 */
/*0540*/ I2F R4, R7 ; /* 0x0000000700047306 */
/* 0x004e640000201400 */
/*0550*/ FFMA R4, R25, R8, R4 ; /* 0x0000000819047223 */
/* 0x002fc40000000004 */
/*0560*/ LDS R25, [R20+0x200] ; /* 0x0002000014197984 */
/* 0x000fe80000000800 */
/*0570*/ F2I.TRUNC.NTZ R8, R4 ; /* 0x0000000400087305 */
/* 0x000e70000020f100 */
/*0580*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x002e240000201400 */
/*0590*/ FFMA R9, R22, R9, R8 ; /* 0x0000000916097223 */
/* 0x001fc40000000008 */
/*05a0*/ LDS R22, [R20+0x180] ; /* 0x0001800014167984 */
/* 0x000e280000000800 */
/*05b0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e70000020f100 */
/*05c0*/ I2F R6, R9 ; /* 0x0000000900067306 */
/* 0x0022a40000201400 */
/*05d0*/ LDS R9, [R20+0x300] ; /* 0x0003000014097984 */
/* 0x002fe20000000800 */
/*05e0*/ FFMA R10, R5, R10, R6 ; /* 0x0000000a050a7223 */
/* 0x004fc60000000006 */
/*05f0*/ LDS.128 R4, [R19+0x10] ; /* 0x0000100013047984 */
/* 0x0002a60000000c00 */
/*0600*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000ee2000020f100 */
/*0610*/ IADD3 R19, R19, 0x40, RZ ; /* 0x0000004013137810 */
/* 0x002fce0007ffe0ff */
/*0620*/ I2F R23, R10 ; /* 0x0000000a00177306 */
/* 0x0082240000201400 */
/*0630*/ LDS R10, [R20+0x380] ; /* 0x00038000140a7984 */
/* 0x002fe20000000800 */
/*0640*/ FFMA R11, R22, R11, R23 ; /* 0x0000000b160b7223 */
/* 0x001fc60000000017 */
/*0650*/ LDS R22, [R20+0x280] ; /* 0x0002800014167984 */
/* 0x0000660000000800 */
/*0660*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000ee2000020f100 */
/*0670*/ IADD3 R20, R20, 0x800, RZ ; /* 0x0000080014147810 */
/* 0x001fce0007ffe0ff */
/*0680*/ I2F R8, R11 ; /* 0x0000000b00087306 */
/* 0x008ea40000201400 */
/*0690*/ FFMA R4, R25, R4, R8 ; /* 0x0000000419047223 */
/* 0x004fcc0000000008 */
/*06a0*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*06b0*/ I2F R8, R4 ; /* 0x0000000400087306 */
/* 0x001e640000201400 */
/*06c0*/ FFMA R5, R22, R5, R8 ; /* 0x0000000516057223 */
/* 0x002fcc0000000008 */
/*06d0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*06e0*/ I2F R8, R5 ; /* 0x0000000500087306 */
/* 0x001e240000201400 */
/*06f0*/ FFMA R8, R9, R6, R8 ; /* 0x0000000609087223 */
/* 0x001fcc0000000008 */
/*0700*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*0710*/ I2F R6, R8 ; /* 0x0000000800067306 */
/* 0x001e240000201400 */
/*0720*/ FFMA R6, R10, R7, R6 ; /* 0x000000070a067223 */
/* 0x001fcc0000000006 */
/*0730*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e22000020f100 */
/*0740*/ @P0 BRA 0x2c0 ; /* 0xfffffb7000000947 */
/* 0x000fea000383ffff */
/*0750*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*0760*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0770*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc600087fe43f */
/*0780*/ @!P1 BRA 0x150 ; /* 0xfffff9c000009947 */
/* 0x000fea000383ffff */
/*0790*/ I2F R5, R6 ; /* 0x0000000600057306 */
/* 0x001e220000201400 */
/*07a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*07b0*/ IMAD R2, R2, 0x186a0, R13 ; /* 0x000186a002027824 */
/* 0x000fd200078e020d */
/*07c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*07d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x7f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cstdio>
#include <ctime>
#include <iostream>
#define TILE_WIDTH 32
#define H 100000
#define W 100000
using namespace std;
void foo(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
v[i * W + j] = 2;
}
}
}
void mult(float* A, float* B, float* C) {
int aux = 0;
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
aux = 0;
for (int k = 0; k < W; k++) aux += A[i * W + k] * B[k * W + j];
C[i * W + j] = aux;
}
}
}
void mostrar(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
cout << v[i * W + j] << " ";
}
cout << endl;
}
}
__global__ void multMat(float* d_A, float* d_B, float* d_C) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
int Pvalue = 0;
for (size_t phase = 0; phase < W / TILE_WIDTH; phase++) {
ds_A[ty][tx] = d_A[row * W + phase * TILE_WIDTH + tx];
ds_B[ty][tx] = d_B[(phase * TILE_WIDTH + ty) * W + col];
__syncthreads();
for (int k = 0; k < W; k++) {
Pvalue += ds_A[ty][k] * ds_B[k][tx];
}
__syncthreads();
}
d_C[col * W + row] = Pvalue;
}
int main() {
float* A = new float[H * W];
float* B = new float[H * W];
float* C = new float[H * W];
float* D = new float[H * W];
foo(A);
foo(B);
// {
// clock_t start = clock();
//
// mult(A, B, C);
//
// clock_t end = clock();
// double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
// printf("Tiempo invertido CPU = %lf s\n", cpu_time_used);
// }
float *d_A, *d_B, *d_D;
float blockSize = TILE_WIDTH;
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(ceil(W / float(blockSize)), ceil(H / float(blockSize)), 1);
cudaMalloc((void**)&d_A, sizeof(float) * H * W);
cudaMalloc((void**)&d_B, sizeof(float) * H * W);
cudaMalloc((void**)&d_D, sizeof(float) * H * W);
{
clock_t start = clock();
cudaMemcpy(d_A, A, sizeof(float) * H * W, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, sizeof(float) * H * W, cudaMemcpyHostToDevice);
multMat<<<dimGrid, dimBlock>>>(d_A, d_B, d_D);
cudaMemcpy(D, d_D, sizeof(float) * H * W, cudaMemcpyDeviceToHost);
clock_t end = clock();
double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
std::cout << "Tiempo invertido GPU = " << cpu_time_used << "s\n";
}
delete A;
delete B;
delete C;
delete D;
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_D);
} | .file "tmpxft_0007c3b5_00000000-6_matrix_mult_tiles.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3fooPf
.type _Z3fooPf, @function
_Z3fooPf:
.LFB3669:
.cfi_startproc
endbr64
movq %rdi, %rcx
leaq 400000(%rdi), %rdx
movabsq $40000400000, %rax
addq %rax, %rcx
movss .LC0(%rip), %xmm0
.L4:
leaq -400000(%rdx), %rax
.L5:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
addq $400000, %rdx
cmpq %rcx, %rdx
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z3fooPf, .-_Z3fooPf
.globl _Z4multPfS_S_
.type _Z4multPfS_S_, @function
_Z4multPfS_S_:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl $0, %ebx
movabsq $40000000000, %rbp
movabsq $-40000000000, %r10
movl $0, %r9d
.L9:
leaq 0(%r13,%rbp), %rsi
imulq $400000, %rbx, %r8
leaq (%r14,%r8), %r11
addq %r12, %r8
movl $0, %edi
.L13:
leaq (%rsi,%r10), %rax
movq %r11, %rdx
movl %r9d, %ecx
.L10:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
addss %xmm1, %xmm0
cvttss2sil %xmm0, %ecx
addq $4, %rdx
addq $400000, %rax
cmpq %rsi, %rax
jne .L10
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%r8,%rdi,4)
addq $1, %rdi
addq $4, %rsi
cmpq $100000, %rdi
jne .L13
addq $1, %rbx
cmpq $100000, %rbx
jne .L9
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z4multPfS_S_, .-_Z4multPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.text
.globl _Z7mostrarPf
.type _Z7mostrarPf, @function
_Z7mostrarPf:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
leaq 400000(%rdi), %rbp
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L17
.L24:
call _ZSt16__throw_bad_castv@PLT
.L25:
movzbl 67(%rbx), %eax
.L21:
movsbl %al, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $400000, %rbp
.L17:
leaq -400000(%rbp), %rbx
.L18:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L24
cmpb $0, 56(%rbx)
jne .L25
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L21
.cfi_endproc
.LFE3671:
.size _Z7mostrarPf, .-_Z7mostrarPf
.globl _Z30__device_stub__Z7multMatPfS_S_PfS_S_
.type _Z30__device_stub__Z7multMatPfS_S_PfS_S_, @function
_Z30__device_stub__Z7multMatPfS_S_PfS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7multMatPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z30__device_stub__Z7multMatPfS_S_PfS_S_, .-_Z30__device_stub__Z7multMatPfS_S_PfS_S_
.globl _Z7multMatPfS_S_
.type _Z7multMatPfS_S_, @function
_Z7multMatPfS_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7multMatPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z7multMatPfS_S_, .-_Z7multMatPfS_S_
.section .rodata.str1.1
.LC3:
.string "Tiempo invertido GPU = "
.LC4:
.string "s\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $5640261632, %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r14
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r13
movq %rbp, %rdi
call _Z3fooPf
movq %rbx, %rdi
call _Z3fooPf
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $3125, 44(%rsp)
movl $3125, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movabsq $40000000000, %r12
movq %r12, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
call clock@PLT
movq %rax, %r15
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
movl $2, %ecx
movabsq $40000000000, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movq %xmm0, %r12
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $4, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r14, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r13, %rdi
call _ZdlPvm@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z7multMatPfS_S_PfS_S_
jmp .L35
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z7multMatPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7multMatPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cstdio>
#include <ctime>
#include <iostream>
#define TILE_WIDTH 32
#define H 100000
#define W 100000
using namespace std;
void foo(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
v[i * W + j] = 2;
}
}
}
void mult(float* A, float* B, float* C) {
int aux = 0;
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
aux = 0;
for (int k = 0; k < W; k++) aux += A[i * W + k] * B[k * W + j];
C[i * W + j] = aux;
}
}
}
void mostrar(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
cout << v[i * W + j] << " ";
}
cout << endl;
}
}
__global__ void multMat(float* d_A, float* d_B, float* d_C) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
int Pvalue = 0;
for (size_t phase = 0; phase < W / TILE_WIDTH; phase++) {
ds_A[ty][tx] = d_A[row * W + phase * TILE_WIDTH + tx];
ds_B[ty][tx] = d_B[(phase * TILE_WIDTH + ty) * W + col];
__syncthreads();
for (int k = 0; k < W; k++) {
Pvalue += ds_A[ty][k] * ds_B[k][tx];
}
__syncthreads();
}
d_C[col * W + row] = Pvalue;
}
int main() {
float* A = new float[H * W];
float* B = new float[H * W];
float* C = new float[H * W];
float* D = new float[H * W];
foo(A);
foo(B);
// {
// clock_t start = clock();
//
// mult(A, B, C);
//
// clock_t end = clock();
// double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
// printf("Tiempo invertido CPU = %lf s\n", cpu_time_used);
// }
float *d_A, *d_B, *d_D;
float blockSize = TILE_WIDTH;
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(ceil(W / float(blockSize)), ceil(H / float(blockSize)), 1);
cudaMalloc((void**)&d_A, sizeof(float) * H * W);
cudaMalloc((void**)&d_B, sizeof(float) * H * W);
cudaMalloc((void**)&d_D, sizeof(float) * H * W);
{
clock_t start = clock();
cudaMemcpy(d_A, A, sizeof(float) * H * W, cudaMemcpyHostToDevice);
cudaMemcpy(d_B, B, sizeof(float) * H * W, cudaMemcpyHostToDevice);
multMat<<<dimGrid, dimBlock>>>(d_A, d_B, d_D);
cudaMemcpy(D, d_D, sizeof(float) * H * W, cudaMemcpyDeviceToHost);
clock_t end = clock();
double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
std::cout << "Tiempo invertido GPU = " << cpu_time_used << "s\n";
}
delete A;
delete B;
delete C;
delete D;
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_D);
} | #include <hip/hip_runtime.h>
#include <cstdio>
#include <ctime>
#include <iostream>
#define TILE_WIDTH 32
#define H 100000
#define W 100000
using namespace std;
void foo(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
v[i * W + j] = 2;
}
}
}
void mult(float* A, float* B, float* C) {
int aux = 0;
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
aux = 0;
for (int k = 0; k < W; k++) aux += A[i * W + k] * B[k * W + j];
C[i * W + j] = aux;
}
}
}
void mostrar(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
cout << v[i * W + j] << " ";
}
cout << endl;
}
}
__global__ void multMat(float* d_A, float* d_B, float* d_C) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
int Pvalue = 0;
for (size_t phase = 0; phase < W / TILE_WIDTH; phase++) {
ds_A[ty][tx] = d_A[row * W + phase * TILE_WIDTH + tx];
ds_B[ty][tx] = d_B[(phase * TILE_WIDTH + ty) * W + col];
__syncthreads();
for (int k = 0; k < W; k++) {
Pvalue += ds_A[ty][k] * ds_B[k][tx];
}
__syncthreads();
}
d_C[col * W + row] = Pvalue;
}
int main() {
float* A = new float[H * W];
float* B = new float[H * W];
float* C = new float[H * W];
float* D = new float[H * W];
foo(A);
foo(B);
// {
// clock_t start = clock();
//
// mult(A, B, C);
//
// clock_t end = clock();
// double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
// printf("Tiempo invertido CPU = %lf s\n", cpu_time_used);
// }
float *d_A, *d_B, *d_D;
float blockSize = TILE_WIDTH;
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(ceil(W / float(blockSize)), ceil(H / float(blockSize)), 1);
hipMalloc((void**)&d_A, sizeof(float) * H * W);
hipMalloc((void**)&d_B, sizeof(float) * H * W);
hipMalloc((void**)&d_D, sizeof(float) * H * W);
{
clock_t start = clock();
hipMemcpy(d_A, A, sizeof(float) * H * W, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, sizeof(float) * H * W, hipMemcpyHostToDevice);
multMat<<<dimGrid, dimBlock>>>(d_A, d_B, d_D);
hipMemcpy(D, d_D, sizeof(float) * H * W, hipMemcpyDeviceToHost);
clock_t end = clock();
double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
std::cout << "Tiempo invertido GPU = " << cpu_time_used << "s\n";
}
delete A;
delete B;
delete C;
delete D;
hipFree(d_A);
hipFree(d_B);
hipFree(d_D);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <ctime>
#include <iostream>
#define TILE_WIDTH 32
#define H 100000
#define W 100000
using namespace std;
void foo(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
v[i * W + j] = 2;
}
}
}
void mult(float* A, float* B, float* C) {
int aux = 0;
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
aux = 0;
for (int k = 0; k < W; k++) aux += A[i * W + k] * B[k * W + j];
C[i * W + j] = aux;
}
}
}
void mostrar(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
cout << v[i * W + j] << " ";
}
cout << endl;
}
}
__global__ void multMat(float* d_A, float* d_B, float* d_C) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
int Pvalue = 0;
for (size_t phase = 0; phase < W / TILE_WIDTH; phase++) {
ds_A[ty][tx] = d_A[row * W + phase * TILE_WIDTH + tx];
ds_B[ty][tx] = d_B[(phase * TILE_WIDTH + ty) * W + col];
__syncthreads();
for (int k = 0; k < W; k++) {
Pvalue += ds_A[ty][k] * ds_B[k][tx];
}
__syncthreads();
}
d_C[col * W + row] = Pvalue;
}
int main() {
float* A = new float[H * W];
float* B = new float[H * W];
float* C = new float[H * W];
float* D = new float[H * W];
foo(A);
foo(B);
// {
// clock_t start = clock();
//
// mult(A, B, C);
//
// clock_t end = clock();
// double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
// printf("Tiempo invertido CPU = %lf s\n", cpu_time_used);
// }
float *d_A, *d_B, *d_D;
float blockSize = TILE_WIDTH;
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(ceil(W / float(blockSize)), ceil(H / float(blockSize)), 1);
hipMalloc((void**)&d_A, sizeof(float) * H * W);
hipMalloc((void**)&d_B, sizeof(float) * H * W);
hipMalloc((void**)&d_D, sizeof(float) * H * W);
{
clock_t start = clock();
hipMemcpy(d_A, A, sizeof(float) * H * W, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, sizeof(float) * H * W, hipMemcpyHostToDevice);
multMat<<<dimGrid, dimBlock>>>(d_A, d_B, d_D);
hipMemcpy(D, d_D, sizeof(float) * H * W, hipMemcpyDeviceToHost);
clock_t end = clock();
double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
std::cout << "Tiempo invertido GPU = " << cpu_time_used << "s\n";
}
delete A;
delete B;
delete C;
delete D;
hipFree(d_A);
hipFree(d_B);
hipFree(d_D);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7multMatPfS_S_
.globl _Z7multMatPfS_S_
.p2align 8
.type _Z7multMatPfS_S_,@function
_Z7multMatPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v1, 0x186a0
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_mov_b32_e32 v7, 0
v_mad_u64_u32 v[4:5], null, s14, s2, v[0:1]
v_lshlrev_b32_e32 v12, 2, v0
v_lshlrev_b32_e32 v0, 7, v3
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v11, vcc_lo
v_ashrrev_i32_e32 v5, 31, v4
v_or_b32_e32 v2, 0x1000, v12
v_add_nc_u32_e32 v8, v0, v12
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_nc_u32_e32 v9, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, v10, v12
v_mov_b32_e32 v10, 0
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
s_lshl_b64 s[4:5], s[2:3], 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_co_u32 v15, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v7, vcc_lo
s_lshl_b64 s[4:5], s[2:3], 7
v_mad_u64_u32 v[13:14], null, v15, 0x61a80, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[15:16], null, v17, 0x61a80, v[14:15]
v_add_co_u32 v16, vcc_lo, v11, s4
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v12, vcc_lo
s_mov_b32 s4, 0
v_mov_b32_e32 v14, v15
global_load_b32 v15, v[16:17], off
global_load_b32 v14, v[13:14], off
v_mov_b32_e32 v13, v2
s_waitcnt vmcnt(1)
ds_store_b32 v8, v15
s_waitcnt vmcnt(0)
ds_store_b32 v9, v14
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
v_add_nc_u32_e32 v14, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_i32_e32 v10, v10
s_add_i32 s4, s4, 4
ds_load_b32 v15, v13
ds_load_b32 v14, v14
s_cmp_eq_u32 s4, 0x61a80
s_waitcnt lgkmcnt(0)
v_dual_fmac_f32 v10, v14, v15 :: v_dual_add_nc_u32 v13, 0x80, v13
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v10, v10
s_cbranch_scc0 .LBB0_2
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[2:3], 0xc35
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v4, 0x186a0, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cvt_f32_i32_e32 v2, v10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7multMatPfS_S_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7multMatPfS_S_, .Lfunc_end0-_Z7multMatPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7multMatPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7multMatPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cstdio>
#include <ctime>
#include <iostream>
#define TILE_WIDTH 32
#define H 100000
#define W 100000
using namespace std;
void foo(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
v[i * W + j] = 2;
}
}
}
void mult(float* A, float* B, float* C) {
int aux = 0;
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
aux = 0;
for (int k = 0; k < W; k++) aux += A[i * W + k] * B[k * W + j];
C[i * W + j] = aux;
}
}
}
void mostrar(float* v) {
for (int i = 0; i < H; i++) {
for (int j = 0; j < W; j++) {
cout << v[i * W + j] << " ";
}
cout << endl;
}
}
__global__ void multMat(float* d_A, float* d_B, float* d_C) {
__shared__ float ds_A[TILE_WIDTH][TILE_WIDTH];
__shared__ float ds_B[TILE_WIDTH][TILE_WIDTH];
int bx = blockIdx.x;
int by = blockIdx.y;
int tx = threadIdx.x;
int ty = threadIdx.y;
int row = by * blockDim.y + ty;
int col = bx * blockDim.x + tx;
int Pvalue = 0;
for (size_t phase = 0; phase < W / TILE_WIDTH; phase++) {
ds_A[ty][tx] = d_A[row * W + phase * TILE_WIDTH + tx];
ds_B[ty][tx] = d_B[(phase * TILE_WIDTH + ty) * W + col];
__syncthreads();
for (int k = 0; k < W; k++) {
Pvalue += ds_A[ty][k] * ds_B[k][tx];
}
__syncthreads();
}
d_C[col * W + row] = Pvalue;
}
int main() {
float* A = new float[H * W];
float* B = new float[H * W];
float* C = new float[H * W];
float* D = new float[H * W];
foo(A);
foo(B);
// {
// clock_t start = clock();
//
// mult(A, B, C);
//
// clock_t end = clock();
// double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
// printf("Tiempo invertido CPU = %lf s\n", cpu_time_used);
// }
float *d_A, *d_B, *d_D;
float blockSize = TILE_WIDTH;
dim3 dimBlock(blockSize, blockSize);
dim3 dimGrid(ceil(W / float(blockSize)), ceil(H / float(blockSize)), 1);
hipMalloc((void**)&d_A, sizeof(float) * H * W);
hipMalloc((void**)&d_B, sizeof(float) * H * W);
hipMalloc((void**)&d_D, sizeof(float) * H * W);
{
clock_t start = clock();
hipMemcpy(d_A, A, sizeof(float) * H * W, hipMemcpyHostToDevice);
hipMemcpy(d_B, B, sizeof(float) * H * W, hipMemcpyHostToDevice);
multMat<<<dimGrid, dimBlock>>>(d_A, d_B, d_D);
hipMemcpy(D, d_D, sizeof(float) * H * W, hipMemcpyDeviceToHost);
clock_t end = clock();
double cpu_time_used = ((double)(end - start)) / CLOCKS_PER_SEC;
std::cout << "Tiempo invertido GPU = " << cpu_time_used << "s\n";
}
delete A;
delete B;
delete C;
delete D;
hipFree(d_A);
hipFree(d_B);
hipFree(d_D);
} | .text
.file "matrix_mult_tiles.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z3fooPf # -- Begin function _Z3fooPf
.p2align 4, 0x90
.type _Z3fooPf,@function
_Z3fooPf: # @_Z3fooPf
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rdi,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $100000, %rcx # imm = 0x186A0
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $400000, %rdi # imm = 0x61A80
cmpq $100000, %rax # imm = 0x186A0
jne .LBB0_1
# %bb.4:
retq
.Lfunc_end0:
.size _Z3fooPf, .Lfunc_end0-_Z3fooPf
.cfi_endproc
# -- End function
.globl _Z4multPfS_S_ # -- Begin function _Z4multPfS_S_
.p2align 4, 0x90
.type _Z4multPfS_S_,@function
_Z4multPfS_S_: # @_Z4multPfS_S_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_3 Depth 3
imulq $400000, %rax, %rcx # imm = 0x61A80
addq %rdx, %rcx
movq %rsi, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_3 Depth 3
xorl %r10d, %r10d
movq %r8, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r11), %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
addss %xmm0, %xmm1
cvttss2si %xmm1, %ebx
incq %r10
addq $400000, %r11 # imm = 0x61A80
cmpq $100000, %r10 # imm = 0x186A0
jne .LBB1_3
# %bb.4: # in Loop: Header=BB1_2 Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, (%rcx,%r9,4)
incq %r9
addq $4, %r8
cmpq $100000, %r9 # imm = 0x186A0
jne .LBB1_2
# %bb.5: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $400000, %rdi # imm = 0x61A80
cmpq $100000, %rax # imm = 0x186A0
jne .LBB1_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4multPfS_S_, .Lfunc_end1-_Z4multPfS_S_
.cfi_endproc
# -- End function
.globl _Z7mostrarPf # -- Begin function _Z7mostrarPf
.p2align 4, 0x90
.type _Z7mostrarPf,@function
_Z7mostrarPf: # @_Z7mostrarPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r15d, %r15d
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_1 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_1 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $400000, %rbx # imm = 0x61A80
cmpq $100000, %r15 # imm = 0x186A0
je .LBB2_8
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_1 Depth=1
cmpb $0, 56(%r14)
je .LBB2_6
# %bb.5: # in Loop: Header=BB2_1 Depth=1
movzbl 67(%r14), %eax
jmp .LBB2_7
.LBB2_8:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_9:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z7mostrarPf, .Lfunc_end2-_Z7mostrarPf
.cfi_endproc
# -- End function
.globl _Z22__device_stub__multMatPfS_S_ # -- Begin function _Z22__device_stub__multMatPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__multMatPfS_S_,@function
_Z22__device_stub__multMatPfS_S_: # @_Z22__device_stub__multMatPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7multMatPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__multMatPfS_S_, .Lfunc_end3-_Z22__device_stub__multMatPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $5640261632, %r12 # imm = 0x1502F9000
movq %r12, %rdi
callq _Znam
movq %rax, %rbx
movq %r12, %rdi
callq _Znam
movq %rax, %r14
movq %r12, %rdi
callq _Znam
movq %rax, %r15
movq %r12, %rdi
callq _Znam
movq %rax, %r12
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rcx,%rdx,4) # imm = 0x40000000
incq %rdx
cmpq $100000, %rdx # imm = 0x186A0
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %rax
addq $400000, %rcx # imm = 0x61A80
cmpq $100000, %rax # imm = 0x186A0
jne .LBB4_1
# %bb.4: # %.preheader.i22.preheader
xorl %eax, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB4_5: # %.preheader.i22
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rcx,%rdx,4) # imm = 0x40000000
incq %rdx
cmpq $100000, %rdx # imm = 0x186A0
jne .LBB4_6
# %bb.7: # in Loop: Header=BB4_5 Depth=1
incq %rax
addq $400000, %rcx # imm = 0x61A80
cmpq $100000, %rax # imm = 0x186A0
jne .LBB4_5
# %bb.8: # %_Z3fooPf.exit29
movabsq $40000000000, %r13 # imm = 0x9502F9000
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq clock
movq %rax, %rbp
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $13421772803125, %rdi # imm = 0xC3500000C35
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7multMatPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
callq clock
subq %rbp, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %r15, %rdi
callq _ZdlPv
movq %r12, %rdi
callq _ZdlPv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7multMatPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z7multMatPfS_S_,@object # @_Z7multMatPfS_S_
.section .rodata,"a",@progbits
.globl _Z7multMatPfS_S_
.p2align 3, 0x0
_Z7multMatPfS_S_:
.quad _Z22__device_stub__multMatPfS_S_
.size _Z7multMatPfS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Tiempo invertido GPU = "
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "s\n"
.size .L.str.2, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7multMatPfS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__multMatPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z7multMatPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7multMatPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R13, SR_CTAID.Y ; /* 0x00000000000d7919 */
/* 0x000e220000002600 */
/*0020*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0030*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0060*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe40008000000 */
/*0070*/ UMOV UR5, URZ ; /* 0x0000003f00057c82 */
/* 0x000fe20008000000 */
/*0080*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e680000002100 */
/*0090*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000ea20000002500 */
/*00a0*/ IMAD R13, R13, c[0x0][0x4], R0 ; /* 0x000001000d0d7a24 */
/* 0x001fe200078e0200 */
/*00b0*/ LEA R15, R0, 0x20, 0x7 ; /* 0x00000020000f7811 */
/* 0x000fc600078e38ff */
/*00c0*/ IMAD R12, R13, 0x186a0, RZ ; /* 0x000186a00d0c7824 */
/* 0x000fe200078e02ff */
/*00d0*/ SHF.R.S32.HI R5, RZ, 0x1f, R3.reuse ; /* 0x0000001fff057819 */
/* 0x102fe20000011403 */
/*00e0*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x004fc600078e0203 */
/*00f0*/ IADD3 R21, P0, R12.reuse, R3, RZ ; /* 0x000000030c157210 */
/* 0x040fe40007f1e0ff */
/*0100*/ SHF.L.U32 R3, R3, 0x2, RZ ; /* 0x0000000203037819 */
/* 0x000fe400000006ff */
/*0110*/ LEA.HI.X.SX32 R12, R12, R5, 0x1, P0 ; /* 0x000000050c0c7211 */
/* 0x000fe400000f0eff */
/*0120*/ IADD3 R14, R3, 0x1400, RZ ; /* 0x00001400030e7810 */
/* 0x000fe20007ffe0ff */
/*0130*/ IMAD R16, R0, 0x80, R3 ; /* 0x0000008000107824 */
/* 0x000fe200078e0203 */
/*0140*/ SHF.R.S32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fe40000011402 */
/*0150*/ USHF.L.U32 UR8, UR4, 0x5, URZ ; /* 0x0000000504087899 */
/* 0x000fe4000800063f */
/*0160*/ USHF.L.U64.HI UR9, UR4, 0x5, UR5 ; /* 0x0000000504097899 */
/* 0x000fc80008010205 */
/*0170*/ IADD3 R9, P0, R0, UR8, RZ ; /* 0x0000000800097c10 */
/* 0x000fc8000ff1e0ff */
/*0180*/ LEA.HI.X.SX32 R4, R0, UR9, 0x1, P0 ; /* 0x0000000900047c11 */
/* 0x000fe200080f0eff */
/*0190*/ IMAD.WIDE.U32 R8, R9, 0x186a0, R2 ; /* 0x000186a009087825 */
/* 0x000fe200078e0002 */
/*01a0*/ IADD3 R7, P0, R21, UR8, RZ ; /* 0x0000000815077c10 */
/* 0x000fc6000ff1e0ff */
/*01b0*/ IMAD R5, R4, 0x186a0, RZ ; /* 0x000186a004057824 */
/* 0x000fe200078e02ff */
/*01c0*/ IADD3.X R18, R12, UR9, RZ, P0, !PT ; /* 0x000000090c127c10 */
/* 0x000fe400087fe4ff */
/*01d0*/ LEA R10, P0, R7, c[0x0][0x160], 0x2 ; /* 0x00005800070a7a11 */
/* 0x000fe400078010ff */
/*01e0*/ LEA R4, P1, R8.reuse, c[0x0][0x168], 0x2 ; /* 0x00005a0008047a11 */
/* 0x040fe400078210ff */
/*01f0*/ IADD3 R5, R9, R5, RZ ; /* 0x0000000509057210 */
/* 0x000fe40007ffe0ff */
/*0200*/ LEA.HI.X R11, R7, c[0x0][0x164], R18, 0x2, P0 ; /* 0x00005900070b7a11 */
/* 0x000fe400000f1412 */
/*0210*/ LEA.HI.X R5, R8, c[0x0][0x16c], R5, 0x2, P1 ; /* 0x00005b0008057a11 */
/* 0x000fc800008f1405 */
/*0220*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000ea8000c1e1900 */
/*0230*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ee2000c1e1900 */
/*0240*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R19, RZ, RZ, R15 ; /* 0x000000ffff137224 */
/* 0x000fe200078e000f */
/*0260*/ MOV R18, 0x400 ; /* 0x0000040000127802 */
/* 0x000fe40000000f00 */
/*0270*/ ISETP.GE.U32.AND P1, PT, R17, 0xc35, PT ; /* 0x00000c351100780c */
/* 0x000fe40003f26070 */
/*0280*/ MOV R20, R14 ; /* 0x0000000e00147202 */
/* 0x000fe20000000f00 */
/*0290*/ STS [R16], R11 ; /* 0x0000000b10007388 */
/* 0x0051e80000000800 */
/*02a0*/ STS [R16+0x1000], R5 ; /* 0x0010000510007388 */
/* 0x0081e80000000800 */
/*02b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02c0*/ LDS R5, [R20+-0x400] ; /* 0xfffc000014057984 */
/* 0x001fe20000000800 */
/*02d0*/ I2F R6, R6 ; /* 0x0000000600067306 */
/* 0x000e220000201400 */
/*02e0*/ IADD3 R18, R18, 0x800, RZ ; /* 0x0000080012127810 */
/* 0x000fc40007ffe0ff */
/*02f0*/ LDS.128 R8, [R19+-0x20] ; /* 0xffffe00013087984 */
/* 0x000e240000000c00 */
/*0300*/ ISETP.NE.AND P0, PT, R18, 0xc35400, PT ; /* 0x00c354001200780c */
/* 0x000fe40003f05270 */
/*0310*/ LDS R4, [R20+-0x380] ; /* 0xfffc800014047984 */
/* 0x000e680000000800 */
/*0320*/ LDS R7, [R20+-0x300] ; /* 0xfffd000014077984 */
/* 0x000ea80000000800 */
/*0330*/ LDS R22, [R20+-0x280] ; /* 0xfffd800014167984 */
/* 0x000ee80000000800 */
/*0340*/ LDS R25, [R20+-0x200] ; /* 0xfffe000014197984 */
/* 0x000fe20000000800 */
/*0350*/ FFMA R5, R5, R8, R6 ; /* 0x0000000805057223 */
/* 0x001fc80000000006 */
/*0360*/ F2I.TRUNC.NTZ R8, R5 ; /* 0x0000000500087305 */
/* 0x000e30000020f100 */
/*0370*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x001e640000201400 */
/*0380*/ FFMA R9, R4, R9, R8 ; /* 0x0000000904097223 */
/* 0x002fcc0000000008 */
/*0390*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000020f100 */
/*03a0*/ I2F R4, R9 ; /* 0x0000000900047306 */
/* 0x0010a40000201400 */
/*03b0*/ LDS R9, [R20+-0x100] ; /* 0xffff000014097984 */
/* 0x001fe20000000800 */
/*03c0*/ FFMA R10, R7, R10, R4 ; /* 0x0000000a070a7223 */
/* 0x004fc60000000004 */
/*03d0*/ LDS.128 R4, [R19+-0x10] ; /* 0xfffff00013047984 */
/* 0x000e260000000c00 */
/*03e0*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000e70000020f100 */
/*03f0*/ I2F R23, R10 ; /* 0x0000000a00177306 */
/* 0x002ee40000201400 */
/*0400*/ FFMA R11, R22, R11, R23 ; /* 0x0000000b160b7223 */
/* 0x008fc40000000017 */
/*0410*/ LDS R22, [R20+-0x180] ; /* 0xfffe800014167984 */
/* 0x000e680000000800 */
/*0420*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000eb0000020f100 */
/*0430*/ I2F R8, R11 ; /* 0x0000000b00087306 */
/* 0x004e240000201400 */
/*0440*/ FFMA R4, R25, R4, R8 ; /* 0x0000000419047223 */
/* 0x001fc40000000008 */
/*0450*/ LDS R25, [R20] ; /* 0x0000000014197984 */
/* 0x000fe80000000800 */
/*0460*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*0470*/ I2F R8, R4 ; /* 0x0000000400087306 */
/* 0x001e640000201400 */
/*0480*/ FFMA R5, R22, R5, R8 ; /* 0x0000000516057223 */
/* 0x002fc40000000008 */
/*0490*/ LDS R22, [R20+-0x80] ; /* 0xffff800014167984 */
/* 0x000e280000000800 */
/*04a0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e70000020f100 */
/*04b0*/ I2F R8, R5 ; /* 0x0000000500087306 */
/* 0x0022a40000201400 */
/*04c0*/ LDS R5, [R20+0x100] ; /* 0x0001000014057984 */
/* 0x002fe20000000800 */
/*04d0*/ FFMA R6, R9, R6, R8 ; /* 0x0000000609067223 */
/* 0x004fc60000000008 */
/*04e0*/ LDS.128 R8, [R19] ; /* 0x0000000013087984 */
/* 0x000e660000000c00 */
/*04f0*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000eb0000020f100 */
/*0500*/ I2F R23, R6 ; /* 0x0000000600177306 */
/* 0x004e240000201400 */
/*0510*/ FFMA R7, R22, R7, R23 ; /* 0x0000000716077223 */
/* 0x001fc40000000017 */
/*0520*/ LDS R22, [R20+0x80] ; /* 0x0000800014167984 */
/* 0x000e280000000800 */
/*0530*/ F2I.TRUNC.NTZ R7, R7 ; /* 0x0000000700077305 */
/* 0x000eb0000020f100 */
/*0540*/ I2F R4, R7 ; /* 0x0000000700047306 */
/* 0x004e640000201400 */
/*0550*/ FFMA R4, R25, R8, R4 ; /* 0x0000000819047223 */
/* 0x002fc40000000004 */
/*0560*/ LDS R25, [R20+0x200] ; /* 0x0002000014197984 */
/* 0x000fe80000000800 */
/*0570*/ F2I.TRUNC.NTZ R8, R4 ; /* 0x0000000400087305 */
/* 0x000e70000020f100 */
/*0580*/ I2F R8, R8 ; /* 0x0000000800087306 */
/* 0x002e240000201400 */
/*0590*/ FFMA R9, R22, R9, R8 ; /* 0x0000000916097223 */
/* 0x001fc40000000008 */
/*05a0*/ LDS R22, [R20+0x180] ; /* 0x0001800014167984 */
/* 0x000e280000000800 */
/*05b0*/ F2I.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e70000020f100 */
/*05c0*/ I2F R6, R9 ; /* 0x0000000900067306 */
/* 0x0022a40000201400 */
/*05d0*/ LDS R9, [R20+0x300] ; /* 0x0003000014097984 */
/* 0x002fe20000000800 */
/*05e0*/ FFMA R10, R5, R10, R6 ; /* 0x0000000a050a7223 */
/* 0x004fc60000000006 */
/*05f0*/ LDS.128 R4, [R19+0x10] ; /* 0x0000100013047984 */
/* 0x0002a60000000c00 */
/*0600*/ F2I.TRUNC.NTZ R10, R10 ; /* 0x0000000a000a7305 */
/* 0x000ee2000020f100 */
/*0610*/ IADD3 R19, R19, 0x40, RZ ; /* 0x0000004013137810 */
/* 0x002fce0007ffe0ff */
/*0620*/ I2F R23, R10 ; /* 0x0000000a00177306 */
/* 0x0082240000201400 */
/*0630*/ LDS R10, [R20+0x380] ; /* 0x00038000140a7984 */
/* 0x002fe20000000800 */
/*0640*/ FFMA R11, R22, R11, R23 ; /* 0x0000000b160b7223 */
/* 0x001fc60000000017 */
/*0650*/ LDS R22, [R20+0x280] ; /* 0x0002800014167984 */
/* 0x0000660000000800 */
/*0660*/ F2I.TRUNC.NTZ R11, R11 ; /* 0x0000000b000b7305 */
/* 0x000ee2000020f100 */
/*0670*/ IADD3 R20, R20, 0x800, RZ ; /* 0x0000080014147810 */
/* 0x001fce0007ffe0ff */
/*0680*/ I2F R8, R11 ; /* 0x0000000b00087306 */
/* 0x008ea40000201400 */
/*0690*/ FFMA R4, R25, R4, R8 ; /* 0x0000000419047223 */
/* 0x004fcc0000000008 */
/*06a0*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x000e30000020f100 */
/*06b0*/ I2F R8, R4 ; /* 0x0000000400087306 */
/* 0x001e640000201400 */
/*06c0*/ FFMA R5, R22, R5, R8 ; /* 0x0000000516057223 */
/* 0x002fcc0000000008 */
/*06d0*/ F2I.TRUNC.NTZ R5, R5 ; /* 0x0000000500057305 */
/* 0x000e30000020f100 */
/*06e0*/ I2F R8, R5 ; /* 0x0000000500087306 */
/* 0x001e240000201400 */
/*06f0*/ FFMA R8, R9, R6, R8 ; /* 0x0000000609087223 */
/* 0x001fcc0000000008 */
/*0700*/ F2I.TRUNC.NTZ R8, R8 ; /* 0x0000000800087305 */
/* 0x000e30000020f100 */
/*0710*/ I2F R6, R8 ; /* 0x0000000800067306 */
/* 0x001e240000201400 */
/*0720*/ FFMA R6, R10, R7, R6 ; /* 0x000000070a067223 */
/* 0x001fcc0000000006 */
/*0730*/ F2I.TRUNC.NTZ R6, R6 ; /* 0x0000000600067305 */
/* 0x000e22000020f100 */
/*0740*/ @P0 BRA 0x2c0 ; /* 0xfffffb7000000947 */
/* 0x000fea000383ffff */
/*0750*/ UIADD3 UR4, UP0, UR4, 0x1, URZ ; /* 0x0000000104047890 */
/* 0x000fe2000ff1e03f */
/*0760*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0770*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fc600087fe43f */
/*0780*/ @!P1 BRA 0x150 ; /* 0xfffff9c000009947 */
/* 0x000fea000383ffff */
/*0790*/ I2F R5, R6 ; /* 0x0000000600057306 */
/* 0x001e220000201400 */
/*07a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*07b0*/ IMAD R2, R2, 0x186a0, R13 ; /* 0x000186a002027824 */
/* 0x000fd200078e020d */
/*07c0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0203 */
/*07d0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x7f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7multMatPfS_S_
.globl _Z7multMatPfS_S_
.p2align 8
.type _Z7multMatPfS_S_,@function
_Z7multMatPfS_S_:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
v_bfe_u32 v3, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v1, 0x186a0
v_ashrrev_i32_e32 v7, 31, v6
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[10:11], 2, v[6:7]
v_mov_b32_e32 v7, 0
v_mad_u64_u32 v[4:5], null, s14, s2, v[0:1]
v_lshlrev_b32_e32 v12, 2, v0
v_lshlrev_b32_e32 v0, 7, v3
v_add_co_u32 v10, vcc_lo, s4, v10
v_add_co_ci_u32_e32 v13, vcc_lo, s5, v11, vcc_lo
v_ashrrev_i32_e32 v5, 31, v4
v_or_b32_e32 v2, 0x1000, v12
v_add_nc_u32_e32 v8, v0, v12
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[5:6], 2, v[4:5]
v_add_nc_u32_e32 v9, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v5, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v11, vcc_lo, v10, v12
v_mov_b32_e32 v10, 0
v_add_co_ci_u32_e32 v12, vcc_lo, 0, v13, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_1:
s_lshl_b64 s[4:5], s[2:3], 5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_add_co_u32 v15, vcc_lo, s4, v3
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v7, vcc_lo
s_lshl_b64 s[4:5], s[2:3], 7
v_mad_u64_u32 v[13:14], null, v15, 0x61a80, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
v_mad_u64_u32 v[15:16], null, v17, 0x61a80, v[14:15]
v_add_co_u32 v16, vcc_lo, v11, s4
v_add_co_ci_u32_e32 v17, vcc_lo, s5, v12, vcc_lo
s_mov_b32 s4, 0
v_mov_b32_e32 v14, v15
global_load_b32 v15, v[16:17], off
global_load_b32 v14, v[13:14], off
v_mov_b32_e32 v13, v2
s_waitcnt vmcnt(1)
ds_store_b32 v8, v15
s_waitcnt vmcnt(0)
ds_store_b32 v9, v14
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
.LBB0_2:
v_add_nc_u32_e32 v14, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_i32_e32 v10, v10
s_add_i32 s4, s4, 4
ds_load_b32 v15, v13
ds_load_b32 v14, v14
s_cmp_eq_u32 s4, 0x61a80
s_waitcnt lgkmcnt(0)
v_dual_fmac_f32 v10, v14, v15 :: v_dual_add_nc_u32 v13, 0x80, v13
s_delay_alu instid0(VALU_DEP_1)
v_cvt_i32_f32_e32 v10, v10
s_cbranch_scc0 .LBB0_2
s_add_u32 s2, s2, 1
s_addc_u32 s3, s3, 0
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u64 s[2:3], 0xc35
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_1
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v4, 0x186a0, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
v_cvt_f32_i32_e32 v2, v10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7multMatPfS_S_
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 18
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7multMatPfS_S_, .Lfunc_end0-_Z7multMatPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7multMatPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7multMatPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 18
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0007c3b5_00000000-6_matrix_mult_tiles.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3675:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3675:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z3fooPf
.type _Z3fooPf, @function
_Z3fooPf:
.LFB3669:
.cfi_startproc
endbr64
movq %rdi, %rcx
leaq 400000(%rdi), %rdx
movabsq $40000400000, %rax
addq %rax, %rcx
movss .LC0(%rip), %xmm0
.L4:
leaq -400000(%rdx), %rax
.L5:
movss %xmm0, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L5
addq $400000, %rdx
cmpq %rcx, %rdx
jne .L4
ret
.cfi_endproc
.LFE3669:
.size _Z3fooPf, .-_Z3fooPf
.globl _Z4multPfS_S_
.type _Z4multPfS_S_, @function
_Z4multPfS_S_:
.LFB3670:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %r14
movq %rsi, %r13
movq %rdx, %r12
movl $0, %ebx
movabsq $40000000000, %rbp
movabsq $-40000000000, %r10
movl $0, %r9d
.L9:
leaq 0(%r13,%rbp), %rsi
imulq $400000, %rbx, %r8
leaq (%r14,%r8), %r11
addq %r12, %r8
movl $0, %edi
.L13:
leaq (%rsi,%r10), %rax
movq %r11, %rdx
movl %r9d, %ecx
.L10:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
addss %xmm1, %xmm0
cvttss2sil %xmm0, %ecx
addq $4, %rdx
addq $400000, %rax
cmpq %rsi, %rax
jne .L10
pxor %xmm0, %xmm0
cvtsi2ssl %ecx, %xmm0
movss %xmm0, (%r8,%rdi,4)
addq $1, %rdi
addq $4, %rsi
cmpq $100000, %rdi
jne .L13
addq $1, %rbx
cmpq $100000, %rbx
jne .L9
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _Z4multPfS_S_, .-_Z4multPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.text
.globl _Z7mostrarPf
.type _Z7mostrarPf, @function
_Z7mostrarPf:
.LFB3671:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $8, %rsp
.cfi_def_cfa_offset 48
leaq 400000(%rdi), %rbp
leaq _ZSt4cout(%rip), %r12
leaq .LC1(%rip), %r13
jmp .L17
.L24:
call _ZSt16__throw_bad_castv@PLT
.L25:
movzbl 67(%rbx), %eax
.L21:
movsbl %al, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $400000, %rbp
.L17:
leaq -400000(%rbp), %rbx
.L18:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L18
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L24
cmpb $0, 56(%rbx)
jne .L25
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
jmp .L21
.cfi_endproc
.LFE3671:
.size _Z7mostrarPf, .-_Z7mostrarPf
.globl _Z30__device_stub__Z7multMatPfS_S_PfS_S_
.type _Z30__device_stub__Z7multMatPfS_S_PfS_S_, @function
_Z30__device_stub__Z7multMatPfS_S_PfS_S_:
.LFB3697:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L30
.L26:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7multMatPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L26
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z30__device_stub__Z7multMatPfS_S_PfS_S_, .-_Z30__device_stub__Z7multMatPfS_S_PfS_S_
.globl _Z7multMatPfS_S_
.type _Z7multMatPfS_S_, @function
_Z7multMatPfS_S_:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z7multMatPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z7multMatPfS_S_, .-_Z7multMatPfS_S_
.section .rodata.str1.1
.LC3:
.string "Tiempo invertido GPU = "
.LC4:
.string "s\n"
.text
.globl main
.type main, @function
main:
.LFB3672:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $72, %rsp
.cfi_def_cfa_offset 128
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movabsq $5640261632, %r12
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbp
movq %r12, %rdi
call _Znam@PLT
movq %rax, %rbx
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r14
movq %r12, %rdi
call _Znam@PLT
movq %rax, %r13
movq %rbp, %rdi
call _Z3fooPf
movq %rbx, %rdi
call _Z3fooPf
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl $3125, 44(%rsp)
movl $3125, 48(%rsp)
movl $1, 52(%rsp)
leaq 8(%rsp), %rdi
movabsq $40000000000, %r12
movq %r12, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
call clock@PLT
movq %rax, %r15
movl $1, %ecx
movq %r12, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L38
.L35:
movl $2, %ecx
movabsq $40000000000, %rdx
movq 24(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
call clock@PLT
subq %r15, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC2(%rip), %xmm0
movq %xmm0, %r12
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r12, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movl $4, %esi
movq %rbp, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %rbx, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r14, %rdi
call _ZdlPvm@PLT
movl $4, %esi
movq %r13, %rdi
call _ZdlPvm@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L39
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L38:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z7multMatPfS_S_PfS_S_
jmp .L35
.L39:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3672:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z7multMatPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z7multMatPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1073741824
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mult_tiles.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z3fooPf # -- Begin function _Z3fooPf
.p2align 4, 0x90
.type _Z3fooPf,@function
_Z3fooPf: # @_Z3fooPf
.cfi_startproc
# %bb.0:
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_2 Depth 2
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # Parent Loop BB0_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rdi,%rcx,4) # imm = 0x40000000
incq %rcx
cmpq $100000, %rcx # imm = 0x186A0
jne .LBB0_2
# %bb.3: # in Loop: Header=BB0_1 Depth=1
incq %rax
addq $400000, %rdi # imm = 0x61A80
cmpq $100000, %rax # imm = 0x186A0
jne .LBB0_1
# %bb.4:
retq
.Lfunc_end0:
.size _Z3fooPf, .Lfunc_end0-_Z3fooPf
.cfi_endproc
# -- End function
.globl _Z4multPfS_S_ # -- Begin function _Z4multPfS_S_
.p2align 4, 0x90
.type _Z4multPfS_S_,@function
_Z4multPfS_S_: # @_Z4multPfS_S_
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # %.preheader19
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
# Child Loop BB1_3 Depth 3
imulq $400000, %rax, %rcx # imm = 0x61A80
addq %rdx, %rcx
movq %rsi, %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_2: # %.preheader
# Parent Loop BB1_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_3 Depth 3
xorl %r10d, %r10d
movq %r8, %r11
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_1 Depth=1
# Parent Loop BB1_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rdi,%r10,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
mulss (%r11), %xmm0
xorps %xmm1, %xmm1
cvtsi2ss %ebx, %xmm1
addss %xmm0, %xmm1
cvttss2si %xmm1, %ebx
incq %r10
addq $400000, %r11 # imm = 0x61A80
cmpq $100000, %r10 # imm = 0x186A0
jne .LBB1_3
# %bb.4: # in Loop: Header=BB1_2 Depth=2
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, (%rcx,%r9,4)
incq %r9
addq $4, %r8
cmpq $100000, %r9 # imm = 0x186A0
jne .LBB1_2
# %bb.5: # in Loop: Header=BB1_1 Depth=1
incq %rax
addq $400000, %rdi # imm = 0x61A80
cmpq $100000, %rax # imm = 0x186A0
jne .LBB1_1
# %bb.6:
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z4multPfS_S_, .Lfunc_end1-_Z4multPfS_S_
.cfi_endproc
# -- End function
.globl _Z7mostrarPf # -- Begin function _Z7mostrarPf
.p2align 4, 0x90
.type _Z7mostrarPf,@function
_Z7mostrarPf: # @_Z7mostrarPf
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
xorl %r15d, %r15d
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_6: # in Loop: Header=BB2_1 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_7: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
# in Loop: Header=BB2_1 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $400000, %rbx # imm = 0x61A80
cmpq $100000, %r15 # imm = 0x186A0
je .LBB2_8
.LBB2_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_2: # Parent Loop BB2_1 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $100000, %r14 # imm = 0x186A0
jne .LBB2_2
# %bb.3: # in Loop: Header=BB2_1 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_9
# %bb.4: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
# in Loop: Header=BB2_1 Depth=1
cmpb $0, 56(%r14)
je .LBB2_6
# %bb.5: # in Loop: Header=BB2_1 Depth=1
movzbl 67(%r14), %eax
jmp .LBB2_7
.LBB2_8:
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_9:
.cfi_def_cfa_offset 32
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size _Z7mostrarPf, .Lfunc_end2-_Z7mostrarPf
.cfi_endproc
# -- End function
.globl _Z22__device_stub__multMatPfS_S_ # -- Begin function _Z22__device_stub__multMatPfS_S_
.p2align 4, 0x90
.type _Z22__device_stub__multMatPfS_S_,@function
_Z22__device_stub__multMatPfS_S_: # @_Z22__device_stub__multMatPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7multMatPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z22__device_stub__multMatPfS_S_, .Lfunc_end3-_Z22__device_stub__multMatPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $5640261632, %r12 # imm = 0x1502F9000
movq %r12, %rdi
callq _Znam
movq %rax, %rbx
movq %r12, %rdi
callq _Znam
movq %rax, %r14
movq %r12, %rdi
callq _Znam
movq %rax, %r15
movq %r12, %rdi
callq _Znam
movq %rax, %r12
xorl %eax, %eax
movq %rbx, %rcx
.p2align 4, 0x90
.LBB4_1: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB4_2 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_2: # Parent Loop BB4_1 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rcx,%rdx,4) # imm = 0x40000000
incq %rdx
cmpq $100000, %rdx # imm = 0x186A0
jne .LBB4_2
# %bb.3: # in Loop: Header=BB4_1 Depth=1
incq %rax
addq $400000, %rcx # imm = 0x61A80
cmpq $100000, %rax # imm = 0x186A0
jne .LBB4_1
# %bb.4: # %.preheader.i22.preheader
xorl %eax, %eax
movq %r14, %rcx
.p2align 4, 0x90
.LBB4_5: # %.preheader.i22
# =>This Loop Header: Depth=1
# Child Loop BB4_6 Depth 2
xorl %edx, %edx
.p2align 4, 0x90
.LBB4_6: # Parent Loop BB4_5 Depth=1
# => This Inner Loop Header: Depth=2
movl $1073741824, (%rcx,%rdx,4) # imm = 0x40000000
incq %rdx
cmpq $100000, %rdx # imm = 0x186A0
jne .LBB4_6
# %bb.7: # in Loop: Header=BB4_5 Depth=1
incq %rax
addq $400000, %rcx # imm = 0x61A80
cmpq $100000, %rax # imm = 0x186A0
jne .LBB4_5
# %bb.8: # %_Z3fooPf.exit29
movabsq $40000000000, %r13 # imm = 0x9502F9000
leaq 24(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
callq clock
movq %rax, %rbp
movq 24(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r14, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
movabsq $13421772803125, %rdi # imm = 0xC3500000C35
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7multMatPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
movq 8(%rsp), %rsi
movq %r12, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
callq clock
subq %rbp, %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI4_0(%rip), %xmm0
movsd %xmm0, 32(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $23, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 32(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.2, %esi
movl $2, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq _ZdlPv
movq %r14, %rdi
callq _ZdlPv
movq %r15, %rdi
callq _ZdlPv
movq %r12, %rdi
callq _ZdlPv
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7multMatPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type _Z7multMatPfS_S_,@object # @_Z7multMatPfS_S_
.section .rodata,"a",@progbits
.globl _Z7multMatPfS_S_
.p2align 3, 0x0
_Z7multMatPfS_S_:
.quad _Z22__device_stub__multMatPfS_S_
.size _Z7multMatPfS_S_, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Tiempo invertido GPU = "
.size .L.str.1, 24
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "s\n"
.size .L.str.2, 3
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7multMatPfS_S_"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__multMatPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZSt4cout
.addrsig_sym _Z7multMatPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | // seems my bitcasting is/was broken ('is', at time of writing this test, 'was' since I probably fixed it by now :-) )
// this code tests this, sortof
// (hmmm, edit, seems to be ok, in fact...)
#include "cuda.h"
#include <iostream>
#include <cassert>
using namespace std;
__global__ void mykernel(int *int1, float *f1, int *int2) {
f1[0] = *(float *)&int1[0];
int2[0] = *(int *)&f1[0];
}
__global__ void floattoint(int *out, float *in) {
out[0] = *(int *)&in[0];
}
__global__ void inttofloat(float *out, int *in) {
out[0] = *(float *)&in[0];
}
int main(int argc, char *argv[]) {
int N = 32;
int *int1_host = new int[N];
float *f1_host = new float[N];
int *int2_host = new int[N];
// float *f2_host = new float[N];
int *int1_gpu;
float *f1_gpu;
int *int2_gpu;
// float *f2_gpu;
cudaMalloc((void**)&int1_gpu, N * sizeof(float));
cudaMalloc((void**)&f1_gpu, N * sizeof(float));
cudaMalloc((void**)&int2_gpu, N * sizeof(float));
// cudaMalloc(&(void**)f2_gpu, N * sizeof(float));
int1_host[0] = 123;
cudaMemcpy(int1_gpu, int1_host, N * sizeof(float), cudaMemcpyHostToDevice);
mykernel<<<dim3(1,1,1), dim3(32,1,1)>>>(int1_gpu, f1_gpu, int2_gpu);
cudaMemcpy(f1_host, f1_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(int2_host, int2_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cout << "this should NOT be 123, should be some weird float value, not even slightly close to 123 :" << endl;
cout << "f1[0] " << f1_host[0] << endl;
assert(f1_host[0] != 123.0f);
cout << "this SHOULD be 123 :" << endl;
cout << "int2[0] " << int2_host[0] << endl;
assert(int2_host[0] == 123);
int1_host[0] = 777;
cudaMemcpy(int1_gpu, int1_host, N * sizeof(float), cudaMemcpyHostToDevice);
cout << "after copy to device" << endl;
inttofloat<<<dim3(1,1,1), dim3(32,1,1)>>>(f1_gpu, int1_gpu);
cout << "after kernel call 2" << endl;
cudaMemcpy(f1_host, f1_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cout << "f1[0]" << f1_host[0] << endl;
assert(f1_host[0] != 777.0f);
floattoint<<<dim3(1,1,1), dim3(32,1,1)>>>(int2_gpu, f1_gpu);
cout << "after kernel call 3" << endl;
cudaMemcpy(int2_host, int2_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cout << "int2[0]" << int2_host[0] << endl;
assert(int2_host[0] == 777);
return 0;
} | code for sm_80
Function : _Z10inttofloatPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fca00078e00ff */
/*0070*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10floattointPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fca00078e00ff */
/*0070*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8mykernelPiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fc600078e00ff */
/*0090*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe8000c101904 */
/*00a0*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | // seems my bitcasting is/was broken ('is', at time of writing this test, 'was' since I probably fixed it by now :-) )
// this code tests this, sortof
// (hmmm, edit, seems to be ok, in fact...)
#include "cuda.h"
#include <iostream>
#include <cassert>
using namespace std;
__global__ void mykernel(int *int1, float *f1, int *int2) {
f1[0] = *(float *)&int1[0];
int2[0] = *(int *)&f1[0];
}
__global__ void floattoint(int *out, float *in) {
out[0] = *(int *)&in[0];
}
__global__ void inttofloat(float *out, int *in) {
out[0] = *(float *)&in[0];
}
int main(int argc, char *argv[]) {
int N = 32;
int *int1_host = new int[N];
float *f1_host = new float[N];
int *int2_host = new int[N];
// float *f2_host = new float[N];
int *int1_gpu;
float *f1_gpu;
int *int2_gpu;
// float *f2_gpu;
cudaMalloc((void**)&int1_gpu, N * sizeof(float));
cudaMalloc((void**)&f1_gpu, N * sizeof(float));
cudaMalloc((void**)&int2_gpu, N * sizeof(float));
// cudaMalloc(&(void**)f2_gpu, N * sizeof(float));
int1_host[0] = 123;
cudaMemcpy(int1_gpu, int1_host, N * sizeof(float), cudaMemcpyHostToDevice);
mykernel<<<dim3(1,1,1), dim3(32,1,1)>>>(int1_gpu, f1_gpu, int2_gpu);
cudaMemcpy(f1_host, f1_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(int2_host, int2_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cout << "this should NOT be 123, should be some weird float value, not even slightly close to 123 :" << endl;
cout << "f1[0] " << f1_host[0] << endl;
assert(f1_host[0] != 123.0f);
cout << "this SHOULD be 123 :" << endl;
cout << "int2[0] " << int2_host[0] << endl;
assert(int2_host[0] == 123);
int1_host[0] = 777;
cudaMemcpy(int1_gpu, int1_host, N * sizeof(float), cudaMemcpyHostToDevice);
cout << "after copy to device" << endl;
inttofloat<<<dim3(1,1,1), dim3(32,1,1)>>>(f1_gpu, int1_gpu);
cout << "after kernel call 2" << endl;
cudaMemcpy(f1_host, f1_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cout << "f1[0]" << f1_host[0] << endl;
assert(f1_host[0] != 777.0f);
floattoint<<<dim3(1,1,1), dim3(32,1,1)>>>(int2_gpu, f1_gpu);
cout << "after kernel call 3" << endl;
cudaMemcpy(int2_host, int2_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cout << "int2[0]" << int2_host[0] << endl;
assert(int2_host[0] == 777);
return 0;
} | .file "tmpxft_00112297_00000000-6_test_bitcast.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8mykernelPiPfS_PiPfS_
.type _Z31__device_stub__Z8mykernelPiPfS_PiPfS_, @function
_Z31__device_stub__Z8mykernelPiPfS_PiPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mykernelPiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z8mykernelPiPfS_PiPfS_, .-_Z31__device_stub__Z8mykernelPiPfS_PiPfS_
.globl _Z8mykernelPiPfS_
.type _Z8mykernelPiPfS_, @function
_Z8mykernelPiPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8mykernelPiPfS_PiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8mykernelPiPfS_, .-_Z8mykernelPiPfS_
.globl _Z32__device_stub__Z10floattointPiPfPiPf
.type _Z32__device_stub__Z10floattointPiPfPiPf, @function
_Z32__device_stub__Z10floattointPiPfPiPf:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10floattointPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z32__device_stub__Z10floattointPiPfPiPf, .-_Z32__device_stub__Z10floattointPiPfPiPf
.globl _Z10floattointPiPf
.type _Z10floattointPiPf, @function
_Z10floattointPiPf:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10floattointPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z10floattointPiPf, .-_Z10floattointPiPf
.globl _Z32__device_stub__Z10inttofloatPfPiPfPi
.type _Z32__device_stub__Z10inttofloatPfPiPfPi, @function
_Z32__device_stub__Z10inttofloatPfPiPfPi:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10inttofloatPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z32__device_stub__Z10inttofloatPfPiPfPi, .-_Z32__device_stub__Z10inttofloatPfPiPfPi
.globl _Z10inttofloatPfPi
.type _Z10inttofloatPfPi, @function
_Z10inttofloatPfPi:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10inttofloatPfPiPfPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z10inttofloatPfPi, .-_Z10inttofloatPfPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "this should NOT be 123, should be some weird float value, not even slightly close to 123 :"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "f1[0] "
.LC2:
.string "this SHOULD be 123 :"
.LC3:
.string "int2[0] "
.LC4:
.string "after copy to device"
.LC5:
.string "after kernel call 2"
.LC6:
.string "f1[0]"
.LC7:
.string "after kernel call 3"
.LC8:
.string "int2[0]"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $128, %edi
call _Znam@PLT
movq %rax, %r12
movl $128, %edi
call _Znam@PLT
movq %rax, %rbp
movl $128, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $123, (%r12)
movl $1, %ecx
movl $128, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%rbx), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $777, (%r12)
movl $1, %ecx
movl $128, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L29:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%rbx), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8mykernelPiPfS_PiPfS_
jmp .L28
.L34:
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z10inttofloatPfPiPfPi
jmp .L29
.L35:
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z10floattointPiPfPiPf
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z10inttofloatPfPi"
.LC10:
.string "_Z10floattointPiPf"
.LC11:
.string "_Z8mykernelPiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10inttofloatPfPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10floattointPiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelPiPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | // seems my bitcasting is/was broken ('is', at time of writing this test, 'was' since I probably fixed it by now :-) )
// this code tests this, sortof
// (hmmm, edit, seems to be ok, in fact...)
#include "cuda.h"
#include <iostream>
#include <cassert>
using namespace std;
__global__ void mykernel(int *int1, float *f1, int *int2) {
f1[0] = *(float *)&int1[0];
int2[0] = *(int *)&f1[0];
}
__global__ void floattoint(int *out, float *in) {
out[0] = *(int *)&in[0];
}
__global__ void inttofloat(float *out, int *in) {
out[0] = *(float *)&in[0];
}
int main(int argc, char *argv[]) {
int N = 32;
int *int1_host = new int[N];
float *f1_host = new float[N];
int *int2_host = new int[N];
// float *f2_host = new float[N];
int *int1_gpu;
float *f1_gpu;
int *int2_gpu;
// float *f2_gpu;
cudaMalloc((void**)&int1_gpu, N * sizeof(float));
cudaMalloc((void**)&f1_gpu, N * sizeof(float));
cudaMalloc((void**)&int2_gpu, N * sizeof(float));
// cudaMalloc(&(void**)f2_gpu, N * sizeof(float));
int1_host[0] = 123;
cudaMemcpy(int1_gpu, int1_host, N * sizeof(float), cudaMemcpyHostToDevice);
mykernel<<<dim3(1,1,1), dim3(32,1,1)>>>(int1_gpu, f1_gpu, int2_gpu);
cudaMemcpy(f1_host, f1_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(int2_host, int2_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cout << "this should NOT be 123, should be some weird float value, not even slightly close to 123 :" << endl;
cout << "f1[0] " << f1_host[0] << endl;
assert(f1_host[0] != 123.0f);
cout << "this SHOULD be 123 :" << endl;
cout << "int2[0] " << int2_host[0] << endl;
assert(int2_host[0] == 123);
int1_host[0] = 777;
cudaMemcpy(int1_gpu, int1_host, N * sizeof(float), cudaMemcpyHostToDevice);
cout << "after copy to device" << endl;
inttofloat<<<dim3(1,1,1), dim3(32,1,1)>>>(f1_gpu, int1_gpu);
cout << "after kernel call 2" << endl;
cudaMemcpy(f1_host, f1_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cout << "f1[0]" << f1_host[0] << endl;
assert(f1_host[0] != 777.0f);
floattoint<<<dim3(1,1,1), dim3(32,1,1)>>>(int2_gpu, f1_gpu);
cout << "after kernel call 3" << endl;
cudaMemcpy(int2_host, int2_gpu, N * sizeof(float), cudaMemcpyDeviceToHost);
cout << "int2[0]" << int2_host[0] << endl;
assert(int2_host[0] == 777);
return 0;
} | // seems my bitcasting is/was broken ('is', at time of writing this test, 'was' since I probably fixed it by now :-) )
// this code tests this, sortof
// (hmmm, edit, seems to be ok, in fact...)
#include "hip/hip_runtime.h"
#include <iostream>
#include <cassert>
using namespace std;
__global__ void mykernel(int *int1, float *f1, int *int2) {
f1[0] = *(float *)&int1[0];
int2[0] = *(int *)&f1[0];
}
__global__ void floattoint(int *out, float *in) {
out[0] = *(int *)&in[0];
}
__global__ void inttofloat(float *out, int *in) {
out[0] = *(float *)&in[0];
}
int main(int argc, char *argv[]) {
int N = 32;
int *int1_host = new int[N];
float *f1_host = new float[N];
int *int2_host = new int[N];
// float *f2_host = new float[N];
int *int1_gpu;
float *f1_gpu;
int *int2_gpu;
// float *f2_gpu;
hipMalloc((void**)&int1_gpu, N * sizeof(float));
hipMalloc((void**)&f1_gpu, N * sizeof(float));
hipMalloc((void**)&int2_gpu, N * sizeof(float));
// cudaMalloc(&(void**)f2_gpu, N * sizeof(float));
int1_host[0] = 123;
hipMemcpy(int1_gpu, int1_host, N * sizeof(float), hipMemcpyHostToDevice);
mykernel<<<dim3(1,1,1), dim3(32,1,1)>>>(int1_gpu, f1_gpu, int2_gpu);
hipMemcpy(f1_host, f1_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(int2_host, int2_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
cout << "this should NOT be 123, should be some weird float value, not even slightly close to 123 :" << endl;
cout << "f1[0] " << f1_host[0] << endl;
assert(f1_host[0] != 123.0f);
cout << "this SHOULD be 123 :" << endl;
cout << "int2[0] " << int2_host[0] << endl;
assert(int2_host[0] == 123);
int1_host[0] = 777;
hipMemcpy(int1_gpu, int1_host, N * sizeof(float), hipMemcpyHostToDevice);
cout << "after copy to device" << endl;
inttofloat<<<dim3(1,1,1), dim3(32,1,1)>>>(f1_gpu, int1_gpu);
cout << "after kernel call 2" << endl;
hipMemcpy(f1_host, f1_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
cout << "f1[0]" << f1_host[0] << endl;
assert(f1_host[0] != 777.0f);
floattoint<<<dim3(1,1,1), dim3(32,1,1)>>>(int2_gpu, f1_gpu);
cout << "after kernel call 3" << endl;
hipMemcpy(int2_host, int2_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
cout << "int2[0]" << int2_host[0] << endl;
assert(int2_host[0] == 777);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | // seems my bitcasting is/was broken ('is', at time of writing this test, 'was' since I probably fixed it by now :-) )
// this code tests this, sortof
// (hmmm, edit, seems to be ok, in fact...)
#include "hip/hip_runtime.h"
#include <iostream>
#include <cassert>
using namespace std;
__global__ void mykernel(int *int1, float *f1, int *int2) {
f1[0] = *(float *)&int1[0];
int2[0] = *(int *)&f1[0];
}
__global__ void floattoint(int *out, float *in) {
out[0] = *(int *)&in[0];
}
__global__ void inttofloat(float *out, int *in) {
out[0] = *(float *)&in[0];
}
int main(int argc, char *argv[]) {
int N = 32;
int *int1_host = new int[N];
float *f1_host = new float[N];
int *int2_host = new int[N];
// float *f2_host = new float[N];
int *int1_gpu;
float *f1_gpu;
int *int2_gpu;
// float *f2_gpu;
hipMalloc((void**)&int1_gpu, N * sizeof(float));
hipMalloc((void**)&f1_gpu, N * sizeof(float));
hipMalloc((void**)&int2_gpu, N * sizeof(float));
// cudaMalloc(&(void**)f2_gpu, N * sizeof(float));
int1_host[0] = 123;
hipMemcpy(int1_gpu, int1_host, N * sizeof(float), hipMemcpyHostToDevice);
mykernel<<<dim3(1,1,1), dim3(32,1,1)>>>(int1_gpu, f1_gpu, int2_gpu);
hipMemcpy(f1_host, f1_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(int2_host, int2_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
cout << "this should NOT be 123, should be some weird float value, not even slightly close to 123 :" << endl;
cout << "f1[0] " << f1_host[0] << endl;
assert(f1_host[0] != 123.0f);
cout << "this SHOULD be 123 :" << endl;
cout << "int2[0] " << int2_host[0] << endl;
assert(int2_host[0] == 123);
int1_host[0] = 777;
hipMemcpy(int1_gpu, int1_host, N * sizeof(float), hipMemcpyHostToDevice);
cout << "after copy to device" << endl;
inttofloat<<<dim3(1,1,1), dim3(32,1,1)>>>(f1_gpu, int1_gpu);
cout << "after kernel call 2" << endl;
hipMemcpy(f1_host, f1_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
cout << "f1[0]" << f1_host[0] << endl;
assert(f1_host[0] != 777.0f);
floattoint<<<dim3(1,1,1), dim3(32,1,1)>>>(int2_gpu, f1_gpu);
cout << "after kernel call 3" << endl;
hipMemcpy(int2_host, int2_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
cout << "int2[0]" << int2_host[0] << endl;
assert(int2_host[0] == 777);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelPiPfS_
.globl _Z8mykernelPiPfS_
.p2align 8
.type _Z8mykernelPiPfS_,@function
_Z8mykernelPiPfS_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_clause 0x1
global_store_b32 v0, v1, s[6:7]
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelPiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelPiPfS_, .Lfunc_end0-_Z8mykernelPiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10floattointPiPf
.globl _Z10floattointPiPf
.p2align 8
.type _Z10floattointPiPf,@function
_Z10floattointPiPf:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10floattointPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10floattointPiPf, .Lfunc_end1-_Z10floattointPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10inttofloatPfPi
.globl _Z10inttofloatPfPi
.p2align 8
.type _Z10inttofloatPfPi,@function
_Z10inttofloatPfPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10inttofloatPfPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10inttofloatPfPi, .Lfunc_end2-_Z10inttofloatPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelPiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z8mykernelPiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10floattointPiPf
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10floattointPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10inttofloatPfPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10inttofloatPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | // seems my bitcasting is/was broken ('is', at time of writing this test, 'was' since I probably fixed it by now :-) )
// this code tests this, sortof
// (hmmm, edit, seems to be ok, in fact...)
#include "hip/hip_runtime.h"
#include <iostream>
#include <cassert>
using namespace std;
__global__ void mykernel(int *int1, float *f1, int *int2) {
f1[0] = *(float *)&int1[0];
int2[0] = *(int *)&f1[0];
}
__global__ void floattoint(int *out, float *in) {
out[0] = *(int *)&in[0];
}
__global__ void inttofloat(float *out, int *in) {
out[0] = *(float *)&in[0];
}
int main(int argc, char *argv[]) {
int N = 32;
int *int1_host = new int[N];
float *f1_host = new float[N];
int *int2_host = new int[N];
// float *f2_host = new float[N];
int *int1_gpu;
float *f1_gpu;
int *int2_gpu;
// float *f2_gpu;
hipMalloc((void**)&int1_gpu, N * sizeof(float));
hipMalloc((void**)&f1_gpu, N * sizeof(float));
hipMalloc((void**)&int2_gpu, N * sizeof(float));
// cudaMalloc(&(void**)f2_gpu, N * sizeof(float));
int1_host[0] = 123;
hipMemcpy(int1_gpu, int1_host, N * sizeof(float), hipMemcpyHostToDevice);
mykernel<<<dim3(1,1,1), dim3(32,1,1)>>>(int1_gpu, f1_gpu, int2_gpu);
hipMemcpy(f1_host, f1_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(int2_host, int2_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
cout << "this should NOT be 123, should be some weird float value, not even slightly close to 123 :" << endl;
cout << "f1[0] " << f1_host[0] << endl;
assert(f1_host[0] != 123.0f);
cout << "this SHOULD be 123 :" << endl;
cout << "int2[0] " << int2_host[0] << endl;
assert(int2_host[0] == 123);
int1_host[0] = 777;
hipMemcpy(int1_gpu, int1_host, N * sizeof(float), hipMemcpyHostToDevice);
cout << "after copy to device" << endl;
inttofloat<<<dim3(1,1,1), dim3(32,1,1)>>>(f1_gpu, int1_gpu);
cout << "after kernel call 2" << endl;
hipMemcpy(f1_host, f1_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
cout << "f1[0]" << f1_host[0] << endl;
assert(f1_host[0] != 777.0f);
floattoint<<<dim3(1,1,1), dim3(32,1,1)>>>(int2_gpu, f1_gpu);
cout << "after kernel call 3" << endl;
hipMemcpy(int2_host, int2_gpu, N * sizeof(float), hipMemcpyDeviceToHost);
cout << "int2[0]" << int2_host[0] << endl;
assert(int2_host[0] == 777);
return 0;
} | .text
.file "test_bitcast.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__mykernelPiPfS_ # -- Begin function _Z23__device_stub__mykernelPiPfS_
.p2align 4, 0x90
.type _Z23__device_stub__mykernelPiPfS_,@function
_Z23__device_stub__mykernelPiPfS_: # @_Z23__device_stub__mykernelPiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mykernelPiPfS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelPiPfS_, .Lfunc_end0-_Z23__device_stub__mykernelPiPfS_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__floattointPiPf # -- Begin function _Z25__device_stub__floattointPiPf
.p2align 4, 0x90
.type _Z25__device_stub__floattointPiPf,@function
_Z25__device_stub__floattointPiPf: # @_Z25__device_stub__floattointPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10floattointPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__floattointPiPf, .Lfunc_end1-_Z25__device_stub__floattointPiPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__inttofloatPfPi # -- Begin function _Z25__device_stub__inttofloatPfPi
.p2align 4, 0x90
.type _Z25__device_stub__inttofloatPfPi,@function
_Z25__device_stub__inttofloatPfPi: # @_Z25__device_stub__inttofloatPfPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10inttofloatPfPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z25__device_stub__inttofloatPfPi, .Lfunc_end2-_Z25__device_stub__inttofloatPfPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movl $128, %edi
callq _Znam
movq %rax, %r13
movl $128, %edi
callq _Znam
movq %rax, %r12
movl $128, %edi
callq _Znam
movq %rax, %rbx
leaq 88(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 80(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movl $123, (%r13)
movq 88(%rsp), %rdi
movl $128, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 31(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 88(%rsp), %rax
movq 8(%rsp), %rcx
movq 80(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 24(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8mykernelPiPfS_, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movl $128, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 80(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $90, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbp
testq %rbp, %rbp
je .LBB3_43
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB3_5
# %bb.4:
movzbl 67(%rbp), %eax
jmp .LBB3_6
.LBB3_5:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB3_43
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i48
cmpb $0, 56(%rbp)
je .LBB3_9
# %bb.8:
movzbl 67(%rbp), %ecx
jmp .LBB3_10
.LBB3_9:
movq %rbp, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit51
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbp
testq %rbp, %rbp
je .LBB3_43
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i53
cmpb $0, 56(%rbp)
je .LBB3_13
# %bb.12:
movzbl 67(%rbp), %eax
jmp .LBB3_14
.LBB3_13:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB3_43
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i58
cmpb $0, 56(%rbp)
je .LBB3_17
# %bb.16:
movzbl 67(%rbp), %ecx
jmp .LBB3_18
.LBB3_17:
movq %rbp, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit61
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $777, (%r13) # imm = 0x309
movq 88(%rsp), %rdi
movl $128, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
movabsq $4294967297, %rbp # imm = 0x100000001
je .LBB3_43
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i63
cmpb $0, 56(%r13)
je .LBB3_21
# %bb.20:
movzbl 67(%r13), %eax
jmp .LBB3_22
.LBB3_21:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit66
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_24
# %bb.23:
movq 8(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10inttofloatPfPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_24:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i68
cmpb $0, 56(%r13)
je .LBB3_27
# %bb.26:
movzbl 67(%r13), %eax
jmp .LBB3_28
.LBB3_27:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit71
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
movl $128, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB3_43
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i73
cmpb $0, 56(%r12)
je .LBB3_31
# %bb.30:
movzbl 67(%r12), %ecx
jmp .LBB3_32
.LBB3_31:
movq %r12, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit76
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_34
# %bb.33:
movq 80(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10floattointPiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_34:
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_43
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78
cmpb $0, 56(%r14)
je .LBB3_37
# %bb.36:
movzbl 67(%r14), %eax
jmp .LBB3_38
.LBB3_37:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit81
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 80(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_43
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83
cmpb $0, 56(%rbx)
je .LBB3_41
# %bb.40:
movzbl 67(%rbx), %ecx
jmp .LBB3_42
.LBB3_41:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_43:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelPiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10floattointPiPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10inttofloatPfPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelPiPfS_,@object # @_Z8mykernelPiPfS_
.section .rodata,"a",@progbits
.globl _Z8mykernelPiPfS_
.p2align 3, 0x0
_Z8mykernelPiPfS_:
.quad _Z23__device_stub__mykernelPiPfS_
.size _Z8mykernelPiPfS_, 8
.type _Z10floattointPiPf,@object # @_Z10floattointPiPf
.globl _Z10floattointPiPf
.p2align 3, 0x0
_Z10floattointPiPf:
.quad _Z25__device_stub__floattointPiPf
.size _Z10floattointPiPf, 8
.type _Z10inttofloatPfPi,@object # @_Z10inttofloatPfPi
.globl _Z10inttofloatPfPi
.p2align 3, 0x0
_Z10inttofloatPfPi:
.quad _Z25__device_stub__inttofloatPfPi
.size _Z10inttofloatPfPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "this should NOT be 123, should be some weird float value, not even slightly close to 123 :"
.size .L.str, 91
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "f1[0] "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "this SHOULD be 123 :"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "int2[0] "
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "after copy to device"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "after kernel call 2"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "f1[0]"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "after kernel call 3"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "int2[0]"
.size .L.str.8, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8mykernelPiPfS_"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10floattointPiPf"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10inttofloatPfPi"
.size .L__unnamed_3, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelPiPfS_
.addrsig_sym _Z25__device_stub__floattointPiPf
.addrsig_sym _Z25__device_stub__inttofloatPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelPiPfS_
.addrsig_sym _Z10floattointPiPf
.addrsig_sym _Z10inttofloatPfPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10inttofloatPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fca00078e00ff */
/*0070*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10floattointPiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fca00078e00ff */
/*0070*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0080*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0090*/ BRA 0x90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8mykernelPiPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x160] ; /* 0x0000580000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0040*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0050*/ MOV R4, c[0x0][0x168] ; /* 0x00005a0000047a02 */
/* 0x000fe20000000f00 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*0070*/ MOV R6, c[0x0][0x170] ; /* 0x00005c0000067a02 */
/* 0x000fe20000000f00 */
/*0080*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x174] ; /* 0x00005d00ff077624 */
/* 0x000fc600078e00ff */
/*0090*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe8000c101904 */
/*00a0*/ STG.E [R6.64], R3 ; /* 0x0000000306007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8mykernelPiPfS_
.globl _Z8mykernelPiPfS_
.p2align 8
.type _Z8mykernelPiPfS_,@function
_Z8mykernelPiPfS_:
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[4:5], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_clause 0x1
global_store_b32 v0, v1, s[6:7]
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8mykernelPiPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8mykernelPiPfS_, .Lfunc_end0-_Z8mykernelPiPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10floattointPiPf
.globl _Z10floattointPiPf
.p2align 8
.type _Z10floattointPiPf,@function
_Z10floattointPiPf:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10floattointPiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10floattointPiPf, .Lfunc_end1-_Z10floattointPiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10inttofloatPfPi
.globl _Z10inttofloatPfPi
.p2align 8
.type _Z10inttofloatPfPi,@function
_Z10inttofloatPfPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_load_b32 s2, s[2:3], 0x0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10inttofloatPfPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z10inttofloatPfPi, .Lfunc_end2-_Z10inttofloatPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8mykernelPiPfS_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z8mykernelPiPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10floattointPiPf
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10floattointPiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10inttofloatPfPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z10inttofloatPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00112297_00000000-6_test_bitcast.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8mykernelPiPfS_PiPfS_
.type _Z31__device_stub__Z8mykernelPiPfS_PiPfS_, @function
_Z31__device_stub__Z8mykernelPiPfS_PiPfS_:
.LFB3694:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8mykernelPiPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z31__device_stub__Z8mykernelPiPfS_PiPfS_, .-_Z31__device_stub__Z8mykernelPiPfS_PiPfS_
.globl _Z8mykernelPiPfS_
.type _Z8mykernelPiPfS_, @function
_Z8mykernelPiPfS_:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8mykernelPiPfS_PiPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z8mykernelPiPfS_, .-_Z8mykernelPiPfS_
.globl _Z32__device_stub__Z10floattointPiPfPiPf
.type _Z32__device_stub__Z10floattointPiPfPiPf, @function
_Z32__device_stub__Z10floattointPiPfPiPf:
.LFB3696:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10floattointPiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3696:
.size _Z32__device_stub__Z10floattointPiPfPiPf, .-_Z32__device_stub__Z10floattointPiPfPiPf
.globl _Z10floattointPiPf
.type _Z10floattointPiPf, @function
_Z10floattointPiPf:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10floattointPiPfPiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _Z10floattointPiPf, .-_Z10floattointPiPf
.globl _Z32__device_stub__Z10inttofloatPfPiPfPi
.type _Z32__device_stub__Z10inttofloatPfPiPfPi, @function
_Z32__device_stub__Z10inttofloatPfPiPfPi:
.LFB3698:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10inttofloatPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3698:
.size _Z32__device_stub__Z10inttofloatPfPiPfPi, .-_Z32__device_stub__Z10inttofloatPfPiPfPi
.globl _Z10inttofloatPfPi
.type _Z10inttofloatPfPi, @function
_Z10inttofloatPfPi:
.LFB3699:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10inttofloatPfPiPfPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3699:
.size _Z10inttofloatPfPi, .-_Z10inttofloatPfPi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "this should NOT be 123, should be some weird float value, not even slightly close to 123 :"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "f1[0] "
.LC2:
.string "this SHOULD be 123 :"
.LC3:
.string "int2[0] "
.LC4:
.string "after copy to device"
.LC5:
.string "after kernel call 2"
.LC6:
.string "f1[0]"
.LC7:
.string "after kernel call 3"
.LC8:
.string "int2[0]"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $72, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $128, %edi
call _Znam@PLT
movq %rax, %r12
movl $128, %edi
call _Znam@PLT
movq %rax, %rbp
movl $128, %edi
call _Znam@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $123, (%r12)
movl $1, %ecx
movl $128, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L28:
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC1(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC2(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC3(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%rbx), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $777, (%r12)
movl $1, %ecx
movl $128, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L29:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %r12
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $128, %edx
movq 16(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC6(%rip), %rsi
movq %r12, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 0(%rbp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $32, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L30:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rbp
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $2, %ecx
movl $128, %edx
movq 24(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
leaq .LC8(%rip), %rsi
movq %rbp, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl (%rbx), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $72, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z31__device_stub__Z8mykernelPiPfS_PiPfS_
jmp .L28
.L34:
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z32__device_stub__Z10inttofloatPfPiPfPi
jmp .L29
.L35:
movq 16(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z32__device_stub__Z10floattointPiPfPiPf
jmp .L30
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC9:
.string "_Z10inttofloatPfPi"
.LC10:
.string "_Z10floattointPiPf"
.LC11:
.string "_Z8mykernelPiPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3701:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _Z10inttofloatPfPi(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z10floattointPiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z8mykernelPiPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3701:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test_bitcast.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__mykernelPiPfS_ # -- Begin function _Z23__device_stub__mykernelPiPfS_
.p2align 4, 0x90
.type _Z23__device_stub__mykernelPiPfS_,@function
_Z23__device_stub__mykernelPiPfS_: # @_Z23__device_stub__mykernelPiPfS_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8mykernelPiPfS_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__mykernelPiPfS_, .Lfunc_end0-_Z23__device_stub__mykernelPiPfS_
.cfi_endproc
# -- End function
.globl _Z25__device_stub__floattointPiPf # -- Begin function _Z25__device_stub__floattointPiPf
.p2align 4, 0x90
.type _Z25__device_stub__floattointPiPf,@function
_Z25__device_stub__floattointPiPf: # @_Z25__device_stub__floattointPiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10floattointPiPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__floattointPiPf, .Lfunc_end1-_Z25__device_stub__floattointPiPf
.cfi_endproc
# -- End function
.globl _Z25__device_stub__inttofloatPfPi # -- Begin function _Z25__device_stub__inttofloatPfPi
.p2align 4, 0x90
.type _Z25__device_stub__inttofloatPfPi,@function
_Z25__device_stub__inttofloatPfPi: # @_Z25__device_stub__inttofloatPfPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10inttofloatPfPi, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end2:
.size _Z25__device_stub__inttofloatPfPi, .Lfunc_end2-_Z25__device_stub__inttofloatPfPi
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %r14 # imm = 0x100000001
movl $128, %edi
callq _Znam
movq %rax, %r13
movl $128, %edi
callq _Znam
movq %rax, %r12
movl $128, %edi
callq _Znam
movq %rax, %rbx
leaq 88(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 8(%rsp), %rdi
movl $128, %esi
callq hipMalloc
leaq 80(%rsp), %rdi
movl $128, %esi
callq hipMalloc
movl $123, (%r13)
movq 88(%rsp), %rdi
movl $128, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
leaq 31(%r14), %r15
movq %r14, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movq 88(%rsp), %rax
movq 8(%rsp), %rcx
movq 80(%rsp), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 24(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 128(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z8mykernelPiPfS_, %edi
pushq 128(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
movq 8(%rsp), %rsi
movl $128, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movq 80(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $90, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbp
testq %rbp, %rbp
je .LBB3_43
# %bb.3: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbp)
je .LBB3_5
# %bb.4:
movzbl 67(%rbp), %eax
jmp .LBB3_6
.LBB3_5:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_6: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB3_43
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i48
cmpb $0, 56(%rbp)
je .LBB3_9
# %bb.8:
movzbl 67(%rbp), %ecx
jmp .LBB3_10
.LBB3_9:
movq %rbp, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit51
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbp
testq %rbp, %rbp
je .LBB3_43
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i53
cmpb $0, 56(%rbp)
je .LBB3_13
# %bb.12:
movzbl 67(%rbp), %eax
jmp .LBB3_14
.LBB3_13:
movq %rbp, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit56
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $_ZSt4cout, %edi
movl $.L.str.3, %esi
movl $8, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbp
testq %rbp, %rbp
je .LBB3_43
# %bb.15: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i58
cmpb $0, 56(%rbp)
je .LBB3_17
# %bb.16:
movzbl 67(%rbp), %ecx
jmp .LBB3_18
.LBB3_17:
movq %rbp, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbp), %rax
movq %rbp, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_18: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit61
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl $777, (%r13) # imm = 0x309
movq 88(%rsp), %rdi
movl $128, %edx
movq %r13, %rsi
movl $1, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
movabsq $4294967297, %rbp # imm = 0x100000001
je .LBB3_43
# %bb.19: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i63
cmpb $0, 56(%r13)
je .LBB3_21
# %bb.20:
movzbl 67(%r13), %eax
jmp .LBB3_22
.LBB3_21:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_22: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit66
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_24
# %bb.23:
movq 8(%rsp), %rax
movq 88(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10inttofloatPfPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_24:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r13
testq %r13, %r13
je .LBB3_43
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i68
cmpb $0, 56(%r13)
je .LBB3_27
# %bb.26:
movzbl 67(%r13), %eax
jmp .LBB3_28
.LBB3_27:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit71
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 8(%rsp), %rsi
movl $128, %edx
movq %r12, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $5, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss (%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %r12
testq %r12, %r12
je .LBB3_43
# %bb.29: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i73
cmpb $0, 56(%r12)
je .LBB3_31
# %bb.30:
movzbl 67(%r12), %ecx
jmp .LBB3_32
.LBB3_31:
movq %r12, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_32: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit76
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbp, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_34
# %bb.33:
movq 80(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z10floattointPiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_34:
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB3_43
# %bb.35: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i78
cmpb $0, 56(%r14)
je .LBB3_37
# %bb.36:
movzbl 67(%r14), %eax
jmp .LBB3_38
.LBB3_37:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB3_38: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit81
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq 80(%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $7, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl (%rbx), %esi
movl $_ZSt4cout, %edi
callq _ZNSolsEi
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB3_43
# %bb.39: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i83
cmpb $0, 56(%rbx)
je .LBB3_41
# %bb.40:
movzbl 67(%rbx), %ecx
jmp .LBB3_42
.LBB3_41:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB3_42: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit86
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_43:
.cfi_def_cfa_offset 192
callq _ZSt16__throw_bad_castv
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8mykernelPiPfS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10floattointPiPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10inttofloatPfPi, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8mykernelPiPfS_,@object # @_Z8mykernelPiPfS_
.section .rodata,"a",@progbits
.globl _Z8mykernelPiPfS_
.p2align 3, 0x0
_Z8mykernelPiPfS_:
.quad _Z23__device_stub__mykernelPiPfS_
.size _Z8mykernelPiPfS_, 8
.type _Z10floattointPiPf,@object # @_Z10floattointPiPf
.globl _Z10floattointPiPf
.p2align 3, 0x0
_Z10floattointPiPf:
.quad _Z25__device_stub__floattointPiPf
.size _Z10floattointPiPf, 8
.type _Z10inttofloatPfPi,@object # @_Z10inttofloatPfPi
.globl _Z10inttofloatPfPi
.p2align 3, 0x0
_Z10inttofloatPfPi:
.quad _Z25__device_stub__inttofloatPfPi
.size _Z10inttofloatPfPi, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "this should NOT be 123, should be some weird float value, not even slightly close to 123 :"
.size .L.str, 91
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "f1[0] "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "this SHOULD be 123 :"
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "int2[0] "
.size .L.str.3, 9
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "after copy to device"
.size .L.str.4, 21
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "after kernel call 2"
.size .L.str.5, 20
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "f1[0]"
.size .L.str.6, 6
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "after kernel call 3"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "int2[0]"
.size .L.str.8, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8mykernelPiPfS_"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10floattointPiPf"
.size .L__unnamed_2, 19
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z10inttofloatPfPi"
.size .L__unnamed_3, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__mykernelPiPfS_
.addrsig_sym _Z25__device_stub__floattointPiPf
.addrsig_sym _Z25__device_stub__inttofloatPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8mykernelPiPfS_
.addrsig_sym _Z10floattointPiPf
.addrsig_sym _Z10inttofloatPfPi
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <map>
#include <utility>
#include <algorithm>
#include <cstdlib>
#include <cmath>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime.h>
using namespace std;
bool verbose=false;
int benchmark=1;
#define LRATE 0.01
#define LPARAM 0.02
#define NUM_FACTORS 32
const float lparam=LPARAM;
const float lrate=LRATE;
double get_walltime(){
struct timeval tp;
gettimeofday(&tp, NULL);
return (double)(tp.tv_sec + tp.tv_usec/1000000.0);
}
float norm(std::vector<float> &vec);
float norm2(std::vector<float> &vec);
void file_to_map(std::ifstream &f, char delim, std::map<int,std::vector<std::pair<int,int> > > &map, int numlines);
void print_map( std::map<int,std::vector<std::pair<int,int> > > &map);
int get_max_user(std::map<int,std::vector<std::pair<int,int> > > &map);
int get_max_movie(std::map<int,std::vector<std::pair<int,int> > > &map);
int get_num_ratings(std::map<int,std::vector<std::pair<int,int> > > &map);
float predict_rating(std::vector<float> &userFactors, std::vector<float> &movieFactors);
void sgdFactors(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map);
void sgdFactorsCuda(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map);
//--------------------------------------------------------------------------CUDA
//__global__ void descendGradient(float *ratings, float *p_u, float *q_i);
__global__ void descendGradient(int num_ratings, float *ratings, float *p_u, float *q_i, float *min);
__device__ void dotNUMFACTORS(int user, int movie, float *p_u, float *q_i, float *res);
__device__ void norm2FACTOR(int vec_indx, float *vec, float *res);
template<class T>
void dump_linear(int nl, std::vector<T> &vec);
std::vector<float> getUserVector(int user, std::map<int,std::vector<std::pair<int,int> > > &map);
int main(int argc,char *argv[]){
std::string input_file_name;
char delim=' ';
int numlines=-1;
//argvars
if(argc>1){
int c=1;
while(c<argc){
std::string arg=argv[c];
if(arg=="-i" || arg=="--input-file"){
if(++c<argc){
input_file_name=argv[c++];
continue;
}
}
if(arg=="-n" || arg=="--size"){
if(++c<argc){
numlines=atoi(argv[c++]);
continue;
}
}
if(arg=="-d" || arg=="--delimiter"){
if(++c<argc){
delim=*argv[c++];
continue;
}
}
if(arg=="-v" || arg=="--verbose"){
verbose=true;
c++;
continue;
}
if(arg=="-k" || arg=="--benchmark"){
benchmark=5;
c++;
continue;
}
}
}
std::ifstream in_file(input_file_name.c_str());
std::map<int,std::vector<std::pair<int,int> > > ratings;
file_to_map(in_file, delim, ratings, numlines);
in_file.close();
std::vector<float> factors(NUM_FACTORS,0.1);
int max_user=get_max_user(ratings);
int max_movie=get_max_movie(ratings);
std::cout<<max_user<<std::endl;
std::cout<<max_movie<<std::endl;
std::vector<std::vector<float> > userFactors(max_user+1, factors);
std::vector<std::vector<float> > movieFactors(max_movie+1, factors);
//print_map(ratings);
double runtime_sum=0;
for(int b=0; b<benchmark; ++b){
double timer=get_walltime();
//sgdFactors(userFactors, movieFactors, ratings);
sgdFactorsCuda(userFactors, movieFactors, ratings);
timer=get_walltime()-timer;
runtime_sum+=timer;
}
runtime_sum/=benchmark;
std::cout<<"calculation time averaged over "<<benchmark<< "run(s) is "<<runtime_sum<<" seconds"<<std::endl;
}
//dangerous method with expected input sizes
//todo:fix!
void file_to_map(std::ifstream &f, char delim, std::map<int,std::vector<std::pair<int,int> > > &map, int numlines){
if(verbose){
std::cout<<"reading file..."<<std::endl;
}
std::string line;
if(f.is_open()){
int linenum=0;
std::vector<int> temp;
while(std::getline(f,line) && (numlines>linenum || numlines<0)){
std::stringstream ss(line);
std::string num;
while(std::getline(ss, num, delim)){
temp.push_back(atoi(num.c_str()));
}
map[temp[0]].push_back(std::make_pair(temp[1],temp[2]));
temp.clear();
linenum++;
}
if(verbose){
std::cout<<"loaded in "<<linenum<<" lines of text"<<std::endl;
std::cout<<"last line:"<<std::endl<<line<<std::endl;
}
}else{
if(verbose){
std::cout<<"file could not be opened"<<std::endl;
}
}
}
void print_map( std::map<int,std::vector<std::pair<int,int> > > &map){
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
std::cout<<"user: "<<user->first<<std::endl;
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
std::cout<<"movie"<<rating->first<<", rating: "<<rating->second<<std::endl;
}
}
}
void sgdFactors(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map){
float min, oldmin=0;
do{
oldmin=min;
min=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
min+=err*err;
for(int i=0;i<movieFactors[0].size();++i){
//float mfv=movieFactors[rating->first][i];
movieFactors[rating->first][i]+=lrate*(err*userFactors[user->first][i] -
lparam*movieFactors[rating->first][i]);
userFactors[user->first][i]+=lrate*(err*movieFactors[rating->first][i] -
lparam*userFactors[user->first][i]);
}
float n_movie=norm2(movieFactors[rating->first]);
float n_user=norm2(userFactors[rating->first]);
min+=lparam*(n_movie+n_user);
}
}
std::cout<<"err: "<<min<<std::endl;
}while(oldmin-min>1e-3 || oldmin==0);
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
std::cout<<err<<std::endl;
}
}
}
void sgdFactorsCuda(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map){
float *ratings;
cudaMalloc((void**)&ratings, 3*get_num_ratings(map)*sizeof(float));
int ratings_copied=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator user;
for(user=map.begin();user!=map.end();++user){
std::vector<float> v=getUserVector(user->first,map);
cudaMemcpy(ratings+(ratings_copied*sizeof(float)), &v[0],v.size()*sizeof(float), cudaMemcpyHostToDevice);
ratings_copied+=v.size();
}
int max_user=get_max_user(map);
int max_movie=get_max_movie(map);
float *q_i, *p_u, *min_d;
cudaMalloc((void**)&p_u, max_user*userFactors.size()*sizeof(float));
cudaMalloc((void**)&q_i, max_movie*movieFactors.size()*sizeof(float));
cudaMalloc((void**)&min_d, sizeof(float));
cudaMemcpy(p_u, &userFactors[0], max_user*userFactors.size()*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(q_i, &movieFactors[0], max_movie*movieFactors.size()*sizeof(float), cudaMemcpyHostToDevice);
float *min, oldmin=0;
min=(float*)malloc(1*sizeof(float));
*min=0;
do{
oldmin=*min;
descendGradient<<<128,128>>>(get_num_ratings(map), ratings, p_u, q_i, min_d);
cudaMemcpy(min, min_d, sizeof(float), cudaMemcpyDeviceToHost);
std::cout<<"err: "<<*min<<std::endl;
}while(oldmin-*min>1e-3 || oldmin==0);
cudaMemcpy(&userFactors[0], p_u, userFactors.size()*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(&movieFactors[0], q_i, movieFactors.size()*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(p_u);
cudaFree(q_i);
cudaFree(min_d);
/*
for(user=map.begin(); user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
std::cout<<err<<std::endl;
}
}
*/
}
__global__ void descendGradient(int num_ratings, float *ratings, float *p_u, float *q_i, float *min){
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
min[0]=300.0;
while(tid<num_ratings){
float predicted;
int userid=ratings[(tid*3)];
int movieid=ratings[(tid*3)+1];
int ratingval=ratings[(tid*3)+2];
//dotNUMFACTORS(userid, movieid, p_u, q_i, &predicted);
float err=ratingval-predicted;
*min+=err*err;
for(int i=0; i<NUM_FACTORS; ++i){
q_i[(NUM_FACTORS*movieid)+i]+=LRATE*(err*p_u[(NUM_FACTORS*userid)+i] - LPARAM*q_i[(NUM_FACTORS*movieid)+i]);
p_u[(NUM_FACTORS*userid)+i]+=LRATE*(err*q_i[(NUM_FACTORS*userid)+i] - LPARAM*q_i[(NUM_FACTORS*movieid)+i]);
}
float n2_movie, n2_user;
norm2FACTOR(userid, p_u, &n2_user);
norm2FACTOR(movieid, q_i, &n2_movie);
*min+=lparam*(n2_movie+n2_user);
__syncthreads();
//atomicAdd(d_sum, x[tid]);
min[0]+=(float)ratingval;
}
}
float predict_rating(std::vector<float> &userFactors, std::vector<float> &movieFactors){
float rating=0;
//assumes same factors size for user and movies
for(int i=0; i<userFactors.size();++i){
rating+=userFactors[i]*movieFactors[i];
}
return rating;
}
int get_max_user(std::map<int,std::vector<std::pair<int,int> > > &map){
int max_user=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
if(e->first>max_user){
max_user=e->first;
}
}
return max_user;
}
int get_max_movie(std::map<int,std::vector<std::pair<int,int> > > &map){
int max_movie=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
vector<pair<int, int> >::iterator mr=e->second.begin();
for(mr; mr<e->second.end(); ++mr){
if(mr->first>max_movie){
max_movie=e->first;
}
}
}
return max_movie;
}
int get_num_ratings(std::map<int,std::vector<std::pair<int,int> > > &map){
int num_ratings=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
vector<pair<int, int> >::iterator mr=e->second.begin();
for(mr; mr<e->second.end(); ++mr){
num_ratings++;
}
}
return num_ratings;
}
std::vector<float> getUserVector(int user, std::map<int,std::vector<std::pair<int,int> > > &map){
std::vector<float> usersRatings;
vector<pair<int,int> >::iterator rating=map[user].begin();
for(rating;rating<map[user].end();++rating){
usersRatings.push_back(user);
usersRatings.push_back(rating->first);
usersRatings.push_back(rating->second);
}
return usersRatings;
}
float norm(std::vector<float> &vec){
float sum=0;
for(int i=0; i<vec.size(); ++i){
sum+=vec[i]*vec[i];
}
return std::sqrt(sum);
}
float norm2(std::vector<float> &vec){
float sum=0;
for(int i=0; i<vec.size(); ++i){
sum+=vec[i]*vec[i];
}
return sum;
}
template<class T>
void dump_linear(int nl, std::vector<T> &vec){
int n=0;
for(int i=0;i<vec.size();++i){
++n;
std::cout<<vec[i]<<' ';
if(n>=nl && nl>0){
std::cout<<std::endl;
n=0;
}
}
std::cout<<std::endl;
}
__device__ void dotNUMFACTORS(int user, int movie, float *p_u, float *q_i, float *res){
__shared__ float cache[NUM_FACTORS];
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
int cache_index=threadIdx.x;
user=0;
movie=0;
float temp=0;
while(tid<NUM_FACTORS){
temp+=p_u[(user*NUM_FACTORS)+tid]*q_i[(movie*NUM_FACTORS)+tid];
tid+=blockDim.x*gridDim.x;//should be unnecessary, since block sizes must be multiple of 32, which is the #factors
}
cache[cache_index]=temp;
__syncthreads();
int i=blockDim.x/2;
while(i!=0){
if(cache_index<i){
cache[cache_index]+=cache[cache_index+i];
}
__syncthreads();
i/=2;
}
if(cache_index==0){
*res=cache[0];
}
}
__device__ void norm2FACTOR(int vec_indx, float *vec, float *res){
__shared__ float cache[NUM_FACTORS];
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
int cache_index=threadIdx.x;
float temp=0;
while(tid<NUM_FACTORS){
temp+=vec[(vec_indx*NUM_FACTORS)+tid]*vec[(vec_indx*NUM_FACTORS)+tid];
tid+=blockDim.x*gridDim.x;//should be unnecessary, since block sizes must be multiple of 32, which is the #factors
}
cache[cache_index]=temp;
__syncthreads();
int i=blockDim.x/2;
while(i!=0){
if(cache_index<i){
cache[cache_index]+=cache[cache_index+i];
}
__syncthreads();
i/=2;
}
if(cache_index==0){
*res=cache[0];
}
} | code for sm_80
Function : _Z15descendGradientiPfS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0x180] ; /* 0x0000600000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fe400078e0200 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x43960000 ; /* 0x43960000ff037424 */
/* 0x000fc600078e00ff */
/*0080*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fe40003f06270 */
/*0090*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0001f6000c101906 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R10, R2, 0x3, RZ ; /* 0x00000003020a7824 */
/* 0x000fe200078e02ff */
/*00d0*/ MOV R7, 0x43960000 ; /* 0x4396000000077802 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.SHL.U32 R3, R0, 0x4, RZ ; /* 0x0000000400037824 */
/* 0x001fe200078e00ff */
/*00f0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fc40000000800 */
/*0100*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc80008011604 */
/*0110*/ IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fca00078e020b */
/*0120*/ LDG.E R12, [R10.64] ; /* 0x000000060a0c7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R13, [R10.64+0x4] ; /* 0x000004060a0d7981 */
/* 0x001ee2000c1e1900 */
/*0140*/ IMAD.MOV.U32 R14, RZ, RZ, 0x7fc00000 ; /* 0x7fc00000ff0e7424 */
/* 0x000fc600078e00ff */
/*0150*/ LDG.E R4, [R10.64+0x8] ; /* 0x000008060a047981 */
/* 0x000162000c1e1900 */
/*0160*/ FFMA R15, R14, +QNAN , R7 ; /* 0x7fc000000e0f7823 */
/* 0x000fe20000000007 */
/*0170*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff107624 */
/* 0x000fe200078e00ff */
/*0190*/ MOV R17, c[0x0][0x17c] ; /* 0x00005f0000117a02 */
/* 0x000fe20000000f00 */
/*01a0*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0001e2000c101906 */
/*01c0*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x004e70000020f100 */
/*01d0*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x008ea2000020f100 */
/*01e0*/ IMAD.SHL.U32 R7, R12, 0x20, RZ ; /* 0x000000200c077824 */
/* 0x002fe200078e00ff */
/*01f0*/ SHF.L.U32 R25, R13, 0x5, RZ ; /* 0x000000050d197819 */
/* 0x005fcc00000006ff */
/*0200*/ MOV R15, UR9 ; /* 0x00000009000f7c02 */
/* 0x001fe20008000f00 */
/*0210*/ IMAD.U32 R14, RZ, RZ, UR8 ; /* 0x00000008ff0e7e24 */
/* 0x000fe2000f8e00ff */
/*0220*/ MOV R13, R17 ; /* 0x00000011000d7202 */
/* 0x000fe20000000f00 */
/*0230*/ IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e0010 */
/*0240*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x000fc800078e020e */
/*0250*/ IMAD.WIDE R16, R25, 0x4, R12 ; /* 0x0000000419107825 */
/* 0x000fe200078e020c */
/*0260*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R20, [R16.64] ; /* 0x0000000610147981 */
/* 0x000ee2000c1e1900 */
/*0280*/ FMUL R27, R18, +QNAN ; /* 0x7fc00000121b7820 */
/* 0x004fe20000400000 */
/*0290*/ F2F.F64.F32 R20, R20 ; /* 0x0000001400147310 */
/* 0x008ff00000201800 */
/*02a0*/ F2F.F64.F32 R18, R27 ; /* 0x0000001b00127310 */
/* 0x000e240000201800 */
/*02b0*/ DFMA R18, R20, c[0x2][0x0], R18 ; /* 0x0080000014127a2b */
/* 0x001e0c0000000012 */
/*02c0*/ DFMA R28, R18, c[0x2][0x8], R20 ; /* 0x00800200121c7a2b */
/* 0x001e140000000014 */
/*02d0*/ F2F.F32.F64 R29, R28 ; /* 0x0000001c001d7310 */
/* 0x001e220000301000 */
/*02e0*/ IMAD.WIDE R18, R7, 0x4, R12 ; /* 0x0000000407127825 */
/* 0x000fe200078e020c */
/*02f0*/ STG.E [R16.64], R29 ; /* 0x0000001d10007986 */
/* 0x0011e8000c101906 */
/*0300*/ LDG.E R21, [R18.64] ; /* 0x0000000612157981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R26, [R14.64] ; /* 0x000000060e1a7981 */
/* 0x000ee2000c1e1900 */
/*0320*/ F2F.F64.F32 R22, R29 ; /* 0x0000001d00167310 */
/* 0x000fe20000201800 */
/*0330*/ FMUL R28, R21, +QNAN ; /* 0x7fc00000151c7820 */
/* 0x004fce0000400000 */
/*0340*/ F2F.F64.F32 R20, R28 ; /* 0x0000001c00147310 */
/* 0x000e640000201800 */
/*0350*/ DFMA R22, R22, c[0x2][0x0], R20 ; /* 0x0080000016167a2b */
/* 0x00264c0000000014 */
/*0360*/ F2F.F64.F32 R20, R26 ; /* 0x0000001a00147310 */
/* 0x008e640000201800 */
/*0370*/ DFMA R26, R22, c[0x2][0x8], R20 ; /* 0x00800200161a7a2b */
/* 0x0022a40000000014 */
/*0380*/ LDG.E R20, [R14.64+0x4] ; /* 0x000004060e147981 */
/* 0x002ef0000c1e1900 */
/*0390*/ F2F.F32.F64 R27, R26 ; /* 0x0000001a001b7310 */
/* 0x004e640000301000 */
/*03a0*/ STG.E [R14.64], R27 ; /* 0x0000001b0e007986 */
/* 0x0023e8000c101906 */
/*03b0*/ LDG.E R22, [R16.64+0x4] ; /* 0x0000040610167981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ FMUL R20, R20, +QNAN ; /* 0x7fc0000014147820 */
/* 0x008fcc0000400000 */
/*03d0*/ F2F.F64.F32 R20, R20 ; /* 0x0000001400147310 */
/* 0x000ff00000201800 */
/*03e0*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x004ea40000201800 */
/*03f0*/ DFMA R20, R22, c[0x2][0x0], R20 ; /* 0x0080000016147a2b */
/* 0x004e0c0000000014 */
/*0400*/ DFMA R28, R20, c[0x2][0x8], R22 ; /* 0x00800200141c7a2b */
/* 0x001e140000000016 */
/*0410*/ F2F.F32.F64 R29, R28 ; /* 0x0000001c001d7310 */
/* 0x001e240000301000 */
/*0420*/ STG.E [R16.64+0x4], R29 ; /* 0x0000041d10007986 */
/* 0x0011e8000c101906 */
/*0430*/ LDG.E R21, [R18.64+0x4] ; /* 0x0000040612157981 */
/* 0x000e68000c1e1900 */
/*0440*/ LDG.E R26, [R14.64+0x4] ; /* 0x000004060e1a7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ F2F.F64.F32 R22, R29 ; /* 0x0000001d00167310 */
/* 0x000fe20000201800 */
/*0460*/ FMUL R27, R21, +QNAN ; /* 0x7fc00000151b7820 */
/* 0x002fce0000400000 */
/*0470*/ F2F.F64.F32 R20, R27 ; /* 0x0000001b00147310 */
/* 0x000e640000201800 */
/*0480*/ DFMA R22, R22, c[0x2][0x0], R20 ; /* 0x0080000016167a2b */
/* 0x00244c0000000014 */
/*0490*/ F2F.F64.F32 R20, R26 ; /* 0x0000001a00147310 */
/* 0x004e640000201800 */
/*04a0*/ DFMA R26, R22, c[0x2][0x8], R20 ; /* 0x00800200161a7a2b */
/* 0x0022a40000000014 */
/*04b0*/ LDG.E R20, [R14.64+0x8] ; /* 0x000008060e147981 */
/* 0x002ef0000c1e1900 */
/*04c0*/ F2F.F32.F64 R27, R26 ; /* 0x0000001a001b7310 */
/* 0x004e640000301000 */
/*04d0*/ STG.E [R14.64+0x4], R27 ; /* 0x0000041b0e007986 */
/* 0x0023e8000c101906 */
/*04e0*/ LDG.E R22, [R16.64+0x8] ; /* 0x0000080610167981 */
/* 0x000ea2000c1e1900 */
/*04f0*/ FMUL R28, R20, +QNAN ; /* 0x7fc00000141c7820 */
/* 0x008fc80000400000 */
/*0500*/ F2F.F64.F32 R20, R28 ; /* 0x0000001c00147310 */
/* 0x000ff00000201800 */
/*0510*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x004ea40000201800 */
/*0520*/ DFMA R20, R22, c[0x2][0x0], R20 ; /* 0x0080000016147a2b */
/* 0x004e0c0000000014 */
/*0530*/ DFMA R28, R20, c[0x2][0x8], R22 ; /* 0x00800200141c7a2b */
/* 0x001e140000000016 */
/*0540*/ F2F.F32.F64 R29, R28 ; /* 0x0000001c001d7310 */
/* 0x001e240000301000 */
/*0550*/ STG.E [R16.64+0x8], R29 ; /* 0x0000081d10007986 */
/* 0x0011e8000c101906 */
/*0560*/ LDG.E R20, [R18.64+0x8] ; /* 0x0000080612147981 */
/* 0x000e68000c1e1900 */
/*0570*/ LDG.E R26, [R14.64+0x8] ; /* 0x000008060e1a7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ F2F.F64.F32 R22, R29 ; /* 0x0000001d00167310 */
/* 0x000fe20000201800 */
/*0590*/ FMUL R27, R20, +QNAN ; /* 0x7fc00000141b7820 */
/* 0x002fce0000400000 */
/*05a0*/ F2F.F64.F32 R20, R27 ; /* 0x0000001b00147310 */
/* 0x000e640000201800 */
/*05b0*/ DFMA R22, R22, c[0x2][0x0], R20 ; /* 0x0080000016167a2b */
/* 0x00244c0000000014 */
/*05c0*/ F2F.F64.F32 R20, R26 ; /* 0x0000001a00147310 */
/* 0x004e640000201800 */
/*05d0*/ DFMA R26, R22, c[0x2][0x8], R20 ; /* 0x00800200161a7a2b */
/* 0x0022a40000000014 */
/*05e0*/ LDG.E R20, [R14.64+0xc] ; /* 0x00000c060e147981 */
/* 0x002ef0000c1e1900 */
/*05f0*/ F2F.F32.F64 R27, R26 ; /* 0x0000001a001b7310 */
/* 0x004e640000301000 */
/*0600*/ STG.E [R14.64+0x8], R27 ; /* 0x0000081b0e007986 */
/* 0x002fe8000c101906 */
/*0610*/ LDG.E R21, [R16.64+0xc] ; /* 0x00000c0610157981 */
/* 0x000ea2000c1e1900 */
/*0620*/ FMUL R20, R20, +QNAN ; /* 0x7fc0000014147820 */
/* 0x008fc80000400000 */
/*0630*/ F2F.F64.F32 R22, R20 ; /* 0x0000001400167310 */
/* 0x000ff00000201800 */
/*0640*/ F2F.F64.F32 R20, R21 ; /* 0x0000001500147310 */
/* 0x004e640000201800 */
/*0650*/ DFMA R22, R20, c[0x2][0x0], R22 ; /* 0x0080000014167a2b */
/* 0x002e0c0000000016 */
/*0660*/ DFMA R28, R22, c[0x2][0x8], R20 ; /* 0x00800200161c7a2b */
/* 0x001e140000000014 */
/*0670*/ F2F.F32.F64 R29, R28 ; /* 0x0000001c001d7310 */
/* 0x001e240000301000 */
/*0680*/ STG.E [R16.64+0xc], R29 ; /* 0x00000c1d10007986 */
/* 0x0011e8000c101906 */
/*0690*/ LDG.E R18, [R18.64+0xc] ; /* 0x00000c0612127981 */
/* 0x0002a8000c1e1900 */
/*06a0*/ LDG.E R19, [R14.64+0xc] ; /* 0x00000c060e137981 */
/* 0x002ee2000c1e1900 */
/*06b0*/ F2F.F64.F32 R22, R29 ; /* 0x0000001d00167310 */
/* 0x000fe20000201800 */
/*06c0*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ ISETP.NE.AND P0, PT, R24, 0x20, PT ; /* 0x000000201800780c */
/* 0x000fe20003f05270 */
/*06e0*/ UIADD3 UR8, UP0, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe2000ff1e03f */
/*06f0*/ IADD3 R16, P1, R12, 0x10, RZ ; /* 0x000000100c107810 */
/* 0x001fc60007f3e0ff */
/*0700*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe400087fe43f */
/*0710*/ IMAD.X R17, RZ, RZ, R13, P1 ; /* 0x000000ffff117224 */
/* 0x000fe400008e060d */
/*0720*/ FMUL R26, R18, +QNAN ; /* 0x7fc00000121a7820 */
/* 0x004fcc0000400000 */
/*0730*/ F2F.F64.F32 R26, R26 ; /* 0x0000001a001a7310 */
/* 0x000e300000201800 */
/*0740*/ F2F.F64.F32 R20, R19 ; /* 0x0000001300147310 */
/* 0x008e620000201800 */
/*0750*/ DFMA R22, R22, c[0x2][0x0], R26 ; /* 0x0080000016167a2b */
/* 0x001e4c000000001a */
/*0760*/ DFMA R20, R22, c[0x2][0x8], R20 ; /* 0x0080020016147a2b */
/* 0x002e140000000014 */
/*0770*/ F2F.F32.F64 R21, R20 ; /* 0x0000001400157310 */
/* 0x001e240000301000 */
/*0780*/ STG.E [R14.64+0xc], R21 ; /* 0x00000c150e007986 */
/* 0x0011e2000c101906 */
/*0790*/ @P0 BRA 0x200 ; /* 0xfffffa6000000947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R2, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x000fe20003f24270 */
/*07b0*/ BSSY B0, 0x8b0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*07c0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf05270 */
/*07d0*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x001fd20000000f00 */
/*07e0*/ @P1 BRA 0x8a0 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0800*/ MOV R14, R2 ; /* 0x00000002000e7202 */
/* 0x000fc80000000f00 */
/*0810*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0820*/ IMAD.IADD R12, R7, 0x1, R14 ; /* 0x00000001070c7824 */
/* 0x000fd200078e020e */
/*0830*/ IMAD.WIDE R12, R12, R13, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fcc00078e020d */
/*0840*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea2000c1e1900 */
/*0850*/ MOV R17, c[0x0][0x0] ; /* 0x0000000000117a02 */
/* 0x000fca0000000f00 */
/*0860*/ IMAD R14, R17, c[0x0][0xc], R14 ; /* 0x00000300110e7a24 */
/* 0x000fca00078e020e */
/*0870*/ ISETP.GE.AND P2, PT, R14, 0x20, PT ; /* 0x000000200e00780c */
/* 0x000fe20003f46270 */
/*0880*/ FFMA R15, R12, R12, R15 ; /* 0x0000000c0c0f7223 */
/* 0x004fd8000000000f */
/*0890*/ @!P2 BRA 0x810 ; /* 0xffffff700000a947 */
/* 0x000fea000383ffff */
/*08a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08b0*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */
/* 0x0001e80000004800 */
/*08c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08d0*/ @!P0 BRA 0x9b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08e0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x001fca000f8e00ff */
/*08f0*/ ISETP.GE.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f46270 */
/*0900*/ IADD3 R14, R7, 0x1, RZ ; /* 0x00000001070e7810 */
/* 0x000fd60007ffe0ff */
/*0910*/ @!P2 LEA R12, R7.reuse, R3, 0x2 ; /* 0x00000003070ca211 */
/* 0x040fe200078e10ff */
/*0920*/ @!P2 LDS R13, [R0.X4] ; /* 0x00000000000da984 */
/* 0x000fe20000004800 */
/*0930*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fc800078f08ff */
/*0940*/ @!P2 LDS R12, [R12] ; /* 0x000000000c0ca984 */
/* 0x000e220000000800 */
/*0950*/ SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fe20000011407 */
/*0960*/ @!P2 FADD R13, R13, R12 ; /* 0x0000000c0d0da221 */
/* 0x001fca0000000000 */
/*0970*/ @!P2 STS [R0.X4], R13 ; /* 0x0000000d0000a388 */
/* 0x0001e80000004800 */
/*0980*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0990*/ ISETP.GT.U32.AND P2, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fda0003f44070 */
/*09a0*/ @P2 BRA 0x8f0 ; /* 0xffffff4000002947 */
/* 0x001fea000383ffff */
/*09b0*/ LDS R14, [RZ] ; /* 0x00000000ff0e7984 */
/* 0x001e220000000800 */
/*09c0*/ BSSY B0, 0xab0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*09d0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*09e0*/ @P1 BRA 0xaa0 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*09f0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0a00*/ MOV R16, R2 ; /* 0x0000000200107202 */
/* 0x000fc80000000f00 */
/*0a10*/ IADD3 R12, R25, R16, RZ ; /* 0x00000010190c7210 */
/* 0x000fe20007ffe0ff */
/*0a20*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0a30*/ IMAD.WIDE R12, R12, R13, c[0x0][0x178] ; /* 0x00005e000c0c7625 */
/* 0x000fcc00078e020d */
/*0a40*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea2000c1e1900 */
/*0a50*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fca0000000f00 */
/*0a60*/ IMAD R16, R15, c[0x0][0xc], R16 ; /* 0x000003000f107a24 */
/* 0x000fca00078e0210 */
/*0a70*/ ISETP.GE.AND P1, PT, R16, 0x20, PT ; /* 0x000000201000780c */
/* 0x000fe20003f26270 */
/*0a80*/ FFMA R7, R12, R12, R7 ; /* 0x0000000c0c077223 */
/* 0x004fd80000000007 */
/*0a90*/ @!P1 BRA 0xa10 ; /* 0xffffff7000009947 */
/* 0x000fea000383ffff */
/*0aa0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ab0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0003e80000004800 */
/*0ac0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0ad0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f25270 */
/*0ae0*/ FSEL R5, R14, R5, !P1 ; /* 0x000000050e057208 */
/* 0x001fe20004800000 */
/*0af0*/ @!P0 BRA 0xbd0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b00*/ MOV R7, UR4 ; /* 0x0000000400077c02 */
/* 0x002fc80008000f00 */
/*0b10*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f06270 */
/*0b20*/ IADD3 R14, R7, 0x1, RZ ; /* 0x00000001070e7810 */
/* 0x000fd60007ffe0ff */
/*0b30*/ @!P0 IMAD R12, R7.reuse, 0x4, R3 ; /* 0x00000004070c8824 */
/* 0x040fe200078e0203 */
/*0b40*/ @!P0 LDS R13, [R0.X4] ; /* 0x00000000000d8984 */
/* 0x000fe20000004800 */
/*0b50*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fc800078f08ff */
/*0b60*/ @!P0 LDS R12, [R12] ; /* 0x000000000c0c8984 */
/* 0x000e220000000800 */
/*0b70*/ SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fe20000011407 */
/*0b80*/ @!P0 FADD R13, R13, R12 ; /* 0x0000000c0d0d8221 */
/* 0x001fca0000000000 */
/*0b90*/ @!P0 STS [R0.X4], R13 ; /* 0x0000000d00008388 */
/* 0x0001e80000004800 */
/*0ba0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0bb0*/ ISETP.GT.U32.AND P0, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fda0003f04070 */
/*0bc0*/ @P0 BRA 0xb10 ; /* 0xffffff4000000947 */
/* 0x001fea000383ffff */
/*0bd0*/ LDG.E R7, [R8.64] ; /* 0x0000000608077981 */
/* 0x002ea8000c1e1900 */
/*0be0*/ LDS R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x000e240000000800 */
/*0bf0*/ @P1 MOV R12, R6 ; /* 0x00000006000c1202 */
/* 0x001fca0000000f00 */
/*0c00*/ FADD R6, R12, R5 ; /* 0x000000050c067221 */
/* 0x000fc80000000000 */
/*0c10*/ FFMA R13, R6, 0.019999999552965164185, R7 ; /* 0x3ca3d70a060d7823 */
/* 0x004fca0000000007 */
/*0c20*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001e8000c101906 */
/*0c30*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c40*/ LDG.E R7, [R8.64] ; /* 0x0000000608077981 */
/* 0x000ea2000c1e1900 */
/*0c50*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x020e70000020f100 */
/*0c60*/ I2F R6, R4 ; /* 0x0000000400067306 */
/* 0x002ea40000201400 */
/*0c70*/ FADD R7, R7, R6 ; /* 0x0000000607077221 */
/* 0x004fe20000000000 */
/*0c80*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x000fc80000000f00 */
/*0c90*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0001e2000c101906 */
/*0ca0*/ BRA 0x120 ; /* 0xfffff47000007947 */
/* 0x000fea000383ffff */
/*0cb0*/ BRA 0xcb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <map>
#include <utility>
#include <algorithm>
#include <cstdlib>
#include <cmath>
#include <sys/time.h>
#include <cuda.h>
#include <cuda_runtime.h>
using namespace std;
bool verbose=false;
int benchmark=1;
#define LRATE 0.01
#define LPARAM 0.02
#define NUM_FACTORS 32
const float lparam=LPARAM;
const float lrate=LRATE;
double get_walltime(){
struct timeval tp;
gettimeofday(&tp, NULL);
return (double)(tp.tv_sec + tp.tv_usec/1000000.0);
}
float norm(std::vector<float> &vec);
float norm2(std::vector<float> &vec);
void file_to_map(std::ifstream &f, char delim, std::map<int,std::vector<std::pair<int,int> > > &map, int numlines);
void print_map( std::map<int,std::vector<std::pair<int,int> > > &map);
int get_max_user(std::map<int,std::vector<std::pair<int,int> > > &map);
int get_max_movie(std::map<int,std::vector<std::pair<int,int> > > &map);
int get_num_ratings(std::map<int,std::vector<std::pair<int,int> > > &map);
float predict_rating(std::vector<float> &userFactors, std::vector<float> &movieFactors);
void sgdFactors(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map);
void sgdFactorsCuda(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map);
//--------------------------------------------------------------------------CUDA
//__global__ void descendGradient(float *ratings, float *p_u, float *q_i);
__global__ void descendGradient(int num_ratings, float *ratings, float *p_u, float *q_i, float *min);
__device__ void dotNUMFACTORS(int user, int movie, float *p_u, float *q_i, float *res);
__device__ void norm2FACTOR(int vec_indx, float *vec, float *res);
template<class T>
void dump_linear(int nl, std::vector<T> &vec);
std::vector<float> getUserVector(int user, std::map<int,std::vector<std::pair<int,int> > > &map);
int main(int argc,char *argv[]){
std::string input_file_name;
char delim=' ';
int numlines=-1;
//argvars
if(argc>1){
int c=1;
while(c<argc){
std::string arg=argv[c];
if(arg=="-i" || arg=="--input-file"){
if(++c<argc){
input_file_name=argv[c++];
continue;
}
}
if(arg=="-n" || arg=="--size"){
if(++c<argc){
numlines=atoi(argv[c++]);
continue;
}
}
if(arg=="-d" || arg=="--delimiter"){
if(++c<argc){
delim=*argv[c++];
continue;
}
}
if(arg=="-v" || arg=="--verbose"){
verbose=true;
c++;
continue;
}
if(arg=="-k" || arg=="--benchmark"){
benchmark=5;
c++;
continue;
}
}
}
std::ifstream in_file(input_file_name.c_str());
std::map<int,std::vector<std::pair<int,int> > > ratings;
file_to_map(in_file, delim, ratings, numlines);
in_file.close();
std::vector<float> factors(NUM_FACTORS,0.1);
int max_user=get_max_user(ratings);
int max_movie=get_max_movie(ratings);
std::cout<<max_user<<std::endl;
std::cout<<max_movie<<std::endl;
std::vector<std::vector<float> > userFactors(max_user+1, factors);
std::vector<std::vector<float> > movieFactors(max_movie+1, factors);
//print_map(ratings);
double runtime_sum=0;
for(int b=0; b<benchmark; ++b){
double timer=get_walltime();
//sgdFactors(userFactors, movieFactors, ratings);
sgdFactorsCuda(userFactors, movieFactors, ratings);
timer=get_walltime()-timer;
runtime_sum+=timer;
}
runtime_sum/=benchmark;
std::cout<<"calculation time averaged over "<<benchmark<< "run(s) is "<<runtime_sum<<" seconds"<<std::endl;
}
//dangerous method with expected input sizes
//todo:fix!
void file_to_map(std::ifstream &f, char delim, std::map<int,std::vector<std::pair<int,int> > > &map, int numlines){
if(verbose){
std::cout<<"reading file..."<<std::endl;
}
std::string line;
if(f.is_open()){
int linenum=0;
std::vector<int> temp;
while(std::getline(f,line) && (numlines>linenum || numlines<0)){
std::stringstream ss(line);
std::string num;
while(std::getline(ss, num, delim)){
temp.push_back(atoi(num.c_str()));
}
map[temp[0]].push_back(std::make_pair(temp[1],temp[2]));
temp.clear();
linenum++;
}
if(verbose){
std::cout<<"loaded in "<<linenum<<" lines of text"<<std::endl;
std::cout<<"last line:"<<std::endl<<line<<std::endl;
}
}else{
if(verbose){
std::cout<<"file could not be opened"<<std::endl;
}
}
}
void print_map( std::map<int,std::vector<std::pair<int,int> > > &map){
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
std::cout<<"user: "<<user->first<<std::endl;
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
std::cout<<"movie"<<rating->first<<", rating: "<<rating->second<<std::endl;
}
}
}
void sgdFactors(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map){
float min, oldmin=0;
do{
oldmin=min;
min=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
min+=err*err;
for(int i=0;i<movieFactors[0].size();++i){
//float mfv=movieFactors[rating->first][i];
movieFactors[rating->first][i]+=lrate*(err*userFactors[user->first][i] -
lparam*movieFactors[rating->first][i]);
userFactors[user->first][i]+=lrate*(err*movieFactors[rating->first][i] -
lparam*userFactors[user->first][i]);
}
float n_movie=norm2(movieFactors[rating->first]);
float n_user=norm2(userFactors[rating->first]);
min+=lparam*(n_movie+n_user);
}
}
std::cout<<"err: "<<min<<std::endl;
}while(oldmin-min>1e-3 || oldmin==0);
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
std::cout<<err<<std::endl;
}
}
}
void sgdFactorsCuda(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map){
float *ratings;
cudaMalloc((void**)&ratings, 3*get_num_ratings(map)*sizeof(float));
int ratings_copied=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator user;
for(user=map.begin();user!=map.end();++user){
std::vector<float> v=getUserVector(user->first,map);
cudaMemcpy(ratings+(ratings_copied*sizeof(float)), &v[0],v.size()*sizeof(float), cudaMemcpyHostToDevice);
ratings_copied+=v.size();
}
int max_user=get_max_user(map);
int max_movie=get_max_movie(map);
float *q_i, *p_u, *min_d;
cudaMalloc((void**)&p_u, max_user*userFactors.size()*sizeof(float));
cudaMalloc((void**)&q_i, max_movie*movieFactors.size()*sizeof(float));
cudaMalloc((void**)&min_d, sizeof(float));
cudaMemcpy(p_u, &userFactors[0], max_user*userFactors.size()*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(q_i, &movieFactors[0], max_movie*movieFactors.size()*sizeof(float), cudaMemcpyHostToDevice);
float *min, oldmin=0;
min=(float*)malloc(1*sizeof(float));
*min=0;
do{
oldmin=*min;
descendGradient<<<128,128>>>(get_num_ratings(map), ratings, p_u, q_i, min_d);
cudaMemcpy(min, min_d, sizeof(float), cudaMemcpyDeviceToHost);
std::cout<<"err: "<<*min<<std::endl;
}while(oldmin-*min>1e-3 || oldmin==0);
cudaMemcpy(&userFactors[0], p_u, userFactors.size()*sizeof(float), cudaMemcpyDeviceToHost);
cudaMemcpy(&movieFactors[0], q_i, movieFactors.size()*sizeof(float), cudaMemcpyDeviceToHost);
cudaFree(p_u);
cudaFree(q_i);
cudaFree(min_d);
/*
for(user=map.begin(); user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
std::cout<<err<<std::endl;
}
}
*/
}
__global__ void descendGradient(int num_ratings, float *ratings, float *p_u, float *q_i, float *min){
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
min[0]=300.0;
while(tid<num_ratings){
float predicted;
int userid=ratings[(tid*3)];
int movieid=ratings[(tid*3)+1];
int ratingval=ratings[(tid*3)+2];
//dotNUMFACTORS(userid, movieid, p_u, q_i, &predicted);
float err=ratingval-predicted;
*min+=err*err;
for(int i=0; i<NUM_FACTORS; ++i){
q_i[(NUM_FACTORS*movieid)+i]+=LRATE*(err*p_u[(NUM_FACTORS*userid)+i] - LPARAM*q_i[(NUM_FACTORS*movieid)+i]);
p_u[(NUM_FACTORS*userid)+i]+=LRATE*(err*q_i[(NUM_FACTORS*userid)+i] - LPARAM*q_i[(NUM_FACTORS*movieid)+i]);
}
float n2_movie, n2_user;
norm2FACTOR(userid, p_u, &n2_user);
norm2FACTOR(movieid, q_i, &n2_movie);
*min+=lparam*(n2_movie+n2_user);
__syncthreads();
//atomicAdd(d_sum, x[tid]);
min[0]+=(float)ratingval;
}
}
float predict_rating(std::vector<float> &userFactors, std::vector<float> &movieFactors){
float rating=0;
//assumes same factors size for user and movies
for(int i=0; i<userFactors.size();++i){
rating+=userFactors[i]*movieFactors[i];
}
return rating;
}
int get_max_user(std::map<int,std::vector<std::pair<int,int> > > &map){
int max_user=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
if(e->first>max_user){
max_user=e->first;
}
}
return max_user;
}
int get_max_movie(std::map<int,std::vector<std::pair<int,int> > > &map){
int max_movie=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
vector<pair<int, int> >::iterator mr=e->second.begin();
for(mr; mr<e->second.end(); ++mr){
if(mr->first>max_movie){
max_movie=e->first;
}
}
}
return max_movie;
}
int get_num_ratings(std::map<int,std::vector<std::pair<int,int> > > &map){
int num_ratings=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
vector<pair<int, int> >::iterator mr=e->second.begin();
for(mr; mr<e->second.end(); ++mr){
num_ratings++;
}
}
return num_ratings;
}
std::vector<float> getUserVector(int user, std::map<int,std::vector<std::pair<int,int> > > &map){
std::vector<float> usersRatings;
vector<pair<int,int> >::iterator rating=map[user].begin();
for(rating;rating<map[user].end();++rating){
usersRatings.push_back(user);
usersRatings.push_back(rating->first);
usersRatings.push_back(rating->second);
}
return usersRatings;
}
float norm(std::vector<float> &vec){
float sum=0;
for(int i=0; i<vec.size(); ++i){
sum+=vec[i]*vec[i];
}
return std::sqrt(sum);
}
float norm2(std::vector<float> &vec){
float sum=0;
for(int i=0; i<vec.size(); ++i){
sum+=vec[i]*vec[i];
}
return sum;
}
template<class T>
void dump_linear(int nl, std::vector<T> &vec){
int n=0;
for(int i=0;i<vec.size();++i){
++n;
std::cout<<vec[i]<<' ';
if(n>=nl && nl>0){
std::cout<<std::endl;
n=0;
}
}
std::cout<<std::endl;
}
__device__ void dotNUMFACTORS(int user, int movie, float *p_u, float *q_i, float *res){
__shared__ float cache[NUM_FACTORS];
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
int cache_index=threadIdx.x;
user=0;
movie=0;
float temp=0;
while(tid<NUM_FACTORS){
temp+=p_u[(user*NUM_FACTORS)+tid]*q_i[(movie*NUM_FACTORS)+tid];
tid+=blockDim.x*gridDim.x;//should be unnecessary, since block sizes must be multiple of 32, which is the #factors
}
cache[cache_index]=temp;
__syncthreads();
int i=blockDim.x/2;
while(i!=0){
if(cache_index<i){
cache[cache_index]+=cache[cache_index+i];
}
__syncthreads();
i/=2;
}
if(cache_index==0){
*res=cache[0];
}
}
__device__ void norm2FACTOR(int vec_indx, float *vec, float *res){
__shared__ float cache[NUM_FACTORS];
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
int cache_index=threadIdx.x;
float temp=0;
while(tid<NUM_FACTORS){
temp+=vec[(vec_indx*NUM_FACTORS)+tid]*vec[(vec_indx*NUM_FACTORS)+tid];
tid+=blockDim.x*gridDim.x;//should be unnecessary, since block sizes must be multiple of 32, which is the #factors
}
cache[cache_index]=temp;
__syncthreads();
int i=blockDim.x/2;
while(i!=0){
if(cache_index<i){
cache[cache_index]+=cache[cache_index+i];
}
__syncthreads();
i/=2;
}
if(cache_index==0){
*res=cache[0];
}
} | #include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <map>
#include <utility>
#include <algorithm>
#include <cstdlib>
#include <cmath>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using namespace std;
bool verbose=false;
int benchmark=1;
#define LRATE 0.01
#define LPARAM 0.02
#define NUM_FACTORS 32
const float lparam=LPARAM;
const float lrate=LRATE;
double get_walltime(){
struct timeval tp;
gettimeofday(&tp, NULL);
return (double)(tp.tv_sec + tp.tv_usec/1000000.0);
}
float norm(std::vector<float> &vec);
float norm2(std::vector<float> &vec);
void file_to_map(std::ifstream &f, char delim, std::map<int,std::vector<std::pair<int,int> > > &map, int numlines);
void print_map( std::map<int,std::vector<std::pair<int,int> > > &map);
int get_max_user(std::map<int,std::vector<std::pair<int,int> > > &map);
int get_max_movie(std::map<int,std::vector<std::pair<int,int> > > &map);
int get_num_ratings(std::map<int,std::vector<std::pair<int,int> > > &map);
float predict_rating(std::vector<float> &userFactors, std::vector<float> &movieFactors);
void sgdFactors(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map);
void sgdFactorsCuda(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map);
//--------------------------------------------------------------------------CUDA
//__global__ void descendGradient(float *ratings, float *p_u, float *q_i);
__global__ void descendGradient(int num_ratings, float *ratings, float *p_u, float *q_i, float *min);
__device__ void dotNUMFACTORS(int user, int movie, float *p_u, float *q_i, float *res);
__device__ void norm2FACTOR(int vec_indx, float *vec, float *res);
template<class T>
void dump_linear(int nl, std::vector<T> &vec);
std::vector<float> getUserVector(int user, std::map<int,std::vector<std::pair<int,int> > > &map);
int main(int argc,char *argv[]){
std::string input_file_name;
char delim=' ';
int numlines=-1;
//argvars
if(argc>1){
int c=1;
while(c<argc){
std::string arg=argv[c];
if(arg=="-i" || arg=="--input-file"){
if(++c<argc){
input_file_name=argv[c++];
continue;
}
}
if(arg=="-n" || arg=="--size"){
if(++c<argc){
numlines=atoi(argv[c++]);
continue;
}
}
if(arg=="-d" || arg=="--delimiter"){
if(++c<argc){
delim=*argv[c++];
continue;
}
}
if(arg=="-v" || arg=="--verbose"){
verbose=true;
c++;
continue;
}
if(arg=="-k" || arg=="--benchmark"){
benchmark=5;
c++;
continue;
}
}
}
std::ifstream in_file(input_file_name.c_str());
std::map<int,std::vector<std::pair<int,int> > > ratings;
file_to_map(in_file, delim, ratings, numlines);
in_file.close();
std::vector<float> factors(NUM_FACTORS,0.1);
int max_user=get_max_user(ratings);
int max_movie=get_max_movie(ratings);
std::cout<<max_user<<std::endl;
std::cout<<max_movie<<std::endl;
std::vector<std::vector<float> > userFactors(max_user+1, factors);
std::vector<std::vector<float> > movieFactors(max_movie+1, factors);
//print_map(ratings);
double runtime_sum=0;
for(int b=0; b<benchmark; ++b){
double timer=get_walltime();
//sgdFactors(userFactors, movieFactors, ratings);
sgdFactorsCuda(userFactors, movieFactors, ratings);
timer=get_walltime()-timer;
runtime_sum+=timer;
}
runtime_sum/=benchmark;
std::cout<<"calculation time averaged over "<<benchmark<< "run(s) is "<<runtime_sum<<" seconds"<<std::endl;
}
//dangerous method with expected input sizes
//todo:fix!
void file_to_map(std::ifstream &f, char delim, std::map<int,std::vector<std::pair<int,int> > > &map, int numlines){
if(verbose){
std::cout<<"reading file..."<<std::endl;
}
std::string line;
if(f.is_open()){
int linenum=0;
std::vector<int> temp;
while(std::getline(f,line) && (numlines>linenum || numlines<0)){
std::stringstream ss(line);
std::string num;
while(std::getline(ss, num, delim)){
temp.push_back(atoi(num.c_str()));
}
map[temp[0]].push_back(std::make_pair(temp[1],temp[2]));
temp.clear();
linenum++;
}
if(verbose){
std::cout<<"loaded in "<<linenum<<" lines of text"<<std::endl;
std::cout<<"last line:"<<std::endl<<line<<std::endl;
}
}else{
if(verbose){
std::cout<<"file could not be opened"<<std::endl;
}
}
}
void print_map( std::map<int,std::vector<std::pair<int,int> > > &map){
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
std::cout<<"user: "<<user->first<<std::endl;
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
std::cout<<"movie"<<rating->first<<", rating: "<<rating->second<<std::endl;
}
}
}
void sgdFactors(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map){
float min, oldmin=0;
do{
oldmin=min;
min=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
min+=err*err;
for(int i=0;i<movieFactors[0].size();++i){
//float mfv=movieFactors[rating->first][i];
movieFactors[rating->first][i]+=lrate*(err*userFactors[user->first][i] -
lparam*movieFactors[rating->first][i]);
userFactors[user->first][i]+=lrate*(err*movieFactors[rating->first][i] -
lparam*userFactors[user->first][i]);
}
float n_movie=norm2(movieFactors[rating->first]);
float n_user=norm2(userFactors[rating->first]);
min+=lparam*(n_movie+n_user);
}
}
std::cout<<"err: "<<min<<std::endl;
}while(oldmin-min>1e-3 || oldmin==0);
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
std::cout<<err<<std::endl;
}
}
}
void sgdFactorsCuda(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map){
float *ratings;
hipMalloc((void**)&ratings, 3*get_num_ratings(map)*sizeof(float));
int ratings_copied=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator user;
for(user=map.begin();user!=map.end();++user){
std::vector<float> v=getUserVector(user->first,map);
hipMemcpy(ratings+(ratings_copied*sizeof(float)), &v[0],v.size()*sizeof(float), hipMemcpyHostToDevice);
ratings_copied+=v.size();
}
int max_user=get_max_user(map);
int max_movie=get_max_movie(map);
float *q_i, *p_u, *min_d;
hipMalloc((void**)&p_u, max_user*userFactors.size()*sizeof(float));
hipMalloc((void**)&q_i, max_movie*movieFactors.size()*sizeof(float));
hipMalloc((void**)&min_d, sizeof(float));
hipMemcpy(p_u, &userFactors[0], max_user*userFactors.size()*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(q_i, &movieFactors[0], max_movie*movieFactors.size()*sizeof(float), hipMemcpyHostToDevice);
float *min, oldmin=0;
min=(float*)malloc(1*sizeof(float));
*min=0;
do{
oldmin=*min;
descendGradient<<<128,128>>>(get_num_ratings(map), ratings, p_u, q_i, min_d);
hipMemcpy(min, min_d, sizeof(float), hipMemcpyDeviceToHost);
std::cout<<"err: "<<*min<<std::endl;
}while(oldmin-*min>1e-3 || oldmin==0);
hipMemcpy(&userFactors[0], p_u, userFactors.size()*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(&movieFactors[0], q_i, movieFactors.size()*sizeof(float), hipMemcpyDeviceToHost);
hipFree(p_u);
hipFree(q_i);
hipFree(min_d);
/*
for(user=map.begin(); user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
std::cout<<err<<std::endl;
}
}
*/
}
__global__ void descendGradient(int num_ratings, float *ratings, float *p_u, float *q_i, float *min){
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
min[0]=300.0;
while(tid<num_ratings){
float predicted;
int userid=ratings[(tid*3)];
int movieid=ratings[(tid*3)+1];
int ratingval=ratings[(tid*3)+2];
//dotNUMFACTORS(userid, movieid, p_u, q_i, &predicted);
float err=ratingval-predicted;
*min+=err*err;
for(int i=0; i<NUM_FACTORS; ++i){
q_i[(NUM_FACTORS*movieid)+i]+=LRATE*(err*p_u[(NUM_FACTORS*userid)+i] - LPARAM*q_i[(NUM_FACTORS*movieid)+i]);
p_u[(NUM_FACTORS*userid)+i]+=LRATE*(err*q_i[(NUM_FACTORS*userid)+i] - LPARAM*q_i[(NUM_FACTORS*movieid)+i]);
}
float n2_movie, n2_user;
norm2FACTOR(userid, p_u, &n2_user);
norm2FACTOR(movieid, q_i, &n2_movie);
*min+=lparam*(n2_movie+n2_user);
__syncthreads();
//atomicAdd(d_sum, x[tid]);
min[0]+=(float)ratingval;
}
}
float predict_rating(std::vector<float> &userFactors, std::vector<float> &movieFactors){
float rating=0;
//assumes same factors size for user and movies
for(int i=0; i<userFactors.size();++i){
rating+=userFactors[i]*movieFactors[i];
}
return rating;
}
int get_max_user(std::map<int,std::vector<std::pair<int,int> > > &map){
int max_user=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
if(e->first>max_user){
max_user=e->first;
}
}
return max_user;
}
int get_max_movie(std::map<int,std::vector<std::pair<int,int> > > &map){
int max_movie=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
vector<pair<int, int> >::iterator mr=e->second.begin();
for(mr; mr<e->second.end(); ++mr){
if(mr->first>max_movie){
max_movie=e->first;
}
}
}
return max_movie;
}
int get_num_ratings(std::map<int,std::vector<std::pair<int,int> > > &map){
int num_ratings=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
vector<pair<int, int> >::iterator mr=e->second.begin();
for(mr; mr<e->second.end(); ++mr){
num_ratings++;
}
}
return num_ratings;
}
std::vector<float> getUserVector(int user, std::map<int,std::vector<std::pair<int,int> > > &map){
std::vector<float> usersRatings;
vector<pair<int,int> >::iterator rating=map[user].begin();
for(rating;rating<map[user].end();++rating){
usersRatings.push_back(user);
usersRatings.push_back(rating->first);
usersRatings.push_back(rating->second);
}
return usersRatings;
}
float norm(std::vector<float> &vec){
float sum=0;
for(int i=0; i<vec.size(); ++i){
sum+=vec[i]*vec[i];
}
return std::sqrt(sum);
}
float norm2(std::vector<float> &vec){
float sum=0;
for(int i=0; i<vec.size(); ++i){
sum+=vec[i]*vec[i];
}
return sum;
}
template<class T>
void dump_linear(int nl, std::vector<T> &vec){
int n=0;
for(int i=0;i<vec.size();++i){
++n;
std::cout<<vec[i]<<' ';
if(n>=nl && nl>0){
std::cout<<std::endl;
n=0;
}
}
std::cout<<std::endl;
}
__device__ void dotNUMFACTORS(int user, int movie, float *p_u, float *q_i, float *res){
__shared__ float cache[NUM_FACTORS];
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
int cache_index=threadIdx.x;
user=0;
movie=0;
float temp=0;
while(tid<NUM_FACTORS){
temp+=p_u[(user*NUM_FACTORS)+tid]*q_i[(movie*NUM_FACTORS)+tid];
tid+=blockDim.x*gridDim.x;//should be unnecessary, since block sizes must be multiple of 32, which is the #factors
}
cache[cache_index]=temp;
__syncthreads();
int i=blockDim.x/2;
while(i!=0){
if(cache_index<i){
cache[cache_index]+=cache[cache_index+i];
}
__syncthreads();
i/=2;
}
if(cache_index==0){
*res=cache[0];
}
}
__device__ void norm2FACTOR(int vec_indx, float *vec, float *res){
__shared__ float cache[NUM_FACTORS];
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
int cache_index=threadIdx.x;
float temp=0;
while(tid<NUM_FACTORS){
temp+=vec[(vec_indx*NUM_FACTORS)+tid]*vec[(vec_indx*NUM_FACTORS)+tid];
tid+=blockDim.x*gridDim.x;//should be unnecessary, since block sizes must be multiple of 32, which is the #factors
}
cache[cache_index]=temp;
__syncthreads();
int i=blockDim.x/2;
while(i!=0){
if(cache_index<i){
cache[cache_index]+=cache[cache_index+i];
}
__syncthreads();
i/=2;
}
if(cache_index==0){
*res=cache[0];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <fstream>
#include <sstream>
#include <string>
#include <vector>
#include <map>
#include <utility>
#include <algorithm>
#include <cstdlib>
#include <cmath>
#include <sys/time.h>
#include <hip/hip_runtime.h>
using namespace std;
bool verbose=false;
int benchmark=1;
#define LRATE 0.01
#define LPARAM 0.02
#define NUM_FACTORS 32
const float lparam=LPARAM;
const float lrate=LRATE;
double get_walltime(){
struct timeval tp;
gettimeofday(&tp, NULL);
return (double)(tp.tv_sec + tp.tv_usec/1000000.0);
}
float norm(std::vector<float> &vec);
float norm2(std::vector<float> &vec);
void file_to_map(std::ifstream &f, char delim, std::map<int,std::vector<std::pair<int,int> > > &map, int numlines);
void print_map( std::map<int,std::vector<std::pair<int,int> > > &map);
int get_max_user(std::map<int,std::vector<std::pair<int,int> > > &map);
int get_max_movie(std::map<int,std::vector<std::pair<int,int> > > &map);
int get_num_ratings(std::map<int,std::vector<std::pair<int,int> > > &map);
float predict_rating(std::vector<float> &userFactors, std::vector<float> &movieFactors);
void sgdFactors(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map);
void sgdFactorsCuda(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map);
//--------------------------------------------------------------------------CUDA
//__global__ void descendGradient(float *ratings, float *p_u, float *q_i);
__global__ void descendGradient(int num_ratings, float *ratings, float *p_u, float *q_i, float *min);
__device__ void dotNUMFACTORS(int user, int movie, float *p_u, float *q_i, float *res);
__device__ void norm2FACTOR(int vec_indx, float *vec, float *res);
template<class T>
void dump_linear(int nl, std::vector<T> &vec);
std::vector<float> getUserVector(int user, std::map<int,std::vector<std::pair<int,int> > > &map);
int main(int argc,char *argv[]){
std::string input_file_name;
char delim=' ';
int numlines=-1;
//argvars
if(argc>1){
int c=1;
while(c<argc){
std::string arg=argv[c];
if(arg=="-i" || arg=="--input-file"){
if(++c<argc){
input_file_name=argv[c++];
continue;
}
}
if(arg=="-n" || arg=="--size"){
if(++c<argc){
numlines=atoi(argv[c++]);
continue;
}
}
if(arg=="-d" || arg=="--delimiter"){
if(++c<argc){
delim=*argv[c++];
continue;
}
}
if(arg=="-v" || arg=="--verbose"){
verbose=true;
c++;
continue;
}
if(arg=="-k" || arg=="--benchmark"){
benchmark=5;
c++;
continue;
}
}
}
std::ifstream in_file(input_file_name.c_str());
std::map<int,std::vector<std::pair<int,int> > > ratings;
file_to_map(in_file, delim, ratings, numlines);
in_file.close();
std::vector<float> factors(NUM_FACTORS,0.1);
int max_user=get_max_user(ratings);
int max_movie=get_max_movie(ratings);
std::cout<<max_user<<std::endl;
std::cout<<max_movie<<std::endl;
std::vector<std::vector<float> > userFactors(max_user+1, factors);
std::vector<std::vector<float> > movieFactors(max_movie+1, factors);
//print_map(ratings);
double runtime_sum=0;
for(int b=0; b<benchmark; ++b){
double timer=get_walltime();
//sgdFactors(userFactors, movieFactors, ratings);
sgdFactorsCuda(userFactors, movieFactors, ratings);
timer=get_walltime()-timer;
runtime_sum+=timer;
}
runtime_sum/=benchmark;
std::cout<<"calculation time averaged over "<<benchmark<< "run(s) is "<<runtime_sum<<" seconds"<<std::endl;
}
//dangerous method with expected input sizes
//todo:fix!
void file_to_map(std::ifstream &f, char delim, std::map<int,std::vector<std::pair<int,int> > > &map, int numlines){
if(verbose){
std::cout<<"reading file..."<<std::endl;
}
std::string line;
if(f.is_open()){
int linenum=0;
std::vector<int> temp;
while(std::getline(f,line) && (numlines>linenum || numlines<0)){
std::stringstream ss(line);
std::string num;
while(std::getline(ss, num, delim)){
temp.push_back(atoi(num.c_str()));
}
map[temp[0]].push_back(std::make_pair(temp[1],temp[2]));
temp.clear();
linenum++;
}
if(verbose){
std::cout<<"loaded in "<<linenum<<" lines of text"<<std::endl;
std::cout<<"last line:"<<std::endl<<line<<std::endl;
}
}else{
if(verbose){
std::cout<<"file could not be opened"<<std::endl;
}
}
}
void print_map( std::map<int,std::vector<std::pair<int,int> > > &map){
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
std::cout<<"user: "<<user->first<<std::endl;
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
std::cout<<"movie"<<rating->first<<", rating: "<<rating->second<<std::endl;
}
}
}
void sgdFactors(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map){
float min, oldmin=0;
do{
oldmin=min;
min=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
min+=err*err;
for(int i=0;i<movieFactors[0].size();++i){
//float mfv=movieFactors[rating->first][i];
movieFactors[rating->first][i]+=lrate*(err*userFactors[user->first][i] -
lparam*movieFactors[rating->first][i]);
userFactors[user->first][i]+=lrate*(err*movieFactors[rating->first][i] -
lparam*userFactors[user->first][i]);
}
float n_movie=norm2(movieFactors[rating->first]);
float n_user=norm2(userFactors[rating->first]);
min+=lparam*(n_movie+n_user);
}
}
std::cout<<"err: "<<min<<std::endl;
}while(oldmin-min>1e-3 || oldmin==0);
std::map<int,std::vector<std::pair<int,int> > >::iterator user=map.begin();
for(user; user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
std::cout<<err<<std::endl;
}
}
}
void sgdFactorsCuda(std::vector<std::vector<float> > &userFactors,
std::vector<std::vector<float> > &movieFactors, std::map<int,std::vector<std::pair<int,int> > > &map){
float *ratings;
hipMalloc((void**)&ratings, 3*get_num_ratings(map)*sizeof(float));
int ratings_copied=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator user;
for(user=map.begin();user!=map.end();++user){
std::vector<float> v=getUserVector(user->first,map);
hipMemcpy(ratings+(ratings_copied*sizeof(float)), &v[0],v.size()*sizeof(float), hipMemcpyHostToDevice);
ratings_copied+=v.size();
}
int max_user=get_max_user(map);
int max_movie=get_max_movie(map);
float *q_i, *p_u, *min_d;
hipMalloc((void**)&p_u, max_user*userFactors.size()*sizeof(float));
hipMalloc((void**)&q_i, max_movie*movieFactors.size()*sizeof(float));
hipMalloc((void**)&min_d, sizeof(float));
hipMemcpy(p_u, &userFactors[0], max_user*userFactors.size()*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(q_i, &movieFactors[0], max_movie*movieFactors.size()*sizeof(float), hipMemcpyHostToDevice);
float *min, oldmin=0;
min=(float*)malloc(1*sizeof(float));
*min=0;
do{
oldmin=*min;
descendGradient<<<128,128>>>(get_num_ratings(map), ratings, p_u, q_i, min_d);
hipMemcpy(min, min_d, sizeof(float), hipMemcpyDeviceToHost);
std::cout<<"err: "<<*min<<std::endl;
}while(oldmin-*min>1e-3 || oldmin==0);
hipMemcpy(&userFactors[0], p_u, userFactors.size()*sizeof(float), hipMemcpyDeviceToHost);
hipMemcpy(&movieFactors[0], q_i, movieFactors.size()*sizeof(float), hipMemcpyDeviceToHost);
hipFree(p_u);
hipFree(q_i);
hipFree(min_d);
/*
for(user=map.begin(); user!=map.end(); ++user){
vector<pair<int, int> >::iterator rating=user->second.begin();
for(rating; rating<user->second.end(); ++rating){
float err=rating->second-predict_rating(userFactors[user->first], movieFactors[rating->first]);
std::cout<<err<<std::endl;
}
}
*/
}
__global__ void descendGradient(int num_ratings, float *ratings, float *p_u, float *q_i, float *min){
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
min[0]=300.0;
while(tid<num_ratings){
float predicted;
int userid=ratings[(tid*3)];
int movieid=ratings[(tid*3)+1];
int ratingval=ratings[(tid*3)+2];
//dotNUMFACTORS(userid, movieid, p_u, q_i, &predicted);
float err=ratingval-predicted;
*min+=err*err;
for(int i=0; i<NUM_FACTORS; ++i){
q_i[(NUM_FACTORS*movieid)+i]+=LRATE*(err*p_u[(NUM_FACTORS*userid)+i] - LPARAM*q_i[(NUM_FACTORS*movieid)+i]);
p_u[(NUM_FACTORS*userid)+i]+=LRATE*(err*q_i[(NUM_FACTORS*userid)+i] - LPARAM*q_i[(NUM_FACTORS*movieid)+i]);
}
float n2_movie, n2_user;
norm2FACTOR(userid, p_u, &n2_user);
norm2FACTOR(movieid, q_i, &n2_movie);
*min+=lparam*(n2_movie+n2_user);
__syncthreads();
//atomicAdd(d_sum, x[tid]);
min[0]+=(float)ratingval;
}
}
float predict_rating(std::vector<float> &userFactors, std::vector<float> &movieFactors){
float rating=0;
//assumes same factors size for user and movies
for(int i=0; i<userFactors.size();++i){
rating+=userFactors[i]*movieFactors[i];
}
return rating;
}
int get_max_user(std::map<int,std::vector<std::pair<int,int> > > &map){
int max_user=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
if(e->first>max_user){
max_user=e->first;
}
}
return max_user;
}
int get_max_movie(std::map<int,std::vector<std::pair<int,int> > > &map){
int max_movie=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
vector<pair<int, int> >::iterator mr=e->second.begin();
for(mr; mr<e->second.end(); ++mr){
if(mr->first>max_movie){
max_movie=e->first;
}
}
}
return max_movie;
}
int get_num_ratings(std::map<int,std::vector<std::pair<int,int> > > &map){
int num_ratings=0;
std::map<int,std::vector<std::pair<int,int> > >::iterator e=map.begin();
for(e; e!=map.end(); ++e){
vector<pair<int, int> >::iterator mr=e->second.begin();
for(mr; mr<e->second.end(); ++mr){
num_ratings++;
}
}
return num_ratings;
}
std::vector<float> getUserVector(int user, std::map<int,std::vector<std::pair<int,int> > > &map){
std::vector<float> usersRatings;
vector<pair<int,int> >::iterator rating=map[user].begin();
for(rating;rating<map[user].end();++rating){
usersRatings.push_back(user);
usersRatings.push_back(rating->first);
usersRatings.push_back(rating->second);
}
return usersRatings;
}
float norm(std::vector<float> &vec){
float sum=0;
for(int i=0; i<vec.size(); ++i){
sum+=vec[i]*vec[i];
}
return std::sqrt(sum);
}
float norm2(std::vector<float> &vec){
float sum=0;
for(int i=0; i<vec.size(); ++i){
sum+=vec[i]*vec[i];
}
return sum;
}
template<class T>
void dump_linear(int nl, std::vector<T> &vec){
int n=0;
for(int i=0;i<vec.size();++i){
++n;
std::cout<<vec[i]<<' ';
if(n>=nl && nl>0){
std::cout<<std::endl;
n=0;
}
}
std::cout<<std::endl;
}
__device__ void dotNUMFACTORS(int user, int movie, float *p_u, float *q_i, float *res){
__shared__ float cache[NUM_FACTORS];
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
int cache_index=threadIdx.x;
user=0;
movie=0;
float temp=0;
while(tid<NUM_FACTORS){
temp+=p_u[(user*NUM_FACTORS)+tid]*q_i[(movie*NUM_FACTORS)+tid];
tid+=blockDim.x*gridDim.x;//should be unnecessary, since block sizes must be multiple of 32, which is the #factors
}
cache[cache_index]=temp;
__syncthreads();
int i=blockDim.x/2;
while(i!=0){
if(cache_index<i){
cache[cache_index]+=cache[cache_index+i];
}
__syncthreads();
i/=2;
}
if(cache_index==0){
*res=cache[0];
}
}
__device__ void norm2FACTOR(int vec_indx, float *vec, float *res){
__shared__ float cache[NUM_FACTORS];
int tid=(blockIdx.x*blockDim.x)+threadIdx.x;
int cache_index=threadIdx.x;
float temp=0;
while(tid<NUM_FACTORS){
temp+=vec[(vec_indx*NUM_FACTORS)+tid]*vec[(vec_indx*NUM_FACTORS)+tid];
tid+=blockDim.x*gridDim.x;//should be unnecessary, since block sizes must be multiple of 32, which is the #factors
}
cache[cache_index]=temp;
__syncthreads();
int i=blockDim.x/2;
while(i!=0){
if(cache_index<i){
cache[cache_index]+=cache[cache_index+i];
}
__syncthreads();
i/=2;
}
if(cache_index==0){
*res=cache[0];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15descendGradientiPfS_S_S_
.globl _Z15descendGradientiPfS_S_S_
.p2align 8
.type _Z15descendGradientiPfS_S_S_,@function
_Z15descendGradientiPfS_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x20
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v9, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0x43960000
global_store_b32 v9, v2, s[8:9]
v_cmp_le_i32_e64 s2, s3, v1
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_21
s_load_b32 s3, s[4:5], 0x0
v_lshl_add_u32 v1, v1, 1, v1
v_lshlrev_b32_e32 v10, 2, v0
s_mov_b32 s13, 0
v_mov_b32_e32 v11, 0x7fc00000
s_load_b64 s[10:11], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s15, s3
s_cselect_b32 s6, 12, 18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, s6
global_load_u16 v3, v2, s[4:5]
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_eq_u32_e64 s0, 0, v0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, v3, v[0:1]
v_mul_lo_u32 v12, s3, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
v_readfirstlane_b32 s12, v3
v_cmp_gt_i32_e64 s1, 32, v4
v_cmp_lt_u32_e64 s3, 1, v3
s_branch .LBB0_3
.LBB0_2:
global_load_b32 v1, v9, s[8:9]
ds_load_b32 v7, v9
v_cndmask_b32_e64 v13, v13, v2, s0
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e64 v14, v14, v7, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v13, v14
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, 0x3ca3d70a, v2
v_cvt_i32_f32_e32 v2, v3
global_store_b32 v9, v1, s[8:9]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v1, v9, s[8:9]
v_cvt_f32_i32_e32 v2, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v1, v2
global_store_b32 v9, v1, s[8:9]
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_21
.LBB0_3:
global_load_b96 v[1:3], v[5:6], off
s_and_b32 s4, exec_lo, s2
global_store_b32 v9, v11, s[8:9]
s_or_b32 s13, s4, s13
s_mov_b64 s[4:5], 0
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v1, v1
v_cvt_i32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v7, 5, v1
v_lshlrev_b32_e32 v1, 5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[15:16], 2, v[7:8]
v_lshlrev_b64 v[17:18], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s10, v17
v_add_co_ci_u32_e32 v16, vcc_lo, s11, v18, vcc_lo
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v17, vcc_lo, v15, s4
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v19, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v8, vcc_lo
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmpk_eq_i32 s4, 0x80
global_store_b32 v[17:18], v11, off
global_store_b32 v[19:20], v11, off
s_cbranch_scc0 .LBB0_4
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s4, s1
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v8, v4
s_mov_b32 s5, 0
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v7, v8
v_add_nc_u32_e32 v8, v8, v12
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_u32 v15, vcc_lo, s6, v15
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 31, v8
global_load_b32 v15, v[15:16], off
s_or_b32 s5, vcc_lo, s5
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v15, v15
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s5
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_and_not1_b32 vcc_lo, exec_lo, s3
s_mov_b32 s4, s12
ds_store_b32 v10, v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_16
.LBB0_10:
ds_load_b32 v2, v9
v_mov_b32_e32 v7, 0
s_and_saveexec_b32 s4, s1
s_cbranch_execz .LBB0_14
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, v4
s_mov_b32 s5, 0
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v15, v1, v8
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_u32 v15, vcc_lo, s10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v16, vcc_lo, s11, v16, vcc_lo
global_load_b32 v15, v[15:16], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v7, v15, v15 :: v_dual_add_nc_u32 v8, v8, v12
v_cmp_lt_i32_e32 vcc_lo, 31, v8
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s5
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_and_not1_b32 vcc_lo, exec_lo, s3
s_mov_b32 s4, s12
ds_store_b32 v10, v7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_19
s_branch .LBB0_2
.p2align 6
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s14
s_cmp_gt_u32 s4, 3
s_mov_b32 s4, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
.LBB0_16:
s_lshr_b32 s5, s4, 1
s_mov_b32 s14, exec_lo
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_15
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v7, v10
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v7
ds_store_b32 v10, v2
s_branch .LBB0_15
.p2align 6
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s14
s_cmp_gt_u32 s4, 3
s_mov_b32 s4, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_19:
s_lshr_b32 s5, s4, 1
s_mov_b32 s14, exec_lo
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_18
v_add_lshl_u32 v1, s5, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v7, v10
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v7
ds_store_b32 v10, v1
s_branch .LBB0_18
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15descendGradientiPfS_S_S_
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15descendGradientiPfS_S_S_, .Lfunc_end0-_Z15descendGradientiPfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15descendGradientiPfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15descendGradientiPfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z15descendGradientiPfS_S_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R8, c[0x0][0x180] ; /* 0x0000600000087a02 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x184] ; /* 0x00006100ff097624 */
/* 0x000fe200078e00ff */
/*0040*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R2, R3, c[0x0][0x0], R0 ; /* 0x0000000003027a24 */
/* 0x001fe400078e0200 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, 0x43960000 ; /* 0x43960000ff037424 */
/* 0x000fc600078e00ff */
/*0080*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fe40003f06270 */
/*0090*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0001f6000c101906 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0b7435 */
/* 0x000fe200000001ff */
/*00c0*/ IMAD R10, R2, 0x3, RZ ; /* 0x00000003020a7824 */
/* 0x000fe200078e02ff */
/*00d0*/ MOV R7, 0x43960000 ; /* 0x4396000000077802 */
/* 0x000fe20000000f00 */
/*00e0*/ IMAD.SHL.U32 R3, R0, 0x4, RZ ; /* 0x0000000400037824 */
/* 0x001fe200078e00ff */
/*00f0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fc40000000800 */
/*0100*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc80008011604 */
/*0110*/ IMAD.WIDE R10, R10, R11, c[0x0][0x168] ; /* 0x00005a000a0a7625 */
/* 0x000fca00078e020b */
/*0120*/ LDG.E R12, [R10.64] ; /* 0x000000060a0c7981 */
/* 0x000ea8000c1e1900 */
/*0130*/ LDG.E R13, [R10.64+0x4] ; /* 0x000004060a0d7981 */
/* 0x001ee2000c1e1900 */
/*0140*/ IMAD.MOV.U32 R14, RZ, RZ, 0x7fc00000 ; /* 0x7fc00000ff0e7424 */
/* 0x000fc600078e00ff */
/*0150*/ LDG.E R4, [R10.64+0x8] ; /* 0x000008060a047981 */
/* 0x000162000c1e1900 */
/*0160*/ FFMA R15, R14, +QNAN , R7 ; /* 0x7fc000000e0f7823 */
/* 0x000fe20000000007 */
/*0170*/ MOV R24, RZ ; /* 0x000000ff00187202 */
/* 0x000fe20000000f00 */
/*0180*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff107624 */
/* 0x000fe200078e00ff */
/*0190*/ MOV R17, c[0x0][0x17c] ; /* 0x00005f0000117a02 */
/* 0x000fe20000000f00 */
/*01a0*/ ULDC.64 UR8, c[0x0][0x170] ; /* 0x00005c0000087ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x0001e2000c101906 */
/*01c0*/ F2I.TRUNC.NTZ R12, R12 ; /* 0x0000000c000c7305 */
/* 0x004e70000020f100 */
/*01d0*/ F2I.TRUNC.NTZ R13, R13 ; /* 0x0000000d000d7305 */
/* 0x008ea2000020f100 */
/*01e0*/ IMAD.SHL.U32 R7, R12, 0x20, RZ ; /* 0x000000200c077824 */
/* 0x002fe200078e00ff */
/*01f0*/ SHF.L.U32 R25, R13, 0x5, RZ ; /* 0x000000050d197819 */
/* 0x005fcc00000006ff */
/*0200*/ MOV R15, UR9 ; /* 0x00000009000f7c02 */
/* 0x001fe20008000f00 */
/*0210*/ IMAD.U32 R14, RZ, RZ, UR8 ; /* 0x00000008ff0e7e24 */
/* 0x000fe2000f8e00ff */
/*0220*/ MOV R13, R17 ; /* 0x00000011000d7202 */
/* 0x000fe20000000f00 */
/*0230*/ IMAD.MOV.U32 R12, RZ, RZ, R16 ; /* 0x000000ffff0c7224 */
/* 0x000fc400078e0010 */
/*0240*/ IMAD.WIDE R14, R7, 0x4, R14 ; /* 0x00000004070e7825 */
/* 0x000fc800078e020e */
/*0250*/ IMAD.WIDE R16, R25, 0x4, R12 ; /* 0x0000000419107825 */
/* 0x000fe200078e020c */
/*0260*/ LDG.E R18, [R14.64] ; /* 0x000000060e127981 */
/* 0x000ea8000c1e1900 */
/*0270*/ LDG.E R20, [R16.64] ; /* 0x0000000610147981 */
/* 0x000ee2000c1e1900 */
/*0280*/ FMUL R27, R18, +QNAN ; /* 0x7fc00000121b7820 */
/* 0x004fe20000400000 */
/*0290*/ F2F.F64.F32 R20, R20 ; /* 0x0000001400147310 */
/* 0x008ff00000201800 */
/*02a0*/ F2F.F64.F32 R18, R27 ; /* 0x0000001b00127310 */
/* 0x000e240000201800 */
/*02b0*/ DFMA R18, R20, c[0x2][0x0], R18 ; /* 0x0080000014127a2b */
/* 0x001e0c0000000012 */
/*02c0*/ DFMA R28, R18, c[0x2][0x8], R20 ; /* 0x00800200121c7a2b */
/* 0x001e140000000014 */
/*02d0*/ F2F.F32.F64 R29, R28 ; /* 0x0000001c001d7310 */
/* 0x001e220000301000 */
/*02e0*/ IMAD.WIDE R18, R7, 0x4, R12 ; /* 0x0000000407127825 */
/* 0x000fe200078e020c */
/*02f0*/ STG.E [R16.64], R29 ; /* 0x0000001d10007986 */
/* 0x0011e8000c101906 */
/*0300*/ LDG.E R21, [R18.64] ; /* 0x0000000612157981 */
/* 0x000ea8000c1e1900 */
/*0310*/ LDG.E R26, [R14.64] ; /* 0x000000060e1a7981 */
/* 0x000ee2000c1e1900 */
/*0320*/ F2F.F64.F32 R22, R29 ; /* 0x0000001d00167310 */
/* 0x000fe20000201800 */
/*0330*/ FMUL R28, R21, +QNAN ; /* 0x7fc00000151c7820 */
/* 0x004fce0000400000 */
/*0340*/ F2F.F64.F32 R20, R28 ; /* 0x0000001c00147310 */
/* 0x000e640000201800 */
/*0350*/ DFMA R22, R22, c[0x2][0x0], R20 ; /* 0x0080000016167a2b */
/* 0x00264c0000000014 */
/*0360*/ F2F.F64.F32 R20, R26 ; /* 0x0000001a00147310 */
/* 0x008e640000201800 */
/*0370*/ DFMA R26, R22, c[0x2][0x8], R20 ; /* 0x00800200161a7a2b */
/* 0x0022a40000000014 */
/*0380*/ LDG.E R20, [R14.64+0x4] ; /* 0x000004060e147981 */
/* 0x002ef0000c1e1900 */
/*0390*/ F2F.F32.F64 R27, R26 ; /* 0x0000001a001b7310 */
/* 0x004e640000301000 */
/*03a0*/ STG.E [R14.64], R27 ; /* 0x0000001b0e007986 */
/* 0x0023e8000c101906 */
/*03b0*/ LDG.E R22, [R16.64+0x4] ; /* 0x0000040610167981 */
/* 0x000ea2000c1e1900 */
/*03c0*/ FMUL R20, R20, +QNAN ; /* 0x7fc0000014147820 */
/* 0x008fcc0000400000 */
/*03d0*/ F2F.F64.F32 R20, R20 ; /* 0x0000001400147310 */
/* 0x000ff00000201800 */
/*03e0*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x004ea40000201800 */
/*03f0*/ DFMA R20, R22, c[0x2][0x0], R20 ; /* 0x0080000016147a2b */
/* 0x004e0c0000000014 */
/*0400*/ DFMA R28, R20, c[0x2][0x8], R22 ; /* 0x00800200141c7a2b */
/* 0x001e140000000016 */
/*0410*/ F2F.F32.F64 R29, R28 ; /* 0x0000001c001d7310 */
/* 0x001e240000301000 */
/*0420*/ STG.E [R16.64+0x4], R29 ; /* 0x0000041d10007986 */
/* 0x0011e8000c101906 */
/*0430*/ LDG.E R21, [R18.64+0x4] ; /* 0x0000040612157981 */
/* 0x000e68000c1e1900 */
/*0440*/ LDG.E R26, [R14.64+0x4] ; /* 0x000004060e1a7981 */
/* 0x000ea2000c1e1900 */
/*0450*/ F2F.F64.F32 R22, R29 ; /* 0x0000001d00167310 */
/* 0x000fe20000201800 */
/*0460*/ FMUL R27, R21, +QNAN ; /* 0x7fc00000151b7820 */
/* 0x002fce0000400000 */
/*0470*/ F2F.F64.F32 R20, R27 ; /* 0x0000001b00147310 */
/* 0x000e640000201800 */
/*0480*/ DFMA R22, R22, c[0x2][0x0], R20 ; /* 0x0080000016167a2b */
/* 0x00244c0000000014 */
/*0490*/ F2F.F64.F32 R20, R26 ; /* 0x0000001a00147310 */
/* 0x004e640000201800 */
/*04a0*/ DFMA R26, R22, c[0x2][0x8], R20 ; /* 0x00800200161a7a2b */
/* 0x0022a40000000014 */
/*04b0*/ LDG.E R20, [R14.64+0x8] ; /* 0x000008060e147981 */
/* 0x002ef0000c1e1900 */
/*04c0*/ F2F.F32.F64 R27, R26 ; /* 0x0000001a001b7310 */
/* 0x004e640000301000 */
/*04d0*/ STG.E [R14.64+0x4], R27 ; /* 0x0000041b0e007986 */
/* 0x0023e8000c101906 */
/*04e0*/ LDG.E R22, [R16.64+0x8] ; /* 0x0000080610167981 */
/* 0x000ea2000c1e1900 */
/*04f0*/ FMUL R28, R20, +QNAN ; /* 0x7fc00000141c7820 */
/* 0x008fc80000400000 */
/*0500*/ F2F.F64.F32 R20, R28 ; /* 0x0000001c00147310 */
/* 0x000ff00000201800 */
/*0510*/ F2F.F64.F32 R22, R22 ; /* 0x0000001600167310 */
/* 0x004ea40000201800 */
/*0520*/ DFMA R20, R22, c[0x2][0x0], R20 ; /* 0x0080000016147a2b */
/* 0x004e0c0000000014 */
/*0530*/ DFMA R28, R20, c[0x2][0x8], R22 ; /* 0x00800200141c7a2b */
/* 0x001e140000000016 */
/*0540*/ F2F.F32.F64 R29, R28 ; /* 0x0000001c001d7310 */
/* 0x001e240000301000 */
/*0550*/ STG.E [R16.64+0x8], R29 ; /* 0x0000081d10007986 */
/* 0x0011e8000c101906 */
/*0560*/ LDG.E R20, [R18.64+0x8] ; /* 0x0000080612147981 */
/* 0x000e68000c1e1900 */
/*0570*/ LDG.E R26, [R14.64+0x8] ; /* 0x000008060e1a7981 */
/* 0x000ea2000c1e1900 */
/*0580*/ F2F.F64.F32 R22, R29 ; /* 0x0000001d00167310 */
/* 0x000fe20000201800 */
/*0590*/ FMUL R27, R20, +QNAN ; /* 0x7fc00000141b7820 */
/* 0x002fce0000400000 */
/*05a0*/ F2F.F64.F32 R20, R27 ; /* 0x0000001b00147310 */
/* 0x000e640000201800 */
/*05b0*/ DFMA R22, R22, c[0x2][0x0], R20 ; /* 0x0080000016167a2b */
/* 0x00244c0000000014 */
/*05c0*/ F2F.F64.F32 R20, R26 ; /* 0x0000001a00147310 */
/* 0x004e640000201800 */
/*05d0*/ DFMA R26, R22, c[0x2][0x8], R20 ; /* 0x00800200161a7a2b */
/* 0x0022a40000000014 */
/*05e0*/ LDG.E R20, [R14.64+0xc] ; /* 0x00000c060e147981 */
/* 0x002ef0000c1e1900 */
/*05f0*/ F2F.F32.F64 R27, R26 ; /* 0x0000001a001b7310 */
/* 0x004e640000301000 */
/*0600*/ STG.E [R14.64+0x8], R27 ; /* 0x0000081b0e007986 */
/* 0x002fe8000c101906 */
/*0610*/ LDG.E R21, [R16.64+0xc] ; /* 0x00000c0610157981 */
/* 0x000ea2000c1e1900 */
/*0620*/ FMUL R20, R20, +QNAN ; /* 0x7fc0000014147820 */
/* 0x008fc80000400000 */
/*0630*/ F2F.F64.F32 R22, R20 ; /* 0x0000001400167310 */
/* 0x000ff00000201800 */
/*0640*/ F2F.F64.F32 R20, R21 ; /* 0x0000001500147310 */
/* 0x004e640000201800 */
/*0650*/ DFMA R22, R20, c[0x2][0x0], R22 ; /* 0x0080000014167a2b */
/* 0x002e0c0000000016 */
/*0660*/ DFMA R28, R22, c[0x2][0x8], R20 ; /* 0x00800200161c7a2b */
/* 0x001e140000000014 */
/*0670*/ F2F.F32.F64 R29, R28 ; /* 0x0000001c001d7310 */
/* 0x001e240000301000 */
/*0680*/ STG.E [R16.64+0xc], R29 ; /* 0x00000c1d10007986 */
/* 0x0011e8000c101906 */
/*0690*/ LDG.E R18, [R18.64+0xc] ; /* 0x00000c0612127981 */
/* 0x0002a8000c1e1900 */
/*06a0*/ LDG.E R19, [R14.64+0xc] ; /* 0x00000c060e137981 */
/* 0x002ee2000c1e1900 */
/*06b0*/ F2F.F64.F32 R22, R29 ; /* 0x0000001d00167310 */
/* 0x000fe20000201800 */
/*06c0*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fc80007ffe0ff */
/*06d0*/ ISETP.NE.AND P0, PT, R24, 0x20, PT ; /* 0x000000201800780c */
/* 0x000fe20003f05270 */
/*06e0*/ UIADD3 UR8, UP0, UR8, 0x10, URZ ; /* 0x0000001008087890 */
/* 0x000fe2000ff1e03f */
/*06f0*/ IADD3 R16, P1, R12, 0x10, RZ ; /* 0x000000100c107810 */
/* 0x001fc60007f3e0ff */
/*0700*/ UIADD3.X UR9, URZ, UR9, URZ, UP0, !UPT ; /* 0x000000093f097290 */
/* 0x000fe400087fe43f */
/*0710*/ IMAD.X R17, RZ, RZ, R13, P1 ; /* 0x000000ffff117224 */
/* 0x000fe400008e060d */
/*0720*/ FMUL R26, R18, +QNAN ; /* 0x7fc00000121a7820 */
/* 0x004fcc0000400000 */
/*0730*/ F2F.F64.F32 R26, R26 ; /* 0x0000001a001a7310 */
/* 0x000e300000201800 */
/*0740*/ F2F.F64.F32 R20, R19 ; /* 0x0000001300147310 */
/* 0x008e620000201800 */
/*0750*/ DFMA R22, R22, c[0x2][0x0], R26 ; /* 0x0080000016167a2b */
/* 0x001e4c000000001a */
/*0760*/ DFMA R20, R22, c[0x2][0x8], R20 ; /* 0x0080020016147a2b */
/* 0x002e140000000014 */
/*0770*/ F2F.F32.F64 R21, R20 ; /* 0x0000001400157310 */
/* 0x001e240000301000 */
/*0780*/ STG.E [R14.64+0xc], R21 ; /* 0x00000c150e007986 */
/* 0x0011e2000c101906 */
/*0790*/ @P0 BRA 0x200 ; /* 0xfffffa6000000947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R2, 0x1f, PT ; /* 0x0000001f0200780c */
/* 0x000fe20003f24270 */
/*07b0*/ BSSY B0, 0x8b0 ; /* 0x000000f000007945 */
/* 0x000fe20003800000 */
/*07c0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe4000bf05270 */
/*07d0*/ MOV R15, RZ ; /* 0x000000ff000f7202 */
/* 0x001fd20000000f00 */
/*07e0*/ @P1 BRA 0x8a0 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.MOV.U32 R15, RZ, RZ, RZ ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e00ff */
/*0800*/ MOV R14, R2 ; /* 0x00000002000e7202 */
/* 0x000fc80000000f00 */
/*0810*/ HFMA2.MMA R13, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff0d7435 */
/* 0x000fe200000001ff */
/*0820*/ IMAD.IADD R12, R7, 0x1, R14 ; /* 0x00000001070c7824 */
/* 0x000fd200078e020e */
/*0830*/ IMAD.WIDE R12, R12, R13, c[0x0][0x170] ; /* 0x00005c000c0c7625 */
/* 0x000fcc00078e020d */
/*0840*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea2000c1e1900 */
/*0850*/ MOV R17, c[0x0][0x0] ; /* 0x0000000000117a02 */
/* 0x000fca0000000f00 */
/*0860*/ IMAD R14, R17, c[0x0][0xc], R14 ; /* 0x00000300110e7a24 */
/* 0x000fca00078e020e */
/*0870*/ ISETP.GE.AND P2, PT, R14, 0x20, PT ; /* 0x000000200e00780c */
/* 0x000fe20003f46270 */
/*0880*/ FFMA R15, R12, R12, R15 ; /* 0x0000000c0c0f7223 */
/* 0x004fd8000000000f */
/*0890*/ @!P2 BRA 0x810 ; /* 0xffffff700000a947 */
/* 0x000fea000383ffff */
/*08a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*08b0*/ STS [R0.X4], R15 ; /* 0x0000000f00007388 */
/* 0x0001e80000004800 */
/*08c0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*08d0*/ @!P0 BRA 0x9b0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*08e0*/ IMAD.U32 R7, RZ, RZ, UR4 ; /* 0x00000004ff077e24 */
/* 0x001fca000f8e00ff */
/*08f0*/ ISETP.GE.AND P2, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f46270 */
/*0900*/ IADD3 R14, R7, 0x1, RZ ; /* 0x00000001070e7810 */
/* 0x000fd60007ffe0ff */
/*0910*/ @!P2 LEA R12, R7.reuse, R3, 0x2 ; /* 0x00000003070ca211 */
/* 0x040fe200078e10ff */
/*0920*/ @!P2 LDS R13, [R0.X4] ; /* 0x00000000000da984 */
/* 0x000fe20000004800 */
/*0930*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fc800078f08ff */
/*0940*/ @!P2 LDS R12, [R12] ; /* 0x000000000c0ca984 */
/* 0x000e220000000800 */
/*0950*/ SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fe20000011407 */
/*0960*/ @!P2 FADD R13, R13, R12 ; /* 0x0000000c0d0da221 */
/* 0x001fca0000000000 */
/*0970*/ @!P2 STS [R0.X4], R13 ; /* 0x0000000d0000a388 */
/* 0x0001e80000004800 */
/*0980*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0990*/ ISETP.GT.U32.AND P2, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fda0003f44070 */
/*09a0*/ @P2 BRA 0x8f0 ; /* 0xffffff4000002947 */
/* 0x001fea000383ffff */
/*09b0*/ LDS R14, [RZ] ; /* 0x00000000ff0e7984 */
/* 0x001e220000000800 */
/*09c0*/ BSSY B0, 0xab0 ; /* 0x000000e000007945 */
/* 0x000fe20003800000 */
/*09d0*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*09e0*/ @P1 BRA 0xaa0 ; /* 0x000000b000001947 */
/* 0x000fea0003800000 */
/*09f0*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe200078e00ff */
/*0a00*/ MOV R16, R2 ; /* 0x0000000200107202 */
/* 0x000fc80000000f00 */
/*0a10*/ IADD3 R12, R25, R16, RZ ; /* 0x00000010190c7210 */
/* 0x000fe20007ffe0ff */
/*0a20*/ IMAD.MOV.U32 R13, RZ, RZ, 0x4 ; /* 0x00000004ff0d7424 */
/* 0x000fc800078e00ff */
/*0a30*/ IMAD.WIDE R12, R12, R13, c[0x0][0x178] ; /* 0x00005e000c0c7625 */
/* 0x000fcc00078e020d */
/*0a40*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000ea2000c1e1900 */
/*0a50*/ MOV R15, c[0x0][0x0] ; /* 0x00000000000f7a02 */
/* 0x000fca0000000f00 */
/*0a60*/ IMAD R16, R15, c[0x0][0xc], R16 ; /* 0x000003000f107a24 */
/* 0x000fca00078e0210 */
/*0a70*/ ISETP.GE.AND P1, PT, R16, 0x20, PT ; /* 0x000000201000780c */
/* 0x000fe20003f26270 */
/*0a80*/ FFMA R7, R12, R12, R7 ; /* 0x0000000c0c077223 */
/* 0x004fd80000000007 */
/*0a90*/ @!P1 BRA 0xa10 ; /* 0xffffff7000009947 */
/* 0x000fea000383ffff */
/*0aa0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0ab0*/ STS [R0.X4], R7 ; /* 0x0000000700007388 */
/* 0x0003e80000004800 */
/*0ac0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0ad0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fc80003f25270 */
/*0ae0*/ FSEL R5, R14, R5, !P1 ; /* 0x000000050e057208 */
/* 0x001fe20004800000 */
/*0af0*/ @!P0 BRA 0xbd0 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0b00*/ MOV R7, UR4 ; /* 0x0000000400077c02 */
/* 0x002fc80008000f00 */
/*0b10*/ ISETP.GE.AND P0, PT, R0, R7, PT ; /* 0x000000070000720c */
/* 0x000fe40003f06270 */
/*0b20*/ IADD3 R14, R7, 0x1, RZ ; /* 0x00000001070e7810 */
/* 0x000fd60007ffe0ff */
/*0b30*/ @!P0 IMAD R12, R7.reuse, 0x4, R3 ; /* 0x00000004070c8824 */
/* 0x040fe200078e0203 */
/*0b40*/ @!P0 LDS R13, [R0.X4] ; /* 0x00000000000d8984 */
/* 0x000fe20000004800 */
/*0b50*/ LEA.HI R7, R7, R7, RZ, 0x1 ; /* 0x0000000707077211 */
/* 0x000fc800078f08ff */
/*0b60*/ @!P0 LDS R12, [R12] ; /* 0x000000000c0c8984 */
/* 0x000e220000000800 */
/*0b70*/ SHF.R.S32.HI R7, RZ, 0x1, R7 ; /* 0x00000001ff077819 */
/* 0x000fe20000011407 */
/*0b80*/ @!P0 FADD R13, R13, R12 ; /* 0x0000000c0d0d8221 */
/* 0x001fca0000000000 */
/*0b90*/ @!P0 STS [R0.X4], R13 ; /* 0x0000000d00008388 */
/* 0x0001e80000004800 */
/*0ba0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0bb0*/ ISETP.GT.U32.AND P0, PT, R14, 0x2, PT ; /* 0x000000020e00780c */
/* 0x000fda0003f04070 */
/*0bc0*/ @P0 BRA 0xb10 ; /* 0xffffff4000000947 */
/* 0x001fea000383ffff */
/*0bd0*/ LDG.E R7, [R8.64] ; /* 0x0000000608077981 */
/* 0x002ea8000c1e1900 */
/*0be0*/ LDS R12, [RZ] ; /* 0x00000000ff0c7984 */
/* 0x000e240000000800 */
/*0bf0*/ @P1 MOV R12, R6 ; /* 0x00000006000c1202 */
/* 0x001fca0000000f00 */
/*0c00*/ FADD R6, R12, R5 ; /* 0x000000050c067221 */
/* 0x000fc80000000000 */
/*0c10*/ FFMA R13, R6, 0.019999999552965164185, R7 ; /* 0x3ca3d70a060d7823 */
/* 0x004fca0000000007 */
/*0c20*/ STG.E [R8.64], R13 ; /* 0x0000000d08007986 */
/* 0x0001e8000c101906 */
/*0c30*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0c40*/ LDG.E R7, [R8.64] ; /* 0x0000000608077981 */
/* 0x000ea2000c1e1900 */
/*0c50*/ F2I.TRUNC.NTZ R4, R4 ; /* 0x0000000400047305 */
/* 0x020e70000020f100 */
/*0c60*/ I2F R6, R4 ; /* 0x0000000400067306 */
/* 0x002ea40000201400 */
/*0c70*/ FADD R7, R7, R6 ; /* 0x0000000607077221 */
/* 0x004fe20000000000 */
/*0c80*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x000fc80000000f00 */
/*0c90*/ STG.E [R8.64], R7 ; /* 0x0000000708007986 */
/* 0x0001e2000c101906 */
/*0ca0*/ BRA 0x120 ; /* 0xfffff47000007947 */
/* 0x000fea000383ffff */
/*0cb0*/ BRA 0xcb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z15descendGradientiPfS_S_S_
.globl _Z15descendGradientiPfS_S_S_
.p2align 8
.type _Z15descendGradientiPfS_S_S_,@function
_Z15descendGradientiPfS_S_S_:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x20
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
v_mov_b32_e32 v9, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0x43960000
global_store_b32 v9, v2, s[8:9]
v_cmp_le_i32_e64 s2, s3, v1
v_cmp_gt_i32_e32 vcc_lo, s3, v1
s_and_saveexec_b32 s3, vcc_lo
s_cbranch_execz .LBB0_21
s_load_b32 s3, s[4:5], 0x0
v_lshl_add_u32 v1, v1, 1, v1
v_lshlrev_b32_e32 v10, 2, v0
s_mov_b32 s13, 0
v_mov_b32_e32 v11, 0x7fc00000
s_load_b64 s[10:11], s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_u32 s15, s3
s_cselect_b32 s6, 12, 18
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_mov_b32_e32 v2, s6
global_load_u16 v3, v2, s[4:5]
s_load_b128 s[4:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_eq_u32_e64 s0, 0, v0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s15, v3, v[0:1]
v_mul_lo_u32 v12, s3, v3
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v2, vcc_lo
v_readfirstlane_b32 s12, v3
v_cmp_gt_i32_e64 s1, 32, v4
v_cmp_lt_u32_e64 s3, 1, v3
s_branch .LBB0_3
.LBB0_2:
global_load_b32 v1, v9, s[8:9]
ds_load_b32 v7, v9
v_cndmask_b32_e64 v13, v13, v2, s0
s_waitcnt lgkmcnt(0)
v_cndmask_b32_e64 v14, v14, v7, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v13, v14
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v1, 0x3ca3d70a, v2
v_cvt_i32_f32_e32 v2, v3
global_store_b32 v9, v1, s[8:9]
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
global_load_b32 v1, v9, s[8:9]
v_cvt_f32_i32_e32 v2, v2
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v1, v1, v2
global_store_b32 v9, v1, s[8:9]
s_and_not1_b32 exec_lo, exec_lo, s13
s_cbranch_execz .LBB0_21
.LBB0_3:
global_load_b96 v[1:3], v[5:6], off
s_and_b32 s4, exec_lo, s2
global_store_b32 v9, v11, s[8:9]
s_or_b32 s13, s4, s13
s_mov_b64 s[4:5], 0
s_waitcnt vmcnt(0)
v_cvt_i32_f32_e32 v1, v1
v_cvt_i32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v7, 5, v1
v_lshlrev_b32_e32 v1, 5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v8, 31, v7
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[15:16], 2, v[7:8]
v_lshlrev_b64 v[17:18], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v15
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v16, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v15, vcc_lo, s10, v17
v_add_co_ci_u32_e32 v16, vcc_lo, s11, v18, vcc_lo
.LBB0_4:
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v17, vcc_lo, v15, s4
v_add_co_ci_u32_e32 v18, vcc_lo, s5, v16, vcc_lo
v_add_co_u32 v19, vcc_lo, v2, s4
v_add_co_ci_u32_e32 v20, vcc_lo, s5, v8, vcc_lo
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmpk_eq_i32 s4, 0x80
global_store_b32 v[17:18], v11, off
global_store_b32 v[19:20], v11, off
s_cbranch_scc0 .LBB0_4
v_mov_b32_e32 v2, 0
s_and_saveexec_b32 s4, s1
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v8, v4
s_mov_b32 s5, 0
.LBB0_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v15, v7, v8
v_add_nc_u32_e32 v8, v8, v12
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_u32 v15, vcc_lo, s6, v15
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v16, vcc_lo, s7, v16, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 31, v8
global_load_b32 v15, v[15:16], off
s_or_b32 s5, vcc_lo, s5
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v2, v15, v15
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_7
s_or_b32 exec_lo, exec_lo, s5
.LBB0_9:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_and_not1_b32 vcc_lo, exec_lo, s3
s_mov_b32 s4, s12
ds_store_b32 v10, v2
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_16
.LBB0_10:
ds_load_b32 v2, v9
v_mov_b32_e32 v7, 0
s_and_saveexec_b32 s4, s1
s_cbranch_execz .LBB0_14
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v8, v4
s_mov_b32 s5, 0
.LBB0_12:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v15, v1, v8
v_ashrrev_i32_e32 v16, 31, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[15:16], 2, v[15:16]
v_add_co_u32 v15, vcc_lo, s10, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v16, vcc_lo, s11, v16, vcc_lo
global_load_b32 v15, v[15:16], off
s_waitcnt vmcnt(0)
v_dual_fmac_f32 v7, v15, v15 :: v_dual_add_nc_u32 v8, v8, v12
v_cmp_lt_i32_e32 vcc_lo, 31, v8
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_12
s_or_b32 exec_lo, exec_lo, s5
.LBB0_14:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
s_and_not1_b32 vcc_lo, exec_lo, s3
s_mov_b32 s4, s12
ds_store_b32 v10, v7
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccz .LBB0_19
s_branch .LBB0_2
.p2align 6
.LBB0_15:
s_or_b32 exec_lo, exec_lo, s14
s_cmp_gt_u32 s4, 3
s_mov_b32 s4, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_10
.LBB0_16:
s_lshr_b32 s5, s4, 1
s_mov_b32 s14, exec_lo
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_15
v_add_lshl_u32 v2, s5, v0, 2
ds_load_b32 v2, v2
ds_load_b32 v7, v10
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v7
ds_store_b32 v10, v2
s_branch .LBB0_15
.p2align 6
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s14
s_cmp_gt_u32 s4, 3
s_mov_b32 s4, s5
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB0_2
.LBB0_19:
s_lshr_b32 s5, s4, 1
s_mov_b32 s14, exec_lo
v_cmpx_gt_u32_e64 s5, v0
s_cbranch_execz .LBB0_18
v_add_lshl_u32 v1, s5, v0, 2
ds_load_b32 v1, v1
ds_load_b32 v7, v10
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v1, v1, v7
ds_store_b32 v10, v1
s_branch .LBB0_18
.LBB0_21:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15descendGradientiPfS_S_S_
.amdhsa_group_segment_fixed_size 128
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 21
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z15descendGradientiPfS_S_S_, .Lfunc_end0-_Z15descendGradientiPfS_S_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 128
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15descendGradientiPfS_S_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15descendGradientiPfS_S_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 21
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* correlation.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <sys/time.h>
#include <cuda.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 1.05
#define GPU_DEVICE 0
/* Problem size */
#define M 2048
#define N 2048
/* Thread block dimensions for kernel 1*/
#define DIM_THREAD_BLOCK_KERNEL_1_X 256
#define DIM_THREAD_BLOCK_KERNEL_1_Y 1
/* Thread block dimensions for kernel 2*/
#define DIM_THREAD_BLOCK_KERNEL_2_X 256
#define DIM_THREAD_BLOCK_KERNEL_2_Y 1
/* Thread block dimensions for kernel 3*/
#define DIM_THREAD_BLOCK_KERNEL_3_X 32
#define DIM_THREAD_BLOCK_KERNEL_3_Y 8
/* Thread block dimensions for kernel 4*/
#define DIM_THREAD_BLOCK_KERNEL_4_X 256
#define DIM_THREAD_BLOCK_KERNEL_4_Y 1
#define sqrt_of_array_cell(x,j) sqrt(x[j])
#define FLOAT_N 3214212.01f
#define EPS 0.005f
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void init_arrays(DATA_TYPE* data)
{
int i, j;
for (i=0; i < (M+1); i++)
{
for (j=0; j< (N+1); j++)
{
data[i*(N+1) + j] = ((DATA_TYPE) i*j)/ (M+1);
}
}
}
void correlation(DATA_TYPE* data, DATA_TYPE* mean, DATA_TYPE* stddev, DATA_TYPE* symmat)
{
int i, j, j1, j2;
// Determine mean of column vectors of input data matrix
for (j = 1; j < (M+1); j++)
{
mean[j] = 0.0;
for (i = 1; i < (N+1); i++)
{
mean[j] += data[i*(M+1) + j];
}
mean[j] /= (DATA_TYPE)FLOAT_N;
}
// Determine standard deviations of column vectors of data matrix.
for (j = 1; j < (M+1); j++)
{
stddev[j] = 0.0;
for (i = 1; i < (N+1); i++)
{
stddev[j] += (data[i*(M+1) + j] - mean[j]) * (data[i*(M+1) + j] - mean[j]);
}
stddev[j] /= FLOAT_N;
stddev[j] = sqrt_of_array_cell(stddev, j);
stddev[j] = stddev[j] <= EPS ? 1.0 : stddev[j];
}
// Center and reduce the column vectors.
for (i = 1; i < (N+1); i++)
{
for (j = 1; j < (M+1); j++)
{
data[i*(M+1) + j] -= mean[j];
data[i*(M+1) + j] /= (sqrt(FLOAT_N)*stddev[j]) ;
}
}
// Calculate the m * m correlation matrix.
for (j1 = 1; j1 < M; j1++)
{
symmat[j1*(M+1) + j1] = 1.0;
for (j2 = j1+1; j2 < (M+1); j2++)
{
symmat[j1*(M+1) + j2] = 0.0;
for (i = 1; i < (N+1); i++)
{
symmat[j1*(M+1) + j2] += (data[i*(M+1) + j1] * data[i*(M+1) + j2]);
}
symmat[j2*(M+1) + j1] = symmat[j1*(M+1) + j2];
}
}
symmat[M*(M+1) + M] = 1.0;
}
void compareResults(DATA_TYPE* symmat, DATA_TYPE* symmat_outputFromGpu)
{
int i,j,fail;
fail = 0;
for (i=1; i < (M+1); i++)
{
for (j=1; j < (N+1); j++)
{
if (percentDiff(symmat[i*(N+1) + j], symmat_outputFromGpu[i*(N+1) + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
printf("i: %d j: %d\n1: %f 2: %f\n", i, j, symmat[i*N + j], symmat_outputFromGpu[i*N + j]);
}
}
}
// print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
cudaSetDevice( GPU_DEVICE );
}
__global__ void mean_kernel(DATA_TYPE *mean, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if ((j >= 1) && (j < (M+1)))
{
mean[j] = 0.0;
int i;
for(i=1; i < (N+1); i++)
{
mean[j] += data[i*(M+1) + j];
}
mean[j] /= (DATA_TYPE)FLOAT_N;
}
}
__global__ void std_kernel(DATA_TYPE *mean, DATA_TYPE *std, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if ((j >= 1) && (j < (M+1)))
{
std[j] = 0.0;
int i;
for(i = 1; i < (N+1); i++)
{
std[j] += (data[i*(M+1) + j] - mean[j]) * (data[i*(M+1) + j] - mean[j]);
}
std[j] /= (FLOAT_N);
std[j] = sqrt(std[j]);
if(std[j] <= EPS)
{
std[j] = 1.0;
}
}
}
__global__ void reduce_kernel(DATA_TYPE *mean, DATA_TYPE *std, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i = blockIdx.y * blockDim.y + threadIdx.y + 1;
if ((i >= 1) && (i < (N+1)) && (j >= 1) && (j < (M+1)))
{
data[i*(M+1) + j] -= mean[j];
data[i*(M+1) + j] /= (sqrt(FLOAT_N) * std[j]);
}
}
__global__ void corr_kernel(DATA_TYPE *symmat, DATA_TYPE *data)
{
int j1 = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i, j2;
if ((j1 >= 1) && (j1 < M))
{
symmat[j1*(M+1) + j1] = 1.0;
for (j2 = (j1 + 1); j2 < (M+1); j2++)
{
symmat[j1*(M+1) + j2] = 0.0;
for(i = 1; i < (N+1); i++)
{
symmat[j1*(M+1) + j2] += data[i*(M+1) + j1] * data[i*(M+1) + j2];
}
symmat[j2*(M+1) + j1] = symmat[j1*(M+1) + j2];
}
}
}
void correlationCuda(DATA_TYPE* data, DATA_TYPE* mean, DATA_TYPE* stddev, DATA_TYPE* symmat,
DATA_TYPE* symmat_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *data_gpu;
DATA_TYPE *stddev_gpu;
DATA_TYPE *mean_gpu;
DATA_TYPE *symmat_gpu;
cudaMalloc((void **)&data_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1));
cudaMalloc((void **)&symmat_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1));
cudaMalloc((void **)&stddev_gpu, sizeof(DATA_TYPE) * (M+1));
cudaMalloc((void **)&mean_gpu, sizeof(DATA_TYPE) * (M+1));
cudaMemcpy(data_gpu, data, sizeof(DATA_TYPE) * (M+1) * (N+1), cudaMemcpyHostToDevice);
cudaMemcpy(symmat_gpu, symmat, sizeof(DATA_TYPE) * (M+1) * (N+1), cudaMemcpyHostToDevice);
cudaMemcpy(stddev_gpu, stddev, sizeof(DATA_TYPE) * (M+1), cudaMemcpyHostToDevice);
cudaMemcpy(mean_gpu, mean, sizeof(DATA_TYPE) * (M+1), cudaMemcpyHostToDevice);
dim3 block1(DIM_THREAD_BLOCK_KERNEL_1_X, DIM_THREAD_BLOCK_KERNEL_1_Y);
dim3 grid1((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_1_X)), 1);
dim3 block2(DIM_THREAD_BLOCK_KERNEL_2_X, DIM_THREAD_BLOCK_KERNEL_2_Y);
dim3 grid2((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_2_X)), 1);
dim3 block3(DIM_THREAD_BLOCK_KERNEL_3_X, DIM_THREAD_BLOCK_KERNEL_3_Y);
dim3 grid3((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_3_X)), (size_t)(ceil((float)(N)) / ((float)DIM_THREAD_BLOCK_KERNEL_3_Y)));
dim3 block4(DIM_THREAD_BLOCK_KERNEL_4_X, DIM_THREAD_BLOCK_KERNEL_4_Y);
dim3 grid4((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_4_X)), 1);
t_start = rtclock();
mean_kernel<<< grid1, block1 >>>(mean_gpu,data_gpu);
cudaThreadSynchronize();
std_kernel<<< grid2, block2 >>>(mean_gpu,stddev_gpu,data_gpu);
cudaThreadSynchronize();
reduce_kernel<<< grid3, block3 >>>(mean_gpu,stddev_gpu,data_gpu);
cudaThreadSynchronize();
corr_kernel<<< grid4, block4 >>>(symmat_gpu,data_gpu);
cudaThreadSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
DATA_TYPE valueAtSymmatIndexMTimesMPlus1PlusMPoint = 1.0;
cudaMemcpy(&(symmat_gpu[(M)*(M+1) + (M)]), &valueAtSymmatIndexMTimesMPlus1PlusMPoint, sizeof(DATA_TYPE), cudaMemcpyHostToDevice);
cudaMemcpy(symmat_outputFromGpu, symmat_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1), cudaMemcpyDeviceToHost);
cudaFree(data_gpu);
cudaFree(symmat_gpu);
cudaFree(stddev_gpu);
cudaFree(mean_gpu);
}
int main()
{
double t_start, t_end;
DATA_TYPE* data;
DATA_TYPE* mean;
DATA_TYPE* stddev;
DATA_TYPE* symmat;
DATA_TYPE* symmat_outputFromGpu;
data = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
mean = (DATA_TYPE*)malloc((M+1)*sizeof(DATA_TYPE));
stddev = (DATA_TYPE*)malloc((M+1)*sizeof(DATA_TYPE));
symmat = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
symmat_outputFromGpu = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
init_arrays(data);
GPU_argv_init();
correlationCuda(data, mean, stddev, symmat, symmat_outputFromGpu);
t_start = rtclock();
correlation(data, mean, stddev, symmat);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(symmat, symmat_outputFromGpu);
free(data);
free(mean);
free(stddev);
free(symmat);
free(symmat_outputFromGpu);
return 0;
} | .file "tmpxft_001bcd9d_00000000-6_correlation.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2068:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2068:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.globl _Z6absValf
.type _Z6absValf, @function
_Z6absValf:
.LFB2058:
.cfi_startproc
endbr64
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L13
.L10:
ret
.L13:
xorps .LC3(%rip), %xmm0
ret
.cfi_endproc
.LFE2058:
.size _Z6absValf, .-_Z6absValf
.globl _Z11percentDiffdd
.type _Z11percentDiffdd, @function
_Z11percentDiffdd:
.LFB2059:
.cfi_startproc
endbr64
pxor %xmm2, %xmm2
cvtsd2ss %xmm0, %xmm2
pxor %xmm3, %xmm3
comiss %xmm2, %xmm3
ja .L35
.L15:
cvtss2sd %xmm2, %xmm2
movsd .LC4(%rip), %xmm3
comisd %xmm2, %xmm3
jbe .L17
pxor %xmm2, %xmm2
cvtsd2ss %xmm1, %xmm2
pxor %xmm3, %xmm3
comiss %xmm2, %xmm3
ja .L36
.L19:
pxor %xmm3, %xmm3
cvtss2sd %xmm2, %xmm3
pxor %xmm2, %xmm2
movsd .LC4(%rip), %xmm4
comisd %xmm3, %xmm4
ja .L14
.L17:
movapd %xmm0, %xmm2
subsd %xmm1, %xmm2
cvtsd2ss %xmm2, %xmm2
pxor %xmm1, %xmm1
comiss %xmm2, %xmm1
ja .L37
.L22:
addsd .LC5(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss %xmm0, %xmm1
pxor %xmm0, %xmm0
comiss %xmm1, %xmm0
ja .L38
.L24:
movaps %xmm2, %xmm0
divss %xmm1, %xmm0
pxor %xmm1, %xmm1
comiss %xmm0, %xmm1
ja .L39
.L26:
movaps %xmm0, %xmm2
mulss .LC6(%rip), %xmm2
.L14:
movaps %xmm2, %xmm0
ret
.L35:
xorps .LC3(%rip), %xmm2
jmp .L15
.L36:
xorps .LC3(%rip), %xmm2
jmp .L19
.L37:
xorps .LC3(%rip), %xmm2
jmp .L22
.L38:
xorps .LC3(%rip), %xmm1
jmp .L24
.L39:
xorps .LC3(%rip), %xmm0
jmp .L26
.cfi_endproc
.LFE2059:
.size _Z11percentDiffdd, .-_Z11percentDiffdd
.globl _Z11init_arraysPf
.type _Z11init_arraysPf, @function
_Z11init_arraysPf:
.LFB2060:
.cfi_startproc
endbr64
movq %rdi, %rdx
movl $0, %ecx
movss .LC7(%rip), %xmm2
.L41:
movl $0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
.L42:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss %xmm1, %xmm0
divss %xmm2, %xmm0
movss %xmm0, (%rdx,%rax,4)
addq $1, %rax
cmpq $2049, %rax
jne .L42
addl $1, %ecx
addq $8196, %rdx
cmpl $2049, %ecx
jne .L41
ret
.cfi_endproc
.LFE2060:
.size _Z11init_arraysPf, .-_Z11init_arraysPf
.globl _Z11correlationPfS_S_S_
.type _Z11correlationPfS_S_S_, @function
_Z11correlationPfS_S_S_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 24(%rsp)
movq %rsi, %r12
movq %rdx, %r13
movq %rcx, 16(%rsp)
leaq 4(%rsi), %r15
leaq 16793608(%rdi), %rbx
movq %rbx, %rcx
movq %r15, %rsi
movl $1, %edi
.L47:
movq %rsi, %rdx
movl $0x00000000, (%rsi)
leaq -16785408(%rcx), %rax
.L46:
movss (%rdx), %xmm0
addss (%rax), %xmm0
movss %xmm0, (%rdx)
addq $8196, %rax
cmpq %rcx, %rax
jne .L46
divss .LC9(%rip), %xmm0
movss %xmm0, (%rdx)
addl $1, %edi
addq $4, %rsi
addq $4, %rcx
cmpl $2049, %edi
jne .L47
leaq 4(%r13), %rax
movq %rax, 8(%rsp)
movq %rbx, %r14
movl $1, 4(%rsp)
.L54:
movq 8(%rsp), %rax
movq %rax, %rbp
movl $0x00000000, (%rax)
leaq -16785408(%r14), %rax
.L48:
movss (%rax), %xmm0
subss (%r15), %xmm0
mulss %xmm0, %xmm0
addss 0(%rbp), %xmm0
movss %xmm0, 0(%rbp)
addq $8196, %rax
cmpq %r14, %rax
jne .L48
divss .LC9(%rip), %xmm0
pxor %xmm3, %xmm3
ucomiss %xmm0, %xmm3
ja .L73
sqrtss %xmm0, %xmm0
.L51:
movss .LC10(%rip), %xmm4
movaps %xmm0, %xmm1
cmpnless %xmm4, %xmm1
andps %xmm1, %xmm0
movss .LC8(%rip), %xmm5
andnps %xmm5, %xmm1
orps %xmm1, %xmm0
movss %xmm0, 0(%rbp)
addl $1, 4(%rsp)
movl 4(%rsp), %eax
addq $4, 8(%rsp)
addq $4, %r15
addq $4, %r14
cmpl $2049, %eax
jne .L54
movq 24(%rsp), %rcx
addq $8200, %rcx
movss .LC11(%rip), %xmm2
.L55:
movq %rcx, %rdx
movl $4, %eax
.L56:
movss (%rdx), %xmm0
subss (%r12,%rax), %xmm0
movss %xmm0, (%rdx)
movaps %xmm2, %xmm1
mulss 0(%r13,%rax), %xmm1
divss %xmm1, %xmm0
movss %xmm0, (%rdx)
addq $4, %rdx
addq $4, %rax
cmpq $8196, %rax
jne .L56
addq $8196, %rcx
cmpq %rbx, %rcx
jne .L55
movq 16(%rsp), %rax
leaq 8204(%rax), %r10
movl $1, %r9d
movss .LC8(%rip), %xmm1
movl $2049, %r11d
jmp .L62
.L73:
call sqrtf@PLT
jmp .L51
.L58:
addq $1, %r9
addq $4, %rbx
addq $8200, %r10
.L62:
movss %xmm1, -4(%r10)
leal 1(%r9), %eax
cmpl $2048, %eax
jg .L58
leaq 8192(%r10), %rdi
movq %r10, %rsi
movl $1, %ecx
movq %r11, %r8
subq %r9, %r8
.L60:
movq %rsi, %rdx
movl $0x00000000, (%rsi)
leaq -16785408(%rbx), %rax
.L59:
movss (%rax), %xmm0
mulss (%rax,%rcx,4), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $8196, %rax
cmpq %rbx, %rax
jne .L59
movss %xmm0, (%rdi)
addq $4, %rsi
addq $8196, %rdi
addq $1, %rcx
cmpq %r8, %rcx
jne .L60
addq $1, %r9
addq $4, %rbx
addq $8200, %r10
cmpq $2048, %r9
jne .L62
movq 16(%rsp), %rax
movl $0x3f800000, 16793600(%rax)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z11correlationPfS_S_S_, .-_Z11correlationPfS_S_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC13:
.string "i: %d j: %d\n1: %f 2: %f\n"
.section .rodata.str1.8
.align 8
.LC14:
.string "Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n"
.text
.globl _Z14compareResultsPfS_
.type _Z14compareResultsPfS_, @function
_Z14compareResultsPfS_:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %r13
movq %rsi, %r12
movq $8200, 8(%rsp)
movl $2048, %r15d
movl $0, %r14d
movl $1, 4(%rsp)
jmp .L77
.L78:
addl $1, %ebp
addq $4, %rbx
cmpl $2049, %ebp
je .L85
.L80:
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rbx), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rbx), %xmm1
call _Z11percentDiffdd
cvtss2sd %xmm0, %xmm0
comisd .LC12(%rip), %xmm0
jbe .L78
addl $1, %r14d
leal 0(%rbp,%r15), %eax
cltq
pxor %xmm0, %xmm0
cvtss2sd 0(%r13,%rax,4), %xmm0
pxor %xmm1, %xmm1
cvtss2sd (%r12,%rax,4), %xmm1
movl %ebp, %ecx
movl 4(%rsp), %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L78
.L85:
addl $1, 4(%rsp)
movl 4(%rsp), %eax
addl $2048, %r15d
addq $8196, 8(%rsp)
cmpl $2049, %eax
je .L81
.L77:
movq 8(%rsp), %rbx
movl $1, %ebp
jmp .L80
.L81:
movl %r14d, %edx
movsd .LC12(%rip), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _Z14compareResultsPfS_, .-_Z14compareResultsPfS_
.section .rodata.str1.8
.align 8
.LC15:
.string "setting device %d with name %s\n"
.text
.globl _Z13GPU_argv_initv
.type _Z13GPU_argv_initv, @function
_Z13GPU_argv_initv:
.LFB2063:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
subq $1040, %rsp
.cfi_def_cfa_offset 1056
movq %fs:40, %rax
movq %rax, 1032(%rsp)
xorl %eax, %eax
movq %rsp, %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
movq %rbx, %rcx
movl $0, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call cudaSetDevice@PLT
movq 1032(%rsp), %rax
subq %fs:40, %rax
jne .L89
addq $1040, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
ret
.L89:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size _Z13GPU_argv_initv, .-_Z13GPU_argv_initv
.globl _Z33__device_stub__Z11mean_kernelPfS_PfS_
.type _Z33__device_stub__Z11mean_kernelPfS_PfS_, @function
_Z33__device_stub__Z11mean_kernelPfS_PfS_:
.LFB2090:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L94
.L90:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L95
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L94:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11mean_kernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L90
.L95:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z33__device_stub__Z11mean_kernelPfS_PfS_, .-_Z33__device_stub__Z11mean_kernelPfS_PfS_
.globl _Z11mean_kernelPfS_
.type _Z11mean_kernelPfS_, @function
_Z11mean_kernelPfS_:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11mean_kernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z11mean_kernelPfS_, .-_Z11mean_kernelPfS_
.globl _Z34__device_stub__Z10std_kernelPfS_S_PfS_S_
.type _Z34__device_stub__Z10std_kernelPfS_S_PfS_S_, @function
_Z34__device_stub__Z10std_kernelPfS_S_PfS_S_:
.LFB2092:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L102
.L98:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L103
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L102:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10std_kernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L98
.L103:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z34__device_stub__Z10std_kernelPfS_S_PfS_S_, .-_Z34__device_stub__Z10std_kernelPfS_S_PfS_S_
.globl _Z10std_kernelPfS_S_
.type _Z10std_kernelPfS_S_, @function
_Z10std_kernelPfS_S_:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10std_kernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z10std_kernelPfS_S_, .-_Z10std_kernelPfS_S_
.globl _Z37__device_stub__Z13reduce_kernelPfS_S_PfS_S_
.type _Z37__device_stub__Z13reduce_kernelPfS_S_PfS_S_, @function
_Z37__device_stub__Z13reduce_kernelPfS_S_PfS_S_:
.LFB2094:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L110
.L106:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L111
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L110:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13reduce_kernelPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L106
.L111:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z37__device_stub__Z13reduce_kernelPfS_S_PfS_S_, .-_Z37__device_stub__Z13reduce_kernelPfS_S_PfS_S_
.globl _Z13reduce_kernelPfS_S_
.type _Z13reduce_kernelPfS_S_, @function
_Z13reduce_kernelPfS_S_:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z13reduce_kernelPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z13reduce_kernelPfS_S_, .-_Z13reduce_kernelPfS_S_
.globl _Z33__device_stub__Z11corr_kernelPfS_PfS_
.type _Z33__device_stub__Z11corr_kernelPfS_PfS_, @function
_Z33__device_stub__Z11corr_kernelPfS_PfS_:
.LFB2096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L118
.L114:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L119
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L118:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11corr_kernelPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L114
.L119:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z33__device_stub__Z11corr_kernelPfS_PfS_, .-_Z33__device_stub__Z11corr_kernelPfS_PfS_
.globl _Z11corr_kernelPfS_
.type _Z11corr_kernelPfS_, @function
_Z11corr_kernelPfS_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11corr_kernelPfS_PfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z11corr_kernelPfS_, .-_Z11corr_kernelPfS_
.section .rodata.str1.1
.LC16:
.string "GPU Runtime: %0.6lfs\n"
.text
.globl _Z15correlationCudaPfS_S_S_S_
.type _Z15correlationCudaPfS_S_S_S_, @function
_Z15correlationCudaPfS_S_S_S_:
.LFB2064:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $160, %rsp
.cfi_def_cfa_offset 208
movq %rdi, %r14
movq %rsi, %rbp
movq %rdx, %r12
movq %rcx, %r13
movq %r8, %rbx
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rdi
movl $16793604, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movl $16793604, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $8196, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $8196, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $16793604, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $16793604, %edx
movq %r13, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8196, %edx
movq %r12, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $8196, %edx
movq %rbp, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $256, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $8, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $256, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $8, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
movl $32, 104(%rsp)
movl $8, 108(%rsp)
movl $1, 112(%rsp)
movl $64, 116(%rsp)
movl $256, 120(%rsp)
movl $1, 124(%rsp)
movl $256, 128(%rsp)
movl $1, 132(%rsp)
movl $1, 136(%rsp)
movl $8, 140(%rsp)
movl $1, 144(%rsp)
movl $1, 148(%rsp)
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movl 64(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 56(%rsp), %rdx
movq 68(%rsp), %rdi
movl 76(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L129
.L123:
call cudaThreadSynchronize@PLT
movl 88(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 80(%rsp), %rdx
movq 92(%rsp), %rdi
movl 100(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L130
.L124:
call cudaThreadSynchronize@PLT
movl 112(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 104(%rsp), %rdx
movq 116(%rsp), %rdi
movl 124(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L131
.L125:
call cudaThreadSynchronize@PLT
movl 136(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 128(%rsp), %rdx
movq 140(%rsp), %rdi
movl 148(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L132
.L126:
call cudaThreadSynchronize@PLT
call _Z7rtclockv
subsd 8(%rsp), %xmm0
leaq .LC16(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movl $0x3f800000, 20(%rsp)
leaq 20(%rsp), %rsi
movq 48(%rsp), %rax
leaq 16793600(%rax), %rdi
movl $1, %ecx
movl $4, %edx
call cudaMemcpy@PLT
movl $2, %ecx
movl $16793604, %edx
movq 48(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L133
addq $160, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L129:
.cfi_restore_state
movq 24(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z33__device_stub__Z11mean_kernelPfS_PfS_
jmp .L123
.L130:
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z34__device_stub__Z10std_kernelPfS_S_PfS_S_
jmp .L124
.L131:
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z37__device_stub__Z13reduce_kernelPfS_S_PfS_S_
jmp .L125
.L132:
movq 24(%rsp), %rsi
movq 48(%rsp), %rdi
call _Z33__device_stub__Z11corr_kernelPfS_PfS_
jmp .L126
.L133:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2064:
.size _Z15correlationCudaPfS_S_S_S_, .-_Z15correlationCudaPfS_S_S_S_
.section .rodata.str1.1
.LC17:
.string "CPU Runtime: %0.6lfs\n"
.text
.globl main
.type main, @function
main:
.LFB2065:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $16, %rsp
.cfi_def_cfa_offset 64
movl $16793604, %edi
call malloc@PLT
movq %rax, %rbp
movl $8196, %edi
call malloc@PLT
movq %rax, %r14
movl $8196, %edi
call malloc@PLT
movq %rax, %r13
movl $16793604, %edi
call malloc@PLT
movq %rax, %rbx
movl $16793604, %edi
call malloc@PLT
movq %rax, %r12
movq %rbp, %rdi
call _Z11init_arraysPf
call _Z13GPU_argv_initv
movq %r12, %r8
movq %rbx, %rcx
movq %r13, %rdx
movq %r14, %rsi
movq %rbp, %rdi
call _Z15correlationCudaPfS_S_S_S_
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movq %rbx, %rcx
movq %r13, %rdx
movq %r14, %rsi
movq %rbp, %rdi
call _Z11correlationPfS_S_S_
call _Z7rtclockv
subsd 8(%rsp), %xmm0
leaq .LC17(%rip), %rdx
movl $2, %esi
movq stdout(%rip), %rdi
movl $1, %eax
call __fprintf_chk@PLT
movq %r12, %rsi
movq %rbx, %rdi
call _Z14compareResultsPfS_
movq %rbp, %rdi
call free@PLT
movq %r14, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r12, %rdi
call free@PLT
movl $0, %eax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z11corr_kernelPfS_"
.LC19:
.string "_Z13reduce_kernelPfS_S_"
.LC20:
.string "_Z10std_kernelPfS_S_"
.LC21:
.string "_Z11mean_kernelPfS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z11corr_kernelPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC19(%rip), %rdx
movq %rdx, %rcx
leaq _Z13reduce_kernelPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC20(%rip), %rdx
movq %rdx, %rcx
leaq _Z10std_kernelPfS_S_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC21(%rip), %rdx
movq %rdx, %rcx
leaq _Z11mean_kernelPfS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC3:
.long -2147483648
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC4:
.long 1202590843
.long 1065646817
.align 8
.LC5:
.long -536870912
.long 1044740494
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1120403456
.align 4
.LC7:
.long 1157632000
.align 4
.LC8:
.long 1065353216
.align 4
.LC9:
.long 1245982224
.align 4
.LC10:
.long 1000593162
.align 4
.LC11:
.long 1155537489
.section .rodata.cst8
.align 8
.LC12:
.long -858993459
.long 1072745676
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* correlation.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <sys/time.h>
#include <cuda.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 1.05
#define GPU_DEVICE 0
/* Problem size */
#define M 2048
#define N 2048
/* Thread block dimensions for kernel 1*/
#define DIM_THREAD_BLOCK_KERNEL_1_X 256
#define DIM_THREAD_BLOCK_KERNEL_1_Y 1
/* Thread block dimensions for kernel 2*/
#define DIM_THREAD_BLOCK_KERNEL_2_X 256
#define DIM_THREAD_BLOCK_KERNEL_2_Y 1
/* Thread block dimensions for kernel 3*/
#define DIM_THREAD_BLOCK_KERNEL_3_X 32
#define DIM_THREAD_BLOCK_KERNEL_3_Y 8
/* Thread block dimensions for kernel 4*/
#define DIM_THREAD_BLOCK_KERNEL_4_X 256
#define DIM_THREAD_BLOCK_KERNEL_4_Y 1
#define sqrt_of_array_cell(x,j) sqrt(x[j])
#define FLOAT_N 3214212.01f
#define EPS 0.005f
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void init_arrays(DATA_TYPE* data)
{
int i, j;
for (i=0; i < (M+1); i++)
{
for (j=0; j< (N+1); j++)
{
data[i*(N+1) + j] = ((DATA_TYPE) i*j)/ (M+1);
}
}
}
void correlation(DATA_TYPE* data, DATA_TYPE* mean, DATA_TYPE* stddev, DATA_TYPE* symmat)
{
int i, j, j1, j2;
// Determine mean of column vectors of input data matrix
for (j = 1; j < (M+1); j++)
{
mean[j] = 0.0;
for (i = 1; i < (N+1); i++)
{
mean[j] += data[i*(M+1) + j];
}
mean[j] /= (DATA_TYPE)FLOAT_N;
}
// Determine standard deviations of column vectors of data matrix.
for (j = 1; j < (M+1); j++)
{
stddev[j] = 0.0;
for (i = 1; i < (N+1); i++)
{
stddev[j] += (data[i*(M+1) + j] - mean[j]) * (data[i*(M+1) + j] - mean[j]);
}
stddev[j] /= FLOAT_N;
stddev[j] = sqrt_of_array_cell(stddev, j);
stddev[j] = stddev[j] <= EPS ? 1.0 : stddev[j];
}
// Center and reduce the column vectors.
for (i = 1; i < (N+1); i++)
{
for (j = 1; j < (M+1); j++)
{
data[i*(M+1) + j] -= mean[j];
data[i*(M+1) + j] /= (sqrt(FLOAT_N)*stddev[j]) ;
}
}
// Calculate the m * m correlation matrix.
for (j1 = 1; j1 < M; j1++)
{
symmat[j1*(M+1) + j1] = 1.0;
for (j2 = j1+1; j2 < (M+1); j2++)
{
symmat[j1*(M+1) + j2] = 0.0;
for (i = 1; i < (N+1); i++)
{
symmat[j1*(M+1) + j2] += (data[i*(M+1) + j1] * data[i*(M+1) + j2]);
}
symmat[j2*(M+1) + j1] = symmat[j1*(M+1) + j2];
}
}
symmat[M*(M+1) + M] = 1.0;
}
void compareResults(DATA_TYPE* symmat, DATA_TYPE* symmat_outputFromGpu)
{
int i,j,fail;
fail = 0;
for (i=1; i < (M+1); i++)
{
for (j=1; j < (N+1); j++)
{
if (percentDiff(symmat[i*(N+1) + j], symmat_outputFromGpu[i*(N+1) + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
printf("i: %d j: %d\n1: %f 2: %f\n", i, j, symmat[i*N + j], symmat_outputFromGpu[i*N + j]);
}
}
}
// print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
cudaSetDevice( GPU_DEVICE );
}
__global__ void mean_kernel(DATA_TYPE *mean, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if ((j >= 1) && (j < (M+1)))
{
mean[j] = 0.0;
int i;
for(i=1; i < (N+1); i++)
{
mean[j] += data[i*(M+1) + j];
}
mean[j] /= (DATA_TYPE)FLOAT_N;
}
}
__global__ void std_kernel(DATA_TYPE *mean, DATA_TYPE *std, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if ((j >= 1) && (j < (M+1)))
{
std[j] = 0.0;
int i;
for(i = 1; i < (N+1); i++)
{
std[j] += (data[i*(M+1) + j] - mean[j]) * (data[i*(M+1) + j] - mean[j]);
}
std[j] /= (FLOAT_N);
std[j] = sqrt(std[j]);
if(std[j] <= EPS)
{
std[j] = 1.0;
}
}
}
__global__ void reduce_kernel(DATA_TYPE *mean, DATA_TYPE *std, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i = blockIdx.y * blockDim.y + threadIdx.y + 1;
if ((i >= 1) && (i < (N+1)) && (j >= 1) && (j < (M+1)))
{
data[i*(M+1) + j] -= mean[j];
data[i*(M+1) + j] /= (sqrt(FLOAT_N) * std[j]);
}
}
__global__ void corr_kernel(DATA_TYPE *symmat, DATA_TYPE *data)
{
int j1 = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i, j2;
if ((j1 >= 1) && (j1 < M))
{
symmat[j1*(M+1) + j1] = 1.0;
for (j2 = (j1 + 1); j2 < (M+1); j2++)
{
symmat[j1*(M+1) + j2] = 0.0;
for(i = 1; i < (N+1); i++)
{
symmat[j1*(M+1) + j2] += data[i*(M+1) + j1] * data[i*(M+1) + j2];
}
symmat[j2*(M+1) + j1] = symmat[j1*(M+1) + j2];
}
}
}
void correlationCuda(DATA_TYPE* data, DATA_TYPE* mean, DATA_TYPE* stddev, DATA_TYPE* symmat,
DATA_TYPE* symmat_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *data_gpu;
DATA_TYPE *stddev_gpu;
DATA_TYPE *mean_gpu;
DATA_TYPE *symmat_gpu;
cudaMalloc((void **)&data_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1));
cudaMalloc((void **)&symmat_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1));
cudaMalloc((void **)&stddev_gpu, sizeof(DATA_TYPE) * (M+1));
cudaMalloc((void **)&mean_gpu, sizeof(DATA_TYPE) * (M+1));
cudaMemcpy(data_gpu, data, sizeof(DATA_TYPE) * (M+1) * (N+1), cudaMemcpyHostToDevice);
cudaMemcpy(symmat_gpu, symmat, sizeof(DATA_TYPE) * (M+1) * (N+1), cudaMemcpyHostToDevice);
cudaMemcpy(stddev_gpu, stddev, sizeof(DATA_TYPE) * (M+1), cudaMemcpyHostToDevice);
cudaMemcpy(mean_gpu, mean, sizeof(DATA_TYPE) * (M+1), cudaMemcpyHostToDevice);
dim3 block1(DIM_THREAD_BLOCK_KERNEL_1_X, DIM_THREAD_BLOCK_KERNEL_1_Y);
dim3 grid1((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_1_X)), 1);
dim3 block2(DIM_THREAD_BLOCK_KERNEL_2_X, DIM_THREAD_BLOCK_KERNEL_2_Y);
dim3 grid2((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_2_X)), 1);
dim3 block3(DIM_THREAD_BLOCK_KERNEL_3_X, DIM_THREAD_BLOCK_KERNEL_3_Y);
dim3 grid3((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_3_X)), (size_t)(ceil((float)(N)) / ((float)DIM_THREAD_BLOCK_KERNEL_3_Y)));
dim3 block4(DIM_THREAD_BLOCK_KERNEL_4_X, DIM_THREAD_BLOCK_KERNEL_4_Y);
dim3 grid4((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_4_X)), 1);
t_start = rtclock();
mean_kernel<<< grid1, block1 >>>(mean_gpu,data_gpu);
cudaThreadSynchronize();
std_kernel<<< grid2, block2 >>>(mean_gpu,stddev_gpu,data_gpu);
cudaThreadSynchronize();
reduce_kernel<<< grid3, block3 >>>(mean_gpu,stddev_gpu,data_gpu);
cudaThreadSynchronize();
corr_kernel<<< grid4, block4 >>>(symmat_gpu,data_gpu);
cudaThreadSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
DATA_TYPE valueAtSymmatIndexMTimesMPlus1PlusMPoint = 1.0;
cudaMemcpy(&(symmat_gpu[(M)*(M+1) + (M)]), &valueAtSymmatIndexMTimesMPlus1PlusMPoint, sizeof(DATA_TYPE), cudaMemcpyHostToDevice);
cudaMemcpy(symmat_outputFromGpu, symmat_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1), cudaMemcpyDeviceToHost);
cudaFree(data_gpu);
cudaFree(symmat_gpu);
cudaFree(stddev_gpu);
cudaFree(mean_gpu);
}
int main()
{
double t_start, t_end;
DATA_TYPE* data;
DATA_TYPE* mean;
DATA_TYPE* stddev;
DATA_TYPE* symmat;
DATA_TYPE* symmat_outputFromGpu;
data = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
mean = (DATA_TYPE*)malloc((M+1)*sizeof(DATA_TYPE));
stddev = (DATA_TYPE*)malloc((M+1)*sizeof(DATA_TYPE));
symmat = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
symmat_outputFromGpu = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
init_arrays(data);
GPU_argv_init();
correlationCuda(data, mean, stddev, symmat, symmat_outputFromGpu);
t_start = rtclock();
correlation(data, mean, stddev, symmat);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(symmat, symmat_outputFromGpu);
free(data);
free(mean);
free(stddev);
free(symmat);
free(symmat_outputFromGpu);
return 0;
} | /**
* correlation.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 1.05
#define GPU_DEVICE 0
/* Problem size */
#define M 2048
#define N 2048
/* Thread block dimensions for kernel 1*/
#define DIM_THREAD_BLOCK_KERNEL_1_X 256
#define DIM_THREAD_BLOCK_KERNEL_1_Y 1
/* Thread block dimensions for kernel 2*/
#define DIM_THREAD_BLOCK_KERNEL_2_X 256
#define DIM_THREAD_BLOCK_KERNEL_2_Y 1
/* Thread block dimensions for kernel 3*/
#define DIM_THREAD_BLOCK_KERNEL_3_X 32
#define DIM_THREAD_BLOCK_KERNEL_3_Y 8
/* Thread block dimensions for kernel 4*/
#define DIM_THREAD_BLOCK_KERNEL_4_X 256
#define DIM_THREAD_BLOCK_KERNEL_4_Y 1
#define sqrt_of_array_cell(x,j) sqrt(x[j])
#define FLOAT_N 3214212.01f
#define EPS 0.005f
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void init_arrays(DATA_TYPE* data)
{
int i, j;
for (i=0; i < (M+1); i++)
{
for (j=0; j< (N+1); j++)
{
data[i*(N+1) + j] = ((DATA_TYPE) i*j)/ (M+1);
}
}
}
void correlation(DATA_TYPE* data, DATA_TYPE* mean, DATA_TYPE* stddev, DATA_TYPE* symmat)
{
int i, j, j1, j2;
// Determine mean of column vectors of input data matrix
for (j = 1; j < (M+1); j++)
{
mean[j] = 0.0;
for (i = 1; i < (N+1); i++)
{
mean[j] += data[i*(M+1) + j];
}
mean[j] /= (DATA_TYPE)FLOAT_N;
}
// Determine standard deviations of column vectors of data matrix.
for (j = 1; j < (M+1); j++)
{
stddev[j] = 0.0;
for (i = 1; i < (N+1); i++)
{
stddev[j] += (data[i*(M+1) + j] - mean[j]) * (data[i*(M+1) + j] - mean[j]);
}
stddev[j] /= FLOAT_N;
stddev[j] = sqrt_of_array_cell(stddev, j);
stddev[j] = stddev[j] <= EPS ? 1.0 : stddev[j];
}
// Center and reduce the column vectors.
for (i = 1; i < (N+1); i++)
{
for (j = 1; j < (M+1); j++)
{
data[i*(M+1) + j] -= mean[j];
data[i*(M+1) + j] /= (sqrt(FLOAT_N)*stddev[j]) ;
}
}
// Calculate the m * m correlation matrix.
for (j1 = 1; j1 < M; j1++)
{
symmat[j1*(M+1) + j1] = 1.0;
for (j2 = j1+1; j2 < (M+1); j2++)
{
symmat[j1*(M+1) + j2] = 0.0;
for (i = 1; i < (N+1); i++)
{
symmat[j1*(M+1) + j2] += (data[i*(M+1) + j1] * data[i*(M+1) + j2]);
}
symmat[j2*(M+1) + j1] = symmat[j1*(M+1) + j2];
}
}
symmat[M*(M+1) + M] = 1.0;
}
void compareResults(DATA_TYPE* symmat, DATA_TYPE* symmat_outputFromGpu)
{
int i,j,fail;
fail = 0;
for (i=1; i < (M+1); i++)
{
for (j=1; j < (N+1); j++)
{
if (percentDiff(symmat[i*(N+1) + j], symmat_outputFromGpu[i*(N+1) + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
printf("i: %d j: %d\n1: %f 2: %f\n", i, j, symmat[i*N + j], symmat_outputFromGpu[i*N + j]);
}
}
}
// print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
hipSetDevice( GPU_DEVICE );
}
__global__ void mean_kernel(DATA_TYPE *mean, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if ((j >= 1) && (j < (M+1)))
{
mean[j] = 0.0;
int i;
for(i=1; i < (N+1); i++)
{
mean[j] += data[i*(M+1) + j];
}
mean[j] /= (DATA_TYPE)FLOAT_N;
}
}
__global__ void std_kernel(DATA_TYPE *mean, DATA_TYPE *std, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if ((j >= 1) && (j < (M+1)))
{
std[j] = 0.0;
int i;
for(i = 1; i < (N+1); i++)
{
std[j] += (data[i*(M+1) + j] - mean[j]) * (data[i*(M+1) + j] - mean[j]);
}
std[j] /= (FLOAT_N);
std[j] = sqrt(std[j]);
if(std[j] <= EPS)
{
std[j] = 1.0;
}
}
}
__global__ void reduce_kernel(DATA_TYPE *mean, DATA_TYPE *std, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i = blockIdx.y * blockDim.y + threadIdx.y + 1;
if ((i >= 1) && (i < (N+1)) && (j >= 1) && (j < (M+1)))
{
data[i*(M+1) + j] -= mean[j];
data[i*(M+1) + j] /= (sqrt(FLOAT_N) * std[j]);
}
}
__global__ void corr_kernel(DATA_TYPE *symmat, DATA_TYPE *data)
{
int j1 = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i, j2;
if ((j1 >= 1) && (j1 < M))
{
symmat[j1*(M+1) + j1] = 1.0;
for (j2 = (j1 + 1); j2 < (M+1); j2++)
{
symmat[j1*(M+1) + j2] = 0.0;
for(i = 1; i < (N+1); i++)
{
symmat[j1*(M+1) + j2] += data[i*(M+1) + j1] * data[i*(M+1) + j2];
}
symmat[j2*(M+1) + j1] = symmat[j1*(M+1) + j2];
}
}
}
void correlationCuda(DATA_TYPE* data, DATA_TYPE* mean, DATA_TYPE* stddev, DATA_TYPE* symmat,
DATA_TYPE* symmat_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *data_gpu;
DATA_TYPE *stddev_gpu;
DATA_TYPE *mean_gpu;
DATA_TYPE *symmat_gpu;
hipMalloc((void **)&data_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1));
hipMalloc((void **)&symmat_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1));
hipMalloc((void **)&stddev_gpu, sizeof(DATA_TYPE) * (M+1));
hipMalloc((void **)&mean_gpu, sizeof(DATA_TYPE) * (M+1));
hipMemcpy(data_gpu, data, sizeof(DATA_TYPE) * (M+1) * (N+1), hipMemcpyHostToDevice);
hipMemcpy(symmat_gpu, symmat, sizeof(DATA_TYPE) * (M+1) * (N+1), hipMemcpyHostToDevice);
hipMemcpy(stddev_gpu, stddev, sizeof(DATA_TYPE) * (M+1), hipMemcpyHostToDevice);
hipMemcpy(mean_gpu, mean, sizeof(DATA_TYPE) * (M+1), hipMemcpyHostToDevice);
dim3 block1(DIM_THREAD_BLOCK_KERNEL_1_X, DIM_THREAD_BLOCK_KERNEL_1_Y);
dim3 grid1((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_1_X)), 1);
dim3 block2(DIM_THREAD_BLOCK_KERNEL_2_X, DIM_THREAD_BLOCK_KERNEL_2_Y);
dim3 grid2((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_2_X)), 1);
dim3 block3(DIM_THREAD_BLOCK_KERNEL_3_X, DIM_THREAD_BLOCK_KERNEL_3_Y);
dim3 grid3((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_3_X)), (size_t)(ceil((float)(N)) / ((float)DIM_THREAD_BLOCK_KERNEL_3_Y)));
dim3 block4(DIM_THREAD_BLOCK_KERNEL_4_X, DIM_THREAD_BLOCK_KERNEL_4_Y);
dim3 grid4((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_4_X)), 1);
t_start = rtclock();
mean_kernel<<< grid1, block1 >>>(mean_gpu,data_gpu);
hipDeviceSynchronize();
std_kernel<<< grid2, block2 >>>(mean_gpu,stddev_gpu,data_gpu);
hipDeviceSynchronize();
reduce_kernel<<< grid3, block3 >>>(mean_gpu,stddev_gpu,data_gpu);
hipDeviceSynchronize();
corr_kernel<<< grid4, block4 >>>(symmat_gpu,data_gpu);
hipDeviceSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
DATA_TYPE valueAtSymmatIndexMTimesMPlus1PlusMPoint = 1.0;
hipMemcpy(&(symmat_gpu[(M)*(M+1) + (M)]), &valueAtSymmatIndexMTimesMPlus1PlusMPoint, sizeof(DATA_TYPE), hipMemcpyHostToDevice);
hipMemcpy(symmat_outputFromGpu, symmat_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1), hipMemcpyDeviceToHost);
hipFree(data_gpu);
hipFree(symmat_gpu);
hipFree(stddev_gpu);
hipFree(mean_gpu);
}
int main()
{
double t_start, t_end;
DATA_TYPE* data;
DATA_TYPE* mean;
DATA_TYPE* stddev;
DATA_TYPE* symmat;
DATA_TYPE* symmat_outputFromGpu;
data = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
mean = (DATA_TYPE*)malloc((M+1)*sizeof(DATA_TYPE));
stddev = (DATA_TYPE*)malloc((M+1)*sizeof(DATA_TYPE));
symmat = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
symmat_outputFromGpu = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
init_arrays(data);
GPU_argv_init();
correlationCuda(data, mean, stddev, symmat, symmat_outputFromGpu);
t_start = rtclock();
correlation(data, mean, stddev, symmat);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(symmat, symmat_outputFromGpu);
free(data);
free(mean);
free(stddev);
free(symmat);
free(symmat_outputFromGpu);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* correlation.cu: This file is part of the PolyBench/GPU 1.0 test suite.
*
*
* Contact: Scott Grauer-Gray <sgrauerg@gmail.com>
* Louis-Noel Pouchet <pouchet@cse.ohio-state.edu>
* Web address: http://www.cse.ohio-state.edu/~pouchet/software/polybench/GPU
*/
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <assert.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
#include "../../common/polybenchUtilFuncts.h"
//define the error threshold for the results "not matching"
#define PERCENT_DIFF_ERROR_THRESHOLD 1.05
#define GPU_DEVICE 0
/* Problem size */
#define M 2048
#define N 2048
/* Thread block dimensions for kernel 1*/
#define DIM_THREAD_BLOCK_KERNEL_1_X 256
#define DIM_THREAD_BLOCK_KERNEL_1_Y 1
/* Thread block dimensions for kernel 2*/
#define DIM_THREAD_BLOCK_KERNEL_2_X 256
#define DIM_THREAD_BLOCK_KERNEL_2_Y 1
/* Thread block dimensions for kernel 3*/
#define DIM_THREAD_BLOCK_KERNEL_3_X 32
#define DIM_THREAD_BLOCK_KERNEL_3_Y 8
/* Thread block dimensions for kernel 4*/
#define DIM_THREAD_BLOCK_KERNEL_4_X 256
#define DIM_THREAD_BLOCK_KERNEL_4_Y 1
#define sqrt_of_array_cell(x,j) sqrt(x[j])
#define FLOAT_N 3214212.01f
#define EPS 0.005f
/* Can switch DATA_TYPE between float and double */
typedef float DATA_TYPE;
void init_arrays(DATA_TYPE* data)
{
int i, j;
for (i=0; i < (M+1); i++)
{
for (j=0; j< (N+1); j++)
{
data[i*(N+1) + j] = ((DATA_TYPE) i*j)/ (M+1);
}
}
}
void correlation(DATA_TYPE* data, DATA_TYPE* mean, DATA_TYPE* stddev, DATA_TYPE* symmat)
{
int i, j, j1, j2;
// Determine mean of column vectors of input data matrix
for (j = 1; j < (M+1); j++)
{
mean[j] = 0.0;
for (i = 1; i < (N+1); i++)
{
mean[j] += data[i*(M+1) + j];
}
mean[j] /= (DATA_TYPE)FLOAT_N;
}
// Determine standard deviations of column vectors of data matrix.
for (j = 1; j < (M+1); j++)
{
stddev[j] = 0.0;
for (i = 1; i < (N+1); i++)
{
stddev[j] += (data[i*(M+1) + j] - mean[j]) * (data[i*(M+1) + j] - mean[j]);
}
stddev[j] /= FLOAT_N;
stddev[j] = sqrt_of_array_cell(stddev, j);
stddev[j] = stddev[j] <= EPS ? 1.0 : stddev[j];
}
// Center and reduce the column vectors.
for (i = 1; i < (N+1); i++)
{
for (j = 1; j < (M+1); j++)
{
data[i*(M+1) + j] -= mean[j];
data[i*(M+1) + j] /= (sqrt(FLOAT_N)*stddev[j]) ;
}
}
// Calculate the m * m correlation matrix.
for (j1 = 1; j1 < M; j1++)
{
symmat[j1*(M+1) + j1] = 1.0;
for (j2 = j1+1; j2 < (M+1); j2++)
{
symmat[j1*(M+1) + j2] = 0.0;
for (i = 1; i < (N+1); i++)
{
symmat[j1*(M+1) + j2] += (data[i*(M+1) + j1] * data[i*(M+1) + j2]);
}
symmat[j2*(M+1) + j1] = symmat[j1*(M+1) + j2];
}
}
symmat[M*(M+1) + M] = 1.0;
}
void compareResults(DATA_TYPE* symmat, DATA_TYPE* symmat_outputFromGpu)
{
int i,j,fail;
fail = 0;
for (i=1; i < (M+1); i++)
{
for (j=1; j < (N+1); j++)
{
if (percentDiff(symmat[i*(N+1) + j], symmat_outputFromGpu[i*(N+1) + j]) > PERCENT_DIFF_ERROR_THRESHOLD)
{
fail++;
printf("i: %d j: %d\n1: %f 2: %f\n", i, j, symmat[i*N + j], symmat_outputFromGpu[i*N + j]);
}
}
}
// print results
printf("Non-Matching CPU-GPU Outputs Beyond Error Threshold of %4.2f Percent: %d\n", PERCENT_DIFF_ERROR_THRESHOLD, fail);
}
void GPU_argv_init()
{
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, GPU_DEVICE);
printf("setting device %d with name %s\n",GPU_DEVICE,deviceProp.name);
hipSetDevice( GPU_DEVICE );
}
__global__ void mean_kernel(DATA_TYPE *mean, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if ((j >= 1) && (j < (M+1)))
{
mean[j] = 0.0;
int i;
for(i=1; i < (N+1); i++)
{
mean[j] += data[i*(M+1) + j];
}
mean[j] /= (DATA_TYPE)FLOAT_N;
}
}
__global__ void std_kernel(DATA_TYPE *mean, DATA_TYPE *std, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
if ((j >= 1) && (j < (M+1)))
{
std[j] = 0.0;
int i;
for(i = 1; i < (N+1); i++)
{
std[j] += (data[i*(M+1) + j] - mean[j]) * (data[i*(M+1) + j] - mean[j]);
}
std[j] /= (FLOAT_N);
std[j] = sqrt(std[j]);
if(std[j] <= EPS)
{
std[j] = 1.0;
}
}
}
__global__ void reduce_kernel(DATA_TYPE *mean, DATA_TYPE *std, DATA_TYPE *data)
{
int j = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i = blockIdx.y * blockDim.y + threadIdx.y + 1;
if ((i >= 1) && (i < (N+1)) && (j >= 1) && (j < (M+1)))
{
data[i*(M+1) + j] -= mean[j];
data[i*(M+1) + j] /= (sqrt(FLOAT_N) * std[j]);
}
}
__global__ void corr_kernel(DATA_TYPE *symmat, DATA_TYPE *data)
{
int j1 = blockIdx.x * blockDim.x + threadIdx.x + 1;
int i, j2;
if ((j1 >= 1) && (j1 < M))
{
symmat[j1*(M+1) + j1] = 1.0;
for (j2 = (j1 + 1); j2 < (M+1); j2++)
{
symmat[j1*(M+1) + j2] = 0.0;
for(i = 1; i < (N+1); i++)
{
symmat[j1*(M+1) + j2] += data[i*(M+1) + j1] * data[i*(M+1) + j2];
}
symmat[j2*(M+1) + j1] = symmat[j1*(M+1) + j2];
}
}
}
void correlationCuda(DATA_TYPE* data, DATA_TYPE* mean, DATA_TYPE* stddev, DATA_TYPE* symmat,
DATA_TYPE* symmat_outputFromGpu)
{
double t_start, t_end;
DATA_TYPE *data_gpu;
DATA_TYPE *stddev_gpu;
DATA_TYPE *mean_gpu;
DATA_TYPE *symmat_gpu;
hipMalloc((void **)&data_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1));
hipMalloc((void **)&symmat_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1));
hipMalloc((void **)&stddev_gpu, sizeof(DATA_TYPE) * (M+1));
hipMalloc((void **)&mean_gpu, sizeof(DATA_TYPE) * (M+1));
hipMemcpy(data_gpu, data, sizeof(DATA_TYPE) * (M+1) * (N+1), hipMemcpyHostToDevice);
hipMemcpy(symmat_gpu, symmat, sizeof(DATA_TYPE) * (M+1) * (N+1), hipMemcpyHostToDevice);
hipMemcpy(stddev_gpu, stddev, sizeof(DATA_TYPE) * (M+1), hipMemcpyHostToDevice);
hipMemcpy(mean_gpu, mean, sizeof(DATA_TYPE) * (M+1), hipMemcpyHostToDevice);
dim3 block1(DIM_THREAD_BLOCK_KERNEL_1_X, DIM_THREAD_BLOCK_KERNEL_1_Y);
dim3 grid1((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_1_X)), 1);
dim3 block2(DIM_THREAD_BLOCK_KERNEL_2_X, DIM_THREAD_BLOCK_KERNEL_2_Y);
dim3 grid2((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_2_X)), 1);
dim3 block3(DIM_THREAD_BLOCK_KERNEL_3_X, DIM_THREAD_BLOCK_KERNEL_3_Y);
dim3 grid3((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_3_X)), (size_t)(ceil((float)(N)) / ((float)DIM_THREAD_BLOCK_KERNEL_3_Y)));
dim3 block4(DIM_THREAD_BLOCK_KERNEL_4_X, DIM_THREAD_BLOCK_KERNEL_4_Y);
dim3 grid4((size_t)(ceil((float)(M)) / ((float)DIM_THREAD_BLOCK_KERNEL_4_X)), 1);
t_start = rtclock();
mean_kernel<<< grid1, block1 >>>(mean_gpu,data_gpu);
hipDeviceSynchronize();
std_kernel<<< grid2, block2 >>>(mean_gpu,stddev_gpu,data_gpu);
hipDeviceSynchronize();
reduce_kernel<<< grid3, block3 >>>(mean_gpu,stddev_gpu,data_gpu);
hipDeviceSynchronize();
corr_kernel<<< grid4, block4 >>>(symmat_gpu,data_gpu);
hipDeviceSynchronize();
t_end = rtclock();
fprintf(stdout, "GPU Runtime: %0.6lfs\n", t_end - t_start);
DATA_TYPE valueAtSymmatIndexMTimesMPlus1PlusMPoint = 1.0;
hipMemcpy(&(symmat_gpu[(M)*(M+1) + (M)]), &valueAtSymmatIndexMTimesMPlus1PlusMPoint, sizeof(DATA_TYPE), hipMemcpyHostToDevice);
hipMemcpy(symmat_outputFromGpu, symmat_gpu, sizeof(DATA_TYPE) * (M+1) * (N+1), hipMemcpyDeviceToHost);
hipFree(data_gpu);
hipFree(symmat_gpu);
hipFree(stddev_gpu);
hipFree(mean_gpu);
}
int main()
{
double t_start, t_end;
DATA_TYPE* data;
DATA_TYPE* mean;
DATA_TYPE* stddev;
DATA_TYPE* symmat;
DATA_TYPE* symmat_outputFromGpu;
data = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
mean = (DATA_TYPE*)malloc((M+1)*sizeof(DATA_TYPE));
stddev = (DATA_TYPE*)malloc((M+1)*sizeof(DATA_TYPE));
symmat = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
symmat_outputFromGpu = (DATA_TYPE*)malloc((M+1)*(N+1)*sizeof(DATA_TYPE));
init_arrays(data);
GPU_argv_init();
correlationCuda(data, mean, stddev, symmat, symmat_outputFromGpu);
t_start = rtclock();
correlation(data, mean, stddev, symmat);
t_end = rtclock();
fprintf(stdout, "CPU Runtime: %0.6lfs\n", t_end - t_start);
compareResults(symmat, symmat_outputFromGpu);
free(data);
free(mean);
free(stddev);
free(symmat);
free(symmat_outputFromGpu);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11mean_kernelPfS_
.globl _Z11mean_kernelPfS_
.p2align 8
.type _Z11mean_kernelPfS_,@function
_Z11mean_kernelPfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x800, v1
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
v_dual_mov_b32 v5, 0 :: v_dual_add_nc_u32 v4, 1, v1
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_movk_i32 s0, 0x802
global_store_b32 v[2:3], v5, off
.LBB0_2:
v_add_nc_u32_e32 v4, s0, v1
s_addk_i32 s0, 0x801
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0x401002
v_lshlrev_b64 v[6:7], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_load_b32 v4, v[6:7], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_cbranch_scc1 .LBB0_2
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v1, null, 0x4a442e10, 0x4a442e10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v1, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v0, 0x4a442e10, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v5, v4
v_fma_f32 v7, -v1, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v7, v4
v_fma_f32 v1, -v1, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v1, v1, v4, v6
v_div_fixup_f32 v0, v1, 0x4a442e10, v0
global_store_b32 v[2:3], v0, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11mean_kernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11mean_kernelPfS_, .Lfunc_end0-_Z11mean_kernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10std_kernelPfS_S_
.globl _Z10std_kernelPfS_S_
.p2align 8
.type _Z10std_kernelPfS_S_,@function
_Z10std_kernelPfS_S_:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e32 0x800, v2
s_cbranch_execz .LBB1_4
s_load_b128 s[4:7], s[0:1], 0x0
v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, 1, v2
s_load_b64 s[0:1], s[0:1], 0x10
s_movk_i32 s2, 0x802
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v6, vcc_lo
v_add_co_u32 v5, vcc_lo, s4, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
global_store_b32 v[0:1], v4, off
.p2align 6
.LBB1_2:
v_add_nc_u32_e32 v3, s2, v2
s_addk_i32 s2, 0x801
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s2, 0x401002
v_lshlrev_b64 v[7:8], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s0, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s1, v8, vcc_lo
global_load_b32 v3, v[5:6], off
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[0:1], off
s_waitcnt vmcnt(1)
v_sub_f32_e32 v3, v7, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v8, v3, v3
global_store_b32 v[0:1], v8, off
s_cbranch_scc1 .LBB1_2
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_div_scale_f32 v3, null, 0x4a442e10, 0x4a442e10, v2
v_div_scale_f32 v6, vcc_lo, v2, 0x4a442e10, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v5
v_div_fixup_f32 v2, v3, 0x4a442e10, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v3, 0x4f800000, v2
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v2
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v4, -1, v3
v_add_nc_u32_e32 v5, 1, v3
v_fma_f32 v6, -v4, v3, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, -v5, v3, v2
v_cmp_ge_f32_e64 s0, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v3, v3, v4, s0
v_cmp_lt_f32_e64 s0, 0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v3, v3, v5, s0
v_mul_f32_e32 v4, 0x37800000, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v2, 0x260
v_cndmask_b32_e32 v2, v3, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmp_nge_f32_e32 vcc_lo, 0x3ba3d70a, v2
v_cndmask_b32_e32 v2, 1.0, v2, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10std_kernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10std_kernelPfS_S_, .Lfunc_end1-_Z10std_kernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13reduce_kernelPfS_S_
.globl _Z13reduce_kernelPfS_S_
.p2align 8
.type _Z13reduce_kernelPfS_S_,@function
_Z13reduce_kernelPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_or_b32_e32 v2, v1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e32 0x800, v2
s_cbranch_execz .LBB2_2
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, 1, v0
v_lshl_add_u32 v1, v1, 11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add3_u32 v2, v0, v1, 0x802
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_sub_f32_e32 v6, v3, v2
v_add_co_u32 v2, vcc_lo, s6, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
global_store_b32 v[0:1], v6, off
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v2, 0x44e01a51, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_scale_f32 v3, null, v2, v2, v6
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v6, v2, v6
v_mul_f32_e32 v7, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, -v3, v7, v5
v_fmac_f32_e32 v7, v8, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v7, v5
v_div_fmas_f32 v3, v3, v4, v7
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v3, v2, v6
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13reduce_kernelPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z13reduce_kernelPfS_S_, .Lfunc_end2-_Z13reduce_kernelPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11corr_kernelPfS_
.globl _Z11corr_kernelPfS_
.p2align 8
.type _Z11corr_kernelPfS_,@function
_Z11corr_kernelPfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mul_i32 s15, s15, s2
s_mov_b32 s2, exec_lo
v_add_nc_u32_e32 v10, s15, v0
v_cmpx_gt_u32_e32 0x7ff, v10
s_cbranch_execz .LBB3_5
v_dual_mov_b32 v8, 1.0 :: v_dual_add_nc_u32 v1, 1, v10
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v3, 0
v_add_nc_u32_e32 v11, 2, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v1, 0x802
s_mov_b32 s1, 0
v_lshlrev_b64 v[4:5], 2, v[2:3]
v_add3_u32 v2, v0, s15, 0x803
v_lshl_add_u32 v0, v1, 11, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v6, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
v_mov_b32_e32 v5, 0
global_store_b32 v[6:7], v8, off
.LBB3_2:
v_add_nc_u32_e32 v4, v11, v0
v_dual_mov_b32 v9, v3 :: v_dual_mov_b32 v8, v2
v_mov_b32_e32 v12, v5
s_movk_i32 s0, 0x802
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], 2, v[4:5]
v_add_co_u32 v6, vcc_lo, s4, v6
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
global_store_b32 v[6:7], v5, off
.p2align 6
.LBB3_3:
v_add_nc_u32_e32 v4, s0, v10
s_addk_i32 s0, 0x801
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0x401002
v_lshlrev_b64 v[13:14], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v13, vcc_lo, s6, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
global_load_b32 v4, v[8:9], off
global_load_b32 v13, v[13:14], off
v_add_co_u32 v8, vcc_lo, v8, 0x2004
v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v12, v13, v4
global_store_b32 v[6:7], v12, off
s_cbranch_scc1 .LBB3_3
global_load_b32 v4, v[6:7], off
v_mad_u64_u32 v[6:7], null, v11, 0x801, v[1:2]
v_dual_mov_b32 v7, v5 :: v_dual_add_nc_u32 v8, 1, v11
v_add_co_u32 v2, s0, v2, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
v_lshlrev_b64 v[6:7], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v6, vcc_lo, s4, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
v_cmp_lt_i32_e32 vcc_lo, 0x7ff, v11
v_mov_b32_e32 v11, v8
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(0)
global_store_b32 v[6:7], v4, off
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB3_2
.LBB3_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11corr_kernelPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z11corr_kernelPfS_, .Lfunc_end3-_Z11corr_kernelPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11mean_kernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11mean_kernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10std_kernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10std_kernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13reduce_kernelPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13reduce_kernelPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11corr_kernelPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11corr_kernelPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.