system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void update_bins(float *vec, int *bin, int *bin_counters, const int num_bins, const int n, const float slope, const float intercept)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int bin_new_val;
float temp = abs(vec[xIndex]);
if ( temp > (intercept *.000001) ){
bin_new_val=slope * (intercept - temp);
}
else bin_new_val = num_bins;
if ( bin[xIndex] != bin_new_val ){
if (bin[xIndex] < num_bins)
atomicAdd(bin_counters+bin[xIndex],-1);
if ( bin_new_val < num_bins )
atomicAdd(bin_counters+bin[xIndex],1);
bin[xIndex]=bin_new_val;
}
}
} | code for sm_80
Function : _Z11update_binsPfPiS0_iiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e000b */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*00b0*/ LEA.HI.X R3, R0, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f14ff */
/*00c0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ F2F.F64.F32 R8, c[0x0][0x184] ; /* 0x0000610000087b10 */
/* 0x000e240000201800 */
/*00e0*/ DMUL R8, R8, c[0x2][0x0] ; /* 0x0080000008087a28 */
/* 0x001e0c0000000000 */
/*00f0*/ F2F.F64.F32 R6, |R4| ; /* 0x4000000400067310 */
/* 0x004e240000201800 */
/*0100*/ DSETP.GEU.AND P0, PT, R8, R6, PT ; /* 0x000000060800722a */
/* 0x0010640003f0e000 */
/*0110*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x001fd80000000f00 */
/*0120*/ @!P0 FADD R0, -|R4|, c[0x0][0x184] ; /* 0x0000610004008621 */
/* 0x002fc80000000300 */
/*0130*/ @!P0 FMUL R0, R0, c[0x0][0x180] ; /* 0x0000600000008a20 */
/* 0x000fc80000400000 */
/*0140*/ @!P0 F2I.TRUNC.NTZ R7, R0 ; /* 0x0000000000078305 */
/* 0x000ee4000020f100 */
/*0150*/ ISETP.NE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x008fda0003f05270 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GE.AND P1, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */
/* 0x000fe20003f26270 */
/*0180*/ BSSY B0, 0x210 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0190*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fd60003f06270 */
/*01a0*/ @P1 BRA 0x200 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*01b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R10 ; /* 0x0000001fff057819 */
/* 0x000fe2000001140a */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, -0x1 ; /* 0xffffffffff097424 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA R4, P1, R10, c[0x0][0x170], 0x2 ; /* 0x00005c000a047a11 */
/* 0x000fc800078210ff */
/*01e0*/ LEA.HI.X R5, R10, c[0x0][0x174], R5, 0x2, P1 ; /* 0x00005d000a057a11 */
/* 0x000fca00008f1405 */
/*01f0*/ RED.E.ADD.STRONG.GPU [R4.64], R9 ; /* 0x000000090400798e */
/* 0x0001e8000c10e184 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ BSSY B0, 0x280 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0220*/ @P0 BRA 0x270 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0230*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x001ea2000c1e1900 */
/*0240*/ HFMA2.MMA R9, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff097435 */
/* 0x000fe200000001ff */
/*0250*/ IMAD.WIDE R4, R4, R11, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x004fcc00078e020b */
/*0260*/ RED.E.ADD.STRONG.GPU [R4.64], R9 ; /* 0x000000090400798e */
/* 0x0001e8000c10e184 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void update_bins(float *vec, int *bin, int *bin_counters, const int num_bins, const int n, const float slope, const float intercept)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int bin_new_val;
float temp = abs(vec[xIndex]);
if ( temp > (intercept *.000001) ){
bin_new_val=slope * (intercept - temp);
}
else bin_new_val = num_bins;
if ( bin[xIndex] != bin_new_val ){
if (bin[xIndex] < num_bins)
atomicAdd(bin_counters+bin[xIndex],-1);
if ( bin_new_val < num_bins )
atomicAdd(bin_counters+bin[xIndex],1);
bin[xIndex]=bin_new_val;
}
}
} | .file "tmpxft_00114954_00000000-6_update_bins.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff
.type _Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff, @function
_Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11update_binsPfPiS0_iiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff, .-_Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff
.globl _Z11update_binsPfPiS0_iiff
.type _Z11update_binsPfPiS0_iiff, @function
_Z11update_binsPfPiS0_iiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11update_binsPfPiS0_iiff, .-_Z11update_binsPfPiS0_iiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11update_binsPfPiS0_iiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11update_binsPfPiS0_iiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void update_bins(float *vec, int *bin, int *bin_counters, const int num_bins, const int n, const float slope, const float intercept)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int bin_new_val;
float temp = abs(vec[xIndex]);
if ( temp > (intercept *.000001) ){
bin_new_val=slope * (intercept - temp);
}
else bin_new_val = num_bins;
if ( bin[xIndex] != bin_new_val ){
if (bin[xIndex] < num_bins)
atomicAdd(bin_counters+bin[xIndex],-1);
if ( bin_new_val < num_bins )
atomicAdd(bin_counters+bin[xIndex],1);
bin[xIndex]=bin_new_val;
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_bins(float *vec, int *bin, int *bin_counters, const int num_bins, const int n, const float slope, const float intercept)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int bin_new_val;
float temp = abs(vec[xIndex]);
if ( temp > (intercept *.000001) ){
bin_new_val=slope * (intercept - temp);
}
else bin_new_val = num_bins;
if ( bin[xIndex] != bin_new_val ){
if (bin[xIndex] < num_bins)
atomicAdd(bin_counters+bin[xIndex],-1);
if ( bin_new_val < num_bins )
atomicAdd(bin_counters+bin[xIndex],1);
bin[xIndex]=bin_new_val;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_bins(float *vec, int *bin, int *bin_counters, const int num_bins, const int n, const float slope, const float intercept)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int bin_new_val;
float temp = abs(vec[xIndex]);
if ( temp > (intercept *.000001) ){
bin_new_val=slope * (intercept - temp);
}
else bin_new_val = num_bins;
if ( bin[xIndex] != bin_new_val ){
if (bin[xIndex] < num_bins)
atomicAdd(bin_counters+bin[xIndex],-1);
if ( bin_new_val < num_bins )
atomicAdd(bin_counters+bin[xIndex],1);
bin[xIndex]=bin_new_val;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11update_binsPfPiS0_iiff
.globl _Z11update_binsPfPiS0_iiff
.p2align 8
.type _Z11update_binsPfPiS0_iiff,@function
_Z11update_binsPfPiS0_iiff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v7, v[2:3], off
s_load_b64 s[4:5], s[0:1], 0x20
s_mov_b32 s7, 0x3eb0c6f7
global_load_b32 v2, v[0:1], off
s_mov_b32 s6, 0xa0b5ed8d
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[3:4], s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], s[6:7]
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e64 v[5:6], |v7|
v_sub_f32_e64 v7, s5, |v7|
v_mul_f32_e32 v7, s4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v7, v7
v_cmp_lt_f64_e32 vcc_lo, v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, s2, v7, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v2, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_atomic_add_u32 v[2:3], v5, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_i32_e32 vcc_lo, s2, v4
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
global_load_b32 v2, v[0:1], off
v_mov_b32_e32 v5, 1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_atomic_add_u32 v[2:3], v5, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
global_store_b32 v[0:1], v4, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11update_binsPfPiS0_iiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11update_binsPfPiS0_iiff, .Lfunc_end0-_Z11update_binsPfPiS0_iiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11update_binsPfPiS0_iiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11update_binsPfPiS0_iiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void update_bins(float *vec, int *bin, int *bin_counters, const int num_bins, const int n, const float slope, const float intercept)
{
unsigned int xIndex = blockDim.x * blockIdx.x + threadIdx.x;
if ( xIndex < n ){
int bin_new_val;
float temp = abs(vec[xIndex]);
if ( temp > (intercept *.000001) ){
bin_new_val=slope * (intercept - temp);
}
else bin_new_val = num_bins;
if ( bin[xIndex] != bin_new_val ){
if (bin[xIndex] < num_bins)
atomicAdd(bin_counters+bin[xIndex],-1);
if ( bin_new_val < num_bins )
atomicAdd(bin_counters+bin[xIndex],1);
bin[xIndex]=bin_new_val;
}
}
} | .text
.file "update_bins.hip"
.globl _Z26__device_stub__update_binsPfPiS0_iiff # -- Begin function _Z26__device_stub__update_binsPfPiS0_iiff
.p2align 4, 0x90
.type _Z26__device_stub__update_binsPfPiS0_iiff,@function
_Z26__device_stub__update_binsPfPiS0_iiff: # @_Z26__device_stub__update_binsPfPiS0_iiff
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11update_binsPfPiS0_iiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__update_binsPfPiS0_iiff, .Lfunc_end0-_Z26__device_stub__update_binsPfPiS0_iiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11update_binsPfPiS0_iiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11update_binsPfPiS0_iiff,@object # @_Z11update_binsPfPiS0_iiff
.section .rodata,"a",@progbits
.globl _Z11update_binsPfPiS0_iiff
.p2align 3, 0x0
_Z11update_binsPfPiS0_iiff:
.quad _Z26__device_stub__update_binsPfPiS0_iiff
.size _Z11update_binsPfPiS0_iiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11update_binsPfPiS0_iiff"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__update_binsPfPiS0_iiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11update_binsPfPiS0_iiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11update_binsPfPiS0_iiff
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x17c], PT ; /* 0x00005f0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE.U32 R4, R0, R11, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fcc00078e000b */
/*0090*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ LEA R2, P0, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fc800078010ff */
/*00b0*/ LEA.HI.X R3, R0, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0000037a11 */
/* 0x000fca00000f14ff */
/*00c0*/ LDG.E R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ee2000c1e1900 */
/*00d0*/ F2F.F64.F32 R8, c[0x0][0x184] ; /* 0x0000610000087b10 */
/* 0x000e240000201800 */
/*00e0*/ DMUL R8, R8, c[0x2][0x0] ; /* 0x0080000008087a28 */
/* 0x001e0c0000000000 */
/*00f0*/ F2F.F64.F32 R6, |R4| ; /* 0x4000000400067310 */
/* 0x004e240000201800 */
/*0100*/ DSETP.GEU.AND P0, PT, R8, R6, PT ; /* 0x000000060800722a */
/* 0x0010640003f0e000 */
/*0110*/ MOV R7, c[0x0][0x178] ; /* 0x00005e0000077a02 */
/* 0x001fd80000000f00 */
/*0120*/ @!P0 FADD R0, -|R4|, c[0x0][0x184] ; /* 0x0000610004008621 */
/* 0x002fc80000000300 */
/*0130*/ @!P0 FMUL R0, R0, c[0x0][0x180] ; /* 0x0000600000008a20 */
/* 0x000fc80000400000 */
/*0140*/ @!P0 F2I.TRUNC.NTZ R7, R0 ; /* 0x0000000000078305 */
/* 0x000ee4000020f100 */
/*0150*/ ISETP.NE.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x008fda0003f05270 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ ISETP.GE.AND P1, PT, R10, c[0x0][0x178], PT ; /* 0x00005e000a007a0c */
/* 0x000fe20003f26270 */
/*0180*/ BSSY B0, 0x210 ; /* 0x0000008000007945 */
/* 0x000fe20003800000 */
/*0190*/ ISETP.GE.AND P0, PT, R7, c[0x0][0x178], PT ; /* 0x00005e0007007a0c */
/* 0x000fd60003f06270 */
/*01a0*/ @P1 BRA 0x200 ; /* 0x0000005000001947 */
/* 0x000fea0003800000 */
/*01b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R10 ; /* 0x0000001fff057819 */
/* 0x000fe2000001140a */
/*01c0*/ IMAD.MOV.U32 R9, RZ, RZ, -0x1 ; /* 0xffffffffff097424 */
/* 0x000fe200078e00ff */
/*01d0*/ LEA R4, P1, R10, c[0x0][0x170], 0x2 ; /* 0x00005c000a047a11 */
/* 0x000fc800078210ff */
/*01e0*/ LEA.HI.X R5, R10, c[0x0][0x174], R5, 0x2, P1 ; /* 0x00005d000a057a11 */
/* 0x000fca00008f1405 */
/*01f0*/ RED.E.ADD.STRONG.GPU [R4.64], R9 ; /* 0x000000090400798e */
/* 0x0001e8000c10e184 */
/*0200*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0210*/ BSSY B0, 0x280 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0220*/ @P0 BRA 0x270 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0230*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x001ea2000c1e1900 */
/*0240*/ HFMA2.MMA R9, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff097435 */
/* 0x000fe200000001ff */
/*0250*/ IMAD.WIDE R4, R4, R11, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x004fcc00078e020b */
/*0260*/ RED.E.ADD.STRONG.GPU [R4.64], R9 ; /* 0x000000090400798e */
/* 0x0001e8000c10e184 */
/*0270*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0280*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x000fe2000c101904 */
/*0290*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*02a0*/ BRA 0x2a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0300*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11update_binsPfPiS0_iiff
.globl _Z11update_binsPfPiS0_iiff
.p2align 8
.type _Z11update_binsPfPiS0_iiff,@function
_Z11update_binsPfPiS0_iiff:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s2, s[0:1], 0x18
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v7, v[2:3], off
s_load_b64 s[4:5], s[0:1], 0x20
s_mov_b32 s7, 0x3eb0c6f7
global_load_b32 v2, v[0:1], off
s_mov_b32 s6, 0xa0b5ed8d
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[3:4], s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_mul_f64 v[3:4], v[3:4], s[6:7]
s_waitcnt vmcnt(1)
v_cvt_f64_f32_e64 v[5:6], |v7|
v_sub_f32_e64 v7, s5, |v7|
v_mul_f32_e32 v7, s4, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cvt_i32_f32_e32 v7, v7
v_cmp_lt_f64_e32 vcc_lo, v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, s2, v7, vcc_lo
s_waitcnt vmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, v2, v4
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_7
s_load_b64 s[0:1], s[0:1], 0x10
s_mov_b32 s3, exec_lo
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_4
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v5, -1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_atomic_add_u32 v[2:3], v5, off
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s3
v_cmp_gt_i32_e32 vcc_lo, s2, v4
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_6
global_load_b32 v2, v[0:1], off
v_mov_b32_e32 v5, 1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_atomic_add_u32 v[2:3], v5, off
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s2
global_store_b32 v[0:1], v4, off
.LBB0_7:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11update_binsPfPiS0_iiff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11update_binsPfPiS0_iiff, .Lfunc_end0-_Z11update_binsPfPiS0_iiff
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11update_binsPfPiS0_iiff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11update_binsPfPiS0_iiff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00114954_00000000-6_update_bins.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff
.type _Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff, @function
_Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z11update_binsPfPiS0_iiff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff, .-_Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff
.globl _Z11update_binsPfPiS0_iiff
.type _Z11update_binsPfPiS0_iiff, @function
_Z11update_binsPfPiS0_iiff:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z11update_binsPfPiS0_iiffPfPiS0_iiff
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11update_binsPfPiS0_iiff, .-_Z11update_binsPfPiS0_iiff
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11update_binsPfPiS0_iiff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11update_binsPfPiS0_iiff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "update_bins.hip"
.globl _Z26__device_stub__update_binsPfPiS0_iiff # -- Begin function _Z26__device_stub__update_binsPfPiS0_iiff
.p2align 4, 0x90
.type _Z26__device_stub__update_binsPfPiS0_iiff,@function
_Z26__device_stub__update_binsPfPiS0_iiff: # @_Z26__device_stub__update_binsPfPiS0_iiff
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11update_binsPfPiS0_iiff, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z26__device_stub__update_binsPfPiS0_iiff, .Lfunc_end0-_Z26__device_stub__update_binsPfPiS0_iiff
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11update_binsPfPiS0_iiff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11update_binsPfPiS0_iiff,@object # @_Z11update_binsPfPiS0_iiff
.section .rodata,"a",@progbits
.globl _Z11update_binsPfPiS0_iiff
.p2align 3, 0x0
_Z11update_binsPfPiS0_iiff:
.quad _Z26__device_stub__update_binsPfPiS0_iiff
.size _Z11update_binsPfPiS0_iiff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11update_binsPfPiS0_iiff"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__update_binsPfPiS0_iiff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11update_binsPfPiS0_iiff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
int main(int argc, char ** argv) {
int deviceCount;
cudaGetDeviceCount(&deviceCount);
for (int dev = 0; dev < deviceCount; dev++) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
// Ne detecte pas CUDA
return -1;
} else {
// Afficher le nombre de device
}
}
// Afficher le nom de la device
// Donner le numero de version majeur et mineur
// Donner la taille de la memoire globale
// Donner la taille de la memoire constante
// Donner la taille de la memoire partagee par bloc
// Donner le nombre de thread max dans chacune des directions
// Donner le taille maximum de la grille pour chaque direction
// Donner la taille du warp
}
return 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
int main(int argc, char ** argv) {
int deviceCount;
cudaGetDeviceCount(&deviceCount);
for (int dev = 0; dev < deviceCount; dev++) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
// Ne detecte pas CUDA
return -1;
} else {
// Afficher le nombre de device
}
}
// Afficher le nom de la device
// Donner le numero de version majeur et mineur
// Donner la taille de la memoire globale
// Donner la taille de la memoire constante
// Donner la taille de la memoire partagee par bloc
// Donner le nombre de thread max dans chacune des directions
// Donner le taille maximum de la grille pour chaque direction
// Donner la taille du warp
}
return 0;
} | .file "tmpxft_00137f3f_00000000-6_cuda_info.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L8
movl $0, %ebx
movabsq $42945378002703, %rbp
jmp .L6
.L5:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L11
.L6:
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
testl %ebx, %ebx
jne .L5
cmpq %rbp, 376(%rsp)
jne .L5
movl $-1, %eax
jmp .L3
.L11:
movl $0, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L12
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movl $0, %eax
jmp .L3
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
int main(int argc, char ** argv) {
int deviceCount;
cudaGetDeviceCount(&deviceCount);
for (int dev = 0; dev < deviceCount; dev++) {
cudaDeviceProp deviceProp;
cudaGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
// Ne detecte pas CUDA
return -1;
} else {
// Afficher le nombre de device
}
}
// Afficher le nom de la device
// Donner le numero de version majeur et mineur
// Donner la taille de la memoire globale
// Donner la taille de la memoire constante
// Donner la taille de la memoire partagee par bloc
// Donner le nombre de thread max dans chacune des directions
// Donner le taille maximum de la grille pour chaque direction
// Donner la taille du warp
}
return 0;
} | #include <hip/hip_runtime.h>
int main(int argc, char ** argv) {
int deviceCount;
hipGetDeviceCount(&deviceCount);
for (int dev = 0; dev < deviceCount; dev++) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
// Ne detecte pas CUDA
return -1;
} else {
// Afficher le nombre de device
}
}
// Afficher le nom de la device
// Donner le numero de version majeur et mineur
// Donner la taille de la memoire globale
// Donner la taille de la memoire constante
// Donner la taille de la memoire partagee par bloc
// Donner le nombre de thread max dans chacune des directions
// Donner le taille maximum de la grille pour chaque direction
// Donner la taille du warp
}
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
int main(int argc, char ** argv) {
int deviceCount;
hipGetDeviceCount(&deviceCount);
for (int dev = 0; dev < deviceCount; dev++) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
// Ne detecte pas CUDA
return -1;
} else {
// Afficher le nombre de device
}
}
// Afficher le nom de la device
// Donner le numero de version majeur et mineur
// Donner la taille de la memoire globale
// Donner la taille de la memoire constante
// Donner la taille de la memoire partagee par bloc
// Donner le nombre de thread max dans chacune des directions
// Donner le taille maximum de la grille pour chaque direction
// Donner la taille du warp
}
return 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
int main(int argc, char ** argv) {
int deviceCount;
hipGetDeviceCount(&deviceCount);
for (int dev = 0; dev < deviceCount; dev++) {
hipDeviceProp_t deviceProp;
hipGetDeviceProperties(&deviceProp, dev);
if (dev == 0) {
if (deviceProp.major == 9999 && deviceProp.minor == 9999) {
// Ne detecte pas CUDA
return -1;
} else {
// Afficher le nombre de device
}
}
// Afficher le nom de la device
// Donner le numero de version majeur et mineur
// Donner la taille de la memoire globale
// Donner la taille de la memoire constante
// Donner la taille de la memoire partagee par bloc
// Donner le nombre de thread max dans chacune des directions
// Donner le taille maximum de la grille pour chaque direction
// Donner la taille du warp
}
return 0;
} | .text
.file "cuda_info.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB0_9
# %bb.1: # %.lr.ph
xorl %ebp, %ebp
leaq 16(%rsp), %r14
xorl %ebx, %ebx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
movb $1, %al
testb %al, %al
je .LBB0_10
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB0_9
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %ebp, %ebp
jne .LBB0_3
# %bb.5: # in Loop: Header=BB0_2 Depth=1
cmpl $9999, 376(%rsp) # imm = 0x270F
jne .LBB0_3
# %bb.6: # in Loop: Header=BB0_2 Depth=1
cmpl $9999, 380(%rsp) # imm = 0x270F
jne .LBB0_3
# %bb.7: # in Loop: Header=BB0_2 Depth=1
xorl %eax, %eax
movl $-1, %ebx
testb %al, %al
jne .LBB0_4
jmp .LBB0_10
.LBB0_9:
xorl %ebx, %ebx
.LBB0_10: # %._crit_edge
movl %ebx, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00137f3f_00000000-6_cuda_info.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl main
.type main, @function
main:
.LFB2027:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $1064, %rsp
.cfi_def_cfa_offset 1088
movq %fs:40, %rax
movq %rax, 1048(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 12(%rsp)
jle .L8
movl $0, %ebx
movabsq $42945378002703, %rbp
jmp .L6
.L5:
addl $1, %ebx
cmpl %ebx, 12(%rsp)
jle .L11
.L6:
leaq 16(%rsp), %rdi
movl %ebx, %esi
call cudaGetDeviceProperties_v2@PLT
testl %ebx, %ebx
jne .L5
cmpq %rbp, 376(%rsp)
jne .L5
movl $-1, %eax
jmp .L3
.L11:
movl $0, %eax
.L3:
movq 1048(%rsp), %rdx
subq %fs:40, %rdx
jne .L12
addq $1064, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L8:
.cfi_restore_state
movl $0, %eax
jmp .L3
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2027:
.size main, .-main
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda_info.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 1520
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
leaq 12(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 12(%rsp)
jle .LBB0_9
# %bb.1: # %.lr.ph
xorl %ebp, %ebp
leaq 16(%rsp), %r14
xorl %ebx, %ebx
jmp .LBB0_2
.p2align 4, 0x90
.LBB0_3: # in Loop: Header=BB0_2 Depth=1
movb $1, %al
testb %al, %al
je .LBB0_10
.LBB0_4: # in Loop: Header=BB0_2 Depth=1
incl %ebp
cmpl 12(%rsp), %ebp
jge .LBB0_9
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
movl %ebp, %esi
callq hipGetDevicePropertiesR0600
testl %ebp, %ebp
jne .LBB0_3
# %bb.5: # in Loop: Header=BB0_2 Depth=1
cmpl $9999, 376(%rsp) # imm = 0x270F
jne .LBB0_3
# %bb.6: # in Loop: Header=BB0_2 Depth=1
cmpl $9999, 380(%rsp) # imm = 0x270F
jne .LBB0_3
# %bb.7: # in Loop: Header=BB0_2 Depth=1
xorl %eax, %eax
movl $-1, %ebx
testb %al, %al
jne .LBB0_4
jmp .LBB0_10
.LBB0_9:
xorl %ebx, %ebx
.LBB0_10: # %._crit_edge
movl %ebx, %eax
addq $1488, %rsp # imm = 0x5D0
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*
* cSumSquares.cu
*
* Copyright 2021 mike <mike@fedora33>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* =====================================================================
* Function g(n) is defined as greatest perfect square which divides n.
* Consider n = 10^9. 31623^2 = 1000014129
* To build a table of useful perfect squares: for x in range(1, 31624) calc x^2
* Requires 976577 blocks of 1024 threads
*
* Host memory approx 14Gb free, 10^9
*
* Available device memory approx. 1.6GiB
* Using a maximum of 190000 * 1024 * sizeof(long) requires 1.56GiB
* For a given value of N:
* calc lines required (N/1024) + 1
* pagecount = (lines/190000) + 1
*
* Launch the kernel pagecount times, summing partial results
*
* =====================================================================
*/
#include <stdio.h>
#include <math.h>
#include <cuda.h>
#define DEBUG 1
__global__ void set_squares(long *d_squares, long n_squares) {
long i = threadIdx.x + (blockIdx.x * blockDim.x);
if(i < n_squares) d_squares[i] = (int)(i+1)*(i+1);
}
__global__ void func_g(long* d_squares, const long n_squares, long *d_sums, long N, long page_size, int page_idx) {
// Calc the index of result in device results page
long i = threadIdx.x + (blockDim.x * blockIdx.x);
// Calc actual target
long target = i + (page_size * page_idx);
if(target <= N) {
//printf("idx: %ld target: %ld\n", i, target); return;
// scan in reverse the squares array
// save first square which divides i in results[i]
if(target > 3) {
for(long x = n_squares-1; x > 0; x -= 1) {
if((target % d_squares[x]) == 0) {
d_sums[i] = d_squares[x];
printf("x: %d target: %ld square: %ld\n", x, target, d_squares[x]);
break;
}
} // for...
} else {
d_sums[i] = i;
}
} // if target...
}
int main(int argc, char **argv)
{
cudaError_t error_id;
long *d_squares = NULL;
// These values based on 1.56GiB available on device
const int PageY = 190000;
const int PageX = 1024;
const int PageSize = PageX*PageY;
long *h_sums = NULL; // large page of partial results
long *d_sums = NULL;
// extract target N
long x = 0;
if(argc == 2) {
x = atol(argv[1]);
} else {
printf("usage: css target (< 1e9)\n");
exit(1);
}
const long N = x;
if(N <= 1e9L) {
printf("target: %ld\n", N);
} else {
printf("target: %ld exceeds program limitations (1e9)\n", N);
exit(2);
}
// determine array dimensions
long limit = (long)(sqrt(sqrt(N)) + 1); // defines size of array
#if(DEBUG)
printf("target: %ld limit: %ld\n", N, limit);
#endif
// Allocate space on device
error_id = cudaMalloc(&d_squares, sizeof(long )*limit);
if(error_id != cudaSuccess) {
printf("cudaMalloc squares failed with %d\n", error_id);
exit(1);
}
// launch the generator on kernel
printf("\nGenerating squares\n");
set_squares<<<1,limit>>>(d_squares, limit);
cudaDeviceSynchronize();
#if(DEBUG)
// allocate space on host and copy device squares
long *h_squares = (long *)malloc(sizeof(long )*limit);
cudaMemcpy(h_squares, d_squares, sizeof(long )*limit, cudaMemcpyDeviceToHost);
// print long array of squares
for(long x = 0; x < limit; ++x) printf("%d:%ld ", x, h_squares[x]); printf("\n");
// clear host array
free(h_squares);
#endif
// Allocate a results page on device
error_id = cudaMalloc(&d_sums, sizeof(long )*PageSize);
if(error_id != cudaSuccess) {
printf("cudaMalloc d_sums failed with %d\n", error_id);
exit(1);
}
// Allocate a results page on host
h_sums = (long*)malloc(sizeof(long)*PageSize);
if(h_sums == NULL) {
printf("Failed to malloc h_sums.");
exit(1);
}
// initialise to zero
for(int x = 0; x < PageSize; ++x) h_sums[x] = 0L;
int rows = (N / 1024) + 1;
int pages = (rows / 190000) + 1;
printf("N: %ld rows: %d pages: %d\n", N, rows, pages);
long Sum = 0;
long counted = 0;
for(int pg = 0; pg < pages; ++pg) {
// launch kernel with appropriate parameters
func_g<<<rows,1024>>>(d_squares, limit, d_sums, N, PageSize, pg);
// device sync and test for errors
error_id = cudaDeviceSynchronize();
if(error_id != cudaSuccess) {
printf("cudaDeviceSync returned %d\n", error_id);
exit(0);
}
// copy device sums to host
error_id = cudaMemcpy(h_sums, d_sums, sizeof(long)*PageSize, cudaMemcpyDeviceToHost);
// DEBUG
for(int x = 0; ((x<PageSize)&&(counted < N)); ++x,++counted) {
printf("%d:%ld ",x,h_sums[x]);
}
printf("\n"); goto exit;
// END DEBUG
#if(0)
// Update S by summing last returned page page
for(int x = 0; ((x<20)&&(counted < N)); ++x,++counted) {
Sum += h_sums[x];
}
#endif
}
exit:
// Output Result as S(N) = S
printf("S(%ld) = %ld.\n", N, Sum);
// CleanUp
free(h_sums);
cudaFree(d_sums);
return 0;
} | code for sm_80
Function : _Z6func_gPllS_lli
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc600078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe40007ffe0ff */
/*0040*/ S2R R9, SR_TID.X ; /* 0x0000000000097919 */
/* 0x000e240000002100 */
/*0050*/ SHF.R.S32.HI R0, RZ, 0x1f, R3 ; /* 0x0000001fff007819 */
/* 0x000fca0000011403 */
/*0060*/ IMAD R0, R0, c[0x0][0x180], RZ ; /* 0x0000600000007a24 */
/* 0x000fe400078e02ff */
/*0070*/ IMAD R8, R8, c[0x0][0x0], R9 ; /* 0x0000000008087a24 */
/* 0x001fe400078e0209 */
/*0080*/ IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff097224 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.WIDE.U32 R4, R3, c[0x0][0x180], R8 ; /* 0x0000600003047a25 */
/* 0x000fc800078e0008 */
/*00a0*/ IMAD R3, R3, c[0x0][0x184], R0 ; /* 0x0000610003037a24 */
/* 0x000fe200078e0200 */
/*00b0*/ ISETP.GT.U32.AND P0, PT, R4, c[0x0][0x178], PT ; /* 0x00005e0004007a0c */
/* 0x000fc60003f04070 */
/*00c0*/ IMAD.IADD R3, R5, 0x1, R3 ; /* 0x0000000105037824 */
/* 0x000fca00078e0203 */
/*00d0*/ ISETP.GT.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f04300 */
/*00e0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00f0*/ ISETP.GT.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f04070 */
/*0100*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0110*/ LEA R10, P1, R8.reuse, c[0x0][0x170], 0x3 ; /* 0x00005c00080a7a11 */
/* 0x040fe400078218ff */
/*0120*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P0 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04300 */
/*0130*/ LEA.HI.X R11, R8, c[0x0][0x174], RZ, 0x3, P1 ; /* 0x00005d00080b7a11 */
/* 0x000fe400008f1cff */
/*0140*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f3e0ff */
/*0150*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fc800008e06ff */
/*0160*/ @!P0 STG.E.64 [R10.64], R8 ; /* 0x000000080a008986 */
/* 0x0001e2000c101b04 */
/*0170*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0180*/ BSSY B0, 0x440 ; /* 0x000002b000007945 */
/* 0x000fe20003800000 */
/*0190*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff007624 */
/* 0x000fe400078e00ff */
/*01a0*/ IMAD.MOV.U32 R16, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff107624 */
/* 0x000fc600078e00ff */
/*01b0*/ ISETP.GE.U32.AND P0, PT, R0.reuse, 0x2, PT ; /* 0x000000020000780c */
/* 0x040fe40003f06070 */
/*01c0*/ IADD3 R8, P1, R0, -0x1, RZ ; /* 0xffffffff00087810 */
/* 0x001fe40007f3e0ff */
/*01d0*/ ISETP.GE.AND.EX P0, PT, R16.reuse, RZ, PT, P0 ; /* 0x000000ff1000720c */
/* 0x040fe40003f06300 */
/*01e0*/ IADD3.X R9, R16, -0x1, RZ, P1, !PT ; /* 0xffffffff10097810 */
/* 0x000fd60000ffe4ff */
/*01f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0200*/ LEA R12, P0, R8, c[0x0][0x160], 0x3 ; /* 0x00005800080c7a11 */
/* 0x000fc800078018ff */
/*0210*/ LEA.HI.X R13, R8, c[0x0][0x164], R9, 0x3, P0 ; /* 0x00005900080d7a11 */
/* 0x000fca00000f1c09 */
/*0220*/ LDG.E.64 R14, [R12.64] ; /* 0x000000040c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0230*/ BSSY B1, 0x400 ; /* 0x000001c000017945 */
/* 0x000fe20003800000 */
/*0240*/ LOP3.LUT R0, R3, R15, RZ, 0xfc, !PT ; /* 0x0000000f03007212 */
/* 0x004fc800078efcff */
/*0250*/ ISETP.NE.U32.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f05070 */
/*0260*/ @!P0 BRA 0x2c0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*0270*/ MOV R0, 0x290 ; /* 0x0000029000007802 */
/* 0x000fe40000000f00 */
/*0280*/ CALL.REL.NOINC 0x570 ; /* 0x000002e000007944 */
/* 0x000fea0003c00000 */
/*0290*/ ISETP.NE.U32.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fc80003f05070 */
/*02a0*/ ISETP.NE.AND.EX P0, PT, R19, RZ, PT, P0 ; /* 0x000000ff1300720c */
/* 0x000fe20003f05300 */
/*02b0*/ BRA 0x3f0 ; /* 0x0000013000007947 */
/* 0x000fee0003800000 */
/*02c0*/ I2F.U32.RP R0, R14 ; /* 0x0000000e00007306 */
/* 0x000e220000209000 */
/*02d0*/ IMAD.MOV R19, RZ, RZ, -R14 ; /* 0x000000ffff137224 */
/* 0x000fe200078e0a0e */
/*02e0*/ ISETP.NE.U32.AND P1, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fcc0003f25070 */
/*02f0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*0300*/ IADD3 R16, R0, 0xffffffe, RZ ; /* 0x0ffffffe00107810 */
/* 0x001fcc0007ffe0ff */
/*0310*/ F2I.FTZ.U32.TRUNC.NTZ R17, R16 ; /* 0x0000001000117305 */
/* 0x000064000021f000 */
/*0320*/ IMAD.MOV.U32 R16, RZ, RZ, RZ ; /* 0x000000ffff107224 */
/* 0x001fe400078e00ff */
/*0330*/ IMAD R19, R19, R17, RZ ; /* 0x0000001113137224 */
/* 0x002fc800078e02ff */
/*0340*/ IMAD.HI.U32 R17, R17, R19, R16 ; /* 0x0000001311117227 */
/* 0x000fcc00078e0010 */
/*0350*/ IMAD.HI.U32 R17, R17, R4, RZ ; /* 0x0000000411117227 */
/* 0x000fc800078e00ff */
/*0360*/ IMAD.MOV R17, RZ, RZ, -R17 ; /* 0x000000ffff117224 */
/* 0x000fc800078e0a11 */
/*0370*/ IMAD R17, R14, R17, R4 ; /* 0x000000110e117224 */
/* 0x000fca00078e0204 */
/*0380*/ ISETP.GE.U32.AND P0, PT, R17, R14, PT ; /* 0x0000000e1100720c */
/* 0x000fda0003f06070 */
/*0390*/ @P0 IMAD.IADD R17, R17, 0x1, -R14 ; /* 0x0000000111110824 */
/* 0x000fca00078e0a0e */
/*03a0*/ ISETP.GE.U32.AND P0, PT, R17, R14, PT ; /* 0x0000000e1100720c */
/* 0x000fda0003f06070 */
/*03b0*/ @P0 IMAD.IADD R17, R17, 0x1, -R14 ; /* 0x0000000111110824 */
/* 0x000fe200078e0a0e */
/*03c0*/ @!P1 LOP3.LUT R17, RZ, R14, RZ, 0x33, !PT ; /* 0x0000000eff119212 */
/* 0x000fc800078e33ff */
/*03d0*/ ISETP.NE.U32.AND P0, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fc80003f05070 */
/*03e0*/ ISETP.NE.AND.EX P0, PT, RZ, RZ, PT, P0 ; /* 0x000000ffff00720c */
/* 0x000fd00003f05300 */
/*03f0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0400*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fe400078e0008 */
/*0410*/ IMAD.MOV.U32 R16, RZ, RZ, R9 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0009 */
/*0420*/ @P0 BRA 0x1b0 ; /* 0xfffffd8000000947 */
/* 0x000fea000383ffff */
/*0430*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0440*/ STG.E.64 [R10.64], R14 ; /* 0x0000000e0a007986 */
/* 0x0001e8000c101b04 */
/*0450*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0460*/ IMAD.MOV.U32 R2, RZ, RZ, R4 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0004 */
/*0470*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0480*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0490*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0001e20000100a00 */
/*04a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*04b0*/ LDC.64 R16, c[0x4][R0] ; /* 0x0100000000107b82 */
/* 0x0000640000000a00 */
/*04c0*/ STL.64 [R1+0x8], R2 ; /* 0x0000080201007387 */
/* 0x0001e80000100a00 */
/*04d0*/ STL.64 [R1+0x10], R12 ; /* 0x0000100c01007387 */
/* 0x0041e40000100a00 */
/*04e0*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x003fe20000000000 */
/*04f0*/ MOV R9, 0x560 ; /* 0x0000056000097802 */
/* 0x000fc40000000f00 */
/*0500*/ MOV R20, 0x4e0 ; /* 0x000004e000147802 */
/* 0x000fe40000000f00 */
/*0510*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0520*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0530*/ IADD3 R20, P0, P1, -R20, R9, R2 ; /* 0x0000000914147210 */
/* 0x000fc8000791e102 */
/*0540*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0550*/ CALL.ABS.NOINC R16 ; /* 0x0000000010007343 */
/* 0x000fea0003c00000 */
/*0560*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0570*/ IADD3 R17, P1, RZ, -R14, RZ ; /* 0x8000000eff117210 */
/* 0x000fe40007f3e0ff */
/*0580*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fc60003f06270 */
/*0590*/ IMAD.X R19, RZ, RZ, ~R15, P1 ; /* 0x000000ffff137224 */
/* 0x000fe200008e0e0f */
/*05a0*/ SEL R16, R17, R14, !P0 ; /* 0x0000000e11107207 */
/* 0x000fc80004000000 */
/*05b0*/ SEL R17, R19, R15, !P0 ; /* 0x0000000f13117207 */
/* 0x000fc80004000000 */
/*05c0*/ I2F.U64.RP R22, R16 ; /* 0x0000001000167312 */
/* 0x000e300000309000 */
/*05d0*/ MUFU.RCP R22, R22 ; /* 0x0000001600167308 */
/* 0x001e240000001000 */
/*05e0*/ IADD3 R18, R22, 0x1ffffffe, RZ ; /* 0x1ffffffe16127810 */
/* 0x001fcc0007ffe0ff */
/*05f0*/ F2I.U64.TRUNC R18, R18 ; /* 0x0000001200127311 */
/* 0x000e24000020d800 */
/*0600*/ IMAD.WIDE.U32 R20, R18, R16, RZ ; /* 0x0000001012147225 */
/* 0x001fc800078e00ff */
/*0610*/ IMAD R21, R18, R17, R21 ; /* 0x0000001112157224 */
/* 0x000fe200078e0215 */
/*0620*/ IADD3 R23, P0, RZ, -R20, RZ ; /* 0x80000014ff177210 */
/* 0x000fc60007f1e0ff */
/*0630*/ IMAD R21, R19, R16, R21 ; /* 0x0000001013157224 */
/* 0x000fe400078e0215 */
/*0640*/ IMAD.HI.U32 R20, R18, R23, RZ ; /* 0x0000001712147227 */
/* 0x000fc800078e00ff */
/*0650*/ IMAD.X R25, RZ, RZ, ~R21, P0 ; /* 0x000000ffff197224 */
/* 0x000fe400000e0e15 */
/*0660*/ IMAD.MOV.U32 R21, RZ, RZ, R18 ; /* 0x000000ffff157224 */
/* 0x000fe400078e0012 */
/*0670*/ IMAD R27, R19, R25.reuse, RZ ; /* 0x00000019131b7224 */
/* 0x080fe400078e02ff */
/*0680*/ IMAD.WIDE.U32 R20, P0, R18, R25, R20 ; /* 0x0000001912147225 */
/* 0x000fcc0007800014 */
/*0690*/ IMAD.HI.U32 R20, P1, R19, R23, R20 ; /* 0x0000001713147227 */
/* 0x000fc80007820014 */
/*06a0*/ IMAD.HI.U32 R23, R19, R25, RZ ; /* 0x0000001913177227 */
/* 0x000fe200078e00ff */
/*06b0*/ IADD3 R21, P2, R27, R20, RZ ; /* 0x000000141b157210 */
/* 0x000fc60007f5e0ff */
/*06c0*/ IMAD.X R23, R23, 0x1, R19, P0 ; /* 0x0000000117177824 */
/* 0x000fe400000e0613 */
/*06d0*/ IMAD.WIDE.U32 R18, R21, R16, RZ ; /* 0x0000001015127225 */
/* 0x000fc600078e00ff */
/*06e0*/ IADD3.X R23, RZ, RZ, R23, P2, P1 ; /* 0x000000ffff177210 */
/* 0x000fe200017e2417 */
/*06f0*/ IMAD R19, R21, R17, R19 ; /* 0x0000001115137224 */
/* 0x000fe200078e0213 */
/*0700*/ IADD3 R25, P0, RZ, -R18, RZ ; /* 0x80000012ff197210 */
/* 0x000fe40007f1e0ff */
/*0710*/ ISETP.GE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe20003f26270 */
/*0720*/ IMAD R19, R23, R16, R19 ; /* 0x0000001017137224 */
/* 0x000fe400078e0213 */
/*0730*/ IMAD.HI.U32 R20, R21, R25, RZ ; /* 0x0000001915147227 */
/* 0x000fc800078e00ff */
/*0740*/ IMAD.X R18, RZ, RZ, ~R19, P0 ; /* 0x000000ffff127224 */
/* 0x000fe200000e0e13 */
/*0750*/ IADD3 R19, P4, RZ, -R4, RZ ; /* 0x80000004ff137210 */
/* 0x000fc60007f9e0ff */
/*0760*/ IMAD.WIDE.U32 R20, P0, R21, R18, R20 ; /* 0x0000001215147225 */
/* 0x000fc80007800014 */
/*0770*/ IMAD R22, R23.reuse, R18, RZ ; /* 0x0000001217167224 */
/* 0x040fe400078e02ff */
/*0780*/ IMAD.HI.U32 R21, P2, R23, R25, R20 ; /* 0x0000001917157227 */
/* 0x000fe20007840014 */
/*0790*/ SEL R20, R19, R4, !P1 ; /* 0x0000000413147207 */
/* 0x000fc60004800000 */
/*07a0*/ IMAD.HI.U32 R18, R23, R18, RZ ; /* 0x0000001217127227 */
/* 0x000fe200078e00ff */
/*07b0*/ IADD3 R25, P3, R22, R21, RZ ; /* 0x0000001516197210 */
/* 0x000fc60007f7e0ff */
/*07c0*/ IMAD.X R21, RZ, RZ, ~R3, P4 ; /* 0x000000ffff157224 */
/* 0x000fe400020e0e03 */
/*07d0*/ IMAD.X R23, R18, 0x1, R23, P0 ; /* 0x0000000112177824 */
/* 0x000fe400000e0617 */
/*07e0*/ IMAD.HI.U32 R18, R25, R20, RZ ; /* 0x0000001419127227 */
/* 0x000fe200078e00ff */
/*07f0*/ SEL R21, R21, R3, !P1 ; /* 0x0000000315157207 */
/* 0x000fe40004800000 */
/*0800*/ IADD3.X R23, RZ, RZ, R23, P3, P2 ; /* 0x000000ffff177210 */
/* 0x000fe20001fe4417 */
/*0810*/ IMAD.MOV.U32 R19, RZ, RZ, RZ ; /* 0x000000ffff137224 */
/* 0x000fc800078e00ff */
/*0820*/ IMAD.WIDE.U32 R18, R25, R21, R18 ; /* 0x0000001519127225 */
/* 0x000fc800078e0012 */
/*0830*/ IMAD R25, R23.reuse, R21, RZ ; /* 0x0000001517197224 */
/* 0x040fe400078e02ff */
/*0840*/ IMAD.HI.U32 R18, P0, R23, R20, R18 ; /* 0x0000001417127227 */
/* 0x000fc80007800012 */
/*0850*/ IMAD.HI.U32 R22, R23, R21, RZ ; /* 0x0000001517167227 */
/* 0x000fe200078e00ff */
/*0860*/ IADD3 R23, P2, R25, R18, RZ ; /* 0x0000001219177210 */
/* 0x000fc60007f5e0ff */
/*0870*/ IMAD.X R22, RZ, RZ, R22, P0 ; /* 0x000000ffff167224 */
/* 0x000fe400000e0616 */
/*0880*/ IMAD.WIDE.U32 R18, R23, R16, RZ ; /* 0x0000001017127225 */
/* 0x000fc800078e00ff */
/*0890*/ IMAD.X R25, RZ, RZ, R22, P2 ; /* 0x000000ffff197224 */
/* 0x000fe400010e0616 */
/*08a0*/ IMAD R23, R23, R17, R19 ; /* 0x0000001117177224 */
/* 0x000fe200078e0213 */
/*08b0*/ IADD3 R19, P2, -R18, R20, RZ ; /* 0x0000001412137210 */
/* 0x000fc60007f5e1ff */
/*08c0*/ IMAD R18, R25, R16.reuse, R23 ; /* 0x0000001019127224 */
/* 0x080fe200078e0217 */
/*08d0*/ ISETP.GE.U32.AND P0, PT, R19, R16, PT ; /* 0x000000101300720c */
/* 0x000fc60003f06070 */
/*08e0*/ IMAD.X R25, R21, 0x1, ~R18, P2 ; /* 0x0000000115197824 */
/* 0x000fe200010e0e12 */
/*08f0*/ IADD3 R21, P2, R19, -R16, RZ ; /* 0x8000001013157210 */
/* 0x000fc80007f5e0ff */
/*0900*/ ISETP.GE.U32.AND.EX P0, PT, R25.reuse, R17, PT, P0 ; /* 0x000000111900720c */
/* 0x040fe20003f06100 */
/*0910*/ IMAD.X R23, R25, 0x1, ~R17, P2 ; /* 0x0000000119177824 */
/* 0x000fc600010e0e11 */
/*0920*/ SEL R21, R21, R19, P0 ; /* 0x0000001315157207 */
/* 0x000fe40000000000 */
/*0930*/ SEL R23, R23, R25, P0 ; /* 0x0000001917177207 */
/* 0x000fe40000000000 */
/*0940*/ ISETP.GE.U32.AND P0, PT, R21.reuse, R16.reuse, PT ; /* 0x000000101500720c */
/* 0x0c0fe40003f06070 */
/*0950*/ IADD3 R18, P2, R21, -R16, RZ ; /* 0x8000001015127210 */
/* 0x000fe40007f5e0ff */
/*0960*/ ISETP.GE.U32.AND.EX P0, PT, R23, R17, PT, P0 ; /* 0x000000111700720c */
/* 0x000fc60003f06100 */
/*0970*/ IMAD.X R19, R23, 0x1, ~R17, P2 ; /* 0x0000000117137824 */
/* 0x000fe200010e0e11 */
/*0980*/ SEL R18, R18, R21, P0 ; /* 0x0000001512127207 */
/* 0x000fc80000000000 */
/*0990*/ SEL R19, R19, R23, P0 ; /* 0x0000001713137207 */
/* 0x000fe40000000000 */
/*09a0*/ IADD3 R17, P2, RZ, -R18.reuse, RZ ; /* 0x80000012ff117210 */
/* 0x080fe40007f5e0ff */
/*09b0*/ ISETP.NE.U32.AND P0, PT, R14, RZ, PT ; /* 0x000000ff0e00720c */
/* 0x000fe40003f05070 */
/*09c0*/ SEL R18, R17, R18, !P1 ; /* 0x0000001211127207 */
/* 0x000fe20004800000 */
/*09d0*/ IMAD.X R16, RZ, RZ, ~R19, P2 ; /* 0x000000ffff107224 */
/* 0x000fe200010e0e13 */
/*09e0*/ ISETP.NE.AND.EX P0, PT, R15, RZ, PT, P0 ; /* 0x000000ff0f00720c */
/* 0x000fe20003f05300 */
/*09f0*/ IMAD.MOV.U32 R17, RZ, RZ, 0x0 ; /* 0x00000000ff117424 */
/* 0x000fc600078e00ff */
/*0a00*/ SEL R19, R16, R19, !P1 ; /* 0x0000001310137207 */
/* 0x000fe20004800000 */
/*0a10*/ IMAD.MOV.U32 R16, RZ, RZ, R0 ; /* 0x000000ffff107224 */
/* 0x000fe200078e0000 */
/*0a20*/ SEL R18, R18, 0xffffffff, P0 ; /* 0xffffffff12127807 */
/* 0x000fe40000000000 */
/*0a30*/ SEL R19, R19, 0xffffffff, P0 ; /* 0xffffffff13137807 */
/* 0x000fe20000000000 */
/*0a40*/ RET.REL.NODEC R16 0x0 ; /* 0xfffff5b010007950 */
/* 0x000fec0003c3ffff */
/*0a50*/ BRA 0xa50; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11set_squaresPll
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R0, R3, c[0x0][0x0], R0 ; /* 0x0000000003007a24 */
/* 0x001fca00078e0200 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fc80003f06070 */
/*0050*/ ISETP.GE.AND.EX P0, PT, RZ, c[0x0][0x16c], PT, P0 ; /* 0x00005b00ff007a0c */
/* 0x000fda0003f06300 */
/*0060*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R6, P0, R0.reuse, 0x1, RZ ; /* 0x0000000100067810 */
/* 0x040fe20007f1e0ff */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0090*/ IADD3 R2, R0, 0x1, RZ ; /* 0x0000000100027810 */
/* 0x000fc60007ffe0ff */
/*00a0*/ IMAD.X R3, RZ, RZ, RZ, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e06ff */
/*00b0*/ SHF.R.S32.HI R5, RZ, 0x1f, R2 ; /* 0x0000001fff057819 */
/* 0x000fe40000011402 */
/*00c0*/ LEA R4, P0, R0, c[0x0][0x160], 0x3 ; /* 0x0000580000047a11 */
/* 0x000fe200078018ff */
/*00d0*/ IMAD R7, R3, R2.reuse, RZ ; /* 0x0000000203077224 */
/* 0x080fe400078e02ff */
/*00e0*/ IMAD.WIDE.U32 R2, R6, R2, RZ ; /* 0x0000000206027225 */
/* 0x000fc800078e00ff */
/*00f0*/ IMAD R7, R5, R6, R7 ; /* 0x0000000605077224 */
/* 0x000fe200078e0207 */
/*0100*/ LEA.HI.X R5, R0, c[0x0][0x164], RZ, 0x3, P0 ; /* 0x0000590000057a11 */
/* 0x000fc600000f1cff */
/*0110*/ IMAD.IADD R3, R3, 0x1, R7 ; /* 0x0000000103037824 */
/* 0x000fca00078e0207 */
/*0120*/ STG.E.64 [R4.64], R2 ; /* 0x0000000204007986 */
/* 0x000fe2000c101b04 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* cSumSquares.cu
*
* Copyright 2021 mike <mike@fedora33>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* =====================================================================
* Function g(n) is defined as greatest perfect square which divides n.
* Consider n = 10^9. 31623^2 = 1000014129
* To build a table of useful perfect squares: for x in range(1, 31624) calc x^2
* Requires 976577 blocks of 1024 threads
*
* Host memory approx 14Gb free, 10^9
*
* Available device memory approx. 1.6GiB
* Using a maximum of 190000 * 1024 * sizeof(long) requires 1.56GiB
* For a given value of N:
* calc lines required (N/1024) + 1
* pagecount = (lines/190000) + 1
*
* Launch the kernel pagecount times, summing partial results
*
* =====================================================================
*/
#include <stdio.h>
#include <math.h>
#include <cuda.h>
#define DEBUG 1
__global__ void set_squares(long *d_squares, long n_squares) {
long i = threadIdx.x + (blockIdx.x * blockDim.x);
if(i < n_squares) d_squares[i] = (int)(i+1)*(i+1);
}
__global__ void func_g(long* d_squares, const long n_squares, long *d_sums, long N, long page_size, int page_idx) {
// Calc the index of result in device results page
long i = threadIdx.x + (blockDim.x * blockIdx.x);
// Calc actual target
long target = i + (page_size * page_idx);
if(target <= N) {
//printf("idx: %ld target: %ld\n", i, target); return;
// scan in reverse the squares array
// save first square which divides i in results[i]
if(target > 3) {
for(long x = n_squares-1; x > 0; x -= 1) {
if((target % d_squares[x]) == 0) {
d_sums[i] = d_squares[x];
printf("x: %d target: %ld square: %ld\n", x, target, d_squares[x]);
break;
}
} // for...
} else {
d_sums[i] = i;
}
} // if target...
}
int main(int argc, char **argv)
{
cudaError_t error_id;
long *d_squares = NULL;
// These values based on 1.56GiB available on device
const int PageY = 190000;
const int PageX = 1024;
const int PageSize = PageX*PageY;
long *h_sums = NULL; // large page of partial results
long *d_sums = NULL;
// extract target N
long x = 0;
if(argc == 2) {
x = atol(argv[1]);
} else {
printf("usage: css target (< 1e9)\n");
exit(1);
}
const long N = x;
if(N <= 1e9L) {
printf("target: %ld\n", N);
} else {
printf("target: %ld exceeds program limitations (1e9)\n", N);
exit(2);
}
// determine array dimensions
long limit = (long)(sqrt(sqrt(N)) + 1); // defines size of array
#if(DEBUG)
printf("target: %ld limit: %ld\n", N, limit);
#endif
// Allocate space on device
error_id = cudaMalloc(&d_squares, sizeof(long )*limit);
if(error_id != cudaSuccess) {
printf("cudaMalloc squares failed with %d\n", error_id);
exit(1);
}
// launch the generator on kernel
printf("\nGenerating squares\n");
set_squares<<<1,limit>>>(d_squares, limit);
cudaDeviceSynchronize();
#if(DEBUG)
// allocate space on host and copy device squares
long *h_squares = (long *)malloc(sizeof(long )*limit);
cudaMemcpy(h_squares, d_squares, sizeof(long )*limit, cudaMemcpyDeviceToHost);
// print long array of squares
for(long x = 0; x < limit; ++x) printf("%d:%ld ", x, h_squares[x]); printf("\n");
// clear host array
free(h_squares);
#endif
// Allocate a results page on device
error_id = cudaMalloc(&d_sums, sizeof(long )*PageSize);
if(error_id != cudaSuccess) {
printf("cudaMalloc d_sums failed with %d\n", error_id);
exit(1);
}
// Allocate a results page on host
h_sums = (long*)malloc(sizeof(long)*PageSize);
if(h_sums == NULL) {
printf("Failed to malloc h_sums.");
exit(1);
}
// initialise to zero
for(int x = 0; x < PageSize; ++x) h_sums[x] = 0L;
int rows = (N / 1024) + 1;
int pages = (rows / 190000) + 1;
printf("N: %ld rows: %d pages: %d\n", N, rows, pages);
long Sum = 0;
long counted = 0;
for(int pg = 0; pg < pages; ++pg) {
// launch kernel with appropriate parameters
func_g<<<rows,1024>>>(d_squares, limit, d_sums, N, PageSize, pg);
// device sync and test for errors
error_id = cudaDeviceSynchronize();
if(error_id != cudaSuccess) {
printf("cudaDeviceSync returned %d\n", error_id);
exit(0);
}
// copy device sums to host
error_id = cudaMemcpy(h_sums, d_sums, sizeof(long)*PageSize, cudaMemcpyDeviceToHost);
// DEBUG
for(int x = 0; ((x<PageSize)&&(counted < N)); ++x,++counted) {
printf("%d:%ld ",x,h_sums[x]);
}
printf("\n"); goto exit;
// END DEBUG
#if(0)
// Update S by summing last returned page page
for(int x = 0; ((x<20)&&(counted < N)); ++x,++counted) {
Sum += h_sums[x];
}
#endif
}
exit:
// Output Result as S(N) = S
printf("S(%ld) = %ld.\n", N, Sum);
// CleanUp
free(h_sums);
cudaFree(d_sums);
return 0;
} | .file "tmpxft_0001299d_00000000-6_dSumSquares.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11set_squaresPllPll
.type _Z32__device_stub__Z11set_squaresPllPll, @function
_Z32__device_stub__Z11set_squaresPllPll:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11set_squaresPll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z11set_squaresPllPll, .-_Z32__device_stub__Z11set_squaresPllPll
.globl _Z11set_squaresPll
.type _Z11set_squaresPll, @function
_Z11set_squaresPll:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11set_squaresPllPll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11set_squaresPll, .-_Z11set_squaresPll
.globl _Z31__device_stub__Z6func_gPllS_lliPllS_lli
.type _Z31__device_stub__Z6func_gPllS_lliPllS_lli, @function
_Z31__device_stub__Z6func_gPllS_lliPllS_lli:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6func_gPllS_lli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z6func_gPllS_lliPllS_lli, .-_Z31__device_stub__Z6func_gPllS_lliPllS_lli
.globl _Z6func_gPllS_lli
.type _Z6func_gPllS_lli, @function
_Z6func_gPllS_lli:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6func_gPllS_lliPllS_lli
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6func_gPllS_lli, .-_Z6func_gPllS_lli
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: css target (< 1e9)\n"
.LC1:
.string "target: %ld\n"
.LC4:
.string "target: %ld\t\tlimit: %ld\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "target: %ld exceeds program limitations (1e9)\n"
.align 8
.LC6:
.string "cudaMalloc squares failed with %d\n"
.section .rodata.str1.1
.LC7:
.string "\nGenerating squares\n"
.LC8:
.string "%d:%ld "
.LC9:
.string "\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "cudaMalloc d_sums failed with %d\n"
.section .rodata.str1.1
.LC11:
.string "Failed to malloc h_sums."
.LC12:
.string "N: %ld\trows: %d\tpages: %d\n"
.LC13:
.string "cudaDeviceSync returned %d\n"
.LC14:
.string "S(%ld) = %ld.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
cmpl $2, %edi
jne .L20
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
cmpq $1000000000, %rax
jg .L54
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L50
sqrtsd %xmm0, %xmm0
.L25:
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L51
sqrtsd %xmm0, %xmm0
.L28:
addsd .LC3(%rip), %xmm0
cvttsd2siq %xmm0, %r12
movq %r12, %rcx
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 0(,%r12,8), %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L55
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L31:
call cudaDeviceSynchronize@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testq %r12, %r12
jle .L32
movl $0, %ebx
leaq .LC8(%rip), %r14
.L33:
movq 0(%r13,%rbx,8), %rcx
movq %rbx, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L33
.L32:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
leaq 8(%rsp), %rdi
movl $1556480000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L57
movl $1556480000, %edi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L58
leaq 1556480000(%rax), %rdx
.L36:
movq $0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L36
leaq 1023(%rbp), %r14
testq %rbp, %rbp
cmovns %rbp, %r14
sarq $10, %r14
addl $1, %r14d
movslq %r14d, %rbx
imulq $740723623, %rbx, %rbx
sarq $47, %rbx
movl %r14d, %eax
sarl $31, %eax
subl %eax, %ebx
addl $1, %ebx
movl %ebx, %r8d
movl %r14d, %ecx
movq %rbp, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L37
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r14d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L38:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
je .L39
movl %eax, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L20:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
call sqrt@PLT
jmp .L25
.L51:
call sqrt@PLT
jmp .L28
.L54:
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %edi
call exit@PLT
.L55:
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movq %r12, %rsi
movq (%rsp), %rdi
call _Z32__device_stub__Z11set_squaresPllPll
jmp .L31
.L57:
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl $0, %r9d
movl $194560000, %r8d
movq %rbp, %rcx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z6func_gPllS_lliPllS_lli
jmp .L38
.L39:
movl $2, %ecx
movl $1556480000, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testq %rbp, %rbp
jle .L40
movl $0, %ebx
leaq .LC8(%rip), %r12
.L41:
movq 0(%r13,%rbx,8), %rcx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl $194559999, %ebx
jg .L40
cmpq %rbp, %rbx
jl .L41
.L40:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L37:
movl $0, %ecx
movq %rbp, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z6func_gPllS_lli"
.LC16:
.string "_Z11set_squaresPll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z6func_gPllS_lli(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z11set_squaresPll(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* cSumSquares.cu
*
* Copyright 2021 mike <mike@fedora33>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* =====================================================================
* Function g(n) is defined as greatest perfect square which divides n.
* Consider n = 10^9. 31623^2 = 1000014129
* To build a table of useful perfect squares: for x in range(1, 31624) calc x^2
* Requires 976577 blocks of 1024 threads
*
* Host memory approx 14Gb free, 10^9
*
* Available device memory approx. 1.6GiB
* Using a maximum of 190000 * 1024 * sizeof(long) requires 1.56GiB
* For a given value of N:
* calc lines required (N/1024) + 1
* pagecount = (lines/190000) + 1
*
* Launch the kernel pagecount times, summing partial results
*
* =====================================================================
*/
#include <stdio.h>
#include <math.h>
#include <cuda.h>
#define DEBUG 1
__global__ void set_squares(long *d_squares, long n_squares) {
long i = threadIdx.x + (blockIdx.x * blockDim.x);
if(i < n_squares) d_squares[i] = (int)(i+1)*(i+1);
}
__global__ void func_g(long* d_squares, const long n_squares, long *d_sums, long N, long page_size, int page_idx) {
// Calc the index of result in device results page
long i = threadIdx.x + (blockDim.x * blockIdx.x);
// Calc actual target
long target = i + (page_size * page_idx);
if(target <= N) {
//printf("idx: %ld target: %ld\n", i, target); return;
// scan in reverse the squares array
// save first square which divides i in results[i]
if(target > 3) {
for(long x = n_squares-1; x > 0; x -= 1) {
if((target % d_squares[x]) == 0) {
d_sums[i] = d_squares[x];
printf("x: %d target: %ld square: %ld\n", x, target, d_squares[x]);
break;
}
} // for...
} else {
d_sums[i] = i;
}
} // if target...
}
int main(int argc, char **argv)
{
cudaError_t error_id;
long *d_squares = NULL;
// These values based on 1.56GiB available on device
const int PageY = 190000;
const int PageX = 1024;
const int PageSize = PageX*PageY;
long *h_sums = NULL; // large page of partial results
long *d_sums = NULL;
// extract target N
long x = 0;
if(argc == 2) {
x = atol(argv[1]);
} else {
printf("usage: css target (< 1e9)\n");
exit(1);
}
const long N = x;
if(N <= 1e9L) {
printf("target: %ld\n", N);
} else {
printf("target: %ld exceeds program limitations (1e9)\n", N);
exit(2);
}
// determine array dimensions
long limit = (long)(sqrt(sqrt(N)) + 1); // defines size of array
#if(DEBUG)
printf("target: %ld limit: %ld\n", N, limit);
#endif
// Allocate space on device
error_id = cudaMalloc(&d_squares, sizeof(long )*limit);
if(error_id != cudaSuccess) {
printf("cudaMalloc squares failed with %d\n", error_id);
exit(1);
}
// launch the generator on kernel
printf("\nGenerating squares\n");
set_squares<<<1,limit>>>(d_squares, limit);
cudaDeviceSynchronize();
#if(DEBUG)
// allocate space on host and copy device squares
long *h_squares = (long *)malloc(sizeof(long )*limit);
cudaMemcpy(h_squares, d_squares, sizeof(long )*limit, cudaMemcpyDeviceToHost);
// print long array of squares
for(long x = 0; x < limit; ++x) printf("%d:%ld ", x, h_squares[x]); printf("\n");
// clear host array
free(h_squares);
#endif
// Allocate a results page on device
error_id = cudaMalloc(&d_sums, sizeof(long )*PageSize);
if(error_id != cudaSuccess) {
printf("cudaMalloc d_sums failed with %d\n", error_id);
exit(1);
}
// Allocate a results page on host
h_sums = (long*)malloc(sizeof(long)*PageSize);
if(h_sums == NULL) {
printf("Failed to malloc h_sums.");
exit(1);
}
// initialise to zero
for(int x = 0; x < PageSize; ++x) h_sums[x] = 0L;
int rows = (N / 1024) + 1;
int pages = (rows / 190000) + 1;
printf("N: %ld rows: %d pages: %d\n", N, rows, pages);
long Sum = 0;
long counted = 0;
for(int pg = 0; pg < pages; ++pg) {
// launch kernel with appropriate parameters
func_g<<<rows,1024>>>(d_squares, limit, d_sums, N, PageSize, pg);
// device sync and test for errors
error_id = cudaDeviceSynchronize();
if(error_id != cudaSuccess) {
printf("cudaDeviceSync returned %d\n", error_id);
exit(0);
}
// copy device sums to host
error_id = cudaMemcpy(h_sums, d_sums, sizeof(long)*PageSize, cudaMemcpyDeviceToHost);
// DEBUG
for(int x = 0; ((x<PageSize)&&(counted < N)); ++x,++counted) {
printf("%d:%ld ",x,h_sums[x]);
}
printf("\n"); goto exit;
// END DEBUG
#if(0)
// Update S by summing last returned page page
for(int x = 0; ((x<20)&&(counted < N)); ++x,++counted) {
Sum += h_sums[x];
}
#endif
}
exit:
// Output Result as S(N) = S
printf("S(%ld) = %ld.\n", N, Sum);
// CleanUp
free(h_sums);
cudaFree(d_sums);
return 0;
} | /*
* cSumSquares.cu
*
* Copyright 2021 mike <mike@fedora33>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* =====================================================================
* Function g(n) is defined as greatest perfect square which divides n.
* Consider n = 10^9. 31623^2 = 1000014129
* To build a table of useful perfect squares: for x in range(1, 31624) calc x^2
* Requires 976577 blocks of 1024 threads
*
* Host memory approx 14Gb free, 10^9
*
* Available device memory approx. 1.6GiB
* Using a maximum of 190000 * 1024 * sizeof(long) requires 1.56GiB
* For a given value of N:
* calc lines required (N/1024) + 1
* pagecount = (lines/190000) + 1
*
* Launch the kernel pagecount times, summing partial results
*
* =====================================================================
*/
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define DEBUG 1
__global__ void set_squares(long *d_squares, long n_squares) {
long i = threadIdx.x + (blockIdx.x * blockDim.x);
if(i < n_squares) d_squares[i] = (int)(i+1)*(i+1);
}
__global__ void func_g(long* d_squares, const long n_squares, long *d_sums, long N, long page_size, int page_idx) {
// Calc the index of result in device results page
long i = threadIdx.x + (blockDim.x * blockIdx.x);
// Calc actual target
long target = i + (page_size * page_idx);
if(target <= N) {
//printf("idx: %ld target: %ld\n", i, target); return;
// scan in reverse the squares array
// save first square which divides i in results[i]
if(target > 3) {
for(long x = n_squares-1; x > 0; x -= 1) {
if((target % d_squares[x]) == 0) {
d_sums[i] = d_squares[x];
printf("x: %d target: %ld square: %ld\n", x, target, d_squares[x]);
break;
}
} // for...
} else {
d_sums[i] = i;
}
} // if target...
}
int main(int argc, char **argv)
{
hipError_t error_id;
long *d_squares = NULL;
// These values based on 1.56GiB available on device
const int PageY = 190000;
const int PageX = 1024;
const int PageSize = PageX*PageY;
long *h_sums = NULL; // large page of partial results
long *d_sums = NULL;
// extract target N
long x = 0;
if(argc == 2) {
x = atol(argv[1]);
} else {
printf("usage: css target (< 1e9)\n");
exit(1);
}
const long N = x;
if(N <= 1e9L) {
printf("target: %ld\n", N);
} else {
printf("target: %ld exceeds program limitations (1e9)\n", N);
exit(2);
}
// determine array dimensions
long limit = (long)(sqrt(sqrt(N)) + 1); // defines size of array
#if(DEBUG)
printf("target: %ld limit: %ld\n", N, limit);
#endif
// Allocate space on device
error_id = hipMalloc(&d_squares, sizeof(long )*limit);
if(error_id != hipSuccess) {
printf("hipMalloc squares failed with %d\n", error_id);
exit(1);
}
// launch the generator on kernel
printf("\nGenerating squares\n");
set_squares<<<1,limit>>>(d_squares, limit);
hipDeviceSynchronize();
#if(DEBUG)
// allocate space on host and copy device squares
long *h_squares = (long *)malloc(sizeof(long )*limit);
hipMemcpy(h_squares, d_squares, sizeof(long )*limit, hipMemcpyDeviceToHost);
// print long array of squares
for(long x = 0; x < limit; ++x) printf("%d:%ld ", x, h_squares[x]); printf("\n");
// clear host array
free(h_squares);
#endif
// Allocate a results page on device
error_id = hipMalloc(&d_sums, sizeof(long )*PageSize);
if(error_id != hipSuccess) {
printf("hipMalloc d_sums failed with %d\n", error_id);
exit(1);
}
// Allocate a results page on host
h_sums = (long*)malloc(sizeof(long)*PageSize);
if(h_sums == NULL) {
printf("Failed to malloc h_sums.");
exit(1);
}
// initialise to zero
for(int x = 0; x < PageSize; ++x) h_sums[x] = 0L;
int rows = (N / 1024) + 1;
int pages = (rows / 190000) + 1;
printf("N: %ld rows: %d pages: %d\n", N, rows, pages);
long Sum = 0;
long counted = 0;
for(int pg = 0; pg < pages; ++pg) {
// launch kernel with appropriate parameters
func_g<<<rows,1024>>>(d_squares, limit, d_sums, N, PageSize, pg);
// device sync and test for errors
error_id = hipDeviceSynchronize();
if(error_id != hipSuccess) {
printf("cudaDeviceSync returned %d\n", error_id);
exit(0);
}
// copy device sums to host
error_id = hipMemcpy(h_sums, d_sums, sizeof(long)*PageSize, hipMemcpyDeviceToHost);
// DEBUG
for(int x = 0; ((x<PageSize)&&(counted < N)); ++x,++counted) {
printf("%d:%ld ",x,h_sums[x]);
}
printf("\n"); goto exit;
// END DEBUG
#if(0)
// Update S by summing last returned page page
for(int x = 0; ((x<20)&&(counted < N)); ++x,++counted) {
Sum += h_sums[x];
}
#endif
}
exit:
// Output Result as S(N) = S
printf("S(%ld) = %ld.\n", N, Sum);
// CleanUp
free(h_sums);
hipFree(d_sums);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* cSumSquares.cu
*
* Copyright 2021 mike <mike@fedora33>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* =====================================================================
* Function g(n) is defined as greatest perfect square which divides n.
* Consider n = 10^9. 31623^2 = 1000014129
* To build a table of useful perfect squares: for x in range(1, 31624) calc x^2
* Requires 976577 blocks of 1024 threads
*
* Host memory approx 14Gb free, 10^9
*
* Available device memory approx. 1.6GiB
* Using a maximum of 190000 * 1024 * sizeof(long) requires 1.56GiB
* For a given value of N:
* calc lines required (N/1024) + 1
* pagecount = (lines/190000) + 1
*
* Launch the kernel pagecount times, summing partial results
*
* =====================================================================
*/
#include <stdio.h>
#include <math.h>
#include <hip/hip_runtime.h>
#define DEBUG 1
__global__ void set_squares(long *d_squares, long n_squares) {
long i = threadIdx.x + (blockIdx.x * blockDim.x);
if(i < n_squares) d_squares[i] = (int)(i+1)*(i+1);
}
__global__ void func_g(long* d_squares, const long n_squares, long *d_sums, long N, long page_size, int page_idx) {
// Calc the index of result in device results page
long i = threadIdx.x + (blockDim.x * blockIdx.x);
// Calc actual target
long target = i + (page_size * page_idx);
if(target <= N) {
//printf("idx: %ld target: %ld\n", i, target); return;
// scan in reverse the squares array
// save first square which divides i in results[i]
if(target > 3) {
for(long x = n_squares-1; x > 0; x -= 1) {
if((target % d_squares[x]) == 0) {
d_sums[i] = d_squares[x];
printf("x: %d target: %ld square: %ld\n", x, target, d_squares[x]);
break;
}
} // for...
} else {
d_sums[i] = i;
}
} // if target...
}
int main(int argc, char **argv)
{
hipError_t error_id;
long *d_squares = NULL;
// These values based on 1.56GiB available on device
const int PageY = 190000;
const int PageX = 1024;
const int PageSize = PageX*PageY;
long *h_sums = NULL; // large page of partial results
long *d_sums = NULL;
// extract target N
long x = 0;
if(argc == 2) {
x = atol(argv[1]);
} else {
printf("usage: css target (< 1e9)\n");
exit(1);
}
const long N = x;
if(N <= 1e9L) {
printf("target: %ld\n", N);
} else {
printf("target: %ld exceeds program limitations (1e9)\n", N);
exit(2);
}
// determine array dimensions
long limit = (long)(sqrt(sqrt(N)) + 1); // defines size of array
#if(DEBUG)
printf("target: %ld limit: %ld\n", N, limit);
#endif
// Allocate space on device
error_id = hipMalloc(&d_squares, sizeof(long )*limit);
if(error_id != hipSuccess) {
printf("hipMalloc squares failed with %d\n", error_id);
exit(1);
}
// launch the generator on kernel
printf("\nGenerating squares\n");
set_squares<<<1,limit>>>(d_squares, limit);
hipDeviceSynchronize();
#if(DEBUG)
// allocate space on host and copy device squares
long *h_squares = (long *)malloc(sizeof(long )*limit);
hipMemcpy(h_squares, d_squares, sizeof(long )*limit, hipMemcpyDeviceToHost);
// print long array of squares
for(long x = 0; x < limit; ++x) printf("%d:%ld ", x, h_squares[x]); printf("\n");
// clear host array
free(h_squares);
#endif
// Allocate a results page on device
error_id = hipMalloc(&d_sums, sizeof(long )*PageSize);
if(error_id != hipSuccess) {
printf("hipMalloc d_sums failed with %d\n", error_id);
exit(1);
}
// Allocate a results page on host
h_sums = (long*)malloc(sizeof(long)*PageSize);
if(h_sums == NULL) {
printf("Failed to malloc h_sums.");
exit(1);
}
// initialise to zero
for(int x = 0; x < PageSize; ++x) h_sums[x] = 0L;
int rows = (N / 1024) + 1;
int pages = (rows / 190000) + 1;
printf("N: %ld rows: %d pages: %d\n", N, rows, pages);
long Sum = 0;
long counted = 0;
for(int pg = 0; pg < pages; ++pg) {
// launch kernel with appropriate parameters
func_g<<<rows,1024>>>(d_squares, limit, d_sums, N, PageSize, pg);
// device sync and test for errors
error_id = hipDeviceSynchronize();
if(error_id != hipSuccess) {
printf("cudaDeviceSync returned %d\n", error_id);
exit(0);
}
// copy device sums to host
error_id = hipMemcpy(h_sums, d_sums, sizeof(long)*PageSize, hipMemcpyDeviceToHost);
// DEBUG
for(int x = 0; ((x<PageSize)&&(counted < N)); ++x,++counted) {
printf("%d:%ld ",x,h_sums[x]);
}
printf("\n"); goto exit;
// END DEBUG
#if(0)
// Update S by summing last returned page page
for(int x = 0; ((x<20)&&(counted < N)); ++x,++counted) {
Sum += h_sums[x];
}
#endif
}
exit:
// Output Result as S(N) = S
printf("S(%ld) = %ld.\n", N, Sum);
// CleanUp
free(h_sums);
hipFree(d_sums);
return 0;
} | .text
.file "dSumSquares.hip"
.globl _Z26__device_stub__set_squaresPll # -- Begin function _Z26__device_stub__set_squaresPll
.p2align 4, 0x90
.type _Z26__device_stub__set_squaresPll,@function
_Z26__device_stub__set_squaresPll: # @_Z26__device_stub__set_squaresPll
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11set_squaresPll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__set_squaresPll, .Lfunc_end0-_Z26__device_stub__set_squaresPll
.cfi_endproc
# -- End function
.globl _Z21__device_stub__func_gPllS_lli # -- Begin function _Z21__device_stub__func_gPllS_lli
.p2align 4, 0x90
.type _Z21__device_stub__func_gPllS_lli,@function
_Z21__device_stub__func_gPllS_lli: # @_Z21__device_stub__func_gPllS_lli
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6func_gPllS_lli, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z21__device_stub__func_gPllS_lli, .Lfunc_end1-_Z21__device_stub__func_gPllS_lli
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 8(%rsp)
movq $0, (%rsp)
cmpl $2, %edi
jne .LBB2_31
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
cmpq $1000000001, %rax # imm = 0x3B9ACA01
jge .LBB2_32
# %bb.2:
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
cvtsi2sd %rbx, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB2_4
# %bb.3:
sqrtsd %xmm0, %xmm0
ucomisd %xmm1, %xmm0
jae .LBB2_6
.LBB2_7: # %call.sqrt106
callq sqrt
jmp .LBB2_8
.LBB2_4: # %call.sqrt
callq sqrt
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB2_7
.LBB2_6:
sqrtsd %xmm0, %xmm0
.LBB2_8: # %.split.split
addsd .LCPI2_0(%rip), %xmm0
cvttsd2si %xmm0, %r14
movl $.L.str.3, %edi
movq %rbx, %rsi
movq %r14, %rdx
xorl %eax, %eax
callq printf
leaq (,%r14,8), %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_9
# %bb.11:
movabsq $4294967296, %r12 # imm = 0x100000000
movl $.Lstr.1, %edi
callq puts@PLT
movl %r14d, %edx
orq %r12, %rdx
leaq 1(%r12), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %r14, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11set_squaresPll, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
callq hipDeviceSynchronize
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq 8(%rsp), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testq %r14, %r14
jle .LBB2_16
# %bb.14: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_15: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%r13,%r15,8), %rdx
movl $.L.str.6, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_15
.LBB2_16: # %._crit_edge
movl $10, %edi
callq putchar@PLT
movq %r13, %rdi
callq free
movq %rsp, %rdi
movl $1556480000, %esi # imm = 0x5CC60000
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.18:
movl $1556480000, %edi # imm = 0x5CC60000
callq malloc
testq %rax, %rax
je .LBB2_33
# %bb.19: # %.preheader.preheader
movq %rax, %r15
movl $1556480000, %edx # imm = 0x5CC60000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 1023(%rbx), %rbp
testq %rbx, %rbx
cmovnsq %rbx, %rbp
shrq $10, %rbp
incl %ebp
movslq %ebp, %r13
imulq $740723623, %r13, %rax # imm = 0x2C268BA7
movq %rax, %rcx
sarq $47, %rcx
shrq $63, %rax
addl %eax, %ecx
incl %ecx
movl $.L.str.10, %edi
movq %rbx, %rsi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl $8, %eax
cmpl $-190000, %r13d # imm = 0xFFFD19D0
jle .LBB2_27
# %bb.20:
movl %ebp, %edi
orq %r12, %rdi
addq $1024, %r12 # imm = 0x400
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_22
# %bb.21:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %r14, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rbx, 48(%rsp)
movq $194560000, 104(%rsp) # imm = 0xB98C000
movl $0, 84(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 84(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6func_gPllS_lli, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_22:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_34
# %bb.23:
movq (%rsp), %rsi
movl $1556480000, %edx # imm = 0x5CC60000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testq %rbx, %rbx
jle .LBB2_26
# %bb.24: # %.lr.ph99.preheader
movq %rbx, %rax
decq %rax
cmpq $194559999, %rax # imm = 0xB98BFFF
movl $194559999, %r12d # imm = 0xB98BFFF
cmovbq %rax, %r12
incq %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_25: # %.lr.ph99
# =>This Inner Loop Header: Depth=1
movq (%r15,%r14,8), %rdx
movl $.L.str.6, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB2_25
.LBB2_26: # %._crit_edge100
movl $10, %edi
callq putchar@PLT
movl $14, %eax
.LBB2_27:
cmpl $14, %eax
je .LBB2_29
# %bb.28:
cmpl $8, %eax
jne .LBB2_30
.LBB2_29:
movl $.L.str.12, %edi
movq %rbx, %rsi
xorl %edx, %edx
xorl %eax, %eax
callq printf
movq %r15, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
.LBB2_30:
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_31:
.cfi_def_cfa_offset 224
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB2_32:
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $2, %edi
callq exit
.LBB2_9:
movl $.L.str.4, %edi
jmp .LBB2_10
.LBB2_17:
movl $.L.str.8, %edi
.LBB2_10:
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB2_33:
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB2_34:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11set_squaresPll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6func_gPllS_lli, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11set_squaresPll,@object # @_Z11set_squaresPll
.section .rodata,"a",@progbits
.globl _Z11set_squaresPll
.p2align 3, 0x0
_Z11set_squaresPll:
.quad _Z26__device_stub__set_squaresPll
.size _Z11set_squaresPll, 8
.type _Z6func_gPllS_lli,@object # @_Z6func_gPllS_lli
.globl _Z6func_gPllS_lli
.p2align 3, 0x0
_Z6func_gPllS_lli:
.quad _Z21__device_stub__func_gPllS_lli
.size _Z6func_gPllS_lli, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "target: %ld\n"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "target: %ld exceeds program limitations (1e9)\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "target: %ld\t\tlimit: %ld\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc squares failed with %d\n"
.size .L.str.4, 34
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d:%ld "
.size .L.str.6, 9
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMalloc d_sums failed with %d\n"
.size .L.str.8, 33
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to malloc h_sums."
.size .L.str.9, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "N: %ld\trows: %d\tpages: %d\n"
.size .L.str.10, 27
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "cudaDeviceSync returned %d\n"
.size .L.str.11, 28
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "S(%ld) = %ld.\n"
.size .L.str.12, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11set_squaresPll"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6func_gPllS_lli"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: css target (< 1e9)"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nGenerating squares"
.size .Lstr.1, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__set_squaresPll
.addrsig_sym _Z21__device_stub__func_gPllS_lli
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11set_squaresPll
.addrsig_sym _Z6func_gPllS_lli
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001299d_00000000-6_dSumSquares.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z11set_squaresPllPll
.type _Z32__device_stub__Z11set_squaresPllPll, @function
_Z32__device_stub__Z11set_squaresPllPll:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11set_squaresPll(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z32__device_stub__Z11set_squaresPllPll, .-_Z32__device_stub__Z11set_squaresPllPll
.globl _Z11set_squaresPll
.type _Z11set_squaresPll, @function
_Z11set_squaresPll:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z11set_squaresPllPll
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11set_squaresPll, .-_Z11set_squaresPll
.globl _Z31__device_stub__Z6func_gPllS_lliPllS_lli
.type _Z31__device_stub__Z6func_gPllS_lliPllS_lli, @function
_Z31__device_stub__Z6func_gPllS_lliPllS_lli:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movl %r9d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z6func_gPllS_lli(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z31__device_stub__Z6func_gPllS_lliPllS_lli, .-_Z31__device_stub__Z6func_gPllS_lliPllS_lli
.globl _Z6func_gPllS_lli
.type _Z6func_gPllS_lli, @function
_Z6func_gPllS_lli:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z6func_gPllS_lliPllS_lli
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z6func_gPllS_lli, .-_Z6func_gPllS_lli
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "usage: css target (< 1e9)\n"
.LC1:
.string "target: %ld\n"
.LC4:
.string "target: %ld\t\tlimit: %ld\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC5:
.string "target: %ld exceeds program limitations (1e9)\n"
.align 8
.LC6:
.string "cudaMalloc squares failed with %d\n"
.section .rodata.str1.1
.LC7:
.string "\nGenerating squares\n"
.LC8:
.string "%d:%ld "
.LC9:
.string "\n"
.section .rodata.str1.8
.align 8
.LC10:
.string "cudaMalloc d_sums failed with %d\n"
.section .rodata.str1.1
.LC11:
.string "Failed to malloc h_sums."
.LC12:
.string "N: %ld\trows: %d\tpages: %d\n"
.LC13:
.string "cudaDeviceSync returned %d\n"
.LC14:
.string "S(%ld) = %ld.\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq $0, (%rsp)
movq $0, 8(%rsp)
cmpl $2, %edi
jne .L20
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
cmpq $1000000000, %rax
jg .L54
movq %rax, %rdx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdq %rbp, %xmm0
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L50
sqrtsd %xmm0, %xmm0
.L25:
pxor %xmm1, %xmm1
ucomisd %xmm0, %xmm1
ja .L51
sqrtsd %xmm0, %xmm0
.L28:
addsd .LC3(%rip), %xmm0
cvttsd2siq %xmm0, %r12
movq %r12, %rcx
movq %rbp, %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 0(,%r12,8), %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
testl %eax, %eax
jne .L55
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L56
.L31:
call cudaDeviceSynchronize@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r13
movl $2, %ecx
movq %rbx, %rdx
movq (%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
testq %r12, %r12
jle .L32
movl $0, %ebx
leaq .LC8(%rip), %r14
.L33:
movq 0(%r13,%rbx,8), %rcx
movq %rbx, %rdx
movq %r14, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq %rbx, %r12
jne .L33
.L32:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
leaq 8(%rsp), %rdi
movl $1556480000, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L57
movl $1556480000, %edi
call malloc@PLT
movq %rax, %r13
testq %rax, %rax
je .L58
leaq 1556480000(%rax), %rdx
.L36:
movq $0, (%rax)
addq $8, %rax
cmpq %rdx, %rax
jne .L36
leaq 1023(%rbp), %r14
testq %rbp, %rbp
cmovns %rbp, %r14
sarq $10, %r14
addl $1, %r14d
movslq %r14d, %rbx
imulq $740723623, %rbx, %rbx
sarq $47, %rbx
movl %r14d, %eax
sarl $31, %eax
subl %eax, %ebx
addl $1, %ebx
movl %ebx, %r8d
movl %r14d, %ecx
movq %rbp, %rdx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
testl %ebx, %ebx
jle .L37
movl $1024, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %r14d, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L59
.L38:
call cudaDeviceSynchronize@PLT
testl %eax, %eax
je .L39
movl %eax, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L20:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L50:
call sqrt@PLT
jmp .L25
.L51:
call sqrt@PLT
jmp .L28
.L54:
movq %rax, %rdx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %edi
call exit@PLT
.L55:
movl %eax, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L56:
movq %r12, %rsi
movq (%rsp), %rdi
call _Z32__device_stub__Z11set_squaresPllPll
jmp .L31
.L57:
movl %eax, %edx
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L58:
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L59:
movl $0, %r9d
movl $194560000, %r8d
movq %rbp, %rcx
movq 8(%rsp), %rdx
movq %r12, %rsi
movq (%rsp), %rdi
call _Z31__device_stub__Z6func_gPllS_lliPllS_lli
jmp .L38
.L39:
movl $2, %ecx
movl $1556480000, %edx
movq 8(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
testq %rbp, %rbp
jle .L40
movl $0, %ebx
leaq .LC8(%rip), %r12
.L41:
movq 0(%r13,%rbx,8), %rcx
movl %ebx, %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl $194559999, %ebx
jg .L40
cmpq %rbp, %rbx
jl .L41
.L40:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L37:
movl $0, %ecx
movq %rbp, %rdx
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %r13, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L60
movl $0, %eax
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z6func_gPllS_lli"
.LC16:
.string "_Z11set_squaresPll"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z6func_gPllS_lli(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z11set_squaresPll(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "dSumSquares.hip"
.globl _Z26__device_stub__set_squaresPll # -- Begin function _Z26__device_stub__set_squaresPll
.p2align 4, 0x90
.type _Z26__device_stub__set_squaresPll,@function
_Z26__device_stub__set_squaresPll: # @_Z26__device_stub__set_squaresPll
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11set_squaresPll, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__set_squaresPll, .Lfunc_end0-_Z26__device_stub__set_squaresPll
.cfi_endproc
# -- End function
.globl _Z21__device_stub__func_gPllS_lli # -- Begin function _Z21__device_stub__func_gPllS_lli
.p2align 4, 0x90
.type _Z21__device_stub__func_gPllS_lli,@function
_Z21__device_stub__func_gPllS_lli: # @_Z21__device_stub__func_gPllS_lli
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movl %r9d, 4(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 4(%rsp), %rax
movq %rax, 136(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z6func_gPllS_lli, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z21__device_stub__func_gPllS_lli, .Lfunc_end1-_Z21__device_stub__func_gPllS_lli
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq $0, 8(%rsp)
movq $0, (%rsp)
cmpl $2, %edi
jne .LBB2_31
# %bb.1:
movq 8(%rsi), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
cmpq $1000000001, %rax # imm = 0x3B9ACA01
jge .LBB2_32
# %bb.2:
movl $.L.str.1, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
cvtsi2sd %rbx, %xmm0
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB2_4
# %bb.3:
sqrtsd %xmm0, %xmm0
ucomisd %xmm1, %xmm0
jae .LBB2_6
.LBB2_7: # %call.sqrt106
callq sqrt
jmp .LBB2_8
.LBB2_4: # %call.sqrt
callq sqrt
xorpd %xmm1, %xmm1
ucomisd %xmm1, %xmm0
jb .LBB2_7
.LBB2_6:
sqrtsd %xmm0, %xmm0
.LBB2_8: # %.split.split
addsd .LCPI2_0(%rip), %xmm0
cvttsd2si %xmm0, %r14
movl $.L.str.3, %edi
movq %rbx, %rsi
movq %r14, %rdx
xorl %eax, %eax
callq printf
leaq (,%r14,8), %r15
leaq 8(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
testl %eax, %eax
jne .LBB2_9
# %bb.11:
movabsq $4294967296, %r12 # imm = 0x100000000
movl $.Lstr.1, %edi
callq puts@PLT
movl %r14d, %edx
orq %r12, %rdx
leaq 1(%r12), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_13
# %bb.12:
movq 8(%rsp), %rax
movq %rax, 72(%rsp)
movq %r14, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11set_squaresPll, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_13:
callq hipDeviceSynchronize
movq %r15, %rdi
callq malloc
movq %rax, %r13
movq 8(%rsp), %rsi
movq %rax, %rdi
movq %r15, %rdx
movl $2, %ecx
callq hipMemcpy
testq %r14, %r14
jle .LBB2_16
# %bb.14: # %.lr.ph.preheader
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_15: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movq (%r13,%r15,8), %rdx
movl $.L.str.6, %edi
movq %r15, %rsi
xorl %eax, %eax
callq printf
incq %r15
cmpq %r15, %r14
jne .LBB2_15
.LBB2_16: # %._crit_edge
movl $10, %edi
callq putchar@PLT
movq %r13, %rdi
callq free
movq %rsp, %rdi
movl $1556480000, %esi # imm = 0x5CC60000
callq hipMalloc
testl %eax, %eax
jne .LBB2_17
# %bb.18:
movl $1556480000, %edi # imm = 0x5CC60000
callq malloc
testq %rax, %rax
je .LBB2_33
# %bb.19: # %.preheader.preheader
movq %rax, %r15
movl $1556480000, %edx # imm = 0x5CC60000
movq %rax, %rdi
xorl %esi, %esi
callq memset@PLT
leaq 1023(%rbx), %rbp
testq %rbx, %rbx
cmovnsq %rbx, %rbp
shrq $10, %rbp
incl %ebp
movslq %ebp, %r13
imulq $740723623, %r13, %rax # imm = 0x2C268BA7
movq %rax, %rcx
sarq $47, %rcx
shrq $63, %rax
addl %eax, %ecx
incl %ecx
movl $.L.str.10, %edi
movq %rbx, %rsi
movl %r13d, %edx
xorl %eax, %eax
callq printf
movl $8, %eax
cmpl $-190000, %r13d # imm = 0xFFFD19D0
jle .LBB2_27
# %bb.20:
movl %ebp, %edi
orq %r12, %rdi
addq $1024, %r12 # imm = 0x400
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_22
# %bb.21:
movq 8(%rsp), %rax
movq (%rsp), %rcx
movq %rax, 72(%rsp)
movq %r14, 64(%rsp)
movq %rcx, 56(%rsp)
movq %rbx, 48(%rsp)
movq $194560000, 104(%rsp) # imm = 0xB98C000
movl $0, 84(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 84(%rsp), %rax
movq %rax, 152(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 96(%rsp), %rdx
leaq 88(%rsp), %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6func_gPllS_lli, %edi
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_22:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB2_34
# %bb.23:
movq (%rsp), %rsi
movl $1556480000, %edx # imm = 0x5CC60000
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
testq %rbx, %rbx
jle .LBB2_26
# %bb.24: # %.lr.ph99.preheader
movq %rbx, %rax
decq %rax
cmpq $194559999, %rax # imm = 0xB98BFFF
movl $194559999, %r12d # imm = 0xB98BFFF
cmovbq %rax, %r12
incq %r12
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_25: # %.lr.ph99
# =>This Inner Loop Header: Depth=1
movq (%r15,%r14,8), %rdx
movl $.L.str.6, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
incq %r14
cmpq %r14, %r12
jne .LBB2_25
.LBB2_26: # %._crit_edge100
movl $10, %edi
callq putchar@PLT
movl $14, %eax
.LBB2_27:
cmpl $14, %eax
je .LBB2_29
# %bb.28:
cmpl $8, %eax
jne .LBB2_30
.LBB2_29:
movl $.L.str.12, %edi
movq %rbx, %rsi
xorl %edx, %edx
xorl %eax, %eax
callq printf
movq %r15, %rdi
callq free
movq (%rsp), %rdi
callq hipFree
.LBB2_30:
xorl %eax, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_31:
.cfi_def_cfa_offset 224
movl $.Lstr, %edi
callq puts@PLT
movl $1, %edi
callq exit
.LBB2_32:
movl $.L.str.2, %edi
movq %rbx, %rsi
xorl %eax, %eax
callq printf
movl $2, %edi
callq exit
.LBB2_9:
movl $.L.str.4, %edi
jmp .LBB2_10
.LBB2_17:
movl $.L.str.8, %edi
.LBB2_10:
movl %eax, %esi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB2_33:
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.LBB2_34:
movl $.L.str.11, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11set_squaresPll, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6func_gPllS_lli, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11set_squaresPll,@object # @_Z11set_squaresPll
.section .rodata,"a",@progbits
.globl _Z11set_squaresPll
.p2align 3, 0x0
_Z11set_squaresPll:
.quad _Z26__device_stub__set_squaresPll
.size _Z11set_squaresPll, 8
.type _Z6func_gPllS_lli,@object # @_Z6func_gPllS_lli
.globl _Z6func_gPllS_lli
.p2align 3, 0x0
_Z6func_gPllS_lli:
.quad _Z21__device_stub__func_gPllS_lli
.size _Z6func_gPllS_lli, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "target: %ld\n"
.size .L.str.1, 13
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "target: %ld exceeds program limitations (1e9)\n"
.size .L.str.2, 47
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "target: %ld\t\tlimit: %ld\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "hipMalloc squares failed with %d\n"
.size .L.str.4, 34
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%d:%ld "
.size .L.str.6, 9
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "hipMalloc d_sums failed with %d\n"
.size .L.str.8, 33
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to malloc h_sums."
.size .L.str.9, 25
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "N: %ld\trows: %d\tpages: %d\n"
.size .L.str.10, 27
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "cudaDeviceSync returned %d\n"
.size .L.str.11, 28
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "S(%ld) = %ld.\n"
.size .L.str.12, 15
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11set_squaresPll"
.size .L__unnamed_1, 19
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6func_gPllS_lli"
.size .L__unnamed_2, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "usage: css target (< 1e9)"
.size .Lstr, 26
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nGenerating squares"
.size .Lstr.1, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__set_squaresPll
.addrsig_sym _Z21__device_stub__func_gPllS_lli
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11set_squaresPll
.addrsig_sym _Z6func_gPllS_lli
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void sumArraysOnGPU(float *A, float *B, float *C) {
int id = threadIdx.x;
C[id] = A[id] + B[id];
} | code for sm_80
Function : _Z14sumArraysOnGPUPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void sumArraysOnGPU(float *A, float *B, float *C) {
int id = threadIdx.x;
C[id] = A[id] + B[id];
} | .file "tmpxft_001b6492_00000000-6_sumArraysOnGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_
.type _Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_, @function
_Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sumArraysOnGPUPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_, .-_Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_
.globl _Z14sumArraysOnGPUPfS_S_
.type _Z14sumArraysOnGPUPfS_S_, @function
_Z14sumArraysOnGPUPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sumArraysOnGPUPfS_S_, .-_Z14sumArraysOnGPUPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sumArraysOnGPUPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sumArraysOnGPUPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void sumArraysOnGPU(float *A, float *B, float *C) {
int id = threadIdx.x;
C[id] = A[id] + B[id];
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumArraysOnGPU(float *A, float *B, float *C) {
int id = threadIdx.x;
C[id] = A[id] + B[id];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumArraysOnGPU(float *A, float *B, float *C) {
int id = threadIdx.x;
C[id] = A[id] + B[id];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sumArraysOnGPUPfS_S_
.globl _Z14sumArraysOnGPUPfS_S_
.p2align 8
.type _Z14sumArraysOnGPUPfS_S_,@function
_Z14sumArraysOnGPUPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sumArraysOnGPUPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sumArraysOnGPUPfS_S_, .Lfunc_end0-_Z14sumArraysOnGPUPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sumArraysOnGPUPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14sumArraysOnGPUPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void sumArraysOnGPU(float *A, float *B, float *C) {
int id = threadIdx.x;
C[id] = A[id] + B[id];
} | .text
.file "sumArraysOnGPU.hip"
.globl _Z29__device_stub__sumArraysOnGPUPfS_S_ # -- Begin function _Z29__device_stub__sumArraysOnGPUPfS_S_
.p2align 4, 0x90
.type _Z29__device_stub__sumArraysOnGPUPfS_S_,@function
_Z29__device_stub__sumArraysOnGPUPfS_S_: # @_Z29__device_stub__sumArraysOnGPUPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sumArraysOnGPUPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__sumArraysOnGPUPfS_S_, .Lfunc_end0-_Z29__device_stub__sumArraysOnGPUPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sumArraysOnGPUPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sumArraysOnGPUPfS_S_,@object # @_Z14sumArraysOnGPUPfS_S_
.section .rodata,"a",@progbits
.globl _Z14sumArraysOnGPUPfS_S_
.p2align 3, 0x0
_Z14sumArraysOnGPUPfS_S_:
.quad _Z29__device_stub__sumArraysOnGPUPfS_S_
.size _Z14sumArraysOnGPUPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sumArraysOnGPUPfS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sumArraysOnGPUPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sumArraysOnGPUPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14sumArraysOnGPUPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0207 */
/*0090*/ FADD R9, R2, R5 ; /* 0x0000000502097221 */
/* 0x004fca0000000000 */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14sumArraysOnGPUPfS_S_
.globl _Z14sumArraysOnGPUPfS_S_
.p2align 8
.type _Z14sumArraysOnGPUPfS_S_,@function
_Z14sumArraysOnGPUPfS_S_:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v2
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14sumArraysOnGPUPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14sumArraysOnGPUPfS_S_, .Lfunc_end0-_Z14sumArraysOnGPUPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14sumArraysOnGPUPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14sumArraysOnGPUPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001b6492_00000000-6_sumArraysOnGPU.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_
.type _Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_, @function
_Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14sumArraysOnGPUPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_, .-_Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_
.globl _Z14sumArraysOnGPUPfS_S_
.type _Z14sumArraysOnGPUPfS_S_, @function
_Z14sumArraysOnGPUPfS_S_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14sumArraysOnGPUPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14sumArraysOnGPUPfS_S_, .-_Z14sumArraysOnGPUPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z14sumArraysOnGPUPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z14sumArraysOnGPUPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumArraysOnGPU.hip"
.globl _Z29__device_stub__sumArraysOnGPUPfS_S_ # -- Begin function _Z29__device_stub__sumArraysOnGPUPfS_S_
.p2align 4, 0x90
.type _Z29__device_stub__sumArraysOnGPUPfS_S_,@function
_Z29__device_stub__sumArraysOnGPUPfS_S_: # @_Z29__device_stub__sumArraysOnGPUPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14sumArraysOnGPUPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z29__device_stub__sumArraysOnGPUPfS_S_, .Lfunc_end0-_Z29__device_stub__sumArraysOnGPUPfS_S_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14sumArraysOnGPUPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14sumArraysOnGPUPfS_S_,@object # @_Z14sumArraysOnGPUPfS_S_
.section .rodata,"a",@progbits
.globl _Z14sumArraysOnGPUPfS_S_
.p2align 3, 0x0
_Z14sumArraysOnGPUPfS_S_:
.quad _Z29__device_stub__sumArraysOnGPUPfS_S_
.size _Z14sumArraysOnGPUPfS_S_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14sumArraysOnGPUPfS_S_"
.size .L__unnamed_1, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__sumArraysOnGPUPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14sumArraysOnGPUPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //#include <stdlib.h>
//#include <stdio.h>
//#include <curand_kernel.h>
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
////#include "../../common/book.h"
//#include "../../common/cpu_anim.h"
//#include "../../common/common.h"
//#include "../../common/TexUtils.h"
//#include "../../common/PlyBlock.h"
//
//#define DIM 1024
//#define PI 3.1415926535897932f
//#define MAX_TEMP 1.0f
//#define MIN_TEMP 0.0001f
//#define SPEED 0.00005f
//
//
////// this kernel takes in a 2-d array of floats
////// it updates the value-of-interest by a scaled value based
////// on itself and its nearest neighbors
//__global__ void blend_kernel(float *dst, bool dstOut, cudaTextureObject_t texIn, cudaTextureObject_t texOut) {
// // map from threadIdx/BlockIdx to pixel position
// int x = threadIdx.x + blockIdx.x * blockDim.x;
// int y = threadIdx.y + blockIdx.y * blockDim.y;
// int offset = x + y * blockDim.x * gridDim.x;
//
// int left = offset - 1;
// int right = offset + 1;
// if (x == 0) left++;
// if (x == DIM - 1) right--;
//
// int top = offset - DIM;
// int bottom = offset + DIM;
// if (y == 0) top += DIM;
// if (y == DIM - 1) bottom -= DIM;
//
// float t, l, c, r, b;
// if (dstOut) {
// t = tex1Dfetch<float>(texIn, top);
// l = tex1Dfetch<float>(texIn, left);
// c = tex1Dfetch<float>(texIn, offset);
// r = tex1Dfetch<float>(texIn, right);
// b = tex1Dfetch<float>(texIn, bottom);
//
// }
// else {
// t = tex1Dfetch<float>(texOut, top);
// l = tex1Dfetch<float>(texOut, left);
// c = tex1Dfetch<float>(texOut, offset);
// r = tex1Dfetch<float>(texOut, right);
// b = tex1Dfetch<float>(texOut, bottom);
// }
// dst[offset] = c + SPEED * (t + b + r + l - 4 * c);
//}
//
//
//
//void anim_gpu(AppBlock *appBlock, int ticks) {
// //HANDLE_ERROR(cudaEventRecord(appBlock->start, 0));
// //dim3 blocks(DIM / 16, DIM / 16);
// //dim3 threads(16, 16);
// //CPUAnimBitmap *bitmap = appBlock->bitmap;
//
// //// since tex is global and bound, we have to use a flag to
// //// select which is in/out per iteration
// //volatile bool dstOut = true;
// //for (int i = 0; i<100; i++) {
// // float *in, *out;
// // if (dstOut) {
// // in = appBlock->d->dev_inSrc;
// // out = appBlock->d->dev_outSrc;
// // }
// // else {
// // out = appBlock->d->dev_inSrc;
// // in = appBlock->d->dev_outSrc;
// // }
// // blend_kernel << <blocks, threads >> >(out, dstOut, *appBlock->d->texIn, *appBlock->d->texOut);
// // dstOut = !dstOut;
// //}
//
// //float_to_color << <blocks, threads >> >(appBlock->d->output_bitmap, appBlock->d->dev_outSrc);
//
// //HANDLE_ERROR(cudaMemcpy(bitmap->get_ptr(),
// // d->output_bitmap,
// // bitmap->image_size(),
// // cudaMemcpyDeviceToHost));
//
// //HANDLE_ERROR(cudaEventRecord(appBlock->stop, 0));
// //HANDLE_ERROR(cudaEventSynchronize(d->stop));
// //float elapsedTime;
// //HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime,
// // d->start, d->stop));
// //d->totalTime += elapsedTime;
// //++d->frames;
// //printf("Average Time per frame: %3.1f ms\n", d->totalTime / d->frames);
// //printf("tic: %d\n\n", ticks);
//}
//
//// clean up memory allocated on the GPU
//
//void anim_exit(AppBlock *d) {
//
// //cudaDestroyTextureObject(*(d->texIn));
// //cudaDestroyTextureObject(*d->texOut);
// //cudaDestroyTextureObject(*d->texConst);
//
// //HANDLE_ERROR(cudaFree(d->dev_inSrc));
// //HANDLE_ERROR(cudaFree(d->dev_outSrc));
// //HANDLE_ERROR(cudaFree(d->dev_constSrc));
//
// //HANDLE_ERROR(cudaEventDestroy(d->start));
// //HANDLE_ERROR(cudaEventDestroy(d->stop));
//}
//
//
////int main(void)
////{
//// PlyBlock data;
//// CPUAnimBitmap bitmap(DIM, DIM, &data);
//// data.bitmap = &bitmap;
//// data.totalTime = 0;
//// data.frames = 0;
//// HANDLE_ERROR(cudaEventCreate(&data.start));
//// HANDLE_ERROR(cudaEventCreate(&data.stop));
////
//// int imageSize = bitmap.image_size();
////
//// HANDLE_ERROR(cudaMalloc((void**)&data.output_bitmap,
//// imageSize));
////
//// // assume float == 4 chars in size (ie rgba)
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_inSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_outSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_constSrc, imageSize));
////
////
//// data.texIn = TexObjFloat1D(data.dev_inSrc, imageSize);
//// data.texOut = TexObjFloat1D(data.dev_outSrc, imageSize);
//// data.texConst = TexObjFloat1D(data.dev_constSrc, imageSize);
////
////
////
//// // intialize the constant data
//// float *temp = RndFloat0to1(DIM*DIM);
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_constSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
////
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_inSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
//// free(temp);
////
//// bitmap.anim_and_exit((void(*)(void*, int))anim_gpu,
//// (void(*)(void*))anim_exit);
////} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //#include <stdlib.h>
//#include <stdio.h>
//#include <curand_kernel.h>
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
////#include "../../common/book.h"
//#include "../../common/cpu_anim.h"
//#include "../../common/common.h"
//#include "../../common/TexUtils.h"
//#include "../../common/PlyBlock.h"
//
//#define DIM 1024
//#define PI 3.1415926535897932f
//#define MAX_TEMP 1.0f
//#define MIN_TEMP 0.0001f
//#define SPEED 0.00005f
//
//
////// this kernel takes in a 2-d array of floats
////// it updates the value-of-interest by a scaled value based
////// on itself and its nearest neighbors
//__global__ void blend_kernel(float *dst, bool dstOut, cudaTextureObject_t texIn, cudaTextureObject_t texOut) {
// // map from threadIdx/BlockIdx to pixel position
// int x = threadIdx.x + blockIdx.x * blockDim.x;
// int y = threadIdx.y + blockIdx.y * blockDim.y;
// int offset = x + y * blockDim.x * gridDim.x;
//
// int left = offset - 1;
// int right = offset + 1;
// if (x == 0) left++;
// if (x == DIM - 1) right--;
//
// int top = offset - DIM;
// int bottom = offset + DIM;
// if (y == 0) top += DIM;
// if (y == DIM - 1) bottom -= DIM;
//
// float t, l, c, r, b;
// if (dstOut) {
// t = tex1Dfetch<float>(texIn, top);
// l = tex1Dfetch<float>(texIn, left);
// c = tex1Dfetch<float>(texIn, offset);
// r = tex1Dfetch<float>(texIn, right);
// b = tex1Dfetch<float>(texIn, bottom);
//
// }
// else {
// t = tex1Dfetch<float>(texOut, top);
// l = tex1Dfetch<float>(texOut, left);
// c = tex1Dfetch<float>(texOut, offset);
// r = tex1Dfetch<float>(texOut, right);
// b = tex1Dfetch<float>(texOut, bottom);
// }
// dst[offset] = c + SPEED * (t + b + r + l - 4 * c);
//}
//
//
//
//void anim_gpu(AppBlock *appBlock, int ticks) {
// //HANDLE_ERROR(cudaEventRecord(appBlock->start, 0));
// //dim3 blocks(DIM / 16, DIM / 16);
// //dim3 threads(16, 16);
// //CPUAnimBitmap *bitmap = appBlock->bitmap;
//
// //// since tex is global and bound, we have to use a flag to
// //// select which is in/out per iteration
// //volatile bool dstOut = true;
// //for (int i = 0; i<100; i++) {
// // float *in, *out;
// // if (dstOut) {
// // in = appBlock->d->dev_inSrc;
// // out = appBlock->d->dev_outSrc;
// // }
// // else {
// // out = appBlock->d->dev_inSrc;
// // in = appBlock->d->dev_outSrc;
// // }
// // blend_kernel << <blocks, threads >> >(out, dstOut, *appBlock->d->texIn, *appBlock->d->texOut);
// // dstOut = !dstOut;
// //}
//
// //float_to_color << <blocks, threads >> >(appBlock->d->output_bitmap, appBlock->d->dev_outSrc);
//
// //HANDLE_ERROR(cudaMemcpy(bitmap->get_ptr(),
// // d->output_bitmap,
// // bitmap->image_size(),
// // cudaMemcpyDeviceToHost));
//
// //HANDLE_ERROR(cudaEventRecord(appBlock->stop, 0));
// //HANDLE_ERROR(cudaEventSynchronize(d->stop));
// //float elapsedTime;
// //HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime,
// // d->start, d->stop));
// //d->totalTime += elapsedTime;
// //++d->frames;
// //printf("Average Time per frame: %3.1f ms\n", d->totalTime / d->frames);
// //printf("tic: %d\n\n", ticks);
//}
//
//// clean up memory allocated on the GPU
//
//void anim_exit(AppBlock *d) {
//
// //cudaDestroyTextureObject(*(d->texIn));
// //cudaDestroyTextureObject(*d->texOut);
// //cudaDestroyTextureObject(*d->texConst);
//
// //HANDLE_ERROR(cudaFree(d->dev_inSrc));
// //HANDLE_ERROR(cudaFree(d->dev_outSrc));
// //HANDLE_ERROR(cudaFree(d->dev_constSrc));
//
// //HANDLE_ERROR(cudaEventDestroy(d->start));
// //HANDLE_ERROR(cudaEventDestroy(d->stop));
//}
//
//
////int main(void)
////{
//// PlyBlock data;
//// CPUAnimBitmap bitmap(DIM, DIM, &data);
//// data.bitmap = &bitmap;
//// data.totalTime = 0;
//// data.frames = 0;
//// HANDLE_ERROR(cudaEventCreate(&data.start));
//// HANDLE_ERROR(cudaEventCreate(&data.stop));
////
//// int imageSize = bitmap.image_size();
////
//// HANDLE_ERROR(cudaMalloc((void**)&data.output_bitmap,
//// imageSize));
////
//// // assume float == 4 chars in size (ie rgba)
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_inSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_outSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_constSrc, imageSize));
////
////
//// data.texIn = TexObjFloat1D(data.dev_inSrc, imageSize);
//// data.texOut = TexObjFloat1D(data.dev_outSrc, imageSize);
//// data.texConst = TexObjFloat1D(data.dev_constSrc, imageSize);
////
////
////
//// // intialize the constant data
//// float *temp = RndFloat0to1(DIM*DIM);
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_constSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
////
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_inSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
//// free(temp);
////
//// bitmap.anim_and_exit((void(*)(void*, int))anim_gpu,
//// (void(*)(void*))anim_exit);
////} | .file "tmpxft_00146efd_00000000-6_Isingo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //#include <stdlib.h>
//#include <stdio.h>
//#include <curand_kernel.h>
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
////#include "../../common/book.h"
//#include "../../common/cpu_anim.h"
//#include "../../common/common.h"
//#include "../../common/TexUtils.h"
//#include "../../common/PlyBlock.h"
//
//#define DIM 1024
//#define PI 3.1415926535897932f
//#define MAX_TEMP 1.0f
//#define MIN_TEMP 0.0001f
//#define SPEED 0.00005f
//
//
////// this kernel takes in a 2-d array of floats
////// it updates the value-of-interest by a scaled value based
////// on itself and its nearest neighbors
//__global__ void blend_kernel(float *dst, bool dstOut, cudaTextureObject_t texIn, cudaTextureObject_t texOut) {
// // map from threadIdx/BlockIdx to pixel position
// int x = threadIdx.x + blockIdx.x * blockDim.x;
// int y = threadIdx.y + blockIdx.y * blockDim.y;
// int offset = x + y * blockDim.x * gridDim.x;
//
// int left = offset - 1;
// int right = offset + 1;
// if (x == 0) left++;
// if (x == DIM - 1) right--;
//
// int top = offset - DIM;
// int bottom = offset + DIM;
// if (y == 0) top += DIM;
// if (y == DIM - 1) bottom -= DIM;
//
// float t, l, c, r, b;
// if (dstOut) {
// t = tex1Dfetch<float>(texIn, top);
// l = tex1Dfetch<float>(texIn, left);
// c = tex1Dfetch<float>(texIn, offset);
// r = tex1Dfetch<float>(texIn, right);
// b = tex1Dfetch<float>(texIn, bottom);
//
// }
// else {
// t = tex1Dfetch<float>(texOut, top);
// l = tex1Dfetch<float>(texOut, left);
// c = tex1Dfetch<float>(texOut, offset);
// r = tex1Dfetch<float>(texOut, right);
// b = tex1Dfetch<float>(texOut, bottom);
// }
// dst[offset] = c + SPEED * (t + b + r + l - 4 * c);
//}
//
//
//
//void anim_gpu(AppBlock *appBlock, int ticks) {
// //HANDLE_ERROR(cudaEventRecord(appBlock->start, 0));
// //dim3 blocks(DIM / 16, DIM / 16);
// //dim3 threads(16, 16);
// //CPUAnimBitmap *bitmap = appBlock->bitmap;
//
// //// since tex is global and bound, we have to use a flag to
// //// select which is in/out per iteration
// //volatile bool dstOut = true;
// //for (int i = 0; i<100; i++) {
// // float *in, *out;
// // if (dstOut) {
// // in = appBlock->d->dev_inSrc;
// // out = appBlock->d->dev_outSrc;
// // }
// // else {
// // out = appBlock->d->dev_inSrc;
// // in = appBlock->d->dev_outSrc;
// // }
// // blend_kernel << <blocks, threads >> >(out, dstOut, *appBlock->d->texIn, *appBlock->d->texOut);
// // dstOut = !dstOut;
// //}
//
// //float_to_color << <blocks, threads >> >(appBlock->d->output_bitmap, appBlock->d->dev_outSrc);
//
// //HANDLE_ERROR(cudaMemcpy(bitmap->get_ptr(),
// // d->output_bitmap,
// // bitmap->image_size(),
// // cudaMemcpyDeviceToHost));
//
// //HANDLE_ERROR(cudaEventRecord(appBlock->stop, 0));
// //HANDLE_ERROR(cudaEventSynchronize(d->stop));
// //float elapsedTime;
// //HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime,
// // d->start, d->stop));
// //d->totalTime += elapsedTime;
// //++d->frames;
// //printf("Average Time per frame: %3.1f ms\n", d->totalTime / d->frames);
// //printf("tic: %d\n\n", ticks);
//}
//
//// clean up memory allocated on the GPU
//
//void anim_exit(AppBlock *d) {
//
// //cudaDestroyTextureObject(*(d->texIn));
// //cudaDestroyTextureObject(*d->texOut);
// //cudaDestroyTextureObject(*d->texConst);
//
// //HANDLE_ERROR(cudaFree(d->dev_inSrc));
// //HANDLE_ERROR(cudaFree(d->dev_outSrc));
// //HANDLE_ERROR(cudaFree(d->dev_constSrc));
//
// //HANDLE_ERROR(cudaEventDestroy(d->start));
// //HANDLE_ERROR(cudaEventDestroy(d->stop));
//}
//
//
////int main(void)
////{
//// PlyBlock data;
//// CPUAnimBitmap bitmap(DIM, DIM, &data);
//// data.bitmap = &bitmap;
//// data.totalTime = 0;
//// data.frames = 0;
//// HANDLE_ERROR(cudaEventCreate(&data.start));
//// HANDLE_ERROR(cudaEventCreate(&data.stop));
////
//// int imageSize = bitmap.image_size();
////
//// HANDLE_ERROR(cudaMalloc((void**)&data.output_bitmap,
//// imageSize));
////
//// // assume float == 4 chars in size (ie rgba)
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_inSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_outSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_constSrc, imageSize));
////
////
//// data.texIn = TexObjFloat1D(data.dev_inSrc, imageSize);
//// data.texOut = TexObjFloat1D(data.dev_outSrc, imageSize);
//// data.texConst = TexObjFloat1D(data.dev_constSrc, imageSize);
////
////
////
//// // intialize the constant data
//// float *temp = RndFloat0to1(DIM*DIM);
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_constSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
////
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_inSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
//// free(temp);
////
//// bitmap.anim_and_exit((void(*)(void*, int))anim_gpu,
//// (void(*)(void*))anim_exit);
////} | #include <hip/hip_runtime.h>
//#include <stdlib.h>
//#include <stdio.h>
//#include <curand_kernel.h>
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
////#include "../../common/book.h"
//#include "../../common/cpu_anim.h"
//#include "../../common/common.h"
//#include "../../common/TexUtils.h"
//#include "../../common/PlyBlock.h"
//
//#define DIM 1024
//#define PI 3.1415926535897932f
//#define MAX_TEMP 1.0f
//#define MIN_TEMP 0.0001f
//#define SPEED 0.00005f
//
//
////// this kernel takes in a 2-d array of floats
////// it updates the value-of-interest by a scaled value based
////// on itself and its nearest neighbors
//__global__ void blend_kernel(float *dst, bool dstOut, cudaTextureObject_t texIn, cudaTextureObject_t texOut) {
// // map from threadIdx/BlockIdx to pixel position
// int x = threadIdx.x + blockIdx.x * blockDim.x;
// int y = threadIdx.y + blockIdx.y * blockDim.y;
// int offset = x + y * blockDim.x * gridDim.x;
//
// int left = offset - 1;
// int right = offset + 1;
// if (x == 0) left++;
// if (x == DIM - 1) right--;
//
// int top = offset - DIM;
// int bottom = offset + DIM;
// if (y == 0) top += DIM;
// if (y == DIM - 1) bottom -= DIM;
//
// float t, l, c, r, b;
// if (dstOut) {
// t = tex1Dfetch<float>(texIn, top);
// l = tex1Dfetch<float>(texIn, left);
// c = tex1Dfetch<float>(texIn, offset);
// r = tex1Dfetch<float>(texIn, right);
// b = tex1Dfetch<float>(texIn, bottom);
//
// }
// else {
// t = tex1Dfetch<float>(texOut, top);
// l = tex1Dfetch<float>(texOut, left);
// c = tex1Dfetch<float>(texOut, offset);
// r = tex1Dfetch<float>(texOut, right);
// b = tex1Dfetch<float>(texOut, bottom);
// }
// dst[offset] = c + SPEED * (t + b + r + l - 4 * c);
//}
//
//
//
//void anim_gpu(AppBlock *appBlock, int ticks) {
// //HANDLE_ERROR(cudaEventRecord(appBlock->start, 0));
// //dim3 blocks(DIM / 16, DIM / 16);
// //dim3 threads(16, 16);
// //CPUAnimBitmap *bitmap = appBlock->bitmap;
//
// //// since tex is global and bound, we have to use a flag to
// //// select which is in/out per iteration
// //volatile bool dstOut = true;
// //for (int i = 0; i<100; i++) {
// // float *in, *out;
// // if (dstOut) {
// // in = appBlock->d->dev_inSrc;
// // out = appBlock->d->dev_outSrc;
// // }
// // else {
// // out = appBlock->d->dev_inSrc;
// // in = appBlock->d->dev_outSrc;
// // }
// // blend_kernel << <blocks, threads >> >(out, dstOut, *appBlock->d->texIn, *appBlock->d->texOut);
// // dstOut = !dstOut;
// //}
//
// //float_to_color << <blocks, threads >> >(appBlock->d->output_bitmap, appBlock->d->dev_outSrc);
//
// //HANDLE_ERROR(cudaMemcpy(bitmap->get_ptr(),
// // d->output_bitmap,
// // bitmap->image_size(),
// // cudaMemcpyDeviceToHost));
//
// //HANDLE_ERROR(cudaEventRecord(appBlock->stop, 0));
// //HANDLE_ERROR(cudaEventSynchronize(d->stop));
// //float elapsedTime;
// //HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime,
// // d->start, d->stop));
// //d->totalTime += elapsedTime;
// //++d->frames;
// //printf("Average Time per frame: %3.1f ms\n", d->totalTime / d->frames);
// //printf("tic: %d\n\n", ticks);
//}
//
//// clean up memory allocated on the GPU
//
//void anim_exit(AppBlock *d) {
//
// //cudaDestroyTextureObject(*(d->texIn));
// //cudaDestroyTextureObject(*d->texOut);
// //cudaDestroyTextureObject(*d->texConst);
//
// //HANDLE_ERROR(cudaFree(d->dev_inSrc));
// //HANDLE_ERROR(cudaFree(d->dev_outSrc));
// //HANDLE_ERROR(cudaFree(d->dev_constSrc));
//
// //HANDLE_ERROR(cudaEventDestroy(d->start));
// //HANDLE_ERROR(cudaEventDestroy(d->stop));
//}
//
//
////int main(void)
////{
//// PlyBlock data;
//// CPUAnimBitmap bitmap(DIM, DIM, &data);
//// data.bitmap = &bitmap;
//// data.totalTime = 0;
//// data.frames = 0;
//// HANDLE_ERROR(cudaEventCreate(&data.start));
//// HANDLE_ERROR(cudaEventCreate(&data.stop));
////
//// int imageSize = bitmap.image_size();
////
//// HANDLE_ERROR(cudaMalloc((void**)&data.output_bitmap,
//// imageSize));
////
//// // assume float == 4 chars in size (ie rgba)
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_inSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_outSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_constSrc, imageSize));
////
////
//// data.texIn = TexObjFloat1D(data.dev_inSrc, imageSize);
//// data.texOut = TexObjFloat1D(data.dev_outSrc, imageSize);
//// data.texConst = TexObjFloat1D(data.dev_constSrc, imageSize);
////
////
////
//// // intialize the constant data
//// float *temp = RndFloat0to1(DIM*DIM);
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_constSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
////
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_inSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
//// free(temp);
////
//// bitmap.anim_and_exit((void(*)(void*, int))anim_gpu,
//// (void(*)(void*))anim_exit);
////} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//#include <stdlib.h>
//#include <stdio.h>
//#include <curand_kernel.h>
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
////#include "../../common/book.h"
//#include "../../common/cpu_anim.h"
//#include "../../common/common.h"
//#include "../../common/TexUtils.h"
//#include "../../common/PlyBlock.h"
//
//#define DIM 1024
//#define PI 3.1415926535897932f
//#define MAX_TEMP 1.0f
//#define MIN_TEMP 0.0001f
//#define SPEED 0.00005f
//
//
////// this kernel takes in a 2-d array of floats
////// it updates the value-of-interest by a scaled value based
////// on itself and its nearest neighbors
//__global__ void blend_kernel(float *dst, bool dstOut, cudaTextureObject_t texIn, cudaTextureObject_t texOut) {
// // map from threadIdx/BlockIdx to pixel position
// int x = threadIdx.x + blockIdx.x * blockDim.x;
// int y = threadIdx.y + blockIdx.y * blockDim.y;
// int offset = x + y * blockDim.x * gridDim.x;
//
// int left = offset - 1;
// int right = offset + 1;
// if (x == 0) left++;
// if (x == DIM - 1) right--;
//
// int top = offset - DIM;
// int bottom = offset + DIM;
// if (y == 0) top += DIM;
// if (y == DIM - 1) bottom -= DIM;
//
// float t, l, c, r, b;
// if (dstOut) {
// t = tex1Dfetch<float>(texIn, top);
// l = tex1Dfetch<float>(texIn, left);
// c = tex1Dfetch<float>(texIn, offset);
// r = tex1Dfetch<float>(texIn, right);
// b = tex1Dfetch<float>(texIn, bottom);
//
// }
// else {
// t = tex1Dfetch<float>(texOut, top);
// l = tex1Dfetch<float>(texOut, left);
// c = tex1Dfetch<float>(texOut, offset);
// r = tex1Dfetch<float>(texOut, right);
// b = tex1Dfetch<float>(texOut, bottom);
// }
// dst[offset] = c + SPEED * (t + b + r + l - 4 * c);
//}
//
//
//
//void anim_gpu(AppBlock *appBlock, int ticks) {
// //HANDLE_ERROR(cudaEventRecord(appBlock->start, 0));
// //dim3 blocks(DIM / 16, DIM / 16);
// //dim3 threads(16, 16);
// //CPUAnimBitmap *bitmap = appBlock->bitmap;
//
// //// since tex is global and bound, we have to use a flag to
// //// select which is in/out per iteration
// //volatile bool dstOut = true;
// //for (int i = 0; i<100; i++) {
// // float *in, *out;
// // if (dstOut) {
// // in = appBlock->d->dev_inSrc;
// // out = appBlock->d->dev_outSrc;
// // }
// // else {
// // out = appBlock->d->dev_inSrc;
// // in = appBlock->d->dev_outSrc;
// // }
// // blend_kernel << <blocks, threads >> >(out, dstOut, *appBlock->d->texIn, *appBlock->d->texOut);
// // dstOut = !dstOut;
// //}
//
// //float_to_color << <blocks, threads >> >(appBlock->d->output_bitmap, appBlock->d->dev_outSrc);
//
// //HANDLE_ERROR(cudaMemcpy(bitmap->get_ptr(),
// // d->output_bitmap,
// // bitmap->image_size(),
// // cudaMemcpyDeviceToHost));
//
// //HANDLE_ERROR(cudaEventRecord(appBlock->stop, 0));
// //HANDLE_ERROR(cudaEventSynchronize(d->stop));
// //float elapsedTime;
// //HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime,
// // d->start, d->stop));
// //d->totalTime += elapsedTime;
// //++d->frames;
// //printf("Average Time per frame: %3.1f ms\n", d->totalTime / d->frames);
// //printf("tic: %d\n\n", ticks);
//}
//
//// clean up memory allocated on the GPU
//
//void anim_exit(AppBlock *d) {
//
// //cudaDestroyTextureObject(*(d->texIn));
// //cudaDestroyTextureObject(*d->texOut);
// //cudaDestroyTextureObject(*d->texConst);
//
// //HANDLE_ERROR(cudaFree(d->dev_inSrc));
// //HANDLE_ERROR(cudaFree(d->dev_outSrc));
// //HANDLE_ERROR(cudaFree(d->dev_constSrc));
//
// //HANDLE_ERROR(cudaEventDestroy(d->start));
// //HANDLE_ERROR(cudaEventDestroy(d->stop));
//}
//
//
////int main(void)
////{
//// PlyBlock data;
//// CPUAnimBitmap bitmap(DIM, DIM, &data);
//// data.bitmap = &bitmap;
//// data.totalTime = 0;
//// data.frames = 0;
//// HANDLE_ERROR(cudaEventCreate(&data.start));
//// HANDLE_ERROR(cudaEventCreate(&data.stop));
////
//// int imageSize = bitmap.image_size();
////
//// HANDLE_ERROR(cudaMalloc((void**)&data.output_bitmap,
//// imageSize));
////
//// // assume float == 4 chars in size (ie rgba)
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_inSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_outSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_constSrc, imageSize));
////
////
//// data.texIn = TexObjFloat1D(data.dev_inSrc, imageSize);
//// data.texOut = TexObjFloat1D(data.dev_outSrc, imageSize);
//// data.texConst = TexObjFloat1D(data.dev_constSrc, imageSize);
////
////
////
//// // intialize the constant data
//// float *temp = RndFloat0to1(DIM*DIM);
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_constSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
////
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_inSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
//// free(temp);
////
//// bitmap.anim_and_exit((void(*)(void*, int))anim_gpu,
//// (void(*)(void*))anim_exit);
////} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//#include <stdlib.h>
//#include <stdio.h>
//#include <curand_kernel.h>
//#include "cuda_runtime.h"
//#include "device_launch_parameters.h"
//
////#include "../../common/book.h"
//#include "../../common/cpu_anim.h"
//#include "../../common/common.h"
//#include "../../common/TexUtils.h"
//#include "../../common/PlyBlock.h"
//
//#define DIM 1024
//#define PI 3.1415926535897932f
//#define MAX_TEMP 1.0f
//#define MIN_TEMP 0.0001f
//#define SPEED 0.00005f
//
//
////// this kernel takes in a 2-d array of floats
////// it updates the value-of-interest by a scaled value based
////// on itself and its nearest neighbors
//__global__ void blend_kernel(float *dst, bool dstOut, cudaTextureObject_t texIn, cudaTextureObject_t texOut) {
// // map from threadIdx/BlockIdx to pixel position
// int x = threadIdx.x + blockIdx.x * blockDim.x;
// int y = threadIdx.y + blockIdx.y * blockDim.y;
// int offset = x + y * blockDim.x * gridDim.x;
//
// int left = offset - 1;
// int right = offset + 1;
// if (x == 0) left++;
// if (x == DIM - 1) right--;
//
// int top = offset - DIM;
// int bottom = offset + DIM;
// if (y == 0) top += DIM;
// if (y == DIM - 1) bottom -= DIM;
//
// float t, l, c, r, b;
// if (dstOut) {
// t = tex1Dfetch<float>(texIn, top);
// l = tex1Dfetch<float>(texIn, left);
// c = tex1Dfetch<float>(texIn, offset);
// r = tex1Dfetch<float>(texIn, right);
// b = tex1Dfetch<float>(texIn, bottom);
//
// }
// else {
// t = tex1Dfetch<float>(texOut, top);
// l = tex1Dfetch<float>(texOut, left);
// c = tex1Dfetch<float>(texOut, offset);
// r = tex1Dfetch<float>(texOut, right);
// b = tex1Dfetch<float>(texOut, bottom);
// }
// dst[offset] = c + SPEED * (t + b + r + l - 4 * c);
//}
//
//
//
//void anim_gpu(AppBlock *appBlock, int ticks) {
// //HANDLE_ERROR(cudaEventRecord(appBlock->start, 0));
// //dim3 blocks(DIM / 16, DIM / 16);
// //dim3 threads(16, 16);
// //CPUAnimBitmap *bitmap = appBlock->bitmap;
//
// //// since tex is global and bound, we have to use a flag to
// //// select which is in/out per iteration
// //volatile bool dstOut = true;
// //for (int i = 0; i<100; i++) {
// // float *in, *out;
// // if (dstOut) {
// // in = appBlock->d->dev_inSrc;
// // out = appBlock->d->dev_outSrc;
// // }
// // else {
// // out = appBlock->d->dev_inSrc;
// // in = appBlock->d->dev_outSrc;
// // }
// // blend_kernel << <blocks, threads >> >(out, dstOut, *appBlock->d->texIn, *appBlock->d->texOut);
// // dstOut = !dstOut;
// //}
//
// //float_to_color << <blocks, threads >> >(appBlock->d->output_bitmap, appBlock->d->dev_outSrc);
//
// //HANDLE_ERROR(cudaMemcpy(bitmap->get_ptr(),
// // d->output_bitmap,
// // bitmap->image_size(),
// // cudaMemcpyDeviceToHost));
//
// //HANDLE_ERROR(cudaEventRecord(appBlock->stop, 0));
// //HANDLE_ERROR(cudaEventSynchronize(d->stop));
// //float elapsedTime;
// //HANDLE_ERROR(cudaEventElapsedTime(&elapsedTime,
// // d->start, d->stop));
// //d->totalTime += elapsedTime;
// //++d->frames;
// //printf("Average Time per frame: %3.1f ms\n", d->totalTime / d->frames);
// //printf("tic: %d\n\n", ticks);
//}
//
//// clean up memory allocated on the GPU
//
//void anim_exit(AppBlock *d) {
//
// //cudaDestroyTextureObject(*(d->texIn));
// //cudaDestroyTextureObject(*d->texOut);
// //cudaDestroyTextureObject(*d->texConst);
//
// //HANDLE_ERROR(cudaFree(d->dev_inSrc));
// //HANDLE_ERROR(cudaFree(d->dev_outSrc));
// //HANDLE_ERROR(cudaFree(d->dev_constSrc));
//
// //HANDLE_ERROR(cudaEventDestroy(d->start));
// //HANDLE_ERROR(cudaEventDestroy(d->stop));
//}
//
//
////int main(void)
////{
//// PlyBlock data;
//// CPUAnimBitmap bitmap(DIM, DIM, &data);
//// data.bitmap = &bitmap;
//// data.totalTime = 0;
//// data.frames = 0;
//// HANDLE_ERROR(cudaEventCreate(&data.start));
//// HANDLE_ERROR(cudaEventCreate(&data.stop));
////
//// int imageSize = bitmap.image_size();
////
//// HANDLE_ERROR(cudaMalloc((void**)&data.output_bitmap,
//// imageSize));
////
//// // assume float == 4 chars in size (ie rgba)
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_inSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_outSrc, imageSize));
//// HANDLE_ERROR(cudaMalloc((void**)&data.dev_constSrc, imageSize));
////
////
//// data.texIn = TexObjFloat1D(data.dev_inSrc, imageSize);
//// data.texOut = TexObjFloat1D(data.dev_outSrc, imageSize);
//// data.texConst = TexObjFloat1D(data.dev_constSrc, imageSize);
////
////
////
//// // intialize the constant data
//// float *temp = RndFloat0to1(DIM*DIM);
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_constSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
////
////
//// HANDLE_ERROR(cudaMemcpy(data.dev_inSrc, temp, imageSize,
//// cudaMemcpyHostToDevice));
//// free(temp);
////
//// bitmap.anim_and_exit((void(*)(void*, int))anim_gpu,
//// (void(*)(void*))anim_exit);
////} | .text
.file "Isingo.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00146efd_00000000-6_Isingo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "Isingo.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*__global__ void Rotate3D(float* Destination, float* Source, int sizeX, int sizeY, float deg)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.z * blockDim.z + threadIdx.z;
int xc = sizeX - sizeX/2;
int yc = sizeY - sizeY/2;
int newx = ((float)i-xc)*cos(deg) + ((float)j-yc)*sin(deg) + xc;
int newy = -((float)i-xc)*sin(deg) + ((float)j-yc)*cos(deg) + yc;
if (newx >= 0 && newx < sizeX && newy >= 0 && newy < sizeY)
{
// putPixVal(Destination, sizeX, i , j, readPixVal(Source, sizeX, newx, newy));
Destination[k* sizeX*sizeY + j*sizeX+i] = Source[k* sizeX*sizeY + newy*sizeX + newx];
}
} */
// rotate a 3D array (2D rotate, with the third dim simultaenously processed) with bilinear interpolation
# define pi 3.141592654f
__global__ void Rotate3D_bilinear(float* Destination, float* Source, int sizeX, int sizeY, float deg)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.z * blockDim.z + threadIdx.z;
int z_offset = k*sizeX*sizeY;
int xc = sizeX - sizeX/2;
int yc = sizeY - sizeY/2;
float cos_rad = cosf(deg/180*pi);
float sin_rad = sinf(deg/180*pi);
float newx = +((float)i-xc)*cos_rad + ((float)j-yc)*sin_rad + xc ;
float newy = -((float)i-xc)*sin_rad + ((float)j-yc)*cos_rad + yc ;
int newx_0 = floorf(newx);
int newy_0 = floorf(newy);
int newx_1 = newx_0 + 1;
int newy_1 = newy_0 + 1;
// put the pixel coo. in unit square
float x = newx - float(newx_0);
float y = newy - float(newy_0);
float val_00 = 0.0, val_01 = 0.0, val_10 = 0.0, val_11 = 0.0, val_intp = 0.0;
if (newx_0 >= 0 && newx_1 < sizeX && newy_0 >= 0 && newy_1 < sizeY)
{
// perform bilinear interpolation
val_00 = Source[z_offset + newy_0*sizeX + newx_0];
val_01 = Source[z_offset + newy_1*sizeX + newx_0];
val_10 = Source[z_offset + newy_0*sizeX + newx_1];
val_11 = Source[z_offset + newy_1*sizeX + newx_1];
val_intp = val_00 + (val_01-val_00)*y + (val_10-val_00)*x + (val_11 + val_00 - val_10 - val_01)*x*y;
Destination[z_offset + j*sizeX+i] = val_intp;
}
} | .file "tmpxft_000f5613_00000000-6_imrotate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif
.type _Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif, @function
_Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17Rotate3D_bilinearPfS_iif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif, .-_Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif
.globl _Z17Rotate3D_bilinearPfS_iif
.type _Z17Rotate3D_bilinearPfS_iif, @function
_Z17Rotate3D_bilinearPfS_iif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17Rotate3D_bilinearPfS_iif, .-_Z17Rotate3D_bilinearPfS_iif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17Rotate3D_bilinearPfS_iif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17Rotate3D_bilinearPfS_iif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*__global__ void Rotate3D(float* Destination, float* Source, int sizeX, int sizeY, float deg)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.z * blockDim.z + threadIdx.z;
int xc = sizeX - sizeX/2;
int yc = sizeY - sizeY/2;
int newx = ((float)i-xc)*cos(deg) + ((float)j-yc)*sin(deg) + xc;
int newy = -((float)i-xc)*sin(deg) + ((float)j-yc)*cos(deg) + yc;
if (newx >= 0 && newx < sizeX && newy >= 0 && newy < sizeY)
{
// putPixVal(Destination, sizeX, i , j, readPixVal(Source, sizeX, newx, newy));
Destination[k* sizeX*sizeY + j*sizeX+i] = Source[k* sizeX*sizeY + newy*sizeX + newx];
}
} */
// rotate a 3D array (2D rotate, with the third dim simultaenously processed) with bilinear interpolation
# define pi 3.141592654f
__global__ void Rotate3D_bilinear(float* Destination, float* Source, int sizeX, int sizeY, float deg)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.z * blockDim.z + threadIdx.z;
int z_offset = k*sizeX*sizeY;
int xc = sizeX - sizeX/2;
int yc = sizeY - sizeY/2;
float cos_rad = cosf(deg/180*pi);
float sin_rad = sinf(deg/180*pi);
float newx = +((float)i-xc)*cos_rad + ((float)j-yc)*sin_rad + xc ;
float newy = -((float)i-xc)*sin_rad + ((float)j-yc)*cos_rad + yc ;
int newx_0 = floorf(newx);
int newy_0 = floorf(newy);
int newx_1 = newx_0 + 1;
int newy_1 = newy_0 + 1;
// put the pixel coo. in unit square
float x = newx - float(newx_0);
float y = newy - float(newy_0);
float val_00 = 0.0, val_01 = 0.0, val_10 = 0.0, val_11 = 0.0, val_intp = 0.0;
if (newx_0 >= 0 && newx_1 < sizeX && newy_0 >= 0 && newy_1 < sizeY)
{
// perform bilinear interpolation
val_00 = Source[z_offset + newy_0*sizeX + newx_0];
val_01 = Source[z_offset + newy_1*sizeX + newx_0];
val_10 = Source[z_offset + newy_0*sizeX + newx_1];
val_11 = Source[z_offset + newy_1*sizeX + newx_1];
val_intp = val_00 + (val_01-val_00)*y + (val_10-val_00)*x + (val_11 + val_00 - val_10 - val_01)*x*y;
Destination[z_offset + j*sizeX+i] = val_intp;
}
} | #include <hip/hip_runtime.h>
/*__global__ void Rotate3D(float* Destination, float* Source, int sizeX, int sizeY, float deg)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.z * blockDim.z + threadIdx.z;
int xc = sizeX - sizeX/2;
int yc = sizeY - sizeY/2;
int newx = ((float)i-xc)*cos(deg) + ((float)j-yc)*sin(deg) + xc;
int newy = -((float)i-xc)*sin(deg) + ((float)j-yc)*cos(deg) + yc;
if (newx >= 0 && newx < sizeX && newy >= 0 && newy < sizeY)
{
// putPixVal(Destination, sizeX, i , j, readPixVal(Source, sizeX, newx, newy));
Destination[k* sizeX*sizeY + j*sizeX+i] = Source[k* sizeX*sizeY + newy*sizeX + newx];
}
} */
// rotate a 3D array (2D rotate, with the third dim simultaenously processed) with bilinear interpolation
# define pi 3.141592654f
__global__ void Rotate3D_bilinear(float* Destination, float* Source, int sizeX, int sizeY, float deg)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.z * blockDim.z + threadIdx.z;
int z_offset = k*sizeX*sizeY;
int xc = sizeX - sizeX/2;
int yc = sizeY - sizeY/2;
float cos_rad = cosf(deg/180*pi);
float sin_rad = sinf(deg/180*pi);
float newx = +((float)i-xc)*cos_rad + ((float)j-yc)*sin_rad + xc ;
float newy = -((float)i-xc)*sin_rad + ((float)j-yc)*cos_rad + yc ;
int newx_0 = floorf(newx);
int newy_0 = floorf(newy);
int newx_1 = newx_0 + 1;
int newy_1 = newy_0 + 1;
// put the pixel coo. in unit square
float x = newx - float(newx_0);
float y = newy - float(newy_0);
float val_00 = 0.0, val_01 = 0.0, val_10 = 0.0, val_11 = 0.0, val_intp = 0.0;
if (newx_0 >= 0 && newx_1 < sizeX && newy_0 >= 0 && newy_1 < sizeY)
{
// perform bilinear interpolation
val_00 = Source[z_offset + newy_0*sizeX + newx_0];
val_01 = Source[z_offset + newy_1*sizeX + newx_0];
val_10 = Source[z_offset + newy_0*sizeX + newx_1];
val_11 = Source[z_offset + newy_1*sizeX + newx_1];
val_intp = val_00 + (val_01-val_00)*y + (val_10-val_00)*x + (val_11 + val_00 - val_10 - val_01)*x*y;
Destination[z_offset + j*sizeX+i] = val_intp;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*__global__ void Rotate3D(float* Destination, float* Source, int sizeX, int sizeY, float deg)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.z * blockDim.z + threadIdx.z;
int xc = sizeX - sizeX/2;
int yc = sizeY - sizeY/2;
int newx = ((float)i-xc)*cos(deg) + ((float)j-yc)*sin(deg) + xc;
int newy = -((float)i-xc)*sin(deg) + ((float)j-yc)*cos(deg) + yc;
if (newx >= 0 && newx < sizeX && newy >= 0 && newy < sizeY)
{
// putPixVal(Destination, sizeX, i , j, readPixVal(Source, sizeX, newx, newy));
Destination[k* sizeX*sizeY + j*sizeX+i] = Source[k* sizeX*sizeY + newy*sizeX + newx];
}
} */
// rotate a 3D array (2D rotate, with the third dim simultaenously processed) with bilinear interpolation
# define pi 3.141592654f
__global__ void Rotate3D_bilinear(float* Destination, float* Source, int sizeX, int sizeY, float deg)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.z * blockDim.z + threadIdx.z;
int z_offset = k*sizeX*sizeY;
int xc = sizeX - sizeX/2;
int yc = sizeY - sizeY/2;
float cos_rad = cosf(deg/180*pi);
float sin_rad = sinf(deg/180*pi);
float newx = +((float)i-xc)*cos_rad + ((float)j-yc)*sin_rad + xc ;
float newy = -((float)i-xc)*sin_rad + ((float)j-yc)*cos_rad + yc ;
int newx_0 = floorf(newx);
int newy_0 = floorf(newy);
int newx_1 = newx_0 + 1;
int newy_1 = newy_0 + 1;
// put the pixel coo. in unit square
float x = newx - float(newx_0);
float y = newy - float(newy_0);
float val_00 = 0.0, val_01 = 0.0, val_10 = 0.0, val_11 = 0.0, val_intp = 0.0;
if (newx_0 >= 0 && newx_1 < sizeX && newy_0 >= 0 && newy_1 < sizeY)
{
// perform bilinear interpolation
val_00 = Source[z_offset + newy_0*sizeX + newx_0];
val_01 = Source[z_offset + newy_1*sizeX + newx_0];
val_10 = Source[z_offset + newy_0*sizeX + newx_1];
val_11 = Source[z_offset + newy_1*sizeX + newx_1];
val_intp = val_00 + (val_01-val_00)*y + (val_10-val_00)*x + (val_11 + val_00 - val_10 - val_01)*x*y;
Destination[z_offset + j*sizeX+i] = val_intp;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17Rotate3D_bilinearPfS_iif
.globl _Z17Rotate3D_bilinearPfS_iif
.p2align 8
.type _Z17Rotate3D_bilinearPfS_iif,@function
_Z17Rotate3D_bilinearPfS_iif:
s_load_b32 s2, s[0:1], 0x18
s_mov_b32 s3, 0x43340000
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v1, null, s3, s3, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v2, v1
s_waitcnt_depctr 0xfff
v_fma_f32 v3, -v1, v2, 1.0
v_fmac_f32_e32 v2, v3, v2
v_div_scale_f32 v3, vcc_lo, s2, 0x43340000, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v3, v2
v_fma_f32 v5, -v1, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v2
v_fma_f32 v1, -v1, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v1, v1, v2, v4
v_div_fixup_f32 v1, v1, 0x43340000, s2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, 0x40490fdb, v1
v_cmp_ngt_f32_e64 s4, 0x48000000, |v4|
v_readfirstlane_b32 s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s4
s_bitset0_b32 s2, 31
s_cbranch_vccz .LBB0_2
s_and_b32 s3, s2, 0x7fffff
s_lshr_b32 s5, s2, 23
s_bitset1_b32 s3, 23
s_addk_i32 s5, 0xff88
s_mul_hi_u32 s6, s3, 0xfe5163ab
s_mul_i32 s7, s3, 0x3c439041
s_mul_hi_u32 s8, s3, 0x3c439041
s_add_u32 s6, s6, s7
s_addc_u32 s7, 0, s8
s_mul_i32 s8, s3, 0xdb629599
s_mul_hi_u32 s9, s3, 0xdb629599
s_add_u32 s7, s7, s8
s_addc_u32 s8, 0, s9
s_mul_i32 s9, s3, 0xf534ddc0
s_mul_hi_u32 s10, s3, 0xf534ddc0
s_add_u32 s8, s8, s9
s_addc_u32 s9, 0, s10
s_mul_i32 s10, s3, 0xfc2757d1
s_mul_hi_u32 s11, s3, 0xfc2757d1
s_add_u32 s9, s9, s10
s_addc_u32 s10, 0, s11
s_mul_i32 s11, s3, 0x4e441529
s_mul_hi_u32 s12, s3, 0x4e441529
s_add_u32 s10, s10, s11
s_addc_u32 s11, 0, s12
s_cmp_gt_u32 s5, 63
s_mul_i32 s12, s3, 0xfe5163ab
s_mul_hi_u32 s16, s3, 0xa2f9836e
s_mul_i32 s3, s3, 0xa2f9836e
s_cselect_b32 s17, s7, s9
s_cselect_b32 s6, s6, s8
s_cselect_b32 s7, s12, s7
s_add_u32 s3, s11, s3
s_addc_u32 s11, 0, s16
s_cmp_gt_u32 s5, 63
s_cselect_b32 s12, 0xffffffc0, 0
s_cselect_b32 s8, s8, s10
s_cselect_b32 s3, s9, s3
s_cselect_b32 s9, s10, s11
s_add_i32 s12, s12, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s12, 31
s_cselect_b32 s5, 0xffffffe0, 0
s_cselect_b32 s10, s8, s3
s_cselect_b32 s3, s3, s9
s_cselect_b32 s8, s17, s8
s_cselect_b32 s9, s6, s17
s_cselect_b32 s6, s7, s6
s_add_i32 s5, s5, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s5, 31
s_cselect_b32 s7, 0xffffffe0, 0
s_cselect_b32 s3, s10, s3
s_cselect_b32 s10, s8, s10
s_cselect_b32 s8, s9, s8
s_cselect_b32 s6, s6, s9
s_add_i32 s7, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_i32 s5, 32, s7
s_cmp_eq_u32 s7, 0
v_mov_b32_e32 v1, s5
s_cselect_b32 s7, -1, 0
v_alignbit_b32 v2, s3, s10, v1
v_alignbit_b32 v3, s10, s8, v1
v_alignbit_b32 v1, s8, s6, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_readfirstlane_b32 s5, v2
v_cndmask_b32_e64 v2, v3, s10, s7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v1, v1, s8, s7
s_cselect_b32 s3, s3, s5
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v3, s3, v2, 30
s_bfe_u32 s5, s3, 0x1001d
s_delay_alu instid0(VALU_DEP_2)
v_alignbit_b32 v2, v2, v1, 30
s_sub_i32 s9, 0, s5
v_alignbit_b32 v1, v1, s6, 30
v_xor_b32_e32 v3, s9, v3
s_lshr_b32 s6, s3, 29
v_xor_b32_e32 v2, s9, v2
s_lshl_b32 s6, s6, 31
v_xor_b32_e32 v1, s9, v1
v_clz_i32_u32_e32 v5, v3
s_or_b32 s7, s6, 0.5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v5, 32, v5
v_sub_nc_u32_e32 v6, 31, v5
v_lshlrev_b32_e32 v7, 23, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v3, v3, v2, v6
v_alignbit_b32 v1, v2, v1, v6
v_sub_nc_u32_e32 v7, s7, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v2, v3, v1, 9
v_clz_i32_u32_e32 v6, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v6, 32, v6
v_sub_nc_u32_e32 v8, 31, v6
v_add_nc_u32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_alignbit_b32 v1, v2, v1, v8
v_lshrrev_b32_e32 v2, 9, v3
v_lshlrev_b32_e32 v3, 23, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_lshrrev_b32_e32 v1, 9, v1
v_or_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v1, v3
v_add_nc_u32_e32 v1, 0x33000000, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_or_b32_e32 v1, s6, v1
v_mul_f32_e32 v3, 0x3fc90fda, v2
s_lshr_b32 s6, s3, 30
s_mov_b32 s3, 0
s_add_i32 s5, s5, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v5, v2, 0x3fc90fda, -v3
v_fmamk_f32 v2, v2, 0x33a22168, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v2, 0x3fc90fda, v1
v_add_f32_e32 v3, v3, v2
s_branch .LBB0_3
.LBB0_2:
s_mov_b32 s3, -1
.LBB0_3:
v_mov_b32_e32 v1, s5
s_and_not1_b32 vcc_lo, exec_lo, s3
s_cbranch_vccnz .LBB0_5
v_mul_f32_e64 v1, 0x3f22f983, |v4|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v1, v1
v_fma_f32 v2, v1, 0xbfc90fda, |v4|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v2, v1, 0xb3a22168, v2
v_fmamk_f32 v3, v1, 0xa7c234c4, v2
v_cvt_i32_f32_e32 v1, v1
.LBB0_5:
s_load_b32 s3, s[0:1], 0x2c
s_and_b32 vcc_lo, exec_lo, s4
s_cbranch_vccz .LBB0_7
s_and_b32 s4, s2, 0x7fffff
s_lshr_b32 s5, s2, 23
s_bitset1_b32 s4, 23
s_addk_i32 s5, 0xff88
s_mul_hi_u32 s6, s4, 0xfe5163ab
s_mul_i32 s7, s4, 0x3c439041
s_mul_hi_u32 s8, s4, 0x3c439041
s_add_u32 s6, s6, s7
s_addc_u32 s7, 0, s8
s_mul_i32 s8, s4, 0xdb629599
s_mul_hi_u32 s9, s4, 0xdb629599
s_add_u32 s7, s7, s8
s_addc_u32 s8, 0, s9
s_mul_i32 s9, s4, 0xf534ddc0
s_mul_hi_u32 s10, s4, 0xf534ddc0
s_add_u32 s8, s8, s9
s_addc_u32 s9, 0, s10
s_mul_i32 s10, s4, 0xfc2757d1
s_mul_hi_u32 s11, s4, 0xfc2757d1
s_add_u32 s9, s9, s10
s_addc_u32 s10, 0, s11
s_mul_i32 s11, s4, 0x4e441529
s_mul_hi_u32 s12, s4, 0x4e441529
s_add_u32 s10, s10, s11
s_addc_u32 s11, 0, s12
s_cmp_gt_u32 s5, 63
s_mul_i32 s12, s4, 0xfe5163ab
s_mul_hi_u32 s16, s4, 0xa2f9836e
s_mul_i32 s4, s4, 0xa2f9836e
s_cselect_b32 s17, s7, s9
s_cselect_b32 s6, s6, s8
s_cselect_b32 s7, s12, s7
s_add_u32 s4, s11, s4
s_addc_u32 s11, 0, s16
s_cmp_gt_u32 s5, 63
s_cselect_b32 s12, 0xffffffc0, 0
s_cselect_b32 s8, s8, s10
s_cselect_b32 s4, s9, s4
s_cselect_b32 s9, s10, s11
s_add_i32 s12, s12, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s12, 31
s_cselect_b32 s5, 0xffffffe0, 0
s_cselect_b32 s10, s8, s4
s_cselect_b32 s4, s4, s9
s_cselect_b32 s8, s17, s8
s_cselect_b32 s9, s6, s17
s_cselect_b32 s6, s7, s6
s_add_i32 s5, s5, s12
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_gt_u32 s5, 31
s_cselect_b32 s7, 0xffffffe0, 0
s_cselect_b32 s4, s10, s4
s_cselect_b32 s10, s8, s10
s_cselect_b32 s8, s9, s8
s_cselect_b32 s6, s6, s9
s_add_i32 s7, s7, s5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
s_sub_i32 s5, 32, s7
s_cmp_eq_u32 s7, 0
v_mov_b32_e32 v2, s5
s_cselect_b32 s7, -1, 0
v_alignbit_b32 v5, s4, s10, v2
v_alignbit_b32 v6, s10, s8, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s5, v5
v_cndmask_b32_e64 v5, v6, s10, s7
s_delay_alu instid0(VALU_DEP_2)
s_cselect_b32 s4, s4, s5
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v6, s4, v5, 30
s_bfe_u32 s5, s4, 0x1001d
s_delay_alu instid0(SALU_CYCLE_1)
s_sub_i32 s9, 0, s5
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_xor_b32_e32 v6, s9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v7, v6
v_min_u32_e32 v7, 32, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b32_e32 v9, 23, v7
v_alignbit_b32 v2, s8, s6, v2
v_sub_nc_u32_e32 v8, 31, v7
v_cndmask_b32_e64 v2, v2, s8, s7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_alignbit_b32 v5, v5, v2, 30
v_alignbit_b32 v2, v2, s6, 30
s_lshr_b32 s6, s4, 29
s_lshl_b32 s6, s6, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v5, s9, v5
v_xor_b32_e32 v2, s9, v2
s_or_b32 s7, s6, 0.5
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_nc_u32_e32 v9, s7, v9
v_alignbit_b32 v6, v6, v5, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_alignbit_b32 v2, v5, v2, v8
v_alignbit_b32 v5, v6, v2, 9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_clz_i32_u32_e32 v8, v5
v_min_u32_e32 v8, 32, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v10, 31, v8
v_alignbit_b32 v2, v5, v2, v10
v_lshrrev_b32_e32 v5, 9, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshrrev_b32_e32 v2, 9, v2
v_or_b32_e32 v5, v5, v9
v_add_nc_u32_e32 v7, v8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b32_e32 v6, 23, v7
v_sub_nc_u32_e32 v2, v2, v6
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v6, 0x3fc90fda, v5
v_add_nc_u32_e32 v2, 0x33000000, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v7, v5, 0x3fc90fda, -v6
v_or_b32_e32 v2, s6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_fmamk_f32 v5, v5, 0x33a22168, v7
s_lshr_b32 s6, s4, 30
s_mov_b32 s4, 0
s_add_i32 s5, s5, s6
v_fmac_f32_e32 v5, 0x3fc90fda, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v5, v6, v5
s_branch .LBB0_8
.LBB0_7:
s_mov_b32 s4, -1
.LBB0_8:
v_mov_b32_e32 v6, s5
s_and_not1_b32 vcc_lo, exec_lo, s4
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_cbranch_vccnz .LBB0_10
v_mul_f32_e64 v2, 0x3f22f983, |v4|
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rndne_f32_e32 v2, v2
v_fma_f32 v5, v2, 0xbfc90fda, |v4|
v_cvt_i32_f32_e32 v6, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmamk_f32 v5, v2, 0xb3a22168, v5
v_fmamk_f32 v5, v2, 0xa7c234c4, v5
.LBB0_10:
v_dual_mul_f32 v2, v3, v3 :: v_dual_and_b32 v9, 1, v1
s_mov_b32 s8, 0x37d75334
s_mov_b32 s5, 0xb94c1982
s_and_b32 s3, 0xffff, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_dual_fmaak_f32 v8, s8, v2, 0xbab64f3b :: v_dual_lshlrev_b32 v1, 30, v1
v_cmp_eq_u32_e32 vcc_lo, 0, v9
s_and_b32 s4, 0xffff, s4
s_load_b64 s[6:7], s[0:1], 0x10
v_dual_fmaak_f32 v8, v2, v8, 0x3d2aabf7 :: v_dual_mul_f32 v11, v5, v5
v_fmaak_f32 v7, s5, v2, 0x3c0881c4
v_and_b32_e32 v13, 0x80000000, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmaak_f32 v14, s5, v11, 0x3c0881c4
v_dual_fmaak_f32 v10, v2, v7, 0xbe2aaa9d :: v_dual_fmaak_f32 v9, v11, v14, 0xbe2aaa9d
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v10, v2, v10 :: v_dual_and_b32 v7, 0x3ff, v0
v_fmaak_f32 v12, v2, v8, 0xbf000004
v_bfe_u32 v8, v0, 10, 10
v_fmac_f32_e32 v3, v3, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fma_f32 v10, v2, v12, 1.0
v_fmaak_f32 v12, s8, v11, 0xbab64f3b
v_mad_u64_u32 v[1:2], null, s13, s3, v[7:8]
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s6, 31
v_cndmask_b32_e64 v7, -v3, v10, vcc_lo
v_mad_u64_u32 v[2:3], null, s14, s4, v[8:9]
s_lshr_b32 s4, s7, 31
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_xor_b32_e32 v3, v13, v7
v_mul_f32_e32 v7, v11, v9
v_dual_fmaak_f32 v10, v11, v12, 0x3d2aabf7 :: v_dual_lshlrev_b32 v9, 30, v6
v_dual_fmac_f32 v5, v5, v7 :: v_dual_fmaak_f32 v8, v11, v10, 0xbf000004
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v7, v11, v8, 1.0
v_and_b32_e32 v6, 1, v6
v_cmp_eq_u32_e32 vcc_lo, 0, v6
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e32 v5, v7, v5, vcc_lo
v_cvt_f32_i32_e32 v7, v2
v_and_b32_e32 v8, 0x80000000, v9
v_xor_b32_e32 v9, s2, v4
s_add_i32 s2, s6, s3
s_add_i32 s3, s7, s4
v_cmp_class_f32_e64 vcc_lo, v4, 0x1f8
s_ashr_i32 s3, s3, 1
s_ashr_i32 s2, s2, 1
s_sub_i32 s3, s7, s3
s_sub_i32 s2, s6, s2
v_cvt_f32_i32_e32 v4, s3
v_cndmask_b32_e32 v3, 0x7fc00000, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v7, v4
v_xor_b32_e32 v6, v9, v8
v_cvt_f32_i32_e32 v8, s2
v_xor_b32_e32 v5, v6, v5
v_cvt_f32_i32_e32 v6, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_cndmask_b32 v5, 0x7fc00000, v5 :: v_dual_sub_f32 v6, v6, v8
v_mul_f32_e32 v9, v7, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v5
v_fma_f32 v5, v7, v3, -v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v4, v5, v4 :: v_dual_fmac_f32 v9, v6, v3
v_floor_f32_e32 v6, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v3, v9, v8
v_cvt_i32_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v5, v3
v_add_nc_u32_e32 v8, 1, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cvt_i32_f32_e32 v5, v5
v_cmp_lt_i32_e64 s3, -1, v6
v_cmp_gt_i32_e64 s2, s7, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v7, 1, v5
v_cmp_lt_i32_e64 s4, -1, v5
v_cmp_gt_i32_e32 vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_b32 s2, s2, s3
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s4, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_12
s_load_b32 s4, s[0:1], 0x30
v_bfe_u32 v0, v0, 20, 10
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v2, v2, s6
s_waitcnt lgkmcnt(0)
s_and_b32 s4, 0xffff, s4
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[9:10], null, s15, s4, v[0:1]
s_mul_i32 s4, s7, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v0, s4, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
v_mad_u64_u32 v[9:10], null, v6, s6, v[0:1]
v_mad_u64_u32 v[10:11], null, v8, s6, v[0:1]
v_cvt_f32_i32_e32 v6, v6
v_add3_u32 v0, v2, v1, v0
v_add_nc_u32_e32 v8, v9, v5
v_add_nc_u32_e32 v13, v9, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_dual_sub_f32 v4, v4, v6 :: v_dual_add_nc_u32 v11, v10, v5
v_add_nc_u32_e32 v15, v10, v7
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v14, 31, v13
v_ashrrev_i32_e32 v12, 31, v11
v_cvt_f32_i32_e32 v5, v5
v_ashrrev_i32_e32 v16, 31, v15
v_lshlrev_b64 v[7:8], 2, v[8:9]
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[9:10], 2, v[11:12]
v_lshlrev_b64 v[11:12], 2, v[13:14]
v_lshlrev_b64 v[13:14], 2, v[15:16]
s_delay_alu instid0(VALU_DEP_4)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
v_add_co_u32 v9, vcc_lo, s2, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
v_add_co_u32 v13, vcc_lo, s2, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
v_add_co_u32 v11, vcc_lo, s2, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s3, v12, vcc_lo
s_clause 0x3
global_load_b32 v13, v[13:14], off
global_load_b32 v7, v[7:8], off
global_load_b32 v8, v[9:10], off
global_load_b32 v9, v[11:12], off
v_sub_f32_e32 v2, v3, v5
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(2)
v_add_f32_e32 v10, v7, v13
s_waitcnt vmcnt(1)
v_sub_f32_e32 v6, v8, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_sub_f32 v3, v9, v7 :: v_dual_sub_f32 v10, v10, v9
v_fma_f32 v5, v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v5, v2, v3
v_sub_f32_e32 v6, v10, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v2, v6
v_fmac_f32_e32 v5, v4, v2
global_store_b32 v[0:1], v5, off
.LBB0_12:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17Rotate3D_bilinearPfS_iif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17Rotate3D_bilinearPfS_iif, .Lfunc_end0-_Z17Rotate3D_bilinearPfS_iif
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17Rotate3D_bilinearPfS_iif
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z17Rotate3D_bilinearPfS_iif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*__global__ void Rotate3D(float* Destination, float* Source, int sizeX, int sizeY, float deg)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.z * blockDim.z + threadIdx.z;
int xc = sizeX - sizeX/2;
int yc = sizeY - sizeY/2;
int newx = ((float)i-xc)*cos(deg) + ((float)j-yc)*sin(deg) + xc;
int newy = -((float)i-xc)*sin(deg) + ((float)j-yc)*cos(deg) + yc;
if (newx >= 0 && newx < sizeX && newy >= 0 && newy < sizeY)
{
// putPixVal(Destination, sizeX, i , j, readPixVal(Source, sizeX, newx, newy));
Destination[k* sizeX*sizeY + j*sizeX+i] = Source[k* sizeX*sizeY + newy*sizeX + newx];
}
} */
// rotate a 3D array (2D rotate, with the third dim simultaenously processed) with bilinear interpolation
# define pi 3.141592654f
__global__ void Rotate3D_bilinear(float* Destination, float* Source, int sizeX, int sizeY, float deg)
{
int i = blockIdx.x * blockDim.x + threadIdx.x;// Kernel definition
int j = blockIdx.y * blockDim.y + threadIdx.y;
int k = blockIdx.z * blockDim.z + threadIdx.z;
int z_offset = k*sizeX*sizeY;
int xc = sizeX - sizeX/2;
int yc = sizeY - sizeY/2;
float cos_rad = cosf(deg/180*pi);
float sin_rad = sinf(deg/180*pi);
float newx = +((float)i-xc)*cos_rad + ((float)j-yc)*sin_rad + xc ;
float newy = -((float)i-xc)*sin_rad + ((float)j-yc)*cos_rad + yc ;
int newx_0 = floorf(newx);
int newy_0 = floorf(newy);
int newx_1 = newx_0 + 1;
int newy_1 = newy_0 + 1;
// put the pixel coo. in unit square
float x = newx - float(newx_0);
float y = newy - float(newy_0);
float val_00 = 0.0, val_01 = 0.0, val_10 = 0.0, val_11 = 0.0, val_intp = 0.0;
if (newx_0 >= 0 && newx_1 < sizeX && newy_0 >= 0 && newy_1 < sizeY)
{
// perform bilinear interpolation
val_00 = Source[z_offset + newy_0*sizeX + newx_0];
val_01 = Source[z_offset + newy_1*sizeX + newx_0];
val_10 = Source[z_offset + newy_0*sizeX + newx_1];
val_11 = Source[z_offset + newy_1*sizeX + newx_1];
val_intp = val_00 + (val_01-val_00)*y + (val_10-val_00)*x + (val_11 + val_00 - val_10 - val_01)*x*y;
Destination[z_offset + j*sizeX+i] = val_intp;
}
} | .text
.file "imrotate.hip"
.globl _Z32__device_stub__Rotate3D_bilinearPfS_iif # -- Begin function _Z32__device_stub__Rotate3D_bilinearPfS_iif
.p2align 4, 0x90
.type _Z32__device_stub__Rotate3D_bilinearPfS_iif,@function
_Z32__device_stub__Rotate3D_bilinearPfS_iif: # @_Z32__device_stub__Rotate3D_bilinearPfS_iif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17Rotate3D_bilinearPfS_iif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__Rotate3D_bilinearPfS_iif, .Lfunc_end0-_Z32__device_stub__Rotate3D_bilinearPfS_iif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17Rotate3D_bilinearPfS_iif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17Rotate3D_bilinearPfS_iif,@object # @_Z17Rotate3D_bilinearPfS_iif
.section .rodata,"a",@progbits
.globl _Z17Rotate3D_bilinearPfS_iif
.p2align 3, 0x0
_Z17Rotate3D_bilinearPfS_iif:
.quad _Z32__device_stub__Rotate3D_bilinearPfS_iif
.size _Z17Rotate3D_bilinearPfS_iif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17Rotate3D_bilinearPfS_iif"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__Rotate3D_bilinearPfS_iif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17Rotate3D_bilinearPfS_iif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f5613_00000000-6_imrotate.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif
.type _Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif, @function
_Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17Rotate3D_bilinearPfS_iif(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif, .-_Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif
.globl _Z17Rotate3D_bilinearPfS_iif
.type _Z17Rotate3D_bilinearPfS_iif, @function
_Z17Rotate3D_bilinearPfS_iif:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z42__device_stub__Z17Rotate3D_bilinearPfS_iifPfS_iif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17Rotate3D_bilinearPfS_iif, .-_Z17Rotate3D_bilinearPfS_iif
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z17Rotate3D_bilinearPfS_iif"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17Rotate3D_bilinearPfS_iif(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "imrotate.hip"
.globl _Z32__device_stub__Rotate3D_bilinearPfS_iif # -- Begin function _Z32__device_stub__Rotate3D_bilinearPfS_iif
.p2align 4, 0x90
.type _Z32__device_stub__Rotate3D_bilinearPfS_iif,@function
_Z32__device_stub__Rotate3D_bilinearPfS_iif: # @_Z32__device_stub__Rotate3D_bilinearPfS_iif
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17Rotate3D_bilinearPfS_iif, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z32__device_stub__Rotate3D_bilinearPfS_iif, .Lfunc_end0-_Z32__device_stub__Rotate3D_bilinearPfS_iif
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17Rotate3D_bilinearPfS_iif, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17Rotate3D_bilinearPfS_iif,@object # @_Z17Rotate3D_bilinearPfS_iif
.section .rodata,"a",@progbits
.globl _Z17Rotate3D_bilinearPfS_iif
.p2align 3, 0x0
_Z17Rotate3D_bilinearPfS_iif:
.quad _Z32__device_stub__Rotate3D_bilinearPfS_iif
.size _Z17Rotate3D_bilinearPfS_iif, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17Rotate3D_bilinearPfS_iif"
.size .L__unnamed_1, 29
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__Rotate3D_bilinearPfS_iif
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17Rotate3D_bilinearPfS_iif
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <assert.h>
#include <iostream>
#include <cstdlib>
#include<sys/time.h>
#include <cmath>
#include "cuda_runtime.h"
const int LANGE = 16;
__global__ void vecAdd(double *d_a, double *d_b, double *d_c, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < (N / LANGE)) {
int large = N / LANGE;
for (int i = 0; i < LANGE; i++)
if (idx % 2 == 0){
d_c[idx + i * large] = d_a[idx + i * large] + d_b[idx + i *large];
}else{
d_c[idx + i * large] = d_a[idx + i * large] - d_b[idx + i * large];
}
}
}
int main (void) {
int n;
std::cin>>n;
assert(n % LANGE == 0);
double *H_a, *H_b, *H_c;
size_t bytes = n * sizeof(double);
H_a = (double*)malloc(bytes);
H_b = (double*)malloc(bytes);
H_c = (double*)malloc(bytes);
for (int i = 0; i < n; i++) {
H_a[i] = sin(i) * sin(i);
H_b[i] = cos(i) * cos(i);
}
//GPU parper
double *d_a, *d_b, *d_c;
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
cudaMemcpy(d_a, H_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, H_b, bytes, cudaMemcpyHostToDevice);
int blockSize = 1024;
int gridSize = ((n-1)/LANGE)/blockSize + 1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//gpu running
cudaEventRecord(start);
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
cudaEventRecord(stop);
cudaDeviceSynchronize();
cudaMemcpy(H_c, d_c, bytes, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float timeGPU = 0;
cudaEventElapsedTime(&timeGPU, start, stop);
std::cout << "Runtime for GPU is: " << timeGPU<<" ms "<< std::endl;
//CPU running.....
struct timeval startCPU,endCPU;
gettimeofday(&startCPU,NULL);
for (int i = 0; i < n; i++) {
H_c[i] = H_a[i] + H_b[i];
}
gettimeofday(&endCPU,NULL);
double timeCPU = endCPU.tv_sec - startCPU.tv_sec + (double)(endCPU.tv_usec - startCPU.tv_usec)/1000000;
std::cout << "Runtime for CPU is: " << timeCPU <<" ms "<< std::endl;
//summary
if(timeGPU<timeCPU){
std::cout<<"GPU is faster than CPU for "<<timeCPU-timeGPU<<" ms "<<std::endl;
}else if(timeGPU>timeCPU){
std::cout<<"CPU is faster than GPU for "<<timeGPU-timeCPU<<" ms "<<std::endl;
}else{
std::cout<<"same time for GPU and CPU"<<std::endl;
}
free(H_a);
free(H_b);
free(H_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | code for sm_80
Function : _Z6vecAddPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0040*/ SHF.R.S32.HI R0, RZ, 0x1f, R0 ; /* 0x0000001fff007819 */
/* 0x000fc80000011400 */
/*0050*/ LEA.HI R0, R0, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0000007a11 */
/* 0x000fc800078f20ff */
/*0060*/ SHF.R.S32.HI R0, RZ, 0x4, R0 ; /* 0x00000004ff007819 */
/* 0x000fe20000011400 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0080*/ ISETP.GE.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R8, R3, R2, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fca00078e0202 */
/*00d0*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ IMAD.WIDE R6, R3, R2, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0202 */
/*00f0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000e2000c1e1b00 */
/*0100*/ LOP3.LUT R14, R3, 0x1, RZ, 0xc0, !PT ; /* 0x00000001030e7812 */
/* 0x000fc800078ec0ff */
/*0110*/ ISETP.NE.U32.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f05070 */
/*0120*/ IMAD.WIDE R6, R0, 0x8, R6 ; /* 0x0000000800067825 */
/* 0x001fe200078e0206 */
/*0130*/ DADD R12, -RZ, -R4 ; /* 0x00000000ff0c7229 */
/* 0x004e140000000904 */
/*0140*/ FSEL R4, R12, R4, !P0 ; /* 0x000000040c047208 */
/* 0x001fe40004000000 */
/*0150*/ FSEL R5, R13, R5, !P0 ; /* 0x000000050d057208 */
/* 0x000fe20004000000 */
/*0160*/ IMAD.WIDE R12, R0, 0x8, R8 ; /* 0x00000008000c7825 */
/* 0x000fca00078e0208 */
/*0170*/ DADD R10, R10, R4 ; /* 0x000000000a0a7229 */
/* 0x0080640000000004 */
/*0180*/ IMAD.WIDE R4, R3, R2, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x001fca00078e0202 */
/*0190*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0021e8000c101b04 */
/*01a0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1b00 */
/*01b0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*01c0*/ IADD3 R3, R0.reuse, R0, R3 ; /* 0x0000000000037210 */
/* 0x040fe20007ffe003 */
/*01d0*/ IMAD.WIDE R14, R0, 0x8, R4 ; /* 0x00000008000e7825 */
/* 0x000fc800078e0204 */
/*01e0*/ IMAD.WIDE R16, R3, R2, c[0x0][0x168] ; /* 0x00005a0003107625 */
/* 0x000fc800078e0202 */
/*01f0*/ IMAD.WIDE R4, R3, R2, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x001fe200078e0202 */
/*0200*/ DADD R8, -RZ, -R12 ; /* 0x00000000ff087229 */
/* 0x004e14000000090c */
/*0210*/ FSEL R8, R8, R12, !P0 ; /* 0x0000000c08087208 */
/* 0x001fe40004000000 */
/*0220*/ FSEL R9, R9, R13, !P0 ; /* 0x0000000d09097208 */
/* 0x000fcc0004000000 */
/*0230*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x008e0e0000000008 */
/*0240*/ STG.E.64 [R14.64], R8 ; /* 0x000000080e007986 */
/* 0x0011e8000c101b04 */
/*0250*/ LDG.E.64 R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee2000c1e1b00 */
/*0270*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fc800078e0202 */
/*0280*/ IMAD.WIDE R8, R0, 0x8, R4 ; /* 0x0000000800087825 */
/* 0x001fe200078e0204 */
/*0290*/ DADD R12, -RZ, -R10 ; /* 0x00000000ff0c7229 */
/* 0x004e14000000090a */
/*02a0*/ FSEL R10, R12, R10, !P0 ; /* 0x0000000a0c0a7208 */
/* 0x001fe40004000000 */
/*02b0*/ FSEL R11, R13, R11, !P0 ; /* 0x0000000b0d0b7208 */
/* 0x000fcc0004000000 */
/*02c0*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x008064000000000a */
/*02d0*/ IMAD.WIDE R10, R0, 0x8, R16 ; /* 0x00000008000a7825 */
/* 0x001fca00078e0210 */
/*02e0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0021e8000c101b04 */
/*02f0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1b00 */
/*0300*/ LDG.E.64 R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x000ee2000c1e1b00 */
/*0310*/ DADD R4, -RZ, -R12 ; /* 0x00000000ff047229 */
/* 0x004e54000000090c */
/*0320*/ FSEL R4, R4, R12, !P0 ; /* 0x0000000c04047208 */
/* 0x002fe40004000000 */
/*0330*/ FSEL R5, R5, R13, !P0 ; /* 0x0000000d05057208 */
/* 0x000fe20004000000 */
/*0340*/ IMAD.WIDE R12, R0, 0x8, R10 ; /* 0x00000008000c7825 */
/* 0x000fca00078e020a */
/*0350*/ DADD R14, R14, R4 ; /* 0x000000000e0e7229 */
/* 0x0082a40000000004 */
/*0360*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x002fca00078e0202 */
/*0370*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0043e8000c101b04 */
/*0380*/ LDG.E.64 R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x001ea2000c1e1b00 */
/*0390*/ IMAD.WIDE R2, R0, 0x8, R8 ; /* 0x0000000800027825 */
/* 0x000fca00078e0208 */
/*03a0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ee2000c1e1b00 */
/*03b0*/ DADD R8, -RZ, -R6 ; /* 0x00000000ff087229 */
/* 0x004e140000000906 */
/*03c0*/ FSEL R6, R8, R6, !P0 ; /* 0x0000000608067208 */
/* 0x001fe40004000000 */
/*03d0*/ FSEL R7, R9, R7, !P0 ; /* 0x0000000709077208 */
/* 0x000fe20004000000 */
/*03e0*/ IMAD.WIDE R8, R0, 0x8, R12 ; /* 0x0000000800087825 */
/* 0x000fca00078e020c */
/*03f0*/ DADD R10, R10, R6 ; /* 0x000000000a0a7229 */
/* 0x0080a40000000006 */
/*0400*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x001fca00078e0204 */
/*0410*/ STG.E.64 [R6.64], R10 ; /* 0x0000000a06007986 */
/* 0x0041e8000c101b04 */
/*0420*/ LDG.E.64 R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x002ea2000c1e1b00 */
/*0430*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x000fca00078e0202 */
/*0440*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ee2000c1e1b00 */
/*0450*/ DADD R2, -RZ, -R14 ; /* 0x00000000ff027229 */
/* 0x004e54000000090e */
/*0460*/ FSEL R2, R2, R14, !P0 ; /* 0x0000000e02027208 */
/* 0x002fe40004000000 */
/*0470*/ FSEL R3, R3, R15, !P0 ; /* 0x0000000f03037208 */
/* 0x000fe20004000000 */
/*0480*/ IMAD.WIDE R14, R0, 0x8, R8 ; /* 0x00000008000e7825 */
/* 0x000fca00078e0208 */
/*0490*/ DADD R12, R12, R2 ; /* 0x000000000c0c7229 */
/* 0x0082a40000000002 */
/*04a0*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x002fca00078e0206 */
/*04b0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0043e8000c101b04 */
/*04c0*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x001ea2000c1e1b00 */
/*04d0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x000fca00078e0204 */
/*04e0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ee2000c1e1b00 */
/*04f0*/ DADD R4, -RZ, -R10 ; /* 0x00000000ff047229 */
/* 0x004e14000000090a */
/*0500*/ FSEL R4, R4, R10, !P0 ; /* 0x0000000a04047208 */
/* 0x001fe40004000000 */
/*0510*/ FSEL R5, R5, R11, !P0 ; /* 0x0000000b05057208 */
/* 0x000fe20004000000 */
/*0520*/ IMAD.WIDE R10, R0, 0x8, R14 ; /* 0x00000008000a7825 */
/* 0x000fca00078e020e */
/*0530*/ DADD R8, R8, R4 ; /* 0x0000000008087229 */
/* 0x0080a40000000004 */
/*0540*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x001fca00078e0202 */
/*0550*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0041e8000c101b04 */
/*0560*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x002ea2000c1e1b00 */
/*0570*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x000fca00078e0206 */
/*0580*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ee2000c1e1b00 */
/*0590*/ DADD R6, -RZ, -R12 ; /* 0x00000000ff067229 */
/* 0x004e54000000090c */
/*05a0*/ FSEL R6, R6, R12, !P0 ; /* 0x0000000c06067208 */
/* 0x002fe40004000000 */
/*05b0*/ FSEL R7, R7, R13, !P0 ; /* 0x0000000d07077208 */
/* 0x000fe20004000000 */
/*05c0*/ IMAD.WIDE R12, R0, 0x8, R10 ; /* 0x00000008000c7825 */
/* 0x000fca00078e020a */
/*05d0*/ DADD R14, R14, R6 ; /* 0x000000000e0e7229 */
/* 0x0082a40000000006 */
/*05e0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x002fca00078e0204 */
/*05f0*/ STG.E.64 [R6.64], R14 ; /* 0x0000000e06007986 */
/* 0x0043e8000c101b04 */
/*0600*/ LDG.E.64 R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x001ea2000c1e1b00 */
/*0610*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x000fca00078e0202 */
/*0620*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ee2000c1e1b00 */
/*0630*/ DADD R2, -RZ, -R8 ; /* 0x00000000ff027229 */
/* 0x004e140000000908 */
/*0640*/ FSEL R2, R2, R8, !P0 ; /* 0x0000000802027208 */
/* 0x001fe40004000000 */
/*0650*/ FSEL R3, R3, R9, !P0 ; /* 0x0000000903037208 */
/* 0x000fe20004000000 */
/*0660*/ IMAD.WIDE R8, R0, 0x8, R12 ; /* 0x0000000800087825 */
/* 0x000fca00078e020c */
/*0670*/ DADD R10, R10, R2 ; /* 0x000000000a0a7229 */
/* 0x0080a40000000002 */
/*0680*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x001fca00078e0206 */
/*0690*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0041e8000c101b04 */
/*06a0*/ LDG.E.64 R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x002ea2000c1e1b00 */
/*06b0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x000fca00078e0204 */
/*06c0*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ee2000c1e1b00 */
/*06d0*/ DADD R4, -RZ, -R14 ; /* 0x00000000ff047229 */
/* 0x004e54000000090e */
/*06e0*/ FSEL R4, R4, R14, !P0 ; /* 0x0000000e04047208 */
/* 0x002fe40004000000 */
/*06f0*/ FSEL R5, R5, R15, !P0 ; /* 0x0000000f05057208 */
/* 0x000fe20004000000 */
/*0700*/ IMAD.WIDE R14, R0, 0x8, R8 ; /* 0x00000008000e7825 */
/* 0x000fca00078e0208 */
/*0710*/ DADD R12, R12, R4 ; /* 0x000000000c0c7229 */
/* 0x0082a40000000004 */
/*0720*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x002fca00078e0202 */
/*0730*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0043e8000c101b04 */
/*0740*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x001ea2000c1e1b00 */
/*0750*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x000fca00078e0206 */
/*0760*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ee2000c1e1b00 */
/*0770*/ DADD R6, -RZ, -R10 ; /* 0x00000000ff067229 */
/* 0x004e14000000090a */
/*0780*/ FSEL R6, R6, R10, !P0 ; /* 0x0000000a06067208 */
/* 0x001fe40004000000 */
/*0790*/ FSEL R7, R7, R11, !P0 ; /* 0x0000000b07077208 */
/* 0x000fe20004000000 */
/*07a0*/ IMAD.WIDE R10, R0, 0x8, R14 ; /* 0x00000008000a7825 */
/* 0x000fca00078e020e */
/*07b0*/ DADD R8, R8, R6 ; /* 0x0000000008087229 */
/* 0x0080a40000000006 */
/*07c0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x001fca00078e0204 */
/*07d0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0041e8000c101b04 */
/*07e0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x002ea2000c1e1b00 */
/*07f0*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x000fca00078e0202 */
/*0800*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1b00 */
/*0810*/ DADD R2, -RZ, -R12 ; /* 0x00000000ff027229 */
/* 0x004e54000000090c */
/*0820*/ FSEL R2, R2, R12, !P0 ; /* 0x0000000c02027208 */
/* 0x002fe40004000000 */
/*0830*/ FSEL R3, R3, R13, !P0 ; /* 0x0000000d03037208 */
/* 0x000fe20004000000 */
/*0840*/ IMAD.WIDE R12, R0, 0x8, R10 ; /* 0x00000008000c7825 */
/* 0x000fca00078e020a */
/*0850*/ DADD R14, R14, R2 ; /* 0x000000000e0e7229 */
/* 0x0082a40000000002 */
/*0860*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x002fca00078e0206 */
/*0870*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0043e8000c101b04 */
/*0880*/ LDG.E.64 R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x001ea2000c1e1b00 */
/*0890*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x000fca00078e0204 */
/*08a0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ee2000c1e1b00 */
/*08b0*/ DADD R4, -RZ, -R8 ; /* 0x00000000ff047229 */
/* 0x004e140000000908 */
/*08c0*/ FSEL R4, R4, R8, !P0 ; /* 0x0000000804047208 */
/* 0x001fe40004000000 */
/*08d0*/ FSEL R5, R5, R9, !P0 ; /* 0x0000000905057208 */
/* 0x000fe20004000000 */
/*08e0*/ IMAD.WIDE R8, R0, 0x8, R12 ; /* 0x0000000800087825 */
/* 0x000fca00078e020c */
/*08f0*/ DADD R10, R10, R4 ; /* 0x000000000a0a7229 */
/* 0x0080a40000000004 */
/*0900*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x001fca00078e0202 */
/*0910*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0041e8000c101b04 */
/*0920*/ LDG.E.64 R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x002ea2000c1e1b00 */
/*0930*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x000fca00078e0206 */
/*0940*/ LDG.E.64 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ee2000c1e1b00 */
/*0950*/ DADD R6, -RZ, -R14 ; /* 0x00000000ff067229 */
/* 0x004e54000000090e */
/*0960*/ FSEL R6, R6, R14, !P0 ; /* 0x0000000e06067208 */
/* 0x002fe40004000000 */
/*0970*/ FSEL R7, R7, R15, !P0 ; /* 0x0000000f07077208 */
/* 0x000fe20004000000 */
/*0980*/ IMAD.WIDE R14, R0, 0x8, R8 ; /* 0x00000008000e7825 */
/* 0x000fca00078e0208 */
/*0990*/ DADD R12, R12, R6 ; /* 0x000000000c0c7229 */
/* 0x0082a40000000006 */
/*09a0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x002fca00078e0204 */
/*09b0*/ STG.E.64 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0043e8000c101b04 */
/*09c0*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x001ea2000c1e1b00 */
/*09d0*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x000fca00078e0202 */
/*09e0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1b00 */
/*09f0*/ DADD R2, -RZ, -R10 ; /* 0x00000000ff027229 */
/* 0x004e14000000090a */
/*0a00*/ FSEL R2, R2, R10, !P0 ; /* 0x0000000a02027208 */
/* 0x001fe40004000000 */
/*0a10*/ FSEL R3, R3, R11, !P0 ; /* 0x0000000b03037208 */
/* 0x000fe20004000000 */
/*0a20*/ IMAD.WIDE R10, R0, 0x8, R14 ; /* 0x00000008000a7825 */
/* 0x000fca00078e020e */
/*0a30*/ DADD R8, R8, R2 ; /* 0x0000000008087229 */
/* 0x0080a40000000002 */
/*0a40*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x001fca00078e0206 */
/*0a50*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x004fe8000c101b04 */
/*0a60*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*0a70*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x002fcc00078e0204 */
/*0a80*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0a90*/ IMAD.WIDE R12, R0, 0x8, R2 ; /* 0x00000008000c7825 */
/* 0x000fe200078e0202 */
/*0aa0*/ DADD R4, -RZ, -R10 ; /* 0x00000000ff047229 */
/* 0x004e14000000090a */
/*0ab0*/ FSEL R4, R4, R10, !P0 ; /* 0x0000000a04047208 */
/* 0x001fe40004000000 */
/*0ac0*/ FSEL R5, R5, R11, !P0 ; /* 0x0000000b05057208 */
/* 0x000fcc0004000000 */
/*0ad0*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x008e0e0000000004 */
/*0ae0*/ STG.E.64 [R12.64], R4 ; /* 0x000000040c007986 */
/* 0x001fe2000c101b04 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <assert.h>
#include <iostream>
#include <cstdlib>
#include<sys/time.h>
#include <cmath>
#include "cuda_runtime.h"
const int LANGE = 16;
__global__ void vecAdd(double *d_a, double *d_b, double *d_c, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < (N / LANGE)) {
int large = N / LANGE;
for (int i = 0; i < LANGE; i++)
if (idx % 2 == 0){
d_c[idx + i * large] = d_a[idx + i * large] + d_b[idx + i *large];
}else{
d_c[idx + i * large] = d_a[idx + i * large] - d_b[idx + i * large];
}
}
}
int main (void) {
int n;
std::cin>>n;
assert(n % LANGE == 0);
double *H_a, *H_b, *H_c;
size_t bytes = n * sizeof(double);
H_a = (double*)malloc(bytes);
H_b = (double*)malloc(bytes);
H_c = (double*)malloc(bytes);
for (int i = 0; i < n; i++) {
H_a[i] = sin(i) * sin(i);
H_b[i] = cos(i) * cos(i);
}
//GPU parper
double *d_a, *d_b, *d_c;
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
cudaMemcpy(d_a, H_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, H_b, bytes, cudaMemcpyHostToDevice);
int blockSize = 1024;
int gridSize = ((n-1)/LANGE)/blockSize + 1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//gpu running
cudaEventRecord(start);
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
cudaEventRecord(stop);
cudaDeviceSynchronize();
cudaMemcpy(H_c, d_c, bytes, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float timeGPU = 0;
cudaEventElapsedTime(&timeGPU, start, stop);
std::cout << "Runtime for GPU is: " << timeGPU<<" ms "<< std::endl;
//CPU running.....
struct timeval startCPU,endCPU;
gettimeofday(&startCPU,NULL);
for (int i = 0; i < n; i++) {
H_c[i] = H_a[i] + H_b[i];
}
gettimeofday(&endCPU,NULL);
double timeCPU = endCPU.tv_sec - startCPU.tv_sec + (double)(endCPU.tv_usec - startCPU.tv_usec)/1000000;
std::cout << "Runtime for CPU is: " << timeCPU <<" ms "<< std::endl;
//summary
if(timeGPU<timeCPU){
std::cout<<"GPU is faster than CPU for "<<timeCPU-timeGPU<<" ms "<<std::endl;
}else if(timeGPU>timeCPU){
std::cout<<"CPU is faster than GPU for "<<timeGPU-timeCPU<<" ms "<<std::endl;
}else{
std::cout<<"same time for GPU and CPU"<<std::endl;
}
free(H_a);
free(H_b);
free(H_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | .file "tmpxft_000fdae9_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
.globl _Z6vecAddPdS_S_i
.type _Z6vecAddPdS_S_i, @function
_Z6vecAddPdS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6vecAddPdS_S_i, .-_Z6vecAddPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Runtime for GPU is: "
.LC2:
.string " ms "
.LC4:
.string "Runtime for CPU is: "
.LC5:
.string "GPU is faster than CPU for "
.LC6:
.string "CPU is faster than GPU for "
.LC7:
.string "same time for GPU and CPU"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 32(%rsp), %ebx
movslq %ebx, %r14
leaq 0(,%r14,8), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L12
movl $0, %ebx
leaq 24(%rsp), %rax
movq %rax, 8(%rsp)
.L13:
leaq 16(%rsp), %rsi
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movq 8(%rsp), %rdi
call sincos@PLT
movsd 16(%rsp), %xmm0
movsd 24(%rsp), %xmm1
mulsd %xmm1, %xmm1
movsd %xmm1, (%r12,%rbx,8)
mulsd %xmm0, %xmm0
movsd %xmm0, 0(%rbp,%rbx,8)
addq $1, %rbx
cmpq %rbx, %r14
jne .L13
.L12:
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
leal 16382(%rax), %ebx
subl $1, %eax
cmovns %eax, %ebx
sarl $14, %ebx
addl $1, %ebx
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %ebx, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L14:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r15, %rdx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 32(%rsp), %edx
testl %edx, %edx
jle .L15
movslq %edx, %rdx
salq $3, %rdx
movl $0, %eax
.L16:
movsd (%r12,%rax), %xmm0
addsd 0(%rbp,%rax), %xmm0
movsd %xmm0, 0(%r13,%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L16
.L15:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
movsd 8(%rsp), %xmm2
comisd %xmm0, %xmm2
ja .L31
comisd 8(%rsp), %xmm0
jbe .L28
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
subsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L19:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl 32(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
jmp .L14
.L31:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm1, %xmm1
cvtss2sd 36(%rsp), %xmm1
movsd 8(%rsp), %xmm0
subsd %xmm1, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L19
.L28:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L19
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z6vecAddPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <assert.h>
#include <iostream>
#include <cstdlib>
#include<sys/time.h>
#include <cmath>
#include "cuda_runtime.h"
const int LANGE = 16;
__global__ void vecAdd(double *d_a, double *d_b, double *d_c, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < (N / LANGE)) {
int large = N / LANGE;
for (int i = 0; i < LANGE; i++)
if (idx % 2 == 0){
d_c[idx + i * large] = d_a[idx + i * large] + d_b[idx + i *large];
}else{
d_c[idx + i * large] = d_a[idx + i * large] - d_b[idx + i * large];
}
}
}
int main (void) {
int n;
std::cin>>n;
assert(n % LANGE == 0);
double *H_a, *H_b, *H_c;
size_t bytes = n * sizeof(double);
H_a = (double*)malloc(bytes);
H_b = (double*)malloc(bytes);
H_c = (double*)malloc(bytes);
for (int i = 0; i < n; i++) {
H_a[i] = sin(i) * sin(i);
H_b[i] = cos(i) * cos(i);
}
//GPU parper
double *d_a, *d_b, *d_c;
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
cudaMemcpy(d_a, H_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b, H_b, bytes, cudaMemcpyHostToDevice);
int blockSize = 1024;
int gridSize = ((n-1)/LANGE)/blockSize + 1;
cudaEvent_t start, stop;
cudaEventCreate(&start);
cudaEventCreate(&stop);
//gpu running
cudaEventRecord(start);
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
cudaEventRecord(stop);
cudaDeviceSynchronize();
cudaMemcpy(H_c, d_c, bytes, cudaMemcpyDeviceToHost);
cudaEventSynchronize(stop);
float timeGPU = 0;
cudaEventElapsedTime(&timeGPU, start, stop);
std::cout << "Runtime for GPU is: " << timeGPU<<" ms "<< std::endl;
//CPU running.....
struct timeval startCPU,endCPU;
gettimeofday(&startCPU,NULL);
for (int i = 0; i < n; i++) {
H_c[i] = H_a[i] + H_b[i];
}
gettimeofday(&endCPU,NULL);
double timeCPU = endCPU.tv_sec - startCPU.tv_sec + (double)(endCPU.tv_usec - startCPU.tv_usec)/1000000;
std::cout << "Runtime for CPU is: " << timeCPU <<" ms "<< std::endl;
//summary
if(timeGPU<timeCPU){
std::cout<<"GPU is faster than CPU for "<<timeCPU-timeGPU<<" ms "<<std::endl;
}else if(timeGPU>timeCPU){
std::cout<<"CPU is faster than GPU for "<<timeGPU-timeCPU<<" ms "<<std::endl;
}else{
std::cout<<"same time for GPU and CPU"<<std::endl;
}
free(H_a);
free(H_b);
free(H_c);
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
return 0;
} | #include <assert.h>
#include <iostream>
#include <cstdlib>
#include<sys/time.h>
#include <cmath>
#include "hip/hip_runtime.h"
const int LANGE = 16;
__global__ void vecAdd(double *d_a, double *d_b, double *d_c, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < (N / LANGE)) {
int large = N / LANGE;
for (int i = 0; i < LANGE; i++)
if (idx % 2 == 0){
d_c[idx + i * large] = d_a[idx + i * large] + d_b[idx + i *large];
}else{
d_c[idx + i * large] = d_a[idx + i * large] - d_b[idx + i * large];
}
}
}
int main (void) {
int n;
std::cin>>n;
assert(n % LANGE == 0);
double *H_a, *H_b, *H_c;
size_t bytes = n * sizeof(double);
H_a = (double*)malloc(bytes);
H_b = (double*)malloc(bytes);
H_c = (double*)malloc(bytes);
for (int i = 0; i < n; i++) {
H_a[i] = sin(i) * sin(i);
H_b[i] = cos(i) * cos(i);
}
//GPU parper
double *d_a, *d_b, *d_c;
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
hipMemcpy(d_a, H_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, H_b, bytes, hipMemcpyHostToDevice);
int blockSize = 1024;
int gridSize = ((n-1)/LANGE)/blockSize + 1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//gpu running
hipEventRecord(start);
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
hipEventRecord(stop);
hipDeviceSynchronize();
hipMemcpy(H_c, d_c, bytes, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float timeGPU = 0;
hipEventElapsedTime(&timeGPU, start, stop);
std::cout << "Runtime for GPU is: " << timeGPU<<" ms "<< std::endl;
//CPU running.....
struct timeval startCPU,endCPU;
gettimeofday(&startCPU,NULL);
for (int i = 0; i < n; i++) {
H_c[i] = H_a[i] + H_b[i];
}
gettimeofday(&endCPU,NULL);
double timeCPU = endCPU.tv_sec - startCPU.tv_sec + (double)(endCPU.tv_usec - startCPU.tv_usec)/1000000;
std::cout << "Runtime for CPU is: " << timeCPU <<" ms "<< std::endl;
//summary
if(timeGPU<timeCPU){
std::cout<<"GPU is faster than CPU for "<<timeCPU-timeGPU<<" ms "<<std::endl;
}else if(timeGPU>timeCPU){
std::cout<<"CPU is faster than GPU for "<<timeGPU-timeCPU<<" ms "<<std::endl;
}else{
std::cout<<"same time for GPU and CPU"<<std::endl;
}
free(H_a);
free(H_b);
free(H_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <assert.h>
#include <iostream>
#include <cstdlib>
#include<sys/time.h>
#include <cmath>
#include "hip/hip_runtime.h"
const int LANGE = 16;
__global__ void vecAdd(double *d_a, double *d_b, double *d_c, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < (N / LANGE)) {
int large = N / LANGE;
for (int i = 0; i < LANGE; i++)
if (idx % 2 == 0){
d_c[idx + i * large] = d_a[idx + i * large] + d_b[idx + i *large];
}else{
d_c[idx + i * large] = d_a[idx + i * large] - d_b[idx + i * large];
}
}
}
int main (void) {
int n;
std::cin>>n;
assert(n % LANGE == 0);
double *H_a, *H_b, *H_c;
size_t bytes = n * sizeof(double);
H_a = (double*)malloc(bytes);
H_b = (double*)malloc(bytes);
H_c = (double*)malloc(bytes);
for (int i = 0; i < n; i++) {
H_a[i] = sin(i) * sin(i);
H_b[i] = cos(i) * cos(i);
}
//GPU parper
double *d_a, *d_b, *d_c;
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
hipMemcpy(d_a, H_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, H_b, bytes, hipMemcpyHostToDevice);
int blockSize = 1024;
int gridSize = ((n-1)/LANGE)/blockSize + 1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//gpu running
hipEventRecord(start);
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
hipEventRecord(stop);
hipDeviceSynchronize();
hipMemcpy(H_c, d_c, bytes, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float timeGPU = 0;
hipEventElapsedTime(&timeGPU, start, stop);
std::cout << "Runtime for GPU is: " << timeGPU<<" ms "<< std::endl;
//CPU running.....
struct timeval startCPU,endCPU;
gettimeofday(&startCPU,NULL);
for (int i = 0; i < n; i++) {
H_c[i] = H_a[i] + H_b[i];
}
gettimeofday(&endCPU,NULL);
double timeCPU = endCPU.tv_sec - startCPU.tv_sec + (double)(endCPU.tv_usec - startCPU.tv_usec)/1000000;
std::cout << "Runtime for CPU is: " << timeCPU <<" ms "<< std::endl;
//summary
if(timeGPU<timeCPU){
std::cout<<"GPU is faster than CPU for "<<timeCPU-timeGPU<<" ms "<<std::endl;
}else if(timeGPU>timeCPU){
std::cout<<"CPU is faster than GPU for "<<timeGPU-timeCPU<<" ms "<<std::endl;
}else{
std::cout<<"same time for GPU and CPU"<<std::endl;
}
free(H_a);
free(H_b);
free(H_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPdS_S_i
.globl _Z6vecAddPdS_S_i
.p2align 8
.type _Z6vecAddPdS_S_i,@function
_Z6vecAddPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_ashr_i32 s2, s3, 31
s_lshr_b32 s2, s2, 28
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s3, s3, s2
s_mov_b32 s2, exec_lo
s_ashr_i32 s8, s3, 4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v0, 1, v1
s_mov_b32 s1, 16
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
v_add_nc_u32_e32 v1, s8, v1
s_add_i32 s1, s1, -1
s_cmp_lg_u32 s1, 0
global_store_b64 v[2:3], v[4:5], off
s_cbranch_scc0 .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s5, v3, s0
s_waitcnt vmcnt(0)
v_add_co_u32 v8, s0, s6, v2
v_add_co_ci_u32_e64 v9, s0, s7, v3, s0
global_load_b64 v[6:7], v[4:5], off
global_load_b64 v[8:9], v[8:9], off
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[6:7], -v[8:9]
.LBB0_5:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_2
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[6:7], v[8:9]
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPdS_S_i, .Lfunc_end0-_Z6vecAddPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <assert.h>
#include <iostream>
#include <cstdlib>
#include<sys/time.h>
#include <cmath>
#include "hip/hip_runtime.h"
const int LANGE = 16;
__global__ void vecAdd(double *d_a, double *d_b, double *d_c, int N) {
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < (N / LANGE)) {
int large = N / LANGE;
for (int i = 0; i < LANGE; i++)
if (idx % 2 == 0){
d_c[idx + i * large] = d_a[idx + i * large] + d_b[idx + i *large];
}else{
d_c[idx + i * large] = d_a[idx + i * large] - d_b[idx + i * large];
}
}
}
int main (void) {
int n;
std::cin>>n;
assert(n % LANGE == 0);
double *H_a, *H_b, *H_c;
size_t bytes = n * sizeof(double);
H_a = (double*)malloc(bytes);
H_b = (double*)malloc(bytes);
H_c = (double*)malloc(bytes);
for (int i = 0; i < n; i++) {
H_a[i] = sin(i) * sin(i);
H_b[i] = cos(i) * cos(i);
}
//GPU parper
double *d_a, *d_b, *d_c;
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
hipMemcpy(d_a, H_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b, H_b, bytes, hipMemcpyHostToDevice);
int blockSize = 1024;
int gridSize = ((n-1)/LANGE)/blockSize + 1;
hipEvent_t start, stop;
hipEventCreate(&start);
hipEventCreate(&stop);
//gpu running
hipEventRecord(start);
vecAdd<<<gridSize, blockSize>>>(d_a, d_b, d_c, n);
hipEventRecord(stop);
hipDeviceSynchronize();
hipMemcpy(H_c, d_c, bytes, hipMemcpyDeviceToHost);
hipEventSynchronize(stop);
float timeGPU = 0;
hipEventElapsedTime(&timeGPU, start, stop);
std::cout << "Runtime for GPU is: " << timeGPU<<" ms "<< std::endl;
//CPU running.....
struct timeval startCPU,endCPU;
gettimeofday(&startCPU,NULL);
for (int i = 0; i < n; i++) {
H_c[i] = H_a[i] + H_b[i];
}
gettimeofday(&endCPU,NULL);
double timeCPU = endCPU.tv_sec - startCPU.tv_sec + (double)(endCPU.tv_usec - startCPU.tv_usec)/1000000;
std::cout << "Runtime for CPU is: " << timeCPU <<" ms "<< std::endl;
//summary
if(timeGPU<timeCPU){
std::cout<<"GPU is faster than CPU for "<<timeCPU-timeGPU<<" ms "<<std::endl;
}else if(timeGPU>timeCPU){
std::cout<<"CPU is faster than GPU for "<<timeGPU-timeCPU<<" ms "<<std::endl;
}else{
std::cout<<"same time for GPU and CPU"<<std::endl;
}
free(H_a);
free(H_b);
free(H_c);
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
return 0;
} | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__vecAddPdS_S_i # -- Begin function _Z21__device_stub__vecAddPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPdS_S_i,@function
_Z21__device_stub__vecAddPdS_S_i: # @_Z21__device_stub__vecAddPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPdS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movslq 12(%rsp), %r13
leaq (,%r13,8), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
testq %r13, %r13
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 40(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r13,8)
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, 40(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r14,%r13,8)
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq 72(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 72(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %r13d
leal -1(%r13), %eax
addl $16382, %r13d # imm = 0x3FFE
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $14, %r13d
incl %r13d
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r13
orq $1024, %rdx # imm = 0x400
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movl 12(%rsp), %esi
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movl %esi, 84(%rsp)
leaq 184(%rsp), %rax
movq %rax, 112(%rsp)
leaq 176(%rsp), %rax
movq %rax, 120(%rsp)
leaq 168(%rsp), %rax
movq %rax, 128(%rsp)
leaq 84(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6vecAddPdS_S_i, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movq 56(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipEventSynchronize
movl $0, 24(%rsp)
movq 104(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_32
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB1_8
# %bb.7:
movzbl 67(%r13), %eax
jmp .LBB1_9
.LBB1_8:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_12
# %bb.10: # %.lr.ph70.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_11: # %.lr.ph70
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rcx,8), %xmm0 # xmm0 = mem[0],zero
addsd (%r14,%rcx,8), %xmm0
movsd %xmm0, (%r15,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_11
.LBB1_12: # %._crit_edge71
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 88(%rsp), %rax
movq 96(%rsp), %rcx
subq 112(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 120(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
divsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_32
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%r13)
je .LBB1_15
# %bb.14:
movzbl 67(%r13), %eax
jmp .LBB1_16
.LBB1_15:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movl $_ZSt4cout, %edi
ucomisd %xmm0, %xmm1
jbe .LBB1_20
# %bb.17:
movl $.L.str.3, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_32
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r13)
je .LBB1_24
.LBB1_19:
movzbl 67(%r13), %eax
jmp .LBB1_25
.LBB1_20:
ucomisd %xmm1, %xmm0
jbe .LBB1_26
# %bb.21:
movl $.L.str.4, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_32
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r13)
jne .LBB1_19
.LBB1_24:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movq %r12, %rdi
jmp .LBB1_31
.LBB1_26:
movl $.L.str.5, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_32
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%r12)
je .LBB1_29
# %bb.28:
movzbl 67(%r12), %eax
jmp .LBB1_30
.LBB1_29:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movl $_ZSt4cout, %edi
.LBB1_31:
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_32:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPdS_S_i,@object # @_Z6vecAddPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPdS_S_i
.p2align 3, 0x0
_Z6vecAddPdS_S_i:
.quad _Z21__device_stub__vecAddPdS_S_i
.size _Z6vecAddPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Runtime for GPU is: "
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Runtime for CPU is: "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU is faster than CPU for "
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU is faster than GPU for "
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "same time for GPU and CPU"
.size .L.str.5, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPdS_S_i
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6vecAddPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e220000002500 */
/*0020*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0040*/ SHF.R.S32.HI R0, RZ, 0x1f, R0 ; /* 0x0000001fff007819 */
/* 0x000fc80000011400 */
/*0050*/ LEA.HI R0, R0, c[0x0][0x178], RZ, 0x4 ; /* 0x00005e0000007a11 */
/* 0x000fc800078f20ff */
/*0060*/ SHF.R.S32.HI R0, RZ, 0x4, R0 ; /* 0x00000004ff007819 */
/* 0x000fe20000011400 */
/*0070*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0080*/ ISETP.GE.AND P0, PT, R3, R0, PT ; /* 0x000000000300720c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R2, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff027435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R8, R3, R2, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fca00078e0202 */
/*00d0*/ LDG.E.64 R4, [R8.64] ; /* 0x0000000408047981 */
/* 0x000ea2000c1e1b00 */
/*00e0*/ IMAD.WIDE R6, R3, R2, c[0x0][0x160] ; /* 0x0000580003067625 */
/* 0x000fca00078e0202 */
/*00f0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x0000e2000c1e1b00 */
/*0100*/ LOP3.LUT R14, R3, 0x1, RZ, 0xc0, !PT ; /* 0x00000001030e7812 */
/* 0x000fc800078ec0ff */
/*0110*/ ISETP.NE.U32.AND P0, PT, R14, 0x1, PT ; /* 0x000000010e00780c */
/* 0x000fe20003f05070 */
/*0120*/ IMAD.WIDE R6, R0, 0x8, R6 ; /* 0x0000000800067825 */
/* 0x001fe200078e0206 */
/*0130*/ DADD R12, -RZ, -R4 ; /* 0x00000000ff0c7229 */
/* 0x004e140000000904 */
/*0140*/ FSEL R4, R12, R4, !P0 ; /* 0x000000040c047208 */
/* 0x001fe40004000000 */
/*0150*/ FSEL R5, R13, R5, !P0 ; /* 0x000000050d057208 */
/* 0x000fe20004000000 */
/*0160*/ IMAD.WIDE R12, R0, 0x8, R8 ; /* 0x00000008000c7825 */
/* 0x000fca00078e0208 */
/*0170*/ DADD R10, R10, R4 ; /* 0x000000000a0a7229 */
/* 0x0080640000000004 */
/*0180*/ IMAD.WIDE R4, R3, R2, c[0x0][0x170] ; /* 0x00005c0003047625 */
/* 0x001fca00078e0202 */
/*0190*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0021e8000c101b04 */
/*01a0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea8000c1e1b00 */
/*01b0*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*01c0*/ IADD3 R3, R0.reuse, R0, R3 ; /* 0x0000000000037210 */
/* 0x040fe20007ffe003 */
/*01d0*/ IMAD.WIDE R14, R0, 0x8, R4 ; /* 0x00000008000e7825 */
/* 0x000fc800078e0204 */
/*01e0*/ IMAD.WIDE R16, R3, R2, c[0x0][0x168] ; /* 0x00005a0003107625 */
/* 0x000fc800078e0202 */
/*01f0*/ IMAD.WIDE R4, R3, R2, c[0x0][0x160] ; /* 0x0000580003047625 */
/* 0x001fe200078e0202 */
/*0200*/ DADD R8, -RZ, -R12 ; /* 0x00000000ff087229 */
/* 0x004e14000000090c */
/*0210*/ FSEL R8, R8, R12, !P0 ; /* 0x0000000c08087208 */
/* 0x001fe40004000000 */
/*0220*/ FSEL R9, R9, R13, !P0 ; /* 0x0000000d09097208 */
/* 0x000fcc0004000000 */
/*0230*/ DADD R8, R6, R8 ; /* 0x0000000006087229 */
/* 0x008e0e0000000008 */
/*0240*/ STG.E.64 [R14.64], R8 ; /* 0x000000080e007986 */
/* 0x0011e8000c101b04 */
/*0250*/ LDG.E.64 R10, [R16.64] ; /* 0x00000004100a7981 */
/* 0x000ea8000c1e1b00 */
/*0260*/ LDG.E.64 R6, [R4.64] ; /* 0x0000000404067981 */
/* 0x000ee2000c1e1b00 */
/*0270*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fc800078e0202 */
/*0280*/ IMAD.WIDE R8, R0, 0x8, R4 ; /* 0x0000000800087825 */
/* 0x001fe200078e0204 */
/*0290*/ DADD R12, -RZ, -R10 ; /* 0x00000000ff0c7229 */
/* 0x004e14000000090a */
/*02a0*/ FSEL R10, R12, R10, !P0 ; /* 0x0000000a0c0a7208 */
/* 0x001fe40004000000 */
/*02b0*/ FSEL R11, R13, R11, !P0 ; /* 0x0000000b0d0b7208 */
/* 0x000fcc0004000000 */
/*02c0*/ DADD R6, R6, R10 ; /* 0x0000000006067229 */
/* 0x008064000000000a */
/*02d0*/ IMAD.WIDE R10, R0, 0x8, R16 ; /* 0x00000008000a7825 */
/* 0x001fca00078e0210 */
/*02e0*/ STG.E.64 [R2.64], R6 ; /* 0x0000000602007986 */
/* 0x0021e8000c101b04 */
/*02f0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x000ea8000c1e1b00 */
/*0300*/ LDG.E.64 R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x000ee2000c1e1b00 */
/*0310*/ DADD R4, -RZ, -R12 ; /* 0x00000000ff047229 */
/* 0x004e54000000090c */
/*0320*/ FSEL R4, R4, R12, !P0 ; /* 0x0000000c04047208 */
/* 0x002fe40004000000 */
/*0330*/ FSEL R5, R5, R13, !P0 ; /* 0x0000000d05057208 */
/* 0x000fe20004000000 */
/*0340*/ IMAD.WIDE R12, R0, 0x8, R10 ; /* 0x00000008000c7825 */
/* 0x000fca00078e020a */
/*0350*/ DADD R14, R14, R4 ; /* 0x000000000e0e7229 */
/* 0x0082a40000000004 */
/*0360*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x002fca00078e0202 */
/*0370*/ STG.E.64 [R4.64], R14 ; /* 0x0000000e04007986 */
/* 0x0043e8000c101b04 */
/*0380*/ LDG.E.64 R6, [R12.64] ; /* 0x000000040c067981 */
/* 0x001ea2000c1e1b00 */
/*0390*/ IMAD.WIDE R2, R0, 0x8, R8 ; /* 0x0000000800027825 */
/* 0x000fca00078e0208 */
/*03a0*/ LDG.E.64 R10, [R2.64] ; /* 0x00000004020a7981 */
/* 0x000ee2000c1e1b00 */
/*03b0*/ DADD R8, -RZ, -R6 ; /* 0x00000000ff087229 */
/* 0x004e140000000906 */
/*03c0*/ FSEL R6, R8, R6, !P0 ; /* 0x0000000608067208 */
/* 0x001fe40004000000 */
/*03d0*/ FSEL R7, R9, R7, !P0 ; /* 0x0000000709077208 */
/* 0x000fe20004000000 */
/*03e0*/ IMAD.WIDE R8, R0, 0x8, R12 ; /* 0x0000000800087825 */
/* 0x000fca00078e020c */
/*03f0*/ DADD R10, R10, R6 ; /* 0x000000000a0a7229 */
/* 0x0080a40000000006 */
/*0400*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x001fca00078e0204 */
/*0410*/ STG.E.64 [R6.64], R10 ; /* 0x0000000a06007986 */
/* 0x0041e8000c101b04 */
/*0420*/ LDG.E.64 R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x002ea2000c1e1b00 */
/*0430*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x000fca00078e0202 */
/*0440*/ LDG.E.64 R12, [R4.64] ; /* 0x00000004040c7981 */
/* 0x000ee2000c1e1b00 */
/*0450*/ DADD R2, -RZ, -R14 ; /* 0x00000000ff027229 */
/* 0x004e54000000090e */
/*0460*/ FSEL R2, R2, R14, !P0 ; /* 0x0000000e02027208 */
/* 0x002fe40004000000 */
/*0470*/ FSEL R3, R3, R15, !P0 ; /* 0x0000000f03037208 */
/* 0x000fe20004000000 */
/*0480*/ IMAD.WIDE R14, R0, 0x8, R8 ; /* 0x00000008000e7825 */
/* 0x000fca00078e0208 */
/*0490*/ DADD R12, R12, R2 ; /* 0x000000000c0c7229 */
/* 0x0082a40000000002 */
/*04a0*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x002fca00078e0206 */
/*04b0*/ STG.E.64 [R2.64], R12 ; /* 0x0000000c02007986 */
/* 0x0043e8000c101b04 */
/*04c0*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x001ea2000c1e1b00 */
/*04d0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x000fca00078e0204 */
/*04e0*/ LDG.E.64 R8, [R6.64] ; /* 0x0000000406087981 */
/* 0x000ee2000c1e1b00 */
/*04f0*/ DADD R4, -RZ, -R10 ; /* 0x00000000ff047229 */
/* 0x004e14000000090a */
/*0500*/ FSEL R4, R4, R10, !P0 ; /* 0x0000000a04047208 */
/* 0x001fe40004000000 */
/*0510*/ FSEL R5, R5, R11, !P0 ; /* 0x0000000b05057208 */
/* 0x000fe20004000000 */
/*0520*/ IMAD.WIDE R10, R0, 0x8, R14 ; /* 0x00000008000a7825 */
/* 0x000fca00078e020e */
/*0530*/ DADD R8, R8, R4 ; /* 0x0000000008087229 */
/* 0x0080a40000000004 */
/*0540*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x001fca00078e0202 */
/*0550*/ STG.E.64 [R4.64], R8 ; /* 0x0000000804007986 */
/* 0x0041e8000c101b04 */
/*0560*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x002ea2000c1e1b00 */
/*0570*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x000fca00078e0206 */
/*0580*/ LDG.E.64 R14, [R2.64] ; /* 0x00000004020e7981 */
/* 0x000ee2000c1e1b00 */
/*0590*/ DADD R6, -RZ, -R12 ; /* 0x00000000ff067229 */
/* 0x004e54000000090c */
/*05a0*/ FSEL R6, R6, R12, !P0 ; /* 0x0000000c06067208 */
/* 0x002fe40004000000 */
/*05b0*/ FSEL R7, R7, R13, !P0 ; /* 0x0000000d07077208 */
/* 0x000fe20004000000 */
/*05c0*/ IMAD.WIDE R12, R0, 0x8, R10 ; /* 0x00000008000c7825 */
/* 0x000fca00078e020a */
/*05d0*/ DADD R14, R14, R6 ; /* 0x000000000e0e7229 */
/* 0x0082a40000000006 */
/*05e0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x002fca00078e0204 */
/*05f0*/ STG.E.64 [R6.64], R14 ; /* 0x0000000e06007986 */
/* 0x0043e8000c101b04 */
/*0600*/ LDG.E.64 R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x001ea2000c1e1b00 */
/*0610*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x000fca00078e0202 */
/*0620*/ LDG.E.64 R10, [R4.64] ; /* 0x00000004040a7981 */
/* 0x000ee2000c1e1b00 */
/*0630*/ DADD R2, -RZ, -R8 ; /* 0x00000000ff027229 */
/* 0x004e140000000908 */
/*0640*/ FSEL R2, R2, R8, !P0 ; /* 0x0000000802027208 */
/* 0x001fe40004000000 */
/*0650*/ FSEL R3, R3, R9, !P0 ; /* 0x0000000903037208 */
/* 0x000fe20004000000 */
/*0660*/ IMAD.WIDE R8, R0, 0x8, R12 ; /* 0x0000000800087825 */
/* 0x000fca00078e020c */
/*0670*/ DADD R10, R10, R2 ; /* 0x000000000a0a7229 */
/* 0x0080a40000000002 */
/*0680*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x001fca00078e0206 */
/*0690*/ STG.E.64 [R2.64], R10 ; /* 0x0000000a02007986 */
/* 0x0041e8000c101b04 */
/*06a0*/ LDG.E.64 R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x002ea2000c1e1b00 */
/*06b0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x000fca00078e0204 */
/*06c0*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ee2000c1e1b00 */
/*06d0*/ DADD R4, -RZ, -R14 ; /* 0x00000000ff047229 */
/* 0x004e54000000090e */
/*06e0*/ FSEL R4, R4, R14, !P0 ; /* 0x0000000e04047208 */
/* 0x002fe40004000000 */
/*06f0*/ FSEL R5, R5, R15, !P0 ; /* 0x0000000f05057208 */
/* 0x000fe20004000000 */
/*0700*/ IMAD.WIDE R14, R0, 0x8, R8 ; /* 0x00000008000e7825 */
/* 0x000fca00078e0208 */
/*0710*/ DADD R12, R12, R4 ; /* 0x000000000c0c7229 */
/* 0x0082a40000000004 */
/*0720*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x002fca00078e0202 */
/*0730*/ STG.E.64 [R4.64], R12 ; /* 0x0000000c04007986 */
/* 0x0043e8000c101b04 */
/*0740*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x001ea2000c1e1b00 */
/*0750*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x000fca00078e0206 */
/*0760*/ LDG.E.64 R8, [R2.64] ; /* 0x0000000402087981 */
/* 0x000ee2000c1e1b00 */
/*0770*/ DADD R6, -RZ, -R10 ; /* 0x00000000ff067229 */
/* 0x004e14000000090a */
/*0780*/ FSEL R6, R6, R10, !P0 ; /* 0x0000000a06067208 */
/* 0x001fe40004000000 */
/*0790*/ FSEL R7, R7, R11, !P0 ; /* 0x0000000b07077208 */
/* 0x000fe20004000000 */
/*07a0*/ IMAD.WIDE R10, R0, 0x8, R14 ; /* 0x00000008000a7825 */
/* 0x000fca00078e020e */
/*07b0*/ DADD R8, R8, R6 ; /* 0x0000000008087229 */
/* 0x0080a40000000006 */
/*07c0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x001fca00078e0204 */
/*07d0*/ STG.E.64 [R6.64], R8 ; /* 0x0000000806007986 */
/* 0x0041e8000c101b04 */
/*07e0*/ LDG.E.64 R12, [R10.64] ; /* 0x000000040a0c7981 */
/* 0x002ea2000c1e1b00 */
/*07f0*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x000fca00078e0202 */
/*0800*/ LDG.E.64 R14, [R4.64] ; /* 0x00000004040e7981 */
/* 0x000ee2000c1e1b00 */
/*0810*/ DADD R2, -RZ, -R12 ; /* 0x00000000ff027229 */
/* 0x004e54000000090c */
/*0820*/ FSEL R2, R2, R12, !P0 ; /* 0x0000000c02027208 */
/* 0x002fe40004000000 */
/*0830*/ FSEL R3, R3, R13, !P0 ; /* 0x0000000d03037208 */
/* 0x000fe20004000000 */
/*0840*/ IMAD.WIDE R12, R0, 0x8, R10 ; /* 0x00000008000c7825 */
/* 0x000fca00078e020a */
/*0850*/ DADD R14, R14, R2 ; /* 0x000000000e0e7229 */
/* 0x0082a40000000002 */
/*0860*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x002fca00078e0206 */
/*0870*/ STG.E.64 [R2.64], R14 ; /* 0x0000000e02007986 */
/* 0x0043e8000c101b04 */
/*0880*/ LDG.E.64 R8, [R12.64] ; /* 0x000000040c087981 */
/* 0x001ea2000c1e1b00 */
/*0890*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x000fca00078e0204 */
/*08a0*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x000ee2000c1e1b00 */
/*08b0*/ DADD R4, -RZ, -R8 ; /* 0x00000000ff047229 */
/* 0x004e140000000908 */
/*08c0*/ FSEL R4, R4, R8, !P0 ; /* 0x0000000804047208 */
/* 0x001fe40004000000 */
/*08d0*/ FSEL R5, R5, R9, !P0 ; /* 0x0000000905057208 */
/* 0x000fe20004000000 */
/*08e0*/ IMAD.WIDE R8, R0, 0x8, R12 ; /* 0x0000000800087825 */
/* 0x000fca00078e020c */
/*08f0*/ DADD R10, R10, R4 ; /* 0x000000000a0a7229 */
/* 0x0080a40000000004 */
/*0900*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x001fca00078e0202 */
/*0910*/ STG.E.64 [R4.64], R10 ; /* 0x0000000a04007986 */
/* 0x0041e8000c101b04 */
/*0920*/ LDG.E.64 R14, [R8.64] ; /* 0x00000004080e7981 */
/* 0x002ea2000c1e1b00 */
/*0930*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x000fca00078e0206 */
/*0940*/ LDG.E.64 R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000ee2000c1e1b00 */
/*0950*/ DADD R6, -RZ, -R14 ; /* 0x00000000ff067229 */
/* 0x004e54000000090e */
/*0960*/ FSEL R6, R6, R14, !P0 ; /* 0x0000000e06067208 */
/* 0x002fe40004000000 */
/*0970*/ FSEL R7, R7, R15, !P0 ; /* 0x0000000f07077208 */
/* 0x000fe20004000000 */
/*0980*/ IMAD.WIDE R14, R0, 0x8, R8 ; /* 0x00000008000e7825 */
/* 0x000fca00078e0208 */
/*0990*/ DADD R12, R12, R6 ; /* 0x000000000c0c7229 */
/* 0x0082a40000000006 */
/*09a0*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x002fca00078e0204 */
/*09b0*/ STG.E.64 [R6.64], R12 ; /* 0x0000000c06007986 */
/* 0x0043e8000c101b04 */
/*09c0*/ LDG.E.64 R10, [R14.64] ; /* 0x000000040e0a7981 */
/* 0x001ea2000c1e1b00 */
/*09d0*/ IMAD.WIDE R4, R0, 0x8, R2 ; /* 0x0000000800047825 */
/* 0x000fca00078e0202 */
/*09e0*/ LDG.E.64 R8, [R4.64] ; /* 0x0000000404087981 */
/* 0x000ee2000c1e1b00 */
/*09f0*/ DADD R2, -RZ, -R10 ; /* 0x00000000ff027229 */
/* 0x004e14000000090a */
/*0a00*/ FSEL R2, R2, R10, !P0 ; /* 0x0000000a02027208 */
/* 0x001fe40004000000 */
/*0a10*/ FSEL R3, R3, R11, !P0 ; /* 0x0000000b03037208 */
/* 0x000fe20004000000 */
/*0a20*/ IMAD.WIDE R10, R0, 0x8, R14 ; /* 0x00000008000a7825 */
/* 0x000fca00078e020e */
/*0a30*/ DADD R8, R8, R2 ; /* 0x0000000008087229 */
/* 0x0080a40000000002 */
/*0a40*/ IMAD.WIDE R2, R0, 0x8, R6 ; /* 0x0000000800027825 */
/* 0x001fca00078e0206 */
/*0a50*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x004fe8000c101b04 */
/*0a60*/ LDG.E.64 R10, [R10.64] ; /* 0x000000040a0a7981 */
/* 0x000ea2000c1e1b00 */
/*0a70*/ IMAD.WIDE R6, R0, 0x8, R4 ; /* 0x0000000800067825 */
/* 0x002fcc00078e0204 */
/*0a80*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ee2000c1e1b00 */
/*0a90*/ IMAD.WIDE R12, R0, 0x8, R2 ; /* 0x00000008000c7825 */
/* 0x000fe200078e0202 */
/*0aa0*/ DADD R4, -RZ, -R10 ; /* 0x00000000ff047229 */
/* 0x004e14000000090a */
/*0ab0*/ FSEL R4, R4, R10, !P0 ; /* 0x0000000a04047208 */
/* 0x001fe40004000000 */
/*0ac0*/ FSEL R5, R5, R11, !P0 ; /* 0x0000000b05057208 */
/* 0x000fcc0004000000 */
/*0ad0*/ DADD R4, R6, R4 ; /* 0x0000000006047229 */
/* 0x008e0e0000000004 */
/*0ae0*/ STG.E.64 [R12.64], R4 ; /* 0x000000040c007986 */
/* 0x001fe2000c101b04 */
/*0af0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b00*/ BRA 0xb00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6vecAddPdS_S_i
.globl _Z6vecAddPdS_S_i
.p2align 8
.type _Z6vecAddPdS_S_i,@function
_Z6vecAddPdS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_ashr_i32 s2, s3, 31
s_lshr_b32 s2, s2, 28
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s3, s3, s2
s_mov_b32 s2, exec_lo
s_ashr_i32 s8, s3, 4
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB0_7
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
v_and_b32_e32 v0, 1, v1
s_mov_b32 s1, 16
s_delay_alu instid0(VALU_DEP_1)
v_cmp_eq_u32_e32 vcc_lo, 1, v0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_3
.p2align 6
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
v_add_nc_u32_e32 v1, s8, v1
s_add_i32 s1, s1, -1
s_cmp_lg_u32 s1, 0
global_store_b64 v[2:3], v[4:5], off
s_cbranch_scc0 .LBB0_7
.LBB0_3:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, s0, s4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v5, s0, s5, v3, s0
s_waitcnt vmcnt(0)
v_add_co_u32 v8, s0, s6, v2
v_add_co_ci_u32_e64 v9, s0, s7, v3, s0
global_load_b64 v[6:7], v[4:5], off
global_load_b64 v[8:9], v[8:9], off
s_and_saveexec_b32 s0, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[6:7], -v[8:9]
.LBB0_5:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_2
s_waitcnt vmcnt(0)
v_add_f64 v[4:5], v[6:7], v[8:9]
s_branch .LBB0_2
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6vecAddPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6vecAddPdS_S_i, .Lfunc_end0-_Z6vecAddPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6vecAddPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6vecAddPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fdae9_00000000-6_main.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3672:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i:
.LFB3694:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6vecAddPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3694:
.size _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
.globl _Z6vecAddPdS_S_i
.type _Z6vecAddPdS_S_i, @function
_Z6vecAddPdS_S_i:
.LFB3695:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3695:
.size _Z6vecAddPdS_S_i, .-_Z6vecAddPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Runtime for GPU is: "
.LC2:
.string " ms "
.LC4:
.string "Runtime for CPU is: "
.LC5:
.string "GPU is faster than CPU for "
.LC6:
.string "CPU is faster than GPU for "
.LC7:
.string "same time for GPU and CPU"
.text
.globl main
.type main, @function
main:
.LFB3669:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 32(%rsp), %rsi
leaq _ZSt3cin(%rip), %rdi
call _ZNSirsERi@PLT
movl 32(%rsp), %ebx
movslq %ebx, %r14
leaq 0(,%r14,8), %r15
movq %r15, %rdi
call malloc@PLT
movq %rax, %r12
movq %r15, %rdi
call malloc@PLT
movq %rax, %rbp
movq %r15, %rdi
call malloc@PLT
movq %rax, %r13
testl %ebx, %ebx
jle .L12
movl $0, %ebx
leaq 24(%rsp), %rax
movq %rax, 8(%rsp)
.L13:
leaq 16(%rsp), %rsi
pxor %xmm0, %xmm0
cvtsi2sdl %ebx, %xmm0
movq 8(%rsp), %rdi
call sincos@PLT
movsd 16(%rsp), %xmm0
movsd 24(%rsp), %xmm1
mulsd %xmm1, %xmm1
movsd %xmm1, (%r12,%rbx,8)
mulsd %xmm0, %xmm0
movsd %xmm0, 0(%rbp,%rbx,8)
addq $1, %rbx
cmpq %rbx, %r14
jne .L13
.L12:
leaq 40(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
leaq 56(%rsp), %rdi
movq %r15, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %r15, %rdx
movq %r12, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r15, %rdx
movq %rbp, %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl 32(%rsp), %eax
leal 16382(%rax), %ebx
subl $1, %eax
cmovns %eax, %ebx
sarl $14, %ebx
addl $1, %ebx
leaq 64(%rsp), %rdi
call cudaEventCreate@PLT
leaq 72(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 64(%rsp), %rdi
call cudaEventRecord@PLT
movl $1024, 96(%rsp)
movl $1, 100(%rsp)
movl $1, 104(%rsp)
movl %ebx, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movl $1, %ecx
movq 80(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L14:
movl $0, %esi
movq 72(%rsp), %rdi
call cudaEventRecord@PLT
call cudaDeviceSynchronize@PLT
movl $2, %ecx
movq %r15, %rdx
movq 56(%rsp), %rsi
movq %r13, %rdi
call cudaMemcpy@PLT
movq 72(%rsp), %rdi
call cudaEventSynchronize@PLT
movl $0x00000000, 36(%rsp)
leaq 36(%rsp), %rdi
movq 72(%rsp), %rdx
movq 64(%rsp), %rsi
call cudaEventElapsedTime@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 80(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movl 32(%rsp), %edx
testl %edx, %edx
jle .L15
movslq %edx, %rdx
salq $3, %rdx
movl $0, %eax
.L16:
movsd (%r12,%rax), %xmm0
addsd 0(%rbp,%rax), %xmm0
movsd %xmm0, 0(%r13,%rax)
addq $8, %rax
cmpq %rax, %rdx
jne .L16
.L15:
leaq 96(%rsp), %rdi
movl $0, %esi
call gettimeofday@PLT
movq 104(%rsp), %rax
subq 88(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC3(%rip), %xmm0
movq 96(%rsp), %rax
subq 80(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
movsd %xmm0, 8(%rsp)
leaq .LC4(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
movsd 8(%rsp), %xmm2
comisd %xmm0, %xmm2
ja .L31
comisd 8(%rsp), %xmm0
jbe .L28
leaq .LC6(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm0, %xmm0
cvtss2sd 36(%rsp), %xmm0
subsd 8(%rsp), %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L19:
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %r13, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl 32(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z30__device_stub__Z6vecAddPdS_S_iPdS_S_i
jmp .L14
.L31:
leaq .LC5(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
pxor %xmm1, %xmm1
cvtss2sd 36(%rsp), %xmm1
movsd 8(%rsp), %xmm0
subsd %xmm1, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L19
.L28:
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L19
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3669:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "_Z6vecAddPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3697:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _Z6vecAddPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3697:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__vecAddPdS_S_i # -- Begin function _Z21__device_stub__vecAddPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__vecAddPdS_S_i,@function
_Z21__device_stub__vecAddPdS_S_i: # @_Z21__device_stub__vecAddPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6vecAddPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__vecAddPdS_S_i, .Lfunc_end0-_Z21__device_stub__vecAddPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
leaq 12(%rsp), %rsi
movl $_ZSt3cin, %edi
callq _ZNSirsERi
movslq 12(%rsp), %r13
leaq (,%r13,8), %r12
movq %r12, %rdi
callq malloc
movq %rax, %rbx
movq %r12, %rdi
callq malloc
movq %rax, %r14
movq %r12, %rdi
callq malloc
movq %rax, %r15
testq %r13, %r13
jle .LBB1_3
# %bb.1: # %.lr.ph.preheader
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2sd %r13d, %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq sin
movsd %xmm0, 40(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq sin
mulsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%rbx,%r13,8)
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
movsd %xmm0, 40(%rsp) # 8-byte Spill
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq cos
mulsd 40(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, (%r14,%r13,8)
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB1_2
.LBB1_3: # %._crit_edge
leaq 72(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 64(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
movq 72(%rsp), %rdi
movq %rbx, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movq 64(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
movl 12(%rsp), %r13d
leal -1(%r13), %eax
addl $16382, %r13d # imm = 0x3FFE
testl %eax, %eax
cmovnsl %eax, %r13d
sarl $14, %r13d
incl %r13d
leaq 104(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 104(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %r13
orq $1024, %rdx # imm = 0x400
movq %r13, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 72(%rsp), %rax
movq 64(%rsp), %rcx
movq 56(%rsp), %rdx
movl 12(%rsp), %esi
movq %rax, 184(%rsp)
movq %rcx, 176(%rsp)
movq %rdx, 168(%rsp)
movl %esi, 84(%rsp)
leaq 184(%rsp), %rax
movq %rax, 112(%rsp)
leaq 176(%rsp), %rax
movq %rax, 120(%rsp)
leaq 168(%rsp), %rax
movq %rax, 128(%rsp)
leaq 84(%rsp), %rax
movq %rax, 136(%rsp)
leaq 88(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 160(%rsp), %rdx
leaq 152(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6vecAddPdS_S_i, %edi
pushq 152(%rsp)
.cfi_adjust_cfa_offset 8
pushq 168(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 48(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
callq hipDeviceSynchronize
movq 56(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 48(%rsp), %rdi
callq hipEventSynchronize
movl $0, 24(%rsp)
movq 104(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 24(%rsp), %rdi
callq hipEventElapsedTime
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_32
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r13)
je .LBB1_8
# %bb.7:
movzbl 67(%r13), %eax
jmp .LBB1_9
.LBB1_8:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_9: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
leaq 112(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movl 12(%rsp), %eax
testl %eax, %eax
jle .LBB1_12
# %bb.10: # %.lr.ph70.preheader
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_11: # %.lr.ph70
# =>This Inner Loop Header: Depth=1
movsd (%rbx,%rcx,8), %xmm0 # xmm0 = mem[0],zero
addsd (%r14,%rcx,8), %xmm0
movsd %xmm0, (%r15,%rcx,8)
incq %rcx
cmpq %rcx, %rax
jne .LBB1_11
.LBB1_12: # %._crit_edge71
leaq 88(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 88(%rsp), %rax
movq 96(%rsp), %rcx
subq 112(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 120(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
divsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 16(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_32
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i46
cmpb $0, 56(%r13)
je .LBB1_15
# %bb.14:
movzbl 67(%r13), %eax
jmp .LBB1_16
.LBB1_15:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit49
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movsd 16(%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
movl $_ZSt4cout, %edi
ucomisd %xmm0, %xmm1
jbe .LBB1_20
# %bb.17:
movl $.L.str.3, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
xorps %xmm1, %xmm1
cvtss2sd %xmm0, %xmm1
movsd 16(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd %xmm1, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_32
# %bb.18: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i51
cmpb $0, 56(%r13)
je .LBB1_24
.LBB1_19:
movzbl 67(%r13), %eax
jmp .LBB1_25
.LBB1_20:
ucomisd %xmm1, %xmm0
jbe .LBB1_26
# %bb.21:
movl $.L.str.4, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movss 24(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movq %rax, %r12
movl $.L.str.1, %esi
movl $4, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r13
testq %r13, %r13
je .LBB1_32
# %bb.22: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i56
cmpb $0, 56(%r13)
jne .LBB1_19
.LBB1_24:
movq %r13, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r13), %rax
movq %r13, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_25: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit54
movsbl %al, %esi
movq %r12, %rdi
jmp .LBB1_31
.LBB1_26:
movl $.L.str.5, %esi
movl $25, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r12
testq %r12, %r12
je .LBB1_32
# %bb.27: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i61
cmpb $0, 56(%r12)
je .LBB1_29
# %bb.28:
movzbl 67(%r12), %eax
jmp .LBB1_30
.LBB1_29:
movq %r12, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r12), %rax
movq %r12, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit64
movsbl %al, %esi
movl $_ZSt4cout, %edi
.LBB1_31:
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 72(%rsp), %rdi
callq hipFree
movq 64(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_32:
.cfi_def_cfa_offset 240
callq _ZSt16__throw_bad_castv
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6vecAddPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6vecAddPdS_S_i,@object # @_Z6vecAddPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6vecAddPdS_S_i
.p2align 3, 0x0
_Z6vecAddPdS_S_i:
.quad _Z21__device_stub__vecAddPdS_S_i
.size _Z6vecAddPdS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Runtime for GPU is: "
.size .L.str, 21
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " ms "
.size .L.str.1, 5
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Runtime for CPU is: "
.size .L.str.2, 21
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "GPU is faster than CPU for "
.size .L.str.3, 28
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU is faster than GPU for "
.size .L.str.4, 28
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "same time for GPU and CPU"
.size .L.str.5, 26
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6vecAddPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__vecAddPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6vecAddPdS_S_i
.addrsig_sym _ZSt3cin
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_A "q2a.txt"
#define OUTPUT_FILE_NAME_B "q2b.txt"
#define OUTPUT_FILE_NAME_C "q2c.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//printf("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
cudaMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void sharedBucket(int* array, int* result, int n) {
__shared__ int local_array[10];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((local_array+numHundreds), 1);
}
__syncthreads();
if ((threadIdx.x | threadIdx.y | threadIdx.z) == 0) {
for (int i = 0; i < 10; i++) {
atomicAdd((result+i), local_array[i]);
// result[i] = local_array[i];
}
}
__syncthreads();
}
void computeSharedBucket(int* array, int n) {
int* result;
cudaMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
sharedBucket<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, result, n);
cudaDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
__global__
void bucket(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((result+numHundreds), 1);
}
}
__global__
void prescan(int* array, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int local_scan[];
for (int d = 1; d < 10; d *= 2) {
if (index + 1 > d && index < 10) {
array[index] += array[index-d];
}
__syncthreads();
}
}
void computeBucket(int* array, int n) {
int* result;
cudaMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
bucket<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
cudaDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_A, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_A);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
prescan<<<1, 10>>>(result, 10);
output = fopen(OUTPUT_FILE_NAME_C, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_C);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeBucket(array, n);
computeSharedBucket(array, n);
//int min = computeMin(array, n);
//printf("min: %d\n", min);
cudaFree(array);
} | code for sm_80
Function : _Z7prescanPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x160 ; /* 0x0000012000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R2.reuse, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x040fe40007ffe0ff */
/*0070*/ IADD3 R3, R2, -0x2, RZ ; /* 0xfffffffe02037810 */
/* 0x000fe40007ffe0ff */
/*0080*/ ISETP.GT.U32.AND P0, PT, R0, 0x8, PT ; /* 0x000000080000780c */
/* 0x000fe40003f04070 */
/*0090*/ ISETP.GT.U32.AND P1, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fe20003f24070 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R4, R2.reuse, -0x4, RZ ; /* 0xfffffffc02047810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ LOP3.LUT R5, R2.reuse, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe02057812 */
/* 0x040fe200078ec0ff */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*00e0*/ ISETP.GT.U32.AND P2, PT, R4, 0x5, PT ; /* 0x000000050400780c */
/* 0x000fc40003f44070 */
/*00f0*/ ISETP.NE.AND P3, PT, R5, 0x8, PT ; /* 0x000000080500780c */
/* 0x000fc60003f65270 */
/*0100*/ @P0 BRA 0x150 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R5, [R2.64+-0x4] ; /* 0xfffffc0402057981 */
/* 0x000ea4000c1e1900 */
/*0130*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*0140*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ BSSY B0, 0x1e0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0180*/ @P1 BRA 0x1d0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R5, [R2.64+-0x8] ; /* 0xfffff80402057981 */
/* 0x001ea4000c1e1900 */
/*01b0*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*01c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ BSSY B0, 0x260 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0200*/ @P2 BRA 0x250 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R5, [R2.64+-0x10] ; /* 0xfffff00402057981 */
/* 0x001ea4000c1e1900 */
/*0230*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ BSSY B0, 0x2e0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0280*/ @P3 BRA 0x2d0 ; /* 0x0000004000003947 */
/* 0x000fea0003800000 */
/*0290*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R5, [R2.64+-0x20] ; /* 0xffffe00402057981 */
/* 0x001ea4000c1e1900 */
/*02b0*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*02c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6bucketPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R6, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0206 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fe20000000f00 */
/*00b0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*00c0*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x001fc60000000f00 */
/*00d0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*00f0*/ IMAD.HI R4, R2, 0x51eb851f, RZ ; /* 0x51eb851f02047827 */
/* 0x004fca00078e02ff */
/*0100*/ SHF.R.U32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011604 */
/*0110*/ LEA.HI.SX32 R5, R4, R5, 0x1b ; /* 0x0000000504057211 */
/* 0x000fca00078fdaff */
/*0120*/ IMAD.WIDE R4, R5, R6, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0206 */
/*0130*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0001e2000c10e184 */
/*0140*/ @!P0 BRA 0x70 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12sharedBucketPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0050*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000e620000002300 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f26270 */
/*0080*/ LOP3.LUT P0, RZ, R4, R3, R2, 0xfe, !PT ; /* 0x0000000304ff7212 */
/* 0x002fd6000780fe02 */
/*0090*/ @P1 BRA 0x160 ; /* 0x000000c000001947 */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*00e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*00f0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*0100*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f26270 */
/*0110*/ IMAD.HI R4, R2, 0x51eb851f, RZ ; /* 0x51eb851f02047827 */
/* 0x004fca00078e02ff */
/*0120*/ SHF.R.U32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x001fc80000011604 */
/*0130*/ LEA.HI.SX32 R5, R4, R5, 0x1b ; /* 0x0000000504057211 */
/* 0x000fca00078fdaff */
/*0140*/ ATOMS.POPC.INC.32 RZ, [R5.X4+URZ] ; /* 0x0000000005ff7f8c */
/* 0x0001e2000d00403f */
/*0150*/ @!P1 BRA 0xa0 ; /* 0xffffff4000009947 */
/* 0x000fea000383ffff */
/*0160*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ BSSY B0, 0x390 ; /* 0x0000020000007945 */
/* 0x000fe20003800000 */
/*0190*/ @P0 BRA 0x380 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*01a0*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000e620000000c00 */
/*01b0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*01c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*01d0*/ UFLO.U32 UR5, UR4 ; /* 0x00000004000572bd */
/* 0x000fe200080e0000 */
/*01e0*/ LDS.128 R4, [0x10] ; /* 0x00001000ff047984 */
/* 0x001e220000000c00 */
/*01f0*/ UPOPC UR4, UR4 ; /* 0x00000004000472bf */
/* 0x000fe20008000000 */
/*0200*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fc40000000f00 */
/*0210*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000ea80000000000 */
/*0220*/ LDS.64 R12, [0x20] ; /* 0x00002000ff0c7984 */
/* 0x000ee20000000a00 */
/*0230*/ ISETP.EQ.U32.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x004fe2000bf02070 */
/*0240*/ IMAD R15, R8, UR4, RZ ; /* 0x00000004080f7c24 */
/* 0x002fe4000f8e02ff */
/*0250*/ IMAD R9, R9, UR4, RZ ; /* 0x0000000409097c24 */
/* 0x000fe4000f8e02ff */
/*0260*/ IMAD R17, R10, UR4, RZ ; /* 0x000000040a117c24 */
/* 0x000fd0000f8e02ff */
/*0270*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R15 ; /* 0x0000000f0200098e */
/* 0x0003e2000c10e186 */
/*0280*/ IMAD R11, R11, UR4, RZ ; /* 0x000000040b0b7c24 */
/* 0x000fe4000f8e02ff */
/*0290*/ IMAD R19, R4, UR4, RZ ; /* 0x0000000404137c24 */
/* 0x001fe2000f8e02ff */
/*02a0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x4], R9 ; /* 0x000004090200098e */
/* 0x0003e2000c10e186 */
/*02b0*/ IMAD R5, R5, UR4, RZ ; /* 0x0000000405057c24 */
/* 0x000fe4000f8e02ff */
/*02c0*/ IMAD R21, R6, UR4, RZ ; /* 0x0000000406157c24 */
/* 0x000fe2000f8e02ff */
/*02d0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x8], R17 ; /* 0x000008110200098e */
/* 0x0003e2000c10e186 */
/*02e0*/ IMAD R7, R7, UR4, RZ ; /* 0x0000000407077c24 */
/* 0x000fe4000f8e02ff */
/*02f0*/ IMAD R23, R12, UR4, RZ ; /* 0x000000040c177c24 */
/* 0x008fe2000f8e02ff */
/*0300*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0xc], R11 ; /* 0x00000c0b0200098e */
/* 0x0003e2000c10e186 */
/*0310*/ IMAD R13, R13, UR4, RZ ; /* 0x000000040d0d7c24 */
/* 0x000fc6000f8e02ff */
/*0320*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x10], R19 ; /* 0x000010130200098e */
/* 0x0003e8000c10e186 */
/*0330*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x14], R5 ; /* 0x000014050200098e */
/* 0x0003e8000c10e186 */
/*0340*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x18], R21 ; /* 0x000018150200098e */
/* 0x0003e8000c10e186 */
/*0350*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x1c], R7 ; /* 0x00001c070200098e */
/* 0x0003e8000c10e186 */
/*0360*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x20], R23 ; /* 0x000020170200098e */
/* 0x0003e8000c10e186 */
/*0370*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x24], R13 ; /* 0x0000240d0200098e */
/* 0x0003e4000c10e186 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_A "q2a.txt"
#define OUTPUT_FILE_NAME_B "q2b.txt"
#define OUTPUT_FILE_NAME_C "q2c.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//printf("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
cudaMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void sharedBucket(int* array, int* result, int n) {
__shared__ int local_array[10];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((local_array+numHundreds), 1);
}
__syncthreads();
if ((threadIdx.x | threadIdx.y | threadIdx.z) == 0) {
for (int i = 0; i < 10; i++) {
atomicAdd((result+i), local_array[i]);
// result[i] = local_array[i];
}
}
__syncthreads();
}
void computeSharedBucket(int* array, int n) {
int* result;
cudaMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
sharedBucket<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, result, n);
cudaDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
__global__
void bucket(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((result+numHundreds), 1);
}
}
__global__
void prescan(int* array, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int local_scan[];
for (int d = 1; d < 10; d *= 2) {
if (index + 1 > d && index < 10) {
array[index] += array[index-d];
}
__syncthreads();
}
}
void computeBucket(int* array, int n) {
int* result;
cudaMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
bucket<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
cudaDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_A, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_A);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
prescan<<<1, 10>>>(result, 10);
output = fopen(OUTPUT_FILE_NAME_C, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_C);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeBucket(array, n);
computeSharedBucket(array, n);
//int min = computeMin(array, n);
//printf("min: %d\n", min);
cudaFree(array);
} | .file "tmpxft_000840e7_00000000-6_q2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d, "
.text
.globl _Z11fileToArrayPcPi
.type _Z11fileToArrayPcPi, @function
_Z11fileToArrayPcPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
jmp .L4
.L5:
addl $1, %ebx
.L4:
leaq 12(%rsp), %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
jne .L5
movl %ebx, (%r12)
movslq %ebx, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq %rbp, %rdi
call rewind@PLT
cmpl $0, (%r12)
jle .L6
movl $0, %ebx
leaq .LC1(%rip), %r13
.L7:
leaq 12(%rsp), %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 12(%rsp), %edx
movq 16(%rsp), %rax
movl %edx, (%rax,%rbx,4)
addq $1, %rbx
cmpl %ebx, (%r12)
jg .L7
.L6:
movq %rbp, %rdi
call fclose@PLT
movq 16(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L11
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11fileToArrayPcPi, .-_Z11fileToArrayPcPi
.globl _Z35__device_stub__Z12sharedBucketPiS_iPiS_i
.type _Z35__device_stub__Z12sharedBucketPiS_iPiS_i, @function
_Z35__device_stub__Z12sharedBucketPiS_iPiS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sharedBucketPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z12sharedBucketPiS_iPiS_i, .-_Z35__device_stub__Z12sharedBucketPiS_iPiS_i
.globl _Z12sharedBucketPiS_i
.type _Z12sharedBucketPiS_i, @function
_Z12sharedBucketPiS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12sharedBucketPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12sharedBucketPiS_i, .-_Z12sharedBucketPiS_i
.section .rodata.str1.1
.LC2:
.string "w"
.LC3:
.string "q2b.txt"
.LC4:
.string "failed to open file %s\n"
.LC5:
.string "%d"
.LC6:
.string ", %d"
.text
.globl _Z19computeSharedBucketPii
.type _Z19computeSharedBucketPii, @function
_Z19computeSharedBucketPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L21:
movq 8(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L21
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L30
.L23:
movq 8(%rsp), %rax
movl (%rax), %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $4, %ebx
leaq .LC6(%rip), %r12
.L24:
movq 8(%rsp), %rax
movl (%rax,%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L24
movq %rbp, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl %ebp, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call _Z35__device_stub__Z12sharedBucketPiS_iPiS_i
jmp .L22
.L30:
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z19computeSharedBucketPii, .-_Z19computeSharedBucketPii
.globl _Z28__device_stub__Z6bucketPiS_iPiS_i
.type _Z28__device_stub__Z6bucketPiS_iPiS_i, @function
_Z28__device_stub__Z6bucketPiS_iPiS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6bucketPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z28__device_stub__Z6bucketPiS_iPiS_i, .-_Z28__device_stub__Z6bucketPiS_iPiS_i
.globl _Z6bucketPiS_i
.type _Z6bucketPiS_i, @function
_Z6bucketPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6bucketPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z6bucketPiS_i, .-_Z6bucketPiS_i
.globl _Z27__device_stub__Z7prescanPiiPii
.type _Z27__device_stub__Z7prescanPiiPii, @function
_Z27__device_stub__Z7prescanPiiPii:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7prescanPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z27__device_stub__Z7prescanPiiPii, .-_Z27__device_stub__Z7prescanPiiPii
.globl _Z7prescanPii
.type _Z7prescanPii, @function
_Z7prescanPii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7prescanPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z7prescanPii, .-_Z7prescanPii
.section .rodata.str1.1
.LC7:
.string "q2a.txt"
.LC8:
.string "q2c.txt"
.text
.globl _Z13computeBucketPii
.type _Z13computeBucketPii, @function
_Z13computeBucketPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L49:
movq 8(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L49
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L50:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L62
.L51:
movq 8(%rsp), %rax
movl (%rax), %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $4, %ebx
leaq .LC6(%rip), %r12
.L52:
movq 8(%rsp), %rax
movl (%rax,%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L52
movq %rbp, %rdi
call fclose@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L53:
leaq .LC2(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L64
.L54:
movq 8(%rsp), %rax
movl (%rax), %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $4, %ebx
leaq .LC6(%rip), %r12
.L55:
movq 8(%rsp), %rax
movl (%rax,%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L55
movq %rbp, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movl %ebp, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call _Z28__device_stub__Z6bucketPiS_iPiS_i
jmp .L50
.L62:
leaq .LC7(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L63:
movl $10, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7prescanPiiPii
jmp .L53
.L64:
leaq .LC8(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L54
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z13computeBucketPii, .-_Z13computeBucketPii
.section .rodata.str1.1
.LC9:
.string "inp.txt"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC9(%rip), %rdi
call _Z11fileToArrayPcPi
movq %rax, %rbx
movl 4(%rsp), %ebp
movl %ebp, %esi
movq %rax, %rdi
call _Z13computeBucketPii
movl %ebp, %esi
movq %rbx, %rdi
call _Z19computeSharedBucketPii
movq %rbx, %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L69
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z7prescanPii"
.LC11:
.string "_Z6bucketPiS_i"
.LC12:
.string "_Z12sharedBucketPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z7prescanPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6bucketPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sharedBucketPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_A "q2a.txt"
#define OUTPUT_FILE_NAME_B "q2b.txt"
#define OUTPUT_FILE_NAME_C "q2c.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//printf("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
cudaMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void sharedBucket(int* array, int* result, int n) {
__shared__ int local_array[10];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((local_array+numHundreds), 1);
}
__syncthreads();
if ((threadIdx.x | threadIdx.y | threadIdx.z) == 0) {
for (int i = 0; i < 10; i++) {
atomicAdd((result+i), local_array[i]);
// result[i] = local_array[i];
}
}
__syncthreads();
}
void computeSharedBucket(int* array, int n) {
int* result;
cudaMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
sharedBucket<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, result, n);
cudaDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
__global__
void bucket(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((result+numHundreds), 1);
}
}
__global__
void prescan(int* array, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int local_scan[];
for (int d = 1; d < 10; d *= 2) {
if (index + 1 > d && index < 10) {
array[index] += array[index-d];
}
__syncthreads();
}
}
void computeBucket(int* array, int n) {
int* result;
cudaMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
bucket<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
cudaDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_A, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_A);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
prescan<<<1, 10>>>(result, 10);
output = fopen(OUTPUT_FILE_NAME_C, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_C);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeBucket(array, n);
computeSharedBucket(array, n);
//int min = computeMin(array, n);
//printf("min: %d\n", min);
cudaFree(array);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_A "q2a.txt"
#define OUTPUT_FILE_NAME_B "q2b.txt"
#define OUTPUT_FILE_NAME_C "q2c.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//printf("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
hipMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void sharedBucket(int* array, int* result, int n) {
__shared__ int local_array[10];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((local_array+numHundreds), 1);
}
__syncthreads();
if ((threadIdx.x | threadIdx.y | threadIdx.z) == 0) {
for (int i = 0; i < 10; i++) {
atomicAdd((result+i), local_array[i]);
// result[i] = local_array[i];
}
}
__syncthreads();
}
void computeSharedBucket(int* array, int n) {
int* result;
hipMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
sharedBucket<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, result, n);
hipDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
__global__
void bucket(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((result+numHundreds), 1);
}
}
__global__
void prescan(int* array, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int local_scan[];
for (int d = 1; d < 10; d *= 2) {
if (index + 1 > d && index < 10) {
array[index] += array[index-d];
}
__syncthreads();
}
}
void computeBucket(int* array, int n) {
int* result;
hipMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
bucket<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
hipDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_A, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_A);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
prescan<<<1, 10>>>(result, 10);
output = fopen(OUTPUT_FILE_NAME_C, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_C);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeBucket(array, n);
computeSharedBucket(array, n);
//int min = computeMin(array, n);
//printf("min: %d\n", min);
hipFree(array);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_A "q2a.txt"
#define OUTPUT_FILE_NAME_B "q2b.txt"
#define OUTPUT_FILE_NAME_C "q2c.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//printf("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
hipMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void sharedBucket(int* array, int* result, int n) {
__shared__ int local_array[10];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((local_array+numHundreds), 1);
}
__syncthreads();
if ((threadIdx.x | threadIdx.y | threadIdx.z) == 0) {
for (int i = 0; i < 10; i++) {
atomicAdd((result+i), local_array[i]);
// result[i] = local_array[i];
}
}
__syncthreads();
}
void computeSharedBucket(int* array, int n) {
int* result;
hipMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
sharedBucket<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, result, n);
hipDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
__global__
void bucket(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((result+numHundreds), 1);
}
}
__global__
void prescan(int* array, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int local_scan[];
for (int d = 1; d < 10; d *= 2) {
if (index + 1 > d && index < 10) {
array[index] += array[index-d];
}
__syncthreads();
}
}
void computeBucket(int* array, int n) {
int* result;
hipMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
bucket<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
hipDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_A, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_A);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
prescan<<<1, 10>>>(result, 10);
output = fopen(OUTPUT_FILE_NAME_C, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_C);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeBucket(array, n);
computeSharedBucket(array, n);
//int min = computeMin(array, n);
//printf("min: %d\n", min);
hipFree(array);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sharedBucketPiS_i
.globl _Z12sharedBucketPiS_i
.p2align 8
.type _Z12sharedBucketPiS_i,@function
_Z12sharedBucketPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_cmpx_gt_i32_e64 s8, v2
s_cbranch_execz .LBB0_3
s_load_b32 s5, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_ashr_i32 s5, s4, 31
s_mov_b32 s3, 0
s_lshl_b64 s[6:7], s[4:5], 2
.p2align 6
.LBB0_2:
global_load_b32 v6, v[3:4], off
v_add_nc_u32_e32 v2, s4, v2
v_add_co_u32 v3, s2, v3, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
v_cmp_le_i32_e32 vcc_lo, s8, v2
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_mul_hi_i32 v6, v6, 0x51eb851f
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v7, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_lshl_u32 v6, v6, v7, 2
ds_add_u32 v6, v5
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
v_bfe_u32 v2, v0, 20, 10
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
v_or3_b32 v0, v0, v2, v1
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s2, s2, 4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s2, 40
s_cbranch_scc0 .LBB0_8
.LBB0_6:
s_mov_b32 s5, exec_lo
s_mov_b32 s4, exec_lo
v_mbcnt_lo_u32_b32 v1, s5, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, s2
s_bcnt1_i32_b32 s5, s5
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s5
global_atomic_add_u32 v0, v1, s[0:1]
s_branch .LBB0_5
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sharedBucketPiS_i
.amdhsa_group_segment_fixed_size 40
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sharedBucketPiS_i, .Lfunc_end0-_Z12sharedBucketPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6bucketPiS_i
.globl _Z6bucketPiS_i
.p2align 8
.type _Z6bucketPiS_i,@function
_Z6bucketPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB1_3
s_load_b32 s5, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_ashr_i32 s5, s4, 31
s_mov_b32 s1, 0
s_lshl_b64 s[6:7], s[4:5], 2
.p2align 6
.LBB1_2:
global_load_b32 v4, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v2, s0, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
s_waitcnt vmcnt(0)
v_mul_hi_i32 v4, v4, 0x51eb851f
v_lshrrev_b32_e32 v5, 31, v4
v_ashrrev_i32_e32 v4, 5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_atomic_add_u32 v[4:5], v0, off
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6bucketPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6bucketPiS_i, .Lfunc_end1-_Z6bucketPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7prescanPii
.globl _Z7prescanPii
.p2align 8
.type _Z7prescanPii,@function
_Z7prescanPii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_gt_i32_e32 vcc_lo, 10, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s0, s1, 1
s_cmp_gt_u32 s1, 4
s_mov_b32 s1, s0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_4
.LBB2_2:
v_cmp_le_i32_e64 s0, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB2_1
v_subrev_nc_u32_e32 v4, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s2, v4
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
s_clause 0x1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_branch .LBB2_1
.LBB2_4:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7prescanPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7prescanPii, .Lfunc_end2-_Z7prescanPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 40
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sharedBucketPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sharedBucketPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6bucketPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6bucketPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7prescanPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7prescanPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <limits.h>
#define OUTPUT_FILE_NAME_A "q2a.txt"
#define OUTPUT_FILE_NAME_B "q2b.txt"
#define OUTPUT_FILE_NAME_C "q2c.txt"
#define NUM_THREADS_A 32
#define NUM_BLOCKS_A 2
#define NUM_THREADS_B 32
#define NUM_BLOCKS_B 2
// int* fileToArray(char file1[], int* n){
// FILE* fptr = fopen(file1, "r");
// char* str = (char*) malloc(sizeof(char)*2048);
// int token;
// fscanf(fptr, "%d,", n);
// int* array;
// //int* array = malloc(sizeof(int)*(*n));
// cudaMallocManaged(&array, sizeof(int)*(*n));
// for(int i = 0; i < *n; i++){
// fscanf(fptr, "%d,", &token);
// array[i] = token;
// }
// fclose(fptr);
// return array;
// }
int* fileToArray(char file1[], int* n){
FILE* fptr = fopen(file1, "r");
char* str = (char*) malloc(sizeof(char)*2048);
int token;
int count = 0;
while (fscanf(fptr, "%d, ", &token) != EOF) {
//printf("%dth token: %d\n", count, token);
count++;
}
*n = count;
//printf("total number of elements: %d\n", *n);
int* array;
hipMallocManaged(&array, sizeof(int)*(*n));
rewind(fptr);
for(int i = 0; i < *n; i++){
fscanf(fptr, "%d, ", &token);
array[i] = token;
}
fclose(fptr);
return array;
}
__global__
void sharedBucket(int* array, int* result, int n) {
__shared__ int local_array[10];
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((local_array+numHundreds), 1);
}
__syncthreads();
if ((threadIdx.x | threadIdx.y | threadIdx.z) == 0) {
for (int i = 0; i < 10; i++) {
atomicAdd((result+i), local_array[i]);
// result[i] = local_array[i];
}
}
__syncthreads();
}
void computeSharedBucket(int* array, int n) {
int* result;
hipMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
sharedBucket<<<NUM_BLOCKS_A, NUM_THREADS_A>>>(array, result, n);
hipDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_B, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_B);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
__global__
void bucket(int* array, int* result, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
int stride = blockDim.x * gridDim.x;
for (int i = index; i < n; i += stride) {
int numHundreds = array[i] / 100;
atomicAdd((result+numHundreds), 1);
}
}
__global__
void prescan(int* array, int n) {
int index = blockIdx.x * blockDim.x + threadIdx.x;
extern __shared__ int local_scan[];
for (int d = 1; d < 10; d *= 2) {
if (index + 1 > d && index < 10) {
array[index] += array[index-d];
}
__syncthreads();
}
}
void computeBucket(int* array, int n) {
int* result;
hipMallocManaged(&result, sizeof(int)*(10));
for (int i = 0; i < 10; i++) {
result[i] = 0;
}
bucket<<<NUM_BLOCKS_B, NUM_THREADS_B>>>(array, result, n);
hipDeviceSynchronize();
FILE *output = fopen(OUTPUT_FILE_NAME_A, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_A);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
prescan<<<1, 10>>>(result, 10);
output = fopen(OUTPUT_FILE_NAME_C, "w");
if(output == NULL) printf("failed to open file %s\n", OUTPUT_FILE_NAME_C);
fprintf(output, "%d", result[0]);
for(int i = 1; i < 10 ; i++) {
fprintf(output, ", %d", result[i]);
}
fclose(output);
}
int main(int argc, char* argv[]){
int n;
int* array = fileToArray("inp.txt", &n);
/*for(int i = 0; i < 10; i++){
printf("%d\n", array[i]);
}*/
computeBucket(array, n);
computeSharedBucket(array, n);
//int min = computeMin(array, n);
//printf("min: %d\n", min);
hipFree(array);
} | .text
.file "q2.hip"
.globl _Z11fileToArrayPcPi # -- Begin function _Z11fileToArrayPcPi
.p2align 4, 0x90
.type _Z11fileToArrayPcPi,@function
_Z11fileToArrayPcPi: # @_Z11fileToArrayPcPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $.L.str, %esi
callq fopen
movq %rax, %r14
movq $-4, %r15
movl $-1, %ebp
leaq 4(%rsp), %r12
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
incl %ebp
cmpl $-1, %eax
jne .LBB0_1
# %bb.2:
movl %ebp, (%rbx)
leaq 8(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
movq %r14, %rdi
callq rewind
cmpl $0, (%rbx)
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
leaq 4(%rsp), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %eax
movq 8(%rsp), %rcx
movl %eax, (%rcx,%r12,4)
incq %r12
movslq (%rbx), %rax
cmpq %rax, %r12
jl .LBB0_4
.LBB0_5: # %._crit_edge
movq %r14, %rdi
callq fclose
movq 8(%rsp), %rax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11fileToArrayPcPi, .Lfunc_end0-_Z11fileToArrayPcPi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__sharedBucketPiS_i # -- Begin function _Z27__device_stub__sharedBucketPiS_i
.p2align 4, 0x90
.type _Z27__device_stub__sharedBucketPiS_i,@function
_Z27__device_stub__sharedBucketPiS_i: # @_Z27__device_stub__sharedBucketPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sharedBucketPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z27__device_stub__sharedBucketPiS_i, .Lfunc_end1-_Z27__device_stub__sharedBucketPiS_i
.cfi_endproc
# -- End function
.globl _Z19computeSharedBucketPii # -- Begin function _Z19computeSharedBucketPii
.p2align 4, 0x90
.type _Z19computeSharedBucketPii,@function
_Z19computeSharedBucketPii: # @_Z19computeSharedBucketPii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
movq %rdi, %r14
movq %rsp, %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movq $0, 32(%rax)
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq (%rsp), %rax
movq %r14, 72(%rsp)
movq %rax, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sharedBucketPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
testq %rax, %rax
jne .LBB2_4
# %bb.3:
movl $.L.str.4, %edi
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
.LBB2_4:
movq (%rsp), %rax
movl (%rax), %edx
movl $.L.str.5, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
movl $1, %r14d
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r14,4), %edx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r14
cmpq $10, %r14
jne .LBB2_5
# %bb.6:
movq %rbx, %rdi
callq fclose
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19computeSharedBucketPii, .Lfunc_end2-_Z19computeSharedBucketPii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__bucketPiS_i # -- Begin function _Z21__device_stub__bucketPiS_i
.p2align 4, 0x90
.type _Z21__device_stub__bucketPiS_i,@function
_Z21__device_stub__bucketPiS_i: # @_Z21__device_stub__bucketPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6bucketPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z21__device_stub__bucketPiS_i, .Lfunc_end3-_Z21__device_stub__bucketPiS_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__prescanPii # -- Begin function _Z22__device_stub__prescanPii
.p2align 4, 0x90
.type _Z22__device_stub__prescanPii,@function
_Z22__device_stub__prescanPii: # @_Z22__device_stub__prescanPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7prescanPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z22__device_stub__prescanPii, .Lfunc_end4-_Z22__device_stub__prescanPii
.cfi_endproc
# -- End function
.globl _Z13computeBucketPii # -- Begin function _Z13computeBucketPii
.p2align 4, 0x90
.type _Z13computeBucketPii,@function
_Z13computeBucketPii: # @_Z13computeBucketPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rsp, %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movq $0, 32(%rax)
leaq 1(%rbx), %rdi
leaq 31(%rbx), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq (%rsp), %rax
movq %r14, 64(%rsp)
movq %rax, 24(%rsp)
movl %ebp, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 76(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6bucketPiS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
callq hipDeviceSynchronize
movl $.L.str.7, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
testq %rax, %rax
jne .LBB5_4
# %bb.3:
movl $.L.str.4, %edi
movl $.L.str.7, %esi
xorl %eax, %eax
callq printf
.LBB5_4:
movq (%rsp), %rax
movl (%rax), %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
movl $1, %r15d
.p2align 4, 0x90
.LBB5_5: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r15,4), %edx
movl $.L.str.6, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
incq %r15
cmpq $10, %r15
jne .LBB5_5
# %bb.6:
movq %r14, %rdi
callq fclose
leaq 9(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7:
movq (%rsp), %rax
movq %rax, 64(%rsp)
movl $10, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7prescanPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_8:
movl $.L.str.8, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
testq %rax, %rax
jne .LBB5_10
# %bb.9:
movl $.L.str.4, %edi
movl $.L.str.8, %esi
xorl %eax, %eax
callq printf
.LBB5_10:
movq (%rsp), %rax
movl (%rax), %edx
movl $.L.str.5, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
movl $1, %r14d
.p2align 4, 0x90
.LBB5_11: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r14,4), %edx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r14
cmpq $10, %r14
jne .LBB5_11
# %bb.12:
movq %rbx, %rdi
callq fclose
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z13computeBucketPii, .Lfunc_end5-_Z13computeBucketPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $.L.str.9, %edi
callq _Z11fileToArrayPcPi
movq %rax, %rbx
movl 4(%rsp), %ebp
movq %rax, %rdi
movl %ebp, %esi
callq _Z13computeBucketPii
movq %rbx, %rdi
movl %ebp, %esi
callq _Z19computeSharedBucketPii
movq %rbx, %rdi
callq hipFree
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sharedBucketPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6bucketPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7prescanPii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d, "
.size .L.str.1, 5
.type _Z12sharedBucketPiS_i,@object # @_Z12sharedBucketPiS_i
.section .rodata,"a",@progbits
.globl _Z12sharedBucketPiS_i
.p2align 3, 0x0
_Z12sharedBucketPiS_i:
.quad _Z27__device_stub__sharedBucketPiS_i
.size _Z12sharedBucketPiS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "q2b.txt"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "failed to open file %s\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz ", %d"
.size .L.str.6, 5
.type _Z6bucketPiS_i,@object # @_Z6bucketPiS_i
.section .rodata,"a",@progbits
.globl _Z6bucketPiS_i
.p2align 3, 0x0
_Z6bucketPiS_i:
.quad _Z21__device_stub__bucketPiS_i
.size _Z6bucketPiS_i, 8
.type _Z7prescanPii,@object # @_Z7prescanPii
.globl _Z7prescanPii
.p2align 3, 0x0
_Z7prescanPii:
.quad _Z22__device_stub__prescanPii
.size _Z7prescanPii, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "q2a.txt"
.size .L.str.7, 8
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "q2c.txt"
.size .L.str.8, 8
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "inp.txt"
.size .L.str.9, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12sharedBucketPiS_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6bucketPiS_i"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7prescanPii"
.size .L__unnamed_3, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sharedBucketPiS_i
.addrsig_sym _Z21__device_stub__bucketPiS_i
.addrsig_sym _Z22__device_stub__prescanPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sharedBucketPiS_i
.addrsig_sym _Z6bucketPiS_i
.addrsig_sym _Z7prescanPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7prescanPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x160 ; /* 0x0000012000007945 */
/* 0x000fe40003800000 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0060*/ IADD3 R0, R2.reuse, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x040fe40007ffe0ff */
/*0070*/ IADD3 R3, R2, -0x2, RZ ; /* 0xfffffffe02037810 */
/* 0x000fe40007ffe0ff */
/*0080*/ ISETP.GT.U32.AND P0, PT, R0, 0x8, PT ; /* 0x000000080000780c */
/* 0x000fe40003f04070 */
/*0090*/ ISETP.GT.U32.AND P1, PT, R3, 0x7, PT ; /* 0x000000070300780c */
/* 0x000fe20003f24070 */
/*00a0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*00b0*/ IADD3 R4, R2.reuse, -0x4, RZ ; /* 0xfffffffc02047810 */
/* 0x040fe40007ffe0ff */
/*00c0*/ LOP3.LUT R5, R2.reuse, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe02057812 */
/* 0x040fe200078ec0ff */
/*00d0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0203 */
/*00e0*/ ISETP.GT.U32.AND P2, PT, R4, 0x5, PT ; /* 0x000000050400780c */
/* 0x000fc40003f44070 */
/*00f0*/ ISETP.NE.AND P3, PT, R5, 0x8, PT ; /* 0x000000080500780c */
/* 0x000fc60003f65270 */
/*0100*/ @P0 BRA 0x150 ; /* 0x0000004000000947 */
/* 0x000fea0003800000 */
/*0110*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0120*/ LDG.E R5, [R2.64+-0x4] ; /* 0xfffffc0402057981 */
/* 0x000ea4000c1e1900 */
/*0130*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*0140*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0150*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0160*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0170*/ BSSY B0, 0x1e0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0180*/ @P1 BRA 0x1d0 ; /* 0x0000004000001947 */
/* 0x000fea0003800000 */
/*0190*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R5, [R2.64+-0x8] ; /* 0xfffff80402057981 */
/* 0x001ea4000c1e1900 */
/*01b0*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*01c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*01d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01f0*/ BSSY B0, 0x260 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0200*/ @P2 BRA 0x250 ; /* 0x0000004000002947 */
/* 0x000fea0003800000 */
/*0210*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0220*/ LDG.E R5, [R2.64+-0x10] ; /* 0xfffff00402057981 */
/* 0x001ea4000c1e1900 */
/*0230*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*0240*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0250*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0270*/ BSSY B0, 0x2e0 ; /* 0x0000006000007945 */
/* 0x000fe20003800000 */
/*0280*/ @P3 BRA 0x2d0 ; /* 0x0000004000003947 */
/* 0x000fea0003800000 */
/*0290*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R5, [R2.64+-0x20] ; /* 0xffffe00402057981 */
/* 0x001ea4000c1e1900 */
/*02b0*/ IMAD.IADD R5, R0, 0x1, R5 ; /* 0x0000000100057824 */
/* 0x004fca00078e0205 */
/*02c0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6bucketPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fd400000001ff */
/*0080*/ IMAD.WIDE R2, R0, R6, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0206 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ MOV R9, c[0x0][0x0] ; /* 0x0000000000097a02 */
/* 0x000fe20000000f00 */
/*00b0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe20003800000 */
/*00c0*/ MOV R7, 0x1 ; /* 0x0000000100077802 */
/* 0x001fc60000000f00 */
/*00d0*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f06270 */
/*00f0*/ IMAD.HI R4, R2, 0x51eb851f, RZ ; /* 0x51eb851f02047827 */
/* 0x004fca00078e02ff */
/*0100*/ SHF.R.U32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x000fc80000011604 */
/*0110*/ LEA.HI.SX32 R5, R4, R5, 0x1b ; /* 0x0000000504057211 */
/* 0x000fca00078fdaff */
/*0120*/ IMAD.WIDE R4, R5, R6, c[0x0][0x168] ; /* 0x00005a0005047625 */
/* 0x000fca00078e0206 */
/*0130*/ RED.E.ADD.STRONG.GPU [R4.64], R7 ; /* 0x000000070400798e */
/* 0x0001e2000c10e184 */
/*0140*/ @!P0 BRA 0x70 ; /* 0xffffff2000008947 */
/* 0x000fea000383ffff */
/*0150*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0160*/ BRA 0x160; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z12sharedBucketPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002200 */
/*0050*/ S2R R4, SR_TID.Z ; /* 0x0000000000047919 */
/* 0x000e620000002300 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe40003f26270 */
/*0080*/ LOP3.LUT P0, RZ, R4, R3, R2, 0xfe, !PT ; /* 0x0000000304ff7212 */
/* 0x002fd6000780fe02 */
/*0090*/ @P1 BRA 0x160 ; /* 0x000000c000001947 */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*00b0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0203 */
/*00c0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00d0*/ MOV R7, c[0x0][0x0] ; /* 0x0000000000077a02 */
/* 0x000fe20000000f00 */
/*00e0*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*00f0*/ IMAD R0, R7, c[0x0][0xc], R0 ; /* 0x0000030007007a24 */
/* 0x000fca00078e0200 */
/*0100*/ ISETP.GE.AND P1, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fe20003f26270 */
/*0110*/ IMAD.HI R4, R2, 0x51eb851f, RZ ; /* 0x51eb851f02047827 */
/* 0x004fca00078e02ff */
/*0120*/ SHF.R.U32.HI R5, RZ, 0x1f, R4 ; /* 0x0000001fff057819 */
/* 0x001fc80000011604 */
/*0130*/ LEA.HI.SX32 R5, R4, R5, 0x1b ; /* 0x0000000504057211 */
/* 0x000fca00078fdaff */
/*0140*/ ATOMS.POPC.INC.32 RZ, [R5.X4+URZ] ; /* 0x0000000005ff7f8c */
/* 0x0001e2000d00403f */
/*0150*/ @!P1 BRA 0xa0 ; /* 0xffffff4000009947 */
/* 0x000fea000383ffff */
/*0160*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0170*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0180*/ BSSY B0, 0x390 ; /* 0x0000020000007945 */
/* 0x000fe20003800000 */
/*0190*/ @P0 BRA 0x380 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*01a0*/ LDS.128 R8, [RZ] ; /* 0x00000000ff087984 */
/* 0x000e620000000c00 */
/*01b0*/ VOTEU.ANY UR4, UPT, PT ; /* 0x0000000000047886 */
/* 0x000fe200038e0100 */
/*01c0*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*01d0*/ UFLO.U32 UR5, UR4 ; /* 0x00000004000572bd */
/* 0x000fe200080e0000 */
/*01e0*/ LDS.128 R4, [0x10] ; /* 0x00001000ff047984 */
/* 0x001e220000000c00 */
/*01f0*/ UPOPC UR4, UR4 ; /* 0x00000004000472bf */
/* 0x000fe20008000000 */
/*0200*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fc40000000f00 */
/*0210*/ S2R R0, SR_LANEID ; /* 0x0000000000007919 */
/* 0x000ea80000000000 */
/*0220*/ LDS.64 R12, [0x20] ; /* 0x00002000ff0c7984 */
/* 0x000ee20000000a00 */
/*0230*/ ISETP.EQ.U32.AND P0, PT, R0, UR5, PT ; /* 0x0000000500007c0c */
/* 0x004fe2000bf02070 */
/*0240*/ IMAD R15, R8, UR4, RZ ; /* 0x00000004080f7c24 */
/* 0x002fe4000f8e02ff */
/*0250*/ IMAD R9, R9, UR4, RZ ; /* 0x0000000409097c24 */
/* 0x000fe4000f8e02ff */
/*0260*/ IMAD R17, R10, UR4, RZ ; /* 0x000000040a117c24 */
/* 0x000fd0000f8e02ff */
/*0270*/ @P0 RED.E.ADD.STRONG.GPU [R2.64], R15 ; /* 0x0000000f0200098e */
/* 0x0003e2000c10e186 */
/*0280*/ IMAD R11, R11, UR4, RZ ; /* 0x000000040b0b7c24 */
/* 0x000fe4000f8e02ff */
/*0290*/ IMAD R19, R4, UR4, RZ ; /* 0x0000000404137c24 */
/* 0x001fe2000f8e02ff */
/*02a0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x4], R9 ; /* 0x000004090200098e */
/* 0x0003e2000c10e186 */
/*02b0*/ IMAD R5, R5, UR4, RZ ; /* 0x0000000405057c24 */
/* 0x000fe4000f8e02ff */
/*02c0*/ IMAD R21, R6, UR4, RZ ; /* 0x0000000406157c24 */
/* 0x000fe2000f8e02ff */
/*02d0*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x8], R17 ; /* 0x000008110200098e */
/* 0x0003e2000c10e186 */
/*02e0*/ IMAD R7, R7, UR4, RZ ; /* 0x0000000407077c24 */
/* 0x000fe4000f8e02ff */
/*02f0*/ IMAD R23, R12, UR4, RZ ; /* 0x000000040c177c24 */
/* 0x008fe2000f8e02ff */
/*0300*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0xc], R11 ; /* 0x00000c0b0200098e */
/* 0x0003e2000c10e186 */
/*0310*/ IMAD R13, R13, UR4, RZ ; /* 0x000000040d0d7c24 */
/* 0x000fc6000f8e02ff */
/*0320*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x10], R19 ; /* 0x000010130200098e */
/* 0x0003e8000c10e186 */
/*0330*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x14], R5 ; /* 0x000014050200098e */
/* 0x0003e8000c10e186 */
/*0340*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x18], R21 ; /* 0x000018150200098e */
/* 0x0003e8000c10e186 */
/*0350*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x1c], R7 ; /* 0x00001c070200098e */
/* 0x0003e8000c10e186 */
/*0360*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x20], R23 ; /* 0x000020170200098e */
/* 0x0003e8000c10e186 */
/*0370*/ @P0 RED.E.ADD.STRONG.GPU [R2.64+0x24], R13 ; /* 0x0000240d0200098e */
/* 0x0003e4000c10e186 */
/*0380*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0390*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*03a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*03b0*/ BRA 0x3b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0400*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0410*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0420*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0430*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0440*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0450*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0460*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0470*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12sharedBucketPiS_i
.globl _Z12sharedBucketPiS_i
.p2align 8
.type _Z12sharedBucketPiS_i,@function
_Z12sharedBucketPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
v_and_b32_e32 v1, 0x3ff, v0
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s9, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
v_cmpx_gt_i32_e64 s8, v2
s_cbranch_execz .LBB0_3
s_load_b32 s5, s[2:3], 0x0
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_mov_b32_e32 v5, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_ashr_i32 s5, s4, 31
s_mov_b32 s3, 0
s_lshl_b64 s[6:7], s[4:5], 2
.p2align 6
.LBB0_2:
global_load_b32 v6, v[3:4], off
v_add_nc_u32_e32 v2, s4, v2
v_add_co_u32 v3, s2, v3, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v4, s2, s7, v4, s2
v_cmp_le_i32_e32 vcc_lo, s8, v2
s_or_b32 s3, vcc_lo, s3
s_waitcnt vmcnt(0)
v_mul_hi_i32 v6, v6, 0x51eb851f
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v7, 31, v6
v_ashrrev_i32_e32 v6, 5, v6
v_add_lshl_u32 v6, v6, v7, 2
ds_add_u32 v6, v5
s_and_not1_b32 exec_lo, exec_lo, s3
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s9
v_bfe_u32 v2, v0, 20, 10
v_bfe_u32 v0, v0, 10, 10
s_mov_b32 s2, 0
s_mov_b32 s3, exec_lo
s_waitcnt lgkmcnt(0)
s_barrier
v_or3_b32 v0, v0, v2, v1
buffer_gl0_inv
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_8
s_load_b64 s[0:1], s[0:1], 0x8
v_mov_b32_e32 v0, 0
s_branch .LBB0_6
.p2align 6
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s4
s_add_i32 s2, s2, 4
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lg_u32 s2, 40
s_cbranch_scc0 .LBB0_8
.LBB0_6:
s_mov_b32 s5, exec_lo
s_mov_b32 s4, exec_lo
v_mbcnt_lo_u32_b32 v1, s5, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v1
s_cbranch_execz .LBB0_5
v_mov_b32_e32 v1, s2
s_bcnt1_i32_b32 s5, s5
ds_load_b32 v1, v1
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s5
global_atomic_add_u32 v0, v1, s[0:1]
s_branch .LBB0_5
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12sharedBucketPiS_i
.amdhsa_group_segment_fixed_size 40
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 2
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12sharedBucketPiS_i, .Lfunc_end0-_Z12sharedBucketPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6bucketPiS_i
.globl _Z6bucketPiS_i
.p2align 8
.type _Z6bucketPiS_i,@function
_Z6bucketPiS_i:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s8, s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s5, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
v_cmpx_gt_i32_e64 s8, v1
s_cbranch_execz .LBB1_3
s_load_b32 s5, s[2:3], 0x0
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v0, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_mul_i32 s4, s5, s4
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
s_ashr_i32 s5, s4, 31
s_mov_b32 s1, 0
s_lshl_b64 s[6:7], s[4:5], 2
.p2align 6
.LBB1_2:
global_load_b32 v4, v[2:3], off
v_add_nc_u32_e32 v1, s4, v1
v_add_co_u32 v2, s0, v2, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s7, v3, s0
s_waitcnt vmcnt(0)
v_mul_hi_i32 v4, v4, 0x51eb851f
v_lshrrev_b32_e32 v5, 31, v4
v_ashrrev_i32_e32 v4, 5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v4, v4, v5
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
v_add_co_u32 v4, vcc_lo, s2, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
v_cmp_le_i32_e32 vcc_lo, s8, v1
global_atomic_add_u32 v[4:5], v0, off
s_or_b32 s1, vcc_lo, s1
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6bucketPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z6bucketPiS_i, .Lfunc_end1-_Z6bucketPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7prescanPii
.globl _Z7prescanPii
.p2align 8
.type _Z7prescanPii,@function
_Z7prescanPii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s1, 1
s_waitcnt lgkmcnt(0)
s_and_b32 s0, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s0, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
v_cmp_gt_i32_e32 vcc_lo, 10, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_2
.p2align 6
.LBB2_1:
s_or_b32 exec_lo, exec_lo, s4
s_lshl_b32 s0, s1, 1
s_cmp_gt_u32 s1, 4
s_mov_b32 s1, s0
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_4
.LBB2_2:
v_cmp_le_i32_e64 s0, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s0, vcc_lo, s0
s_and_saveexec_b32 s4, s0
s_cbranch_execz .LBB2_1
v_subrev_nc_u32_e32 v4, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_co_u32 v4, s0, s2, v4
v_add_co_ci_u32_e64 v5, s0, s3, v5, s0
s_clause 0x1
global_load_b32 v0, v[4:5], off
global_load_b32 v4, v[2:3], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v0, v4, v0
global_store_b32 v[2:3], v0, off
s_branch .LBB2_1
.LBB2_4:
s_set_inst_prefetch_distance 0x2
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7prescanPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z7prescanPii, .Lfunc_end2-_Z7prescanPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 40
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12sharedBucketPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12sharedBucketPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6bucketPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6bucketPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7prescanPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7prescanPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000840e7_00000000-6_q2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2063:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2063:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r"
.LC1:
.string "%d, "
.text
.globl _Z11fileToArrayPcPi
.type _Z11fileToArrayPcPi, @function
_Z11fileToArrayPcPi:
.LFB2057:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $40, %rsp
.cfi_def_cfa_offset 80
movq %rsi, %r12
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, %rbp
movl $0, %ebx
leaq .LC1(%rip), %r13
jmp .L4
.L5:
addl $1, %ebx
.L4:
leaq 12(%rsp), %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
cmpl $-1, %eax
jne .L5
movl %ebx, (%r12)
movslq %ebx, %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movq %rbp, %rdi
call rewind@PLT
cmpl $0, (%r12)
jle .L6
movl $0, %ebx
leaq .LC1(%rip), %r13
.L7:
leaq 12(%rsp), %rdx
movq %r13, %rsi
movq %rbp, %rdi
movl $0, %eax
call __isoc23_fscanf@PLT
movl 12(%rsp), %edx
movq 16(%rsp), %rax
movl %edx, (%rax,%rbx,4)
addq $1, %rbx
cmpl %ebx, (%r12)
jg .L7
.L6:
movq %rbp, %rdi
call fclose@PLT
movq 16(%rsp), %rax
movq 24(%rsp), %rdx
subq %fs:40, %rdx
jne .L11
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z11fileToArrayPcPi, .-_Z11fileToArrayPcPi
.globl _Z35__device_stub__Z12sharedBucketPiS_iPiS_i
.type _Z35__device_stub__Z12sharedBucketPiS_iPiS_i, @function
_Z35__device_stub__Z12sharedBucketPiS_iPiS_i:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12sharedBucketPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z35__device_stub__Z12sharedBucketPiS_iPiS_i, .-_Z35__device_stub__Z12sharedBucketPiS_iPiS_i
.globl _Z12sharedBucketPiS_i
.type _Z12sharedBucketPiS_i, @function
_Z12sharedBucketPiS_i:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12sharedBucketPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z12sharedBucketPiS_i, .-_Z12sharedBucketPiS_i
.section .rodata.str1.1
.LC2:
.string "w"
.LC3:
.string "q2b.txt"
.LC4:
.string "failed to open file %s\n"
.LC5:
.string "%d"
.LC6:
.string ", %d"
.text
.globl _Z19computeSharedBucketPii
.type _Z19computeSharedBucketPii, @function
_Z19computeSharedBucketPii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L21:
movq 8(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L21
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L29
.L22:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L30
.L23:
movq 8(%rsp), %rax
movl (%rax), %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $4, %ebx
leaq .LC6(%rip), %r12
.L24:
movq 8(%rsp), %rax
movl (%rax,%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L24
movq %rbp, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L31
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
movl %ebp, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call _Z35__device_stub__Z12sharedBucketPiS_iPiS_i
jmp .L22
.L30:
leaq .LC3(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L31:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z19computeSharedBucketPii, .-_Z19computeSharedBucketPii
.globl _Z28__device_stub__Z6bucketPiS_iPiS_i
.type _Z28__device_stub__Z6bucketPiS_iPiS_i, @function
_Z28__device_stub__Z6bucketPiS_iPiS_i:
.LFB2087:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L36
.L32:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L37
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6bucketPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L32
.L37:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z28__device_stub__Z6bucketPiS_iPiS_i, .-_Z28__device_stub__Z6bucketPiS_iPiS_i
.globl _Z6bucketPiS_i
.type _Z6bucketPiS_i, @function
_Z6bucketPiS_i:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z6bucketPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z6bucketPiS_i, .-_Z6bucketPiS_i
.globl _Z27__device_stub__Z7prescanPiiPii
.type _Z27__device_stub__Z7prescanPiiPii, @function
_Z27__device_stub__Z7prescanPiiPii:
.LFB2089:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L44
.L40:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L45
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L44:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7prescanPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L40
.L45:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2089:
.size _Z27__device_stub__Z7prescanPiiPii, .-_Z27__device_stub__Z7prescanPiiPii
.globl _Z7prescanPii
.type _Z7prescanPii, @function
_Z7prescanPii:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7prescanPiiPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _Z7prescanPii, .-_Z7prescanPii
.section .rodata.str1.1
.LC7:
.string "q2a.txt"
.LC8:
.string "q2c.txt"
.text
.globl _Z13computeBucketPii
.type _Z13computeBucketPii, @function
_Z13computeBucketPii:
.LFB2059:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $48, %rsp
.cfi_def_cfa_offset 80
movq %rdi, %rbx
movl %esi, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $1, %edx
movl $40, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L49:
movq 8(%rsp), %rdx
movl $0, (%rdx,%rax)
addq $4, %rax
cmpq $40, %rax
jne .L49
movl $32, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $2, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L61
.L50:
call cudaDeviceSynchronize@PLT
leaq .LC2(%rip), %rsi
leaq .LC7(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L62
.L51:
movq 8(%rsp), %rax
movl (%rax), %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $4, %ebx
leaq .LC6(%rip), %r12
.L52:
movq 8(%rsp), %rax
movl (%rax,%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L52
movq %rbp, %rdi
call fclose@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L63
.L53:
leaq .LC2(%rip), %rsi
leaq .LC8(%rip), %rdi
call fopen@PLT
movq %rax, %rbp
testq %rax, %rax
je .L64
.L54:
movq 8(%rsp), %rax
movl (%rax), %ecx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $4, %ebx
leaq .LC6(%rip), %r12
.L55:
movq 8(%rsp), %rax
movl (%rax,%rbx), %ecx
movq %r12, %rdx
movl $2, %esi
movq %rbp, %rdi
movl $0, %eax
call __fprintf_chk@PLT
addq $4, %rbx
cmpq $40, %rbx
jne .L55
movq %rbp, %rdi
call fclose@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L65
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L61:
.cfi_restore_state
movl %ebp, %edx
movq 8(%rsp), %rsi
movq %rbx, %rdi
call _Z28__device_stub__Z6bucketPiS_iPiS_i
jmp .L50
.L62:
leaq .LC7(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L51
.L63:
movl $10, %esi
movq 8(%rsp), %rdi
call _Z27__device_stub__Z7prescanPiiPii
jmp .L53
.L64:
leaq .LC8(%rip), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L54
.L65:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z13computeBucketPii, .-_Z13computeBucketPii
.section .rodata.str1.1
.LC9:
.string "inp.txt"
.text
.globl main
.type main, @function
main:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $24, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rsi
leaq .LC9(%rip), %rdi
call _Z11fileToArrayPcPi
movq %rax, %rbx
movl 4(%rsp), %ebp
movl %ebp, %esi
movq %rax, %rdi
call _Z13computeBucketPii
movl %ebp, %esi
movq %rbx, %rdi
call _Z19computeSharedBucketPii
movq %rbx, %rdi
call cudaFree@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L69
movl $0, %eax
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L69:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size main, .-main
.section .rodata.str1.1
.LC10:
.string "_Z7prescanPii"
.LC11:
.string "_Z6bucketPiS_i"
.LC12:
.string "_Z12sharedBucketPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2092:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _Z7prescanPii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6bucketPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12sharedBucketPiS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2092:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "q2.hip"
.globl _Z11fileToArrayPcPi # -- Begin function _Z11fileToArrayPcPi
.p2align 4, 0x90
.type _Z11fileToArrayPcPi,@function
_Z11fileToArrayPcPi: # @_Z11fileToArrayPcPi
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $16, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl $.L.str, %esi
callq fopen
movq %rax, %r14
movq $-4, %r15
movl $-1, %ebp
leaq 4(%rsp), %r12
.p2align 4, 0x90
.LBB0_1: # =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r12, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
addq $4, %r15
incl %ebp
cmpl $-1, %eax
jne .LBB0_1
# %bb.2:
movl %ebp, (%rbx)
leaq 8(%rsp), %rdi
movq %r15, %rsi
movl $1, %edx
callq hipMallocManaged
movq %r14, %rdi
callq rewind
cmpl $0, (%rbx)
jle .LBB0_5
# %bb.3: # %.lr.ph.preheader
leaq 4(%rsp), %r15
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $.L.str.1, %esi
movq %r14, %rdi
movq %r15, %rdx
xorl %eax, %eax
callq __isoc23_fscanf
movl 4(%rsp), %eax
movq 8(%rsp), %rcx
movl %eax, (%rcx,%r12,4)
incq %r12
movslq (%rbx), %rax
cmpq %rax, %r12
jl .LBB0_4
.LBB0_5: # %._crit_edge
movq %r14, %rdi
callq fclose
movq 8(%rsp), %rax
addq $16, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z11fileToArrayPcPi, .Lfunc_end0-_Z11fileToArrayPcPi
.cfi_endproc
# -- End function
.globl _Z27__device_stub__sharedBucketPiS_i # -- Begin function _Z27__device_stub__sharedBucketPiS_i
.p2align 4, 0x90
.type _Z27__device_stub__sharedBucketPiS_i,@function
_Z27__device_stub__sharedBucketPiS_i: # @_Z27__device_stub__sharedBucketPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sharedBucketPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z27__device_stub__sharedBucketPiS_i, .Lfunc_end1-_Z27__device_stub__sharedBucketPiS_i
.cfi_endproc
# -- End function
.globl _Z19computeSharedBucketPii # -- Begin function _Z19computeSharedBucketPii
.p2align 4, 0x90
.type _Z19computeSharedBucketPii,@function
_Z19computeSharedBucketPii: # @_Z19computeSharedBucketPii
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl %esi, %ebx
movq %rdi, %r14
movq %rsp, %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movq $0, 32(%rax)
movabsq $4294967298, %rdi # imm = 0x100000002
leaq 30(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq (%rsp), %rax
movq %r14, 72(%rsp)
movq %rax, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12sharedBucketPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
callq hipDeviceSynchronize
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
testq %rax, %rax
jne .LBB2_4
# %bb.3:
movl $.L.str.4, %edi
movl $.L.str.2, %esi
xorl %eax, %eax
callq printf
.LBB2_4:
movq (%rsp), %rax
movl (%rax), %edx
movl $.L.str.5, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
movl $1, %r14d
.p2align 4, 0x90
.LBB2_5: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r14,4), %edx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r14
cmpq $10, %r14
jne .LBB2_5
# %bb.6:
movq %rbx, %rdi
callq fclose
addq $104, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z19computeSharedBucketPii, .Lfunc_end2-_Z19computeSharedBucketPii
.cfi_endproc
# -- End function
.globl _Z21__device_stub__bucketPiS_i # -- Begin function _Z21__device_stub__bucketPiS_i
.p2align 4, 0x90
.type _Z21__device_stub__bucketPiS_i,@function
_Z21__device_stub__bucketPiS_i: # @_Z21__device_stub__bucketPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6bucketPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z21__device_stub__bucketPiS_i, .Lfunc_end3-_Z21__device_stub__bucketPiS_i
.cfi_endproc
# -- End function
.globl _Z22__device_stub__prescanPii # -- Begin function _Z22__device_stub__prescanPii
.p2align 4, 0x90
.type _Z22__device_stub__prescanPii,@function
_Z22__device_stub__prescanPii: # @_Z22__device_stub__prescanPii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7prescanPii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end4:
.size _Z22__device_stub__prescanPii, .Lfunc_end4-_Z22__device_stub__prescanPii
.cfi_endproc
# -- End function
.globl _Z13computeBucketPii # -- Begin function _Z13computeBucketPii
.p2align 4, 0x90
.type _Z13computeBucketPii,@function
_Z13computeBucketPii: # @_Z13computeBucketPii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %esi, %ebp
movq %rdi, %r14
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rsp, %rdi
movl $40, %esi
movl $1, %edx
callq hipMallocManaged
movq (%rsp), %rax
xorps %xmm0, %xmm0
movups %xmm0, (%rax)
movups %xmm0, 16(%rax)
movq $0, 32(%rax)
leaq 1(%rbx), %rdi
leaq 31(%rbx), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movq (%rsp), %rax
movq %r14, 64(%rsp)
movq %rax, 24(%rsp)
movl %ebp, 76(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 76(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6bucketPiS_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
callq hipDeviceSynchronize
movl $.L.str.7, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %r14
testq %rax, %rax
jne .LBB5_4
# %bb.3:
movl $.L.str.4, %edi
movl $.L.str.7, %esi
xorl %eax, %eax
callq printf
.LBB5_4:
movq (%rsp), %rax
movl (%rax), %edx
movl $.L.str.5, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
movl $1, %r15d
.p2align 4, 0x90
.LBB5_5: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r15,4), %edx
movl $.L.str.6, %esi
movq %r14, %rdi
xorl %eax, %eax
callq fprintf
incq %r15
cmpq $10, %r15
jne .LBB5_5
# %bb.6:
movq %r14, %rdi
callq fclose
leaq 9(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_8
# %bb.7:
movq (%rsp), %rax
movq %rax, 64(%rsp)
movl $10, 8(%rsp)
leaq 64(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7prescanPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_8:
movl $.L.str.8, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, %rbx
testq %rax, %rax
jne .LBB5_10
# %bb.9:
movl $.L.str.4, %edi
movl $.L.str.8, %esi
xorl %eax, %eax
callq printf
.LBB5_10:
movq (%rsp), %rax
movl (%rax), %edx
movl $.L.str.5, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
movl $1, %r14d
.p2align 4, 0x90
.LBB5_11: # =>This Inner Loop Header: Depth=1
movq (%rsp), %rax
movl (%rax,%r14,4), %edx
movl $.L.str.6, %esi
movq %rbx, %rdi
xorl %eax, %eax
callq fprintf
incq %r14
cmpq $10, %r14
jne .LBB5_11
# %bb.12:
movq %rbx, %rdi
callq fclose
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z13computeBucketPii, .Lfunc_end5-_Z13computeBucketPii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
pushq %rax
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -24
.cfi_offset %rbp, -16
leaq 4(%rsp), %rsi
movl $.L.str.9, %edi
callq _Z11fileToArrayPcPi
movq %rax, %rbx
movl 4(%rsp), %ebp
movq %rax, %rdi
movl %ebp, %esi
callq _Z13computeBucketPii
movq %rbx, %rdi
movl %ebp, %esi
callq _Z19computeSharedBucketPii
movq %rbx, %rdi
callq hipFree
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12sharedBucketPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6bucketPiS_i, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7prescanPii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "r"
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d, "
.size .L.str.1, 5
.type _Z12sharedBucketPiS_i,@object # @_Z12sharedBucketPiS_i
.section .rodata,"a",@progbits
.globl _Z12sharedBucketPiS_i
.p2align 3, 0x0
_Z12sharedBucketPiS_i:
.quad _Z27__device_stub__sharedBucketPiS_i
.size _Z12sharedBucketPiS_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "q2b.txt"
.size .L.str.2, 8
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "w"
.size .L.str.3, 2
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "failed to open file %s\n"
.size .L.str.4, 24
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "%d"
.size .L.str.5, 3
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz ", %d"
.size .L.str.6, 5
.type _Z6bucketPiS_i,@object # @_Z6bucketPiS_i
.section .rodata,"a",@progbits
.globl _Z6bucketPiS_i
.p2align 3, 0x0
_Z6bucketPiS_i:
.quad _Z21__device_stub__bucketPiS_i
.size _Z6bucketPiS_i, 8
.type _Z7prescanPii,@object # @_Z7prescanPii
.globl _Z7prescanPii
.p2align 3, 0x0
_Z7prescanPii:
.quad _Z22__device_stub__prescanPii
.size _Z7prescanPii, 8
.type .L.str.7,@object # @.str.7
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.7:
.asciz "q2a.txt"
.size .L.str.7, 8
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "q2c.txt"
.size .L.str.8, 8
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "inp.txt"
.size .L.str.9, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12sharedBucketPiS_i"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z6bucketPiS_i"
.size .L__unnamed_2, 15
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z7prescanPii"
.size .L__unnamed_3, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__sharedBucketPiS_i
.addrsig_sym _Z21__device_stub__bucketPiS_i
.addrsig_sym _Z22__device_stub__prescanPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12sharedBucketPiS_i
.addrsig_sym _Z6bucketPiS_i
.addrsig_sym _Z7prescanPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define NDISP 48
typedef unsigned char uchar;
using namespace std;
__global__ void path_aggregate(int width, int height, int D, int P1, int P2,
int dir, int* Espace, cudaTextureObject_t Cost,
short* texturePerp, short* textureParallel)
{
__shared__ short L_p0[NDISP+2];
__shared__ short L_c0[NDISP+2];
__shared__ short delta0;
short Tp = 0, T = 0, Tp2 = 0;
float Kt = 0;
int P1a, P2a; int Td;
int dy, dx;
int tid = threadIdx.x;
int d = tid+1;
//just one thread to prevent bank conflicts
if(tid == 0)
L_p0[0] = L_p0[NDISP+1] = L_c0[0] = L_c0[NDISP+1] = SHRT_MAX;
if(tid < D)
L_p0[d] = SHRT_MAX;
if(tid == 0)
delta0 = SHRT_MAX;
int x = 0;
int y = 0;
//set initial coordinates of a block
switch(dir)
{
case 0:
x = 0; y = blockIdx.x; dy = 0; dx = 1;
break;
case 1:
if(blockIdx.x < height)
{ y = height-1-(blockIdx.x); x = 0; dy=1; dx=1;}
else
{ y = 0; x = (blockIdx.x)-height;}
break;
case 2:
y = 0; x = blockIdx.x; dy = 1; dx = 0;
break;
case 3:
if(blockIdx.x < width)
{ x = blockIdx.x; y = 0; dy = 1; dx = -1;}
else
{ y = blockIdx.x-width; x = width-1; dy = 1; dx = -1;}
break;
case 4:
x = width-1; y = blockIdx.x; dy = 0; dx= -1;
break;
case 5:
if(blockIdx.x < height)
{ x = width-1; y = blockIdx.x; dy=-1; dx = -1;}
else
{ y = height-1; x = blockIdx.x-height; dy=-1; dx = -1;}
break;
case 6:
y = height-1; x = blockIdx.x; dy = -1; dx = 0;
break;
case 7:
if(blockIdx.x < height)
{ x = 0; y = blockIdx.x; dy = -1; dx = 1;}
else
{ x = blockIdx.x-height; y = height-1; dy = -1; dx = 1;}
break;
}
__syncthreads();
//main loop of a thread
while(x >= 0 && y >= 0 && x < width && y < height)
{
//read texture and adjust penalties
Kt = 1;//textureParallel[y*width+x]/500;
T = texturePerp[y*width+x];
Td = abs(T-Tp2);
short C;
short bestsad; short bestdisp;
P1a = P1;
P2a = P2;
Tp2 = Tp;
Tp = T;
if(tid < D)
{
C = tex2D<short>(Cost, (d-1)*width+x, y);
if(C < SHRT_MAX-5)
{
L_c0[d] = C + min((int)L_p0[d], min((int)L_p0[d-1]+P1a, min((int)L_p0[d+1]+P1a, (int)delta0))) - delta0;
Espace[y*width*D + x*D + d-1] += (int)L_c0[d]*Kt;
L_p0[d] = L_c0[d];
}
else
{
L_c0[d] = SHRT_MAX;
Espace[y*width*D + x*D + d-1] += SHRT_MAX;
L_p0[d] = L_c0[d];
}
__syncthreads();
for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
{
if((d-1) < n)
{
L_c0[d] = min((int)L_c0[d], (int)L_c0[d+n]);
}
if(n*2 != i)
{
L_c0[n+1] = L_c0[2*n+1];
n = n+1;
}
i = n;
__syncthreads();
}
delta0 = L_c0[1] + P2a;
}
__syncthreads();
x += dx; y += dy;
}
}
/* BM_cost
*
* Calculates block matching cost for D disparity levels
* between image1 and image2
*/
__global__ void BM_cost(cudaTextureObject_t image1, cudaTextureObject_t image2,
short* cost, int width, int height, int D)
{
extern __shared__ short I[];
int x = threadIdx.x;
int y = blockIdx.x;
I[x] = tex2D<uchar>(image2, x, y);
__syncthreads();
short i = tex2D<uchar>(image1, x, y);
int r = y*width*D + x;
for(int d=0; d<D; d++)
{
if(x >= d)
{
cost[r + d*width] = abs(i - I[x-d]);
}
else
cost[r + d*width] = SHRT_MAX;
}
}
__global__ void energy_minimalize(int *Energy, short* disparity, short* disparity2,
int D, int width, int height)
{
__shared__ int L[NDISP]; //storage for disparity values
__shared__ int cL[NDISP];
int d = threadIdx.x;
int x = blockIdx.x;
int y = blockIdx.y;
float d_refined;
//read energy for each disparity (one operation)
L[d] = Energy[y*width*D + x*D + d];
cL[d] = L[d];
__syncthreads();
//use reduction algorithm to minimalize energy
for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
{
if(d < n)
{
L[d] = min(L[d], L[d+n]);
}
if(n*2 != i)
{
L[n] = L[2*n];
n = n+1;
}
i = n;
__syncthreads();
}
if(cL[d] == L[0])
{
if(0 < d && d < D-1)
{
int denom2 = max((Energy[(y * width * D) + (x * D) + d - 1]
+ Energy[(y * width * D) + (x * D) + d + 1]
- 2 * Energy[(y * width * D) + (x * D) + d]), 1);
d_refined = 10 * ((float) d) + (float)((Energy[(y * width * D)
+ (x * D) + d - 1] - Energy[(y * width * D)
+ (x * D) + d + 1]) + denom2) / (denom2 * 2);
}
else
{
d_refined = 10*(float)d;
}
disparity[y*width+x] = d_refined;
if(x-1-d >= 0)
disparity2[y*width+x-1-d] = d_refined;
}
__syncthreads();
}
__global__ void validate(short* disparity, short* disparity2, int width, int height, int disp12maxdiff)
{
int x = threadIdx.x;
int y = blockIdx.x;
int d0 = disparity[y*width + x];
if(d0 != -1)
{
int x2 = x - d0;
if(0 <= x2 && abs(disparity2[y*width + x2]-d0) > 10*disp12maxdiff)
{
disparity[y*width+x] = -1;
}
}
} | .file "tmpxft_000317d5_00000000-6_sgm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_
.type _Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_, @function
_Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq 248(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14path_aggregateiiiiiiPiyPsS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_, .-_Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_
.globl _Z14path_aggregateiiiiiiPiyPsS0_
.type _Z14path_aggregateiiiiiiPiyPsS0_, @function
_Z14path_aggregateiiiiiiPiyPsS0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14path_aggregateiiiiiiPiyPsS0_, .-_Z14path_aggregateiiiiiiPiyPsS0_
.globl _Z31__device_stub__Z7BM_costyyPsiiiyyPsiii
.type _Z31__device_stub__Z7BM_costyyPsiiiyyPsiii, @function
_Z31__device_stub__Z7BM_costyyPsiiiyyPsiii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7BM_costyyPsiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z31__device_stub__Z7BM_costyyPsiiiyyPsiii, .-_Z31__device_stub__Z7BM_costyyPsiiiyyPsiii
.globl _Z7BM_costyyPsiii
.type _Z7BM_costyyPsiii, @function
_Z7BM_costyyPsiii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7BM_costyyPsiiiyyPsiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z7BM_costyyPsiii, .-_Z7BM_costyyPsiii
.globl _Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii
.type _Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii, @function
_Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17energy_minimalizePiPsS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii, .-_Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii
.globl _Z17energy_minimalizePiPsS0_iii
.type _Z17energy_minimalizePiPsS0_iii, @function
_Z17energy_minimalizePiPsS0_iii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z17energy_minimalizePiPsS0_iii, .-_Z17energy_minimalizePiPsS0_iii
.globl _Z32__device_stub__Z8validatePsS_iiiPsS_iii
.type _Z32__device_stub__Z8validatePsS_iiiPsS_iii, @function
_Z32__device_stub__Z8validatePsS_iiiPsS_iii:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8validatePsS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z32__device_stub__Z8validatePsS_iiiPsS_iii, .-_Z32__device_stub__Z8validatePsS_iiiPsS_iii
.globl _Z8validatePsS_iii
.type _Z8validatePsS_iii, @function
_Z8validatePsS_iii:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8validatePsS_iiiPsS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8validatePsS_iii, .-_Z8validatePsS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8validatePsS_iii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z17energy_minimalizePiPsS0_iii"
.section .rodata.str1.1
.LC2:
.string "_Z7BM_costyyPsiii"
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z14path_aggregateiiiiiiPiyPsS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8validatePsS_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17energy_minimalizePiPsS0_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7BM_costyyPsiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14path_aggregateiiiiiiPiyPsS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define NDISP 48
typedef unsigned char uchar;
using namespace std;
__global__ void path_aggregate(int width, int height, int D, int P1, int P2,
int dir, int* Espace, cudaTextureObject_t Cost,
short* texturePerp, short* textureParallel)
{
__shared__ short L_p0[NDISP+2];
__shared__ short L_c0[NDISP+2];
__shared__ short delta0;
short Tp = 0, T = 0, Tp2 = 0;
float Kt = 0;
int P1a, P2a; int Td;
int dy, dx;
int tid = threadIdx.x;
int d = tid+1;
//just one thread to prevent bank conflicts
if(tid == 0)
L_p0[0] = L_p0[NDISP+1] = L_c0[0] = L_c0[NDISP+1] = SHRT_MAX;
if(tid < D)
L_p0[d] = SHRT_MAX;
if(tid == 0)
delta0 = SHRT_MAX;
int x = 0;
int y = 0;
//set initial coordinates of a block
switch(dir)
{
case 0:
x = 0; y = blockIdx.x; dy = 0; dx = 1;
break;
case 1:
if(blockIdx.x < height)
{ y = height-1-(blockIdx.x); x = 0; dy=1; dx=1;}
else
{ y = 0; x = (blockIdx.x)-height;}
break;
case 2:
y = 0; x = blockIdx.x; dy = 1; dx = 0;
break;
case 3:
if(blockIdx.x < width)
{ x = blockIdx.x; y = 0; dy = 1; dx = -1;}
else
{ y = blockIdx.x-width; x = width-1; dy = 1; dx = -1;}
break;
case 4:
x = width-1; y = blockIdx.x; dy = 0; dx= -1;
break;
case 5:
if(blockIdx.x < height)
{ x = width-1; y = blockIdx.x; dy=-1; dx = -1;}
else
{ y = height-1; x = blockIdx.x-height; dy=-1; dx = -1;}
break;
case 6:
y = height-1; x = blockIdx.x; dy = -1; dx = 0;
break;
case 7:
if(blockIdx.x < height)
{ x = 0; y = blockIdx.x; dy = -1; dx = 1;}
else
{ x = blockIdx.x-height; y = height-1; dy = -1; dx = 1;}
break;
}
__syncthreads();
//main loop of a thread
while(x >= 0 && y >= 0 && x < width && y < height)
{
//read texture and adjust penalties
Kt = 1;//textureParallel[y*width+x]/500;
T = texturePerp[y*width+x];
Td = abs(T-Tp2);
short C;
short bestsad; short bestdisp;
P1a = P1;
P2a = P2;
Tp2 = Tp;
Tp = T;
if(tid < D)
{
C = tex2D<short>(Cost, (d-1)*width+x, y);
if(C < SHRT_MAX-5)
{
L_c0[d] = C + min((int)L_p0[d], min((int)L_p0[d-1]+P1a, min((int)L_p0[d+1]+P1a, (int)delta0))) - delta0;
Espace[y*width*D + x*D + d-1] += (int)L_c0[d]*Kt;
L_p0[d] = L_c0[d];
}
else
{
L_c0[d] = SHRT_MAX;
Espace[y*width*D + x*D + d-1] += SHRT_MAX;
L_p0[d] = L_c0[d];
}
__syncthreads();
for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
{
if((d-1) < n)
{
L_c0[d] = min((int)L_c0[d], (int)L_c0[d+n]);
}
if(n*2 != i)
{
L_c0[n+1] = L_c0[2*n+1];
n = n+1;
}
i = n;
__syncthreads();
}
delta0 = L_c0[1] + P2a;
}
__syncthreads();
x += dx; y += dy;
}
}
/* BM_cost
*
* Calculates block matching cost for D disparity levels
* between image1 and image2
*/
__global__ void BM_cost(cudaTextureObject_t image1, cudaTextureObject_t image2,
short* cost, int width, int height, int D)
{
extern __shared__ short I[];
int x = threadIdx.x;
int y = blockIdx.x;
I[x] = tex2D<uchar>(image2, x, y);
__syncthreads();
short i = tex2D<uchar>(image1, x, y);
int r = y*width*D + x;
for(int d=0; d<D; d++)
{
if(x >= d)
{
cost[r + d*width] = abs(i - I[x-d]);
}
else
cost[r + d*width] = SHRT_MAX;
}
}
__global__ void energy_minimalize(int *Energy, short* disparity, short* disparity2,
int D, int width, int height)
{
__shared__ int L[NDISP]; //storage for disparity values
__shared__ int cL[NDISP];
int d = threadIdx.x;
int x = blockIdx.x;
int y = blockIdx.y;
float d_refined;
//read energy for each disparity (one operation)
L[d] = Energy[y*width*D + x*D + d];
cL[d] = L[d];
__syncthreads();
//use reduction algorithm to minimalize energy
for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
{
if(d < n)
{
L[d] = min(L[d], L[d+n]);
}
if(n*2 != i)
{
L[n] = L[2*n];
n = n+1;
}
i = n;
__syncthreads();
}
if(cL[d] == L[0])
{
if(0 < d && d < D-1)
{
int denom2 = max((Energy[(y * width * D) + (x * D) + d - 1]
+ Energy[(y * width * D) + (x * D) + d + 1]
- 2 * Energy[(y * width * D) + (x * D) + d]), 1);
d_refined = 10 * ((float) d) + (float)((Energy[(y * width * D)
+ (x * D) + d - 1] - Energy[(y * width * D)
+ (x * D) + d + 1]) + denom2) / (denom2 * 2);
}
else
{
d_refined = 10*(float)d;
}
disparity[y*width+x] = d_refined;
if(x-1-d >= 0)
disparity2[y*width+x-1-d] = d_refined;
}
__syncthreads();
}
__global__ void validate(short* disparity, short* disparity2, int width, int height, int disp12maxdiff)
{
int x = threadIdx.x;
int y = blockIdx.x;
int d0 = disparity[y*width + x];
if(d0 != -1)
{
int x2 = x - d0;
if(0 <= x2 && abs(disparity2[y*width + x2]-d0) > 10*disp12maxdiff)
{
disparity[y*width+x] = -1;
}
}
} | #include <hip/hip_runtime.h>
#define NDISP 48
typedef unsigned char uchar;
using namespace std;
__global__ void path_aggregate(int width, int height, int D, int P1, int P2,
int dir, int* Espace, hipTextureObject_t Cost,
short* texturePerp, short* textureParallel)
{
__shared__ short L_p0[NDISP+2];
__shared__ short L_c0[NDISP+2];
__shared__ short delta0;
short Tp = 0, T = 0, Tp2 = 0;
float Kt = 0;
int P1a, P2a; int Td;
int dy, dx;
int tid = threadIdx.x;
int d = tid+1;
//just one thread to prevent bank conflicts
if(tid == 0)
L_p0[0] = L_p0[NDISP+1] = L_c0[0] = L_c0[NDISP+1] = SHRT_MAX;
if(tid < D)
L_p0[d] = SHRT_MAX;
if(tid == 0)
delta0 = SHRT_MAX;
int x = 0;
int y = 0;
//set initial coordinates of a block
switch(dir)
{
case 0:
x = 0; y = blockIdx.x; dy = 0; dx = 1;
break;
case 1:
if(blockIdx.x < height)
{ y = height-1-(blockIdx.x); x = 0; dy=1; dx=1;}
else
{ y = 0; x = (blockIdx.x)-height;}
break;
case 2:
y = 0; x = blockIdx.x; dy = 1; dx = 0;
break;
case 3:
if(blockIdx.x < width)
{ x = blockIdx.x; y = 0; dy = 1; dx = -1;}
else
{ y = blockIdx.x-width; x = width-1; dy = 1; dx = -1;}
break;
case 4:
x = width-1; y = blockIdx.x; dy = 0; dx= -1;
break;
case 5:
if(blockIdx.x < height)
{ x = width-1; y = blockIdx.x; dy=-1; dx = -1;}
else
{ y = height-1; x = blockIdx.x-height; dy=-1; dx = -1;}
break;
case 6:
y = height-1; x = blockIdx.x; dy = -1; dx = 0;
break;
case 7:
if(blockIdx.x < height)
{ x = 0; y = blockIdx.x; dy = -1; dx = 1;}
else
{ x = blockIdx.x-height; y = height-1; dy = -1; dx = 1;}
break;
}
__syncthreads();
//main loop of a thread
while(x >= 0 && y >= 0 && x < width && y < height)
{
//read texture and adjust penalties
Kt = 1;//textureParallel[y*width+x]/500;
T = texturePerp[y*width+x];
Td = abs(T-Tp2);
short C;
short bestsad; short bestdisp;
P1a = P1;
P2a = P2;
Tp2 = Tp;
Tp = T;
if(tid < D)
{
C = tex2D<short>(Cost, (d-1)*width+x, y);
if(C < SHRT_MAX-5)
{
L_c0[d] = C + min((int)L_p0[d], min((int)L_p0[d-1]+P1a, min((int)L_p0[d+1]+P1a, (int)delta0))) - delta0;
Espace[y*width*D + x*D + d-1] += (int)L_c0[d]*Kt;
L_p0[d] = L_c0[d];
}
else
{
L_c0[d] = SHRT_MAX;
Espace[y*width*D + x*D + d-1] += SHRT_MAX;
L_p0[d] = L_c0[d];
}
__syncthreads();
for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
{
if((d-1) < n)
{
L_c0[d] = min((int)L_c0[d], (int)L_c0[d+n]);
}
if(n*2 != i)
{
L_c0[n+1] = L_c0[2*n+1];
n = n+1;
}
i = n;
__syncthreads();
}
delta0 = L_c0[1] + P2a;
}
__syncthreads();
x += dx; y += dy;
}
}
/* BM_cost
*
* Calculates block matching cost for D disparity levels
* between image1 and image2
*/
__global__ void BM_cost(hipTextureObject_t image1, hipTextureObject_t image2,
short* cost, int width, int height, int D)
{
extern __shared__ short I[];
int x = threadIdx.x;
int y = blockIdx.x;
I[x] = tex2D<uchar>(image2, x, y);
__syncthreads();
short i = tex2D<uchar>(image1, x, y);
int r = y*width*D + x;
for(int d=0; d<D; d++)
{
if(x >= d)
{
cost[r + d*width] = abs(i - I[x-d]);
}
else
cost[r + d*width] = SHRT_MAX;
}
}
__global__ void energy_minimalize(int *Energy, short* disparity, short* disparity2,
int D, int width, int height)
{
__shared__ int L[NDISP]; //storage for disparity values
__shared__ int cL[NDISP];
int d = threadIdx.x;
int x = blockIdx.x;
int y = blockIdx.y;
float d_refined;
//read energy for each disparity (one operation)
L[d] = Energy[y*width*D + x*D + d];
cL[d] = L[d];
__syncthreads();
//use reduction algorithm to minimalize energy
for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
{
if(d < n)
{
L[d] = min(L[d], L[d+n]);
}
if(n*2 != i)
{
L[n] = L[2*n];
n = n+1;
}
i = n;
__syncthreads();
}
if(cL[d] == L[0])
{
if(0 < d && d < D-1)
{
int denom2 = max((Energy[(y * width * D) + (x * D) + d - 1]
+ Energy[(y * width * D) + (x * D) + d + 1]
- 2 * Energy[(y * width * D) + (x * D) + d]), 1);
d_refined = 10 * ((float) d) + (float)((Energy[(y * width * D)
+ (x * D) + d - 1] - Energy[(y * width * D)
+ (x * D) + d + 1]) + denom2) / (denom2 * 2);
}
else
{
d_refined = 10*(float)d;
}
disparity[y*width+x] = d_refined;
if(x-1-d >= 0)
disparity2[y*width+x-1-d] = d_refined;
}
__syncthreads();
}
__global__ void validate(short* disparity, short* disparity2, int width, int height, int disp12maxdiff)
{
int x = threadIdx.x;
int y = blockIdx.x;
int d0 = disparity[y*width + x];
if(d0 != -1)
{
int x2 = x - d0;
if(0 <= x2 && abs(disparity2[y*width + x2]-d0) > 10*disp12maxdiff)
{
disparity[y*width+x] = -1;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define NDISP 48
typedef unsigned char uchar;
using namespace std;
__global__ void path_aggregate(int width, int height, int D, int P1, int P2,
int dir, int* Espace, hipTextureObject_t Cost,
short* texturePerp, short* textureParallel)
{
__shared__ short L_p0[NDISP+2];
__shared__ short L_c0[NDISP+2];
__shared__ short delta0;
short Tp = 0, T = 0, Tp2 = 0;
float Kt = 0;
int P1a, P2a; int Td;
int dy, dx;
int tid = threadIdx.x;
int d = tid+1;
//just one thread to prevent bank conflicts
if(tid == 0)
L_p0[0] = L_p0[NDISP+1] = L_c0[0] = L_c0[NDISP+1] = SHRT_MAX;
if(tid < D)
L_p0[d] = SHRT_MAX;
if(tid == 0)
delta0 = SHRT_MAX;
int x = 0;
int y = 0;
//set initial coordinates of a block
switch(dir)
{
case 0:
x = 0; y = blockIdx.x; dy = 0; dx = 1;
break;
case 1:
if(blockIdx.x < height)
{ y = height-1-(blockIdx.x); x = 0; dy=1; dx=1;}
else
{ y = 0; x = (blockIdx.x)-height;}
break;
case 2:
y = 0; x = blockIdx.x; dy = 1; dx = 0;
break;
case 3:
if(blockIdx.x < width)
{ x = blockIdx.x; y = 0; dy = 1; dx = -1;}
else
{ y = blockIdx.x-width; x = width-1; dy = 1; dx = -1;}
break;
case 4:
x = width-1; y = blockIdx.x; dy = 0; dx= -1;
break;
case 5:
if(blockIdx.x < height)
{ x = width-1; y = blockIdx.x; dy=-1; dx = -1;}
else
{ y = height-1; x = blockIdx.x-height; dy=-1; dx = -1;}
break;
case 6:
y = height-1; x = blockIdx.x; dy = -1; dx = 0;
break;
case 7:
if(blockIdx.x < height)
{ x = 0; y = blockIdx.x; dy = -1; dx = 1;}
else
{ x = blockIdx.x-height; y = height-1; dy = -1; dx = 1;}
break;
}
__syncthreads();
//main loop of a thread
while(x >= 0 && y >= 0 && x < width && y < height)
{
//read texture and adjust penalties
Kt = 1;//textureParallel[y*width+x]/500;
T = texturePerp[y*width+x];
Td = abs(T-Tp2);
short C;
short bestsad; short bestdisp;
P1a = P1;
P2a = P2;
Tp2 = Tp;
Tp = T;
if(tid < D)
{
C = tex2D<short>(Cost, (d-1)*width+x, y);
if(C < SHRT_MAX-5)
{
L_c0[d] = C + min((int)L_p0[d], min((int)L_p0[d-1]+P1a, min((int)L_p0[d+1]+P1a, (int)delta0))) - delta0;
Espace[y*width*D + x*D + d-1] += (int)L_c0[d]*Kt;
L_p0[d] = L_c0[d];
}
else
{
L_c0[d] = SHRT_MAX;
Espace[y*width*D + x*D + d-1] += SHRT_MAX;
L_p0[d] = L_c0[d];
}
__syncthreads();
for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
{
if((d-1) < n)
{
L_c0[d] = min((int)L_c0[d], (int)L_c0[d+n]);
}
if(n*2 != i)
{
L_c0[n+1] = L_c0[2*n+1];
n = n+1;
}
i = n;
__syncthreads();
}
delta0 = L_c0[1] + P2a;
}
__syncthreads();
x += dx; y += dy;
}
}
/* BM_cost
*
* Calculates block matching cost for D disparity levels
* between image1 and image2
*/
__global__ void BM_cost(hipTextureObject_t image1, hipTextureObject_t image2,
short* cost, int width, int height, int D)
{
extern __shared__ short I[];
int x = threadIdx.x;
int y = blockIdx.x;
I[x] = tex2D<uchar>(image2, x, y);
__syncthreads();
short i = tex2D<uchar>(image1, x, y);
int r = y*width*D + x;
for(int d=0; d<D; d++)
{
if(x >= d)
{
cost[r + d*width] = abs(i - I[x-d]);
}
else
cost[r + d*width] = SHRT_MAX;
}
}
__global__ void energy_minimalize(int *Energy, short* disparity, short* disparity2,
int D, int width, int height)
{
__shared__ int L[NDISP]; //storage for disparity values
__shared__ int cL[NDISP];
int d = threadIdx.x;
int x = blockIdx.x;
int y = blockIdx.y;
float d_refined;
//read energy for each disparity (one operation)
L[d] = Energy[y*width*D + x*D + d];
cL[d] = L[d];
__syncthreads();
//use reduction algorithm to minimalize energy
for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
{
if(d < n)
{
L[d] = min(L[d], L[d+n]);
}
if(n*2 != i)
{
L[n] = L[2*n];
n = n+1;
}
i = n;
__syncthreads();
}
if(cL[d] == L[0])
{
if(0 < d && d < D-1)
{
int denom2 = max((Energy[(y * width * D) + (x * D) + d - 1]
+ Energy[(y * width * D) + (x * D) + d + 1]
- 2 * Energy[(y * width * D) + (x * D) + d]), 1);
d_refined = 10 * ((float) d) + (float)((Energy[(y * width * D)
+ (x * D) + d - 1] - Energy[(y * width * D)
+ (x * D) + d + 1]) + denom2) / (denom2 * 2);
}
else
{
d_refined = 10*(float)d;
}
disparity[y*width+x] = d_refined;
if(x-1-d >= 0)
disparity2[y*width+x-1-d] = d_refined;
}
__syncthreads();
}
__global__ void validate(short* disparity, short* disparity2, int width, int height, int disp12maxdiff)
{
int x = threadIdx.x;
int y = blockIdx.x;
int d0 = disparity[y*width + x];
if(d0 != -1)
{
int x2 = x - d0;
if(0 <= x2 && abs(disparity2[y*width + x2]-d0) > 10*disp12maxdiff)
{
disparity[y*width+x] = -1;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.globl _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.p2align 8
.type _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_,@function
_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_2
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0x7fff
ds_store_b16 v1, v2 offset:98
ds_store_b16 v1, v2
ds_store_b16 v1, v2 offset:210
ds_store_b16 v1, v2 offset:112
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
s_load_b32 s3, s[0:1], 0x8
v_add_nc_u32_e32 v1, 1, v0
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e64 s2, s3, v0
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB0_4
v_dual_mov_b32 v3, 0x7fff :: v_dual_lshlrev_b32 v2, 1, v1
ds_store_b16 v2, v3 offset:112
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_6
v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0x7fff
ds_store_b16 v2, v3 offset:100
.LBB0_6:
s_or_b32 exec_lo, exec_lo, s4
s_clause 0x1
s_load_b32 s4, s[0:1], 0x14
s_load_b64 s[8:9], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s4, 4
s_cbranch_scc1 .LBB0_12
s_cmp_lt_i32 s4, 6
s_cbranch_scc1 .LBB0_13
s_cmp_lt_i32 s4, 7
s_cbranch_scc1 .LBB0_14
s_mov_b32 s5, 0
s_cmp_eq_u32 s4, 7
s_mov_b32 s14, 0
s_mov_b32 s16, 0
s_cbranch_scc0 .LBB0_15
s_cmp_lt_u32 s15, s9
s_cbranch_scc1 .LBB0_64
s_sub_i32 s16, s15, s9
s_add_i32 s14, s9, -1
s_branch .LBB0_65
.LBB0_12:
s_branch .LBB0_28
.LBB0_13:
s_branch .LBB0_18
.LBB0_14:
s_mov_b32 s5, -1
.LBB0_15:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccnz .LBB0_17
.LBB0_16:
s_mov_b32 s17, -1
s_add_i32 s14, s9, -1
s_mov_b32 s18, 0
s_mov_b32 s16, s15
.LBB0_17:
s_cbranch_execnz .LBB0_27
.LBB0_18:
s_cmp_gt_i32 s4, 4
s_cbranch_scc0 .LBB0_21
s_cmp_ge_u32 s15, s9
s_cbranch_scc0 .LBB0_22
s_mov_b32 s17, -1
s_add_i32 s14, s9, -1
s_sub_i32 s16, s15, s9
s_cbranch_execz .LBB0_23
s_branch .LBB0_24
.LBB0_21:
s_mov_b32 s5, -1
s_branch .LBB0_25
.LBB0_22:
.LBB0_23:
s_mov_b32 s17, -1
s_add_i32 s16, s8, -1
s_mov_b32 s14, s15
.LBB0_24:
s_mov_b32 s5, 0
.LBB0_25:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s5
s_mov_b32 s18, s17
s_cbranch_vccnz .LBB0_27
s_mov_b32 s18, -1
s_add_i32 s16, s8, -1
s_mov_b32 s17, 0
s_mov_b32 s14, s15
.LBB0_27:
s_cbranch_execnz .LBB0_47
.LBB0_28:
s_cmp_lt_i32 s4, 2
s_cbranch_scc1 .LBB0_33
s_cmp_gt_i32 s4, 2
s_cbranch_scc0 .LBB0_34
s_mov_b32 s5, 0
s_cmp_lt_u32 s15, s8
s_mov_b32 s14, 0
s_mov_b32 s16, s15
s_cbranch_scc1 .LBB0_32
s_sub_i32 s14, s15, s8
s_add_i32 s16, s8, -1
.LBB0_32:
s_mov_b32 s18, -1
s_mov_b32 s17, 1
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccz .LBB0_35
s_branch .LBB0_36
.LBB0_33:
s_branch .LBB0_37
.LBB0_34:
.LBB0_35:
s_mov_b32 s14, 0
s_mov_b32 s16, s15
s_mov_b32 s17, 1
s_mov_b32 s18, 0
.LBB0_36:
s_cbranch_execnz .LBB0_47
.LBB0_37:
s_cmp_gt_i32 s4, 0
s_cbranch_scc0 .LBB0_40
s_cmp_ge_u32 s15, s9
s_cbranch_scc0 .LBB0_41
s_sub_i32 s16, s15, s9
s_mov_b32 s5, 0
s_mov_b32 s14, 0
s_branch .LBB0_42
.LBB0_40:
s_branch .LBB0_45
.LBB0_41:
s_mov_b32 s5, -1
.LBB0_42:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s5
s_mov_b32 s17, 1
s_cbranch_vccnz .LBB0_44
s_not_b32 s5, s15
s_mov_b32 s16, 0
s_add_i32 s14, s5, s9
.LBB0_44:
s_mov_b32 s18, s17
s_cbranch_execnz .LBB0_47
.LBB0_45:
s_mov_b32 s16, 0
s_cmp_lg_u32 s4, 0
s_mov_b32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b32 s18, 1
s_mov_b32 s17, 0
s_mov_b32 s14, s15
.LBB0_47:
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s4, s16, s14
s_cmp_gt_i32 s4, -1
s_barrier
s_cselect_b32 s4, -1, 0
s_cmp_lt_i32 s16, s8
buffer_gl0_inv
s_cselect_b32 s5, -1, 0
s_cmp_lt_i32 s14, s9
s_cselect_b32 s6, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s5, s5, s6
s_and_b32 s4, s5, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 vcc_lo, exec_lo, s4
s_cbranch_vccnz .LBB0_63
s_clause 0x1
s_load_b64 s[10:11], s[0:1], 0xc
s_load_b128 s[4:7], s[0:1], 0x18
v_dual_mov_b32 v7, 0 :: v_dual_lshlrev_b32 v2, 1, v1
v_lshlrev_b32_e32 v6, 1, v0
v_mul_lo_u32 v3, v0, s8
s_add_u32 s12, s0, 56
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v4, 0x70, v2
s_addc_u32 s13, s1, 0
v_add_nc_u32_e32 v5, 0x70, v6
v_add_nc_u32_e32 v6, 0x74, v6
s_branch .LBB0_51
.LBB0_49:
s_set_inst_prefetch_distance 0x2
ds_load_u16 v8, v7 offset:2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v8, s11, v8
ds_store_b16 v7, v8 offset:100
.LBB0_50:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s16, s16, s18
s_add_i32 s14, s14, s17
s_waitcnt lgkmcnt(0)
s_or_b32 s0, s16, s14
s_barrier
s_cmp_gt_i32 s0, -1
buffer_gl0_inv
s_cselect_b32 s0, -1, 0
s_cmp_lt_i32 s16, s8
s_cselect_b32 s1, -1, 0
s_cmp_lt_i32 s14, s9
s_cselect_b32 s15, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s1, s1, s15
s_and_b32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_63
.LBB0_51:
s_and_saveexec_b32 s1, s2
s_cbranch_execz .LBB0_50
s_waitcnt lgkmcnt(0)
s_clause 0x3
s_load_b32 s0, s[6:7], 0x38
s_load_b32 s19, s[6:7], 0x30
s_load_b32 s20, s[6:7], 0x8
s_load_b32 s21, s[6:7], 0x28
s_mul_i32 s15, s14, s8
v_cvt_f32_i32_e32 v8, s14
s_add_i32 s15, s15, s16
s_load_b128 s[28:31], s[6:7], 0x30
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s0, 20
s_cselect_b32 vcc_lo, -1, 0
v_cvt_f32_u32_e32 v10, s21
s_bitcmp0_b32 s19, 15
s_cselect_b32 s0, -1, 0
s_bfe_u32 s19, s20, 0xe000e
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v10, 1.0, v10, s0
s_add_i32 s19, s19, 1
s_load_b256 s[20:27], s[6:7], 0x0
v_cvt_f32_u32_e32 v9, s19
v_rcp_f32_e32 v13, v10
v_add_nc_u32_e32 v11, s16, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v9, 1.0, v9, s0
s_mov_b32 s0, exec_lo
v_cvt_f32_i32_e32 v11, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v12, v9
v_dual_mul_f32 v9, v9, v8 :: v_dual_mul_f32 v10, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v9, v9
v_floor_f32_e32 v10, v10
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v10, v13, v10 :: v_dual_mul_f32 v9, v12, v9
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v9, v8, v9 :: v_dual_cndmask_b32 v8, v11, v10
s_waitcnt lgkmcnt(0)
image_sample_lz v8, v[8:9], s[20:27], s[28:31] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_cmpx_lt_i16_e32 0x7ff9, v8
s_xor_b32 s0, exec_lo, s0
s_cbranch_execz .LBB0_54
v_mad_u64_u32 v[8:9], null, s15, s3, v[0:1]
v_mov_b32_e32 v11, 0x7fff
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_load_b32 v10, v[8:9], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v10, 0x7fff, v10
global_store_b32 v[8:9], v10, off
ds_store_b16 v2, v11
ds_store_b16 v4, v11
.LBB0_54:
s_and_not1_saveexec_b32 s0, s0
s_cbranch_execz .LBB0_56
v_mad_u64_u32 v[9:10], null, s15, s3, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v10, 31, v9
v_lshlrev_b64 v[9:10], 2, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s4, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
global_load_b32 v11, v[9:10], off
ds_load_i16 v12, v6
ds_load_u16 v13, v7 offset:100
ds_load_i16 v14, v5
ds_load_i16 v15, v4
s_waitcnt lgkmcnt(3)
v_add_nc_u32_e32 v12, s10, v12
s_waitcnt lgkmcnt(2)
v_bfe_i32 v16, v13, 0, 16
v_sub_nc_u16 v8, v8, v13
s_delay_alu instid0(VALU_DEP_2)
v_min_i32_e32 v12, v12, v16
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v11, v11
s_waitcnt lgkmcnt(1)
v_add_nc_u32_e32 v14, s10, v14
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min3_i32 v12, v15, v14, v12
v_add_nc_u16 v8, v8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_bfe_i32 v12, v8, 0, 16
v_cvt_f32_i32_e32 v12, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v11, v12
v_cvt_i32_f32_e32 v11, v11
global_store_b32 v[9:10], v11, off
ds_store_b16 v2, v8
ds_store_b16 v4, v8
.LBB0_56:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_load_b32 s0, s[12:13], 0xc
s_waitcnt lgkmcnt(0)
v_cmp_lt_u16_e64 s15, s0, 2
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s15
s_cbranch_vccnz .LBB0_49
s_and_b32 s15, 0xffff, s0
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_59
.p2align 6
.LBB0_58:
s_cmp_lt_u32 s0, 2
s_mov_b32 s15, s0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_49
.LBB0_59:
s_lshr_b32 s0, s15, 1
s_mov_b32 s19, exec_lo
v_cmpx_gt_u32_e64 s0, v0
s_cbranch_execz .LBB0_61
v_add_lshl_u32 v8, s0, v1, 1
ds_load_u16 v9, v2
ds_load_u16 v8, v8
s_waitcnt lgkmcnt(0)
v_min_i16 v8, v9, v8
ds_store_b16 v2, v8
.LBB0_61:
s_or_b32 exec_lo, exec_lo, s19
s_bitcmp0_b32 s15, 0
s_cbranch_scc1 .LBB0_58
s_lshl_b32 s15, s15, 1
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v8, s15
s_lshl_b32 s15, s0, 1
s_add_i32 s0, s0, 1
v_mov_b32_e32 v9, s15
ds_load_u16 v8, v8
s_waitcnt lgkmcnt(0)
ds_store_b16 v9, v8 offset:2
s_branch .LBB0_58
.LBB0_63:
s_endpgm
.LBB0_64:
s_mov_b32 s14, s15
.LBB0_65:
s_mov_b32 s18, 1
s_mov_b32 s17, -1
s_and_not1_b32 vcc_lo, exec_lo, s5
s_cbranch_vccz .LBB0_16
s_branch .LBB0_17
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.amdhsa_group_segment_fixed_size 212
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, .Lfunc_end0-_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z7BM_costP13__hip_textureS0_Psiii
.globl _Z7BM_costP13__hip_textureS0_Psiii
.p2align 8
.type _Z7BM_costP13__hip_textureS0_Psiii,@function
_Z7BM_costP13__hip_textureS0_Psiii:
s_clause 0x1
s_load_b64 s[6:7], s[0:1], 0x8
s_load_b32 s4, s[0:1], 0x20
v_cvt_f32_i32_e32 v1, s15
s_waitcnt lgkmcnt(0)
s_clause 0x4
s_load_b32 s2, s[6:7], 0x38
s_load_b32 s3, s[6:7], 0x30
s_load_b32 s5, s[6:7], 0x8
s_load_b32 s8, s[6:7], 0x28
s_load_b256 s[16:23], s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s2, 20
s_cselect_b32 vcc_lo, -1, 0
s_bitcmp0_b32 s3, 15
v_cvt_f32_u32_e32 v3, s8
s_cselect_b32 s2, -1, 0
s_bfe_u32 s3, s5, 0xe000e
s_load_b128 s[8:11], s[6:7], 0x30
s_add_i32 s3, s3, 1
v_cndmask_b32_e64 v3, 1.0, v3, s2
v_cvt_f32_u32_e32 v2, s3
s_mov_b32 s5, 0
s_cmp_lt_i32 s4, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v3
v_cndmask_b32_e64 v4, 1.0, v2, s2
v_cvt_f32_i32_e32 v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
v_dual_mul_f32 v4, v4, v1 :: v_dual_mul_f32 v3, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_floor_f32_e32 v4, v4
v_floor_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v4, v5, v4 :: v_dual_mul_f32 v3, v6, v3
s_delay_alu instid0(VALU_DEP_1)
v_dual_cndmask_b32 v4, v1, v4 :: v_dual_cndmask_b32 v3, v2, v3
s_waitcnt lgkmcnt(0)
image_sample_lz v4, v[3:4], s[16:23], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
v_lshl_add_u32 v3, v0, 1, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v4, 0xff, v4
ds_store_b16 v3, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_5
s_clause 0x2
s_load_b64 s[6:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_load_b32 s1, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_clause 0x5
s_load_b32 s0, s[6:7], 0x38
s_load_b32 s12, s[6:7], 0x30
s_load_b32 s13, s[6:7], 0x28
s_load_b32 s14, s[6:7], 0x8
s_load_b128 s[8:11], s[6:7], 0x30
s_load_b256 s[16:23], s[6:7], 0x0
s_mul_i32 s15, s15, s1
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s0, 20
s_cselect_b32 vcc_lo, -1, 0
s_bitcmp0_b32 s12, 15
v_cvt_f32_u32_e32 v4, s13
s_cselect_b32 s0, -1, 0
s_bfe_u32 s12, s14, 0xe000e
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_add_i32 s12, s12, 1
v_cndmask_b32_e64 v4, 1.0, v4, s0
v_cvt_f32_u32_e32 v5, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v6, v4
v_cndmask_b32_e64 v5, 1.0, v5, s0
v_mul_f32_e32 v4, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v7, v5
v_mul_f32_e32 v5, v5, v1
v_floor_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_floor_f32_e32 v5, v5
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v4, v6, v4 :: v_dual_mul_f32 v5, v7, v5
v_dual_cndmask_b32 v4, v2, v4 :: v_dual_cndmask_b32 v5, v1, v5
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
image_sample_lz v4, v[4:5], s[16:23], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
s_waitcnt vmcnt(0)
v_and_b32_e32 v4, 0xff, v4
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_3
.p2align 6
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s0
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v3, -2, v3
s_add_i32 s5, s5, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_cmp_eq_u32 s4, s5
v_lshlrev_b64 v[6:7], 1, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, s2, v6
v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
global_store_b16 v[6:7], v5, off
s_cbranch_scc1 .LBB1_5
.LBB1_3:
v_mov_b32_e32 v5, 0x7fff
s_mov_b32 s0, exec_lo
v_cmpx_le_u32_e64 s5, v0
s_cbranch_execz .LBB1_2
ds_load_i16 v2, v3
s_waitcnt lgkmcnt(0)
v_sub_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v5, 0, v2
v_max_i32_e32 v5, v2, v5
s_branch .LBB1_2
.LBB1_5:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7BM_costP13__hip_textureS0_Psiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 36
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z7BM_costP13__hip_textureS0_Psiii, .Lfunc_end1-_Z7BM_costP13__hip_textureS0_Psiii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17energy_minimalizePiPsS0_iii
.globl _Z17energy_minimalizePiPsS0_iii
.p2align 8
.type _Z17energy_minimalizePiPsS0_iii,@function
_Z17energy_minimalizePiPsS0_iii:
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x34
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b32_e32 v3, 2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_add_nc_u32_e32 v4, 0xc0, v3
s_waitcnt lgkmcnt(0)
s_mul_i32 s3, s15, s3
s_add_i32 s4, s3, s14
v_cmp_lt_u16_e64 s3, s5, 2
v_mad_u64_u32 v[1:2], null, s4, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
s_and_b32 vcc_lo, exec_lo, s3
global_load_b32 v5, v[1:2], off
s_waitcnt vmcnt(0)
ds_store_2addr_b32 v3, v5, v5 offset1:48
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB2_7
s_and_b32 s5, 0xffff, s5
s_set_inst_prefetch_distance 0x1
s_branch .LBB2_3
.p2align 6
.LBB2_2:
s_cmp_lt_i32 s3, 2
s_mov_b32 s5, s3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB2_7
.LBB2_3:
s_lshr_b32 s3, s5, 1
s_mov_b32 s6, exec_lo
v_cmpx_gt_u32_e64 s3, v0
s_cbranch_execz .LBB2_5
v_add_lshl_u32 v5, s3, v0, 2
ds_load_b32 v6, v3
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
v_min_i32_e32 v5, v6, v5
ds_store_b32 v3, v5
.LBB2_5:
s_or_b32 exec_lo, exec_lo, s6
s_and_b32 s6, s5, 0x7ffffffe
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s6, s5
s_cbranch_scc1 .LBB2_2
s_lshl_b32 s5, s6, 2
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v5, s5
s_lshl_b32 s5, s3, 2
s_add_i32 s3, s3, 1
v_mov_b32_e32 v6, s5
ds_load_b32 v5, v5
s_waitcnt lgkmcnt(0)
ds_store_b32 v6, v5
s_branch .LBB2_2
.LBB2_7:
s_set_inst_prefetch_distance 0x2
v_mov_b32_e32 v3, 0
s_mov_b32 s3, exec_lo
ds_load_b32 v4, v4
ds_load_b32 v3, v3
s_waitcnt lgkmcnt(0)
v_cmpx_eq_u32_e64 v4, v3
s_cbranch_execz .LBB2_14
s_add_i32 s2, s2, -1
v_cmp_eq_u32_e32 vcc_lo, 0, v0
v_cmp_le_i32_e64 s2, s2, v0
v_cvt_f32_i32_e32 v3, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s5, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_xor_b32 s2, exec_lo, s5
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v4, 0x41200000, v3
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB2_12
s_clause 0x1
global_load_b32 v4, v[1:2], off offset:-4
global_load_b64 v[1:2], v[1:2], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v5, v2, v4
v_lshlrev_b32_e32 v1, 1, v1
v_sub_nc_u32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v1, v5, v1
v_max_i32_e32 v1, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v1
v_lshlrev_b32_e32 v1, 1, v1
v_cvt_f32_i32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v1, v1
v_div_scale_f32 v4, null, v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
v_div_scale_f32 v6, vcc_lo, v2, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v7, v6, v5
v_fma_f32 v8, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v7, v8, v5
v_fma_f32 v4, -v4, v7, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v4, v4, v5, v7
v_div_fixup_f32 v1, v4, v1, v2
s_delay_alu instid0(VALU_DEP_1)
v_fmamk_f32 v4, v3, 0x41200000, v1
.LBB2_12:
s_or_b32 exec_lo, exec_lo, s2
s_load_b64 s[6:7], s[0:1], 0x8
v_subrev_nc_u32_e32 v2, s14, v0
s_ashr_i32 s5, s4, 31
v_cvt_i32_f32_e32 v1, v4
s_lshl_b64 s[8:9], s[4:5], 1
v_mov_b32_e32 v3, 0
v_cmp_gt_i32_e32 vcc_lo, 0, v2
s_waitcnt lgkmcnt(0)
s_add_u32 s6, s6, s8
s_addc_u32 s7, s7, s9
global_store_b16 v3, v1, s[6:7]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB2_14
s_load_b64 s[0:1], s[0:1], 0x10
v_xad_u32 v2, v0, -1, s4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 1, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b16 v[2:3], v1, off
.LBB2_14:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17energy_minimalizePiPsS0_iii
.amdhsa_group_segment_fixed_size 384
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z17energy_minimalizePiPsS0_iii, .Lfunc_end2-_Z17energy_minimalizePiPsS0_iii
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8validatePsS_iii
.globl _Z8validatePsS_iii
.p2align 8
.type _Z8validatePsS_iii,@function
_Z8validatePsS_iii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s15, s15, s4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, s15, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 1, v[1:2]
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
s_mov_b32 s2, exec_lo
global_load_u16 v3, v[1:2], off
s_waitcnt vmcnt(0)
v_cmpx_ne_u16_e32 -1, v3
s_cbranch_execz .LBB3_4
v_bfe_i32 v3, v3, 0, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_cmp_lt_i32_e32 vcc_lo, -1, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_4
s_load_b64 s[2:3], s[0:1], 0x8
v_add_nc_u32_e32 v4, s15, v0
s_load_b32 s0, s[0:1], 0x18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[4:5], 1, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s3, v5, vcc_lo
s_mul_i32 s0, s0, 10
global_load_i16 v0, v[4:5], off
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, 0, v0
v_max_i32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, s0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_4
v_mov_b32_e32 v0, -1
global_store_b16 v[1:2], v0, off
.LBB3_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8validatePsS_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z8validatePsS_iii, .Lfunc_end3-_Z8validatePsS_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 48
.size: 8
.value_kind: global_buffer
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 212
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 36
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7BM_costP13__hip_textureS0_Psiii
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z7BM_costP13__hip_textureS0_Psiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 384
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17energy_minimalizePiPsS0_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17energy_minimalizePiPsS0_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8validatePsS_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8validatePsS_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define NDISP 48
typedef unsigned char uchar;
using namespace std;
__global__ void path_aggregate(int width, int height, int D, int P1, int P2,
int dir, int* Espace, hipTextureObject_t Cost,
short* texturePerp, short* textureParallel)
{
__shared__ short L_p0[NDISP+2];
__shared__ short L_c0[NDISP+2];
__shared__ short delta0;
short Tp = 0, T = 0, Tp2 = 0;
float Kt = 0;
int P1a, P2a; int Td;
int dy, dx;
int tid = threadIdx.x;
int d = tid+1;
//just one thread to prevent bank conflicts
if(tid == 0)
L_p0[0] = L_p0[NDISP+1] = L_c0[0] = L_c0[NDISP+1] = SHRT_MAX;
if(tid < D)
L_p0[d] = SHRT_MAX;
if(tid == 0)
delta0 = SHRT_MAX;
int x = 0;
int y = 0;
//set initial coordinates of a block
switch(dir)
{
case 0:
x = 0; y = blockIdx.x; dy = 0; dx = 1;
break;
case 1:
if(blockIdx.x < height)
{ y = height-1-(blockIdx.x); x = 0; dy=1; dx=1;}
else
{ y = 0; x = (blockIdx.x)-height;}
break;
case 2:
y = 0; x = blockIdx.x; dy = 1; dx = 0;
break;
case 3:
if(blockIdx.x < width)
{ x = blockIdx.x; y = 0; dy = 1; dx = -1;}
else
{ y = blockIdx.x-width; x = width-1; dy = 1; dx = -1;}
break;
case 4:
x = width-1; y = blockIdx.x; dy = 0; dx= -1;
break;
case 5:
if(blockIdx.x < height)
{ x = width-1; y = blockIdx.x; dy=-1; dx = -1;}
else
{ y = height-1; x = blockIdx.x-height; dy=-1; dx = -1;}
break;
case 6:
y = height-1; x = blockIdx.x; dy = -1; dx = 0;
break;
case 7:
if(blockIdx.x < height)
{ x = 0; y = blockIdx.x; dy = -1; dx = 1;}
else
{ x = blockIdx.x-height; y = height-1; dy = -1; dx = 1;}
break;
}
__syncthreads();
//main loop of a thread
while(x >= 0 && y >= 0 && x < width && y < height)
{
//read texture and adjust penalties
Kt = 1;//textureParallel[y*width+x]/500;
T = texturePerp[y*width+x];
Td = abs(T-Tp2);
short C;
short bestsad; short bestdisp;
P1a = P1;
P2a = P2;
Tp2 = Tp;
Tp = T;
if(tid < D)
{
C = tex2D<short>(Cost, (d-1)*width+x, y);
if(C < SHRT_MAX-5)
{
L_c0[d] = C + min((int)L_p0[d], min((int)L_p0[d-1]+P1a, min((int)L_p0[d+1]+P1a, (int)delta0))) - delta0;
Espace[y*width*D + x*D + d-1] += (int)L_c0[d]*Kt;
L_p0[d] = L_c0[d];
}
else
{
L_c0[d] = SHRT_MAX;
Espace[y*width*D + x*D + d-1] += SHRT_MAX;
L_p0[d] = L_c0[d];
}
__syncthreads();
for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
{
if((d-1) < n)
{
L_c0[d] = min((int)L_c0[d], (int)L_c0[d+n]);
}
if(n*2 != i)
{
L_c0[n+1] = L_c0[2*n+1];
n = n+1;
}
i = n;
__syncthreads();
}
delta0 = L_c0[1] + P2a;
}
__syncthreads();
x += dx; y += dy;
}
}
/* BM_cost
*
* Calculates block matching cost for D disparity levels
* between image1 and image2
*/
__global__ void BM_cost(hipTextureObject_t image1, hipTextureObject_t image2,
short* cost, int width, int height, int D)
{
extern __shared__ short I[];
int x = threadIdx.x;
int y = blockIdx.x;
I[x] = tex2D<uchar>(image2, x, y);
__syncthreads();
short i = tex2D<uchar>(image1, x, y);
int r = y*width*D + x;
for(int d=0; d<D; d++)
{
if(x >= d)
{
cost[r + d*width] = abs(i - I[x-d]);
}
else
cost[r + d*width] = SHRT_MAX;
}
}
__global__ void energy_minimalize(int *Energy, short* disparity, short* disparity2,
int D, int width, int height)
{
__shared__ int L[NDISP]; //storage for disparity values
__shared__ int cL[NDISP];
int d = threadIdx.x;
int x = blockIdx.x;
int y = blockIdx.y;
float d_refined;
//read energy for each disparity (one operation)
L[d] = Energy[y*width*D + x*D + d];
cL[d] = L[d];
__syncthreads();
//use reduction algorithm to minimalize energy
for(int i = blockDim.x, n = blockDim.x/2; n>0; n /= 2)
{
if(d < n)
{
L[d] = min(L[d], L[d+n]);
}
if(n*2 != i)
{
L[n] = L[2*n];
n = n+1;
}
i = n;
__syncthreads();
}
if(cL[d] == L[0])
{
if(0 < d && d < D-1)
{
int denom2 = max((Energy[(y * width * D) + (x * D) + d - 1]
+ Energy[(y * width * D) + (x * D) + d + 1]
- 2 * Energy[(y * width * D) + (x * D) + d]), 1);
d_refined = 10 * ((float) d) + (float)((Energy[(y * width * D)
+ (x * D) + d - 1] - Energy[(y * width * D)
+ (x * D) + d + 1]) + denom2) / (denom2 * 2);
}
else
{
d_refined = 10*(float)d;
}
disparity[y*width+x] = d_refined;
if(x-1-d >= 0)
disparity2[y*width+x-1-d] = d_refined;
}
__syncthreads();
}
__global__ void validate(short* disparity, short* disparity2, int width, int height, int disp12maxdiff)
{
int x = threadIdx.x;
int y = blockIdx.x;
int d0 = disparity[y*width + x];
if(d0 != -1)
{
int x2 = x - d0;
if(0 <= x2 && abs(disparity2[y*width + x2]-d0) > 10*disp12maxdiff)
{
disparity[y*width+x] = -1;
}
}
} | .text
.file "sgm.hip"
.globl _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_ # -- Begin function _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
.p2align 4, 0x90
.type _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_,@function
_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_: # @_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_, .Lfunc_end0-_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__BM_costP13__hip_textureS0_Psiii # -- Begin function _Z22__device_stub__BM_costP13__hip_textureS0_Psiii
.p2align 4, 0x90
.type _Z22__device_stub__BM_costP13__hip_textureS0_Psiii,@function
_Z22__device_stub__BM_costP13__hip_textureS0_Psiii: # @_Z22__device_stub__BM_costP13__hip_textureS0_Psiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7BM_costP13__hip_textureS0_Psiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z22__device_stub__BM_costP13__hip_textureS0_Psiii, .Lfunc_end1-_Z22__device_stub__BM_costP13__hip_textureS0_Psiii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__energy_minimalizePiPsS0_iii # -- Begin function _Z32__device_stub__energy_minimalizePiPsS0_iii
.p2align 4, 0x90
.type _Z32__device_stub__energy_minimalizePiPsS0_iii,@function
_Z32__device_stub__energy_minimalizePiPsS0_iii: # @_Z32__device_stub__energy_minimalizePiPsS0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17energy_minimalizePiPsS0_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z32__device_stub__energy_minimalizePiPsS0_iii, .Lfunc_end2-_Z32__device_stub__energy_minimalizePiPsS0_iii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__validatePsS_iii # -- Begin function _Z23__device_stub__validatePsS_iii
.p2align 4, 0x90
.type _Z23__device_stub__validatePsS_iii,@function
_Z23__device_stub__validatePsS_iii: # @_Z23__device_stub__validatePsS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8validatePsS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z23__device_stub__validatePsS_iii, .Lfunc_end3-_Z23__device_stub__validatePsS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7BM_costP13__hip_textureS0_Psiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17energy_minimalizePiPsS0_iii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8validatePsS_iii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_,@object # @_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.section .rodata,"a",@progbits
.globl _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.p2align 3, 0x0
_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_:
.quad _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
.size _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, 8
.type _Z7BM_costP13__hip_textureS0_Psiii,@object # @_Z7BM_costP13__hip_textureS0_Psiii
.globl _Z7BM_costP13__hip_textureS0_Psiii
.p2align 3, 0x0
_Z7BM_costP13__hip_textureS0_Psiii:
.quad _Z22__device_stub__BM_costP13__hip_textureS0_Psiii
.size _Z7BM_costP13__hip_textureS0_Psiii, 8
.type _Z17energy_minimalizePiPsS0_iii,@object # @_Z17energy_minimalizePiPsS0_iii
.globl _Z17energy_minimalizePiPsS0_iii
.p2align 3, 0x0
_Z17energy_minimalizePiPsS0_iii:
.quad _Z32__device_stub__energy_minimalizePiPsS0_iii
.size _Z17energy_minimalizePiPsS0_iii, 8
.type _Z8validatePsS_iii,@object # @_Z8validatePsS_iii
.globl _Z8validatePsS_iii
.p2align 3, 0x0
_Z8validatePsS_iii:
.quad _Z23__device_stub__validatePsS_iii
.size _Z8validatePsS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_"
.size .L__unnamed_1, 48
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7BM_costP13__hip_textureS0_Psiii"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17energy_minimalizePiPsS0_iii"
.size .L__unnamed_3, 32
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z8validatePsS_iii"
.size .L__unnamed_4, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
.addrsig_sym _Z22__device_stub__BM_costP13__hip_textureS0_Psiii
.addrsig_sym _Z32__device_stub__energy_minimalizePiPsS0_iii
.addrsig_sym _Z23__device_stub__validatePsS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.addrsig_sym _Z7BM_costP13__hip_textureS0_Psiii
.addrsig_sym _Z17energy_minimalizePiPsS0_iii
.addrsig_sym _Z8validatePsS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000317d5_00000000-6_sgm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_
.type _Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_, @function
_Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_:
.LFB2051:
.cfi_startproc
endbr64
subq $216, %rsp
.cfi_def_cfa_offset 224
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movl %edx, 36(%rsp)
movl %ecx, 32(%rsp)
movl %r8d, 28(%rsp)
movl %r9d, 24(%rsp)
movq 224(%rsp), %rax
movq %rax, 16(%rsp)
movq 240(%rsp), %rax
movq %rax, 8(%rsp)
movq 248(%rsp), %rax
movq %rax, (%rsp)
movq %fs:40, %rax
movq %rax, 200(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 16(%rsp), %rax
movq %rax, 160(%rsp)
leaq 232(%rsp), %rax
movq %rax, 168(%rsp)
leaq 8(%rsp), %rax
movq %rax, 176(%rsp)
movq %rsp, %rax
movq %rax, 184(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 200(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $216, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 232
pushq 56(%rsp)
.cfi_def_cfa_offset 240
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z14path_aggregateiiiiiiPiyPsS0_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 224
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_, .-_Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_
.globl _Z14path_aggregateiiiiiiPiyPsS0_
.type _Z14path_aggregateiiiiiiPiyPsS0_, @function
_Z14path_aggregateiiiiiiPiyPsS0_:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
pushq 40(%rsp)
.cfi_def_cfa_offset 24
pushq 40(%rsp)
.cfi_def_cfa_offset 32
pushq 40(%rsp)
.cfi_def_cfa_offset 40
pushq 40(%rsp)
.cfi_def_cfa_offset 48
call _Z46__device_stub__Z14path_aggregateiiiiiiPiyPsS0_iiiiiiPiyPsS0_
addq $40, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z14path_aggregateiiiiiiPiyPsS0_, .-_Z14path_aggregateiiiiiiPiyPsS0_
.globl _Z31__device_stub__Z7BM_costyyPsiiiyyPsiii
.type _Z31__device_stub__Z7BM_costyyPsiiiyyPsiii, @function
_Z31__device_stub__Z7BM_costyyPsiiiyyPsiii:
.LFB2053:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z7BM_costyyPsiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z31__device_stub__Z7BM_costyyPsiiiyyPsiii, .-_Z31__device_stub__Z7BM_costyyPsiiiyyPsiii
.globl _Z7BM_costyyPsiii
.type _Z7BM_costyyPsiii, @function
_Z7BM_costyyPsiii:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z7BM_costyyPsiiiyyPsiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z7BM_costyyPsiii, .-_Z7BM_costyyPsiii
.globl _Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii
.type _Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii, @function
_Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii:
.LFB2055:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z17energy_minimalizePiPsS0_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2055:
.size _Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii, .-_Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii
.globl _Z17energy_minimalizePiPsS0_iii
.type _Z17energy_minimalizePiPsS0_iii, @function
_Z17energy_minimalizePiPsS0_iii:
.LFB2056:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z17energy_minimalizePiPsS0_iiiPiPsS0_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _Z17energy_minimalizePiPsS0_iii, .-_Z17energy_minimalizePiPsS0_iii
.globl _Z32__device_stub__Z8validatePsS_iiiPsS_iii
.type _Z32__device_stub__Z8validatePsS_iiiPsS_iii, @function
_Z32__device_stub__Z8validatePsS_iiiPsS_iii:
.LFB2057:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8validatePsS_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z32__device_stub__Z8validatePsS_iiiPsS_iii, .-_Z32__device_stub__Z8validatePsS_iiiPsS_iii
.globl _Z8validatePsS_iii
.type _Z8validatePsS_iii, @function
_Z8validatePsS_iii:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z8validatePsS_iiiPsS_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8validatePsS_iii, .-_Z8validatePsS_iii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8validatePsS_iii"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "_Z17energy_minimalizePiPsS0_iii"
.section .rodata.str1.1
.LC2:
.string "_Z7BM_costyyPsiii"
.section .rodata.str1.8
.align 8
.LC3:
.string "_Z14path_aggregateiiiiiiPiyPsS0_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8validatePsS_iii(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z17energy_minimalizePiPsS0_iii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z7BM_costyyPsiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14path_aggregateiiiiiiPiyPsS0_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sgm.hip"
.globl _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_ # -- Begin function _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
.p2align 4, 0x90
.type _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_,@function
_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_: # @_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movl %edx, 20(%rsp)
movl %ecx, 16(%rsp)
movl %r8d, 12(%rsp)
movl %r9d, 8(%rsp)
leaq 28(%rsp), %rax
movq %rax, 80(%rsp)
leaq 24(%rsp), %rax
movq %rax, 88(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 176(%rsp), %rax
movq %rax, 128(%rsp)
leaq 184(%rsp), %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_, .Lfunc_end0-_Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
.cfi_endproc
# -- End function
.globl _Z22__device_stub__BM_costP13__hip_textureS0_Psiii # -- Begin function _Z22__device_stub__BM_costP13__hip_textureS0_Psiii
.p2align 4, 0x90
.type _Z22__device_stub__BM_costP13__hip_textureS0_Psiii,@function
_Z22__device_stub__BM_costP13__hip_textureS0_Psiii: # @_Z22__device_stub__BM_costP13__hip_textureS0_Psiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z7BM_costP13__hip_textureS0_Psiii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z22__device_stub__BM_costP13__hip_textureS0_Psiii, .Lfunc_end1-_Z22__device_stub__BM_costP13__hip_textureS0_Psiii
.cfi_endproc
# -- End function
.globl _Z32__device_stub__energy_minimalizePiPsS0_iii # -- Begin function _Z32__device_stub__energy_minimalizePiPsS0_iii
.p2align 4, 0x90
.type _Z32__device_stub__energy_minimalizePiPsS0_iii,@function
_Z32__device_stub__energy_minimalizePiPsS0_iii: # @_Z32__device_stub__energy_minimalizePiPsS0_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z17energy_minimalizePiPsS0_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z32__device_stub__energy_minimalizePiPsS0_iii, .Lfunc_end2-_Z32__device_stub__energy_minimalizePiPsS0_iii
.cfi_endproc
# -- End function
.globl _Z23__device_stub__validatePsS_iii # -- Begin function _Z23__device_stub__validatePsS_iii
.p2align 4, 0x90
.type _Z23__device_stub__validatePsS_iii,@function
_Z23__device_stub__validatePsS_iii: # @_Z23__device_stub__validatePsS_iii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8validatePsS_iii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z23__device_stub__validatePsS_iii, .Lfunc_end3-_Z23__device_stub__validatePsS_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7BM_costP13__hip_textureS0_Psiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17energy_minimalizePiPsS0_iii, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8validatePsS_iii, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_,@object # @_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.section .rodata,"a",@progbits
.globl _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.p2align 3, 0x0
_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_:
.quad _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
.size _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_, 8
.type _Z7BM_costP13__hip_textureS0_Psiii,@object # @_Z7BM_costP13__hip_textureS0_Psiii
.globl _Z7BM_costP13__hip_textureS0_Psiii
.p2align 3, 0x0
_Z7BM_costP13__hip_textureS0_Psiii:
.quad _Z22__device_stub__BM_costP13__hip_textureS0_Psiii
.size _Z7BM_costP13__hip_textureS0_Psiii, 8
.type _Z17energy_minimalizePiPsS0_iii,@object # @_Z17energy_minimalizePiPsS0_iii
.globl _Z17energy_minimalizePiPsS0_iii
.p2align 3, 0x0
_Z17energy_minimalizePiPsS0_iii:
.quad _Z32__device_stub__energy_minimalizePiPsS0_iii
.size _Z17energy_minimalizePiPsS0_iii, 8
.type _Z8validatePsS_iii,@object # @_Z8validatePsS_iii
.globl _Z8validatePsS_iii
.p2align 3, 0x0
_Z8validatePsS_iii:
.quad _Z23__device_stub__validatePsS_iii
.size _Z8validatePsS_iii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_"
.size .L__unnamed_1, 48
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z7BM_costP13__hip_textureS0_Psiii"
.size .L__unnamed_2, 35
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z17energy_minimalizePiPsS0_iii"
.size .L__unnamed_3, 32
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z8validatePsS_iii"
.size .L__unnamed_4, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__path_aggregateiiiiiiPiP13__hip_texturePsS2_
.addrsig_sym _Z22__device_stub__BM_costP13__hip_textureS0_Psiii
.addrsig_sym _Z32__device_stub__energy_minimalizePiPsS0_iii
.addrsig_sym _Z23__device_stub__validatePsS_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14path_aggregateiiiiiiPiP13__hip_texturePsS2_
.addrsig_sym _Z7BM_costP13__hip_textureS0_Psiii
.addrsig_sym _Z17energy_minimalizePiPsS0_iii
.addrsig_sym _Z8validatePsS_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <list>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/copy.h>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <cassert>
#define ITERATIONS 25
#ifndef DATA_TYPE
#define DATA_TYPE float
#endif
using namespace std;
int main(int argc, char ** argv){
long total_time = 0;
struct timespec start, stop;
list<DATA_TYPE> int_list;
unsigned long N = 32000;
if(argc > 1){
N = atol(argv[1]);
}
for(int i = 0; i < ITERATIONS; i++){
for(int c = N; c > 0; c--){
int_list.push_back((DATA_TYPE)(rand() % 500000));
}
std::list<DATA_TYPE>::iterator __first = int_list.begin();
std::list<DATA_TYPE>::iterator __last = int_list.end();
size_t __total_size = N;
thrust::device_vector<DATA_TYPE> __device(__total_size);
clock_gettime(CLOCK_REALTIME,&start);
// Not provably continuous memory, so use iterators to copy
thrust::host_vector<DATA_TYPE> __host(__total_size);
unsigned long __idx = 0;
for(; __first != __last; ++__first){
__host[__idx] = *__first;
++__idx;
}
thrust::copy(__host.begin(),__host.end(),__device.begin());
clock_gettime(CLOCK_REALTIME,&stop);
thrust::copy(__device.begin(),__device.end(),__host.begin());
__idx = 0;
for(; __first != __last; ++__first){
*__first = __host[__idx];
++__idx;
}
total_time += ((stop.tv_sec-start.tv_sec)*1000000000) + (stop.tv_nsec - start.tv_nsec);
int_list.clear();
}
int val = 0;
for(std::list<DATA_TYPE>::iterator it = int_list.begin(), e = int_list.end(); it != e; ++it){
assert(*it >= val);
val = *it;
}
printf("%lu\n", total_time);
return 0;
} | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <list>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/copy.h>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <cassert>
#define ITERATIONS 25
#ifndef DATA_TYPE
#define DATA_TYPE float
#endif
using namespace std;
int main(int argc, char ** argv){
long total_time = 0;
struct timespec start, stop;
list<DATA_TYPE> int_list;
unsigned long N = 32000;
if(argc > 1){
N = atol(argv[1]);
}
for(int i = 0; i < ITERATIONS; i++){
for(int c = N; c > 0; c--){
int_list.push_back((DATA_TYPE)(rand() % 500000));
}
std::list<DATA_TYPE>::iterator __first = int_list.begin();
std::list<DATA_TYPE>::iterator __last = int_list.end();
size_t __total_size = N;
thrust::device_vector<DATA_TYPE> __device(__total_size);
clock_gettime(CLOCK_REALTIME,&start);
// Not provably continuous memory, so use iterators to copy
thrust::host_vector<DATA_TYPE> __host(__total_size);
unsigned long __idx = 0;
for(; __first != __last; ++__first){
__host[__idx] = *__first;
++__idx;
}
thrust::copy(__host.begin(),__host.end(),__device.begin());
clock_gettime(CLOCK_REALTIME,&stop);
thrust::copy(__device.begin(),__device.end(),__host.begin());
__idx = 0;
for(; __first != __last; ++__first){
*__first = __host[__idx];
++__idx;
}
total_time += ((stop.tv_sec-start.tv_sec)*1000000000) + (stop.tv_nsec - start.tv_nsec);
int_list.clear();
}
int val = 0;
for(std::list<DATA_TYPE>::iterator it = int_list.begin(), e = int_list.end(); it != e; ++it){
assert(*it >= val);
val = *it;
}
printf("%lu\n", total_time);
return 0;
} | #include <hip/hip_runtime.h>
#include <list>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/copy.h>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <cassert>
#define ITERATIONS 25
#ifndef DATA_TYPE
#define DATA_TYPE float
#endif
using namespace std;
int main(int argc, char ** argv){
long total_time = 0;
struct timespec start, stop;
list<DATA_TYPE> int_list;
unsigned long N = 32000;
if(argc > 1){
N = atol(argv[1]);
}
for(int i = 0; i < ITERATIONS; i++){
for(int c = N; c > 0; c--){
int_list.push_back((DATA_TYPE)(rand() % 500000));
}
std::list<DATA_TYPE>::iterator __first = int_list.begin();
std::list<DATA_TYPE>::iterator __last = int_list.end();
size_t __total_size = N;
thrust::device_vector<DATA_TYPE> __device(__total_size);
clock_gettime(CLOCK_REALTIME,&start);
// Not provably continuous memory, so use iterators to copy
thrust::host_vector<DATA_TYPE> __host(__total_size);
unsigned long __idx = 0;
for(; __first != __last; ++__first){
__host[__idx] = *__first;
++__idx;
}
thrust::copy(__host.begin(),__host.end(),__device.begin());
clock_gettime(CLOCK_REALTIME,&stop);
thrust::copy(__device.begin(),__device.end(),__host.begin());
__idx = 0;
for(; __first != __last; ++__first){
*__first = __host[__idx];
++__idx;
}
total_time += ((stop.tv_sec-start.tv_sec)*1000000000) + (stop.tv_nsec - start.tv_nsec);
int_list.clear();
}
int val = 0;
for(std::list<DATA_TYPE>::iterator it = int_list.begin(), e = int_list.end(); it != e; ++it){
assert(*it >= val);
val = *it;
}
printf("%lu\n", total_time);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <list>
#include <thrust/device_vector.h>
#include <thrust/host_vector.h>
#include <thrust/copy.h>
#include <cstdlib>
#include <cstdio>
#include <time.h>
#include <cassert>
#define ITERATIONS 25
#ifndef DATA_TYPE
#define DATA_TYPE float
#endif
using namespace std;
int main(int argc, char ** argv){
long total_time = 0;
struct timespec start, stop;
list<DATA_TYPE> int_list;
unsigned long N = 32000;
if(argc > 1){
N = atol(argv[1]);
}
for(int i = 0; i < ITERATIONS; i++){
for(int c = N; c > 0; c--){
int_list.push_back((DATA_TYPE)(rand() % 500000));
}
std::list<DATA_TYPE>::iterator __first = int_list.begin();
std::list<DATA_TYPE>::iterator __last = int_list.end();
size_t __total_size = N;
thrust::device_vector<DATA_TYPE> __device(__total_size);
clock_gettime(CLOCK_REALTIME,&start);
// Not provably continuous memory, so use iterators to copy
thrust::host_vector<DATA_TYPE> __host(__total_size);
unsigned long __idx = 0;
for(; __first != __last; ++__first){
__host[__idx] = *__first;
++__idx;
}
thrust::copy(__host.begin(),__host.end(),__device.begin());
clock_gettime(CLOCK_REALTIME,&stop);
thrust::copy(__device.begin(),__device.end(),__host.begin());
__idx = 0;
for(; __first != __last; ++__first){
*__first = __host[__idx];
++__idx;
}
total_time += ((stop.tv_sec-start.tv_sec)*1000000000) + (stop.tv_nsec - start.tv_nsec);
int_list.clear();
}
int val = 0;
for(std::list<DATA_TYPE>::iterator it = int_list.begin(), e = int_list.end(); it != e; ++it){
assert(*it >= val);
val = *it;
}
printf("%lu\n", total_time);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _ZN3cub17CUB_200700_800_NS6detail8for_each13static_kernelINS2_12policy_hub_t12policy_350_tEmN6thrust20THRUST_200700_800_NS8cuda_cub20__uninitialized_fill7functorINS7_10device_ptrIfEEfEEEEvT0_T1_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.WIDE.U32 R2, R2, 0x200, RZ ; /* 0x0000020002027825 */
/* 0x001fca00078e00ff */
/*0050*/ IADD3 R4, P1, -R2.reuse, c[0x0][0x160], RZ ; /* 0x0000580002047a10 */
/* 0x040fe40007f3e1ff */
/*0060*/ IADD3 R0, P2, R2, R5, RZ ; /* 0x0000000502007210 */
/* 0x002fe40007f5e0ff */
/*0070*/ ISETP.GT.U32.AND P0, PT, R4, 0x1ff, PT ; /* 0x000001ff0400780c */
/* 0x000fe40003f04070 */
/*0080*/ IADD3.X R6, ~R3, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590003067a10 */
/* 0x000fe20000ffe5ff */
/*0090*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe200010e0603 */
/*00a0*/ LEA R2, P1, R0, c[0x0][0x168], 0x2 ; /* 0x00005a0000027a11 */
/* 0x000fe400078210ff */
/*00b0*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fc40003f04100 */
/*00c0*/ LEA.HI.X R3, R0, c[0x0][0x16c], R3, 0x2, P1 ; /* 0x00005b0000037a11 */
/* 0x000fd600008f1403 */
/*00d0*/ @P0 BRA 0x1a0 ; /* 0x000000c000000947 */
/* 0x000fea0003800000 */
/*00e0*/ ISETP.GT.U32.AND P0, PT, R4, R5, PT ; /* 0x000000050400720c */
/* 0x000fe40003f04070 */
/*00f0*/ SHF.R.S32.HI R6, RZ, 0x1f, R4 ; /* 0x0000001fff067819 */
/* 0x000fe40000011404 */
/*0100*/ IADD3 R0, R5, 0x100, RZ ; /* 0x0000010005007810 */
/* 0x000fe40007ffe0ff */
/*0110*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0120*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff070624 */
/* 0x000fca00078e00ff */
/*0130*/ @P0 STG.E [R2.64], R7 ; /* 0x0000000702000986 */
/* 0x0001e2000c101904 */
/*0140*/ ISETP.GT.U32.AND P0, PT, R4, R0, PT ; /* 0x000000000400720c */
/* 0x000fc80003f04070 */
/*0150*/ ISETP.GT.U32.AND.EX P0, PT, R6, RZ, PT, P0 ; /* 0x000000ff0600720c */
/* 0x000fda0003f04100 */
/*0160*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x001fca00078e00ff */
/*0180*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff057624 */
/* 0x000fca00078e00ff */
/*01b0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*01c0*/ STG.E [R2.64+0x400], R5 ; /* 0x0004000502007986 */
/* 0x000fe2000c101904 */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _ZN3cub17CUB_200700_800_NS11EmptyKernelIvEEvv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0020*/ BRA 0x20; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0080*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.protected _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.globl _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.p2align 8
.type _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,@function
_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_:
s_load_b128 s[4:7], s[0:1], 0x10
s_lshl_b32 s2, s15, 8
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s6
s_addc_u32 s3, 0, s7
s_sub_u32 s4, s4, s2
s_subb_u32 s5, s5, s3
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u64_e64 s5, 0x100, s[4:5]
s_and_b32 s5, s5, exec_lo
s_cselect_b32 s4, s4, 0x100
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_cmp_gt_u32_e32 vcc_lo, s4, v0
s_cmpk_eq_i32 s4, 0x100
s_cselect_b32 s4, -1, 0
s_or_b32 s4, s4, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s4
s_cbranch_execz .LBB0_2
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x0
s_load_b32 s6, s[0:1], 0x8
v_lshlrev_b32_e32 v0, 2, v0
s_lshl_b64 s[0:1], s[2:3], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s4, s0
s_addc_u32 s1, s5, s1
v_add_co_u32 v0, s0, s0, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v1, null, s1, 0, s0
v_mov_b32_e32 v2, s6
flat_store_b32 v[0:1], v2
.LBB0_2:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,"axG",@progbits,_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_,comdat
.Lfunc_end0:
.size _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_, .Lfunc_end0-_ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 16
.value_kind: by_value
- .offset: 16
.size: 8
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 256
.name: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _ZN6thrust11hip_rocprim14__parallel_for6kernelILj256ENS0_20__uninitialized_fill7functorINS_10device_ptrIfEEfEEmLj1EEEvT0_T1_S9_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /*==========================================================
* patch2hank.cu
*
* making block hankel matrix
*
* compile command
* nvcc('patch2hank_single.cu -arch sm_35')
*
* This is a MEX-file for MATLAB.
*
*========================================================*/
/* $created: 11-Mar-2015 $ */
// #define fmin(a,b) ((a) < (b) ? (a) : (b))
// #define fmax(a,b) ((a) > (b) ? (a) : (b))
// #include "mex.h"
// #include "cuda.h"
__global__ void patch2hank_single(float* out,float* y,int sy,int sx,int sz,int firy, int firx)
{
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int um=sy-firy+1;
int un=firy;
int ii=0,jj=0,zz=0,di=0,dj=0,ri=0,rj=0,pi=0,pj=0,k=0;
if ( idx < (sy-firy+1)*(sx-firx+1)*firy*firx*sz )
{
zz=(int)(idx/((sy-firy+1)*(sx-firx+1)*firy*firx));
k=idx%((sy-firy+1)*(sx-firx+1)*firy*firx);
ii=k%((sy-firy+1)*(sx-firx+1));
jj=(int)(k/((sy-firy+1)*(sx-firx+1)));
di=ii/um;
dj=jj/un;
ri=ii%um;
rj=jj%un;
pi= ri+rj;
pj= di+dj;
out[ii + jj*((sy-firy+1)*(sx-firx+1)) + zz*((sy-firy+1)*(sx-firx+1)*firy*firx)]=y[pi+pj*sy+zz*sy*sx];
}
} | code for sm_80
Function : _Z17patch2hank_singlePfS_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0060*/ ULDC UR5, c[0x0][0x180] ; /* 0x0000600000057ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIADD3 UR4, UR4, 0x1, -UR5 ; /* 0x0000000104047890 */
/* 0x000fe2000fffe805 */
/*0080*/ IADD3 R3, R3, 0x1, -R0 ; /* 0x0000000103037810 */
/* 0x000fe20007ffe800 */
/*0090*/ ULDC UR6, c[0x0][0x17c] ; /* 0x00005f0000067ab9 */
/* 0x000fe40000000800 */
/*00a0*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x000fc4000f8e023f */
/*00b0*/ IMAD R0, R3, UR4, RZ ; /* 0x0000000403007c24 */
/* 0x000fc8000f8e02ff */
/*00c0*/ IMAD R2, R0, UR5, RZ ; /* 0x0000000500027c24 */
/* 0x000fe4000f8e02ff */
/*00d0*/ IMAD R11, R4, c[0x0][0x0], R11 ; /* 0x00000000040b7a24 */
/* 0x001fe400078e020b */
/*00e0*/ IMAD R4, R2, c[0x0][0x178], RZ ; /* 0x00005e0002047a24 */
/* 0x000fca00078e02ff */
/*00f0*/ ISETP.GE.AND P0, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x000fda0003f06270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ IABS R9, R2.reuse ; /* 0x0000000200097213 */
/* 0x080fe20000000000 */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IABS R10, R2 ; /* 0x00000002000a7213 */
/* 0x000fe40000000000 */
/*0140*/ I2F.RP R6, R9 ; /* 0x0000000900067306 */
/* 0x000e220000209400 */
/*0150*/ IABS R14, R3.reuse ; /* 0x00000003000e7213 */
/* 0x080fe40000000000 */
/*0160*/ IABS R16, R3 ; /* 0x0000000300107213 */
/* 0x000fca0000000000 */
/*0170*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0180*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0190*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*01b0*/ IADD3 R8, RZ, -R5, RZ ; /* 0x80000005ff087210 */
/* 0x002fca0007ffe0ff */
/*01c0*/ IMAD R7, R8, R9, RZ ; /* 0x0000000908077224 */
/* 0x000fe200078e02ff */
/*01d0*/ IABS R8, R11 ; /* 0x0000000b00087213 */
/* 0x000fc60000000000 */
/*01e0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*01f0*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fc60000000000 */
/*0200*/ IMAD.MOV R4, RZ, RZ, -R10 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0a0a */
/*0210*/ I2F.RP R6, R7 ; /* 0x0000000700067306 */
/* 0x000e220000209400 */
/*0220*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD R4, R5, R4, R8 ; /* 0x0000000405047224 */
/* 0x000fca00078e0208 */
/*0240*/ ISETP.GT.U32.AND P1, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fe20003f24070 */
/*0250*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e180000001000 */
/*0260*/ @!P1 IMAD.IADD R4, R4, 0x1, -R9 ; /* 0x0000000104049824 */
/* 0x000fe200078e0a09 */
/*0270*/ @!P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105059810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f25270 */
/*0290*/ ISETP.GE.U32.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fe40003f06070 */
/*02a0*/ LOP3.LUT R4, R11, R2, RZ, 0x3c, !PT ; /* 0x000000020b047212 */
/* 0x000fe400078e3cff */
/*02b0*/ IADD3 R8, R6, 0xffffffe, RZ ; /* 0x0ffffffe06087810 */
/* 0x001fe40007ffe0ff */
/*02c0*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc40003f46270 */
/*02d0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000062000021f000 */
/*02e0*/ IABS R4, c[0x0][0x17c] ; /* 0x00005f0000047a13 */
/* 0x000fc80000000000 */
/*02f0*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fc60007ffe0ff */
/*0300*/ I2F.RP R13, R4 ; /* 0x00000004000d7306 */
/* 0x000ea20000209400 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0320*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*0330*/ @!P1 LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff059212 */
/* 0x000fe200078e33ff */
/*0340*/ IMAD.MOV R10, RZ, RZ, -R9 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a09 */
/*0350*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0a05 */
/*0360*/ IMAD R15, R10, R7, RZ ; /* 0x000000070a0f7224 */
/* 0x000fe400078e02ff */
/*0370*/ IMAD R11, R2, R6, R11 ; /* 0x00000006020b7224 */
/* 0x000fe200078e020b */
/*0380*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fe20000000000 */
/*0390*/ IMAD.HI.U32 R8, R9, R15, R8 ; /* 0x0000000f09087227 */
/* 0x000fe200078e0008 */
/*03a0*/ MUFU.RCP R13, R13 ; /* 0x0000000d000d7308 */
/* 0x004e240000001000 */
/*03b0*/ IABS R10, R11 ; /* 0x0000000b000a7213 */
/* 0x000fe40000000000 */
/*03c0*/ IADD3 R12, RZ, -R6, RZ ; /* 0x80000006ff0c7210 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fc400078e000e */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, R10 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000a */
/*03f0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*0400*/ I2F.RP R14, R6 ; /* 0x00000006000e7306 */
/* 0x000e620000209400 */
/*0410*/ IMAD.HI.U32 R8, R8, R9, RZ ; /* 0x0000000908087227 */
/* 0x000fc800078e00ff */
/*0420*/ IMAD R10, R8, R10, R9 ; /* 0x0000000a080a7224 */
/* 0x000fe200078e0209 */
/*0430*/ IADD3 R9, R13, 0xffffffe, RZ ; /* 0x0ffffffe0d097810 */
/* 0x001fc80007ffe0ff */
/*0440*/ ISETP.GT.U32.AND P1, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x000fe40003f24070 */
/*0450*/ F2I.FTZ.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000021f000 */
/*0460*/ MUFU.RCP R14, R14 ; /* 0x0000000e000e7308 */
/* 0x002e660000001000 */
/*0470*/ @!P1 IADD3 R10, R10, -R7, RZ ; /* 0x800000070a0a9210 */
/* 0x000fc40007ffe0ff */
/*0480*/ @!P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108089810 */
/* 0x000fe40007ffe0ff */
/*0490*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fe20003f06070 */
/*04a0*/ IMAD.MOV R15, RZ, RZ, -R9 ; /* 0x000000ffff0f7224 */
/* 0x001fe200078e0a09 */
/*04b0*/ LOP3.LUT R7, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b077212 */
/* 0x000fe400078e3cff */
/*04c0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*04d0*/ IMAD R15, R15, R4, RZ ; /* 0x000000040f0f7224 */
/* 0x000fe200078e02ff */
/*04e0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f46270 */
/*04f0*/ IADD3 R12, R14, 0xffffffe, RZ ; /* 0x0ffffffe0e0c7810 */
/* 0x002fca0007ffe0ff */
/*0500*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fe20007ffe0ff */
/*0510*/ F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; /* 0x0000000c000d7305 */
/* 0x000e28000021f000 */
/*0520*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0008 */
/*0530*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0540*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0550*/ @!P1 LOP3.LUT R7, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff079212 */
/* 0x000fe200078e33ff */
/*0560*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */
/* 0x000fc600078e0008 */
/*0570*/ IABS R14, R7 ; /* 0x00000007000e7213 */
/* 0x000fe20000000000 */
/*0580*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a07 */
/*0590*/ IADD3 R17, RZ, -R13, RZ ; /* 0x8000000dff117210 */
/* 0x001fe20007ffe0ff */
/*05a0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e00ff */
/*05b0*/ IMAD R8, R0, R10, R11 ; /* 0x0000000a00087224 */
/* 0x000fe400078e020b */
/*05c0*/ IMAD R11, R17, R6, RZ ; /* 0x00000006110b7224 */
/* 0x000fe400078e02ff */
/*05d0*/ IMAD.HI.U32 R10, R9, R14, RZ ; /* 0x0000000e090a7227 */
/* 0x000fe200078e00ff */
/*05e0*/ IABS R15, R8 ; /* 0x00000008000f7213 */
/* 0x000fc60000000000 */
/*05f0*/ IMAD.HI.U32 R12, R13, R11, R12 ; /* 0x0000000b0d0c7227 */
/* 0x000fe200078e000c */
/*0600*/ IADD3 R13, RZ, -R16, RZ ; /* 0x80000010ff0d7210 */
/* 0x000fc60007ffe0ff */
/*0610*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000f */
/*0620*/ IMAD.MOV R11, RZ, RZ, -R10 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0a0a */
/*0630*/ IMAD.HI.U32 R12, R12, R9, RZ ; /* 0x000000090c0c7227 */
/* 0x000fc800078e00ff */
/*0640*/ IMAD R11, R4, R11, R14 ; /* 0x0000000b040b7224 */
/* 0x000fe400078e020e */
/*0650*/ IMAD R9, R12, R13, R9 ; /* 0x0000000d0c097224 */
/* 0x000fc600078e0209 */
/*0660*/ ISETP.GT.U32.AND P5, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x000fe40003fa4070 */
/*0670*/ ISETP.GT.U32.AND P4, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fd60003f84070 */
/*0680*/ @!P5 IMAD.IADD R11, R11, 0x1, -R4 ; /* 0x000000010b0bd824 */
/* 0x000fe200078e0a04 */
/*0690*/ @!P5 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0ad810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ @!P4 IADD3 R9, R9, -R6, RZ ; /* 0x800000060909c210 */
/* 0x000fe40007ffe0ff */
/*06b0*/ ISETP.GE.U32.AND P0, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x000fe40003f06070 */
/*06c0*/ ISETP.GE.U32.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe40003f26070 */
/*06d0*/ LOP3.LUT R6, R7, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0007067a12 */
/* 0x000fe400078e3cff */
/*06e0*/ LOP3.LUT R4, R8, R3, RZ, 0x3c, !PT ; /* 0x0000000308047212 */
/* 0x000fc400078e3cff */
/*06f0*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f46270 */
/*0700*/ ISETP.GE.AND P3, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f66270 */
/*0710*/ @!P4 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0cc810 */
/* 0x000fe40007ffe0ff */
/*0720*/ ISETP.NE.AND P4, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f85270 */
/*0730*/ ISETP.NE.AND P5, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003fa5270 */
/*0740*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fc40007ffe0ff */
/*0750*/ @P1 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c1810 */
/* 0x000fc60007ffe0ff */
/*0760*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe400078e0a0a */
/*0770*/ @!P3 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0cb224 */
/* 0x000fe400078e0a0c */
/*0780*/ @!P4 LOP3.LUT R12, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff0cc212 */
/* 0x000fe400078e33ff */
/*0790*/ @!P5 LOP3.LUT R10, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff0ada12 */
/* 0x000fc600078e33ff */
/*07a0*/ IMAD.MOV R6, RZ, RZ, -R12.reuse ; /* 0x000000ffff067224 */
/* 0x100fe200078e0a0c */
/*07b0*/ IADD3 R4, -R10, RZ, RZ ; /* 0x000000ff0a047210 */
/* 0x000fe20007ffe1ff */
/*07c0*/ IMAD R9, R5, c[0x0][0x174], R12 ; /* 0x00005d0005097a24 */
/* 0x000fe400078e020c */
/*07d0*/ IMAD R3, R3, R6, R8 ; /* 0x0000000603037224 */
/* 0x000fe400078e0208 */
/*07e0*/ IMAD R4, R4, c[0x0][0x17c], R7 ; /* 0x00005f0004047a24 */
/* 0x000fe400078e0207 */
/*07f0*/ IMAD.IADD R9, R10, 0x1, R9 ; /* 0x000000010a097824 */
/* 0x000fc600078e0209 */
/*0800*/ IADD3 R4, R3, R4, RZ ; /* 0x0000000403047210 */
/* 0x000fe20007ffe0ff */
/*0810*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0820*/ IMAD R4, R9, c[0x0][0x170], R4 ; /* 0x00005c0009047a24 */
/* 0x000fc800078e0204 */
/*0830*/ IMAD.WIDE R10, R4, R3, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fcc00078e0203 */
/*0840*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*0850*/ IMAD R2, R2, R5, R8 ; /* 0x0000000502027224 */
/* 0x000fc800078e0208 */
/*0860*/ IMAD R2, R0, R7, R2 ; /* 0x0000000700027224 */
/* 0x000fc800078e0202 */
/*0870*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0880*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x004fe2000c101904 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*==========================================================
* patch2hank.cu
*
* making block hankel matrix
*
* compile command
* nvcc('patch2hank_single.cu -arch sm_35')
*
* This is a MEX-file for MATLAB.
*
*========================================================*/
/* $created: 11-Mar-2015 $ */
// #define fmin(a,b) ((a) < (b) ? (a) : (b))
// #define fmax(a,b) ((a) > (b) ? (a) : (b))
// #include "mex.h"
// #include "cuda.h"
__global__ void patch2hank_single(float* out,float* y,int sy,int sx,int sz,int firy, int firx)
{
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int um=sy-firy+1;
int un=firy;
int ii=0,jj=0,zz=0,di=0,dj=0,ri=0,rj=0,pi=0,pj=0,k=0;
if ( idx < (sy-firy+1)*(sx-firx+1)*firy*firx*sz )
{
zz=(int)(idx/((sy-firy+1)*(sx-firx+1)*firy*firx));
k=idx%((sy-firy+1)*(sx-firx+1)*firy*firx);
ii=k%((sy-firy+1)*(sx-firx+1));
jj=(int)(k/((sy-firy+1)*(sx-firx+1)));
di=ii/um;
dj=jj/un;
ri=ii%um;
rj=jj%un;
pi= ri+rj;
pj= di+dj;
out[ii + jj*((sy-firy+1)*(sx-firx+1)) + zz*((sy-firy+1)*(sx-firx+1)*firy*firx)]=y[pi+pj*sy+zz*sy*sx];
}
} | .file "tmpxft_001959e1_00000000-6_patch2hank_single.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii
.type _Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii, @function
_Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17patch2hank_singlePfS_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii, .-_Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii
.globl _Z17patch2hank_singlePfS_iiiii
.type _Z17patch2hank_singlePfS_iiiii, @function
_Z17patch2hank_singlePfS_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17patch2hank_singlePfS_iiiii, .-_Z17patch2hank_singlePfS_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17patch2hank_singlePfS_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17patch2hank_singlePfS_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*==========================================================
* patch2hank.cu
*
* making block hankel matrix
*
* compile command
* nvcc('patch2hank_single.cu -arch sm_35')
*
* This is a MEX-file for MATLAB.
*
*========================================================*/
/* $created: 11-Mar-2015 $ */
// #define fmin(a,b) ((a) < (b) ? (a) : (b))
// #define fmax(a,b) ((a) > (b) ? (a) : (b))
// #include "mex.h"
// #include "cuda.h"
__global__ void patch2hank_single(float* out,float* y,int sy,int sx,int sz,int firy, int firx)
{
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int um=sy-firy+1;
int un=firy;
int ii=0,jj=0,zz=0,di=0,dj=0,ri=0,rj=0,pi=0,pj=0,k=0;
if ( idx < (sy-firy+1)*(sx-firx+1)*firy*firx*sz )
{
zz=(int)(idx/((sy-firy+1)*(sx-firx+1)*firy*firx));
k=idx%((sy-firy+1)*(sx-firx+1)*firy*firx);
ii=k%((sy-firy+1)*(sx-firx+1));
jj=(int)(k/((sy-firy+1)*(sx-firx+1)));
di=ii/um;
dj=jj/un;
ri=ii%um;
rj=jj%un;
pi= ri+rj;
pj= di+dj;
out[ii + jj*((sy-firy+1)*(sx-firx+1)) + zz*((sy-firy+1)*(sx-firx+1)*firy*firx)]=y[pi+pj*sy+zz*sy*sx];
}
} | #include <hip/hip_runtime.h>
/*==========================================================
* patch2hank.cu
*
* making block hankel matrix
*
* compile command
* nvcc('patch2hank_single.cu -arch sm_35')
*
* This is a MEX-file for MATLAB.
*
*========================================================*/
/* $created: 11-Mar-2015 $ */
// #define fmin(a,b) ((a) < (b) ? (a) : (b))
// #define fmax(a,b) ((a) > (b) ? (a) : (b))
// #include "mex.h"
// #include "cuda.h"
__global__ void patch2hank_single(float* out,float* y,int sy,int sx,int sz,int firy, int firx)
{
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int um=sy-firy+1;
int un=firy;
int ii=0,jj=0,zz=0,di=0,dj=0,ri=0,rj=0,pi=0,pj=0,k=0;
if ( idx < (sy-firy+1)*(sx-firx+1)*firy*firx*sz )
{
zz=(int)(idx/((sy-firy+1)*(sx-firx+1)*firy*firx));
k=idx%((sy-firy+1)*(sx-firx+1)*firy*firx);
ii=k%((sy-firy+1)*(sx-firx+1));
jj=(int)(k/((sy-firy+1)*(sx-firx+1)));
di=ii/um;
dj=jj/un;
ri=ii%um;
rj=jj%un;
pi= ri+rj;
pj= di+dj;
out[ii + jj*((sy-firy+1)*(sx-firx+1)) + zz*((sy-firy+1)*(sx-firx+1)*firy*firx)]=y[pi+pj*sy+zz*sy*sx];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*==========================================================
* patch2hank.cu
*
* making block hankel matrix
*
* compile command
* nvcc('patch2hank_single.cu -arch sm_35')
*
* This is a MEX-file for MATLAB.
*
*========================================================*/
/* $created: 11-Mar-2015 $ */
// #define fmin(a,b) ((a) < (b) ? (a) : (b))
// #define fmax(a,b) ((a) > (b) ? (a) : (b))
// #include "mex.h"
// #include "cuda.h"
__global__ void patch2hank_single(float* out,float* y,int sy,int sx,int sz,int firy, int firx)
{
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int um=sy-firy+1;
int un=firy;
int ii=0,jj=0,zz=0,di=0,dj=0,ri=0,rj=0,pi=0,pj=0,k=0;
if ( idx < (sy-firy+1)*(sx-firx+1)*firy*firx*sz )
{
zz=(int)(idx/((sy-firy+1)*(sx-firx+1)*firy*firx));
k=idx%((sy-firy+1)*(sx-firx+1)*firy*firx);
ii=k%((sy-firy+1)*(sx-firx+1));
jj=(int)(k/((sy-firy+1)*(sx-firx+1)));
di=ii/um;
dj=jj/un;
ri=ii%um;
rj=jj%un;
pi= ri+rj;
pj= di+dj;
out[ii + jj*((sy-firy+1)*(sx-firx+1)) + zz*((sy-firy+1)*(sx-firx+1)*firy*firx)]=y[pi+pj*sy+zz*sy*sx];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17patch2hank_singlePfS_iiiii
.globl _Z17patch2hank_singlePfS_iiiii
.p2align 8
.type _Z17patch2hank_singlePfS_iiiii,@function
_Z17patch2hank_singlePfS_iiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_sub_i32 s3, s4, s7
s_sub_i32 s9, s5, s8
s_add_i32 s3, s3, 1
s_add_i32 s9, s9, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s3, s9
s_mul_i32 s8, s8, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s8, s2
s_mul_i32 s6, s8, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s6, s8, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s9, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s9, s9, s6
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s9
s_sub_i32 s10, 0, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s6, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s10, v0
s_ashr_i32 s10, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s2, s10
s_xor_b32 s11, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_sub_i32 s6, 0, s11
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s9
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s9, v2
v_cmp_le_u32_e32 vcc_lo, s9, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_cvt_f32_u32_e32 v5, s11
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s9, v2
v_rcp_iflag_f32_e32 v2, v5
s_ashr_i32 s9, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s3, s9
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_xor_b32 s12, s12, s9
v_cvt_f32_u32_e32 v8, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_sub_nc_u32_e32 v0, v0, v3
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v0, s8
v_mul_lo_u32 v4, s6, v2
s_ashr_i32 s6, s7, 31
v_mul_lo_u32 v0, v0, s5
s_add_i32 s8, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
s_xor_b32 s8, s8, s6
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v2, v4
v_ashrrev_i32_e32 v5, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v6, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v6, v5
v_xor_b32_e32 v5, s10, v5
s_sub_i32 s10, 0, s8
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v2, s11
v_sub_nc_u32_e32 v4, v4, v6
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s11, v4
v_cmp_le_u32_e32 vcc_lo, s11, v4
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_cvt_f32_u32_e32 v6, s8
v_add_nc_u32_e32 v7, 1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s11, v4
v_rcp_iflag_f32_e32 v6, v6
v_rcp_iflag_f32_e32 v4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
v_xor_b32_e32 v2, v2, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x4f7ffffe, v6
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_sub_nc_u32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v5, v6
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v6, v2, s2
v_mul_lo_u32 v7, s10, v5
s_sub_i32 s2, 0, s12
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v8, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v9, v1, v6
v_ashrrev_i32_e32 v1, 31, v2
v_mul_hi_u32 v7, v5, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v8, v4, v8
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v11, v2, v1
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v7, v11, v1
v_add_nc_u32_e32 v12, v9, v10
v_add_nc_u32_e32 v4, v4, v8
v_xor_b32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v5, v7, v5
v_xor_b32_e32 v8, v12, v10
v_xor_b32_e32 v10, s9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v4, v8, v4
v_mul_lo_u32 v11, v5, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v12, v4, s12
v_sub_nc_u32_e32 v7, v7, v11
v_add_nc_u32_e32 v11, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s8, v7
v_sub_nc_u32_e32 v8, v8, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v5, v5, v11 :: v_dual_add_nc_u32 v12, 1, v4
v_subrev_nc_u32_e32 v11, s8, v7
v_subrev_nc_u32_e32 v13, s12, v8
v_cmp_le_u32_e64 s2, s12, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v7, v11, vcc_lo
v_add_nc_u32_e32 v11, 1, v5
v_cndmask_b32_e64 v4, v4, v12, s2
v_cndmask_b32_e64 v8, v8, v13, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s8, v7
v_dual_cndmask_b32 v5, v5, v11 :: v_dual_add_nc_u32 v12, 1, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s12, v8
v_xor_b32_e32 v5, v5, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v12, vcc_lo
v_sub_nc_u32_e32 v1, v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v10
v_mul_lo_u32 v5, v1, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v10
v_mul_lo_u32 v7, v4, s3
v_add3_u32 v0, v4, v0, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v2, v5
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v0, v0, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v9, v7
v_add3_u32 v0, v1, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
v_add3_u32 v0, v9, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17patch2hank_singlePfS_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17patch2hank_singlePfS_iiiii, .Lfunc_end0-_Z17patch2hank_singlePfS_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17patch2hank_singlePfS_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17patch2hank_singlePfS_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*==========================================================
* patch2hank.cu
*
* making block hankel matrix
*
* compile command
* nvcc('patch2hank_single.cu -arch sm_35')
*
* This is a MEX-file for MATLAB.
*
*========================================================*/
/* $created: 11-Mar-2015 $ */
// #define fmin(a,b) ((a) < (b) ? (a) : (b))
// #define fmax(a,b) ((a) > (b) ? (a) : (b))
// #include "mex.h"
// #include "cuda.h"
__global__ void patch2hank_single(float* out,float* y,int sy,int sx,int sz,int firy, int firx)
{
int idx = threadIdx.x+blockIdx.x*blockDim.x;
int um=sy-firy+1;
int un=firy;
int ii=0,jj=0,zz=0,di=0,dj=0,ri=0,rj=0,pi=0,pj=0,k=0;
if ( idx < (sy-firy+1)*(sx-firx+1)*firy*firx*sz )
{
zz=(int)(idx/((sy-firy+1)*(sx-firx+1)*firy*firx));
k=idx%((sy-firy+1)*(sx-firx+1)*firy*firx);
ii=k%((sy-firy+1)*(sx-firx+1));
jj=(int)(k/((sy-firy+1)*(sx-firx+1)));
di=ii/um;
dj=jj/un;
ri=ii%um;
rj=jj%un;
pi= ri+rj;
pj= di+dj;
out[ii + jj*((sy-firy+1)*(sx-firx+1)) + zz*((sy-firy+1)*(sx-firx+1)*firy*firx)]=y[pi+pj*sy+zz*sy*sx];
}
} | .text
.file "patch2hank_single.hip"
.globl _Z32__device_stub__patch2hank_singlePfS_iiiii # -- Begin function _Z32__device_stub__patch2hank_singlePfS_iiiii
.p2align 4, 0x90
.type _Z32__device_stub__patch2hank_singlePfS_iiiii,@function
_Z32__device_stub__patch2hank_singlePfS_iiiii: # @_Z32__device_stub__patch2hank_singlePfS_iiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17patch2hank_singlePfS_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z32__device_stub__patch2hank_singlePfS_iiiii, .Lfunc_end0-_Z32__device_stub__patch2hank_singlePfS_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17patch2hank_singlePfS_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17patch2hank_singlePfS_iiiii,@object # @_Z17patch2hank_singlePfS_iiiii
.section .rodata,"a",@progbits
.globl _Z17patch2hank_singlePfS_iiiii
.p2align 3, 0x0
_Z17patch2hank_singlePfS_iiiii:
.quad _Z32__device_stub__patch2hank_singlePfS_iiiii
.size _Z17patch2hank_singlePfS_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17patch2hank_singlePfS_iiiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__patch2hank_singlePfS_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17patch2hank_singlePfS_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z17patch2hank_singlePfS_iiiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC UR4, c[0x0][0x174] ; /* 0x00005d0000047ab9 */
/* 0x000fe20000000800 */
/*0040*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff007624 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R4, SR_CTAID.X ; /* 0x0000000000047919 */
/* 0x000e220000002500 */
/*0060*/ ULDC UR5, c[0x0][0x180] ; /* 0x0000600000057ab9 */
/* 0x000fe40000000800 */
/*0070*/ UIADD3 UR4, UR4, 0x1, -UR5 ; /* 0x0000000104047890 */
/* 0x000fe2000fffe805 */
/*0080*/ IADD3 R3, R3, 0x1, -R0 ; /* 0x0000000103037810 */
/* 0x000fe20007ffe800 */
/*0090*/ ULDC UR6, c[0x0][0x17c] ; /* 0x00005f0000067ab9 */
/* 0x000fe40000000800 */
/*00a0*/ UIMAD UR5, UR5, UR6, URZ ; /* 0x00000006050572a4 */
/* 0x000fc4000f8e023f */
/*00b0*/ IMAD R0, R3, UR4, RZ ; /* 0x0000000403007c24 */
/* 0x000fc8000f8e02ff */
/*00c0*/ IMAD R2, R0, UR5, RZ ; /* 0x0000000500027c24 */
/* 0x000fe4000f8e02ff */
/*00d0*/ IMAD R11, R4, c[0x0][0x0], R11 ; /* 0x00000000040b7a24 */
/* 0x001fe400078e020b */
/*00e0*/ IMAD R4, R2, c[0x0][0x178], RZ ; /* 0x00005e0002047a24 */
/* 0x000fca00078e02ff */
/*00f0*/ ISETP.GE.AND P0, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x000fda0003f06270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ IABS R9, R2.reuse ; /* 0x0000000200097213 */
/* 0x080fe20000000000 */
/*0120*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IABS R10, R2 ; /* 0x00000002000a7213 */
/* 0x000fe40000000000 */
/*0140*/ I2F.RP R6, R9 ; /* 0x0000000900067306 */
/* 0x000e220000209400 */
/*0150*/ IABS R14, R3.reuse ; /* 0x00000003000e7213 */
/* 0x080fe40000000000 */
/*0160*/ IABS R16, R3 ; /* 0x0000000300107213 */
/* 0x000fca0000000000 */
/*0170*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e240000001000 */
/*0180*/ IADD3 R4, R6, 0xffffffe, RZ ; /* 0x0ffffffe06047810 */
/* 0x001fcc0007ffe0ff */
/*0190*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*01a0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x001fe200078e00ff */
/*01b0*/ IADD3 R8, RZ, -R5, RZ ; /* 0x80000005ff087210 */
/* 0x002fca0007ffe0ff */
/*01c0*/ IMAD R7, R8, R9, RZ ; /* 0x0000000908077224 */
/* 0x000fe200078e02ff */
/*01d0*/ IABS R8, R11 ; /* 0x0000000b00087213 */
/* 0x000fc60000000000 */
/*01e0*/ IMAD.HI.U32 R5, R5, R7, R4 ; /* 0x0000000705057227 */
/* 0x000fe200078e0004 */
/*01f0*/ IABS R7, R0 ; /* 0x0000000000077213 */
/* 0x000fc60000000000 */
/*0200*/ IMAD.MOV R4, RZ, RZ, -R10 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0a0a */
/*0210*/ I2F.RP R6, R7 ; /* 0x0000000700067306 */
/* 0x000e220000209400 */
/*0220*/ IMAD.HI.U32 R5, R5, R8, RZ ; /* 0x0000000805057227 */
/* 0x000fc800078e00ff */
/*0230*/ IMAD R4, R5, R4, R8 ; /* 0x0000000405047224 */
/* 0x000fca00078e0208 */
/*0240*/ ISETP.GT.U32.AND P1, PT, R9, R4, PT ; /* 0x000000040900720c */
/* 0x000fe20003f24070 */
/*0250*/ MUFU.RCP R6, R6 ; /* 0x0000000600067308 */
/* 0x001e180000001000 */
/*0260*/ @!P1 IMAD.IADD R4, R4, 0x1, -R9 ; /* 0x0000000104049824 */
/* 0x000fe200078e0a09 */
/*0270*/ @!P1 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105059810 */
/* 0x000fe40007ffe0ff */
/*0280*/ ISETP.NE.AND P1, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f25270 */
/*0290*/ ISETP.GE.U32.AND P0, PT, R4, R9, PT ; /* 0x000000090400720c */
/* 0x000fe40003f06070 */
/*02a0*/ LOP3.LUT R4, R11, R2, RZ, 0x3c, !PT ; /* 0x000000020b047212 */
/* 0x000fe400078e3cff */
/*02b0*/ IADD3 R8, R6, 0xffffffe, RZ ; /* 0x0ffffffe06087810 */
/* 0x001fe40007ffe0ff */
/*02c0*/ ISETP.GE.AND P2, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fc40003f46270 */
/*02d0*/ F2I.FTZ.U32.TRUNC.NTZ R9, R8 ; /* 0x0000000800097305 */
/* 0x000062000021f000 */
/*02e0*/ IABS R4, c[0x0][0x17c] ; /* 0x00005f0000047a13 */
/* 0x000fc80000000000 */
/*02f0*/ @P0 IADD3 R5, R5, 0x1, RZ ; /* 0x0000000105050810 */
/* 0x000fc60007ffe0ff */
/*0300*/ I2F.RP R13, R4 ; /* 0x00000004000d7306 */
/* 0x000ea20000209400 */
/*0310*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe400078e00ff */
/*0320*/ @!P2 IADD3 R5, -R5, RZ, RZ ; /* 0x000000ff0505a210 */
/* 0x000fe40007ffe1ff */
/*0330*/ @!P1 LOP3.LUT R5, RZ, R2, RZ, 0x33, !PT ; /* 0x00000002ff059212 */
/* 0x000fe200078e33ff */
/*0340*/ IMAD.MOV R10, RZ, RZ, -R9 ; /* 0x000000ffff0a7224 */
/* 0x002fc800078e0a09 */
/*0350*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0a05 */
/*0360*/ IMAD R15, R10, R7, RZ ; /* 0x000000070a0f7224 */
/* 0x000fe400078e02ff */
/*0370*/ IMAD R11, R2, R6, R11 ; /* 0x00000006020b7224 */
/* 0x000fe200078e020b */
/*0380*/ IABS R6, R0 ; /* 0x0000000000067213 */
/* 0x000fe20000000000 */
/*0390*/ IMAD.HI.U32 R8, R9, R15, R8 ; /* 0x0000000f09087227 */
/* 0x000fe200078e0008 */
/*03a0*/ MUFU.RCP R13, R13 ; /* 0x0000000d000d7308 */
/* 0x004e240000001000 */
/*03b0*/ IABS R10, R11 ; /* 0x0000000b000a7213 */
/* 0x000fe40000000000 */
/*03c0*/ IADD3 R12, RZ, -R6, RZ ; /* 0x80000006ff0c7210 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD.MOV.U32 R6, RZ, RZ, R14 ; /* 0x000000ffff067224 */
/* 0x000fc400078e000e */
/*03e0*/ IMAD.MOV.U32 R9, RZ, RZ, R10 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000a */
/*03f0*/ IMAD.MOV.U32 R10, RZ, RZ, R12 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e000c */
/*0400*/ I2F.RP R14, R6 ; /* 0x00000006000e7306 */
/* 0x000e620000209400 */
/*0410*/ IMAD.HI.U32 R8, R8, R9, RZ ; /* 0x0000000908087227 */
/* 0x000fc800078e00ff */
/*0420*/ IMAD R10, R8, R10, R9 ; /* 0x0000000a080a7224 */
/* 0x000fe200078e0209 */
/*0430*/ IADD3 R9, R13, 0xffffffe, RZ ; /* 0x0ffffffe0d097810 */
/* 0x001fc80007ffe0ff */
/*0440*/ ISETP.GT.U32.AND P1, PT, R7, R10, PT ; /* 0x0000000a0700720c */
/* 0x000fe40003f24070 */
/*0450*/ F2I.FTZ.U32.TRUNC.NTZ R9, R9 ; /* 0x0000000900097305 */
/* 0x000e30000021f000 */
/*0460*/ MUFU.RCP R14, R14 ; /* 0x0000000e000e7308 */
/* 0x002e660000001000 */
/*0470*/ @!P1 IADD3 R10, R10, -R7, RZ ; /* 0x800000070a0a9210 */
/* 0x000fc40007ffe0ff */
/*0480*/ @!P1 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108089810 */
/* 0x000fe40007ffe0ff */
/*0490*/ ISETP.GE.U32.AND P0, PT, R10, R7, PT ; /* 0x000000070a00720c */
/* 0x000fe20003f06070 */
/*04a0*/ IMAD.MOV R15, RZ, RZ, -R9 ; /* 0x000000ffff0f7224 */
/* 0x001fe200078e0a09 */
/*04b0*/ LOP3.LUT R7, R11, R0, RZ, 0x3c, !PT ; /* 0x000000000b077212 */
/* 0x000fe400078e3cff */
/*04c0*/ ISETP.NE.AND P1, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fe20003f25270 */
/*04d0*/ IMAD R15, R15, R4, RZ ; /* 0x000000040f0f7224 */
/* 0x000fe200078e02ff */
/*04e0*/ ISETP.GE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fe40003f46270 */
/*04f0*/ IADD3 R12, R14, 0xffffffe, RZ ; /* 0x0ffffffe0e0c7810 */
/* 0x002fca0007ffe0ff */
/*0500*/ @P0 IADD3 R8, R8, 0x1, RZ ; /* 0x0000000108080810 */
/* 0x000fe20007ffe0ff */
/*0510*/ F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; /* 0x0000000c000d7305 */
/* 0x000e28000021f000 */
/*0520*/ IMAD.MOV.U32 R7, RZ, RZ, R8 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0008 */
/*0530*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe400078e00ff */
/*0540*/ @!P2 IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff07a224 */
/* 0x000fe200078e0a07 */
/*0550*/ @!P1 LOP3.LUT R7, RZ, R0, RZ, 0x33, !PT ; /* 0x00000000ff079212 */
/* 0x000fe200078e33ff */
/*0560*/ IMAD.HI.U32 R9, R9, R15, R8 ; /* 0x0000000f09097227 */
/* 0x000fc600078e0008 */
/*0570*/ IABS R14, R7 ; /* 0x00000007000e7213 */
/* 0x000fe20000000000 */
/*0580*/ IMAD.MOV R10, RZ, RZ, -R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0a07 */
/*0590*/ IADD3 R17, RZ, -R13, RZ ; /* 0x8000000dff117210 */
/* 0x001fe20007ffe0ff */
/*05a0*/ IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e00ff */
/*05b0*/ IMAD R8, R0, R10, R11 ; /* 0x0000000a00087224 */
/* 0x000fe400078e020b */
/*05c0*/ IMAD R11, R17, R6, RZ ; /* 0x00000006110b7224 */
/* 0x000fe400078e02ff */
/*05d0*/ IMAD.HI.U32 R10, R9, R14, RZ ; /* 0x0000000e090a7227 */
/* 0x000fe200078e00ff */
/*05e0*/ IABS R15, R8 ; /* 0x00000008000f7213 */
/* 0x000fc60000000000 */
/*05f0*/ IMAD.HI.U32 R12, R13, R11, R12 ; /* 0x0000000b0d0c7227 */
/* 0x000fe200078e000c */
/*0600*/ IADD3 R13, RZ, -R16, RZ ; /* 0x80000010ff0d7210 */
/* 0x000fc60007ffe0ff */
/*0610*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fe400078e000f */
/*0620*/ IMAD.MOV R11, RZ, RZ, -R10 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0a0a */
/*0630*/ IMAD.HI.U32 R12, R12, R9, RZ ; /* 0x000000090c0c7227 */
/* 0x000fc800078e00ff */
/*0640*/ IMAD R11, R4, R11, R14 ; /* 0x0000000b040b7224 */
/* 0x000fe400078e020e */
/*0650*/ IMAD R9, R12, R13, R9 ; /* 0x0000000d0c097224 */
/* 0x000fc600078e0209 */
/*0660*/ ISETP.GT.U32.AND P5, PT, R4, R11, PT ; /* 0x0000000b0400720c */
/* 0x000fe40003fa4070 */
/*0670*/ ISETP.GT.U32.AND P4, PT, R6, R9, PT ; /* 0x000000090600720c */
/* 0x000fd60003f84070 */
/*0680*/ @!P5 IMAD.IADD R11, R11, 0x1, -R4 ; /* 0x000000010b0bd824 */
/* 0x000fe200078e0a04 */
/*0690*/ @!P5 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0ad810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ @!P4 IADD3 R9, R9, -R6, RZ ; /* 0x800000060909c210 */
/* 0x000fe40007ffe0ff */
/*06b0*/ ISETP.GE.U32.AND P0, PT, R11, R4, PT ; /* 0x000000040b00720c */
/* 0x000fe40003f06070 */
/*06c0*/ ISETP.GE.U32.AND P1, PT, R9, R6, PT ; /* 0x000000060900720c */
/* 0x000fe40003f26070 */
/*06d0*/ LOP3.LUT R6, R7, c[0x0][0x17c], RZ, 0x3c, !PT ; /* 0x00005f0007067a12 */
/* 0x000fe400078e3cff */
/*06e0*/ LOP3.LUT R4, R8, R3, RZ, 0x3c, !PT ; /* 0x0000000308047212 */
/* 0x000fc400078e3cff */
/*06f0*/ ISETP.GE.AND P2, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f46270 */
/*0700*/ ISETP.GE.AND P3, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f66270 */
/*0710*/ @!P4 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0cc810 */
/* 0x000fe40007ffe0ff */
/*0720*/ ISETP.NE.AND P4, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f85270 */
/*0730*/ ISETP.NE.AND P5, PT, RZ, c[0x0][0x17c], PT ; /* 0x00005f00ff007a0c */
/* 0x000fe40003fa5270 */
/*0740*/ @P0 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a0810 */
/* 0x000fc40007ffe0ff */
/*0750*/ @P1 IADD3 R12, R12, 0x1, RZ ; /* 0x000000010c0c1810 */
/* 0x000fc60007ffe0ff */
/*0760*/ @!P2 IMAD.MOV R10, RZ, RZ, -R10 ; /* 0x000000ffff0aa224 */
/* 0x000fe400078e0a0a */
/*0770*/ @!P3 IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0cb224 */
/* 0x000fe400078e0a0c */
/*0780*/ @!P4 LOP3.LUT R12, RZ, R3, RZ, 0x33, !PT ; /* 0x00000003ff0cc212 */
/* 0x000fe400078e33ff */
/*0790*/ @!P5 LOP3.LUT R10, RZ, c[0x0][0x17c], RZ, 0x33, !PT ; /* 0x00005f00ff0ada12 */
/* 0x000fc600078e33ff */
/*07a0*/ IMAD.MOV R6, RZ, RZ, -R12.reuse ; /* 0x000000ffff067224 */
/* 0x100fe200078e0a0c */
/*07b0*/ IADD3 R4, -R10, RZ, RZ ; /* 0x000000ff0a047210 */
/* 0x000fe20007ffe1ff */
/*07c0*/ IMAD R9, R5, c[0x0][0x174], R12 ; /* 0x00005d0005097a24 */
/* 0x000fe400078e020c */
/*07d0*/ IMAD R3, R3, R6, R8 ; /* 0x0000000603037224 */
/* 0x000fe400078e0208 */
/*07e0*/ IMAD R4, R4, c[0x0][0x17c], R7 ; /* 0x00005f0004047a24 */
/* 0x000fe400078e0207 */
/*07f0*/ IMAD.IADD R9, R10, 0x1, R9 ; /* 0x000000010a097824 */
/* 0x000fc600078e0209 */
/*0800*/ IADD3 R4, R3, R4, RZ ; /* 0x0000000403047210 */
/* 0x000fe20007ffe0ff */
/*0810*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0820*/ IMAD R4, R9, c[0x0][0x170], R4 ; /* 0x00005c0009047a24 */
/* 0x000fc800078e0204 */
/*0830*/ IMAD.WIDE R10, R4, R3, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fcc00078e0203 */
/*0840*/ LDG.E R11, [R10.64] ; /* 0x000000040a0b7981 */
/* 0x000ea2000c1e1900 */
/*0850*/ IMAD R2, R2, R5, R8 ; /* 0x0000000502027224 */
/* 0x000fc800078e0208 */
/*0860*/ IMAD R2, R0, R7, R2 ; /* 0x0000000700027224 */
/* 0x000fc800078e0202 */
/*0870*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0880*/ STG.E [R2.64], R11 ; /* 0x0000000b02007986 */
/* 0x004fe2000c101904 */
/*0890*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*08a0*/ BRA 0x8a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0900*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0910*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0920*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0930*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0940*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0950*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z17patch2hank_singlePfS_iiiii
.globl _Z17patch2hank_singlePfS_iiiii
.p2align 8
.type _Z17patch2hank_singlePfS_iiiii,@function
_Z17patch2hank_singlePfS_iiiii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b128 s[4:7], s[0:1], 0x10
s_load_b32 s8, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_sub_i32 s3, s4, s7
s_sub_i32 s9, s5, s8
s_add_i32 s3, s3, 1
s_add_i32 s9, s9, 1
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s3, s9
s_mul_i32 s8, s8, s7
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s8, s8, s2
s_mul_i32 s6, s8, s6
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB0_2
s_ashr_i32 s6, s8, 31
v_ashrrev_i32_e32 v3, 31, v1
s_add_i32 s9, s8, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s9, s9, s6
v_add_nc_u32_e32 v4, v1, v3
v_cvt_f32_u32_e32 v0, s9
s_sub_i32 s10, 0, s9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v3
v_rcp_iflag_f32_e32 v0, v0
v_xor_b32_e32 v3, s6, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s10, v0
s_ashr_i32 s10, s2, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s11, s2, s10
s_xor_b32 s11, s11, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_sub_i32 s6, 0, s11
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
v_mul_hi_u32 v0, v4, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v2, v0, s9
v_sub_nc_u32_e32 v2, v4, v2
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v5, s9, v2
v_cmp_le_u32_e32 vcc_lo, s9, v2
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_cvt_f32_u32_e32 v5, s11
v_add_nc_u32_e32 v4, 1, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s9, v2
v_rcp_iflag_f32_e32 v2, v5
s_ashr_i32 s9, s3, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
s_add_i32 s12, s3, s9
v_cndmask_b32_e32 v0, v0, v4, vcc_lo
s_xor_b32 s12, s12, s9
v_cvt_f32_u32_e32 v8, s12
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, 0x4f7ffffe, v2
v_sub_nc_u32_e32 v0, v0, v3
v_cvt_u32_f32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v3, v0, s8
v_mul_lo_u32 v4, s6, v2
s_ashr_i32 s6, s7, 31
v_mul_lo_u32 v0, v0, s5
s_add_i32 s8, s7, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
s_xor_b32 s8, s8, s6
v_sub_nc_u32_e32 v1, v1, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v4, v2, v4
v_ashrrev_i32_e32 v5, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v2, v4
v_add_nc_u32_e32 v6, v1, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v6, v5
v_xor_b32_e32 v5, s10, v5
s_sub_i32 s10, 0, s8
v_mul_hi_u32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, v2, s11
v_sub_nc_u32_e32 v4, v4, v6
v_add_nc_u32_e32 v6, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_subrev_nc_u32_e32 v7, s11, v4
v_cmp_le_u32_e32 vcc_lo, s11, v4
v_cndmask_b32_e32 v2, v2, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v4, v4, v7, vcc_lo
v_cvt_f32_u32_e32 v6, s8
v_add_nc_u32_e32 v7, 1, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s11, v4
v_rcp_iflag_f32_e32 v6, v6
v_rcp_iflag_f32_e32 v4, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v2, v2, v7, vcc_lo
v_xor_b32_e32 v2, v2, v5
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, 0x4f7ffffe, v6
v_mul_f32_e32 v4, 0x4f7ffffe, v4
v_sub_nc_u32_e32 v2, v2, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cvt_u32_f32_e32 v5, v6
v_cvt_u32_f32_e32 v4, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_lo_u32 v6, v2, s2
v_mul_lo_u32 v7, s10, v5
s_sub_i32 s2, 0, s12
s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
v_mul_lo_u32 v8, s2, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_sub_nc_u32_e32 v9, v1, v6
v_ashrrev_i32_e32 v1, 31, v2
v_mul_hi_u32 v7, v5, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v8, v4, v8
v_ashrrev_i32_e32 v10, 31, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_nc_u32_e32 v11, v2, v1
v_add_nc_u32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_xor_b32_e32 v7, v11, v1
v_add_nc_u32_e32 v12, v9, v10
v_add_nc_u32_e32 v4, v4, v8
v_xor_b32_e32 v1, s6, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v5, v7, v5
v_xor_b32_e32 v8, v12, v10
v_xor_b32_e32 v10, s9, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_mul_hi_u32 v4, v8, v4
v_mul_lo_u32 v11, v5, s8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v12, v4, s12
v_sub_nc_u32_e32 v7, v7, v11
v_add_nc_u32_e32 v11, 1, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cmp_le_u32_e32 vcc_lo, s8, v7
v_sub_nc_u32_e32 v8, v8, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_cndmask_b32 v5, v5, v11 :: v_dual_add_nc_u32 v12, 1, v4
v_subrev_nc_u32_e32 v11, s8, v7
v_subrev_nc_u32_e32 v13, s12, v8
v_cmp_le_u32_e64 s2, s12, v8
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v7, v7, v11, vcc_lo
v_add_nc_u32_e32 v11, 1, v5
v_cndmask_b32_e64 v4, v4, v12, s2
v_cndmask_b32_e64 v8, v8, v13, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_le_u32_e32 vcc_lo, s8, v7
v_dual_cndmask_b32 v5, v5, v11 :: v_dual_add_nc_u32 v12, 1, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_le_u32_e32 vcc_lo, s12, v8
v_xor_b32_e32 v5, v5, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, v4, v12, vcc_lo
v_sub_nc_u32_e32 v1, v5, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v4, v4, v10
v_mul_lo_u32 v5, v1, s7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v4, v10
v_mul_lo_u32 v7, v4, s3
v_add3_u32 v0, v4, v0, v1
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v1, v2, v5
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v0, v0, s4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v2, v9, v7
v_add3_u32 v0, v1, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[0:1], off
v_add3_u32 v0, v9, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17patch2hank_singlePfS_iiiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z17patch2hank_singlePfS_iiiii, .Lfunc_end0-_Z17patch2hank_singlePfS_iiiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17patch2hank_singlePfS_iiiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17patch2hank_singlePfS_iiiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001959e1_00000000-6_patch2hank_single.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii
.type _Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii, @function
_Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 152(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 152(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $168, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 184
pushq 40(%rsp)
.cfi_def_cfa_offset 192
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z17patch2hank_singlePfS_iiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 176
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii, .-_Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii
.globl _Z17patch2hank_singlePfS_iiiii
.type _Z17patch2hank_singlePfS_iiiii, @function
_Z17patch2hank_singlePfS_iiiii:
.LFB2052:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z44__device_stub__Z17patch2hank_singlePfS_iiiiiPfS_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z17patch2hank_singlePfS_iiiii, .-_Z17patch2hank_singlePfS_iiiii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z17patch2hank_singlePfS_iiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z17patch2hank_singlePfS_iiiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "patch2hank_single.hip"
.globl _Z32__device_stub__patch2hank_singlePfS_iiiii # -- Begin function _Z32__device_stub__patch2hank_singlePfS_iiiii
.p2align 4, 0x90
.type _Z32__device_stub__patch2hank_singlePfS_iiiii,@function
_Z32__device_stub__patch2hank_singlePfS_iiiii: # @_Z32__device_stub__patch2hank_singlePfS_iiiii
.cfi_startproc
# %bb.0:
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 144(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z17patch2hank_singlePfS_iiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $152, %rsp
.cfi_adjust_cfa_offset -152
retq
.Lfunc_end0:
.size _Z32__device_stub__patch2hank_singlePfS_iiiii, .Lfunc_end0-_Z32__device_stub__patch2hank_singlePfS_iiiii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17patch2hank_singlePfS_iiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z17patch2hank_singlePfS_iiiii,@object # @_Z17patch2hank_singlePfS_iiiii
.section .rodata,"a",@progbits
.globl _Z17patch2hank_singlePfS_iiiii
.p2align 3, 0x0
_Z17patch2hank_singlePfS_iiiii:
.quad _Z32__device_stub__patch2hank_singlePfS_iiiii
.size _Z17patch2hank_singlePfS_iiiii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z17patch2hank_singlePfS_iiiii"
.size .L__unnamed_1, 31
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z32__device_stub__patch2hank_singlePfS_iiiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z17patch2hank_singlePfS_iiiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
/* Kintsakis Athanasios AEM 6667 */
#define inf 9999
__global__ void funct(int n, int k, float* x, int* qx)
{
int ix= blockIdx.x*blockDim.x + threadIdx.x;
//Epeksigisi
/*
float temp2=x[i*n+k] + x[k*n+j];
omws
i=ix/n;
kai
j=ix%n = ix&(n-1)
i*n = ix/n * n = ix-ix%n= ix-j
*/
int j=ix&(n-1);
float temp2=x[ix-j+k]+x[k*n+j];
if(x[ix]>temp2)
{
x[ix]=temp2;
qx[ix]=k;
}
if(x[ix]==inf)
{
qx[ix]=-2;
}
} | code for sm_80
Function : _Z5functiiPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fe200078e0203 */
/*0070*/ IADD3 R3, R4, -0x1, RZ ; /* 0xffffffff04037810 */
/* 0x000fca0007ffe0ff */
/*0080*/ IMAD.WIDE R6, R8, R9, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fe200078e0209 */
/*0090*/ LOP3.LUT R3, R3, R8, RZ, 0xc0, !PT ; /* 0x0000000803037212 */
/* 0x000fc800078ec0ff */
/*00a0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD R4, R4, c[0x0][0x164], R3 ; /* 0x0000590004047a24 */
/* 0x000fe200078e0203 */
/*00c0*/ IADD3 R3, -R3, c[0x0][0x164], R8 ; /* 0x0000590003037a10 */
/* 0x000fc60007ffe108 */
/*00d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R2, R3, R9.reuse, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x080fe400078e0209 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*0110*/ BSSY B0, 0x1b0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0120*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fc800078e0209 */
/*0130*/ FADD R11, R4, R3 ; /* 0x00000003040b7221 */
/* 0x008fca0000000000 */
/*0140*/ FSETP.GT.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720b */
/* 0x004fda0003f04000 */
/*0150*/ @!P0 BRA 0x1a0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0170*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0180*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0001e8000c101904 */
/*0190*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000164000c1e1900 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ FSETP.NEU.AND P0, PT, R0, 9999, PT ; /* 0x461c3c000000780b */
/* 0x020fda0003f0d000 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ MOV R3, 0xfffffffe ; /* 0xfffffffe00037802 */
/* 0x001fca0000000f00 */
/*01e0*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
/* Kintsakis Athanasios AEM 6667 */
#define inf 9999
__global__ void funct(int n, int k, float* x, int* qx)
{
int ix= blockIdx.x*blockDim.x + threadIdx.x;
//Epeksigisi
/*
float temp2=x[i*n+k] + x[k*n+j];
omws
i=ix/n;
kai
j=ix%n = ix&(n-1)
i*n = ix/n * n = ix-ix%n= ix-j
*/
int j=ix&(n-1);
float temp2=x[ix-j+k]+x[k*n+j];
if(x[ix]>temp2)
{
x[ix]=temp2;
qx[ix]=k;
}
if(x[ix]==inf)
{
qx[ix]=-2;
}
} | .file "tmpxft_001a68d8_00000000-6_funct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5functiiPfPiiiPfPi
.type _Z28__device_stub__Z5functiiPfPiiiPfPi, @function
_Z28__device_stub__Z5functiiPfPiiiPfPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5functiiPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z5functiiPfPiiiPfPi, .-_Z28__device_stub__Z5functiiPfPiiiPfPi
.globl _Z5functiiPfPi
.type _Z5functiiPfPi, @function
_Z5functiiPfPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5functiiPfPiiiPfPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5functiiPfPi, .-_Z5functiiPfPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5functiiPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5functiiPfPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
/* Kintsakis Athanasios AEM 6667 */
#define inf 9999
__global__ void funct(int n, int k, float* x, int* qx)
{
int ix= blockIdx.x*blockDim.x + threadIdx.x;
//Epeksigisi
/*
float temp2=x[i*n+k] + x[k*n+j];
omws
i=ix/n;
kai
j=ix%n = ix&(n-1)
i*n = ix/n * n = ix-ix%n= ix-j
*/
int j=ix&(n-1);
float temp2=x[ix-j+k]+x[k*n+j];
if(x[ix]>temp2)
{
x[ix]=temp2;
qx[ix]=k;
}
if(x[ix]==inf)
{
qx[ix]=-2;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
/* Kintsakis Athanasios AEM 6667 */
#define inf 9999
__global__ void funct(int n, int k, float* x, int* qx)
{
int ix= blockIdx.x*blockDim.x + threadIdx.x;
//Epeksigisi
/*
float temp2=x[i*n+k] + x[k*n+j];
omws
i=ix/n;
kai
j=ix%n = ix&(n-1)
i*n = ix/n * n = ix-ix%n= ix-j
*/
int j=ix&(n-1);
float temp2=x[ix-j+k]+x[k*n+j];
if(x[ix]>temp2)
{
x[ix]=temp2;
qx[ix]=k;
}
if(x[ix]==inf)
{
qx[ix]=-2;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* Kintsakis Athanasios AEM 6667 */
#define inf 9999
__global__ void funct(int n, int k, float* x, int* qx)
{
int ix= blockIdx.x*blockDim.x + threadIdx.x;
//Epeksigisi
/*
float temp2=x[i*n+k] + x[k*n+j];
omws
i=ix/n;
kai
j=ix%n = ix&(n-1)
i*n = ix/n * n = ix-ix%n= ix-j
*/
int j=ix&(n-1);
float temp2=x[ix-j+k]+x[k*n+j];
if(x[ix]>temp2)
{
x[ix]=temp2;
qx[ix]=k;
}
if(x[ix]==inf)
{
qx[ix]=-2;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5functiiPfPi
.globl _Z5functiiPfPi
.p2align 8
.type _Z5functiiPfPi,@function
_Z5functiiPfPi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_add_i32 s2, s4, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_b32_e32 v0, s2, v1
v_add_nc_u32_e32 v2, s5, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s5, s4, v[0:1]
v_sub_nc_u32_e32 v2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s6, v3
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_clause 0x1
global_load_b32 v0, v[8:9], off
global_load_b32 v7, v[3:4], off
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
global_load_b32 v8, v[3:4], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 v8, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_mov_b32_e32 v7, s5
global_store_b32 v[3:4], v0, off
global_store_b32 v[5:6], v7, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v0, v[3:4], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 0x461c3c00, v0
s_cbranch_execz .LBB0_4
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, -2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5functiiPfPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5functiiPfPi, .Lfunc_end0-_Z5functiiPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5functiiPfPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5functiiPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
/* Kintsakis Athanasios AEM 6667 */
#define inf 9999
__global__ void funct(int n, int k, float* x, int* qx)
{
int ix= blockIdx.x*blockDim.x + threadIdx.x;
//Epeksigisi
/*
float temp2=x[i*n+k] + x[k*n+j];
omws
i=ix/n;
kai
j=ix%n = ix&(n-1)
i*n = ix/n * n = ix-ix%n= ix-j
*/
int j=ix&(n-1);
float temp2=x[ix-j+k]+x[k*n+j];
if(x[ix]>temp2)
{
x[ix]=temp2;
qx[ix]=k;
}
if(x[ix]==inf)
{
qx[ix]=-2;
}
} | .text
.file "funct.hip"
.globl _Z20__device_stub__functiiPfPi # -- Begin function _Z20__device_stub__functiiPfPi
.p2align 4, 0x90
.type _Z20__device_stub__functiiPfPi,@function
_Z20__device_stub__functiiPfPi: # @_Z20__device_stub__functiiPfPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5functiiPfPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__functiiPfPi, .Lfunc_end0-_Z20__device_stub__functiiPfPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5functiiPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5functiiPfPi,@object # @_Z5functiiPfPi
.section .rodata,"a",@progbits
.globl _Z5functiiPfPi
.p2align 3, 0x0
_Z5functiiPfPi:
.quad _Z20__device_stub__functiiPfPi
.size _Z5functiiPfPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5functiiPfPi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__functiiPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5functiiPfPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z5functiiPfPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ MOV R4, c[0x0][0x160] ; /* 0x0000580000047a02 */
/* 0x000fe20000000f00 */
/*0030*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x001fe200078e0203 */
/*0070*/ IADD3 R3, R4, -0x1, RZ ; /* 0xffffffff04037810 */
/* 0x000fca0007ffe0ff */
/*0080*/ IMAD.WIDE R6, R8, R9, c[0x0][0x168] ; /* 0x00005a0008067625 */
/* 0x000fe200078e0209 */
/*0090*/ LOP3.LUT R3, R3, R8, RZ, 0xc0, !PT ; /* 0x0000000803037212 */
/* 0x000fc800078ec0ff */
/*00a0*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000ea2000c1e1900 */
/*00b0*/ IMAD R4, R4, c[0x0][0x164], R3 ; /* 0x0000590004047a24 */
/* 0x000fe200078e0203 */
/*00c0*/ IADD3 R3, -R3, c[0x0][0x164], R8 ; /* 0x0000590003037a10 */
/* 0x000fc60007ffe108 */
/*00d0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc800078e0209 */
/*00e0*/ IMAD.WIDE R2, R3, R9.reuse, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x080fe400078e0209 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ee8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ee2000c1e1900 */
/*0110*/ BSSY B0, 0x1b0 ; /* 0x0000009000007945 */
/* 0x000fe20003800000 */
/*0120*/ IMAD.WIDE R8, R8, R9, c[0x0][0x170] ; /* 0x00005c0008087625 */
/* 0x000fc800078e0209 */
/*0130*/ FADD R11, R4, R3 ; /* 0x00000003040b7221 */
/* 0x008fca0000000000 */
/*0140*/ FSETP.GT.AND P0, PT, R0, R11, PT ; /* 0x0000000b0000720b */
/* 0x004fda0003f04000 */
/*0150*/ @!P0 BRA 0x1a0 ; /* 0x0000004000008947 */
/* 0x000fea0003800000 */
/*0160*/ MOV R3, c[0x0][0x164] ; /* 0x0000590000037a02 */
/* 0x000fe20000000f00 */
/*0170*/ STG.E [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101904 */
/*0180*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x0001e8000c101904 */
/*0190*/ LDG.E R0, [R6.64] ; /* 0x0000000406007981 */
/* 0x000164000c1e1900 */
/*01a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01b0*/ FSETP.NEU.AND P0, PT, R0, 9999, PT ; /* 0x461c3c000000780b */
/* 0x020fda0003f0d000 */
/*01c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*01d0*/ MOV R3, 0xfffffffe ; /* 0xfffffffe00037802 */
/* 0x001fca0000000f00 */
/*01e0*/ STG.E [R8.64], R3 ; /* 0x0000000308007986 */
/* 0x000fe2000c101904 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5functiiPfPi
.globl _Z5functiiPfPi
.p2align 8
.type _Z5functiiPfPi,@function
_Z5functiiPfPi:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_add_i32 s2, s4, -1
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_and_b32_e32 v0, s2, v1
v_add_nc_u32_e32 v2, s5, v1
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s5, s4, v[0:1]
v_sub_nc_u32_e32 v2, v2, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ashrrev_i32_e32 v3, 31, v2
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_lshlrev_b64 v[3:4], 2, v[4:5]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v8, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v9, vcc_lo, s7, v7, vcc_lo
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v3, vcc_lo, s6, v3
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
s_clause 0x1
global_load_b32 v0, v[8:9], off
global_load_b32 v7, v[3:4], off
v_add_co_u32 v3, vcc_lo, s6, v5
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
global_load_b32 v8, v[3:4], off
s_waitcnt vmcnt(1)
v_add_f32_e32 v0, v0, v7
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 v8, v0
s_cbranch_execz .LBB0_2
v_add_co_u32 v5, vcc_lo, s0, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
v_mov_b32_e32 v7, s5
global_store_b32 v[3:4], v0, off
global_store_b32 v[5:6], v7, off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s2
global_load_b32 v0, v[3:4], off
s_mov_b32 s2, exec_lo
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 0x461c3c00, v0
s_cbranch_execz .LBB0_4
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, -2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5functiiPfPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 10
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5functiiPfPi, .Lfunc_end0-_Z5functiiPfPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5functiiPfPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5functiiPfPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 10
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001a68d8_00000000-6_funct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z28__device_stub__Z5functiiPfPiiiPfPi
.type _Z28__device_stub__Z5functiiPfPiiiPfPi, @function
_Z28__device_stub__Z5functiiPfPiiiPfPi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5functiiPfPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z28__device_stub__Z5functiiPfPiiiPfPi, .-_Z28__device_stub__Z5functiiPfPiiiPfPi
.globl _Z5functiiPfPi
.type _Z5functiiPfPi, @function
_Z5functiiPfPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5functiiPfPiiiPfPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z5functiiPfPi, .-_Z5functiiPfPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z5functiiPfPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z5functiiPfPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "funct.hip"
.globl _Z20__device_stub__functiiPfPi # -- Begin function _Z20__device_stub__functiiPfPi
.p2align 4, 0x90
.type _Z20__device_stub__functiiPfPi,@function
_Z20__device_stub__functiiPfPi: # @_Z20__device_stub__functiiPfPi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 72(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5functiiPfPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z20__device_stub__functiiPfPi, .Lfunc_end0-_Z20__device_stub__functiiPfPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5functiiPfPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5functiiPfPi,@object # @_Z5functiiPfPi
.section .rodata,"a",@progbits
.globl _Z5functiiPfPi
.p2align 3, 0x0
_Z5functiiPfPi:
.quad _Z20__device_stub__functiiPfPi
.size _Z5functiiPfPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z5functiiPfPi"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__functiiPfPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5functiiPfPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
#define MEM_DIM 64
#define RADIO 3
#define SIZE_BLOQUE 8
#define SIZE_GRID 8
#define RADIO 3
/*Programar una funcion que haga la media de numeros end GPU sin memoria compartida, en GPU con memoria compartida
y en CPU. Comparar los tiempos de ejecucion*/
__global__ void kernel_Shared(int *d_input, int *d_output)
{
int i;
int valorFinal = 0;
__shared__ int arrayValores[ MEM_DIM + RADIO + RADIO ];
//Inicializar el array para poder calcular las medias
arrayValores[threadIdx.x + RADIO] = 0;
//Inicializar las posiciones extras en el array
if (threadIdx.x < RADIO)
arrayValores[threadIdx.x] = 0;
if (threadIdx.x >= (SIZE_BLOQUE - RADIO))
arrayValores[threadIdx.x + RADIO] = 0;
/*
//En esta posicion los valores de arrayValores son correctos - Inicializados a 0
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor deberia ser 0: %d\n", arrayValores[i]);
}
*/
// Sincronizar todos los threads - Se puede omitir?
__syncthreads();
//Copiar los valores desde la memoria global a la memoria compartida
arrayValores[threadIdx.x + RADIO] = d_input[blockIdx.x * blockDim.x + threadIdx.x];
//
/*if (threadIdx.x == 0)
{
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor deberia ser 0: %d\n", arrayValores[i]);
}
}*/
//d_output[blockIdx.x * blockDim.x + threadIdx.x];
/*if (threadIdx.x == 0)
{
for(int i = 0; i < MEM_DIM + RADIO + RADIO; ++i)
printf(" %d", arrayValores[i]);
}
printf("\n");*/
//Copiar los valores extras
if (threadIdx.x < RADIO)
{
if (blockIdx.x > 0)
{
arrayValores[threadIdx.x] = d_input[(blockIdx.x * blockDim.x + threadIdx.x) - RADIO];
}
}
if (threadIdx.x >= (SIZE_BLOQUE - RADIO))
{
if (blockIdx.x < SIZE_GRID - 1)
{
arrayValores[threadIdx.x + RADIO + RADIO] = d_input[(blockIdx.x * blockDim.x + threadIdx.x) + RADIO];
}
}
if (threadIdx.x == 0)
{
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor kernel (%d, %d): %d\n", blockIdx.x, i, arrayValores[i]);
}
printf("%d\n\n", blockIdx.x * blockDim.x + threadIdx.x);
}
//Sincronizar los threads
__syncthreads();
//Hacer la media en el array de outputs
for (i = -RADIO; i <= RADIO; ++i)
{
valorFinal += arrayValores[(threadIdx.x + RADIO) + i];
}
valorFinal /= (RADIO + RADIO + 1);
printf("Valor en el thread actual (%d, %d): %d\n", blockIdx.x, threadIdx.x, valorFinal);
d_output[blockIdx.x * blockDim.x + threadIdx.x] = valorFinal;
printf("Bloque: %d -> Thread: %d -> PosicionArray: %d -> Posicion Array Global: %d -> Valor Guardado: %d\n", blockIdx.x, threadIdx.x, threadIdx.x + RADIO, blockIdx.x * blockDim.x + threadIdx.x, arrayValores[threadIdx.x + RADIO]);
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n = SIZE_BLOQUE * SIZE_GRID;
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_input;
int *d_output;
int *h_input;
int *h_output;
cudaMalloc((void **) &d_input, numBytes );
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
cudaMalloc((void **) &d_output, numBytes );
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
cudaMemset(d_output, 0, n);
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
h_input = (int *)malloc(numBytes);
h_output = (int *)malloc(numBytes);
for(int i = 0; i < n; ++i)
h_input[i] = i;
cudaMemcpy (d_input, h_input, numBytes, cudaMemcpyHostToDevice);
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
dim3 blockSize(SIZE_BLOQUE);
dim3 gridSize(SIZE_GRID);
tiempoInicio = tiempo();
kernel_Shared <<<gridSize, blockSize>>>(d_input, d_output);
cudaThreadSynchronize();
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda _1\n");
}
tiempoFin = tiempo();
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
cudaMemcpy (h_output, d_output, numBytes, cudaMemcpyDeviceToHost);
tiempoFin = tiempo();
if ( cudaSuccess != cudaGetLastError() )
printf( "Error! _2\n" );
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
for(int i = 0; i < n; ++i)
{
printf("%d - ", h_output[i]);
}
printf("\n\n\nDone.\n");
return 0;
} | code for sm_80
Function : _Z13kernel_SharedPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R19, SR_TID.X ; /* 0x0000000000137919 */
/* 0x000e220000002100 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR36, c[0x0][0x118] ; /* 0x0000460000247ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IADD3 R1, R1, -0x18, RZ ; /* 0xffffffe801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R16, SR_CTAID.X ; /* 0x0000000000107919 */
/* 0x000e620000002500 */
/*0060*/ ISETP.GT.U32.AND P2, PT, R19, 0x2, PT ; /* 0x000000021300780c */
/* 0x001fc60003f44070 */
/*0070*/ STS [R19.X4+0xc], RZ ; /* 0x00000cff13007388 */
/* 0x0001e20000004800 */
/*0080*/ ISETP.GE.U32.AND P3, PT, R19.reuse, 0x5, PT ; /* 0x000000051300780c */
/* 0x040fe40003f66070 */
/*0090*/ ISETP.NE.AND P0, PT, R16.reuse, RZ, PT ; /* 0x000000ff1000720c */
/* 0x042fe20003f05270 */
/*00a0*/ IMAD R23, R16.reuse, c[0x0][0x0], R19 ; /* 0x0000000010177a24 */
/* 0x040fe200078e0213 */
/*00b0*/ ISETP.GT.U32.AND P1, PT, R16, 0x6, PT ; /* 0x000000061000780c */
/* 0x000fe40003f24070 */
/*00c0*/ ISETP.GT.U32.OR P0, PT, R19, 0x2, !P0 ; /* 0x000000021300780c */
/* 0x000fe20004704470 */
/*00d0*/ IMAD.WIDE.U32 R2, R23, R7, c[0x0][0x160] ; /* 0x0000580017027625 */
/* 0x000fe200078e0007 */
/*00e0*/ ISETP.LT.U32.OR P1, PT, R19, 0x5, P1 ; /* 0x000000051300780c */
/* 0x000fe20000f21470 */
/*00f0*/ @!P2 STS [R19.X4], RZ ; /* 0x000000ff1300a388 */
/* 0x0001e80000004800 */
/*0100*/ @P3 STS [R19.X4+0xc], RZ ; /* 0x00000cff13003388 */
/* 0x0001e80000004800 */
/*0110*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0120*/ @!P0 IADD3 R4, R23, -0x3, RZ ; /* 0xfffffffd17048810 */
/* 0x000fc40007ffe0ff */
/*0130*/ @!P1 IADD3 R6, R23, 0x3, RZ ; /* 0x0000000317069810 */
/* 0x000fc60007ffe0ff */
/*0140*/ @!P0 IMAD.WIDE.U32 R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004048625 */
/* 0x000fc800078e0007 */
/*0150*/ @!P1 IMAD.WIDE.U32 R6, R6, R7, c[0x0][0x160] ; /* 0x0000580006069625 */
/* 0x000fe200078e0007 */
/*0160*/ LDG.E R2, [R2.64] ; /* 0x0000002402027981 */
/* 0x000ea8000c1e1900 */
/*0170*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000002404048981 */
/* 0x000ee8000c1e1900 */
/*0180*/ @!P1 LDG.E R6, [R6.64] ; /* 0x0000002406069981 */
/* 0x000f28000c1e1900 */
/*0190*/ STS [R19.X4+0xc], R2 ; /* 0x00000c0213007388 */
/* 0x0041e80000004800 */
/*01a0*/ @!P0 STS [R19.X4], R4 ; /* 0x0000000413008388 */
/* 0x0081e20000004800 */
/*01b0*/ ISETP.NE.AND P0, PT, R19, RZ, PT ; /* 0x000000ff1300720c */
/* 0x000fc60003f05270 */
/*01c0*/ @!P1 STS [R19.X4+0x18], R6 ; /* 0x0000180613009388 */
/* 0x0101e20000004800 */
/*01d0*/ IADD3 R25, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001197a10 */
/* 0x000fca0007f3e0ff */
/*01e0*/ IMAD.X R24, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff187624 */
/* 0x000fc800008e06ff */
/*01f0*/ @P0 BRA 0xa60 ; /* 0x0000086000000947 */
/* 0x000fea0003800000 */
/*0200*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff007624 */
/* 0x001fca00078e00ff */
/*0210*/ IADD3 R27, R0, 0x6, RZ ; /* 0x00000006001b7810 */
/* 0x000fc80007ffe0ff */
/*0220*/ ISETP.NE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fda0003f05270 */
/*0230*/ @!P0 BRA 0x970 ; /* 0x0000073000008947 */
/* 0x000fea0003800000 */
/*0240*/ IADD3 R0, R0, 0x5, RZ ; /* 0x0000000500007810 */
/* 0x000fe20007ffe0ff */
/*0250*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fe200078e00ff */
/*0260*/ LOP3.LUT R27, R27, 0x3, RZ, 0xc0, !PT ; /* 0x000000031b1b7812 */
/* 0x000fe400078ec0ff */
/*0270*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f06070 */
/*0280*/ @!P0 BRA 0x7c0 ; /* 0x0000053000008947 */
/* 0x000fea0003800000 */
/*0290*/ BSSY B6, 0x7c0 ; /* 0x0000052000067945 */
/* 0x000fe20003800000 */
/*02a0*/ IADD3 R18, -R27, c[0x0][0x0], RZ ; /* 0x000000001b127a10 */
/* 0x000fe20007ffe1ff */
/*02b0*/ IMAD.MOV.U32 R22, RZ, RZ, RZ ; /* 0x000000ffff167224 */
/* 0x000fe400078e00ff */
/*02c0*/ IMAD.MOV.U32 R17, RZ, RZ, RZ ; /* 0x000000ffff117224 */
/* 0x000fc600078e00ff */
/*02d0*/ LDS R0, [R22] ; /* 0x0000000016007984 */
/* 0x000e220000000800 */
/*02e0*/ MOV R26, 0x0 ; /* 0x00000000001a7802 */
/* 0x000fe20000000f00 */
/*02f0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0300*/ IADD3 R18, R18, -0x4, RZ ; /* 0xfffffffc12127810 */
/* 0x000fe20007ffe0ff */
/*0310*/ STL.64 [R1], R16 ; /* 0x0000001001007387 */
/* 0x0003e20000100a00 */
/*0320*/ LDC.64 R2, c[0x4][R26] ; /* 0x010000001a027b82 */
/* 0x0002a20000000a00 */
/*0330*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0340*/ ISETP.NE.AND P0, PT, R18, -0x6, PT ; /* 0xfffffffa1200780c */
/* 0x000fe20003f05270 */
/*0350*/ IMAD.MOV.U32 R6, RZ, RZ, R25 ; /* 0x000000ffff067224 */
/* 0x000fc400078e0019 */
/*0360*/ IMAD.MOV.U32 R7, RZ, RZ, R24 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0018 */
/*0370*/ P2R R28, PR, RZ, 0x1 ; /* 0x00000001ff1c7803 */
/* 0x000fe20000000000 */
/*0380*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0013e80000100800 */
/*0390*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x004fe20000000000 */
/*03a0*/ MOV R11, 0x410 ; /* 0x00000410000b7802 */
/* 0x000fe40000000f00 */
/*03b0*/ MOV R20, 0x390 ; /* 0x0000039000147802 */
/* 0x000fe40000000f00 */
/*03c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*03d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*03e0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*03f0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0400*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0410*/ LDS R0, [R22+0x4] ; /* 0x0000040016007984 */
/* 0x000e220000000800 */
/*0420*/ IADD3 R9, R17, 0x1, RZ ; /* 0x0000000111097810 */
/* 0x000fe20007ffe0ff */
/*0430*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0010 */
/*0440*/ LDC.64 R2, c[0x4][R26] ; /* 0x010000001a027b82 */
/* 0x0002a20000000a00 */
/*0450*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0460*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0470*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0003e20000100a00 */
/*0480*/ IMAD.MOV.U32 R6, RZ, RZ, R25 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0019 */
/*0490*/ IMAD.MOV.U32 R7, RZ, RZ, R24 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0018 */
/*04a0*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0013e80000100800 */
/*04b0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe20000000000 */
/*04c0*/ MOV R11, 0x530 ; /* 0x00000530000b7802 */
/* 0x000fc40000000f00 */
/*04d0*/ MOV R20, 0x4b0 ; /* 0x000004b000147802 */
/* 0x000fe40000000f00 */
/*04e0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*04f0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0500*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0510*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0520*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0530*/ LDS R0, [R22+0x8] ; /* 0x0000080016007984 */
/* 0x000e220000000800 */
/*0540*/ IADD3 R9, R17, 0x2, RZ ; /* 0x0000000211097810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0010 */
/*0560*/ LDC.64 R2, c[0x4][R26] ; /* 0x010000001a027b82 */
/* 0x0002a20000000a00 */
/*0570*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0580*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0590*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0003e20000100a00 */
/*05a0*/ IMAD.MOV.U32 R6, RZ, RZ, R25 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0019 */
/*05b0*/ IMAD.MOV.U32 R7, RZ, RZ, R24 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0018 */
/*05c0*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0013e80000100800 */
/*05d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe20000000000 */
/*05e0*/ MOV R11, 0x650 ; /* 0x00000650000b7802 */
/* 0x000fc40000000f00 */
/*05f0*/ MOV R20, 0x5d0 ; /* 0x000005d000147802 */
/* 0x000fe40000000f00 */
/*0600*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0610*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0620*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0630*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0640*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0650*/ LDS R0, [R22+0xc] ; /* 0x00000c0016007984 */
/* 0x000e220000000800 */
/*0660*/ IADD3 R9, R17, 0x3, RZ ; /* 0x0000000311097810 */
/* 0x000fe20007ffe0ff */
/*0670*/ IMAD.MOV.U32 R8, RZ, RZ, R16 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0010 */
/*0680*/ LDC.64 R2, c[0x4][R26] ; /* 0x010000001a027b82 */
/* 0x0002a20000000a00 */
/*0690*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*06a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*06b0*/ STL.64 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0003e20000100a00 */
/*06c0*/ IMAD.MOV.U32 R6, RZ, RZ, R25 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0019 */
/*06d0*/ IMAD.MOV.U32 R7, RZ, RZ, R24 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0018 */
/*06e0*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0013e80000100800 */
/*06f0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x006fe20000000000 */
/*0700*/ MOV R11, 0x770 ; /* 0x00000770000b7802 */
/* 0x000fc40000000f00 */
/*0710*/ MOV R20, 0x6f0 ; /* 0x000006f000147802 */
/* 0x000fe40000000f00 */
/*0720*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0730*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0740*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0750*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0760*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0770*/ ISETP.NE.AND P6, PT, R28, RZ, PT ; /* 0x000000ff1c00720c */
/* 0x000fe40003fc5270 */
/*0780*/ IADD3 R22, R22, 0x10, RZ ; /* 0x0000001016167810 */
/* 0x000fe40007ffe0ff */
/*0790*/ IADD3 R17, R17, 0x4, RZ ; /* 0x0000000411117810 */
/* 0x000fd20007ffe0ff */
/*07a0*/ @P6 BRA 0x2d0 ; /* 0xfffffb2000006947 */
/* 0x000fea000383ffff */
/*07b0*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*07c0*/ ISETP.NE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fe20003f05270 */
/*07d0*/ BSSY B6, 0x970 ; /* 0x0000019000067945 */
/* 0x000fd80003800000 */
/*07e0*/ @!P0 BRA 0x960 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*07f0*/ IMAD.SHL.U32 R18, R17, 0x4, RZ ; /* 0x0000000411127824 */
/* 0x000fca00078e00ff */
/*0800*/ LDS R0, [R18] ; /* 0x0000000012007984 */
/* 0x000e220000000800 */
/*0810*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0820*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0830*/ STL.64 [R1], R16 ; /* 0x0000001001007387 */
/* 0x0003e20000100a00 */
/*0840*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0850*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000ea20000000a00 */
/*0860*/ IMAD.MOV.U32 R6, RZ, RZ, R25 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0019 */
/*0870*/ IMAD.MOV.U32 R7, RZ, RZ, R24 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0018 */
/*0880*/ STL [R1+0x8], R0 ; /* 0x0000080001007387 */
/* 0x0013e80000100800 */
/*0890*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x004fe20000000000 */
/*08a0*/ MOV R11, 0x910 ; /* 0x00000910000b7802 */
/* 0x000fc40000000f00 */
/*08b0*/ MOV R20, 0x890 ; /* 0x0000089000147802 */
/* 0x000fe40000000f00 */
/*08c0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*08d0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*08e0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*08f0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0900*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x000fea0003c00000 */
/*0910*/ IADD3 R27, R27, -0x1, RZ ; /* 0xffffffff1b1b7810 */
/* 0x000fe40007ffe0ff */
/*0920*/ IADD3 R18, R18, 0x4, RZ ; /* 0x0000000412127810 */
/* 0x000fe40007ffe0ff */
/*0930*/ ISETP.NE.AND P0, PT, R27, RZ, PT ; /* 0x000000ff1b00720c */
/* 0x000fe40003f05270 */
/*0940*/ IADD3 R17, R17, 0x1, RZ ; /* 0x0000000111117810 */
/* 0x000fd60007ffe0ff */
/*0950*/ @P0 BRA 0x800 ; /* 0xfffffea000000947 */
/* 0x000fea000383ffff */
/*0960*/ BSYNC B6 ; /* 0x0000000000067941 */
/* 0x000fea0003800000 */
/*0970*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0980*/ STL [R1], R23 ; /* 0x0000001701007387 */
/* 0x0001e20000100800 */
/*0990*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x10] ; /* 0x01000400ff047624 */
/* 0x000fe400078e00ff */
/*09a0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x14] ; /* 0x01000500ff057624 */
/* 0x000fe400078e00ff */
/*09b0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e620000000a00 */
/*09c0*/ IMAD.MOV.U32 R6, RZ, RZ, R25 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0019 */
/*09d0*/ IMAD.MOV.U32 R7, RZ, RZ, R24 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0018 */
/*09e0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*09f0*/ MOV R11, 0xa60 ; /* 0x00000a60000b7802 */
/* 0x000fc40000000f00 */
/*0a00*/ MOV R20, 0x9e0 ; /* 0x000009e000147802 */
/* 0x000fe40000000f00 */
/*0a10*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0a20*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0a30*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0a40*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0a50*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x003fea0003c00000 */
/*0a60*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x001fe40003800000 */
/*0a70*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0a80*/ IMAD.MOV.U32 R18, RZ, RZ, R16 ; /* 0x000000ffff127224 */
/* 0x000fe200078e0010 */
/*0a90*/ MOV R17, 0x0 ; /* 0x0000000000117802 */
/* 0x000fc80000000f00 */
/*0aa0*/ STL.64 [R1], R18 ; /* 0x0000001201007387 */
/* 0x000fe80000100a00 */
/*0ab0*/ LDS R0, [R19.X4+0x4] ; /* 0x0000040013007984 */
/* 0x000fe80000004800 */
/*0ac0*/ LDS R3, [R19.X4] ; /* 0x0000000013037984 */
/* 0x000fe80000004800 */
/*0ad0*/ LDS R2, [R19.X4+0x8] ; /* 0x0000080013027984 */
/* 0x000e280000004800 */
/*0ae0*/ LDS R5, [R19.X4+0xc] ; /* 0x00000c0013057984 */
/* 0x000fe80000004800 */
/*0af0*/ LDS R4, [R19.X4+0x10] ; /* 0x0000100013047984 */
/* 0x000e680000004800 */
/*0b00*/ LDS R7, [R19.X4+0x14] ; /* 0x0000140013077984 */
/* 0x000fe80000004800 */
/*0b10*/ LDS R6, [R19.X4+0x18] ; /* 0x0000180013067984 */
/* 0x000ea20000004800 */
/*0b20*/ IADD3 R0, R2, R0, R3 ; /* 0x0000000002007210 */
/* 0x001fe20007ffe003 */
/*0b30*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fc600078e00ff */
/*0b40*/ IADD3 R0, R4, R5, R0 ; /* 0x0000000504007210 */
/* 0x002fe20007ffe000 */
/*0b50*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x18] ; /* 0x01000600ff047624 */
/* 0x000fe400078e00ff */
/*0b60*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x1c] ; /* 0x01000700ff057624 */
/* 0x000fe200078e00ff */
/*0b70*/ IADD3 R3, R6, R7, R0 ; /* 0x0000000706037210 */
/* 0x004fe20007ffe000 */
/*0b80*/ IMAD.MOV.U32 R6, RZ, RZ, R25 ; /* 0x000000ffff067224 */
/* 0x000fe400078e0019 */
/*0b90*/ IMAD.MOV.U32 R7, RZ, RZ, R24 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0018 */
/*0ba0*/ IMAD.HI R2, R3, -0x6db6db6d, R2 ; /* 0x9249249303027827 */
/* 0x000fca00078e0202 */
/*0bb0*/ SHF.R.U32.HI R3, RZ, 0x1f, R2 ; /* 0x0000001fff037819 */
/* 0x000fc80000011602 */
/*0bc0*/ LEA.HI.SX32 R26, R2, R3, 0x1e ; /* 0x00000003021a7211 */
/* 0x000fe400078ff2ff */
/*0bd0*/ LDC.64 R2, c[0x4][R17] ; /* 0x0100000011027b82 */
/* 0x0000660000000a00 */
/*0be0*/ STL [R1+0x8], R26 ; /* 0x0000081a01007387 */
/* 0x0001e40000100800 */
/*0bf0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe20000000000 */
/*0c00*/ MOV R11, 0xc70 ; /* 0x00000c70000b7802 */
/* 0x000fe40000000f00 */
/*0c10*/ MOV R20, 0xbf0 ; /* 0x00000bf000147802 */
/* 0x000fe40000000f00 */
/*0c20*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0c30*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0c40*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0c50*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0c60*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x003fea0003c00000 */
/*0c70*/ LDS R0, [R19.X4+0xc] ; /* 0x00000c0013007984 */
/* 0x000e220000004800 */
/*0c80*/ LEA R2, P0, R23, c[0x0][0x168], 0x2 ; /* 0x00005a0017027a11 */
/* 0x000fe200078010ff */
/*0c90*/ IMAD.MOV.U32 R10, RZ, RZ, R16 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0010 */
/*0ca0*/ IADD3 R22, R19, 0x3, RZ ; /* 0x0000000313167810 */
/* 0x000fe20007ffe0ff */
/*0cb0*/ IMAD.MOV.U32 R11, RZ, RZ, R19 ; /* 0x000000ffff0b7224 */
/* 0x000fe200078e0013 */
/*0cc0*/ LEA.HI.X R3, R23, c[0x0][0x16c], RZ, 0x2, P0 ; /* 0x00005b0017037a11 */
/* 0x000fe200000f14ff */
/*0cd0*/ LDC.64 R8, c[0x4][R17] ; /* 0x0100000011087b82 */
/* 0x0002a20000000a00 */
/*0ce0*/ IMAD.MOV.U32 R6, RZ, RZ, R25 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0019 */
/*0cf0*/ STL.64 [R1+0x8], R22 ; /* 0x0000081601007387 */
/* 0x0003e20000100a00 */
/*0d00*/ IMAD.MOV.U32 R7, RZ, RZ, R24 ; /* 0x000000ffff077224 */
/* 0x000fe400078e0018 */
/*0d10*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x20] ; /* 0x01000800ff047624 */
/* 0x000fe200078e00ff */
/*0d20*/ STL.64 [R1], R10 ; /* 0x0000000a01007387 */
/* 0x0003e20000100a00 */
/*0d30*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0x24] ; /* 0x01000900ff057624 */
/* 0x000fc600078e00ff */
/*0d40*/ STG.E [R2.64], R26 ; /* 0x0000001a02007986 */
/* 0x0003e8000c101924 */
/*0d50*/ STL [R1+0x10], R0 ; /* 0x0000100001007387 */
/* 0x0013e40000100800 */
/*0d60*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x006fe20000000000 */
/*0d70*/ MOV R11, 0xde0 ; /* 0x00000de0000b7802 */
/* 0x000fe40000000f00 */
/*0d80*/ MOV R20, 0xd60 ; /* 0x00000d6000147802 */
/* 0x000fe40000000f00 */
/*0d90*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0da0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fc40000000f00 */
/*0db0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*0dc0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*0dd0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x000fea0003c00000 */
/*0de0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0df0*/ BRA 0xdf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
#define MEM_DIM 64
#define RADIO 3
#define SIZE_BLOQUE 8
#define SIZE_GRID 8
#define RADIO 3
/*Programar una funcion que haga la media de numeros end GPU sin memoria compartida, en GPU con memoria compartida
y en CPU. Comparar los tiempos de ejecucion*/
__global__ void kernel_Shared(int *d_input, int *d_output)
{
int i;
int valorFinal = 0;
__shared__ int arrayValores[ MEM_DIM + RADIO + RADIO ];
//Inicializar el array para poder calcular las medias
arrayValores[threadIdx.x + RADIO] = 0;
//Inicializar las posiciones extras en el array
if (threadIdx.x < RADIO)
arrayValores[threadIdx.x] = 0;
if (threadIdx.x >= (SIZE_BLOQUE - RADIO))
arrayValores[threadIdx.x + RADIO] = 0;
/*
//En esta posicion los valores de arrayValores son correctos - Inicializados a 0
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor deberia ser 0: %d\n", arrayValores[i]);
}
*/
// Sincronizar todos los threads - Se puede omitir?
__syncthreads();
//Copiar los valores desde la memoria global a la memoria compartida
arrayValores[threadIdx.x + RADIO] = d_input[blockIdx.x * blockDim.x + threadIdx.x];
//
/*if (threadIdx.x == 0)
{
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor deberia ser 0: %d\n", arrayValores[i]);
}
}*/
//d_output[blockIdx.x * blockDim.x + threadIdx.x];
/*if (threadIdx.x == 0)
{
for(int i = 0; i < MEM_DIM + RADIO + RADIO; ++i)
printf(" %d", arrayValores[i]);
}
printf("\n");*/
//Copiar los valores extras
if (threadIdx.x < RADIO)
{
if (blockIdx.x > 0)
{
arrayValores[threadIdx.x] = d_input[(blockIdx.x * blockDim.x + threadIdx.x) - RADIO];
}
}
if (threadIdx.x >= (SIZE_BLOQUE - RADIO))
{
if (blockIdx.x < SIZE_GRID - 1)
{
arrayValores[threadIdx.x + RADIO + RADIO] = d_input[(blockIdx.x * blockDim.x + threadIdx.x) + RADIO];
}
}
if (threadIdx.x == 0)
{
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor kernel (%d, %d): %d\n", blockIdx.x, i, arrayValores[i]);
}
printf("%d\n\n", blockIdx.x * blockDim.x + threadIdx.x);
}
//Sincronizar los threads
__syncthreads();
//Hacer la media en el array de outputs
for (i = -RADIO; i <= RADIO; ++i)
{
valorFinal += arrayValores[(threadIdx.x + RADIO) + i];
}
valorFinal /= (RADIO + RADIO + 1);
printf("Valor en el thread actual (%d, %d): %d\n", blockIdx.x, threadIdx.x, valorFinal);
d_output[blockIdx.x * blockDim.x + threadIdx.x] = valorFinal;
printf("Bloque: %d -> Thread: %d -> PosicionArray: %d -> Posicion Array Global: %d -> Valor Guardado: %d\n", blockIdx.x, threadIdx.x, threadIdx.x + RADIO, blockIdx.x * blockDim.x + threadIdx.x, arrayValores[threadIdx.x + RADIO]);
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n = SIZE_BLOQUE * SIZE_GRID;
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_input;
int *d_output;
int *h_input;
int *h_output;
cudaMalloc((void **) &d_input, numBytes );
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
cudaMalloc((void **) &d_output, numBytes );
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
cudaMemset(d_output, 0, n);
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
h_input = (int *)malloc(numBytes);
h_output = (int *)malloc(numBytes);
for(int i = 0; i < n; ++i)
h_input[i] = i;
cudaMemcpy (d_input, h_input, numBytes, cudaMemcpyHostToDevice);
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
dim3 blockSize(SIZE_BLOQUE);
dim3 gridSize(SIZE_GRID);
tiempoInicio = tiempo();
kernel_Shared <<<gridSize, blockSize>>>(d_input, d_output);
cudaThreadSynchronize();
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda _1\n");
}
tiempoFin = tiempo();
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
cudaMemcpy (h_output, d_output, numBytes, cudaMemcpyDeviceToHost);
tiempoFin = tiempo();
if ( cudaSuccess != cudaGetLastError() )
printf( "Error! _2\n" );
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
for(int i = 0; i < n; ++i)
{
printf("%d - ", h_output[i]);
}
printf("\n\n\nDone.\n");
return 0;
} | .file "tmpxft_0006ed54_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6tiempov
.type _Z6tiempov, @function
_Z6tiempov:
.LFB2070:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z6tiempov, .-_Z6tiempov
.globl _Z35__device_stub__Z13kernel_SharedPiS_PiS_
.type _Z35__device_stub__Z13kernel_SharedPiS_PiS_, @function
_Z35__device_stub__Z13kernel_SharedPiS_PiS_:
.LFB2096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13kernel_SharedPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z35__device_stub__Z13kernel_SharedPiS_PiS_, .-_Z35__device_stub__Z13kernel_SharedPiS_PiS_
.globl _Z13kernel_SharedPiS_
.type _Z13kernel_SharedPiS_, @function
_Z13kernel_SharedPiS_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13kernel_SharedPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z13kernel_SharedPiS_, .-_Z13kernel_SharedPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nElementos a reservar: %d\n\n\n"
.LC2:
.string "Error de cuda\n"
.LC3:
.string "Error de cuda _1\n"
.LC4:
.string "Tiempo de inicio Kernel: %lf\n"
.LC5:
.string "Tiempo de fin Kernel: %lf\n"
.LC6:
.string "Tiempo total: %lf\n\n\n"
.LC7:
.string "Error! _2\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Tiempo de inicio Transferencia: %lf\n"
.align 8
.LC9:
.string "Tiempo de fin Transferencia: %lf\n"
.section .rodata.str1.1
.LC10:
.string "%d - "
.LC11:
.string "\n\n\nDone.\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
.L16:
leaq 24(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L30
.L17:
movl $64, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L31
.L18:
movl $256, %edi
call malloc@PLT
movq %rax, %rbx
movl $256, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L19:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L19
movl $1, %ecx
movl $256, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
.L20:
movl $8, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $8, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
call _Z6tiempov
movsd %xmm0, (%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L21:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L34
.L22:
call _Z6tiempov
movsd %xmm0, 8(%rsp)
movsd (%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm1
subsd (%rsp), %xmm1
movapd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z6tiempov
movsd %xmm0, (%rsp)
movl $2, %ecx
movl $256, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call _Z6tiempov
movsd %xmm0, 8(%rsp)
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
.L23:
movsd (%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm2
subsd (%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $256, %rbp
leaq .LC10(%rip), %r12
.L24:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L30:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L31:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L32:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L33:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z13kernel_SharedPiS_PiS_
jmp .L21
.L34:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L35:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z13kernel_SharedPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_SharedPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
#define MEM_DIM 64
#define RADIO 3
#define SIZE_BLOQUE 8
#define SIZE_GRID 8
#define RADIO 3
/*Programar una funcion que haga la media de numeros end GPU sin memoria compartida, en GPU con memoria compartida
y en CPU. Comparar los tiempos de ejecucion*/
__global__ void kernel_Shared(int *d_input, int *d_output)
{
int i;
int valorFinal = 0;
__shared__ int arrayValores[ MEM_DIM + RADIO + RADIO ];
//Inicializar el array para poder calcular las medias
arrayValores[threadIdx.x + RADIO] = 0;
//Inicializar las posiciones extras en el array
if (threadIdx.x < RADIO)
arrayValores[threadIdx.x] = 0;
if (threadIdx.x >= (SIZE_BLOQUE - RADIO))
arrayValores[threadIdx.x + RADIO] = 0;
/*
//En esta posicion los valores de arrayValores son correctos - Inicializados a 0
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor deberia ser 0: %d\n", arrayValores[i]);
}
*/
// Sincronizar todos los threads - Se puede omitir?
__syncthreads();
//Copiar los valores desde la memoria global a la memoria compartida
arrayValores[threadIdx.x + RADIO] = d_input[blockIdx.x * blockDim.x + threadIdx.x];
//
/*if (threadIdx.x == 0)
{
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor deberia ser 0: %d\n", arrayValores[i]);
}
}*/
//d_output[blockIdx.x * blockDim.x + threadIdx.x];
/*if (threadIdx.x == 0)
{
for(int i = 0; i < MEM_DIM + RADIO + RADIO; ++i)
printf(" %d", arrayValores[i]);
}
printf("\n");*/
//Copiar los valores extras
if (threadIdx.x < RADIO)
{
if (blockIdx.x > 0)
{
arrayValores[threadIdx.x] = d_input[(blockIdx.x * blockDim.x + threadIdx.x) - RADIO];
}
}
if (threadIdx.x >= (SIZE_BLOQUE - RADIO))
{
if (blockIdx.x < SIZE_GRID - 1)
{
arrayValores[threadIdx.x + RADIO + RADIO] = d_input[(blockIdx.x * blockDim.x + threadIdx.x) + RADIO];
}
}
if (threadIdx.x == 0)
{
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor kernel (%d, %d): %d\n", blockIdx.x, i, arrayValores[i]);
}
printf("%d\n\n", blockIdx.x * blockDim.x + threadIdx.x);
}
//Sincronizar los threads
__syncthreads();
//Hacer la media en el array de outputs
for (i = -RADIO; i <= RADIO; ++i)
{
valorFinal += arrayValores[(threadIdx.x + RADIO) + i];
}
valorFinal /= (RADIO + RADIO + 1);
printf("Valor en el thread actual (%d, %d): %d\n", blockIdx.x, threadIdx.x, valorFinal);
d_output[blockIdx.x * blockDim.x + threadIdx.x] = valorFinal;
printf("Bloque: %d -> Thread: %d -> PosicionArray: %d -> Posicion Array Global: %d -> Valor Guardado: %d\n", blockIdx.x, threadIdx.x, threadIdx.x + RADIO, blockIdx.x * blockDim.x + threadIdx.x, arrayValores[threadIdx.x + RADIO]);
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n = SIZE_BLOQUE * SIZE_GRID;
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_input;
int *d_output;
int *h_input;
int *h_output;
cudaMalloc((void **) &d_input, numBytes );
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
cudaMalloc((void **) &d_output, numBytes );
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
cudaMemset(d_output, 0, n);
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
h_input = (int *)malloc(numBytes);
h_output = (int *)malloc(numBytes);
for(int i = 0; i < n; ++i)
h_input[i] = i;
cudaMemcpy (d_input, h_input, numBytes, cudaMemcpyHostToDevice);
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda\n");
}
dim3 blockSize(SIZE_BLOQUE);
dim3 gridSize(SIZE_GRID);
tiempoInicio = tiempo();
kernel_Shared <<<gridSize, blockSize>>>(d_input, d_output);
cudaThreadSynchronize();
if(cudaSuccess != cudaGetLastError())
{
printf("Error de cuda _1\n");
}
tiempoFin = tiempo();
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
cudaMemcpy (h_output, d_output, numBytes, cudaMemcpyDeviceToHost);
tiempoFin = tiempo();
if ( cudaSuccess != cudaGetLastError() )
printf( "Error! _2\n" );
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
for(int i = 0; i < n; ++i)
{
printf("%d - ", h_output[i]);
}
printf("\n\n\nDone.\n");
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
#define MEM_DIM 64
#define RADIO 3
#define SIZE_BLOQUE 8
#define SIZE_GRID 8
#define RADIO 3
/*Programar una funcion que haga la media de numeros end GPU sin memoria compartida, en GPU con memoria compartida
y en CPU. Comparar los tiempos de ejecucion*/
__global__ void kernel_Shared(int *d_input, int *d_output)
{
int i;
int valorFinal = 0;
__shared__ int arrayValores[ MEM_DIM + RADIO + RADIO ];
//Inicializar el array para poder calcular las medias
arrayValores[threadIdx.x + RADIO] = 0;
//Inicializar las posiciones extras en el array
if (threadIdx.x < RADIO)
arrayValores[threadIdx.x] = 0;
if (threadIdx.x >= (SIZE_BLOQUE - RADIO))
arrayValores[threadIdx.x + RADIO] = 0;
/*
//En esta posicion los valores de arrayValores son correctos - Inicializados a 0
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor deberia ser 0: %d\n", arrayValores[i]);
}
*/
// Sincronizar todos los threads - Se puede omitir?
__syncthreads();
//Copiar los valores desde la memoria global a la memoria compartida
arrayValores[threadIdx.x + RADIO] = d_input[blockIdx.x * blockDim.x + threadIdx.x];
//
/*if (threadIdx.x == 0)
{
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor deberia ser 0: %d\n", arrayValores[i]);
}
}*/
//d_output[blockIdx.x * blockDim.x + threadIdx.x];
/*if (threadIdx.x == 0)
{
for(int i = 0; i < MEM_DIM + RADIO + RADIO; ++i)
printf(" %d", arrayValores[i]);
}
printf("\n");*/
//Copiar los valores extras
if (threadIdx.x < RADIO)
{
if (blockIdx.x > 0)
{
arrayValores[threadIdx.x] = d_input[(blockIdx.x * blockDim.x + threadIdx.x) - RADIO];
}
}
if (threadIdx.x >= (SIZE_BLOQUE - RADIO))
{
if (blockIdx.x < SIZE_GRID - 1)
{
arrayValores[threadIdx.x + RADIO + RADIO] = d_input[(blockIdx.x * blockDim.x + threadIdx.x) + RADIO];
}
}
if (threadIdx.x == 0)
{
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor kernel (%d, %d): %d\n", blockIdx.x, i, arrayValores[i]);
}
printf("%d\n\n", blockIdx.x * blockDim.x + threadIdx.x);
}
//Sincronizar los threads
__syncthreads();
//Hacer la media en el array de outputs
for (i = -RADIO; i <= RADIO; ++i)
{
valorFinal += arrayValores[(threadIdx.x + RADIO) + i];
}
valorFinal /= (RADIO + RADIO + 1);
printf("Valor en el thread actual (%d, %d): %d\n", blockIdx.x, threadIdx.x, valorFinal);
d_output[blockIdx.x * blockDim.x + threadIdx.x] = valorFinal;
printf("Bloque: %d -> Thread: %d -> PosicionArray: %d -> Posicion Array Global: %d -> Valor Guardado: %d\n", blockIdx.x, threadIdx.x, threadIdx.x + RADIO, blockIdx.x * blockDim.x + threadIdx.x, arrayValores[threadIdx.x + RADIO]);
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n = SIZE_BLOQUE * SIZE_GRID;
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_input;
int *d_output;
int *h_input;
int *h_output;
hipMalloc((void **) &d_input, numBytes );
if(hipSuccess != hipGetLastError())
{
printf("Error de cuda\n");
}
hipMalloc((void **) &d_output, numBytes );
if(hipSuccess != hipGetLastError())
{
printf("Error de cuda\n");
}
hipMemset(d_output, 0, n);
if(hipSuccess != hipGetLastError())
{
printf("Error de cuda\n");
}
h_input = (int *)malloc(numBytes);
h_output = (int *)malloc(numBytes);
for(int i = 0; i < n; ++i)
h_input[i] = i;
hipMemcpy (d_input, h_input, numBytes, hipMemcpyHostToDevice);
if(hipSuccess != hipGetLastError())
{
printf("Error de cuda\n");
}
dim3 blockSize(SIZE_BLOQUE);
dim3 gridSize(SIZE_GRID);
tiempoInicio = tiempo();
kernel_Shared <<<gridSize, blockSize>>>(d_input, d_output);
hipDeviceSynchronize();
if(hipSuccess != hipGetLastError())
{
printf("Error de cuda _1\n");
}
tiempoFin = tiempo();
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
hipMemcpy (h_output, d_output, numBytes, hipMemcpyDeviceToHost);
tiempoFin = tiempo();
if ( hipSuccess != hipGetLastError() )
printf( "Error! _2\n" );
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
for(int i = 0; i < n; ++i)
{
printf("%d - ", h_output[i]);
}
printf("\n\n\nDone.\n");
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <sys/time.h>
#define MEM_DIM 64
#define RADIO 3
#define SIZE_BLOQUE 8
#define SIZE_GRID 8
#define RADIO 3
/*Programar una funcion que haga la media de numeros end GPU sin memoria compartida, en GPU con memoria compartida
y en CPU. Comparar los tiempos de ejecucion*/
__global__ void kernel_Shared(int *d_input, int *d_output)
{
int i;
int valorFinal = 0;
__shared__ int arrayValores[ MEM_DIM + RADIO + RADIO ];
//Inicializar el array para poder calcular las medias
arrayValores[threadIdx.x + RADIO] = 0;
//Inicializar las posiciones extras en el array
if (threadIdx.x < RADIO)
arrayValores[threadIdx.x] = 0;
if (threadIdx.x >= (SIZE_BLOQUE - RADIO))
arrayValores[threadIdx.x + RADIO] = 0;
/*
//En esta posicion los valores de arrayValores son correctos - Inicializados a 0
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor deberia ser 0: %d\n", arrayValores[i]);
}
*/
// Sincronizar todos los threads - Se puede omitir?
__syncthreads();
//Copiar los valores desde la memoria global a la memoria compartida
arrayValores[threadIdx.x + RADIO] = d_input[blockIdx.x * blockDim.x + threadIdx.x];
//
/*if (threadIdx.x == 0)
{
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor deberia ser 0: %d\n", arrayValores[i]);
}
}*/
//d_output[blockIdx.x * blockDim.x + threadIdx.x];
/*if (threadIdx.x == 0)
{
for(int i = 0; i < MEM_DIM + RADIO + RADIO; ++i)
printf(" %d", arrayValores[i]);
}
printf("\n");*/
//Copiar los valores extras
if (threadIdx.x < RADIO)
{
if (blockIdx.x > 0)
{
arrayValores[threadIdx.x] = d_input[(blockIdx.x * blockDim.x + threadIdx.x) - RADIO];
}
}
if (threadIdx.x >= (SIZE_BLOQUE - RADIO))
{
if (blockIdx.x < SIZE_GRID - 1)
{
arrayValores[threadIdx.x + RADIO + RADIO] = d_input[(blockIdx.x * blockDim.x + threadIdx.x) + RADIO];
}
}
if (threadIdx.x == 0)
{
for(int i = 0; i < blockDim.x + RADIO + RADIO; ++i)
{
printf("Valor kernel (%d, %d): %d\n", blockIdx.x, i, arrayValores[i]);
}
printf("%d\n\n", blockIdx.x * blockDim.x + threadIdx.x);
}
//Sincronizar los threads
__syncthreads();
//Hacer la media en el array de outputs
for (i = -RADIO; i <= RADIO; ++i)
{
valorFinal += arrayValores[(threadIdx.x + RADIO) + i];
}
valorFinal /= (RADIO + RADIO + 1);
printf("Valor en el thread actual (%d, %d): %d\n", blockIdx.x, threadIdx.x, valorFinal);
d_output[blockIdx.x * blockDim.x + threadIdx.x] = valorFinal;
printf("Bloque: %d -> Thread: %d -> PosicionArray: %d -> Posicion Array Global: %d -> Valor Guardado: %d\n", blockIdx.x, threadIdx.x, threadIdx.x + RADIO, blockIdx.x * blockDim.x + threadIdx.x, arrayValores[threadIdx.x + RADIO]);
}
double tiempo( void )
{
struct timeval tv;
gettimeofday(&tv, NULL);
return (double) (tv.tv_usec) / 1000000 + (double) (tv.tv_sec);
}
int main(int argc, char** argv)
{
double tiempoInicio;
double tiempoFin;
int n = SIZE_BLOQUE * SIZE_GRID;
printf("\nElementos a reservar: %d\n\n\n", n);
int numBytes = n * sizeof(int);
int *d_input;
int *d_output;
int *h_input;
int *h_output;
hipMalloc((void **) &d_input, numBytes );
if(hipSuccess != hipGetLastError())
{
printf("Error de cuda\n");
}
hipMalloc((void **) &d_output, numBytes );
if(hipSuccess != hipGetLastError())
{
printf("Error de cuda\n");
}
hipMemset(d_output, 0, n);
if(hipSuccess != hipGetLastError())
{
printf("Error de cuda\n");
}
h_input = (int *)malloc(numBytes);
h_output = (int *)malloc(numBytes);
for(int i = 0; i < n; ++i)
h_input[i] = i;
hipMemcpy (d_input, h_input, numBytes, hipMemcpyHostToDevice);
if(hipSuccess != hipGetLastError())
{
printf("Error de cuda\n");
}
dim3 blockSize(SIZE_BLOQUE);
dim3 gridSize(SIZE_GRID);
tiempoInicio = tiempo();
kernel_Shared <<<gridSize, blockSize>>>(d_input, d_output);
hipDeviceSynchronize();
if(hipSuccess != hipGetLastError())
{
printf("Error de cuda _1\n");
}
tiempoFin = tiempo();
printf("Tiempo de inicio Kernel: %lf\n", tiempoInicio);
printf("Tiempo de fin Kernel: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
tiempoInicio = tiempo();
hipMemcpy (h_output, d_output, numBytes, hipMemcpyDeviceToHost);
tiempoFin = tiempo();
if ( hipSuccess != hipGetLastError() )
printf( "Error! _2\n" );
printf("Tiempo de inicio Transferencia: %lf\n", tiempoInicio);
printf("Tiempo de fin Transferencia: %lf\n", tiempoFin);
printf("Tiempo total: %lf\n\n\n", tiempoFin - tiempoInicio);
for(int i = 0; i < n; ++i)
{
printf("%d - ", h_output[i]);
}
printf("\n\n\nDone.\n");
return 0;
} | .text
.file "main.hip"
.globl _Z28__device_stub__kernel_SharedPiS_ # -- Begin function _Z28__device_stub__kernel_SharedPiS_
.p2align 4, 0x90
.type _Z28__device_stub__kernel_SharedPiS_,@function
_Z28__device_stub__kernel_SharedPiS_: # @_Z28__device_stub__kernel_SharedPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_SharedPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_SharedPiS_, .Lfunc_end0-_Z28__device_stub__kernel_SharedPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6tiempov
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z6tiempov
.p2align 4, 0x90
.type _Z6tiempov,@function
_Z6tiempov: # @_Z6tiempov
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI1_0(%rip), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6tiempov, .Lfunc_end1-_Z6tiempov
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
movl $64, %esi
xorl %eax, %eax
callq printf
leaq 48(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_2:
leaq 40(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_4:
movq 40(%rsp), %rdi
movl $64, %edx
xorl %esi, %esi
callq hipMemset
callq hipGetLastError
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_6:
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r14
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB2_7
# %bb.8:
movq 48(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB2_10
# %bb.9:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_10:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 24(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movabsq $4294967304, %rdi # imm = 0x100000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 24(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13kernel_SharedPiS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd (%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB2_14
# %bb.13:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB2_14:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movl $.L.str.3, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movq 40(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
callq hipGetLastError
testl %eax, %eax
je .LBB2_16
# %bb.15:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB2_16:
movl $.L.str.7, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.8, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_17: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $64, %r14
jne .LBB2_17
# %bb.18:
movl $.Lstr.6, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_SharedPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_SharedPiS_,@object # @_Z13kernel_SharedPiS_
.section .rodata,"a",@progbits
.globl _Z13kernel_SharedPiS_
.p2align 3, 0x0
_Z13kernel_SharedPiS_:
.quad _Z28__device_stub__kernel_SharedPiS_
.size _Z13kernel_SharedPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nElementos a reservar: %d\n\n\n"
.size .L.str, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Tiempo de inicio Kernel: %lf\n"
.size .L.str.3, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo de fin Kernel: %lf\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Tiempo total: %lf\n\n\n"
.size .L.str.5, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Tiempo de inicio Transferencia: %lf\n"
.size .L.str.7, 37
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Tiempo de fin Transferencia: %lf\n"
.size .L.str.8, 34
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d - "
.size .L.str.9, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13kernel_SharedPiS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.3,@object # @str.3
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.3:
.asciz "Error de cuda"
.size .Lstr.3, 14
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error de cuda _1"
.size .Lstr.4, 17
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error! _2"
.size .Lstr.5, 10
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "\n\n\nDone."
.size .Lstr.6, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_SharedPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_SharedPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006ed54_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2074:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2074:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6tiempov
.type _Z6tiempov, @function
_Z6tiempov:
.LFB2070:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $0, %esi
call gettimeofday@PLT
pxor %xmm0, %xmm0
cvtsi2sdq 8(%rsp), %xmm0
divsd .LC0(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq (%rsp), %xmm1
addsd %xmm1, %xmm0
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z6tiempov, .-_Z6tiempov
.globl _Z35__device_stub__Z13kernel_SharedPiS_PiS_
.type _Z35__device_stub__Z13kernel_SharedPiS_PiS_, @function
_Z35__device_stub__Z13kernel_SharedPiS_PiS_:
.LFB2096:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z13kernel_SharedPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z35__device_stub__Z13kernel_SharedPiS_PiS_, .-_Z35__device_stub__Z13kernel_SharedPiS_PiS_
.globl _Z13kernel_SharedPiS_
.type _Z13kernel_SharedPiS_, @function
_Z13kernel_SharedPiS_:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z13kernel_SharedPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z13kernel_SharedPiS_, .-_Z13kernel_SharedPiS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "\nElementos a reservar: %d\n\n\n"
.LC2:
.string "Error de cuda\n"
.LC3:
.string "Error de cuda _1\n"
.LC4:
.string "Tiempo de inicio Kernel: %lf\n"
.LC5:
.string "Tiempo de fin Kernel: %lf\n"
.LC6:
.string "Tiempo total: %lf\n\n\n"
.LC7:
.string "Error! _2\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC8:
.string "Tiempo de inicio Transferencia: %lf\n"
.align 8
.LC9:
.string "Tiempo de fin Transferencia: %lf\n"
.section .rodata.str1.1
.LC10:
.string "%d - "
.LC11:
.string "\n\n\nDone.\n"
.text
.globl main
.type main, @function
main:
.LFB2071:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $64, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 16(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L29
.L16:
leaq 24(%rsp), %rdi
movl $256, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L30
.L17:
movl $64, %edx
movl $0, %esi
movq 24(%rsp), %rdi
call cudaMemset@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L31
.L18:
movl $256, %edi
call malloc@PLT
movq %rax, %rbx
movl $256, %edi
call malloc@PLT
movq %rax, %rbp
movl $0, %eax
.L19:
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L19
movl $1, %ecx
movl $256, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L32
.L20:
movl $8, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $8, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
call _Z6tiempov
movsd %xmm0, (%rsp)
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L33
.L21:
call cudaThreadSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L34
.L22:
call _Z6tiempov
movsd %xmm0, 8(%rsp)
movsd (%rsp), %xmm0
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm1
subsd (%rsp), %xmm1
movapd %xmm1, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call _Z6tiempov
movsd %xmm0, (%rsp)
movl $2, %ecx
movl $256, %edx
movq 24(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call _Z6tiempov
movsd %xmm0, 8(%rsp)
call cudaGetLastError@PLT
testl %eax, %eax
jne .L35
.L23:
movsd (%rsp), %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd 8(%rsp), %xmm2
subsd (%rsp), %xmm2
movapd %xmm2, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rbx
addq $256, %rbp
leaq .LC10(%rip), %r12
.L24:
movl (%rbx), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L24
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L36
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L16
.L30:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L17
.L31:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L18
.L32:
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L20
.L33:
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z35__device_stub__Z13kernel_SharedPiS_PiS_
jmp .L21
.L34:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L22
.L35:
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L23
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2071:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z13kernel_SharedPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z13kernel_SharedPiS_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.globl _Z28__device_stub__kernel_SharedPiS_ # -- Begin function _Z28__device_stub__kernel_SharedPiS_
.p2align 4, 0x90
.type _Z28__device_stub__kernel_SharedPiS_,@function
_Z28__device_stub__kernel_SharedPiS_: # @_Z28__device_stub__kernel_SharedPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z13kernel_SharedPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z28__device_stub__kernel_SharedPiS_, .Lfunc_end0-_Z28__device_stub__kernel_SharedPiS_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z6tiempov
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z6tiempov
.p2align 4, 0x90
.type _Z6tiempov,@function
_Z6tiempov: # @_Z6tiempov
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
leaq 8(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 16(%rsp), %xmm1
divsd .LCPI1_0(%rip), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z6tiempov, .Lfunc_end1-_Z6tiempov
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $120, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $.L.str, %edi
movl $64, %esi
xorl %eax, %eax
callq printf
leaq 48(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_2:
leaq 40(%rsp), %rdi
movl $256, %esi # imm = 0x100
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
je .LBB2_4
# %bb.3:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_4:
movq 40(%rsp), %rdi
movl $64, %edx
xorl %esi, %esi
callq hipMemset
callq hipGetLastError
testl %eax, %eax
je .LBB2_6
# %bb.5:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_6:
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %r14
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_7: # =>This Inner Loop Header: Depth=1
movl %eax, (%r14,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB2_7
# %bb.8:
movq 48(%rsp), %rdi
movl $256, %edx # imm = 0x100
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
je .LBB2_10
# %bb.9:
movl $.Lstr.3, %edi
callq puts@PLT
.LBB2_10:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
cvtsi2sdq 24(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
movabsq $4294967304, %rdi # imm = 0x100000008
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_12
# %bb.11:
movq 48(%rsp), %rax
movq 40(%rsp), %rcx
movq %rax, 112(%rsp)
movq %rcx, 104(%rsp)
leaq 112(%rsp), %rax
movq %rax, 16(%rsp)
leaq 104(%rsp), %rax
movq %rax, 24(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z13kernel_SharedPiS_, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_12:
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd (%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 8(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
je .LBB2_14
# %bb.13:
movl $.Lstr.4, %edi
callq puts@PLT
.LBB2_14:
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
movl $.L.str.3, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.4, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, 8(%rsp) # 8-byte Spill
movq 40(%rsp), %rsi
movl $256, %edx # imm = 0x100
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
divsd .LCPI2_0(%rip), %xmm0
xorps %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm0, %xmm1
movsd %xmm1, (%rsp) # 8-byte Spill
callq hipGetLastError
testl %eax, %eax
je .LBB2_16
# %bb.15:
movl $.Lstr.5, %edi
callq puts@PLT
.LBB2_16:
movl $.L.str.7, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movl $.L.str.8, %edi
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
movb $1, %al
callq printf
movsd (%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
subsd 8(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_17: # =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
incq %r14
cmpq $64, %r14
jne .LBB2_17
# %bb.18:
movl $.Lstr.6, %edi
callq puts@PLT
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13kernel_SharedPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13kernel_SharedPiS_,@object # @_Z13kernel_SharedPiS_
.section .rodata,"a",@progbits
.globl _Z13kernel_SharedPiS_
.p2align 3, 0x0
_Z13kernel_SharedPiS_:
.quad _Z28__device_stub__kernel_SharedPiS_
.size _Z13kernel_SharedPiS_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nElementos a reservar: %d\n\n\n"
.size .L.str, 29
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Tiempo de inicio Kernel: %lf\n"
.size .L.str.3, 30
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Tiempo de fin Kernel: %lf\n"
.size .L.str.4, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Tiempo total: %lf\n\n\n"
.size .L.str.5, 21
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Tiempo de inicio Transferencia: %lf\n"
.size .L.str.7, 37
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Tiempo de fin Transferencia: %lf\n"
.size .L.str.8, 34
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "%d - "
.size .L.str.9, 6
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13kernel_SharedPiS_"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.3,@object # @str.3
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.3:
.asciz "Error de cuda"
.size .Lstr.3, 14
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Error de cuda _1"
.size .Lstr.4, 17
.type .Lstr.5,@object # @str.5
.Lstr.5:
.asciz "Error! _2"
.size .Lstr.5, 10
.type .Lstr.6,@object # @str.6
.Lstr.6:
.asciz "\n\n\nDone."
.size .Lstr.6, 9
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__kernel_SharedPiS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13kernel_SharedPiS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include "readfile.cuh"
using namespace std;
readfile::readfile()
{
already_open = 0;
buffer = new char [MAX_LINE_LENGTH];
if(!buffer){ cout<< "allocation error in readfile"<<endl; exit(0);}
result = new char [MAX_LINE_LENGTH];
if(!result){ cout<<"allocation error in readfile"<<endl; exit(0);}
}
void readfile::openinput(char *file)
{
if(!already_open){
fd=fopen(file,"r+");
if(fd==NULL){
cout<<"readfile::openinput: can't open file"<<endl;
exit(1);
}
already_open=1;
}
else{
rewind(fd);
}
}
void readfile::closeinput( void )
{
if(already_open){
int value=fclose( fd );
already_open=0;
if(value!=0)
{
cout<<"file not correctly closed"<<endl;
exit(0);
}
}
}
int readfile::setinput(char *a)
{
int m,n;
n = (int)strlen(a);
rewind(fd);
while(read_one_line()){
m=(int)strlen(buffer);
if(m==n){
if(strncmp(buffer,a,n)==0)return(1);
}
}
return(0);
}
char* readfile::setget(char *key, char *a)
{
int m,i,n,j=0;
n = (int)strlen(a);
// reset file pointer to the key word
if (!setinput(key)) {
printf( "\n readfile::setget: key word '%s' missing\n", key );
exit(-1);
}
while(read_one_line()){ // read lines following the key
m=(int)strlen(buffer);
if (strchr(buffer,38)) break; // '&' contained -> break
if(m>n+1) { // length sufficient
for(int i=0;i<m-n;i++) { // scan the line for variable name
if(strncmp(buffer+i,a,n)==0){ // if found, write it to result[]
if(buffer[n+i]=='='){
i++;
while(buffer[n+i+j]!=',' && n+i+j<m ) {
result[j]=buffer[n+i+j];
j++;
}
result[j]=0;
return(result); // and return pointer to result
}
}
}
}
}
printf(" readfile::setget: can't find name "); // otherwise: send error message
for(i=0;i<n;i++)putchar(a[i]);
printf(" following key word %s \n\n",key);
exit(1);
return(result);
}
char* readfile::getinput(char *a)
{
int m,n,i=0,j=0;
n = (int)strlen(a);
rewind(fd);
while(read_one_line()){ // read lines
m=(int)strlen(buffer);
if(m>n+1) { // length sufficient
for(i=0;i<m-n;i++) { // scan the line for variable name
if(strncmp(buffer+i,a,n)==0){ // if found, write it to result[]
if(buffer[n+i]=='='){
i++;
while(buffer[n+i+j]!=',' && n+i+j<m ) {
result[j]=buffer[n+i+j];
j++;
}
result[j]=0;
return(result); // and return pointer to result
}
}
}
}
}
printf("readfile::getinput: can't find name ");
for(i=0;i<n;i++)putchar(a[i]);
printf(" in input file \n");
exit(1);
return(result);
}
int readfile::read_one_line( void )
{
int i=0,c;
while(i<MAX_LINE_LENGTH){
c=getc(fd);
if(c==EOF)return(0);
else if(c=='\n'){
buffer[i++]=0;
return(1);
}
else if(c=='#'){
buffer[i++]=0;
while(getc(fd)!='\n');
return(1);
}
else if(c!=' '){
buffer[i++]=c;
}
}
printf("readfile::read_one_line: line too long\n");
exit(-1);
return(-1);
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <iostream>
#include "readfile.cuh"
using namespace std;
readfile::readfile()
{
already_open = 0;
buffer = new char [MAX_LINE_LENGTH];
if(!buffer){ cout<< "allocation error in readfile"<<endl; exit(0);}
result = new char [MAX_LINE_LENGTH];
if(!result){ cout<<"allocation error in readfile"<<endl; exit(0);}
}
void readfile::openinput(char *file)
{
if(!already_open){
fd=fopen(file,"r+");
if(fd==NULL){
cout<<"readfile::openinput: can't open file"<<endl;
exit(1);
}
already_open=1;
}
else{
rewind(fd);
}
}
void readfile::closeinput( void )
{
if(already_open){
int value=fclose( fd );
already_open=0;
if(value!=0)
{
cout<<"file not correctly closed"<<endl;
exit(0);
}
}
}
int readfile::setinput(char *a)
{
int m,n;
n = (int)strlen(a);
rewind(fd);
while(read_one_line()){
m=(int)strlen(buffer);
if(m==n){
if(strncmp(buffer,a,n)==0)return(1);
}
}
return(0);
}
char* readfile::setget(char *key, char *a)
{
int m,i,n,j=0;
n = (int)strlen(a);
// reset file pointer to the key word
if (!setinput(key)) {
printf( "\n readfile::setget: key word '%s' missing\n", key );
exit(-1);
}
while(read_one_line()){ // read lines following the key
m=(int)strlen(buffer);
if (strchr(buffer,38)) break; // '&' contained -> break
if(m>n+1) { // length sufficient
for(int i=0;i<m-n;i++) { // scan the line for variable name
if(strncmp(buffer+i,a,n)==0){ // if found, write it to result[]
if(buffer[n+i]=='='){
i++;
while(buffer[n+i+j]!=',' && n+i+j<m ) {
result[j]=buffer[n+i+j];
j++;
}
result[j]=0;
return(result); // and return pointer to result
}
}
}
}
}
printf(" readfile::setget: can't find name "); // otherwise: send error message
for(i=0;i<n;i++)putchar(a[i]);
printf(" following key word %s \n\n",key);
exit(1);
return(result);
}
char* readfile::getinput(char *a)
{
int m,n,i=0,j=0;
n = (int)strlen(a);
rewind(fd);
while(read_one_line()){ // read lines
m=(int)strlen(buffer);
if(m>n+1) { // length sufficient
for(i=0;i<m-n;i++) { // scan the line for variable name
if(strncmp(buffer+i,a,n)==0){ // if found, write it to result[]
if(buffer[n+i]=='='){
i++;
while(buffer[n+i+j]!=',' && n+i+j<m ) {
result[j]=buffer[n+i+j];
j++;
}
result[j]=0;
return(result); // and return pointer to result
}
}
}
}
}
printf("readfile::getinput: can't find name ");
for(i=0;i<n;i++)putchar(a[i]);
printf(" in input file \n");
exit(1);
return(result);
}
int readfile::read_one_line( void )
{
int i=0,c;
while(i<MAX_LINE_LENGTH){
c=getc(fd);
if(c==EOF)return(0);
else if(c=='\n'){
buffer[i++]=0;
return(1);
}
else if(c=='#'){
buffer[i++]=0;
while(getc(fd)!='\n');
return(1);
}
else if(c!=' '){
buffer[i++]=c;
}
}
printf("readfile::read_one_line: line too long\n");
exit(-1);
return(-1);
} | .file "tmpxft_0009db92_00000000-6_readfile.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3680:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3680:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN8readfileC2Ev
.type _ZN8readfileC2Ev, @function
_ZN8readfileC2Ev:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $0, (%rdi)
movl $1000, %edi
call _Znam@PLT
movq %rax, 16(%rbx)
movl $1000, %edi
call _Znam@PLT
movq %rax, 24(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _ZN8readfileC2Ev, .-_ZN8readfileC2Ev
.globl _ZN8readfileC1Ev
.set _ZN8readfileC1Ev,_ZN8readfileC2Ev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r+"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "readfile::openinput: can't open file"
.text
.align 2
.globl _ZN8readfile9openinputEPc
.type _ZN8readfile9openinputEPc, @function
_ZN8readfile9openinputEPc:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpl $0, (%rdi)
jne .L6
movq %rsi, %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, 8(%rbx)
testq %rax, %rax
je .L10
movl $1, (%rbx)
jmp .L5
.L10:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L6:
movq 8(%rdi), %rdi
call rewind@PLT
.L5:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZN8readfile9openinputEPc, .-_ZN8readfile9openinputEPc
.section .rodata.str1.1
.LC2:
.string "file not correctly closed"
.text
.align 2
.globl _ZN8readfile10closeinputEv
.type _ZN8readfile10closeinputEv, @function
_ZN8readfile10closeinputEv:
.LFB3673:
.cfi_startproc
endbr64
cmpl $0, (%rdi)
jne .L20
ret
.L20:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
call fclose@PLT
movl $0, (%rbx)
testl %eax, %eax
jne .L21
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $25, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L22
cmpb $0, 56(%rbx)
je .L14
movzbl 67(%rbx), %esi
.L15:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %edi
call exit@PLT
.L22:
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.cfi_endproc
.LFE3673:
.size _ZN8readfile10closeinputEv, .-_ZN8readfile10closeinputEv
.section .rodata.str1.8
.align 8
.LC3:
.string "readfile::read_one_line: line too long\n"
.text
.align 2
.globl _ZN8readfile13read_one_lineEv
.type _ZN8readfile13read_one_lineEv, @function
_ZN8readfile13read_one_lineEv:
.LFB3677:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl $0, %ebp
.L24:
movl %ebp, %r12d
.L29:
cmpq $1000, %rbp
je .L35
movq 8(%rbx), %rdi
call getc@PLT
cmpl $-1, %eax
je .L31
cmpl $10, %eax
je .L36
cmpl $35, %eax
je .L37
cmpl $32, %eax
je .L29
movq 16(%rbx), %rdx
movb %al, (%rdx,%rbp)
addq $1, %rbp
jmp .L24
.L36:
movslq %r12d, %r12
movq 16(%rbx), %rax
movb $0, (%rax,%r12)
movl $1, %eax
jmp .L23
.L37:
movslq %r12d, %r12
movq 16(%rbx), %rax
movb $0, (%rax,%r12)
.L28:
movq 8(%rbx), %rdi
call getc@PLT
cmpl $10, %eax
jne .L28
movl $1, %eax
jmp .L23
.L35:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
movl $0, %eax
.L23:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZN8readfile13read_one_lineEv, .-_ZN8readfile13read_one_lineEv
.align 2
.globl _ZN8readfile8setinputEPc
.type _ZN8readfile8setinputEPc, @function
_ZN8readfile8setinputEPc:
.LFB3674:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbx
movq %rsi, %r12
movq %rsi, %rdi
call strlen@PLT
movl %eax, %ebp
movq 8(%rbx), %rdi
call rewind@PLT
movslq %ebp, %r13
.L43:
movq %rbx, %rdi
call _ZN8readfile13read_one_lineEv
testl %eax, %eax
je .L38
movq 16(%rbx), %r14
movq %r14, %rdi
call strlen@PLT
cmpl %eax, %ebp
jne .L43
movq %r13, %rdx
movq %r12, %rsi
movq %r14, %rdi
call strncmp@PLT
testl %eax, %eax
jne .L43
movl $1, %eax
.L38:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZN8readfile8setinputEPc, .-_ZN8readfile8setinputEPc
.section .rodata.str1.8
.align 8
.LC4:
.string "\n readfile::setget: key word '%s' missing\n"
.align 8
.LC5:
.string " readfile::setget: can't find name "
.section .rodata.str1.1
.LC6:
.string " following key word %s \n\n"
.text
.align 2
.globl _ZN8readfile6setgetEPcS0_
.type _ZN8readfile6setgetEPcS0_, @function
_ZN8readfile6setgetEPcS0_:
.LFB3675:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %r15
movq %rsi, 40(%rsp)
movq %rdx, %r14
movq %rdx, %rdi
call strlen@PLT
movq %rax, 8(%rsp)
movl %eax, %ebx
movl %eax, 36(%rsp)
movq %r15, %rsi
movq %r12, %rdi
call _ZN8readfile8setinputEPc
testl %eax, %eax
je .L62
leal 1(%rbx), %eax
movl %eax, 32(%rsp)
.L57:
movq %r12, %rdi
call _ZN8readfile13read_one_lineEv
testl %eax, %eax
je .L47
movq 16(%r12), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rbx
movq %rax, 24(%rsp)
movl %eax, 20(%rsp)
movl $38, %esi
movq %rbp, %rdi
call strchr@PLT
testq %rax, %rax
jne .L47
cmpl %ebx, 32(%rsp)
jge .L57
movl 24(%rsp), %r13d
movl 36(%rsp), %eax
subl %eax, %r13d
movslq %r13d, %r13
movl $0, %ebx
movslq %eax, %r15
jmp .L52
.L62:
movq 40(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L48:
addq $1, %rbx
cmpq %r13, %rbx
je .L57
.L52:
leaq 0(%rbp,%rbx), %rdi
movq %r15, %rdx
movq %r14, %rsi
call strncmp@PLT
testl %eax, %eax
jne .L48
movl 8(%rsp), %ecx
leal (%rbx,%rcx), %edx
movslq %edx, %rdx
cmpb $61, 0(%rbp,%rdx)
jne .L48
movq 8(%rsp), %rsi
leal 1(%rbx,%rsi), %edi
movslq %edi, %r8
movzbl 0(%rbp,%r8), %ecx
movl 24(%rsp), %esi
cmpl %esi, %edi
jge .L49
cmpb $44, %cl
je .L49
movl $0, %edx
addl $1, %edi
.L50:
movq 24(%r12), %rax
movb %cl, (%rax,%rdx)
movl %edx, %eax
movq %r8, %rcx
addq 16(%r12), %rcx
movzbl 1(%rdx,%rcx), %ecx
addq $1, %rdx
leal (%rdi,%rax), %esi
cmpl %esi, 20(%rsp)
jle .L56
cmpb $44, %cl
jne .L50
.L56:
addl $1, %eax
.L49:
cltq
movq 24(%r12), %rdx
movb $0, (%rdx,%rax)
movq 24(%r12), %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
testl %eax, %eax
jle .L54
movq %r14, %rbx
leal -1(%rax), %eax
leaq 1(%r14,%rax), %rbp
.L55:
movsbl (%rbx), %edi
movq stdout(%rip), %rsi
call putc@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L55
.L54:
movq 40(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3675:
.size _ZN8readfile6setgetEPcS0_, .-_ZN8readfile6setgetEPcS0_
.section .rodata.str1.8
.align 8
.LC7:
.string "readfile::getinput: can't find name "
.section .rodata.str1.1
.LC8:
.string " in input file \n"
.text
.align 2
.globl _ZN8readfile8getinputEPc
.type _ZN8readfile8getinputEPc, @function
_ZN8readfile8getinputEPc:
.LFB3676:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r14
movq %rsi, %rdi
call strlen@PLT
movq %rax, (%rsp)
movl %eax, %ebx
movl %eax, 28(%rsp)
movq 8(%r12), %rdi
call rewind@PLT
movl %ebx, %eax
addl $1, %eax
movl %eax, 24(%rsp)
.L79:
movq %r12, %rdi
call _ZN8readfile13read_one_lineEv
testl %eax, %eax
je .L82
movq 16(%r12), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, 16(%rsp)
movl %eax, 12(%rsp)
cmpl %eax, 24(%rsp)
jge .L79
movl 16(%rsp), %r13d
movl 28(%rsp), %eax
subl %eax, %r13d
movslq %r13d, %r13
movl $0, %ebx
movslq %eax, %r15
jmp .L71
.L67:
addq $1, %rbx
cmpq %r13, %rbx
je .L79
.L71:
leaq 0(%rbp,%rbx), %rdi
movq %r15, %rdx
movq %r14, %rsi
call strncmp@PLT
testl %eax, %eax
jne .L67
movl (%rsp), %ecx
leal (%rbx,%rcx), %edx
movslq %edx, %rdx
cmpb $61, 0(%rbp,%rdx)
jne .L67
movq (%rsp), %rsi
leal 1(%rbx,%rsi), %edi
movslq %edi, %r8
movzbl 0(%rbp,%r8), %ecx
movl 16(%rsp), %esi
cmpl %esi, %edi
jge .L68
cmpb $44, %cl
je .L68
movl $0, %edx
addl $1, %edi
.L69:
movq 24(%r12), %rax
movb %cl, (%rax,%rdx)
movl %edx, %eax
movq %rdx, %rcx
addq 16(%r12), %rcx
movzbl 1(%r8,%rcx), %ecx
addq $1, %rdx
leal (%rdi,%rax), %esi
cmpl %esi, 12(%rsp)
jle .L75
cmpb $44, %cl
jne .L69
.L75:
addl $1, %eax
.L68:
cltq
movq 24(%r12), %rdx
movb $0, (%rdx,%rax)
movq 24(%r12), %rax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq (%rsp), %rax
testl %eax, %eax
jle .L73
movq %r14, %rbx
leal -1(%rax), %eax
leaq 1(%r14,%rax), %rbp
.L74:
movsbl (%rbx), %edi
movq stdout(%rip), %rsi
call putc@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L74
.L73:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3676:
.size _ZN8readfile8getinputEPc, .-_ZN8readfile8getinputEPc
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include "readfile.cuh"
using namespace std;
readfile::readfile()
{
already_open = 0;
buffer = new char [MAX_LINE_LENGTH];
if(!buffer){ cout<< "allocation error in readfile"<<endl; exit(0);}
result = new char [MAX_LINE_LENGTH];
if(!result){ cout<<"allocation error in readfile"<<endl; exit(0);}
}
void readfile::openinput(char *file)
{
if(!already_open){
fd=fopen(file,"r+");
if(fd==NULL){
cout<<"readfile::openinput: can't open file"<<endl;
exit(1);
}
already_open=1;
}
else{
rewind(fd);
}
}
void readfile::closeinput( void )
{
if(already_open){
int value=fclose( fd );
already_open=0;
if(value!=0)
{
cout<<"file not correctly closed"<<endl;
exit(0);
}
}
}
int readfile::setinput(char *a)
{
int m,n;
n = (int)strlen(a);
rewind(fd);
while(read_one_line()){
m=(int)strlen(buffer);
if(m==n){
if(strncmp(buffer,a,n)==0)return(1);
}
}
return(0);
}
char* readfile::setget(char *key, char *a)
{
int m,i,n,j=0;
n = (int)strlen(a);
// reset file pointer to the key word
if (!setinput(key)) {
printf( "\n readfile::setget: key word '%s' missing\n", key );
exit(-1);
}
while(read_one_line()){ // read lines following the key
m=(int)strlen(buffer);
if (strchr(buffer,38)) break; // '&' contained -> break
if(m>n+1) { // length sufficient
for(int i=0;i<m-n;i++) { // scan the line for variable name
if(strncmp(buffer+i,a,n)==0){ // if found, write it to result[]
if(buffer[n+i]=='='){
i++;
while(buffer[n+i+j]!=',' && n+i+j<m ) {
result[j]=buffer[n+i+j];
j++;
}
result[j]=0;
return(result); // and return pointer to result
}
}
}
}
}
printf(" readfile::setget: can't find name "); // otherwise: send error message
for(i=0;i<n;i++)putchar(a[i]);
printf(" following key word %s \n\n",key);
exit(1);
return(result);
}
char* readfile::getinput(char *a)
{
int m,n,i=0,j=0;
n = (int)strlen(a);
rewind(fd);
while(read_one_line()){ // read lines
m=(int)strlen(buffer);
if(m>n+1) { // length sufficient
for(i=0;i<m-n;i++) { // scan the line for variable name
if(strncmp(buffer+i,a,n)==0){ // if found, write it to result[]
if(buffer[n+i]=='='){
i++;
while(buffer[n+i+j]!=',' && n+i+j<m ) {
result[j]=buffer[n+i+j];
j++;
}
result[j]=0;
return(result); // and return pointer to result
}
}
}
}
}
printf("readfile::getinput: can't find name ");
for(i=0;i<n;i++)putchar(a[i]);
printf(" in input file \n");
exit(1);
return(result);
}
int readfile::read_one_line( void )
{
int i=0,c;
while(i<MAX_LINE_LENGTH){
c=getc(fd);
if(c==EOF)return(0);
else if(c=='\n'){
buffer[i++]=0;
return(1);
}
else if(c=='#'){
buffer[i++]=0;
while(getc(fd)!='\n');
return(1);
}
else if(c!=' '){
buffer[i++]=c;
}
}
printf("readfile::read_one_line: line too long\n");
exit(-1);
return(-1);
} | #define READFILE_H
#define MAX_LINE_LENGTH 1000
#define MAX_COL 50
///////////////////////////////////////////////////////////////
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
//------------------------------------------------
#ifndef READ
#define READ
class readfile{
public:
readfile();
void openinput(char*);
void closeinput( void );
int setinput( char* );
char* getinput( char* );
char* setget( char*, char* );
int read_one_line( void );
private:
int already_open;
FILE *fd;
char *buffer;
char *result;
};
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #define READFILE_H
#define MAX_LINE_LENGTH 1000
#define MAX_COL 50
///////////////////////////////////////////////////////////////
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
//------------------------------------------------
#ifndef READ
#define READ
class readfile{
public:
readfile();
void openinput(char*);
void closeinput( void );
int setinput( char* );
char* getinput( char* );
char* setget( char*, char* );
int read_one_line( void );
private:
int already_open;
FILE *fd;
char *buffer;
char *result;
};
#endif | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #define READFILE_H
#define MAX_LINE_LENGTH 1000
#define MAX_COL 50
///////////////////////////////////////////////////////////////
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
//------------------------------------------------
#ifndef READ
#define READ
class readfile{
public:
readfile();
void openinput(char*);
void closeinput( void );
int setinput( char* );
char* getinput( char* );
char* setget( char*, char* );
int read_one_line( void );
private:
int already_open;
FILE *fd;
char *buffer;
char *result;
};
#endif | .text
.file "readfile.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009db92_00000000-6_readfile.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3680:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3680:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.align 2
.globl _ZN8readfileC2Ev
.type _ZN8readfileC2Ev, @function
_ZN8readfileC2Ev:
.LFB3670:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movl $0, (%rdi)
movl $1000, %edi
call _Znam@PLT
movq %rax, 16(%rbx)
movl $1000, %edi
call _Znam@PLT
movq %rax, 24(%rbx)
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3670:
.size _ZN8readfileC2Ev, .-_ZN8readfileC2Ev
.globl _ZN8readfileC1Ev
.set _ZN8readfileC1Ev,_ZN8readfileC2Ev
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "r+"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "readfile::openinput: can't open file"
.text
.align 2
.globl _ZN8readfile9openinputEPc
.type _ZN8readfile9openinputEPc, @function
_ZN8readfile9openinputEPc:
.LFB3672:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
cmpl $0, (%rdi)
jne .L6
movq %rsi, %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
movq %rax, 8(%rbx)
testq %rax, %rax
je .L10
movl $1, (%rbx)
jmp .L5
.L10:
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $1, %edi
call exit@PLT
.L6:
movq 8(%rdi), %rdi
call rewind@PLT
.L5:
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3672:
.size _ZN8readfile9openinputEPc, .-_ZN8readfile9openinputEPc
.section .rodata.str1.1
.LC2:
.string "file not correctly closed"
.text
.align 2
.globl _ZN8readfile10closeinputEv
.type _ZN8readfile10closeinputEv, @function
_ZN8readfile10closeinputEv:
.LFB3673:
.cfi_startproc
endbr64
cmpl $0, (%rdi)
jne .L20
ret
.L20:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movq %rdi, %rbx
movq 8(%rdi), %rdi
call fclose@PLT
movl $0, (%rbx)
testl %eax, %eax
jne .L21
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $25, %edx
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rbx
movq %rbx, %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq 240(%rbx,%rax), %rbx
testq %rbx, %rbx
je .L22
cmpb $0, 56(%rbx)
je .L14
movzbl 67(%rbx), %esi
.L15:
movsbl %sil, %esi
leaq _ZSt4cout(%rip), %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
movl $0, %edi
call exit@PLT
.L22:
call _ZSt16__throw_bad_castv@PLT
.L14:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
jmp .L15
.cfi_endproc
.LFE3673:
.size _ZN8readfile10closeinputEv, .-_ZN8readfile10closeinputEv
.section .rodata.str1.8
.align 8
.LC3:
.string "readfile::read_one_line: line too long\n"
.text
.align 2
.globl _ZN8readfile13read_one_lineEv
.type _ZN8readfile13read_one_lineEv, @function
_ZN8readfile13read_one_lineEv:
.LFB3677:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
movq %rdi, %rbx
movl $0, %ebp
.L24:
movl %ebp, %r12d
.L29:
cmpq $1000, %rbp
je .L35
movq 8(%rbx), %rdi
call getc@PLT
cmpl $-1, %eax
je .L31
cmpl $10, %eax
je .L36
cmpl $35, %eax
je .L37
cmpl $32, %eax
je .L29
movq 16(%rbx), %rdx
movb %al, (%rdx,%rbp)
addq $1, %rbp
jmp .L24
.L36:
movslq %r12d, %r12
movq 16(%rbx), %rax
movb $0, (%rax,%r12)
movl $1, %eax
jmp .L23
.L37:
movslq %r12d, %r12
movq 16(%rbx), %rax
movb $0, (%rax,%r12)
.L28:
movq 8(%rbx), %rdi
call getc@PLT
cmpl $10, %eax
jne .L28
movl $1, %eax
jmp .L23
.L35:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L31:
movl $0, %eax
.L23:
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3677:
.size _ZN8readfile13read_one_lineEv, .-_ZN8readfile13read_one_lineEv
.align 2
.globl _ZN8readfile8setinputEPc
.type _ZN8readfile8setinputEPc, @function
_ZN8readfile8setinputEPc:
.LFB3674:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
movq %rdi, %rbx
movq %rsi, %r12
movq %rsi, %rdi
call strlen@PLT
movl %eax, %ebp
movq 8(%rbx), %rdi
call rewind@PLT
movslq %ebp, %r13
.L43:
movq %rbx, %rdi
call _ZN8readfile13read_one_lineEv
testl %eax, %eax
je .L38
movq 16(%rbx), %r14
movq %r14, %rdi
call strlen@PLT
cmpl %eax, %ebp
jne .L43
movq %r13, %rdx
movq %r12, %rsi
movq %r14, %rdi
call strncmp@PLT
testl %eax, %eax
jne .L43
movl $1, %eax
.L38:
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3674:
.size _ZN8readfile8setinputEPc, .-_ZN8readfile8setinputEPc
.section .rodata.str1.8
.align 8
.LC4:
.string "\n readfile::setget: key word '%s' missing\n"
.align 8
.LC5:
.string " readfile::setget: can't find name "
.section .rodata.str1.1
.LC6:
.string " following key word %s \n\n"
.text
.align 2
.globl _ZN8readfile6setgetEPcS0_
.type _ZN8readfile6setgetEPcS0_, @function
_ZN8readfile6setgetEPcS0_:
.LFB3675:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, %r15
movq %rsi, 40(%rsp)
movq %rdx, %r14
movq %rdx, %rdi
call strlen@PLT
movq %rax, 8(%rsp)
movl %eax, %ebx
movl %eax, 36(%rsp)
movq %r15, %rsi
movq %r12, %rdi
call _ZN8readfile8setinputEPc
testl %eax, %eax
je .L62
leal 1(%rbx), %eax
movl %eax, 32(%rsp)
.L57:
movq %r12, %rdi
call _ZN8readfile13read_one_lineEv
testl %eax, %eax
je .L47
movq 16(%r12), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, %rbx
movq %rax, 24(%rsp)
movl %eax, 20(%rsp)
movl $38, %esi
movq %rbp, %rdi
call strchr@PLT
testq %rax, %rax
jne .L47
cmpl %ebx, 32(%rsp)
jge .L57
movl 24(%rsp), %r13d
movl 36(%rsp), %eax
subl %eax, %r13d
movslq %r13d, %r13
movl $0, %ebx
movslq %eax, %r15
jmp .L52
.L62:
movq 40(%rsp), %rdx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L48:
addq $1, %rbx
cmpq %r13, %rbx
je .L57
.L52:
leaq 0(%rbp,%rbx), %rdi
movq %r15, %rdx
movq %r14, %rsi
call strncmp@PLT
testl %eax, %eax
jne .L48
movl 8(%rsp), %ecx
leal (%rbx,%rcx), %edx
movslq %edx, %rdx
cmpb $61, 0(%rbp,%rdx)
jne .L48
movq 8(%rsp), %rsi
leal 1(%rbx,%rsi), %edi
movslq %edi, %r8
movzbl 0(%rbp,%r8), %ecx
movl 24(%rsp), %esi
cmpl %esi, %edi
jge .L49
cmpb $44, %cl
je .L49
movl $0, %edx
addl $1, %edi
.L50:
movq 24(%r12), %rax
movb %cl, (%rax,%rdx)
movl %edx, %eax
movq %r8, %rcx
addq 16(%r12), %rcx
movzbl 1(%rdx,%rcx), %ecx
addq $1, %rdx
leal (%rdi,%rax), %esi
cmpl %esi, 20(%rsp)
jle .L56
cmpb $44, %cl
jne .L50
.L56:
addl $1, %eax
.L49:
cltq
movq 24(%r12), %rdx
movb $0, (%rdx,%rax)
movq 24(%r12), %rax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L47:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rax
testl %eax, %eax
jle .L54
movq %r14, %rbx
leal -1(%rax), %eax
leaq 1(%r14,%rax), %rbp
.L55:
movsbl (%rbx), %edi
movq stdout(%rip), %rsi
call putc@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L55
.L54:
movq 40(%rsp), %rdx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3675:
.size _ZN8readfile6setgetEPcS0_, .-_ZN8readfile6setgetEPcS0_
.section .rodata.str1.8
.align 8
.LC7:
.string "readfile::getinput: can't find name "
.section .rodata.str1.1
.LC8:
.string " in input file \n"
.text
.align 2
.globl _ZN8readfile8getinputEPc
.type _ZN8readfile8getinputEPc, @function
_ZN8readfile8getinputEPc:
.LFB3676:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r14
movq %rsi, %rdi
call strlen@PLT
movq %rax, (%rsp)
movl %eax, %ebx
movl %eax, 28(%rsp)
movq 8(%r12), %rdi
call rewind@PLT
movl %ebx, %eax
addl $1, %eax
movl %eax, 24(%rsp)
.L79:
movq %r12, %rdi
call _ZN8readfile13read_one_lineEv
testl %eax, %eax
je .L82
movq 16(%r12), %rbp
movq %rbp, %rdi
call strlen@PLT
movq %rax, 16(%rsp)
movl %eax, 12(%rsp)
cmpl %eax, 24(%rsp)
jge .L79
movl 16(%rsp), %r13d
movl 28(%rsp), %eax
subl %eax, %r13d
movslq %r13d, %r13
movl $0, %ebx
movslq %eax, %r15
jmp .L71
.L67:
addq $1, %rbx
cmpq %r13, %rbx
je .L79
.L71:
leaq 0(%rbp,%rbx), %rdi
movq %r15, %rdx
movq %r14, %rsi
call strncmp@PLT
testl %eax, %eax
jne .L67
movl (%rsp), %ecx
leal (%rbx,%rcx), %edx
movslq %edx, %rdx
cmpb $61, 0(%rbp,%rdx)
jne .L67
movq (%rsp), %rsi
leal 1(%rbx,%rsi), %edi
movslq %edi, %r8
movzbl 0(%rbp,%r8), %ecx
movl 16(%rsp), %esi
cmpl %esi, %edi
jge .L68
cmpb $44, %cl
je .L68
movl $0, %edx
addl $1, %edi
.L69:
movq 24(%r12), %rax
movb %cl, (%rax,%rdx)
movl %edx, %eax
movq %rdx, %rcx
addq 16(%r12), %rcx
movzbl 1(%r8,%rcx), %ecx
addq $1, %rdx
leal (%rdi,%rax), %esi
cmpl %esi, 12(%rsp)
jle .L75
cmpb $44, %cl
jne .L69
.L75:
addl $1, %eax
.L68:
cltq
movq 24(%r12), %rdx
movb $0, (%rdx,%rax)
movq 24(%r12), %rax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L82:
.cfi_restore_state
leaq .LC7(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movq (%rsp), %rax
testl %eax, %eax
jle .L73
movq %r14, %rbx
leal -1(%rax), %eax
leaq 1(%r14,%rax), %rbp
.L74:
movsbl (%rbx), %edi
movq stdout(%rip), %rsi
call putc@PLT
addq $1, %rbx
cmpq %rbp, %rbx
jne .L74
.L73:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.cfi_endproc
.LFE3676:
.size _ZN8readfile8getinputEPc, .-_ZN8readfile8getinputEPc
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3703:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3703:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "readfile.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda.h>
#include <sys/time.h>
#define N 1024
struct nodeAOS {
int a;
double b;
char c;
} *allnodesAOS;
struct nodeSOA {
int *a;
double *b;
char *c;
} allnodesSOA;
__global__ void dkernelaos(struct nodeAOS *allnodesAOS) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
allnodesAOS[id].a = id;
allnodesAOS[id].b = 0.0;
allnodesAOS[id].c = 'c';
}
__global__ void dkernelsoa(int *a, double *b, char *c) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
a[id] = id;
b[id] = 0.0;
c[id] = 'd';
}
double rtclock() {
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d", stat);
return(Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
void printtime(const char *str, double starttime, double endtime) {
printf("%s%3f seconds\n", str, endtime - starttime);
}
#define BLOCKSIZE 1024
int main(int nn, char *str[]) {
cudaMalloc(&allnodesAOS, N * sizeof(struct nodeAOS));
cudaMalloc(&allnodesSOA.a, N * sizeof(int));
cudaMalloc(&allnodesSOA.b, N * sizeof(double));
cudaMalloc(&allnodesSOA.c, N * sizeof(char));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
double starttime = rtclock();
dkernelaos<<<nblocks, BLOCKSIZE>>>(allnodesAOS);
cudaThreadSynchronize();
double endtime = rtclock();
printtime("AoS time: ", starttime, endtime);
starttime = rtclock();
dkernelsoa<<<nblocks, BLOCKSIZE>>>(allnodesSOA.a, allnodesSOA.b, allnodesSOA.c);
cudaThreadSynchronize();
endtime = rtclock();
printtime("SoA time: ", starttime, endtime);
return 0;
} | code for sm_80
Function : _Z10dkernelsoaPiPdPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fe200078e0200 */
/*0070*/ MOV R0, 0x64 ; /* 0x0000006400007802 */
/* 0x000fc80000000f00 */
/*0080*/ IMAD.WIDE.U32 R2, R9.reuse, R2, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x040fe200078e0002 */
/*0090*/ IADD3 R6, P0, R9, c[0x0][0x170], RZ ; /* 0x00005c0009067a10 */
/* 0x000fc60007f1e0ff */
/*00a0*/ IMAD.WIDE.U32 R4, R9, R4, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fe200078e0004 */
/*00b0*/ IADD3.X R7, RZ, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00ff077a10 */
/* 0x000fe200007fe4ff */
/*00c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101b04 */
/*00e0*/ STG.E.U8 [R6.64], R0 ; /* 0x0000000006007986 */
/* 0x000fe2000c101104 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10dkernelaosP7nodeAOS
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fe200078e0200 */
/*0060*/ MOV R0, 0x63 ; /* 0x0000006300007802 */
/* 0x000fc80000000f00 */
/*0070*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0002 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*0090*/ STG.E.U8 [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101104 */
/*00a0*/ STG.E.64 [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda.h>
#include <sys/time.h>
#define N 1024
struct nodeAOS {
int a;
double b;
char c;
} *allnodesAOS;
struct nodeSOA {
int *a;
double *b;
char *c;
} allnodesSOA;
__global__ void dkernelaos(struct nodeAOS *allnodesAOS) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
allnodesAOS[id].a = id;
allnodesAOS[id].b = 0.0;
allnodesAOS[id].c = 'c';
}
__global__ void dkernelsoa(int *a, double *b, char *c) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
a[id] = id;
b[id] = 0.0;
c[id] = 'd';
}
double rtclock() {
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d", stat);
return(Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
void printtime(const char *str, double starttime, double endtime) {
printf("%s%3f seconds\n", str, endtime - starttime);
}
#define BLOCKSIZE 1024
int main(int nn, char *str[]) {
cudaMalloc(&allnodesAOS, N * sizeof(struct nodeAOS));
cudaMalloc(&allnodesSOA.a, N * sizeof(int));
cudaMalloc(&allnodesSOA.b, N * sizeof(double));
cudaMalloc(&allnodesSOA.c, N * sizeof(char));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
double starttime = rtclock();
dkernelaos<<<nblocks, BLOCKSIZE>>>(allnodesAOS);
cudaThreadSynchronize();
double endtime = rtclock();
printtime("AoS time: ", starttime, endtime);
starttime = rtclock();
dkernelsoa<<<nblocks, BLOCKSIZE>>>(allnodesSOA.a, allnodesSOA.b, allnodesSOA.c);
cudaThreadSynchronize();
endtime = rtclock();
printtime("SoA time: ", starttime, endtime);
return 0;
} | .file "tmpxft_00004861_00000000-6_soa.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%s%3f seconds\n"
.text
.globl _Z9printtimePKcdd
.type _Z9printtimePKcdd, @function
_Z9printtimePKcdd:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rdx
subsd %xmm0, %xmm1
movapd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9printtimePKcdd, .-_Z9printtimePKcdd
.globl _Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS
.type _Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS, @function
_Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10dkernelaosP7nodeAOS(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS, .-_Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS
.globl _Z10dkernelaosP7nodeAOS
.type _Z10dkernelaosP7nodeAOS, @function
_Z10dkernelaosP7nodeAOS:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10dkernelaosP7nodeAOS, .-_Z10dkernelaosP7nodeAOS
.globl _Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc
.type _Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc, @function
_Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10dkernelsoaPiPdPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc, .-_Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc
.globl _Z10dkernelsoaPiPdPc
.type _Z10dkernelsoaPiPdPc, @function
_Z10dkernelsoaPiPdPc:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10dkernelsoaPiPdPc, .-_Z10dkernelsoaPiPdPc
.section .rodata.str1.1
.LC3:
.string "AoS time: "
.LC4:
.string "SoA time: "
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $24576, %esi
leaq allnodesAOS(%rip), %rdi
call cudaMalloc@PLT
movl $4096, %esi
leaq allnodesSOA(%rip), %rdi
call cudaMalloc@PLT
movl $8192, %esi
leaq 8+allnodesSOA(%rip), %rdi
call cudaMalloc@PLT
movl $1024, %esi
leaq 16+allnodesSOA(%rip), %rdi
call cudaMalloc@PLT
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L28:
call cudaThreadSynchronize@PLT
call _Z7rtclockv
movapd %xmm0, %xmm1
movsd 8(%rsp), %xmm0
leaq .LC3(%rip), %rdi
call _Z9printtimePKcdd
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L29:
call cudaThreadSynchronize@PLT
call _Z7rtclockv
movapd %xmm0, %xmm1
movsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rdi
call _Z9printtimePKcdd
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq allnodesAOS(%rip), %rdi
call _Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS
jmp .L28
.L32:
movq 16+allnodesSOA(%rip), %rdx
movq 8+allnodesSOA(%rip), %rsi
movq allnodesSOA(%rip), %rdi
call _Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc
jmp .L29
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10dkernelsoaPiPdPc"
.LC6:
.string "_Z10dkernelaosP7nodeAOS"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10dkernelsoaPiPdPc(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10dkernelaosP7nodeAOS(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl allnodesSOA
.bss
.align 16
.type allnodesSOA, @object
.size allnodesSOA, 24
allnodesSOA:
.zero 24
.globl allnodesAOS
.align 8
.type allnodesAOS, @object
.size allnodesAOS, 8
allnodesAOS:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <sys/time.h>
#define N 1024
struct nodeAOS {
int a;
double b;
char c;
} *allnodesAOS;
struct nodeSOA {
int *a;
double *b;
char *c;
} allnodesSOA;
__global__ void dkernelaos(struct nodeAOS *allnodesAOS) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
allnodesAOS[id].a = id;
allnodesAOS[id].b = 0.0;
allnodesAOS[id].c = 'c';
}
__global__ void dkernelsoa(int *a, double *b, char *c) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
a[id] = id;
b[id] = 0.0;
c[id] = 'd';
}
double rtclock() {
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d", stat);
return(Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
void printtime(const char *str, double starttime, double endtime) {
printf("%s%3f seconds\n", str, endtime - starttime);
}
#define BLOCKSIZE 1024
int main(int nn, char *str[]) {
cudaMalloc(&allnodesAOS, N * sizeof(struct nodeAOS));
cudaMalloc(&allnodesSOA.a, N * sizeof(int));
cudaMalloc(&allnodesSOA.b, N * sizeof(double));
cudaMalloc(&allnodesSOA.c, N * sizeof(char));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
double starttime = rtclock();
dkernelaos<<<nblocks, BLOCKSIZE>>>(allnodesAOS);
cudaThreadSynchronize();
double endtime = rtclock();
printtime("AoS time: ", starttime, endtime);
starttime = rtclock();
dkernelsoa<<<nblocks, BLOCKSIZE>>>(allnodesSOA.a, allnodesSOA.b, allnodesSOA.c);
cudaThreadSynchronize();
endtime = rtclock();
printtime("SoA time: ", starttime, endtime);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define N 1024
struct nodeAOS {
int a;
double b;
char c;
} *allnodesAOS;
struct nodeSOA {
int *a;
double *b;
char *c;
} allnodesSOA;
__global__ void dkernelaos(struct nodeAOS *allnodesAOS) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
allnodesAOS[id].a = id;
allnodesAOS[id].b = 0.0;
allnodesAOS[id].c = 'c';
}
__global__ void dkernelsoa(int *a, double *b, char *c) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
a[id] = id;
b[id] = 0.0;
c[id] = 'd';
}
double rtclock() {
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d", stat);
return(Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
void printtime(const char *str, double starttime, double endtime) {
printf("%s%3f seconds\n", str, endtime - starttime);
}
#define BLOCKSIZE 1024
int main(int nn, char *str[]) {
hipMalloc(&allnodesAOS, N * sizeof(struct nodeAOS));
hipMalloc(&allnodesSOA.a, N * sizeof(int));
hipMalloc(&allnodesSOA.b, N * sizeof(double));
hipMalloc(&allnodesSOA.c, N * sizeof(char));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
double starttime = rtclock();
dkernelaos<<<nblocks, BLOCKSIZE>>>(allnodesAOS);
hipDeviceSynchronize();
double endtime = rtclock();
printtime("AoS time: ", starttime, endtime);
starttime = rtclock();
dkernelsoa<<<nblocks, BLOCKSIZE>>>(allnodesSOA.a, allnodesSOA.b, allnodesSOA.c);
hipDeviceSynchronize();
endtime = rtclock();
printtime("SoA time: ", starttime, endtime);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define N 1024
struct nodeAOS {
int a;
double b;
char c;
} *allnodesAOS;
struct nodeSOA {
int *a;
double *b;
char *c;
} allnodesSOA;
__global__ void dkernelaos(struct nodeAOS *allnodesAOS) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
allnodesAOS[id].a = id;
allnodesAOS[id].b = 0.0;
allnodesAOS[id].c = 'c';
}
__global__ void dkernelsoa(int *a, double *b, char *c) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
a[id] = id;
b[id] = 0.0;
c[id] = 'd';
}
double rtclock() {
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d", stat);
return(Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
void printtime(const char *str, double starttime, double endtime) {
printf("%s%3f seconds\n", str, endtime - starttime);
}
#define BLOCKSIZE 1024
int main(int nn, char *str[]) {
hipMalloc(&allnodesAOS, N * sizeof(struct nodeAOS));
hipMalloc(&allnodesSOA.a, N * sizeof(int));
hipMalloc(&allnodesSOA.b, N * sizeof(double));
hipMalloc(&allnodesSOA.c, N * sizeof(char));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
double starttime = rtclock();
dkernelaos<<<nblocks, BLOCKSIZE>>>(allnodesAOS);
hipDeviceSynchronize();
double endtime = rtclock();
printtime("AoS time: ", starttime, endtime);
starttime = rtclock();
dkernelsoa<<<nblocks, BLOCKSIZE>>>(allnodesSOA.a, allnodesSOA.b, allnodesSOA.c);
hipDeviceSynchronize();
endtime = rtclock();
printtime("SoA time: ", starttime, endtime);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10dkernelaosP7nodeAOS
.globl _Z10dkernelaosP7nodeAOS
.p2align 8
.type _Z10dkernelaosP7nodeAOS,@function
_Z10dkernelaosP7nodeAOS:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v0, 0x63 :: v_dual_mov_b32 v3, v2
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, v1, 24, s[0:1]
s_clause 0x2
global_store_b32 v[4:5], v1, off
global_store_b64 v[4:5], v[2:3], off offset:8
global_store_b8 v[4:5], v0, off offset:16
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10dkernelaosP7nodeAOS
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10dkernelaosP7nodeAOS, .Lfunc_end0-_Z10dkernelaosP7nodeAOS
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10dkernelsoaPiPdPc
.globl _Z10dkernelsoaPiPdPc
.p2align 8
.type _Z10dkernelsoaPiPdPc,@function
_Z10dkernelsoaPiPdPc:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v4, v3
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v0, 0x64
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_lshlrev_b64 v[7:8], 3, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_store_b32 v[5:6], v1, off
global_store_b64 v[7:8], v[3:4], off
global_store_b8 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10dkernelsoaPiPdPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10dkernelsoaPiPdPc, .Lfunc_end1-_Z10dkernelsoaPiPdPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
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.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10dkernelaosP7nodeAOS
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10dkernelaosP7nodeAOS.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10dkernelsoaPiPdPc
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10dkernelsoaPiPdPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <sys/time.h>
#define N 1024
struct nodeAOS {
int a;
double b;
char c;
} *allnodesAOS;
struct nodeSOA {
int *a;
double *b;
char *c;
} allnodesSOA;
__global__ void dkernelaos(struct nodeAOS *allnodesAOS) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
allnodesAOS[id].a = id;
allnodesAOS[id].b = 0.0;
allnodesAOS[id].c = 'c';
}
__global__ void dkernelsoa(int *a, double *b, char *c) {
unsigned id = blockIdx.x * blockDim.x + threadIdx.x;
a[id] = id;
b[id] = 0.0;
c[id] = 'd';
}
double rtclock() {
struct timezone Tzp;
struct timeval Tp;
int stat;
stat = gettimeofday(&Tp, &Tzp);
if (stat != 0) printf("Error return from gettimeofday: %d", stat);
return(Tp.tv_sec + Tp.tv_usec * 1.0e-6);
}
void printtime(const char *str, double starttime, double endtime) {
printf("%s%3f seconds\n", str, endtime - starttime);
}
#define BLOCKSIZE 1024
int main(int nn, char *str[]) {
hipMalloc(&allnodesAOS, N * sizeof(struct nodeAOS));
hipMalloc(&allnodesSOA.a, N * sizeof(int));
hipMalloc(&allnodesSOA.b, N * sizeof(double));
hipMalloc(&allnodesSOA.c, N * sizeof(char));
unsigned nblocks = ceil((float)N / BLOCKSIZE);
double starttime = rtclock();
dkernelaos<<<nblocks, BLOCKSIZE>>>(allnodesAOS);
hipDeviceSynchronize();
double endtime = rtclock();
printtime("AoS time: ", starttime, endtime);
starttime = rtclock();
dkernelsoa<<<nblocks, BLOCKSIZE>>>(allnodesSOA.a, allnodesSOA.b, allnodesSOA.c);
hipDeviceSynchronize();
endtime = rtclock();
printtime("SoA time: ", starttime, endtime);
return 0;
} | .text
.file "soa.hip"
.globl _Z25__device_stub__dkernelaosP7nodeAOS # -- Begin function _Z25__device_stub__dkernelaosP7nodeAOS
.p2align 4, 0x90
.type _Z25__device_stub__dkernelaosP7nodeAOS,@function
_Z25__device_stub__dkernelaosP7nodeAOS: # @_Z25__device_stub__dkernelaosP7nodeAOS
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10dkernelaosP7nodeAOS, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__dkernelaosP7nodeAOS, .Lfunc_end0-_Z25__device_stub__dkernelaosP7nodeAOS
.cfi_endproc
# -- End function
.globl _Z25__device_stub__dkernelsoaPiPdPc # -- Begin function _Z25__device_stub__dkernelsoaPiPdPc
.p2align 4, 0x90
.type _Z25__device_stub__dkernelsoaPiPdPc,@function
_Z25__device_stub__dkernelsoaPiPdPc: # @_Z25__device_stub__dkernelsoaPiPdPc
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10dkernelsoaPiPdPc, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__dkernelsoaPiPdPc, .Lfunc_end1-_Z25__device_stub__dkernelsoaPiPdPc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB2_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7rtclockv, .Lfunc_end2-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z9printtimePKcdd # -- Begin function _Z9printtimePKcdd
.p2align 4, 0x90
.type _Z9printtimePKcdd,@function
_Z9printtimePKcdd: # @_Z9printtimePKcdd
.cfi_startproc
# %bb.0:
movq %rdi, %rsi
subsd %xmm0, %xmm1
movl $.L.str.1, %edi
movapd %xmm1, %xmm0
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z9printtimePKcdd, .Lfunc_end3-_Z9printtimePKcdd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $allnodesAOS, %edi
movl $24576, %esi # imm = 0x6000
callq hipMalloc
movl $allnodesSOA, %edi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl $allnodesSOA+8, %edi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movl $allnodesSOA+16, %edi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rsp, %rsi
callq gettimeofday
testl %eax, %eax
je .LBB4_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_2: # %_Z7rtclockv.exit
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, 96(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
movabsq $4294967297, %rbx # imm = 0x100000001
mulsd .LCPI4_0(%rip), %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
leaq 1023(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq allnodesAOS(%rip), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10dkernelaosP7nodeAOS, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 96(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 56(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
movq %rsp, %rsi
callq gettimeofday
testl %eax, %eax
je .LBB4_6
# %bb.5:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_6: # %_Z7rtclockv.exit13
cvtsi2sdq 16(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movb $1, %al
callq printf
leaq 16(%rsp), %rdi
movq %rsp, %rsi
callq gettimeofday
testl %eax, %eax
je .LBB4_8
# %bb.7:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_8: # %_Z7rtclockv.exit15
movq 16(%rsp), %r15
movq 24(%rsp), %r12
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq allnodesSOA(%rip), %rax
movq allnodesSOA+8(%rip), %rcx
movq allnodesSOA+16(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rax
movq %rax, 24(%rsp)
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
movq %rsp, %rdi
leaq 80(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10dkernelsoaPiPdPc, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
movq %rsp, %rsi
callq gettimeofday
testl %eax, %eax
je .LBB4_12
# %bb.11:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_12: # %_Z7rtclockv.exit23
xorps %xmm1, %xmm1
cvtsi2sd %r12, %xmm1
movsd .LCPI4_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
cvtsi2sd %r15, %xmm3
cvtsi2sdq 16(%rsp), %xmm4
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
addsd %xmm1, %xmm3
mulsd %xmm2, %xmm0
addsd %xmm4, %xmm0
subsd %xmm3, %xmm0
movl $.L.str.1, %edi
movl $.L.str.3, %esi
movb $1, %al
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10dkernelaosP7nodeAOS, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10dkernelsoaPiPdPc, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type allnodesAOS,@object # @allnodesAOS
.bss
.globl allnodesAOS
.p2align 3, 0x0
allnodesAOS:
.quad 0
.size allnodesAOS, 8
.type allnodesSOA,@object # @allnodesSOA
.globl allnodesSOA
.p2align 3, 0x0
allnodesSOA:
.zero 24
.size allnodesSOA, 24
.type _Z10dkernelaosP7nodeAOS,@object # @_Z10dkernelaosP7nodeAOS
.section .rodata,"a",@progbits
.globl _Z10dkernelaosP7nodeAOS
.p2align 3, 0x0
_Z10dkernelaosP7nodeAOS:
.quad _Z25__device_stub__dkernelaosP7nodeAOS
.size _Z10dkernelaosP7nodeAOS, 8
.type _Z10dkernelsoaPiPdPc,@object # @_Z10dkernelsoaPiPdPc
.globl _Z10dkernelsoaPiPdPc
.p2align 3, 0x0
_Z10dkernelsoaPiPdPc:
.quad _Z25__device_stub__dkernelsoaPiPdPc
.size _Z10dkernelsoaPiPdPc, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s%3f seconds\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "AoS time: "
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "SoA time: "
.size .L.str.3, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10dkernelaosP7nodeAOS"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10dkernelsoaPiPdPc"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__dkernelaosP7nodeAOS
.addrsig_sym _Z25__device_stub__dkernelsoaPiPdPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym allnodesAOS
.addrsig_sym allnodesSOA
.addrsig_sym _Z10dkernelaosP7nodeAOS
.addrsig_sym _Z10dkernelsoaPiPdPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10dkernelsoaPiPdPc
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ HFMA2.MMA R4, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff047435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R9, R9, c[0x0][0x0], R0 ; /* 0x0000000009097a24 */
/* 0x001fe200078e0200 */
/*0070*/ MOV R0, 0x64 ; /* 0x0000006400007802 */
/* 0x000fc80000000f00 */
/*0080*/ IMAD.WIDE.U32 R2, R9.reuse, R2, c[0x0][0x160] ; /* 0x0000580009027625 */
/* 0x040fe200078e0002 */
/*0090*/ IADD3 R6, P0, R9, c[0x0][0x170], RZ ; /* 0x00005c0009067a10 */
/* 0x000fc60007f1e0ff */
/*00a0*/ IMAD.WIDE.U32 R4, R9, R4, c[0x0][0x168] ; /* 0x00005a0009047625 */
/* 0x000fe200078e0004 */
/*00b0*/ IADD3.X R7, RZ, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d00ff077a10 */
/* 0x000fe200007fe4ff */
/*00c0*/ STG.E [R2.64], R9 ; /* 0x0000000902007986 */
/* 0x000fe8000c101904 */
/*00d0*/ STG.E.64 [R4.64], RZ ; /* 0x000000ff04007986 */
/* 0x000fe8000c101b04 */
/*00e0*/ STG.E.U8 [R6.64], R0 ; /* 0x0000000006007986 */
/* 0x000fe2000c101104 */
/*00f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z10dkernelaosP7nodeAOS
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R2, -RZ, RZ, 0, 1.430511474609375e-06 ; /* 0x00000018ff027435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fe200078e0200 */
/*0060*/ MOV R0, 0x63 ; /* 0x0000006300007802 */
/* 0x000fc80000000f00 */
/*0070*/ IMAD.WIDE.U32 R2, R5, R2, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fca00078e0002 */
/*0080*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe8000c101904 */
/*0090*/ STG.E.U8 [R2.64+0x10], R0 ; /* 0x0000100002007986 */
/* 0x000fe8000c101104 */
/*00a0*/ STG.E.64 [R2.64+0x8], RZ ; /* 0x000008ff02007986 */
/* 0x000fe2000c101b04 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10dkernelaosP7nodeAOS
.globl _Z10dkernelaosP7nodeAOS
.p2align 8
.type _Z10dkernelaosP7nodeAOS,@function
_Z10dkernelaosP7nodeAOS:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_dual_mov_b32 v0, 0x63 :: v_dual_mov_b32 v3, v2
s_delay_alu instid0(VALU_DEP_3)
v_mad_u64_u32 v[4:5], null, v1, 24, s[0:1]
s_clause 0x2
global_store_b32 v[4:5], v1, off
global_store_b64 v[4:5], v[2:3], off offset:8
global_store_b8 v[4:5], v0, off offset:16
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10dkernelaosP7nodeAOS
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10dkernelaosP7nodeAOS, .Lfunc_end0-_Z10dkernelaosP7nodeAOS
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z10dkernelsoaPiPdPc
.globl _Z10dkernelsoaPiPdPc
.p2align 8
.type _Z10dkernelsoaPiPdPc,@function
_Z10dkernelsoaPiPdPc:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
v_mov_b32_e32 v3, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v4, v3
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v0, 0x64
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_lshlrev_b64 v[7:8], 3, v[1:2]
v_add_co_u32 v5, vcc_lo, s4, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
v_add_co_u32 v7, vcc_lo, s6, v7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_store_b32 v[5:6], v1, off
global_store_b64 v[7:8], v[3:4], off
global_store_b8 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10dkernelsoaPiPdPc
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z10dkernelsoaPiPdPc, .Lfunc_end1-_Z10dkernelsoaPiPdPc
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10dkernelaosP7nodeAOS
.private_segment_fixed_size: 0
.sgpr_count: 16
.sgpr_spill_count: 0
.symbol: _Z10dkernelaosP7nodeAOS.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10dkernelsoaPiPdPc
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10dkernelsoaPiPdPc.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00004861_00000000-6_soa.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Error return from gettimeofday: %d"
.text
.globl _Z7rtclockv
.type _Z7rtclockv, @function
_Z7rtclockv:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
testl %eax, %eax
jne .L7
.L4:
pxor %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LC1(%rip), %xmm0
pxor %xmm1, %xmm1
cvtsi2sdq 16(%rsp), %xmm1
addsd %xmm1, %xmm0
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
movl %eax, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L4
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z7rtclockv, .-_Z7rtclockv
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "%s%3f seconds\n"
.text
.globl _Z9printtimePKcdd
.type _Z9printtimePKcdd, @function
_Z9printtimePKcdd:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq %rdi, %rdx
subsd %xmm0, %xmm1
movapd %xmm1, %xmm0
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z9printtimePKcdd, .-_Z9printtimePKcdd
.globl _Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS
.type _Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS, @function
_Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS:
.LFB2084:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10dkernelaosP7nodeAOS(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS, .-_Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS
.globl _Z10dkernelaosP7nodeAOS
.type _Z10dkernelaosP7nodeAOS, @function
_Z10dkernelaosP7nodeAOS:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z10dkernelaosP7nodeAOS, .-_Z10dkernelaosP7nodeAOS
.globl _Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc
.type _Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc, @function
_Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc:
.LFB2086:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10dkernelsoaPiPdPc(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc, .-_Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc
.globl _Z10dkernelsoaPiPdPc
.type _Z10dkernelsoaPiPdPc, @function
_Z10dkernelsoaPiPdPc:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z10dkernelsoaPiPdPc, .-_Z10dkernelsoaPiPdPc
.section .rodata.str1.1
.LC3:
.string "AoS time: "
.LC4:
.string "SoA time: "
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movl $24576, %esi
leaq allnodesAOS(%rip), %rdi
call cudaMalloc@PLT
movl $4096, %esi
leaq allnodesSOA(%rip), %rdi
call cudaMalloc@PLT
movl $8192, %esi
leaq 8+allnodesSOA(%rip), %rdi
call cudaMalloc@PLT
movl $1024, %esi
leaq 16+allnodesSOA(%rip), %rdi
call cudaMalloc@PLT
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L28:
call cudaThreadSynchronize@PLT
call _Z7rtclockv
movapd %xmm0, %xmm1
movsd 8(%rsp), %xmm0
leaq .LC3(%rip), %rdi
call _Z9printtimePKcdd
call _Z7rtclockv
movsd %xmm0, 8(%rsp)
movl $1024, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L32
.L29:
call cudaThreadSynchronize@PLT
call _Z7rtclockv
movapd %xmm0, %xmm1
movsd 8(%rsp), %xmm0
leaq .LC4(%rip), %rdi
call _Z9printtimePKcdd
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
movq allnodesAOS(%rip), %rdi
call _Z37__device_stub__Z10dkernelaosP7nodeAOSP7nodeAOS
jmp .L28
.L32:
movq 16+allnodesSOA(%rip), %rdx
movq 8+allnodesSOA(%rip), %rsi
movq allnodesSOA(%rip), %rdi
call _Z34__device_stub__Z10dkernelsoaPiPdPcPiPdPc
jmp .L29
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z10dkernelsoaPiPdPc"
.LC6:
.string "_Z10dkernelaosP7nodeAOS"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2089:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z10dkernelsoaPiPdPc(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z10dkernelaosP7nodeAOS(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl allnodesSOA
.bss
.align 16
.type allnodesSOA, @object
.size allnodesSOA, 24
allnodesSOA:
.zero 24
.globl allnodesAOS
.align 8
.type allnodesAOS, @object
.size allnodesAOS, 8
allnodesAOS:
.zero 8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1598689907
.long 1051772663
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "soa.hip"
.globl _Z25__device_stub__dkernelaosP7nodeAOS # -- Begin function _Z25__device_stub__dkernelaosP7nodeAOS
.p2align 4, 0x90
.type _Z25__device_stub__dkernelaosP7nodeAOS,@function
_Z25__device_stub__dkernelaosP7nodeAOS: # @_Z25__device_stub__dkernelaosP7nodeAOS
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z10dkernelaosP7nodeAOS, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z25__device_stub__dkernelaosP7nodeAOS, .Lfunc_end0-_Z25__device_stub__dkernelaosP7nodeAOS
.cfi_endproc
# -- End function
.globl _Z25__device_stub__dkernelsoaPiPdPc # -- Begin function _Z25__device_stub__dkernelsoaPiPdPc
.p2align 4, 0x90
.type _Z25__device_stub__dkernelsoaPiPdPc,@function
_Z25__device_stub__dkernelsoaPiPdPc: # @_Z25__device_stub__dkernelsoaPiPdPc
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10dkernelsoaPiPdPc, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end1:
.size _Z25__device_stub__dkernelsoaPiPdPc, .Lfunc_end1-_Z25__device_stub__dkernelsoaPiPdPc
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z7rtclockv
.LCPI2_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl _Z7rtclockv
.p2align 4, 0x90
.type _Z7rtclockv,@function
_Z7rtclockv: # @_Z7rtclockv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
testl %eax, %eax
je .LBB2_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB2_2:
cvtsi2sdq (%rsp), %xmm1
cvtsi2sdq 8(%rsp), %xmm0
mulsd .LCPI2_0(%rip), %xmm0
addsd %xmm1, %xmm0
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z7rtclockv, .Lfunc_end2-_Z7rtclockv
.cfi_endproc
# -- End function
.globl _Z9printtimePKcdd # -- Begin function _Z9printtimePKcdd
.p2align 4, 0x90
.type _Z9printtimePKcdd,@function
_Z9printtimePKcdd: # @_Z9printtimePKcdd
.cfi_startproc
# %bb.0:
movq %rdi, %rsi
subsd %xmm0, %xmm1
movl $.L.str.1, %edi
movapd %xmm1, %xmm0
movb $1, %al
jmp printf # TAILCALL
.Lfunc_end3:
.size _Z9printtimePKcdd, .Lfunc_end3-_Z9printtimePKcdd
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI4_0:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $120, %rsp
.cfi_def_cfa_offset 160
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $allnodesAOS, %edi
movl $24576, %esi # imm = 0x6000
callq hipMalloc
movl $allnodesSOA, %edi
movl $4096, %esi # imm = 0x1000
callq hipMalloc
movl $allnodesSOA+8, %edi
movl $8192, %esi # imm = 0x2000
callq hipMalloc
movl $allnodesSOA+16, %edi
movl $1024, %esi # imm = 0x400
callq hipMalloc
leaq 16(%rsp), %rdi
movq %rsp, %rsi
callq gettimeofday
testl %eax, %eax
je .LBB4_2
# %bb.1:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_2: # %_Z7rtclockv.exit
cvtsi2sdq 16(%rsp), %xmm0
movsd %xmm0, 96(%rsp) # 8-byte Spill
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
movabsq $4294967297, %rbx # imm = 0x100000001
mulsd .LCPI4_0(%rip), %xmm0
movsd %xmm0, 56(%rsp) # 8-byte Spill
leaq 1023(%rbx), %r14
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq allnodesAOS(%rip), %rax
movq %rax, 80(%rsp)
leaq 80(%rsp), %rax
movq %rax, 48(%rsp)
leaq 16(%rsp), %rdi
movq %rsp, %rsi
leaq 72(%rsp), %rdx
leaq 64(%rsp), %rcx
callq __hipPopCallConfiguration
movq 16(%rsp), %rsi
movl 24(%rsp), %edx
movq (%rsp), %rcx
movl 8(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10dkernelaosP7nodeAOS, %edi
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movsd 56(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
addsd 96(%rsp), %xmm0 # 8-byte Folded Reload
movsd %xmm0, 56(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
movq %rsp, %rsi
callq gettimeofday
testl %eax, %eax
je .LBB4_6
# %bb.5:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_6: # %_Z7rtclockv.exit13
cvtsi2sdq 16(%rsp), %xmm1
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
mulsd .LCPI4_0(%rip), %xmm0
addsd %xmm1, %xmm0
subsd 56(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.1, %edi
movl $.L.str.2, %esi
movb $1, %al
callq printf
leaq 16(%rsp), %rdi
movq %rsp, %rsi
callq gettimeofday
testl %eax, %eax
je .LBB4_8
# %bb.7:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_8: # %_Z7rtclockv.exit15
movq 16(%rsp), %r15
movq 24(%rsp), %r12
movq %rbx, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_10
# %bb.9:
movq allnodesSOA(%rip), %rax
movq allnodesSOA+8(%rip), %rcx
movq allnodesSOA+16(%rip), %rdx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
movq %rdx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 16(%rsp)
leaq 64(%rsp), %rax
movq %rax, 24(%rsp)
leaq 48(%rsp), %rax
movq %rax, 32(%rsp)
movq %rsp, %rdi
leaq 80(%rsp), %rsi
leaq 112(%rsp), %rdx
leaq 104(%rsp), %rcx
callq __hipPopCallConfiguration
movq (%rsp), %rsi
movl 8(%rsp), %edx
movq 80(%rsp), %rcx
movl 88(%rsp), %r8d
leaq 16(%rsp), %r9
movl $_Z10dkernelsoaPiPdPc, %edi
pushq 104(%rsp)
.cfi_adjust_cfa_offset 8
pushq 120(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_10:
callq hipDeviceSynchronize
leaq 16(%rsp), %rdi
movq %rsp, %rsi
callq gettimeofday
testl %eax, %eax
je .LBB4_12
# %bb.11:
movl $.L.str, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
.LBB4_12: # %_Z7rtclockv.exit23
xorps %xmm1, %xmm1
cvtsi2sd %r12, %xmm1
movsd .LCPI4_0(%rip), %xmm2 # xmm2 = mem[0],zero
mulsd %xmm2, %xmm1
cvtsi2sd %r15, %xmm3
cvtsi2sdq 16(%rsp), %xmm4
xorps %xmm0, %xmm0
cvtsi2sdq 24(%rsp), %xmm0
addsd %xmm1, %xmm3
mulsd %xmm2, %xmm0
addsd %xmm4, %xmm0
subsd %xmm3, %xmm0
movl $.L.str.1, %edi
movl $.L.str.3, %esi
movb $1, %al
callq printf
xorl %eax, %eax
addq $120, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10dkernelaosP7nodeAOS, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10dkernelsoaPiPdPc, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type allnodesAOS,@object # @allnodesAOS
.bss
.globl allnodesAOS
.p2align 3, 0x0
allnodesAOS:
.quad 0
.size allnodesAOS, 8
.type allnodesSOA,@object # @allnodesSOA
.globl allnodesSOA
.p2align 3, 0x0
allnodesSOA:
.zero 24
.size allnodesSOA, 24
.type _Z10dkernelaosP7nodeAOS,@object # @_Z10dkernelaosP7nodeAOS
.section .rodata,"a",@progbits
.globl _Z10dkernelaosP7nodeAOS
.p2align 3, 0x0
_Z10dkernelaosP7nodeAOS:
.quad _Z25__device_stub__dkernelaosP7nodeAOS
.size _Z10dkernelaosP7nodeAOS, 8
.type _Z10dkernelsoaPiPdPc,@object # @_Z10dkernelsoaPiPdPc
.globl _Z10dkernelsoaPiPdPc
.p2align 3, 0x0
_Z10dkernelsoaPiPdPc:
.quad _Z25__device_stub__dkernelsoaPiPdPc
.size _Z10dkernelsoaPiPdPc, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Error return from gettimeofday: %d"
.size .L.str, 35
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%s%3f seconds\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "AoS time: "
.size .L.str.2, 11
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "SoA time: "
.size .L.str.3, 11
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z10dkernelaosP7nodeAOS"
.size .L__unnamed_1, 24
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10dkernelsoaPiPdPc"
.size .L__unnamed_2, 21
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__dkernelaosP7nodeAOS
.addrsig_sym _Z25__device_stub__dkernelsoaPiPdPc
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym allnodesAOS
.addrsig_sym allnodesSOA
.addrsig_sym _Z10dkernelaosP7nodeAOS
.addrsig_sym _Z10dkernelsoaPiPdPc
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <sys/time.h>
#define BLOCK_SIZE 512
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,cudaGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
typedef struct {
struct timeval startTime;
struct timeval endTime;
} Timer;
void startTime(Timer* timer) {
gettimeofday(&(timer->startTime), NULL);
}
void stopTime(Timer* timer) {
gettimeofday(&(timer->endTime), NULL);
}
float elapsedTime(Timer timer) {
return ((float) ((timer.endTime.tv_sec - timer.startTime.tv_sec) \
+ (timer.endTime.tv_usec - timer.startTime.tv_usec)/1.0e6));
}
//Split based on each bit
__global__ void split(unsigned int*in_d, unsigned int *out_d, unsigned int in_size,int bit_shift) {
unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
int bit = 0;
if (index < in_size) {
bit = in_d[index] & (1 << bit_shift);// get the value on each bit
bit = (bit > 0) ? 1 : 0;
out_d[index] = 1 - bit;
}
}
__global__ void exclusiveScan(unsigned int *out, unsigned int* in, unsigned int*sum, unsigned int inputSize) {
__shared__ unsigned int temp[2 * BLOCK_SIZE];
int start = 2 * blockIdx.x * blockDim.x;
int tx = threadIdx.x;
int index = 0;
if (start + tx < inputSize) {
temp[tx] = in[start + tx];
} else {
temp[tx] = 0;
}
if (start + tx + blockDim.x < inputSize) {
temp[tx + blockDim.x] = in[start + tx + blockDim.x];
} else {
temp[tx + blockDim.x] = 0;
}
__syncthreads();
// up-sweep phase
int stride = 1;
while(stride <= blockDim.x) {
index = (tx + 1) * 2 * stride - 1;
if (index < (2 * blockDim.x)) {
temp[index] += temp[index - stride];
}
stride *= 2;
__syncthreads();
}
// first store the reduction sum in sum array
// make it zero since it is exclusive scan
if (tx == 0) {
// sum array contains the prefix sum of each
// 2*blockDim blocks of element..
if (sum != NULL) {
sum[blockIdx.x] = temp[2*blockDim.x - 1];
}
temp[2*blockDim.x - 1] = 0;
}
//wait for thread zero to write
__syncthreads();
stride = blockDim.x;
index = 0;
unsigned int var = 0;
while(stride > 0) {
index = (2 * stride * (tx + 1)) - 1;
if (index < 2 * blockDim.x) {
var = temp[index];
temp[index] += temp[index - stride];
temp[index-stride] = var;
}
stride >>= 1;
__syncthreads();
}
// write the temp array to output
if (start + tx < inputSize) {
out[start + tx] = temp[tx];
}
if(start + tx + blockDim.x < inputSize) {
out[start + tx + blockDim.x] = temp[tx + blockDim.x];
}
}
// merge the scan blocks
__global__ void mergeScanBlocks(unsigned int *sum, unsigned int* output, int opSize) {
int index = 2 * blockDim.x * blockIdx.x + threadIdx.x;
if (index < opSize) {
output[index] += sum[blockIdx.x];
}
if (index + blockDim.x < opSize) {
output[index + blockDim.x] += sum[blockIdx.x];
}
}
void preScan(unsigned int *out, unsigned int *in, unsigned int in_size)
{
unsigned int numBlocks1 = in_size / BLOCK_SIZE;
if (in_size % BLOCK_SIZE) numBlocks1++;
int numBlocks2 = numBlocks1 / 2;
if(numBlocks1 % 2) numBlocks2++;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x = numBlocks2;
dimGrid.y = 1;
dimGrid.z = 1;
unsigned int*sumArr_d = NULL;
if (in_size > (2*BLOCK_SIZE)) {
// we need the sum auxilarry array only if numblocks2 > 1
cudaMalloc((void**)&sumArr_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
}
exclusiveScan<<<dimGrid, dimThreadBlock>>>(out, in, sumArr_d, in_size);
cudaDeviceSynchronize();
cudaCheckError();
if (in_size <= (2*BLOCK_SIZE)) {
// out has proper exclusive scan. return
return;
} else {
// now we need to perform exclusive scan on the auxilliary sum array
unsigned int *sumArr_scan_d;
cudaMalloc((void**)&sumArr_scan_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
preScan(sumArr_scan_d, sumArr_d, numBlocks2);
// sumAdd_scan_d now contains the exclusive scan op of individual blocks
// now just do a one-one addition of blocks
mergeScanBlocks<<<dimGrid,dimThreadBlock>>>(sumArr_scan_d, out, in_size);
cudaDeviceSynchronize();
cudaCheckError();
cudaFree(sumArr_d);
cudaFree(sumArr_scan_d);
}
}
//Define the destination index
__global__ void indexDefine(unsigned int *in_d, unsigned int *rev_bit_d,
unsigned int in_size, unsigned int last_input) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
int total_falses = in_d[in_size - 1] + last_input;
__syncthreads();
if (index < in_size) {
if (rev_bit_d[index] == 0) {
int val = in_d[index];
in_d[index] = index + 1 - val + total_falses;
}
}
}
//Scatter input using in_d address
__global__ void scatterElements(unsigned int *in_d, unsigned int *index_d, unsigned int *out_d, unsigned int in_size) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < in_size) {
unsigned int val = index_d[index];
if (val < in_size) {
out_d[val] = in_d[index];
}
}
}
void radix_sort(unsigned int *in_d, unsigned int *out_d, unsigned int *out_scan_d, unsigned int *in_h,unsigned int *out_scan_h, int num_elements) {
unsigned int *temp;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x =(int)(ceil(num_elements/(1.0 * dimThreadBlock.x)));
dimGrid.y = 1;
dimGrid.z = 1;
for (int i =0;i<32;i++) {
split<<<dimGrid, dimThreadBlock>>>(in_d,out_d,num_elements,i);
cudaDeviceSynchronize();
cudaCheckError();
preScan(out_scan_d, out_d, num_elements);
cudaDeviceSynchronize();
cudaCheckError();
indexDefine<<<dimGrid, dimThreadBlock>>>(out_scan_d, out_d, num_elements, in_h[num_elements - 1]);
cudaDeviceSynchronize();
cudaCheckError();
scatterElements<<<dimGrid, dimThreadBlock>>>(in_d, out_scan_d, out_d, num_elements);
cudaDeviceSynchronize();
cudaCheckError();
// swap pointers
temp = in_d;
in_d = out_d;
out_d = temp;
}
}
int compare(const void *a, const void *b) {
int a1 = *((unsigned int*)a);
int b1 = *((unsigned int*)b);
if (a1 == b1) return 0;
else if (a1 < b1) return -1;
else return 1;
}
int main(){
Timer timer;
unsigned int *in_h;
unsigned int *out_h;
unsigned int *out_d;
unsigned int *in_d;
unsigned int *out_scan_d;
unsigned int num_elements = 1000000;
in_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
out_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
unsigned int *out_scan_h = (unsigned int *)malloc(num_elements * sizeof(unsigned int));
cudaMalloc((void**)&in_d, num_elements * sizeof(unsigned int));
cudaCheckError();
cudaMalloc((void**)&out_d, num_elements * sizeof(unsigned int));
cudaCheckError();
cudaMalloc((void**)&out_scan_d, num_elements * sizeof(unsigned int ));
cudaCheckError();
cudaDeviceSynchronize();
//init array
for(int i = 0;i < num_elements;i++) {
in_h[i] = num_elements - 1 - i;
}
// Copy host variables to device ------------------------------------------
cudaMemcpy(in_d, in_h, num_elements * sizeof(unsigned int),
cudaMemcpyHostToDevice);
cudaCheckError();
cudaDeviceSynchronize();
// Launch kernel ----------------------------------------------------------
startTime(&timer);
radix_sort(in_d, out_d, out_scan_d, in_h, out_scan_h, num_elements);
cudaDeviceSynchronize();
cudaCheckError();
stopTime(&timer); printf("GPU Sort time: %f s\n", elapsedTime(timer));
cudaCheckError();
// Copy device variables from host ----------------------------------------
cudaMemcpy(out_h, out_d, num_elements * sizeof(unsigned int),
cudaMemcpyDeviceToHost);
cudaCheckError();
cudaDeviceSynchronize();
// Verify correctness -----------------------------------------------------
qsort(in_h, num_elements, sizeof(unsigned int),compare);
int flag = 0;
for (int i = 0;i < num_elements;i++) {
if (in_h[i] != out_h[i]) {
flag = 1;
break;
}
}
if (flag == 1) {
printf("test failed\n");
} else
printf("test passed\n");
// Free memory
cudaFree(in_d);
cudaFree(out_scan_d);
cudaFree(out_d);
free(in_h);
free(out_h);
return 0;
} | code for sm_80
Function : _Z15scatterElementsPjS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0207 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.GE.U32.AND P0, PT, R2, c[0x0][0x178], PT ; /* 0x00005e0002007a0c */
/* 0x004fda0003f06070 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*00d0*/ LEA R4, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000047a11 */
/* 0x000fc800078010ff */
/*00e0*/ LEA.HI.X R5, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000057a11 */
/* 0x000fcc00000f1403 */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0007 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z11indexDefinePjS_jj
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x1 ; /* 0x00000001ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0060*/ IADD3 R2, -R2, c[0x0][0x170], RZ ; /* 0x00005c0002027a10 */
/* 0x000fe20007ffe1ff */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fc800078e0203 */
/*0080*/ IMAD.WIDE.U32 R2, R2, R7, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe200078e0007 */
/*0090*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fc80003f06070 */
/*00a0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000168000c1e1900 */
/*00b0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x001fcc00078e0207 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*0120*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*0130*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*0140*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1900 */
/*0150*/ IADD3 R5, R5, c[0x0][0x174], R0 ; /* 0x00005d0005057a10 */
/* 0x020fc80007ffe000 */
/*0160*/ IADD3 R5, -R4, 0x1, R5 ; /* 0x0000000104057810 */
/* 0x004fca0007ffe105 */
/*0170*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0180*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0190*/ BRA 0x190; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z15mergeScanBlocksPjS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e220000002500 */
/*0020*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0030*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*0040*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe2000800063f */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ BSSY B0, 0x140 ; /* 0x000000d000007945 */
/* 0x000fe80003800000 */
/*0070*/ IMAD R4, R2, UR4, R3 ; /* 0x0000000402047c24 */
/* 0x001fe2000f8e0203 */
/*0080*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc40000000a00 */
/*0090*/ IMAD.WIDE.U32 R2, R2, R9, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fe400078e0009 */
/*00a0*/ ISETP.GE.AND P0, PT, R4.reuse, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x040fe40003f06270 */
/*00b0*/ IADD3 R6, R4, c[0x0][0x0], RZ ; /* 0x0000000004067a10 */
/* 0x000fc80007ffe0ff */
/*00c0*/ ISETP.GE.U32.AND P1, PT, R6, c[0x0][0x170], PT ; /* 0x00005c0006007a0c */
/* 0x000fce0003f26070 */
/*00d0*/ @P0 BRA 0x130 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*00e0*/ IMAD.WIDE R4, R4, R9, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0209 */
/*00f0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0110*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x004fca0007ffe0ff */
/*0120*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x0001e4000c101904 */
/*0130*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0140*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0150*/ IMAD.WIDE.U32 R4, R6, R9, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x001fe200078e0009 */
/*0160*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0170*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0180*/ IADD3 R7, R2, R7, RZ ; /* 0x0000000702077210 */
/* 0x004fca0007ffe0ff */
/*0190*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*01a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01b0*/ BRA 0x1b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z13exclusiveScanPjS_S_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R10, SR_CTAID.X ; /* 0x00000000000a7919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0040*/ IMAD.SHL.U32 R3, R10, 0x2, RZ ; /* 0x000000020a037824 */
/* 0x001fc800078e00ff */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x002fca00078e0202 */
/*0060*/ IADD3 R0, R3.reuse, c[0x0][0x0], RZ ; /* 0x0000000003007a10 */
/* 0x040fe40007ffe0ff */
/*0070*/ ISETP.GE.U32.AND P3, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe40003f66070 */
/*0080*/ ISETP.GE.U32.AND P4, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fd60003f86070 */
/*0090*/ @!P3 IMAD.MOV.U32 R6, RZ, RZ, 0x4 ; /* 0x00000004ff06b424 */
/* 0x000fe400078e00ff */
/*00a0*/ @!P4 IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff09c424 */
/* 0x000fe400078e00ff */
/*00b0*/ @!P3 IMAD.WIDE R6, R3, R6, c[0x0][0x168] ; /* 0x00005a000306b625 */
/* 0x000fc800078e0206 */
/*00c0*/ @!P4 IMAD.WIDE.U32 R8, R0, R9, c[0x0][0x168] ; /* 0x00005a000008c625 */
/* 0x000fe400078e0009 */
/*00d0*/ @!P3 LDG.E R7, [R6.64] ; /* 0x000000060607b981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ @!P4 LDG.E R9, [R8.64] ; /* 0x000000060809c981 */
/* 0x000ee2000c1e1900 */
/*00f0*/ ISETP.NE.AND P5, PT, RZ, c[0x0][0x0], PT ; /* 0x00000000ff007a0c */
/* 0x000fe20003fa5270 */
/*0100*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff057624 */
/* 0x000fe200078e00ff */
/*0110*/ IADD3 R4, R2, c[0x0][0x0], RZ ; /* 0x0000000002047a10 */
/* 0x000fe20007ffe0ff */
/*0120*/ @P3 STS [R2.X4], RZ ; /* 0x000000ff02003388 */
/* 0x0001e20000004800 */
/*0130*/ MOV R11, c[0x0][0x0] ; /* 0x00000000000b7a02 */
/* 0x000fc40000000f00 */
/*0140*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fe40003f05270 */
/*0150*/ ISETP.GE.AND P2, PT, R11, 0x1, PT ; /* 0x000000010b00780c */
/* 0x000fe40003f46270 */
/*0160*/ ISETP.GE.U32.AND P1, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f26070 */
/*0170*/ @!P3 STS [R2.X4], R7 ; /* 0x000000070200b388 */
/* 0x0041e80000004800 */
/*0180*/ @P4 STS [R4.X4], RZ ; /* 0x000000ff04004388 */
/* 0x0001e80000004800 */
/*0190*/ @!P4 STS [R4.X4], R9 ; /* 0x000000090400c388 */
/* 0x0081e80000004800 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ @!P5 BRA 0x2b0 ; /* 0x000000f00000d947 */
/* 0x000fea0003800000 */
/*01c0*/ LEA R6, R2, 0x2, 0x1 ; /* 0x0000000202067811 */
/* 0x001fe200078e08ff */
/*01d0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*01e0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fc40000000800 */
/*01f0*/ USHF.L.U32 UR4, UR4, 0x1, URZ ; /* 0x0000000104047899 */
/* 0x000fe4000800063f */
/*0200*/ IMAD R12, R6, R7, -0x1 ; /* 0xffffffff060c7424 */
/* 0x000fca00078e0207 */
/*0210*/ ISETP.GE.U32.AND P3, PT, R12, UR4, PT ; /* 0x000000040c007c0c */
/* 0x000fda000bf66070 */
/*0220*/ @!P3 IMAD.IADD R8, R12, 0x1, -R7 ; /* 0x000000010c08b824 */
/* 0x000fe200078e0a07 */
/*0230*/ @!P3 LDS R9, [R12.X4] ; /* 0x000000000c09b984 */
/* 0x000fe20000004800 */
/*0240*/ IMAD.SHL.U32 R7, R7, 0x2, RZ ; /* 0x0000000207077824 */
/* 0x000fc800078e00ff */
/*0250*/ @!P3 LDS R8, [R8.X4] ; /* 0x000000000808b984 */
/* 0x000e240000004800 */
/*0260*/ @!P3 IADD3 R9, R9, R8, RZ ; /* 0x000000080909b210 */
/* 0x001fca0007ffe0ff */
/*0270*/ @!P3 STS [R12.X4], R9 ; /* 0x000000090c00b388 */
/* 0x0001e80000004800 */
/*0280*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0290*/ ISETP.GT.U32.AND P3, PT, R7, c[0x0][0x0], PT ; /* 0x0000000007007a0c */
/* 0x000fda0003f64070 */
/*02a0*/ @!P3 BRA 0x200 ; /* 0xffffff500000b947 */
/* 0x001fea000383ffff */
/*02b0*/ BSSY B0, 0x370 ; /* 0x000000b000007945 */
/* 0x001fe20003800000 */
/*02c0*/ @P0 BRA 0x360 ; /* 0x0000009000000947 */
/* 0x000fea0003800000 */
/*02d0*/ ISETP.NE.U32.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe20003f05070 */
/*02e0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*02f0*/ USHF.L.U32 UR4, UR4, 0x3, URZ ; /* 0x0000000304047899 */
/* 0x000fe2000800063f */
/*0300*/ ISETP.NE.AND.EX P0, PT, RZ, c[0x0][0x174], PT, P0 ; /* 0x00005d00ff007a0c */
/* 0x000fda0003f05300 */
/*0310*/ @P0 LDS R9, [UR4+-0x4] ; /* 0xfffffc04ff090984 */
/* 0x000e220008000800 */
/*0320*/ @P0 IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff070424 */
/* 0x000fc600078e00ff */
/*0330*/ STS [UR4+-0x4], RZ ; /* 0xfffffcffff007988 */
/* 0x000fe20008000804 */
/*0340*/ @P0 IMAD.WIDE.U32 R6, R10, R7, c[0x0][0x170] ; /* 0x00005c000a060625 */
/* 0x000fca00078e0007 */
/*0350*/ @P0 STG.E [R6.64], R9 ; /* 0x0000000906000986 */
/* 0x0011e4000c101906 */
/*0360*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0370*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0380*/ @!P2 BRA 0x470 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0390*/ SHF.L.U32 R11, R11, 0x1, RZ ; /* 0x000000010b0b7819 */
/* 0x000fe400000006ff */
/*03a0*/ LEA R12, R2, 0x2, 0x1 ; /* 0x00000002020c7811 */
/* 0x000fca00078e08ff */
/*03b0*/ IMAD R10, R12, R5, -0x1 ; /* 0xffffffff0c0a7424 */
/* 0x000fca00078e0205 */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R10, R11, PT ; /* 0x0000000b0a00720c */
/* 0x000fda0003f06070 */
/*03d0*/ @!P0 IMAD.IADD R6, R10, 0x1, -R5.reuse ; /* 0x000000010a068824 */
/* 0x101fe200078e0a05 */
/*03e0*/ @!P0 LDS R8, [R10.X4] ; /* 0x000000000a088984 */
/* 0x000fe20000004800 */
/*03f0*/ SHF.R.U32.HI R5, RZ, 0x1, R5 ; /* 0x00000001ff057819 */
/* 0x000fc60000011605 */
/*0400*/ @!P0 LDS R7, [R6.X4] ; /* 0x0000000006078984 */
/* 0x000e240000004800 */
/*0410*/ @!P0 IMAD.IADD R7, R7, 0x1, R8 ; /* 0x0000000107078824 */
/* 0x001fca00078e0208 */
/*0420*/ @!P0 STS [R10.X4], R7 ; /* 0x000000070a008388 */
/* 0x0001e80000004800 */
/*0430*/ @!P0 STS [R6.X4], R8 ; /* 0x0000000806008388 */
/* 0x0001e80000004800 */
/*0440*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0450*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0460*/ @P0 BRA 0x3b0 ; /* 0xffffff4000000947 */
/* 0x001fea000383ffff */
/*0470*/ @!P1 LDS R5, [R2.X4] ; /* 0x0000000002059984 */
/* 0x000e620000004800 */
/*0480*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0490*/ @!P1 MOV R6, 0x4 ; /* 0x0000000400069802 */
/* 0x001fca0000000f00 */
/*04a0*/ @!P1 IMAD.WIDE R6, R3, R6, c[0x0][0x160] ; /* 0x0000580003069625 */
/* 0x000fca00078e0206 */
/*04b0*/ @!P1 STG.E [R6.64], R5 ; /* 0x0000000506009986 */
/* 0x0021e2000c101906 */
/*04c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*04d0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x001e220000004800 */
/*04e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*04f0*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0003 */
/*0500*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*0510*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0520*/ BRA 0x520; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0530*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0540*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0550*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0560*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0570*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z5splitPjS_ji
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE.U32 R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0005 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ UMOV UR4, 0x1 ; /* 0x0000000100047882 */
/* 0x000fe20000000000 */
/*00b0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fe200078e0005 */
/*00c0*/ ULDC UR5, c[0x0][0x174] ; /* 0x00005d0000057ab9 */
/* 0x000fe40000000800 */
/*00d0*/ USHF.L.U32 UR4, UR4, UR5, URZ ; /* 0x0000000504047299 */
/* 0x000fcc000800063f */
/*00e0*/ LOP3.LUT R0, R2, UR4, RZ, 0xc0, !PT ; /* 0x0000000402007c12 */
/* 0x004fc8000f8ec0ff */
/*00f0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fc80003f06270 */
/*0100*/ SEL R7, RZ, 0x1, P0 ; /* 0x00000001ff077807 */
/* 0x000fca0000000000 */
/*0110*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101906 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <sys/time.h>
#define BLOCK_SIZE 512
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,cudaGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
typedef struct {
struct timeval startTime;
struct timeval endTime;
} Timer;
void startTime(Timer* timer) {
gettimeofday(&(timer->startTime), NULL);
}
void stopTime(Timer* timer) {
gettimeofday(&(timer->endTime), NULL);
}
float elapsedTime(Timer timer) {
return ((float) ((timer.endTime.tv_sec - timer.startTime.tv_sec) \
+ (timer.endTime.tv_usec - timer.startTime.tv_usec)/1.0e6));
}
//Split based on each bit
__global__ void split(unsigned int*in_d, unsigned int *out_d, unsigned int in_size,int bit_shift) {
unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
int bit = 0;
if (index < in_size) {
bit = in_d[index] & (1 << bit_shift);// get the value on each bit
bit = (bit > 0) ? 1 : 0;
out_d[index] = 1 - bit;
}
}
__global__ void exclusiveScan(unsigned int *out, unsigned int* in, unsigned int*sum, unsigned int inputSize) {
__shared__ unsigned int temp[2 * BLOCK_SIZE];
int start = 2 * blockIdx.x * blockDim.x;
int tx = threadIdx.x;
int index = 0;
if (start + tx < inputSize) {
temp[tx] = in[start + tx];
} else {
temp[tx] = 0;
}
if (start + tx + blockDim.x < inputSize) {
temp[tx + blockDim.x] = in[start + tx + blockDim.x];
} else {
temp[tx + blockDim.x] = 0;
}
__syncthreads();
// up-sweep phase
int stride = 1;
while(stride <= blockDim.x) {
index = (tx + 1) * 2 * stride - 1;
if (index < (2 * blockDim.x)) {
temp[index] += temp[index - stride];
}
stride *= 2;
__syncthreads();
}
// first store the reduction sum in sum array
// make it zero since it is exclusive scan
if (tx == 0) {
// sum array contains the prefix sum of each
// 2*blockDim blocks of element..
if (sum != NULL) {
sum[blockIdx.x] = temp[2*blockDim.x - 1];
}
temp[2*blockDim.x - 1] = 0;
}
//wait for thread zero to write
__syncthreads();
stride = blockDim.x;
index = 0;
unsigned int var = 0;
while(stride > 0) {
index = (2 * stride * (tx + 1)) - 1;
if (index < 2 * blockDim.x) {
var = temp[index];
temp[index] += temp[index - stride];
temp[index-stride] = var;
}
stride >>= 1;
__syncthreads();
}
// write the temp array to output
if (start + tx < inputSize) {
out[start + tx] = temp[tx];
}
if(start + tx + blockDim.x < inputSize) {
out[start + tx + blockDim.x] = temp[tx + blockDim.x];
}
}
// merge the scan blocks
__global__ void mergeScanBlocks(unsigned int *sum, unsigned int* output, int opSize) {
int index = 2 * blockDim.x * blockIdx.x + threadIdx.x;
if (index < opSize) {
output[index] += sum[blockIdx.x];
}
if (index + blockDim.x < opSize) {
output[index + blockDim.x] += sum[blockIdx.x];
}
}
void preScan(unsigned int *out, unsigned int *in, unsigned int in_size)
{
unsigned int numBlocks1 = in_size / BLOCK_SIZE;
if (in_size % BLOCK_SIZE) numBlocks1++;
int numBlocks2 = numBlocks1 / 2;
if(numBlocks1 % 2) numBlocks2++;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x = numBlocks2;
dimGrid.y = 1;
dimGrid.z = 1;
unsigned int*sumArr_d = NULL;
if (in_size > (2*BLOCK_SIZE)) {
// we need the sum auxilarry array only if numblocks2 > 1
cudaMalloc((void**)&sumArr_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
}
exclusiveScan<<<dimGrid, dimThreadBlock>>>(out, in, sumArr_d, in_size);
cudaDeviceSynchronize();
cudaCheckError();
if (in_size <= (2*BLOCK_SIZE)) {
// out has proper exclusive scan. return
return;
} else {
// now we need to perform exclusive scan on the auxilliary sum array
unsigned int *sumArr_scan_d;
cudaMalloc((void**)&sumArr_scan_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
preScan(sumArr_scan_d, sumArr_d, numBlocks2);
// sumAdd_scan_d now contains the exclusive scan op of individual blocks
// now just do a one-one addition of blocks
mergeScanBlocks<<<dimGrid,dimThreadBlock>>>(sumArr_scan_d, out, in_size);
cudaDeviceSynchronize();
cudaCheckError();
cudaFree(sumArr_d);
cudaFree(sumArr_scan_d);
}
}
//Define the destination index
__global__ void indexDefine(unsigned int *in_d, unsigned int *rev_bit_d,
unsigned int in_size, unsigned int last_input) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
int total_falses = in_d[in_size - 1] + last_input;
__syncthreads();
if (index < in_size) {
if (rev_bit_d[index] == 0) {
int val = in_d[index];
in_d[index] = index + 1 - val + total_falses;
}
}
}
//Scatter input using in_d address
__global__ void scatterElements(unsigned int *in_d, unsigned int *index_d, unsigned int *out_d, unsigned int in_size) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < in_size) {
unsigned int val = index_d[index];
if (val < in_size) {
out_d[val] = in_d[index];
}
}
}
void radix_sort(unsigned int *in_d, unsigned int *out_d, unsigned int *out_scan_d, unsigned int *in_h,unsigned int *out_scan_h, int num_elements) {
unsigned int *temp;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x =(int)(ceil(num_elements/(1.0 * dimThreadBlock.x)));
dimGrid.y = 1;
dimGrid.z = 1;
for (int i =0;i<32;i++) {
split<<<dimGrid, dimThreadBlock>>>(in_d,out_d,num_elements,i);
cudaDeviceSynchronize();
cudaCheckError();
preScan(out_scan_d, out_d, num_elements);
cudaDeviceSynchronize();
cudaCheckError();
indexDefine<<<dimGrid, dimThreadBlock>>>(out_scan_d, out_d, num_elements, in_h[num_elements - 1]);
cudaDeviceSynchronize();
cudaCheckError();
scatterElements<<<dimGrid, dimThreadBlock>>>(in_d, out_scan_d, out_d, num_elements);
cudaDeviceSynchronize();
cudaCheckError();
// swap pointers
temp = in_d;
in_d = out_d;
out_d = temp;
}
}
int compare(const void *a, const void *b) {
int a1 = *((unsigned int*)a);
int b1 = *((unsigned int*)b);
if (a1 == b1) return 0;
else if (a1 < b1) return -1;
else return 1;
}
int main(){
Timer timer;
unsigned int *in_h;
unsigned int *out_h;
unsigned int *out_d;
unsigned int *in_d;
unsigned int *out_scan_d;
unsigned int num_elements = 1000000;
in_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
out_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
unsigned int *out_scan_h = (unsigned int *)malloc(num_elements * sizeof(unsigned int));
cudaMalloc((void**)&in_d, num_elements * sizeof(unsigned int));
cudaCheckError();
cudaMalloc((void**)&out_d, num_elements * sizeof(unsigned int));
cudaCheckError();
cudaMalloc((void**)&out_scan_d, num_elements * sizeof(unsigned int ));
cudaCheckError();
cudaDeviceSynchronize();
//init array
for(int i = 0;i < num_elements;i++) {
in_h[i] = num_elements - 1 - i;
}
// Copy host variables to device ------------------------------------------
cudaMemcpy(in_d, in_h, num_elements * sizeof(unsigned int),
cudaMemcpyHostToDevice);
cudaCheckError();
cudaDeviceSynchronize();
// Launch kernel ----------------------------------------------------------
startTime(&timer);
radix_sort(in_d, out_d, out_scan_d, in_h, out_scan_h, num_elements);
cudaDeviceSynchronize();
cudaCheckError();
stopTime(&timer); printf("GPU Sort time: %f s\n", elapsedTime(timer));
cudaCheckError();
// Copy device variables from host ----------------------------------------
cudaMemcpy(out_h, out_d, num_elements * sizeof(unsigned int),
cudaMemcpyDeviceToHost);
cudaCheckError();
cudaDeviceSynchronize();
// Verify correctness -----------------------------------------------------
qsort(in_h, num_elements, sizeof(unsigned int),compare);
int flag = 0;
for (int i = 0;i < num_elements;i++) {
if (in_h[i] != out_h[i]) {
flag = 1;
break;
}
}
if (flag == 1) {
printf("test failed\n");
} else
printf("test passed\n");
// Free memory
cudaFree(in_d);
cudaFree(out_scan_d);
cudaFree(out_d);
free(in_h);
free(out_h);
return 0;
} | .file "tmpxft_000346de_00000000-6_bit_based_radix_sort.cudafe1.cpp"
.text
#APP
#NO_APP
.globl _Z7comparePKvS0_
.type _Z7comparePKvS0_, @function
_Z7comparePKvS0_:
.LFB2062:
.cfi_startproc
endbr64
movl (%rdi), %ecx
movl (%rsi), %edx
movl $0, %eax
cmpl %edx, %ecx
je .L1
setge %al
movzbl %al, %eax
leal -1(%rax,%rax), %eax
.L1:
ret
.cfi_endproc
.LFE2062:
.size _Z7comparePKvS0_, .-_Z7comparePKvS0_
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2066:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2066:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9startTimeP5Timer
.type _Z9startTimeP5Timer, @function
_Z9startTimeP5Timer:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
call gettimeofday@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z9startTimeP5Timer, .-_Z9startTimeP5Timer
.globl _Z8stopTimeP5Timer
.type _Z8stopTimeP5Timer, @function
_Z8stopTimeP5Timer:
.LFB2058:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
addq $16, %rdi
movl $0, %esi
call gettimeofday@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z8stopTimeP5Timer, .-_Z8stopTimeP5Timer
.globl _Z11elapsedTime5Timer
.type _Z11elapsedTime5Timer, @function
_Z11elapsedTime5Timer:
.LFB2059:
.cfi_startproc
endbr64
movq 32(%rsp), %rax
subq 16(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
movq 24(%rsp), %rax
subq 8(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
ret
.cfi_endproc
.LFE2059:
.size _Z11elapsedTime5Timer, .-_Z11elapsedTime5Timer
.globl _Z28__device_stub__Z5splitPjS_jiPjS_ji
.type _Z28__device_stub__Z5splitPjS_jiPjS_ji, @function
_Z28__device_stub__Z5splitPjS_jiPjS_ji:
.LFB2088:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L16
.L12:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z5splitPjS_ji(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L12
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z28__device_stub__Z5splitPjS_jiPjS_ji, .-_Z28__device_stub__Z5splitPjS_jiPjS_ji
.globl _Z5splitPjS_ji
.type _Z5splitPjS_ji, @function
_Z5splitPjS_ji:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z5splitPjS_jiPjS_ji
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z5splitPjS_ji, .-_Z5splitPjS_ji
.globl _Z38__device_stub__Z13exclusiveScanPjS_S_jPjS_S_j
.type _Z38__device_stub__Z13exclusiveScanPjS_S_jPjS_S_j, @function
_Z38__device_stub__Z13exclusiveScanPjS_S_jPjS_S_j:
.LFB2090:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13exclusiveScanPjS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2090:
.size _Z38__device_stub__Z13exclusiveScanPjS_S_jPjS_S_j, .-_Z38__device_stub__Z13exclusiveScanPjS_S_jPjS_S_j
.globl _Z13exclusiveScanPjS_S_j
.type _Z13exclusiveScanPjS_S_j, @function
_Z13exclusiveScanPjS_S_j:
.LFB2091:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z13exclusiveScanPjS_S_jPjS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _Z13exclusiveScanPjS_S_j, .-_Z13exclusiveScanPjS_S_j
.globl _Z38__device_stub__Z15mergeScanBlocksPjS_iPjS_i
.type _Z38__device_stub__Z15mergeScanBlocksPjS_iPjS_i, @function
_Z38__device_stub__Z15mergeScanBlocksPjS_iPjS_i:
.LFB2092:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L32
.L28:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L33
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L32:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15mergeScanBlocksPjS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L28
.L33:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2092:
.size _Z38__device_stub__Z15mergeScanBlocksPjS_iPjS_i, .-_Z38__device_stub__Z15mergeScanBlocksPjS_iPjS_i
.globl _Z15mergeScanBlocksPjS_i
.type _Z15mergeScanBlocksPjS_i, @function
_Z15mergeScanBlocksPjS_i:
.LFB2093:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z15mergeScanBlocksPjS_iPjS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2093:
.size _Z15mergeScanBlocksPjS_i, .-_Z15mergeScanBlocksPjS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "/home/ubuntu/Datasets/stackv2/train-structured/rkzheng/parallel-radix-sort/master/bit_based_radix_sort.cu"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "Cuda failure %s:%d: '%s'\n"
.text
.globl _Z7preScanPjS_j
.type _Z7preScanPjS_j, @function
_Z7preScanPjS_j:
.LFB2060:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $48, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %r14
movl %edx, %ebp
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %edx, %eax
shrl $9, %eax
andl $511, %edx
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, %ebx
shrl %ebx
andl $1, %eax
cmpl $1, %eax
sbbl $-1, %ebx
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $512, 16(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ebx, %r13d
movl %ebx, 28(%rsp)
movq $0, (%rsp)
cmpl $1024, %ebp
jbe .L39
movslq %ebx, %rsi
salq $2, %rsi
movq %rsp, %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L48
.L39:
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L40:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L50
cmpl $1024, %ebp
ja .L51
.L36:
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L52
addq $48, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $145, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L49:
movl %ebp, %ecx
movq (%rsp), %rdx
movq %r14, %rsi
movq %r12, %rdi
call _Z38__device_stub__Z13exclusiveScanPjS_S_jPjS_S_j
jmp .L40
.L50:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $149, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L51:
movslq %ebx, %rsi
salq $2, %rsi
leaq 8(%rsp), %rdi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L53
movl %r13d, %edx
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z7preScanPjS_j
movl 24(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movq 28(%rsp), %rdi
movl 36(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L54
.L44:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L55
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
jmp .L36
.L53:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $157, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L54:
movl %ebp, %edx
movq %r12, %rsi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z15mergeScanBlocksPjS_iPjS_i
jmp .L44
.L55:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $163, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L52:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2060:
.size _Z7preScanPjS_j, .-_Z7preScanPjS_j
.globl _Z35__device_stub__Z11indexDefinePjS_jjPjS_jj
.type _Z35__device_stub__Z11indexDefinePjS_jjPjS_jj, @function
_Z35__device_stub__Z11indexDefinePjS_jjPjS_jj:
.LFB2094:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L60
.L56:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L61
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L60:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11indexDefinePjS_jj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L56
.L61:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2094:
.size _Z35__device_stub__Z11indexDefinePjS_jjPjS_jj, .-_Z35__device_stub__Z11indexDefinePjS_jjPjS_jj
.globl _Z11indexDefinePjS_jj
.type _Z11indexDefinePjS_jj, @function
_Z11indexDefinePjS_jj:
.LFB2095:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z11indexDefinePjS_jjPjS_jj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2095:
.size _Z11indexDefinePjS_jj, .-_Z11indexDefinePjS_jj
.globl _Z40__device_stub__Z15scatterElementsPjS_S_jPjS_S_j
.type _Z40__device_stub__Z15scatterElementsPjS_S_jPjS_S_j, @function
_Z40__device_stub__Z15scatterElementsPjS_S_jPjS_S_j:
.LFB2096:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L68
.L64:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L69
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L68:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z15scatterElementsPjS_S_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L64
.L69:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2096:
.size _Z40__device_stub__Z15scatterElementsPjS_S_jPjS_S_j, .-_Z40__device_stub__Z15scatterElementsPjS_S_jPjS_S_j
.globl _Z15scatterElementsPjS_S_j
.type _Z15scatterElementsPjS_S_j, @function
_Z15scatterElementsPjS_S_j:
.LFB2097:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z15scatterElementsPjS_S_jPjS_S_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2097:
.size _Z15scatterElementsPjS_S_j, .-_Z15scatterElementsPjS_S_j
.globl _Z10radix_sortPjS_S_S_S_i
.type _Z10radix_sortPjS_S_S_S_i, @function
_Z10radix_sortPjS_S_S_S_i:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r12
movq %rsi, %rbx
movq %rdx, %r14
movl %r9d, %r13d
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
pxor %xmm0, %xmm0
cvtsi2sdl %r9d, %xmm0
mulsd .LC3(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC7(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L73
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L73:
cvttsd2sil %xmm3, %eax
movl %eax, 20(%rsp)
movslq %r13d, %rax
leaq -4(%rcx,%rax,4), %r15
movl $0, %ebp
jmp .L81
.L86:
movl %ebp, %ecx
movl %r13d, %edx
movq %rbx, %rsi
movq %r12, %rdi
call _Z28__device_stub__Z5splitPjS_jiPjS_ji
jmp .L74
.L87:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $213, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L88:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $216, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L89:
movl (%r15), %ecx
movl %r13d, %edx
movq %rbx, %rsi
movq %r14, %rdi
call _Z35__device_stub__Z11indexDefinePjS_jjPjS_jj
jmp .L77
.L90:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $219, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L79:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L84
addl $1, %ebp
movq %rbx, %rax
movq %r12, %rbx
cmpl $32, %ebp
je .L85
movq %rax, %r12
.L81:
movl $512, 8(%rsp)
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L86
.L74:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L87
movl %r13d, %edx
movq %rbx, %rsi
movq %r14, %rdi
call _Z7preScanPjS_j
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L88
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L89
.L77:
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L90
movl 16(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 8(%rsp), %rdx
movq 20(%rsp), %rdi
movl 28(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L79
movl %r13d, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq %r12, %rdi
call _Z40__device_stub__Z15scatterElementsPjS_S_jPjS_S_j
jmp .L79
.L84:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $222, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L85:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _Z10radix_sortPjS_S_S_S_i, .-_Z10radix_sortPjS_S_S_S_i
.section .rodata.str1.1
.LC8:
.string "GPU Sort time: %f s\n"
.LC9:
.string "test failed\n"
.LC10:
.string "test passed\n"
.text
.globl main
.type main, @function
main:
.LFB2063:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $80, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbx
movl $4000000, %edi
call malloc@PLT
movq %rax, %rbp
movl $4000000, %edi
call malloc@PLT
movq %rax, %r12
leaq 16(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L110
leaq 8(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L111
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L112
call cudaDeviceSynchronize@PLT
movl $0, %eax
movl $999999, %ecx
.L95:
movl %ecx, %edx
subl %eax, %edx
movl %edx, (%rbx,%rax,4)
addq $1, %rax
cmpq $1000000, %rax
jne .L95
movl $1, %ecx
movl $4000000, %edx
movq %rbx, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L113
call cudaDeviceSynchronize@PLT
leaq 32(%rsp), %rdi
call _Z9startTimeP5Timer
movl $1000000, %r9d
movq %r12, %r8
movq %rbx, %rcx
movq 24(%rsp), %rdx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z10radix_sortPjS_S_S_S_i
call cudaDeviceSynchronize@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L114
leaq 32(%rsp), %rdi
call _Z8stopTimeP5Timer
subq $32, %rsp
.cfi_def_cfa_offset 144
movdqa 64(%rsp), %xmm1
movups %xmm1, (%rsp)
movdqa 80(%rsp), %xmm2
movups %xmm2, 16(%rsp)
call _Z11elapsedTime5Timer
addq $32, %rsp
.cfi_def_cfa_offset 112
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L115
movl $2, %ecx
movl $4000000, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
call cudaGetLastError@PLT
testl %eax, %eax
jne .L116
call cudaDeviceSynchronize@PLT
leaq _Z7comparePKvS0_(%rip), %rcx
movl $4, %edx
movl $1000000, %esi
movq %rbx, %rdi
call qsort@PLT
movl $0, %eax
.L101:
movl 0(%rbp,%rax), %esi
cmpl %esi, (%rbx,%rax)
jne .L100
addq $4, %rax
cmpq $4000000, %rax
jne .L101
leaq .LC10(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L103:
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L117
movl $0, %eax
addq $80, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L110:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $255, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L111:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $257, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L112:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $259, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L113:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $270, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L114:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $278, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L115:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $281, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L116:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %r8
movl $288, %ecx
leaq .LC1(%rip), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L100:
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L103
.L117:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2063:
.size main, .-main
.section .rodata.str1.1
.LC11:
.string "_Z15scatterElementsPjS_S_j"
.LC12:
.string "_Z11indexDefinePjS_jj"
.LC13:
.string "_Z15mergeScanBlocksPjS_i"
.LC14:
.string "_Z13exclusiveScanPjS_S_j"
.LC15:
.string "_Z5splitPjS_ji"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2099:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z15scatterElementsPjS_S_j(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z11indexDefinePjS_jj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _Z15mergeScanBlocksPjS_i(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC14(%rip), %rdx
movq %rdx, %rcx
leaq _Z13exclusiveScanPjS_S_j(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z5splitPjS_ji(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2099:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.align 8
.LC3:
.long 0
.long 1063256064
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC7:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <sys/time.h>
#define BLOCK_SIZE 512
#define cudaCheckError() { \
cudaError_t e=cudaGetLastError(); \
if(e!=cudaSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,cudaGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
typedef struct {
struct timeval startTime;
struct timeval endTime;
} Timer;
void startTime(Timer* timer) {
gettimeofday(&(timer->startTime), NULL);
}
void stopTime(Timer* timer) {
gettimeofday(&(timer->endTime), NULL);
}
float elapsedTime(Timer timer) {
return ((float) ((timer.endTime.tv_sec - timer.startTime.tv_sec) \
+ (timer.endTime.tv_usec - timer.startTime.tv_usec)/1.0e6));
}
//Split based on each bit
__global__ void split(unsigned int*in_d, unsigned int *out_d, unsigned int in_size,int bit_shift) {
unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
int bit = 0;
if (index < in_size) {
bit = in_d[index] & (1 << bit_shift);// get the value on each bit
bit = (bit > 0) ? 1 : 0;
out_d[index] = 1 - bit;
}
}
__global__ void exclusiveScan(unsigned int *out, unsigned int* in, unsigned int*sum, unsigned int inputSize) {
__shared__ unsigned int temp[2 * BLOCK_SIZE];
int start = 2 * blockIdx.x * blockDim.x;
int tx = threadIdx.x;
int index = 0;
if (start + tx < inputSize) {
temp[tx] = in[start + tx];
} else {
temp[tx] = 0;
}
if (start + tx + blockDim.x < inputSize) {
temp[tx + blockDim.x] = in[start + tx + blockDim.x];
} else {
temp[tx + blockDim.x] = 0;
}
__syncthreads();
// up-sweep phase
int stride = 1;
while(stride <= blockDim.x) {
index = (tx + 1) * 2 * stride - 1;
if (index < (2 * blockDim.x)) {
temp[index] += temp[index - stride];
}
stride *= 2;
__syncthreads();
}
// first store the reduction sum in sum array
// make it zero since it is exclusive scan
if (tx == 0) {
// sum array contains the prefix sum of each
// 2*blockDim blocks of element..
if (sum != NULL) {
sum[blockIdx.x] = temp[2*blockDim.x - 1];
}
temp[2*blockDim.x - 1] = 0;
}
//wait for thread zero to write
__syncthreads();
stride = blockDim.x;
index = 0;
unsigned int var = 0;
while(stride > 0) {
index = (2 * stride * (tx + 1)) - 1;
if (index < 2 * blockDim.x) {
var = temp[index];
temp[index] += temp[index - stride];
temp[index-stride] = var;
}
stride >>= 1;
__syncthreads();
}
// write the temp array to output
if (start + tx < inputSize) {
out[start + tx] = temp[tx];
}
if(start + tx + blockDim.x < inputSize) {
out[start + tx + blockDim.x] = temp[tx + blockDim.x];
}
}
// merge the scan blocks
__global__ void mergeScanBlocks(unsigned int *sum, unsigned int* output, int opSize) {
int index = 2 * blockDim.x * blockIdx.x + threadIdx.x;
if (index < opSize) {
output[index] += sum[blockIdx.x];
}
if (index + blockDim.x < opSize) {
output[index + blockDim.x] += sum[blockIdx.x];
}
}
void preScan(unsigned int *out, unsigned int *in, unsigned int in_size)
{
unsigned int numBlocks1 = in_size / BLOCK_SIZE;
if (in_size % BLOCK_SIZE) numBlocks1++;
int numBlocks2 = numBlocks1 / 2;
if(numBlocks1 % 2) numBlocks2++;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x = numBlocks2;
dimGrid.y = 1;
dimGrid.z = 1;
unsigned int*sumArr_d = NULL;
if (in_size > (2*BLOCK_SIZE)) {
// we need the sum auxilarry array only if numblocks2 > 1
cudaMalloc((void**)&sumArr_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
}
exclusiveScan<<<dimGrid, dimThreadBlock>>>(out, in, sumArr_d, in_size);
cudaDeviceSynchronize();
cudaCheckError();
if (in_size <= (2*BLOCK_SIZE)) {
// out has proper exclusive scan. return
return;
} else {
// now we need to perform exclusive scan on the auxilliary sum array
unsigned int *sumArr_scan_d;
cudaMalloc((void**)&sumArr_scan_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
preScan(sumArr_scan_d, sumArr_d, numBlocks2);
// sumAdd_scan_d now contains the exclusive scan op of individual blocks
// now just do a one-one addition of blocks
mergeScanBlocks<<<dimGrid,dimThreadBlock>>>(sumArr_scan_d, out, in_size);
cudaDeviceSynchronize();
cudaCheckError();
cudaFree(sumArr_d);
cudaFree(sumArr_scan_d);
}
}
//Define the destination index
__global__ void indexDefine(unsigned int *in_d, unsigned int *rev_bit_d,
unsigned int in_size, unsigned int last_input) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
int total_falses = in_d[in_size - 1] + last_input;
__syncthreads();
if (index < in_size) {
if (rev_bit_d[index] == 0) {
int val = in_d[index];
in_d[index] = index + 1 - val + total_falses;
}
}
}
//Scatter input using in_d address
__global__ void scatterElements(unsigned int *in_d, unsigned int *index_d, unsigned int *out_d, unsigned int in_size) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < in_size) {
unsigned int val = index_d[index];
if (val < in_size) {
out_d[val] = in_d[index];
}
}
}
void radix_sort(unsigned int *in_d, unsigned int *out_d, unsigned int *out_scan_d, unsigned int *in_h,unsigned int *out_scan_h, int num_elements) {
unsigned int *temp;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x =(int)(ceil(num_elements/(1.0 * dimThreadBlock.x)));
dimGrid.y = 1;
dimGrid.z = 1;
for (int i =0;i<32;i++) {
split<<<dimGrid, dimThreadBlock>>>(in_d,out_d,num_elements,i);
cudaDeviceSynchronize();
cudaCheckError();
preScan(out_scan_d, out_d, num_elements);
cudaDeviceSynchronize();
cudaCheckError();
indexDefine<<<dimGrid, dimThreadBlock>>>(out_scan_d, out_d, num_elements, in_h[num_elements - 1]);
cudaDeviceSynchronize();
cudaCheckError();
scatterElements<<<dimGrid, dimThreadBlock>>>(in_d, out_scan_d, out_d, num_elements);
cudaDeviceSynchronize();
cudaCheckError();
// swap pointers
temp = in_d;
in_d = out_d;
out_d = temp;
}
}
int compare(const void *a, const void *b) {
int a1 = *((unsigned int*)a);
int b1 = *((unsigned int*)b);
if (a1 == b1) return 0;
else if (a1 < b1) return -1;
else return 1;
}
int main(){
Timer timer;
unsigned int *in_h;
unsigned int *out_h;
unsigned int *out_d;
unsigned int *in_d;
unsigned int *out_scan_d;
unsigned int num_elements = 1000000;
in_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
out_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
unsigned int *out_scan_h = (unsigned int *)malloc(num_elements * sizeof(unsigned int));
cudaMalloc((void**)&in_d, num_elements * sizeof(unsigned int));
cudaCheckError();
cudaMalloc((void**)&out_d, num_elements * sizeof(unsigned int));
cudaCheckError();
cudaMalloc((void**)&out_scan_d, num_elements * sizeof(unsigned int ));
cudaCheckError();
cudaDeviceSynchronize();
//init array
for(int i = 0;i < num_elements;i++) {
in_h[i] = num_elements - 1 - i;
}
// Copy host variables to device ------------------------------------------
cudaMemcpy(in_d, in_h, num_elements * sizeof(unsigned int),
cudaMemcpyHostToDevice);
cudaCheckError();
cudaDeviceSynchronize();
// Launch kernel ----------------------------------------------------------
startTime(&timer);
radix_sort(in_d, out_d, out_scan_d, in_h, out_scan_h, num_elements);
cudaDeviceSynchronize();
cudaCheckError();
stopTime(&timer); printf("GPU Sort time: %f s\n", elapsedTime(timer));
cudaCheckError();
// Copy device variables from host ----------------------------------------
cudaMemcpy(out_h, out_d, num_elements * sizeof(unsigned int),
cudaMemcpyDeviceToHost);
cudaCheckError();
cudaDeviceSynchronize();
// Verify correctness -----------------------------------------------------
qsort(in_h, num_elements, sizeof(unsigned int),compare);
int flag = 0;
for (int i = 0;i < num_elements;i++) {
if (in_h[i] != out_h[i]) {
flag = 1;
break;
}
}
if (flag == 1) {
printf("test failed\n");
} else
printf("test passed\n");
// Free memory
cudaFree(in_d);
cudaFree(out_scan_d);
cudaFree(out_d);
free(in_h);
free(out_h);
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <sys/time.h>
#define BLOCK_SIZE 512
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,hipGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
typedef struct {
struct timeval startTime;
struct timeval endTime;
} Timer;
void startTime(Timer* timer) {
gettimeofday(&(timer->startTime), NULL);
}
void stopTime(Timer* timer) {
gettimeofday(&(timer->endTime), NULL);
}
float elapsedTime(Timer timer) {
return ((float) ((timer.endTime.tv_sec - timer.startTime.tv_sec) \
+ (timer.endTime.tv_usec - timer.startTime.tv_usec)/1.0e6));
}
//Split based on each bit
__global__ void split(unsigned int*in_d, unsigned int *out_d, unsigned int in_size,int bit_shift) {
unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
int bit = 0;
if (index < in_size) {
bit = in_d[index] & (1 << bit_shift);// get the value on each bit
bit = (bit > 0) ? 1 : 0;
out_d[index] = 1 - bit;
}
}
__global__ void exclusiveScan(unsigned int *out, unsigned int* in, unsigned int*sum, unsigned int inputSize) {
__shared__ unsigned int temp[2 * BLOCK_SIZE];
int start = 2 * blockIdx.x * blockDim.x;
int tx = threadIdx.x;
int index = 0;
if (start + tx < inputSize) {
temp[tx] = in[start + tx];
} else {
temp[tx] = 0;
}
if (start + tx + blockDim.x < inputSize) {
temp[tx + blockDim.x] = in[start + tx + blockDim.x];
} else {
temp[tx + blockDim.x] = 0;
}
__syncthreads();
// up-sweep phase
int stride = 1;
while(stride <= blockDim.x) {
index = (tx + 1) * 2 * stride - 1;
if (index < (2 * blockDim.x)) {
temp[index] += temp[index - stride];
}
stride *= 2;
__syncthreads();
}
// first store the reduction sum in sum array
// make it zero since it is exclusive scan
if (tx == 0) {
// sum array contains the prefix sum of each
// 2*blockDim blocks of element..
if (sum != NULL) {
sum[blockIdx.x] = temp[2*blockDim.x - 1];
}
temp[2*blockDim.x - 1] = 0;
}
//wait for thread zero to write
__syncthreads();
stride = blockDim.x;
index = 0;
unsigned int var = 0;
while(stride > 0) {
index = (2 * stride * (tx + 1)) - 1;
if (index < 2 * blockDim.x) {
var = temp[index];
temp[index] += temp[index - stride];
temp[index-stride] = var;
}
stride >>= 1;
__syncthreads();
}
// write the temp array to output
if (start + tx < inputSize) {
out[start + tx] = temp[tx];
}
if(start + tx + blockDim.x < inputSize) {
out[start + tx + blockDim.x] = temp[tx + blockDim.x];
}
}
// merge the scan blocks
__global__ void mergeScanBlocks(unsigned int *sum, unsigned int* output, int opSize) {
int index = 2 * blockDim.x * blockIdx.x + threadIdx.x;
if (index < opSize) {
output[index] += sum[blockIdx.x];
}
if (index + blockDim.x < opSize) {
output[index + blockDim.x] += sum[blockIdx.x];
}
}
void preScan(unsigned int *out, unsigned int *in, unsigned int in_size)
{
unsigned int numBlocks1 = in_size / BLOCK_SIZE;
if (in_size % BLOCK_SIZE) numBlocks1++;
int numBlocks2 = numBlocks1 / 2;
if(numBlocks1 % 2) numBlocks2++;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x = numBlocks2;
dimGrid.y = 1;
dimGrid.z = 1;
unsigned int*sumArr_d = NULL;
if (in_size > (2*BLOCK_SIZE)) {
// we need the sum auxilarry array only if numblocks2 > 1
hipMalloc((void**)&sumArr_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
}
exclusiveScan<<<dimGrid, dimThreadBlock>>>(out, in, sumArr_d, in_size);
hipDeviceSynchronize();
cudaCheckError();
if (in_size <= (2*BLOCK_SIZE)) {
// out has proper exclusive scan. return
return;
} else {
// now we need to perform exclusive scan on the auxilliary sum array
unsigned int *sumArr_scan_d;
hipMalloc((void**)&sumArr_scan_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
preScan(sumArr_scan_d, sumArr_d, numBlocks2);
// sumAdd_scan_d now contains the exclusive scan op of individual blocks
// now just do a one-one addition of blocks
mergeScanBlocks<<<dimGrid,dimThreadBlock>>>(sumArr_scan_d, out, in_size);
hipDeviceSynchronize();
cudaCheckError();
hipFree(sumArr_d);
hipFree(sumArr_scan_d);
}
}
//Define the destination index
__global__ void indexDefine(unsigned int *in_d, unsigned int *rev_bit_d,
unsigned int in_size, unsigned int last_input) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
int total_falses = in_d[in_size - 1] + last_input;
__syncthreads();
if (index < in_size) {
if (rev_bit_d[index] == 0) {
int val = in_d[index];
in_d[index] = index + 1 - val + total_falses;
}
}
}
//Scatter input using in_d address
__global__ void scatterElements(unsigned int *in_d, unsigned int *index_d, unsigned int *out_d, unsigned int in_size) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < in_size) {
unsigned int val = index_d[index];
if (val < in_size) {
out_d[val] = in_d[index];
}
}
}
void radix_sort(unsigned int *in_d, unsigned int *out_d, unsigned int *out_scan_d, unsigned int *in_h,unsigned int *out_scan_h, int num_elements) {
unsigned int *temp;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x =(int)(ceil(num_elements/(1.0 * dimThreadBlock.x)));
dimGrid.y = 1;
dimGrid.z = 1;
for (int i =0;i<32;i++) {
split<<<dimGrid, dimThreadBlock>>>(in_d,out_d,num_elements,i);
hipDeviceSynchronize();
cudaCheckError();
preScan(out_scan_d, out_d, num_elements);
hipDeviceSynchronize();
cudaCheckError();
indexDefine<<<dimGrid, dimThreadBlock>>>(out_scan_d, out_d, num_elements, in_h[num_elements - 1]);
hipDeviceSynchronize();
cudaCheckError();
scatterElements<<<dimGrid, dimThreadBlock>>>(in_d, out_scan_d, out_d, num_elements);
hipDeviceSynchronize();
cudaCheckError();
// swap pointers
temp = in_d;
in_d = out_d;
out_d = temp;
}
}
int compare(const void *a, const void *b) {
int a1 = *((unsigned int*)a);
int b1 = *((unsigned int*)b);
if (a1 == b1) return 0;
else if (a1 < b1) return -1;
else return 1;
}
int main(){
Timer timer;
unsigned int *in_h;
unsigned int *out_h;
unsigned int *out_d;
unsigned int *in_d;
unsigned int *out_scan_d;
unsigned int num_elements = 1000000;
in_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
out_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
unsigned int *out_scan_h = (unsigned int *)malloc(num_elements * sizeof(unsigned int));
hipMalloc((void**)&in_d, num_elements * sizeof(unsigned int));
cudaCheckError();
hipMalloc((void**)&out_d, num_elements * sizeof(unsigned int));
cudaCheckError();
hipMalloc((void**)&out_scan_d, num_elements * sizeof(unsigned int ));
cudaCheckError();
hipDeviceSynchronize();
//init array
for(int i = 0;i < num_elements;i++) {
in_h[i] = num_elements - 1 - i;
}
// Copy host variables to device ------------------------------------------
hipMemcpy(in_d, in_h, num_elements * sizeof(unsigned int),
hipMemcpyHostToDevice);
cudaCheckError();
hipDeviceSynchronize();
// Launch kernel ----------------------------------------------------------
startTime(&timer);
radix_sort(in_d, out_d, out_scan_d, in_h, out_scan_h, num_elements);
hipDeviceSynchronize();
cudaCheckError();
stopTime(&timer); printf("GPU Sort time: %f s\n", elapsedTime(timer));
cudaCheckError();
// Copy device variables from host ----------------------------------------
hipMemcpy(out_h, out_d, num_elements * sizeof(unsigned int),
hipMemcpyDeviceToHost);
cudaCheckError();
hipDeviceSynchronize();
// Verify correctness -----------------------------------------------------
qsort(in_h, num_elements, sizeof(unsigned int),compare);
int flag = 0;
for (int i = 0;i < num_elements;i++) {
if (in_h[i] != out_h[i]) {
flag = 1;
break;
}
}
if (flag == 1) {
printf("test failed\n");
} else
printf("test passed\n");
// Free memory
hipFree(in_d);
hipFree(out_scan_d);
hipFree(out_d);
free(in_h);
free(out_h);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <sys/time.h>
#define BLOCK_SIZE 512
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,hipGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
typedef struct {
struct timeval startTime;
struct timeval endTime;
} Timer;
void startTime(Timer* timer) {
gettimeofday(&(timer->startTime), NULL);
}
void stopTime(Timer* timer) {
gettimeofday(&(timer->endTime), NULL);
}
float elapsedTime(Timer timer) {
return ((float) ((timer.endTime.tv_sec - timer.startTime.tv_sec) \
+ (timer.endTime.tv_usec - timer.startTime.tv_usec)/1.0e6));
}
//Split based on each bit
__global__ void split(unsigned int*in_d, unsigned int *out_d, unsigned int in_size,int bit_shift) {
unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
int bit = 0;
if (index < in_size) {
bit = in_d[index] & (1 << bit_shift);// get the value on each bit
bit = (bit > 0) ? 1 : 0;
out_d[index] = 1 - bit;
}
}
__global__ void exclusiveScan(unsigned int *out, unsigned int* in, unsigned int*sum, unsigned int inputSize) {
__shared__ unsigned int temp[2 * BLOCK_SIZE];
int start = 2 * blockIdx.x * blockDim.x;
int tx = threadIdx.x;
int index = 0;
if (start + tx < inputSize) {
temp[tx] = in[start + tx];
} else {
temp[tx] = 0;
}
if (start + tx + blockDim.x < inputSize) {
temp[tx + blockDim.x] = in[start + tx + blockDim.x];
} else {
temp[tx + blockDim.x] = 0;
}
__syncthreads();
// up-sweep phase
int stride = 1;
while(stride <= blockDim.x) {
index = (tx + 1) * 2 * stride - 1;
if (index < (2 * blockDim.x)) {
temp[index] += temp[index - stride];
}
stride *= 2;
__syncthreads();
}
// first store the reduction sum in sum array
// make it zero since it is exclusive scan
if (tx == 0) {
// sum array contains the prefix sum of each
// 2*blockDim blocks of element..
if (sum != NULL) {
sum[blockIdx.x] = temp[2*blockDim.x - 1];
}
temp[2*blockDim.x - 1] = 0;
}
//wait for thread zero to write
__syncthreads();
stride = blockDim.x;
index = 0;
unsigned int var = 0;
while(stride > 0) {
index = (2 * stride * (tx + 1)) - 1;
if (index < 2 * blockDim.x) {
var = temp[index];
temp[index] += temp[index - stride];
temp[index-stride] = var;
}
stride >>= 1;
__syncthreads();
}
// write the temp array to output
if (start + tx < inputSize) {
out[start + tx] = temp[tx];
}
if(start + tx + blockDim.x < inputSize) {
out[start + tx + blockDim.x] = temp[tx + blockDim.x];
}
}
// merge the scan blocks
__global__ void mergeScanBlocks(unsigned int *sum, unsigned int* output, int opSize) {
int index = 2 * blockDim.x * blockIdx.x + threadIdx.x;
if (index < opSize) {
output[index] += sum[blockIdx.x];
}
if (index + blockDim.x < opSize) {
output[index + blockDim.x] += sum[blockIdx.x];
}
}
void preScan(unsigned int *out, unsigned int *in, unsigned int in_size)
{
unsigned int numBlocks1 = in_size / BLOCK_SIZE;
if (in_size % BLOCK_SIZE) numBlocks1++;
int numBlocks2 = numBlocks1 / 2;
if(numBlocks1 % 2) numBlocks2++;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x = numBlocks2;
dimGrid.y = 1;
dimGrid.z = 1;
unsigned int*sumArr_d = NULL;
if (in_size > (2*BLOCK_SIZE)) {
// we need the sum auxilarry array only if numblocks2 > 1
hipMalloc((void**)&sumArr_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
}
exclusiveScan<<<dimGrid, dimThreadBlock>>>(out, in, sumArr_d, in_size);
hipDeviceSynchronize();
cudaCheckError();
if (in_size <= (2*BLOCK_SIZE)) {
// out has proper exclusive scan. return
return;
} else {
// now we need to perform exclusive scan on the auxilliary sum array
unsigned int *sumArr_scan_d;
hipMalloc((void**)&sumArr_scan_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
preScan(sumArr_scan_d, sumArr_d, numBlocks2);
// sumAdd_scan_d now contains the exclusive scan op of individual blocks
// now just do a one-one addition of blocks
mergeScanBlocks<<<dimGrid,dimThreadBlock>>>(sumArr_scan_d, out, in_size);
hipDeviceSynchronize();
cudaCheckError();
hipFree(sumArr_d);
hipFree(sumArr_scan_d);
}
}
//Define the destination index
__global__ void indexDefine(unsigned int *in_d, unsigned int *rev_bit_d,
unsigned int in_size, unsigned int last_input) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
int total_falses = in_d[in_size - 1] + last_input;
__syncthreads();
if (index < in_size) {
if (rev_bit_d[index] == 0) {
int val = in_d[index];
in_d[index] = index + 1 - val + total_falses;
}
}
}
//Scatter input using in_d address
__global__ void scatterElements(unsigned int *in_d, unsigned int *index_d, unsigned int *out_d, unsigned int in_size) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < in_size) {
unsigned int val = index_d[index];
if (val < in_size) {
out_d[val] = in_d[index];
}
}
}
void radix_sort(unsigned int *in_d, unsigned int *out_d, unsigned int *out_scan_d, unsigned int *in_h,unsigned int *out_scan_h, int num_elements) {
unsigned int *temp;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x =(int)(ceil(num_elements/(1.0 * dimThreadBlock.x)));
dimGrid.y = 1;
dimGrid.z = 1;
for (int i =0;i<32;i++) {
split<<<dimGrid, dimThreadBlock>>>(in_d,out_d,num_elements,i);
hipDeviceSynchronize();
cudaCheckError();
preScan(out_scan_d, out_d, num_elements);
hipDeviceSynchronize();
cudaCheckError();
indexDefine<<<dimGrid, dimThreadBlock>>>(out_scan_d, out_d, num_elements, in_h[num_elements - 1]);
hipDeviceSynchronize();
cudaCheckError();
scatterElements<<<dimGrid, dimThreadBlock>>>(in_d, out_scan_d, out_d, num_elements);
hipDeviceSynchronize();
cudaCheckError();
// swap pointers
temp = in_d;
in_d = out_d;
out_d = temp;
}
}
int compare(const void *a, const void *b) {
int a1 = *((unsigned int*)a);
int b1 = *((unsigned int*)b);
if (a1 == b1) return 0;
else if (a1 < b1) return -1;
else return 1;
}
int main(){
Timer timer;
unsigned int *in_h;
unsigned int *out_h;
unsigned int *out_d;
unsigned int *in_d;
unsigned int *out_scan_d;
unsigned int num_elements = 1000000;
in_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
out_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
unsigned int *out_scan_h = (unsigned int *)malloc(num_elements * sizeof(unsigned int));
hipMalloc((void**)&in_d, num_elements * sizeof(unsigned int));
cudaCheckError();
hipMalloc((void**)&out_d, num_elements * sizeof(unsigned int));
cudaCheckError();
hipMalloc((void**)&out_scan_d, num_elements * sizeof(unsigned int ));
cudaCheckError();
hipDeviceSynchronize();
//init array
for(int i = 0;i < num_elements;i++) {
in_h[i] = num_elements - 1 - i;
}
// Copy host variables to device ------------------------------------------
hipMemcpy(in_d, in_h, num_elements * sizeof(unsigned int),
hipMemcpyHostToDevice);
cudaCheckError();
hipDeviceSynchronize();
// Launch kernel ----------------------------------------------------------
startTime(&timer);
radix_sort(in_d, out_d, out_scan_d, in_h, out_scan_h, num_elements);
hipDeviceSynchronize();
cudaCheckError();
stopTime(&timer); printf("GPU Sort time: %f s\n", elapsedTime(timer));
cudaCheckError();
// Copy device variables from host ----------------------------------------
hipMemcpy(out_h, out_d, num_elements * sizeof(unsigned int),
hipMemcpyDeviceToHost);
cudaCheckError();
hipDeviceSynchronize();
// Verify correctness -----------------------------------------------------
qsort(in_h, num_elements, sizeof(unsigned int),compare);
int flag = 0;
for (int i = 0;i < num_elements;i++) {
if (in_h[i] != out_h[i]) {
flag = 1;
break;
}
}
if (flag == 1) {
printf("test failed\n");
} else
printf("test passed\n");
// Free memory
hipFree(in_d);
hipFree(out_scan_d);
hipFree(out_d);
free(in_h);
free(out_h);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z5splitPjS_ji
.globl _Z5splitPjS_ji
.p2align 8
.type _Z5splitPjS_ji,@function
_Z5splitPjS_ji:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_u32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mov_b32_e32 v2, 0
s_load_b32 s0, s[0:1], 0x14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
s_lshl_b32 s0, 1, s0
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_and_b32_e32 v2, s0, v2
v_cmp_gt_i32_e32 vcc_lo, 1, v2
v_cndmask_b32_e64 v2, 0, 1, vcc_lo
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5splitPjS_ji
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z5splitPjS_ji, .Lfunc_end0-_Z5splitPjS_ji
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13exclusiveScanPjS_S_j
.globl _Z13exclusiveScanPjS_S_j
.p2align 8
.type _Z13exclusiveScanPjS_S_j,@function
_Z13exclusiveScanPjS_S_j:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x2c
s_load_b32 s3, s[0:1], 0x18
s_load_b64 s[6:7], s[0:1], 0x8
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v2, 0
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s8, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s2, s15, s8
v_lshl_add_u32 v1, s2, 1, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_u32_e64 s2, s3, v1
s_and_saveexec_b32 s9, s2
s_cbranch_execz .LBB1_2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_add_co_u32 v2, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
global_load_b32 v2, v[2:3], off
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v3, s8, v1
v_lshlrev_b32_e32 v5, 2, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmp_gt_u32_e64 s3, s3, v3
s_waitcnt vmcnt(0)
ds_store_b32 v5, v2
s_and_saveexec_b32 s9, s3
s_cbranch_execz .LBB1_4
v_mov_b32_e32 v4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[3:4]
v_add_co_u32 v4, vcc_lo, s6, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
global_load_b32 v4, v[4:5], off
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s9
v_cmp_eq_u16_e64 s5, s5, 0
v_add_lshl_u32 v2, v0, s8, 2
s_delay_alu instid0(VALU_DEP_2)
s_and_b32 vcc_lo, exec_lo, s5
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_vccnz .LBB1_9
v_lshl_add_u32 v2, v0, 1, 2
s_mov_b32 s5, 1
s_lshl_b32 s6, s8, 1
s_branch .LBB1_7
.p2align 6
.LBB1_6:
s_or_b32 exec_lo, exec_lo, s7
s_lshl_b32 s5, s5, 1
s_waitcnt lgkmcnt(0)
s_cmp_le_u32 s5, s8
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_9
.LBB1_7:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[4:5], null, s5, v2, -1
s_mov_b32 s7, exec_lo
v_cmpx_gt_u32_e64 s6, v4
s_cbranch_execz .LBB1_6
v_subrev_nc_u32_e32 v5, s5, v4
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v5, v5
ds_load_b32 v6, v4
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v5, v6, v5
ds_store_b32 v4, v5
s_branch .LBB1_6
.LBB1_9:
s_mov_b32 s9, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_13
s_load_b64 s[6:7], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_cmp_eq_u64 s[6:7], 0
s_cbranch_scc1 .LBB1_12
s_lshl_b32 s5, s8, 3
v_mov_b32_e32 v4, 0
s_add_i32 s5, s5, -4
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mov_b32_e32 v2, s5
s_mov_b32 s5, 0
s_lshl_b64 s[4:5], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s4, s6, s4
ds_load_b32 v2, v2
s_addc_u32 s5, s7, s5
s_waitcnt lgkmcnt(0)
global_store_b32 v4, v2, s[4:5]
.LBB1_12:
s_lshl_b32 s4, s8, 3
v_mov_b32_e32 v2, 0
s_add_i32 s4, s4, -4
s_delay_alu instid0(SALU_CYCLE_1)
v_mov_b32_e32 v4, s4
ds_store_b32 v4, v2
.LBB1_13:
s_or_b32 exec_lo, exec_lo, s9
s_cmp_eq_u32 s8, 0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB1_18
v_lshl_add_u32 v2, v0, 1, 2
s_lshl_b32 s4, s8, 1
s_mov_b32 s5, s8
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_16
.p2align 6
.LBB1_15:
s_or_b32 exec_lo, exec_lo, s6
s_lshr_b32 s6, s5, 1
s_cmp_gt_u32 s5, 1
s_mov_b32 s5, s6
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc0 .LBB1_18
.LBB1_16:
v_mad_u32_u24 v4, v2, s5, -1
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s4, v4
s_cbranch_execz .LBB1_15
v_subrev_nc_u32_e32 v5, s5, v4
v_lshlrev_b32_e32 v4, 2, v4
s_delay_alu instid0(VALU_DEP_2)
v_lshlrev_b32_e32 v5, 2, v5
ds_load_b32 v6, v4
ds_load_b32 v7, v5
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v7, v7, v6
ds_store_b32 v4, v7
ds_store_b32 v5, v6
s_branch .LBB1_15
.LBB1_18:
s_set_inst_prefetch_distance 0x2
s_load_b64 s[0:1], s[0:1], 0x0
s_and_saveexec_b32 s4, s2
s_cbranch_execz .LBB1_20
v_lshlrev_b32_e32 v2, 2, v0
ds_load_b32 v4, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_store_b32 v[1:2], v4, off
.LBB1_20:
s_or_b32 exec_lo, exec_lo, s4
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB1_22
v_add_lshl_u32 v0, v0, s8, 2
v_mov_b32_e32 v4, 0
ds_load_b32 v2, v0
v_lshlrev_b64 v[0:1], 2, v[3:4]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_22:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13exclusiveScanPjS_S_j
.amdhsa_group_segment_fixed_size 4096
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13exclusiveScanPjS_S_j, .Lfunc_end1-_Z13exclusiveScanPjS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15mergeScanBlocksPjS_i
.globl _Z15mergeScanBlocksPjS_i
.p2align 8
.type _Z15mergeScanBlocksPjS_i,@function
_Z15mergeScanBlocksPjS_i:
s_clause 0x2
s_load_b32 s5, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
s_mov_b32 s4, s15
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_and_b32 s7, s5, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s15, s7
v_lshl_add_u32 v0, s5, 1, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s6, v0
s_cbranch_execz .LBB2_2
v_ashrrev_i32_e32 v1, 31, v0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[10:11], s[4:5], 2
s_add_u32 s10, s0, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
s_addc_u32 s11, s1, s11
s_load_b32 s5, s[10:11], 0x0
v_add_co_u32 v1, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[1:2], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_add_nc_u32_e32 v3, s5, v3
global_store_b32 v[1:2], v3, off
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s8
v_add_nc_u32_e32 v0, s7, v0
s_mov_b32 s5, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s6, v0
s_cbranch_execz .LBB2_4
v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
s_mov_b32 s5, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[4:5], s[4:5], 2
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_add_u32 s0, s0, s4
s_addc_u32 s1, s1, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v2, s[0:1]
global_load_b32 v3, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, v3, v2
global_store_b32 v[0:1], v2, off
.LBB2_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15mergeScanBlocksPjS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z15mergeScanBlocksPjS_i, .Lfunc_end2-_Z15mergeScanBlocksPjS_i
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z11indexDefinePjS_jj
.globl _Z11indexDefinePjS_jj
.p2align 8
.type _Z11indexDefinePjS_jj,@function
_Z11indexDefinePjS_jj:
s_clause 0x2
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x10
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s4, s4, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_add_i32 s4, s6, -1
s_lshl_b64 s[4:5], s[4:5], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_add_u32 s4, s2, s4
s_addc_u32 s5, s3, s5
v_cmp_gt_u32_e32 vcc_lo, s6, v1
s_and_saveexec_b32 s6, vcc_lo
s_cbranch_execz .LBB3_3
s_load_b64 s[6:7], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s6, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB3_3
v_lshlrev_b64 v[2:3], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s0, s[0:1], 0x14
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s0, s2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add3_u32 v1, s0, 1, v1
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v0, v1, v0
global_store_b32 v[2:3], v0, off
.LBB3_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11indexDefinePjS_jj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z11indexDefinePjS_jj, .Lfunc_end3-_Z11indexDefinePjS_jj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15scatterElementsPjS_S_j
.globl _Z15scatterElementsPjS_S_j
.p2align 8
.type _Z15scatterElementsPjS_S_j,@function
_Z15scatterElementsPjS_S_j:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB4_3
s_load_b64 s[4:5], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s4, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s5, v2, vcc_lo
global_load_b32 v0, v[3:4], off
s_waitcnt vmcnt(0)
v_cmp_gt_u32_e32 vcc_lo, s2, v0
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB4_3
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v2, v[1:2], off
v_mov_b32_e32 v1, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB4_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15scatterElementsPjS_S_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end4:
.size _Z15scatterElementsPjS_S_j, .Lfunc_end4-_Z15scatterElementsPjS_S_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5splitPjS_ji
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z5splitPjS_ji.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 4096
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13exclusiveScanPjS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13exclusiveScanPjS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15mergeScanBlocksPjS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15mergeScanBlocksPjS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11indexDefinePjS_jj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11indexDefinePjS_jj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15scatterElementsPjS_S_j
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z15scatterElementsPjS_S_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <sys/time.h>
#define BLOCK_SIZE 512
#define cudaCheckError() { \
hipError_t e=hipGetLastError(); \
if(e!=hipSuccess) { \
printf("Cuda failure %s:%d: '%s'\n",__FILE__,__LINE__,hipGetErrorString(e)); \
exit(EXIT_FAILURE); \
} \
}
typedef struct {
struct timeval startTime;
struct timeval endTime;
} Timer;
void startTime(Timer* timer) {
gettimeofday(&(timer->startTime), NULL);
}
void stopTime(Timer* timer) {
gettimeofday(&(timer->endTime), NULL);
}
float elapsedTime(Timer timer) {
return ((float) ((timer.endTime.tv_sec - timer.startTime.tv_sec) \
+ (timer.endTime.tv_usec - timer.startTime.tv_usec)/1.0e6));
}
//Split based on each bit
__global__ void split(unsigned int*in_d, unsigned int *out_d, unsigned int in_size,int bit_shift) {
unsigned int index = threadIdx.x + blockDim.x * blockIdx.x;
int bit = 0;
if (index < in_size) {
bit = in_d[index] & (1 << bit_shift);// get the value on each bit
bit = (bit > 0) ? 1 : 0;
out_d[index] = 1 - bit;
}
}
__global__ void exclusiveScan(unsigned int *out, unsigned int* in, unsigned int*sum, unsigned int inputSize) {
__shared__ unsigned int temp[2 * BLOCK_SIZE];
int start = 2 * blockIdx.x * blockDim.x;
int tx = threadIdx.x;
int index = 0;
if (start + tx < inputSize) {
temp[tx] = in[start + tx];
} else {
temp[tx] = 0;
}
if (start + tx + blockDim.x < inputSize) {
temp[tx + blockDim.x] = in[start + tx + blockDim.x];
} else {
temp[tx + blockDim.x] = 0;
}
__syncthreads();
// up-sweep phase
int stride = 1;
while(stride <= blockDim.x) {
index = (tx + 1) * 2 * stride - 1;
if (index < (2 * blockDim.x)) {
temp[index] += temp[index - stride];
}
stride *= 2;
__syncthreads();
}
// first store the reduction sum in sum array
// make it zero since it is exclusive scan
if (tx == 0) {
// sum array contains the prefix sum of each
// 2*blockDim blocks of element..
if (sum != NULL) {
sum[blockIdx.x] = temp[2*blockDim.x - 1];
}
temp[2*blockDim.x - 1] = 0;
}
//wait for thread zero to write
__syncthreads();
stride = blockDim.x;
index = 0;
unsigned int var = 0;
while(stride > 0) {
index = (2 * stride * (tx + 1)) - 1;
if (index < 2 * blockDim.x) {
var = temp[index];
temp[index] += temp[index - stride];
temp[index-stride] = var;
}
stride >>= 1;
__syncthreads();
}
// write the temp array to output
if (start + tx < inputSize) {
out[start + tx] = temp[tx];
}
if(start + tx + blockDim.x < inputSize) {
out[start + tx + blockDim.x] = temp[tx + blockDim.x];
}
}
// merge the scan blocks
__global__ void mergeScanBlocks(unsigned int *sum, unsigned int* output, int opSize) {
int index = 2 * blockDim.x * blockIdx.x + threadIdx.x;
if (index < opSize) {
output[index] += sum[blockIdx.x];
}
if (index + blockDim.x < opSize) {
output[index + blockDim.x] += sum[blockIdx.x];
}
}
void preScan(unsigned int *out, unsigned int *in, unsigned int in_size)
{
unsigned int numBlocks1 = in_size / BLOCK_SIZE;
if (in_size % BLOCK_SIZE) numBlocks1++;
int numBlocks2 = numBlocks1 / 2;
if(numBlocks1 % 2) numBlocks2++;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x = numBlocks2;
dimGrid.y = 1;
dimGrid.z = 1;
unsigned int*sumArr_d = NULL;
if (in_size > (2*BLOCK_SIZE)) {
// we need the sum auxilarry array only if numblocks2 > 1
hipMalloc((void**)&sumArr_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
}
exclusiveScan<<<dimGrid, dimThreadBlock>>>(out, in, sumArr_d, in_size);
hipDeviceSynchronize();
cudaCheckError();
if (in_size <= (2*BLOCK_SIZE)) {
// out has proper exclusive scan. return
return;
} else {
// now we need to perform exclusive scan on the auxilliary sum array
unsigned int *sumArr_scan_d;
hipMalloc((void**)&sumArr_scan_d, numBlocks2 * sizeof(unsigned int));
cudaCheckError();
preScan(sumArr_scan_d, sumArr_d, numBlocks2);
// sumAdd_scan_d now contains the exclusive scan op of individual blocks
// now just do a one-one addition of blocks
mergeScanBlocks<<<dimGrid,dimThreadBlock>>>(sumArr_scan_d, out, in_size);
hipDeviceSynchronize();
cudaCheckError();
hipFree(sumArr_d);
hipFree(sumArr_scan_d);
}
}
//Define the destination index
__global__ void indexDefine(unsigned int *in_d, unsigned int *rev_bit_d,
unsigned int in_size, unsigned int last_input) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
int total_falses = in_d[in_size - 1] + last_input;
__syncthreads();
if (index < in_size) {
if (rev_bit_d[index] == 0) {
int val = in_d[index];
in_d[index] = index + 1 - val + total_falses;
}
}
}
//Scatter input using in_d address
__global__ void scatterElements(unsigned int *in_d, unsigned int *index_d, unsigned int *out_d, unsigned int in_size) {
int index = threadIdx.x + blockDim.x * blockIdx.x;
if (index < in_size) {
unsigned int val = index_d[index];
if (val < in_size) {
out_d[val] = in_d[index];
}
}
}
void radix_sort(unsigned int *in_d, unsigned int *out_d, unsigned int *out_scan_d, unsigned int *in_h,unsigned int *out_scan_h, int num_elements) {
unsigned int *temp;
dim3 dimThreadBlock;
dimThreadBlock.x = BLOCK_SIZE;
dimThreadBlock.y = 1;
dimThreadBlock.z = 1;
dim3 dimGrid;
dimGrid.x =(int)(ceil(num_elements/(1.0 * dimThreadBlock.x)));
dimGrid.y = 1;
dimGrid.z = 1;
for (int i =0;i<32;i++) {
split<<<dimGrid, dimThreadBlock>>>(in_d,out_d,num_elements,i);
hipDeviceSynchronize();
cudaCheckError();
preScan(out_scan_d, out_d, num_elements);
hipDeviceSynchronize();
cudaCheckError();
indexDefine<<<dimGrid, dimThreadBlock>>>(out_scan_d, out_d, num_elements, in_h[num_elements - 1]);
hipDeviceSynchronize();
cudaCheckError();
scatterElements<<<dimGrid, dimThreadBlock>>>(in_d, out_scan_d, out_d, num_elements);
hipDeviceSynchronize();
cudaCheckError();
// swap pointers
temp = in_d;
in_d = out_d;
out_d = temp;
}
}
int compare(const void *a, const void *b) {
int a1 = *((unsigned int*)a);
int b1 = *((unsigned int*)b);
if (a1 == b1) return 0;
else if (a1 < b1) return -1;
else return 1;
}
int main(){
Timer timer;
unsigned int *in_h;
unsigned int *out_h;
unsigned int *out_d;
unsigned int *in_d;
unsigned int *out_scan_d;
unsigned int num_elements = 1000000;
in_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
out_h = (unsigned int*) malloc(num_elements*sizeof(unsigned int));
unsigned int *out_scan_h = (unsigned int *)malloc(num_elements * sizeof(unsigned int));
hipMalloc((void**)&in_d, num_elements * sizeof(unsigned int));
cudaCheckError();
hipMalloc((void**)&out_d, num_elements * sizeof(unsigned int));
cudaCheckError();
hipMalloc((void**)&out_scan_d, num_elements * sizeof(unsigned int ));
cudaCheckError();
hipDeviceSynchronize();
//init array
for(int i = 0;i < num_elements;i++) {
in_h[i] = num_elements - 1 - i;
}
// Copy host variables to device ------------------------------------------
hipMemcpy(in_d, in_h, num_elements * sizeof(unsigned int),
hipMemcpyHostToDevice);
cudaCheckError();
hipDeviceSynchronize();
// Launch kernel ----------------------------------------------------------
startTime(&timer);
radix_sort(in_d, out_d, out_scan_d, in_h, out_scan_h, num_elements);
hipDeviceSynchronize();
cudaCheckError();
stopTime(&timer); printf("GPU Sort time: %f s\n", elapsedTime(timer));
cudaCheckError();
// Copy device variables from host ----------------------------------------
hipMemcpy(out_h, out_d, num_elements * sizeof(unsigned int),
hipMemcpyDeviceToHost);
cudaCheckError();
hipDeviceSynchronize();
// Verify correctness -----------------------------------------------------
qsort(in_h, num_elements, sizeof(unsigned int),compare);
int flag = 0;
for (int i = 0;i < num_elements;i++) {
if (in_h[i] != out_h[i]) {
flag = 1;
break;
}
}
if (flag == 1) {
printf("test failed\n");
} else
printf("test passed\n");
// Free memory
hipFree(in_d);
hipFree(out_scan_d);
hipFree(out_d);
free(in_h);
free(out_h);
return 0;
} | .text
.file "bit_based_radix_sort.hip"
.globl _Z9startTimeP5Timer # -- Begin function _Z9startTimeP5Timer
.p2align 4, 0x90
.type _Z9startTimeP5Timer,@function
_Z9startTimeP5Timer: # @_Z9startTimeP5Timer
.cfi_startproc
# %bb.0:
xorl %esi, %esi
jmp gettimeofday # TAILCALL
.Lfunc_end0:
.size _Z9startTimeP5Timer, .Lfunc_end0-_Z9startTimeP5Timer
.cfi_endproc
# -- End function
.globl _Z8stopTimeP5Timer # -- Begin function _Z8stopTimeP5Timer
.p2align 4, 0x90
.type _Z8stopTimeP5Timer,@function
_Z8stopTimeP5Timer: # @_Z8stopTimeP5Timer
.cfi_startproc
# %bb.0:
addq $16, %rdi
xorl %esi, %esi
jmp gettimeofday # TAILCALL
.Lfunc_end1:
.size _Z8stopTimeP5Timer, .Lfunc_end1-_Z8stopTimeP5Timer
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z11elapsedTime5Timer
.LCPI2_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z11elapsedTime5Timer
.p2align 4, 0x90
.type _Z11elapsedTime5Timer,@function
_Z11elapsedTime5Timer: # @_Z11elapsedTime5Timer
.cfi_startproc
# %bb.0:
movq 24(%rsp), %rax
movq 32(%rsp), %rcx
subq 8(%rsp), %rax
cvtsi2sd %rax, %xmm0
subq 16(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
divsd .LCPI2_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
retq
.Lfunc_end2:
.size _Z11elapsedTime5Timer, .Lfunc_end2-_Z11elapsedTime5Timer
.cfi_endproc
# -- End function
.globl _Z20__device_stub__splitPjS_ji # -- Begin function _Z20__device_stub__splitPjS_ji
.p2align 4, 0x90
.type _Z20__device_stub__splitPjS_ji,@function
_Z20__device_stub__splitPjS_ji: # @_Z20__device_stub__splitPjS_ji
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z5splitPjS_ji, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z20__device_stub__splitPjS_ji, .Lfunc_end3-_Z20__device_stub__splitPjS_ji
.cfi_endproc
# -- End function
.globl _Z28__device_stub__exclusiveScanPjS_S_j # -- Begin function _Z28__device_stub__exclusiveScanPjS_S_j
.p2align 4, 0x90
.type _Z28__device_stub__exclusiveScanPjS_S_j,@function
_Z28__device_stub__exclusiveScanPjS_S_j: # @_Z28__device_stub__exclusiveScanPjS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13exclusiveScanPjS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end4:
.size _Z28__device_stub__exclusiveScanPjS_S_j, .Lfunc_end4-_Z28__device_stub__exclusiveScanPjS_S_j
.cfi_endproc
# -- End function
.globl _Z30__device_stub__mergeScanBlocksPjS_i # -- Begin function _Z30__device_stub__mergeScanBlocksPjS_i
.p2align 4, 0x90
.type _Z30__device_stub__mergeScanBlocksPjS_i,@function
_Z30__device_stub__mergeScanBlocksPjS_i: # @_Z30__device_stub__mergeScanBlocksPjS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15mergeScanBlocksPjS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end5:
.size _Z30__device_stub__mergeScanBlocksPjS_i, .Lfunc_end5-_Z30__device_stub__mergeScanBlocksPjS_i
.cfi_endproc
# -- End function
.globl _Z7preScanPjS_j # -- Begin function _Z7preScanPjS_j
.p2align 4, 0x90
.type _Z7preScanPjS_j,@function
_Z7preScanPjS_j: # @_Z7preScanPjS_j
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movq %rsi, %rbp
movq %rdi, %r14
movl %edx, %r15d
shrl $9, %r15d
movl %edx, %eax
andl $511, %eax # imm = 0x1FF
cmpl $1, %eax
sbbl $-1, %r15d
movl %r15d, %eax
shrl %eax
andl $1, %r15d
addl %eax, %r15d
movq $0, 24(%rsp)
cmpl $1025, %edx # imm = 0x401
jb .LBB6_4
# %bb.1:
leaq (,%r15,4), %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB6_2
.LBB6_4:
movabsq $4294967808, %r12 # imm = 0x100000200
leaq (%r15,%r12), %r13
addq $-512, %r13 # imm = 0xFE00
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_6
# %bb.5:
movq 24(%rsp), %rax
movq %r14, 88(%rsp)
movq %rbp, 80(%rsp)
movq %rax, 40(%rsp)
movl %ebx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13exclusiveScanPjS_S_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_6:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB6_7
# %bb.8:
cmpl $1025, %ebx # imm = 0x401
jb .LBB6_16
# %bb.9:
leaq (,%r15,4), %rsi
leaq 16(%rsp), %rdi
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB6_10
# %bb.11:
movq 16(%rsp), %rdi
movq 24(%rsp), %rsi
movl %r15d, %edx
callq _Z7preScanPjS_j
movq %r13, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_13
# %bb.12:
movq 16(%rsp), %rax
movq %rax, 88(%rsp)
movq %r14, 80(%rsp)
movl %ebx, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15mergeScanBlocksPjS_i, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_13:
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB6_14
# %bb.15:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
.LBB6_16:
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_7:
.cfi_def_cfa_offset 192
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $151, %edx
jmp .LBB6_3
.LBB6_2:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $147, %edx
jmp .LBB6_3
.LBB6_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $159, %edx
jmp .LBB6_3
.LBB6_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $165, %edx
.LBB6_3:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end6:
.size _Z7preScanPjS_j, .Lfunc_end6-_Z7preScanPjS_j
.cfi_endproc
# -- End function
.globl _Z26__device_stub__indexDefinePjS_jj # -- Begin function _Z26__device_stub__indexDefinePjS_jj
.p2align 4, 0x90
.type _Z26__device_stub__indexDefinePjS_jj,@function
_Z26__device_stub__indexDefinePjS_jj: # @_Z26__device_stub__indexDefinePjS_jj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11indexDefinePjS_jj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z26__device_stub__indexDefinePjS_jj, .Lfunc_end7-_Z26__device_stub__indexDefinePjS_jj
.cfi_endproc
# -- End function
.globl _Z30__device_stub__scatterElementsPjS_S_j # -- Begin function _Z30__device_stub__scatterElementsPjS_S_j
.p2align 4, 0x90
.type _Z30__device_stub__scatterElementsPjS_S_j,@function
_Z30__device_stub__scatterElementsPjS_S_j: # @_Z30__device_stub__scatterElementsPjS_S_j
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z15scatterElementsPjS_S_j, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end8:
.size _Z30__device_stub__scatterElementsPjS_S_j, .Lfunc_end8-_Z30__device_stub__scatterElementsPjS_S_j
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10radix_sortPjS_S_S_S_i
.LCPI9_0:
.quad 0x3f60000000000000 # double 0.001953125
.text
.globl _Z10radix_sortPjS_S_S_S_i
.p2align 4, 0x90
.type _Z10radix_sortPjS_S_S_S_i,@function
_Z10radix_sortPjS_S_S_S_i: # @_Z10radix_sortPjS_S_S_S_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movq %rcx, 144(%rsp) # 8-byte Spill
movq %rdx, 88(%rsp) # 8-byte Spill
movq %rsi, %r14
movq %rdi, %r12
movabsq $4294967808, %r15 # imm = 0x100000200
cvtsi2sd %r9d, %xmm0
mulsd .LCPI9_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %eax
leaq (%rax,%r15), %rbp
addq $-512, %rbp # imm = 0xFE00
movslq %ebx, %rax
movq %rax, 136(%rsp) # 8-byte Spill
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB9_2: # =>This Inner Loop Header: Depth=1
movq %r12, %r15
movq %rbp, %rdi
movl $1, %esi
movabsq $4294967808, %r12 # imm = 0x100000200
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_4
# %bb.3: # in Loop: Header=BB9_2 Depth=1
movq %r15, 80(%rsp)
movq %r14, 72(%rsp)
movl %ebx, 16(%rsp)
movl %r13d, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z5splitPjS_ji, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_4: # in Loop: Header=BB9_2 Depth=1
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB9_5
# %bb.7: # in Loop: Header=BB9_2 Depth=1
movq 88(%rsp), %rdi # 8-byte Reload
movq %r14, %rsi
movl %ebx, %edx
callq _Z7preScanPjS_j
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB9_8
# %bb.9: # in Loop: Header=BB9_2 Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_11
# %bb.10: # in Loop: Header=BB9_2 Depth=1
movq 144(%rsp), %rax # 8-byte Reload
movq 136(%rsp), %rcx # 8-byte Reload
movl -4(%rax,%rcx,4), %eax
movq 88(%rsp), %rcx # 8-byte Reload
movq %rcx, 80(%rsp)
movq %r14, 72(%rsp)
movl %ebx, 16(%rsp)
movl %eax, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z11indexDefinePjS_jj, %edi
leaq 96(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_11: # in Loop: Header=BB9_2 Depth=1
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB9_12
# %bb.13: # in Loop: Header=BB9_2 Depth=1
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_15
# %bb.14: # in Loop: Header=BB9_2 Depth=1
movq %r15, 80(%rsp)
movq 88(%rsp), %rax # 8-byte Reload
movq %rax, 72(%rsp)
movq %r14, 64(%rsp)
movl %ebx, 12(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 12(%rsp), %rax
movq %rax, 120(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movl $_Z15scatterElementsPjS_S_j, %edi
leaq 96(%rsp), %r9
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_15: # in Loop: Header=BB9_2 Depth=1
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB9_16
# %bb.1: # in Loop: Header=BB9_2 Depth=1
incl %r13d
movq %r14, %r12
movq %r15, %r14
cmpl $32, %r13d
jne .LBB9_2
# %bb.17:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB9_16:
.cfi_def_cfa_offset 208
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $224, %edx
jmp .LBB9_6
.LBB9_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $221, %edx
jmp .LBB9_6
.LBB9_8:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $218, %edx
jmp .LBB9_6
.LBB9_5:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $215, %edx
.LBB9_6:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end9:
.size _Z10radix_sortPjS_S_S_S_i, .Lfunc_end9-_Z10radix_sortPjS_S_S_S_i
.cfi_endproc
# -- End function
.globl _Z7comparePKvS0_ # -- Begin function _Z7comparePKvS0_
.p2align 4, 0x90
.type _Z7comparePKvS0_,@function
_Z7comparePKvS0_: # @_Z7comparePKvS0_
.cfi_startproc
# %bb.0:
movl (%rdi), %eax
xorl %ecx, %ecx
xorl %edx, %edx
cmpl (%rsi), %eax
setge %dl
leal -1(%rdx,%rdx), %eax
cmovel %ecx, %eax
retq
.Lfunc_end10:
.size _Z7comparePKvS0_, .Lfunc_end10-_Z7comparePKvS0_
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI11_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $56, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq malloc
movq %rax, %r14
movq %rsp, %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB11_1
# %bb.3:
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB11_4
# %bb.5:
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
callq hipGetLastError
testl %eax, %eax
jne .LBB11_6
# %bb.7:
callq hipDeviceSynchronize
movl $999999, %eax # imm = 0xF423F
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB11_8: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rcx,4)
incq %rcx
decl %eax
cmpq $1000000, %rcx # imm = 0xF4240
jne .LBB11_8
# %bb.9:
movq (%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB11_10
# %bb.11:
callq hipDeviceSynchronize
leaq 24(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq (%rsp), %rdi
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
movq %rbx, %rcx
movl $1000000, %r9d # imm = 0xF4240
callq _Z10radix_sortPjS_S_S_S_i
callq hipDeviceSynchronize
callq hipGetLastError
testl %eax, %eax
jne .LBB11_12
# %bb.13:
leaq 40(%rsp), %rdi
xorl %esi, %esi
callq gettimeofday
movq 40(%rsp), %rax
movq 48(%rsp), %rcx
subq 24(%rsp), %rax
cvtsi2sd %rax, %xmm0
subq 32(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
divsd .LCPI11_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.2, %edi
movb $1, %al
callq printf
callq hipGetLastError
testl %eax, %eax
jne .LBB11_14
# %bb.15:
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
callq hipGetLastError
testl %eax, %eax
jne .LBB11_16
# %bb.19:
callq hipDeviceSynchronize
movl $1000000, %esi # imm = 0xF4240
movl $4, %edx
movl $_Z7comparePKvS0_, %ecx
movq %rbx, %rdi
callq qsort
xorl %eax, %eax
.p2align 4, 0x90
.LBB11_20: # =>This Inner Loop Header: Depth=1
movl (%rbx,%rax,4), %ecx
cmpl (%r14,%rax,4), %ecx
jne .LBB11_21
# %bb.17: # in Loop: Header=BB11_20 Depth=1
incq %rax
cmpq $1000000, %rax # imm = 0xF4240
jne .LBB11_20
# %bb.18:
movl $.Lstr, %edi
jmp .LBB11_22
.LBB11_21:
movl $.Lstr.1, %edi
.LBB11_22: # %.critedge
callq puts@PLT
movq (%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB11_1:
.cfi_def_cfa_offset 80
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $257, %edx # imm = 0x101
jmp .LBB11_2
.LBB11_4:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $259, %edx # imm = 0x103
jmp .LBB11_2
.LBB11_6:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $261, %edx # imm = 0x105
jmp .LBB11_2
.LBB11_10:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $272, %edx # imm = 0x110
jmp .LBB11_2
.LBB11_12:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $280, %edx # imm = 0x118
jmp .LBB11_2
.LBB11_14:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $283, %edx # imm = 0x11B
jmp .LBB11_2
.LBB11_16:
movl %eax, %edi
callq hipGetErrorString
movl $.L.str, %edi
movl $.L.str.1, %esi
movl $290, %edx # imm = 0x122
.LBB11_2:
movq %rax, %rcx
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end11:
.size main, .Lfunc_end11-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB12_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB12_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5splitPjS_ji, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13exclusiveScanPjS_S_j, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15mergeScanBlocksPjS_i, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11indexDefinePjS_jj, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15scatterElementsPjS_S_j, %esi
movl $.L__unnamed_5, %edx
movl $.L__unnamed_5, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end12:
.size __hip_module_ctor, .Lfunc_end12-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB13_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB13_2:
retq
.Lfunc_end13:
.size __hip_module_dtor, .Lfunc_end13-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z5splitPjS_ji,@object # @_Z5splitPjS_ji
.section .rodata,"a",@progbits
.globl _Z5splitPjS_ji
.p2align 3, 0x0
_Z5splitPjS_ji:
.quad _Z20__device_stub__splitPjS_ji
.size _Z5splitPjS_ji, 8
.type _Z13exclusiveScanPjS_S_j,@object # @_Z13exclusiveScanPjS_S_j
.globl _Z13exclusiveScanPjS_S_j
.p2align 3, 0x0
_Z13exclusiveScanPjS_S_j:
.quad _Z28__device_stub__exclusiveScanPjS_S_j
.size _Z13exclusiveScanPjS_S_j, 8
.type _Z15mergeScanBlocksPjS_i,@object # @_Z15mergeScanBlocksPjS_i
.globl _Z15mergeScanBlocksPjS_i
.p2align 3, 0x0
_Z15mergeScanBlocksPjS_i:
.quad _Z30__device_stub__mergeScanBlocksPjS_i
.size _Z15mergeScanBlocksPjS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Cuda failure %s:%d: '%s'\n"
.size .L.str, 26
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "/home/ubuntu/Datasets/stackv2/train-structured-repos-hip/rkzheng/parallel-radix-sort/master/bit_based_radix_sort.hip"
.size .L.str.1, 117
.type _Z11indexDefinePjS_jj,@object # @_Z11indexDefinePjS_jj
.section .rodata,"a",@progbits
.globl _Z11indexDefinePjS_jj
.p2align 3, 0x0
_Z11indexDefinePjS_jj:
.quad _Z26__device_stub__indexDefinePjS_jj
.size _Z11indexDefinePjS_jj, 8
.type _Z15scatterElementsPjS_S_j,@object # @_Z15scatterElementsPjS_S_j
.globl _Z15scatterElementsPjS_S_j
.p2align 3, 0x0
_Z15scatterElementsPjS_S_j:
.quad _Z30__device_stub__scatterElementsPjS_S_j
.size _Z15scatterElementsPjS_S_j, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "GPU Sort time: %f s\n"
.size .L.str.2, 21
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z5splitPjS_ji"
.size .L__unnamed_1, 15
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13exclusiveScanPjS_S_j"
.size .L__unnamed_2, 25
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z15mergeScanBlocksPjS_i"
.size .L__unnamed_3, 25
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z11indexDefinePjS_jj"
.size .L__unnamed_4, 22
.type .L__unnamed_5,@object # @4
.L__unnamed_5:
.asciz "_Z15scatterElementsPjS_S_j"
.size .L__unnamed_5, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "test passed"
.size .Lstr, 12
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "test failed"
.size .Lstr.1, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z20__device_stub__splitPjS_ji
.addrsig_sym _Z28__device_stub__exclusiveScanPjS_S_j
.addrsig_sym _Z30__device_stub__mergeScanBlocksPjS_i
.addrsig_sym _Z26__device_stub__indexDefinePjS_jj
.addrsig_sym _Z30__device_stub__scatterElementsPjS_S_j
.addrsig_sym _Z7comparePKvS0_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z5splitPjS_ji
.addrsig_sym _Z13exclusiveScanPjS_S_j
.addrsig_sym _Z15mergeScanBlocksPjS_i
.addrsig_sym _Z11indexDefinePjS_jj
.addrsig_sym _Z15scatterElementsPjS_S_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
/**
* In this section, we will discover concurrent operation in CUDA
* 1) blocks in grid: concurrent tasks, no gurantee their order of execution (no synchronization)
* 2) warp in blocks: concurrent threads, explicitly synchronizable (it will be discussed in next section)
* 3) thread in warp: implicitly synchronized
*/
__global__ void idx_print()
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int warp_idx = threadIdx.x / warpSize;
int lane_idx = threadIdx.x & (warpSize - 1);
if ((lane_idx & (warpSize/2 - 1)) == 0)
// thread, block, warp, lane"
printf(" %5d\t%5d\t %2d\t%2d\n", idx, blockIdx.x, warp_idx, lane_idx);
}
int main(int argc, char* argv[])
{
if (argc == 1) {
puts("Please put Block Size and Thread Block Size..");
puts("./cuda_thread_block [grid size] [block size]");
puts("e.g.) ./cuda_thread_block 4 128");
exit(1);
}
int gridSize = atoi(argv[1]);
int blockSize = atoi(argv[2]);
puts("thread, block, warp, lane");
idx_print<<<gridSize, blockSize>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z9idx_printv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x10, RZ ; /* 0xfffffff001017810 */
/* 0x000fc80007ffe0ff */
/*0030*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe40007f1e0ff */
/*0040*/ LOP3.LUT R11, R8, 0x1f, RZ, 0xc0, !PT ; /* 0x0000001f080b7812 */
/* 0x001fc800078ec0ff */
/*0050*/ LOP3.LUT P1, RZ, R11, 0xf, RZ, 0xc0, !PT ; /* 0x0000000f0bff7812 */
/* 0x000fda000782c0ff */
/*0060*/ @P1 EXIT ; /* 0x000000000000194d */
/* 0x000fea0003800000 */
/*0070*/ I2F.U32.RP R0, 0x20 ; /* 0x0000002000007906 */
/* 0x000e220000209000 */
/*0080*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e620000002500 */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*00a0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fc800078e00ff */
/*00b0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00c0*/ IADD3 R2, R0, 0xffffffe, RZ ; /* 0x0ffffffe00027810 */
/* 0x001fcc0007ffe0ff */
/*00d0*/ F2I.FTZ.U32.TRUNC.NTZ R3, R2 ; /* 0x0000000200037305 */
/* 0x0000a4000021f000 */
/*00e0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x001fe400078e00ff */
/*00f0*/ IMAD.U32 R5, R3, -0x20, RZ ; /* 0xffffffe003057824 */
/* 0x004fc800078e00ff */
/*0100*/ IMAD.HI.U32 R3, R3, R5, R2 ; /* 0x0000000503037227 */
/* 0x000fe200078e0002 */
/*0110*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fc60000000f00 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0130*/ IMAD.HI.U32 R10, R3, R8, RZ ; /* 0x00000008030a7227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD R3, R10, -0x20, R8.reuse ; /* 0xffffffe00a037824 */
/* 0x100fe400078e0208 */
/*0150*/ IMAD R8, R9, c[0x0][0x0], R8 ; /* 0x0000000009087a24 */
/* 0x002fc600078e0208 */
/*0160*/ ISETP.GE.U32.AND P1, PT, R3, 0x20, PT ; /* 0x000000200300780c */
/* 0x000fda0003f26070 */
/*0170*/ @P1 IADD3 R3, R3, -0x20, RZ ; /* 0xffffffe003031810 */
/* 0x000fe40007ffe0ff */
/*0180*/ @P1 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a1810 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.GE.U32.AND P2, PT, R3, 0x20, PT ; /* 0x000000200300780c */
/* 0x000fe40003f46070 */
/*01a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e360000000a00 */
/*01b0*/ @P2 IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a2810 */
/* 0x000fca0007ffe0ff */
/*01c0*/ STL.128 [R1], R8 ; /* 0x0000000801007387 */
/* 0x0003e40000100c00 */
/*01d0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x002fe40000000000 */
/*01e0*/ MOV R11, 0x250 ; /* 0x00000250000b7802 */
/* 0x000fe40000000f00 */
/*01f0*/ MOV R20, 0x1d0 ; /* 0x000001d000147802 */
/* 0x000fe40000000f00 */
/*0200*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*0210*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*0220*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0230*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0240*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0250*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0260*/ BRA 0x260; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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