system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
__global__ void my_copysign(double* v)
{
int i = threadIdx.x;
*v = std::copysign(*v, double(i == 0 ? 1 : -1));
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11my_copysignPd
.globl _Z11my_copysignPd
.p2align 8
.type _Z11my_copysignPd,@function
_Z11my_copysignPd:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_cndmask_b32_e64 v0, -1, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[0:1], v0
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s2
v_bfi_b32 v1, 0x7fffffff, s3, v1
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11my_copysignPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11my_copysignPd, .Lfunc_end0-_Z11my_copysignPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11my_copysignPd
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11my_copysignPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
__global__ void my_copysign(double* v)
{
int i = threadIdx.x;
*v = std::copysign(*v, double(i == 0 ? 1 : -1));
} | .text
.file "copysign.hip"
.globl _Z26__device_stub__my_copysignPd # -- Begin function _Z26__device_stub__my_copysignPd
.p2align 4, 0x90
.type _Z26__device_stub__my_copysignPd,@function
_Z26__device_stub__my_copysignPd: # @_Z26__device_stub__my_copysignPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11my_copysignPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__my_copysignPd, .Lfunc_end0-_Z26__device_stub__my_copysignPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11my_copysignPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11my_copysignPd,@object # @_Z11my_copysignPd
.section .rodata,"a",@progbits
.globl _Z11my_copysignPd
.p2align 3, 0x0
_Z11my_copysignPd:
.quad _Z26__device_stub__my_copysignPd
.size _Z11my_copysignPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11my_copysignPd"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__my_copysignPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11my_copysignPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11my_copysignPd
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fca00078e00ff */
/*0040*/ LDG.E.64 R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea2000c1e1b00 */
/*0050*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fc600078e00ff */
/*0060*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0070*/ ISETP.NE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x001fc80003f05270 */
/*0080*/ SEL R6, R6, 0xffffffff, !P0 ; /* 0xffffffff06067807 */
/* 0x000fcc0004000000 */
/*0090*/ I2F.F64 R6, R6 ; /* 0x0000000600067312 */
/* 0x000e220000201c00 */
/*00a0*/ LOP3.LUT R5, R5, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff05057812 */
/* 0x004fc800078ec0ff */
/*00b0*/ LOP3.LUT R5, R5, 0x80000000, R7, 0xf8, !PT ; /* 0x8000000005057812 */
/* 0x001fca00078ef807 */
/*00c0*/ STG.E.64 [R2.64], R4 ; /* 0x0000000402007986 */
/* 0x000fe2000c101b04 */
/*00d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00e0*/ BRA 0xe0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11my_copysignPd
.globl _Z11my_copysignPd
.p2align 8
.type _Z11my_copysignPd,@function
_Z11my_copysignPd:
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_load_b64 s[0:1], s[0:1], 0x0
v_mov_b32_e32 v2, 0
v_cndmask_b32_e64 v0, -1, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
v_cvt_f64_i32_e32 v[0:1], v0
s_waitcnt lgkmcnt(0)
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mov_b32_e32 v0, s2
v_bfi_b32 v1, 0x7fffffff, s3, v1
global_store_b64 v2, v[0:1], s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11my_copysignPd
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11my_copysignPd, .Lfunc_end0-_Z11my_copysignPd
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11my_copysignPd
.private_segment_fixed_size: 0
.sgpr_count: 6
.sgpr_spill_count: 0
.symbol: _Z11my_copysignPd.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00091187_00000000-6_copysign.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z11my_copysignPdPd
.type _Z31__device_stub__Z11my_copysignPdPd, @function
_Z31__device_stub__Z11my_copysignPdPd:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z11my_copysignPd(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z31__device_stub__Z11my_copysignPdPd, .-_Z31__device_stub__Z11my_copysignPdPd
.globl _Z11my_copysignPd
.type _Z11my_copysignPd, @function
_Z11my_copysignPd:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z11my_copysignPdPd
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z11my_copysignPd, .-_Z11my_copysignPd
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11my_copysignPd"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11my_copysignPd(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "copysign.hip"
.globl _Z26__device_stub__my_copysignPd # -- Begin function _Z26__device_stub__my_copysignPd
.p2align 4, 0x90
.type _Z26__device_stub__my_copysignPd,@function
_Z26__device_stub__my_copysignPd: # @_Z26__device_stub__my_copysignPd
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z11my_copysignPd, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z26__device_stub__my_copysignPd, .Lfunc_end0-_Z26__device_stub__my_copysignPd
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11my_copysignPd, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11my_copysignPd,@object # @_Z11my_copysignPd
.section .rodata,"a",@progbits
.globl _Z11my_copysignPd
.p2align 3, 0x0
_Z11my_copysignPd:
.quad _Z26__device_stub__my_copysignPd
.size _Z11my_copysignPd, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11my_copysignPd"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__my_copysignPd
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11my_copysignPd
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /* Copyright 2017 Eric Aubanel
* This file contains code implementing Algorithm 4.14 from
* Elements of Parallel Computing, by Eric Aubanel, 2016, CRC Press.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* -------------------------------------------------------------------
* Implementation of reduction of n floats using CUDA
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
int isPowerOf2(int n);
//reduce n floats in array a to a partial sum for each block,
//stored in array c. Block size must be power of 2
__global__ void reductionGPU(float *a, float *c, int n){
//size of b indicated by kernel call in main (blockSize)
extern __shared__ float b[];
int gsize = blockDim.x; //block size
int nt = gsize * gridDim.x; //total number of threads
int gid = blockIdx.x; //block id
int tid = threadIdx.x; //local thread id
int id = gid*gsize + tid; //global thread id
//if n<nt, then some threads will have nothing to do
int istart;
int iend;
if(n<nt){
istart = id;
iend = id;
}
else{
//evaluate as float to avoid overflow
istart = (float)id*n/nt;
iend = (float)(id+1)*n/nt - 1;
}
if(n<nt && id>=n){
b[tid] = 0;
}else{
float psum = 0.0;
for(int i=istart; i<=iend; i++)
psum += a[i];
b[tid] = psum;
}
__syncthreads();
for(int j=gsize>>1; j>=1; j >>= 1){
if(tid<j)
b[tid] += b[tid+j];
__syncthreads();
}
c[gid] = b[0];
}
int main(int argc, char **argv){
float *a_h; //array to be reduced on host (CPU)
float *c_h; //array of partial sums on host
float *a_d; //array to be reduced on device (GPU)
float *c_d; //array of partial sums on device
cudaError_t error1, error2;
struct timespec tstart, tend;
float time;
if(argc < 4){
fprintf(stderr,"usage: %s n blockSize numBlocks\n", argv[0]);
return 1;
}
int n = strtol(argv[1], NULL, 10);
int blockSize = strtol(argv[2], NULL, 10); //size of thread block on device
int numBlocks = strtol(argv[3], NULL, 10); //number of blocks on device
if(!isPowerOf2(blockSize)){
fprintf(stderr,"blockSize must be power of 2\n");
return 1;
}
//memory allocation on host and device
a_h = (float *)malloc(n*sizeof(float));
c_h = (float *)malloc(numBlocks*sizeof(float));
if(a_h == NULL || c_h == NULL){
fprintf(stderr,"couldn't allocate memory on host\n");
return 1;
}
error1 = cudaMalloc((void **)&a_d, n*sizeof(float));
error2 = cudaMalloc((void **)&c_d, numBlocks*sizeof(float));
if(error1 != cudaSuccess || error2 != cudaSuccess){
fprintf(stderr,"couldn't allocate memory on device\n");
return 1;
}
for(int i=0; i<n; i++)
a_h[i] = rand()%100;
//sequential reduction for verification and timing
clock_gettime(CLOCK_MONOTONIC, &tstart);
float sum = 0.0;
for(int i=0; i<n; i++)
sum += a_h[i];
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("CPU reduction time in s: %f\n", time);
//timing won't include transfer of array to device
cudaMemcpy(a_d, a_h, n*sizeof(float), cudaMemcpyHostToDevice);
clock_gettime(CLOCK_MONOTONIC, &tstart);
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error1 = cudaThreadSynchronize();// wait until GPU kernel finished
if(error1 != cudaSuccess){
fprintf(stderr,"error executing kernel: %s\n", cudaGetErrorString(error1));
return 1;
}
//Do not copy back to host and do CPU reduction. Do it on the GPU recersively.
while(1){
cudaMemset(a_d, 0, n);
n = numBlocks;
numBlocks = n/blockSize + ((n%blockSize==0)?0:1);
cudaMemcpy(a_d, c_d, n*sizeof(float), cudaMemcpyDeviceToDevice);
cudaMemset(c_d, 0, n*sizeof(float));
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error2 = cudaThreadSynchronize();// wait until GPU kernel finished
if(error2 != cudaSuccess){
fprintf(stderr,"error executing kernel: %s\n", cudaGetErrorString(error2));
return 1;
}
cudaMemcpy(c_h, c_d, numBlocks*sizeof(float), cudaMemcpyDeviceToHost);
if(numBlocks==1)break;
}
cudaMemcpy(c_h, c_d, numBlocks*sizeof(float), cudaMemcpyDeviceToHost);
float dsum = c_h[0];
printf("dsum: %f\n", dsum);
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("GPUS time in s: %f\n", time);
//not necessarily the same because of differences in roundoff error
printf("relative difference between sequential and parallel sums: %g\n",
fabs(dsum-sum)/sum);
return 0;
}
int isPowerOf2(int n){
while(n){
if(n & 1)
break;
n >>= 1;
}
return (1 == n? 1:0);
} | code for sm_80
Function : _Z12reductionGPUPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe400078e00ff */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e220000002100 */
/*0050*/ IMAD R2, R2, c[0x0][0xc], RZ ; /* 0x0000030002027a24 */
/* 0x000fca00078e02ff */
/*0060*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], PT ; /* 0x00005c0002007a0c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R3, R0, c[0x0][0x0], R5 ; /* 0x0000000000037a24 */
/* 0x001fc800078e0205 */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0003 */
/*0090*/ MOV R7, R3 ; /* 0x0000000300077202 */
/* 0x000fce0000000f00 */
/*00a0*/ @P0 BRA 0x300 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*00b0*/ I2F R6, R2 ; /* 0x0000000200067306 */
/* 0x000e220000201400 */
/*00c0*/ BSSY B0, 0x1c0 ; /* 0x000000f000007945 */
/* 0x000fee0003800000 */
/*00d0*/ I2F R7, R3 ; /* 0x0000000300077306 */
/* 0x000ff00000201400 */
/*00e0*/ I2F R8, c[0x0][0x170] ; /* 0x00005c0000087b06 */
/* 0x000e700000201400 */
/*00f0*/ MUFU.RCP R9, R6 ; /* 0x0000000600097308 */
/* 0x001e220000001000 */
/*0100*/ FMUL R7, R7, R8 ; /* 0x0000000807077220 */
/* 0x002fce0000400000 */
/*0110*/ FCHK P0, R7, R6 ; /* 0x0000000607007302 */
/* 0x000e620000000000 */
/*0120*/ FFMA R10, -R6, R9, 1 ; /* 0x3f800000060a7423 */
/* 0x001fc80000000109 */
/*0130*/ FFMA R10, R9, R10, R9 ; /* 0x0000000a090a7223 */
/* 0x000fc80000000009 */
/*0140*/ FFMA R9, R7, R10, RZ ; /* 0x0000000a07097223 */
/* 0x000fc800000000ff */
/*0150*/ FFMA R11, -R6, R9, R7 ; /* 0x00000009060b7223 */
/* 0x000fc80000000107 */
/*0160*/ FFMA R9, R10, R11, R9 ; /* 0x0000000b0a097223 */
/* 0x000fe20000000009 */
/*0170*/ @!P0 BRA 0x1b0 ; /* 0x0000003000008947 */
/* 0x002fea0003800000 */
/*0180*/ IMAD.MOV.U32 R13, RZ, RZ, R7 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e0007 */
/*0190*/ MOV R10, 0x1b0 ; /* 0x000001b0000a7802 */
/* 0x000fe40000000f00 */
/*01a0*/ CALL.REL.NOINC 0xbd0 ; /* 0x00000a2000007944 */
/* 0x000fea0003c00000 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R10, R3, 0x1, RZ ; /* 0x00000001030a7810 */
/* 0x000fe20007ffe0ff */
/*01d0*/ MUFU.RCP R13, R6 ; /* 0x00000006000d7308 */
/* 0x000e620000001000 */
/*01e0*/ BSSY B0, 0x2e0 ; /* 0x000000f000007945 */
/* 0x000fee0003800000 */
/*01f0*/ I2F R11, R10 ; /* 0x0000000a000b7306 */
/* 0x000ea20000201400 */
/*0200*/ FFMA R12, -R6, R13, 1 ; /* 0x3f800000060c7423 */
/* 0x002fce000000010d */
/*0210*/ F2I.TRUNC.NTZ R7, R9 ; /* 0x0000000900077305 */
/* 0x001fe2000020f100 */
/*0220*/ FFMA R12, R13, R12, R13 ; /* 0x0000000c0d0c7223 */
/* 0x000fe4000000000d */
/*0230*/ FMUL R11, R8, R11 ; /* 0x0000000b080b7220 */
/* 0x004fca0000400000 */
/*0240*/ FCHK P0, R11, R6 ; /* 0x000000060b007302 */
/* 0x000e220000000000 */
/*0250*/ FFMA R8, R12, R11, RZ ; /* 0x0000000b0c087223 */
/* 0x000fc800000000ff */
/*0260*/ FFMA R13, -R6, R8, R11 ; /* 0x00000008060d7223 */
/* 0x000fc8000000010b */
/*0270*/ FFMA R8, R12, R13, R8 ; /* 0x0000000d0c087223 */
/* 0x000fe20000000008 */
/*0280*/ @!P0 BRA 0x2d0 ; /* 0x0000004000008947 */
/* 0x001fea0003800000 */
/*0290*/ IMAD.MOV.U32 R13, RZ, RZ, R11 ; /* 0x000000ffff0d7224 */
/* 0x000fe200078e000b */
/*02a0*/ MOV R10, 0x2c0 ; /* 0x000002c0000a7802 */
/* 0x000fe40000000f00 */
/*02b0*/ CALL.REL.NOINC 0xbd0 ; /* 0x0000091000007944 */
/* 0x000fea0003c00000 */
/*02c0*/ MOV R8, R9 ; /* 0x0000000900087202 */
/* 0x001fe40000000f00 */
/*02d0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*02e0*/ FADD R8, R8, -1 ; /* 0xbf80000008087421 */
/* 0x000fc80000000000 */
/*02f0*/ F2I.TRUNC.NTZ R6, R8 ; /* 0x0000000800067305 */
/* 0x000066000020f100 */
/*0300*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x170], PT ; /* 0x00005c0003007a0c */
/* 0x000fe20003f06270 */
/*0310*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0320*/ BSSY B0, 0xa70 ; /* 0x0000074000007945 */
/* 0x000fe20003800000 */
/*0330*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x001fe200078e00ff */
/*0340*/ ISETP.GT.AND P0, PT, R2, c[0x0][0x170], P0 ; /* 0x00005c0002007a0c */
/* 0x000fc80000704270 */
/*0350*/ ISETP.LT.OR P0, PT, R6, R7, P0 ; /* 0x000000070600720c */
/* 0x002fda0000701670 */
/*0360*/ @P0 BRA 0xa60 ; /* 0x000006f000000947 */
/* 0x000fea0003800000 */
/*0370*/ IADD3 R2, -R7, 0x1, R6 ; /* 0x0000000107027810 */
/* 0x000fe20007ffe106 */
/*0380*/ IMAD.IADD R3, R6, 0x1, -R7 ; /* 0x0000000106037824 */
/* 0x000fe200078e0a07 */
/*0390*/ BSSY B1, 0x4e0 ; /* 0x0000014000017945 */
/* 0x000fe20003800000 */
/*03a0*/ IMAD.MOV.U32 R8, RZ, RZ, RZ ; /* 0x000000ffff087224 */
/* 0x000fe200078e00ff */
/*03b0*/ LOP3.LUT P1, R9, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302097812 */
/* 0x000fe4000782c0ff */
/*03c0*/ ISETP.GE.U32.AND P0, PT, R3, 0x3, PT ; /* 0x000000030300780c */
/* 0x000fe40003f06070 */
/*03d0*/ MOV R10, R7 ; /* 0x00000007000a7202 */
/* 0x000fd20000000f00 */
/*03e0*/ @!P1 BRA 0x4d0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*03f0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0400*/ HFMA2.MMA R8, -RZ, RZ, 0, 0 ; /* 0x00000000ff087435 */
/* 0x000fe200000001ff */
/*0410*/ IMAD.MOV.U32 R10, RZ, RZ, R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0007 */
/*0420*/ IMAD.WIDE R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fc800078e0202 */
/*0430*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fc800078e0003 */
/*0440*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fcc00078e000b */
/*0450*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x0000a2000c1e1900 */
/*0460*/ IADD3 R9, R9, -0x1, RZ ; /* 0xffffffff09097810 */
/* 0x000fe40007ffe0ff */
/*0470*/ IADD3 R10, R10, 0x1, RZ ; /* 0x000000010a0a7810 */
/* 0x000fe40007ffe0ff */
/*0480*/ ISETP.NE.AND P1, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f25270 */
/*0490*/ IADD3 R2, P2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x001fca0007f5e0ff */
/*04a0*/ IMAD.X R11, RZ, RZ, R11, P2 ; /* 0x000000ffff0b7224 */
/* 0x000fe400010e060b */
/*04b0*/ FADD R8, R3, R8 ; /* 0x0000000803087221 */
/* 0x004fc80000000000 */
/*04c0*/ @P1 BRA 0x440 ; /* 0xffffff7000001947 */
/* 0x000fea000383ffff */
/*04d0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*04e0*/ @!P0 BRA 0xa60 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*04f0*/ IADD3 R7, R10.reuse, -0x1, RZ ; /* 0xffffffff0a077810 */
/* 0x040fe20007ffe0ff */
/*0500*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fe200078e00ff */
/*0510*/ BSSY B1, 0x810 ; /* 0x000002f000017945 */
/* 0x000fe40003800000 */
/*0520*/ IADD3 R9, -R7, R6, RZ ; /* 0x0000000607097210 */
/* 0x000fe20007ffe1ff */
/*0530*/ IMAD.WIDE R2, R10, R3, c[0x0][0x160] ; /* 0x000058000a027625 */
/* 0x000fc600078e0203 */
/*0540*/ ISETP.GT.AND P1, PT, R9, 0xc, PT ; /* 0x0000000c0900780c */
/* 0x000fe40003f24270 */
/*0550*/ IADD3 R2, P0, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fca0007f1e0ff */
/*0560*/ IMAD.X R3, RZ, RZ, R3, P0 ; /* 0x000000ffff037224 */
/* 0x000fe200000e0603 */
/*0570*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fca0003f0f070 */
/*0580*/ @!P1 BRA 0x800 ; /* 0x0000027000009947 */
/* 0x000fea0003800000 */
/*0590*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*05a0*/ IADD3 R12, R6, -0xc, RZ ; /* 0xfffffff4060c7810 */
/* 0x000fe40007ffe0ff */
/*05b0*/ LDG.E R21, [R2.64+-0x8] ; /* 0xfffff80402157981 */
/* 0x0000a8000c1e1900 */
/*05c0*/ LDG.E R22, [R2.64+-0x4] ; /* 0xfffffc0402167981 */
/* 0x0000e8000c1e1900 */
/*05d0*/ LDG.E R24, [R2.64] ; /* 0x0000000402187981 */
/* 0x000128000c1e1900 */
/*05e0*/ LDG.E R26, [R2.64+0x4] ; /* 0x00000404021a7981 */
/* 0x000168000c1e1900 */
/*05f0*/ LDG.E R28, [R2.64+0x8] ; /* 0x00000804021c7981 */
/* 0x000168000c1e1900 */
/*0600*/ LDG.E R20, [R2.64+0xc] ; /* 0x00000c0402147981 */
/* 0x000168000c1e1900 */
/*0610*/ LDG.E R19, [R2.64+0x10] ; /* 0x0000100402137981 */
/* 0x000168000c1e1900 */
/*0620*/ LDG.E R18, [R2.64+0x14] ; /* 0x0000140402127981 */
/* 0x000168000c1e1900 */
/*0630*/ LDG.E R17, [R2.64+0x18] ; /* 0x0000180402117981 */
/* 0x000168000c1e1900 */
/*0640*/ LDG.E R16, [R2.64+0x1c] ; /* 0x00001c0402107981 */
/* 0x000168000c1e1900 */
/*0650*/ LDG.E R15, [R2.64+0x20] ; /* 0x00002004020f7981 */
/* 0x000168000c1e1900 */
/*0660*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000168000c1e1900 */
/*0670*/ LDG.E R13, [R2.64+0x28] ; /* 0x00002804020d7981 */
/* 0x000168000c1e1900 */
/*0680*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */
/* 0x000168000c1e1900 */
/*0690*/ LDG.E R11, [R2.64+0x30] ; /* 0x00003004020b7981 */
/* 0x000168000c1e1900 */
/*06a0*/ LDG.E R9, [R2.64+0x34] ; /* 0x0000340402097981 */
/* 0x000162000c1e1900 */
/*06b0*/ IADD3 R7, R7, 0x10, RZ ; /* 0x0000001007077810 */
/* 0x000fc80007ffe0ff */
/*06c0*/ ISETP.GE.AND P1, PT, R7, R12, PT ; /* 0x0000000c0700720c */
/* 0x000fe40003f26270 */
/*06d0*/ IADD3 R2, P2, R2, 0x40, RZ ; /* 0x0000004002027810 */
/* 0x001fca0007f5e0ff */
/*06e0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fe400010e0603 */
/*06f0*/ FADD R21, R21, R8 ; /* 0x0000000815157221 */
/* 0x004fc80000000000 */
/*0700*/ FADD R21, R21, R22 ; /* 0x0000001615157221 */
/* 0x008fc80000000000 */
/*0710*/ FADD R21, R21, R24 ; /* 0x0000001815157221 */
/* 0x010fc80000000000 */
/*0720*/ FADD R21, R21, R26 ; /* 0x0000001a15157221 */
/* 0x020fc80000000000 */
/*0730*/ FADD R21, R21, R28 ; /* 0x0000001c15157221 */
/* 0x000fc80000000000 */
/*0740*/ FADD R20, R21, R20 ; /* 0x0000001415147221 */
/* 0x000fc80000000000 */
/*0750*/ FADD R19, R20, R19 ; /* 0x0000001314137221 */
/* 0x000fc80000000000 */
/*0760*/ FADD R18, R19, R18 ; /* 0x0000001213127221 */
/* 0x000fc80000000000 */
/*0770*/ FADD R17, R18, R17 ; /* 0x0000001112117221 */
/* 0x000fc80000000000 */
/*0780*/ FADD R16, R17, R16 ; /* 0x0000001011107221 */
/* 0x000fc80000000000 */
/*0790*/ FADD R15, R16, R15 ; /* 0x0000000f100f7221 */
/* 0x000fc80000000000 */
/*07a0*/ FADD R14, R15, R14 ; /* 0x0000000e0f0e7221 */
/* 0x000fc80000000000 */
/*07b0*/ FADD R13, R14, R13 ; /* 0x0000000d0e0d7221 */
/* 0x000fc80000000000 */
/*07c0*/ FADD R10, R13, R10 ; /* 0x0000000a0d0a7221 */
/* 0x000fc80000000000 */
/*07d0*/ FADD R10, R10, R11 ; /* 0x0000000b0a0a7221 */
/* 0x000fc80000000000 */
/*07e0*/ FADD R8, R10, R9 ; /* 0x000000090a087221 */
/* 0x000fe20000000000 */
/*07f0*/ @!P1 BRA 0x5b0 ; /* 0xfffffdb000009947 */
/* 0x000fea000383ffff */
/*0800*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0810*/ IMAD.IADD R9, R6, 0x1, -R7 ; /* 0x0000000106097824 */
/* 0x000fe200078e0a07 */
/*0820*/ BSSY B1, 0x9c0 ; /* 0x0000019000017945 */
/* 0x000fe80003800000 */
/*0830*/ ISETP.GT.AND P1, PT, R9, 0x4, PT ; /* 0x000000040900780c */
/* 0x000fda0003f24270 */
/*0840*/ @!P1 BRA 0x9b0 ; /* 0x0000016000009947 */
/* 0x000fea0003800000 */
/*0850*/ LDG.E R9, [R2.64+-0x8] ; /* 0xfffff80402097981 */
/* 0x000ea8000c1e1900 */
/*0860*/ LDG.E R10, [R2.64+-0x4] ; /* 0xfffffc04020a7981 */
/* 0x000ee8000c1e1900 */
/*0870*/ LDG.E R12, [R2.64] ; /* 0x00000004020c7981 */
/* 0x000f28000c1e1900 */
/*0880*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000168000c1e1900 */
/*0890*/ LDG.E R16, [R2.64+0x8] ; /* 0x0000080402107981 */
/* 0x000168000c1e1900 */
/*08a0*/ LDG.E R18, [R2.64+0xc] ; /* 0x00000c0402127981 */
/* 0x000168000c1e1900 */
/*08b0*/ LDG.E R20, [R2.64+0x10] ; /* 0x0000100402147981 */
/* 0x000168000c1e1900 */
/*08c0*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140402167981 */
/* 0x000162000c1e1900 */
/*08d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fc40003f0e170 */
/*08e0*/ IADD3 R7, R7, 0x8, RZ ; /* 0x0000000807077810 */
/* 0x000fe20007ffe0ff */
/*08f0*/ FADD R9, R8, R9 ; /* 0x0000000908097221 */
/* 0x004fc80000000000 */
/*0900*/ FADD R9, R9, R10 ; /* 0x0000000a09097221 */
/* 0x008fe20000000000 */
/*0910*/ IADD3 R10, P1, R2, 0x20, RZ ; /* 0x00000020020a7810 */
/* 0x000fc60007f3e0ff */
/*0920*/ FADD R9, R9, R12 ; /* 0x0000000c09097221 */
/* 0x010fe20000000000 */
/*0930*/ IADD3.X R11, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff0b7210 */
/* 0x000fe20000ffe4ff */
/*0940*/ IMAD.MOV.U32 R2, RZ, RZ, R10 ; /* 0x000000ffff027224 */
/* 0x001fe400078e000a */
/*0950*/ FADD R9, R9, R14 ; /* 0x0000000e09097221 */
/* 0x020fe40000000000 */
/*0960*/ IMAD.MOV.U32 R3, RZ, RZ, R11 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000b */
/*0970*/ FADD R9, R9, R16 ; /* 0x0000001009097221 */
/* 0x000fc80000000000 */
/*0980*/ FADD R9, R9, R18 ; /* 0x0000001209097221 */
/* 0x000fc80000000000 */
/*0990*/ FADD R9, R9, R20 ; /* 0x0000001409097221 */
/* 0x000fc80000000000 */
/*09a0*/ FADD R8, R9, R22 ; /* 0x0000001609087221 */
/* 0x000fe40000000000 */
/*09b0*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*09c0*/ ISETP.LT.OR P0, PT, R7, R6, P0 ; /* 0x000000060700720c */
/* 0x000fda0000701670 */
/*09d0*/ @!P0 BRA 0xa60 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*09e0*/ LDG.E R7, [R2.64+-0x8] ; /* 0xfffff80402077981 */
/* 0x000ea8000c1e1900 */
/*09f0*/ LDG.E R6, [R2.64+-0x4] ; /* 0xfffffc0402067981 */
/* 0x000ee8000c1e1900 */
/*0a00*/ LDG.E R9, [R2.64] ; /* 0x0000000402097981 */
/* 0x000f28000c1e1900 */
/*0a10*/ LDG.E R11, [R2.64+0x4] ; /* 0x00000404020b7981 */
/* 0x000f62000c1e1900 */
/*0a20*/ FADD R7, R8, R7 ; /* 0x0000000708077221 */
/* 0x004fc80000000000 */
/*0a30*/ FADD R6, R7, R6 ; /* 0x0000000607067221 */
/* 0x008fc80000000000 */
/*0a40*/ FADD R6, R6, R9 ; /* 0x0000000906067221 */
/* 0x010fc80000000000 */
/*0a50*/ FADD R8, R6, R11 ; /* 0x0000000b06087221 */
/* 0x020fe40000000000 */
/*0a60*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0a70*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff027624 */
/* 0x000fe200078e00ff */
/*0a80*/ STS [R5.X4], R8 ; /* 0x0000000805007388 */
/* 0x0001e80000004800 */
/*0a90*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0aa0*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f06270 */
/*0ab0*/ @!P0 BRA 0xb80 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*0ac0*/ SHF.L.U32 R2, R5, 0x2, RZ ; /* 0x0000000205027819 */
/* 0x001fe400000006ff */
/*0ad0*/ SHF.R.S32.HI R7, RZ, 0x1, R4 ; /* 0x00000001ff077819 */
/* 0x000fc80000011404 */
/*0ae0*/ ISETP.GE.AND P0, PT, R5, R7, PT ; /* 0x000000070500720c */
/* 0x000fda0003f06270 */
/*0af0*/ @!P0 IMAD R3, R7, 0x4, R2 ; /* 0x0000000407038824 */
/* 0x000fe200078e0202 */
/*0b00*/ @!P0 LDS R6, [R5.X4] ; /* 0x0000000005068984 */
/* 0x000fea0000004800 */
/*0b10*/ @!P0 LDS R3, [R3] ; /* 0x0000000003038984 */
/* 0x000e240000000800 */
/*0b20*/ @!P0 FADD R6, R6, R3 ; /* 0x0000000306068221 */
/* 0x001fca0000000000 */
/*0b30*/ @!P0 STS [R5.X4], R6 ; /* 0x0000000605008388 */
/* 0x0001e80000004800 */
/*0b40*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0b50*/ ISETP.GT.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f04270 */
/*0b60*/ IMAD.MOV.U32 R4, RZ, RZ, R7 ; /* 0x000000ffff047224 */
/* 0x000fd800078e0007 */
/*0b70*/ @P0 BRA 0xad0 ; /* 0xffffff5000000947 */
/* 0x001fea000383ffff */
/*0b80*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x001e220000000800 */
/*0b90*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0ba0*/ IMAD.WIDE R2, R0, R3, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fca00078e0203 */
/*0bb0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0bc0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bd0*/ SHF.R.U32.HI R12, RZ, 0x17, R6.reuse ; /* 0x00000017ff0c7819 */
/* 0x100fe20000011606 */
/*0be0*/ BSSY B1, 0x1230 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*0bf0*/ SHF.R.U32.HI R9, RZ, 0x17, R13 ; /* 0x00000017ff097819 */
/* 0x000fe2000001160d */
/*0c00*/ IMAD.MOV.U32 R14, RZ, RZ, R6 ; /* 0x000000ffff0e7224 */
/* 0x000fe200078e0006 */
/*0c10*/ LOP3.LUT R12, R12, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0c0c7812 */
/* 0x000fe400078ec0ff */
/*0c20*/ LOP3.LUT R17, R9, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff09117812 */
/* 0x000fe400078ec0ff */
/*0c30*/ IADD3 R16, R12, -0x1, RZ ; /* 0xffffffff0c107810 */
/* 0x000fe40007ffe0ff */
/*0c40*/ IADD3 R15, R17, -0x1, RZ ; /* 0xffffffff110f7810 */
/* 0x000fc40007ffe0ff */
/*0c50*/ ISETP.GT.U32.AND P0, PT, R16, 0xfd, PT ; /* 0x000000fd1000780c */
/* 0x000fe40003f04070 */
/*0c60*/ MOV R9, R13 ; /* 0x0000000d00097202 */
/* 0x000fe40000000f00 */
/*0c70*/ ISETP.GT.U32.OR P0, PT, R15, 0xfd, P0 ; /* 0x000000fd0f00780c */
/* 0x000fda0000704470 */
/*0c80*/ @!P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b8224 */
/* 0x000fe200078e00ff */
/*0c90*/ @!P0 BRA 0xe10 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0ca0*/ FSETP.GTU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fe40003f1c200 */
/*0cb0*/ FSETP.GTU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fc80003f3c200 */
/*0cc0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*0cd0*/ @P0 BRA 0x1210 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*0ce0*/ LOP3.LUT P0, RZ, R14, 0x7fffffff, R9, 0xc8, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fda000780c809 */
/*0cf0*/ @!P0 BRA 0x11f0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*0d00*/ FSETP.NEU.FTZ.AND P2, PT, |R13|.reuse, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x040fe40003f5d200 */
/*0d10*/ FSETP.NEU.FTZ.AND P1, PT, |R6|, +INF , PT ; /* 0x7f8000000600780b */
/* 0x000fe40003f3d200 */
/*0d20*/ FSETP.NEU.FTZ.AND P0, PT, |R13|, +INF , PT ; /* 0x7f8000000d00780b */
/* 0x000fd60003f1d200 */
/*0d30*/ @!P1 BRA !P2, 0x11f0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0d40*/ LOP3.LUT P2, RZ, R9, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff09ff7812 */
/* 0x000fc8000784c0ff */
/*0d50*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0d60*/ @P1 BRA 0x11d0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0d70*/ LOP3.LUT P1, RZ, R14, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff0eff7812 */
/* 0x000fc8000782c0ff */
/*0d80*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0d90*/ @P0 BRA 0x11a0 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0da0*/ ISETP.GE.AND P0, PT, R15, RZ, PT ; /* 0x000000ff0f00720c */
/* 0x000fe40003f06270 */
/*0db0*/ ISETP.GE.AND P1, PT, R16, RZ, PT ; /* 0x000000ff1000720c */
/* 0x000fd60003f26270 */
/*0dc0*/ @P0 IMAD.MOV.U32 R11, RZ, RZ, RZ ; /* 0x000000ffff0b0224 */
/* 0x000fe200078e00ff */
/*0dd0*/ @!P0 MOV R11, 0xffffffc0 ; /* 0xffffffc0000b8802 */
/* 0x000fe20000000f00 */
/*0de0*/ @!P0 FFMA R9, R13, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000d098823 */
/* 0x000fe400000000ff */
/*0df0*/ @!P1 FFMA R14, R6, 1.84467440737095516160e+19, RZ ; /* 0x5f800000060e9823 */
/* 0x000fe200000000ff */
/*0e00*/ @!P1 IADD3 R11, R11, 0x40, RZ ; /* 0x000000400b0b9810 */
/* 0x000fe40007ffe0ff */
/*0e10*/ LEA R13, R12, 0xc0800000, 0x17 ; /* 0xc08000000c0d7811 */
/* 0x000fe200078eb8ff */
/*0e20*/ BSSY B2, 0x1190 ; /* 0x0000036000027945 */
/* 0x000fe80003800000 */
/*0e30*/ IMAD.IADD R14, R14, 0x1, -R13 ; /* 0x000000010e0e7824 */
/* 0x000fe200078e0a0d */
/*0e40*/ IADD3 R13, R17, -0x7f, RZ ; /* 0xffffff81110d7810 */
/* 0x000fc60007ffe0ff */
/*0e50*/ MUFU.RCP R15, R14 ; /* 0x0000000e000f7308 */
/* 0x0000620000001000 */
/*0e60*/ FADD.FTZ R16, -R14, -RZ ; /* 0x800000ff0e107221 */
/* 0x000fe40000010100 */
/*0e70*/ IMAD R9, R13.reuse, -0x800000, R9 ; /* 0xff8000000d097824 */
/* 0x040fe200078e0209 */
/*0e80*/ IADD3 R14, R13, 0x7f, -R12 ; /* 0x0000007f0d0e7810 */
/* 0x001fca0007ffe80c */
/*0e90*/ IMAD.IADD R14, R14, 0x1, R11 ; /* 0x000000010e0e7824 */
/* 0x000fe400078e020b */
/*0ea0*/ FFMA R18, R15, R16, 1 ; /* 0x3f8000000f127423 */
/* 0x002fc80000000010 */
/*0eb0*/ FFMA R20, R15, R18, R15 ; /* 0x000000120f147223 */
/* 0x000fc8000000000f */
/*0ec0*/ FFMA R15, R9, R20, RZ ; /* 0x00000014090f7223 */
/* 0x000fc800000000ff */
/*0ed0*/ FFMA R18, R16, R15, R9 ; /* 0x0000000f10127223 */
/* 0x000fc80000000009 */
/*0ee0*/ FFMA R15, R20, R18, R15 ; /* 0x00000012140f7223 */
/* 0x000fc8000000000f */
/*0ef0*/ FFMA R16, R16, R15, R9 ; /* 0x0000000f10107223 */
/* 0x000fc80000000009 */
/*0f00*/ FFMA R9, R20, R16, R15 ; /* 0x0000001014097223 */
/* 0x000fca000000000f */
/*0f10*/ SHF.R.U32.HI R12, RZ, 0x17, R9 ; /* 0x00000017ff0c7819 */
/* 0x000fc80000011609 */
/*0f20*/ LOP3.LUT R12, R12, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff0c0c7812 */
/* 0x000fc800078ec0ff */
/*0f30*/ IADD3 R17, R12, R14, RZ ; /* 0x0000000e0c117210 */
/* 0x000fc80007ffe0ff */
/*0f40*/ IADD3 R11, R17, -0x1, RZ ; /* 0xffffffff110b7810 */
/* 0x000fc80007ffe0ff */
/*0f50*/ ISETP.GE.U32.AND P0, PT, R11, 0xfe, PT ; /* 0x000000fe0b00780c */
/* 0x000fda0003f06070 */
/*0f60*/ @!P0 BRA 0x1170 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0f70*/ ISETP.GT.AND P0, PT, R17, 0xfe, PT ; /* 0x000000fe1100780c */
/* 0x000fda0003f04270 */
/*0f80*/ @P0 BRA 0x1140 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0f90*/ ISETP.GE.AND P0, PT, R17, 0x1, PT ; /* 0x000000011100780c */
/* 0x000fda0003f06270 */
/*0fa0*/ @P0 BRA 0x1180 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*0fb0*/ ISETP.GE.AND P0, PT, R17, -0x18, PT ; /* 0xffffffe81100780c */
/* 0x000fe40003f06270 */
/*0fc0*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fd600078ec0ff */
/*0fd0*/ @!P0 BRA 0x1180 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*0fe0*/ FFMA.RZ R11, R20.reuse, R16.reuse, R15.reuse ; /* 0x00000010140b7223 */
/* 0x1c0fe2000000c00f */
/*0ff0*/ IADD3 R14, R17.reuse, 0x20, RZ ; /* 0x00000020110e7810 */
/* 0x040fe20007ffe0ff */
/*1000*/ FFMA.RM R12, R20.reuse, R16.reuse, R15.reuse ; /* 0x00000010140c7223 */
/* 0x1c0fe2000000400f */
/*1010*/ ISETP.NE.AND P2, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe40003f45270 */
/*1020*/ LOP3.LUT R13, R11, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0b0d7812 */
/* 0x000fe200078ec0ff */
/*1030*/ FFMA.RP R11, R20, R16, R15 ; /* 0x00000010140b7223 */
/* 0x000fe2000000800f */
/*1040*/ ISETP.NE.AND P1, PT, R17, RZ, PT ; /* 0x000000ff1100720c */
/* 0x000fe20003f25270 */
/*1050*/ IMAD.MOV R15, RZ, RZ, -R17 ; /* 0x000000ffff0f7224 */
/* 0x000fe200078e0a11 */
/*1060*/ LOP3.LUT R13, R13, 0x800000, RZ, 0xfc, !PT ; /* 0x008000000d0d7812 */
/* 0x000fe400078efcff */
/*1070*/ FSETP.NEU.FTZ.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720b */
/* 0x000fc40003f1d000 */
/*1080*/ SHF.L.U32 R14, R13, R14, RZ ; /* 0x0000000e0d0e7219 */
/* 0x000fe400000006ff */
/*1090*/ SEL R12, R15, RZ, P2 ; /* 0x000000ff0f0c7207 */
/* 0x000fe40001000000 */
/*10a0*/ ISETP.NE.AND P1, PT, R14, RZ, P1 ; /* 0x000000ff0e00720c */
/* 0x000fe40000f25270 */
/*10b0*/ SHF.R.U32.HI R12, RZ, R12, R13 ; /* 0x0000000cff0c7219 */
/* 0x000fe4000001160d */
/*10c0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*10d0*/ SHF.R.U32.HI R14, RZ, 0x1, R12 ; /* 0x00000001ff0e7819 */
/* 0x000fc4000001160c */
/*10e0*/ SEL R11, RZ, 0x1, !P0 ; /* 0x00000001ff0b7807 */
/* 0x000fc80004000000 */
/*10f0*/ LOP3.LUT R11, R11, 0x1, R14, 0xf8, !PT ; /* 0x000000010b0b7812 */
/* 0x000fc800078ef80e */
/*1100*/ LOP3.LUT R11, R11, R12, RZ, 0xc0, !PT ; /* 0x0000000c0b0b7212 */
/* 0x000fca00078ec0ff */
/*1110*/ IMAD.IADD R14, R14, 0x1, R11 ; /* 0x000000010e0e7824 */
/* 0x000fca00078e020b */
/*1120*/ LOP3.LUT R9, R14, R9, RZ, 0xfc, !PT ; /* 0x000000090e097212 */
/* 0x000fe200078efcff */
/*1130*/ BRA 0x1180 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*1140*/ LOP3.LUT R9, R9, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000009097812 */
/* 0x000fc800078ec0ff */
/*1150*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*1160*/ BRA 0x1180 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1170*/ LEA R9, R14, R9, 0x17 ; /* 0x000000090e097211 */
/* 0x000fe400078eb8ff */
/*1180*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*1190*/ BRA 0x1220 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*11a0*/ LOP3.LUT R9, R14, 0x80000000, R9, 0x48, !PT ; /* 0x800000000e097812 */
/* 0x000fc800078e4809 */
/*11b0*/ LOP3.LUT R9, R9, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000009097812 */
/* 0x000fe200078efcff */
/*11c0*/ BRA 0x1220 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*11d0*/ LOP3.LUT R9, R14, 0x80000000, R9, 0x48, !PT ; /* 0x800000000e097812 */
/* 0x000fe200078e4809 */
/*11e0*/ BRA 0x1220 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*11f0*/ MUFU.RSQ R9, -QNAN ; /* 0xffc0000000097908 */
/* 0x000e220000001400 */
/*1200*/ BRA 0x1220 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*1210*/ FADD.FTZ R9, R13, R6 ; /* 0x000000060d097221 */
/* 0x000fe40000010000 */
/*1220*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*1230*/ IMAD.MOV.U32 R11, RZ, RZ, 0x0 ; /* 0x00000000ff0b7424 */
/* 0x000fc800078e00ff */
/*1240*/ RET.REL.NODEC R10 0x0 ; /* 0xffffedb00a007950 */
/* 0x000fea0003c3ffff */
/*1250*/ BRA 0x1250; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*12f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* Copyright 2017 Eric Aubanel
* This file contains code implementing Algorithm 4.14 from
* Elements of Parallel Computing, by Eric Aubanel, 2016, CRC Press.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* -------------------------------------------------------------------
* Implementation of reduction of n floats using CUDA
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
int isPowerOf2(int n);
//reduce n floats in array a to a partial sum for each block,
//stored in array c. Block size must be power of 2
__global__ void reductionGPU(float *a, float *c, int n){
//size of b indicated by kernel call in main (blockSize)
extern __shared__ float b[];
int gsize = blockDim.x; //block size
int nt = gsize * gridDim.x; //total number of threads
int gid = blockIdx.x; //block id
int tid = threadIdx.x; //local thread id
int id = gid*gsize + tid; //global thread id
//if n<nt, then some threads will have nothing to do
int istart;
int iend;
if(n<nt){
istart = id;
iend = id;
}
else{
//evaluate as float to avoid overflow
istart = (float)id*n/nt;
iend = (float)(id+1)*n/nt - 1;
}
if(n<nt && id>=n){
b[tid] = 0;
}else{
float psum = 0.0;
for(int i=istart; i<=iend; i++)
psum += a[i];
b[tid] = psum;
}
__syncthreads();
for(int j=gsize>>1; j>=1; j >>= 1){
if(tid<j)
b[tid] += b[tid+j];
__syncthreads();
}
c[gid] = b[0];
}
int main(int argc, char **argv){
float *a_h; //array to be reduced on host (CPU)
float *c_h; //array of partial sums on host
float *a_d; //array to be reduced on device (GPU)
float *c_d; //array of partial sums on device
cudaError_t error1, error2;
struct timespec tstart, tend;
float time;
if(argc < 4){
fprintf(stderr,"usage: %s n blockSize numBlocks\n", argv[0]);
return 1;
}
int n = strtol(argv[1], NULL, 10);
int blockSize = strtol(argv[2], NULL, 10); //size of thread block on device
int numBlocks = strtol(argv[3], NULL, 10); //number of blocks on device
if(!isPowerOf2(blockSize)){
fprintf(stderr,"blockSize must be power of 2\n");
return 1;
}
//memory allocation on host and device
a_h = (float *)malloc(n*sizeof(float));
c_h = (float *)malloc(numBlocks*sizeof(float));
if(a_h == NULL || c_h == NULL){
fprintf(stderr,"couldn't allocate memory on host\n");
return 1;
}
error1 = cudaMalloc((void **)&a_d, n*sizeof(float));
error2 = cudaMalloc((void **)&c_d, numBlocks*sizeof(float));
if(error1 != cudaSuccess || error2 != cudaSuccess){
fprintf(stderr,"couldn't allocate memory on device\n");
return 1;
}
for(int i=0; i<n; i++)
a_h[i] = rand()%100;
//sequential reduction for verification and timing
clock_gettime(CLOCK_MONOTONIC, &tstart);
float sum = 0.0;
for(int i=0; i<n; i++)
sum += a_h[i];
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("CPU reduction time in s: %f\n", time);
//timing won't include transfer of array to device
cudaMemcpy(a_d, a_h, n*sizeof(float), cudaMemcpyHostToDevice);
clock_gettime(CLOCK_MONOTONIC, &tstart);
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error1 = cudaThreadSynchronize();// wait until GPU kernel finished
if(error1 != cudaSuccess){
fprintf(stderr,"error executing kernel: %s\n", cudaGetErrorString(error1));
return 1;
}
//Do not copy back to host and do CPU reduction. Do it on the GPU recersively.
while(1){
cudaMemset(a_d, 0, n);
n = numBlocks;
numBlocks = n/blockSize + ((n%blockSize==0)?0:1);
cudaMemcpy(a_d, c_d, n*sizeof(float), cudaMemcpyDeviceToDevice);
cudaMemset(c_d, 0, n*sizeof(float));
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error2 = cudaThreadSynchronize();// wait until GPU kernel finished
if(error2 != cudaSuccess){
fprintf(stderr,"error executing kernel: %s\n", cudaGetErrorString(error2));
return 1;
}
cudaMemcpy(c_h, c_d, numBlocks*sizeof(float), cudaMemcpyDeviceToHost);
if(numBlocks==1)break;
}
cudaMemcpy(c_h, c_d, numBlocks*sizeof(float), cudaMemcpyDeviceToHost);
float dsum = c_h[0];
printf("dsum: %f\n", dsum);
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("GPUS time in s: %f\n", time);
//not necessarily the same because of differences in roundoff error
printf("relative difference between sequential and parallel sums: %g\n",
fabs(dsum-sum)/sum);
return 0;
}
int isPowerOf2(int n){
while(n){
if(n & 1)
break;
n >>= 1;
}
return (1 == n? 1:0);
} | .file "tmpxft_000f2bf2_00000000-6_reductionCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10isPowerOf2i
.type _Z10isPowerOf2i, @function
_Z10isPowerOf2i:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
je .L4
testb $1, %dil
jne .L4
.L5:
sarl %edi
je .L4
testb $1, %dil
je .L5
.L4:
cmpl $1, %edi
sete %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z10isPowerOf2i, .-_Z10isPowerOf2i
.globl _Z35__device_stub__Z12reductionGPUPfS_iPfS_i
.type _Z35__device_stub__Z12reductionGPUPfS_iPfS_i, @function
_Z35__device_stub__Z12reductionGPUPfS_iPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12reductionGPUPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z12reductionGPUPfS_iPfS_i, .-_Z35__device_stub__Z12reductionGPUPfS_iPfS_i
.globl _Z12reductionGPUPfS_i
.type _Z12reductionGPUPfS_i, @function
_Z12reductionGPUPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12reductionGPUPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12reductionGPUPfS_i, .-_Z12reductionGPUPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "usage: %s n blockSize numBlocks\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "blockSize must be power of 2\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "couldn't allocate memory on host\n"
.align 8
.LC4:
.string "couldn't allocate memory on device\n"
.section .rodata.str1.1
.LC6:
.string "CPU reduction time in s: %f\n"
.LC7:
.string "error executing kernel: %s\n"
.LC8:
.string "dsum: %f\n"
.LC9:
.string "GPUS time in s: %f\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "relative difference between sequential and parallel sums: %g\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L39
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 40(%rsp)
movl %eax, %r14d
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movl %r14d, %edi
call _Z10isPowerOf2i
testl %eax, %eax
je .L40
movl %r13d, %ebp
movq 16(%rsp), %r12
movl %r12d, %ebx
movslq %r13d, %rax
salq $2, %rax
movq %rax, 24(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 32(%rsp)
movslq %r12d, %rax
leaq 0(,%rax,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testq %r15, %r15
je .L32
testq %rax, %rax
je .L32
leaq 56(%rsp), %rdi
movq 24(%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %r15d
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
orl %r15d, %eax
jne .L21
testl %r13d, %r13d
jle .L41
movq 32(%rsp), %rcx
movq %rcx, %r12
leal -1(%r13), %eax
movq %rcx, %r13
leaq 4(%rcx,%rax,4), %r15
.L24:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13)
addq $4, %r13
cmpq %r15, %r13
jne .L24
leaq 96(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $0x00000000, 4(%rsp)
.L25:
movss 4(%rsp), %xmm2
addss (%r12), %xmm2
movss %xmm2, 4(%rsp)
addq $4, %r12
cmpq %r15, %r12
jne .L25
.L30:
leaq 112(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC5(%rip), %xmm0
movq 112(%rsp), %rax
subq 96(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %ecx
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movq 40(%rsp), %rcx
movslq %ecx, %rax
leaq 0(,%rax,4), %r15
movl %ecx, %r13d
movl %ecx, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl 16(%rsp), %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movq %r15, %r8
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L26:
call cudaThreadSynchronize@PLT
testl %eax, %eax
je .L27
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L39:
movq (%rsi), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
.L15:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L32:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L21:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L42:
movl %ebp, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z12reductionGPUPfS_iPfS_i
jmp .L26
.L28:
call cudaThreadSynchronize@PLT
testl %eax, %eax
jne .L44
movslq %ebx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 64(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, %ebx
je .L45
.L27:
movslq %ebp, %rdx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
movl %ebx, %eax
cltd
idivl %r14d
movl %ebx, %ebp
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, %ebx
movslq %ebp, %r12
salq $2, %r12
movl $3, %ecx
movq %r12, %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq %r12, %rdx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaMemset@PLT
movl %r13d, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl %ebx, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movq %r15, %r8
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L28
movl %ebp, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z12reductionGPUPfS_iPfS_i
jmp .L28
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L45:
movl $2, %ecx
movl $4, %edx
movq 64(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movss (%rbx), %xmm0
movss %xmm0, 8(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC5(%rip), %xmm0
movq 112(%rsp), %rax
subq 96(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 8(%rsp), %xmm0
movss 4(%rsp), %xmm3
subss %xmm3, %xmm0
andps .LC10(%rip), %xmm0
divss %xmm3, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L15
.L41:
leaq 96(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $0x00000000, 4(%rsp)
jmp .L30
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12reductionGPUPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12reductionGPUPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long -400107883
.long 1041313291
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC10:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* Copyright 2017 Eric Aubanel
* This file contains code implementing Algorithm 4.14 from
* Elements of Parallel Computing, by Eric Aubanel, 2016, CRC Press.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* -------------------------------------------------------------------
* Implementation of reduction of n floats using CUDA
*/
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
int isPowerOf2(int n);
//reduce n floats in array a to a partial sum for each block,
//stored in array c. Block size must be power of 2
__global__ void reductionGPU(float *a, float *c, int n){
//size of b indicated by kernel call in main (blockSize)
extern __shared__ float b[];
int gsize = blockDim.x; //block size
int nt = gsize * gridDim.x; //total number of threads
int gid = blockIdx.x; //block id
int tid = threadIdx.x; //local thread id
int id = gid*gsize + tid; //global thread id
//if n<nt, then some threads will have nothing to do
int istart;
int iend;
if(n<nt){
istart = id;
iend = id;
}
else{
//evaluate as float to avoid overflow
istart = (float)id*n/nt;
iend = (float)(id+1)*n/nt - 1;
}
if(n<nt && id>=n){
b[tid] = 0;
}else{
float psum = 0.0;
for(int i=istart; i<=iend; i++)
psum += a[i];
b[tid] = psum;
}
__syncthreads();
for(int j=gsize>>1; j>=1; j >>= 1){
if(tid<j)
b[tid] += b[tid+j];
__syncthreads();
}
c[gid] = b[0];
}
int main(int argc, char **argv){
float *a_h; //array to be reduced on host (CPU)
float *c_h; //array of partial sums on host
float *a_d; //array to be reduced on device (GPU)
float *c_d; //array of partial sums on device
cudaError_t error1, error2;
struct timespec tstart, tend;
float time;
if(argc < 4){
fprintf(stderr,"usage: %s n blockSize numBlocks\n", argv[0]);
return 1;
}
int n = strtol(argv[1], NULL, 10);
int blockSize = strtol(argv[2], NULL, 10); //size of thread block on device
int numBlocks = strtol(argv[3], NULL, 10); //number of blocks on device
if(!isPowerOf2(blockSize)){
fprintf(stderr,"blockSize must be power of 2\n");
return 1;
}
//memory allocation on host and device
a_h = (float *)malloc(n*sizeof(float));
c_h = (float *)malloc(numBlocks*sizeof(float));
if(a_h == NULL || c_h == NULL){
fprintf(stderr,"couldn't allocate memory on host\n");
return 1;
}
error1 = cudaMalloc((void **)&a_d, n*sizeof(float));
error2 = cudaMalloc((void **)&c_d, numBlocks*sizeof(float));
if(error1 != cudaSuccess || error2 != cudaSuccess){
fprintf(stderr,"couldn't allocate memory on device\n");
return 1;
}
for(int i=0; i<n; i++)
a_h[i] = rand()%100;
//sequential reduction for verification and timing
clock_gettime(CLOCK_MONOTONIC, &tstart);
float sum = 0.0;
for(int i=0; i<n; i++)
sum += a_h[i];
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("CPU reduction time in s: %f\n", time);
//timing won't include transfer of array to device
cudaMemcpy(a_d, a_h, n*sizeof(float), cudaMemcpyHostToDevice);
clock_gettime(CLOCK_MONOTONIC, &tstart);
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error1 = cudaThreadSynchronize();// wait until GPU kernel finished
if(error1 != cudaSuccess){
fprintf(stderr,"error executing kernel: %s\n", cudaGetErrorString(error1));
return 1;
}
//Do not copy back to host and do CPU reduction. Do it on the GPU recersively.
while(1){
cudaMemset(a_d, 0, n);
n = numBlocks;
numBlocks = n/blockSize + ((n%blockSize==0)?0:1);
cudaMemcpy(a_d, c_d, n*sizeof(float), cudaMemcpyDeviceToDevice);
cudaMemset(c_d, 0, n*sizeof(float));
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error2 = cudaThreadSynchronize();// wait until GPU kernel finished
if(error2 != cudaSuccess){
fprintf(stderr,"error executing kernel: %s\n", cudaGetErrorString(error2));
return 1;
}
cudaMemcpy(c_h, c_d, numBlocks*sizeof(float), cudaMemcpyDeviceToHost);
if(numBlocks==1)break;
}
cudaMemcpy(c_h, c_d, numBlocks*sizeof(float), cudaMemcpyDeviceToHost);
float dsum = c_h[0];
printf("dsum: %f\n", dsum);
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("GPUS time in s: %f\n", time);
//not necessarily the same because of differences in roundoff error
printf("relative difference between sequential and parallel sums: %g\n",
fabs(dsum-sum)/sum);
return 0;
}
int isPowerOf2(int n){
while(n){
if(n & 1)
break;
n >>= 1;
}
return (1 == n? 1:0);
} | /* Copyright 2017 Eric Aubanel
* This file contains code implementing Algorithm 4.14 from
* Elements of Parallel Computing, by Eric Aubanel, 2016, CRC Press.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* -------------------------------------------------------------------
* Implementation of reduction of n floats using CUDA
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
int isPowerOf2(int n);
//reduce n floats in array a to a partial sum for each block,
//stored in array c. Block size must be power of 2
__global__ void reductionGPU(float *a, float *c, int n){
//size of b indicated by kernel call in main (blockSize)
extern __shared__ float b[];
int gsize = blockDim.x; //block size
int nt = gsize * gridDim.x; //total number of threads
int gid = blockIdx.x; //block id
int tid = threadIdx.x; //local thread id
int id = gid*gsize + tid; //global thread id
//if n<nt, then some threads will have nothing to do
int istart;
int iend;
if(n<nt){
istart = id;
iend = id;
}
else{
//evaluate as float to avoid overflow
istart = (float)id*n/nt;
iend = (float)(id+1)*n/nt - 1;
}
if(n<nt && id>=n){
b[tid] = 0;
}else{
float psum = 0.0;
for(int i=istart; i<=iend; i++)
psum += a[i];
b[tid] = psum;
}
__syncthreads();
for(int j=gsize>>1; j>=1; j >>= 1){
if(tid<j)
b[tid] += b[tid+j];
__syncthreads();
}
c[gid] = b[0];
}
int main(int argc, char **argv){
float *a_h; //array to be reduced on host (CPU)
float *c_h; //array of partial sums on host
float *a_d; //array to be reduced on device (GPU)
float *c_d; //array of partial sums on device
hipError_t error1, error2;
struct timespec tstart, tend;
float time;
if(argc < 4){
fprintf(stderr,"usage: %s n blockSize numBlocks\n", argv[0]);
return 1;
}
int n = strtol(argv[1], NULL, 10);
int blockSize = strtol(argv[2], NULL, 10); //size of thread block on device
int numBlocks = strtol(argv[3], NULL, 10); //number of blocks on device
if(!isPowerOf2(blockSize)){
fprintf(stderr,"blockSize must be power of 2\n");
return 1;
}
//memory allocation on host and device
a_h = (float *)malloc(n*sizeof(float));
c_h = (float *)malloc(numBlocks*sizeof(float));
if(a_h == NULL || c_h == NULL){
fprintf(stderr,"couldn't allocate memory on host\n");
return 1;
}
error1 = hipMalloc((void **)&a_d, n*sizeof(float));
error2 = hipMalloc((void **)&c_d, numBlocks*sizeof(float));
if(error1 != hipSuccess || error2 != hipSuccess){
fprintf(stderr,"couldn't allocate memory on device\n");
return 1;
}
for(int i=0; i<n; i++)
a_h[i] = rand()%100;
//sequential reduction for verification and timing
clock_gettime(CLOCK_MONOTONIC, &tstart);
float sum = 0.0;
for(int i=0; i<n; i++)
sum += a_h[i];
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("CPU reduction time in s: %f\n", time);
//timing won't include transfer of array to device
hipMemcpy(a_d, a_h, n*sizeof(float), hipMemcpyHostToDevice);
clock_gettime(CLOCK_MONOTONIC, &tstart);
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error1 = hipDeviceSynchronize();// wait until GPU kernel finished
if(error1 != hipSuccess){
fprintf(stderr,"error executing kernel: %s\n", hipGetErrorString(error1));
return 1;
}
//Do not copy back to host and do CPU reduction. Do it on the GPU recersively.
while(1){
hipMemset(a_d, 0, n);
n = numBlocks;
numBlocks = n/blockSize + ((n%blockSize==0)?0:1);
hipMemcpy(a_d, c_d, n*sizeof(float), hipMemcpyDeviceToDevice);
hipMemset(c_d, 0, n*sizeof(float));
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error2 = hipDeviceSynchronize();// wait until GPU kernel finished
if(error2 != hipSuccess){
fprintf(stderr,"error executing kernel: %s\n", hipGetErrorString(error2));
return 1;
}
hipMemcpy(c_h, c_d, numBlocks*sizeof(float), hipMemcpyDeviceToHost);
if(numBlocks==1)break;
}
hipMemcpy(c_h, c_d, numBlocks*sizeof(float), hipMemcpyDeviceToHost);
float dsum = c_h[0];
printf("dsum: %f\n", dsum);
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("GPUS time in s: %f\n", time);
//not necessarily the same because of differences in roundoff error
printf("relative difference between sequential and parallel sums: %g\n",
fabs(dsum-sum)/sum);
return 0;
}
int isPowerOf2(int n){
while(n){
if(n & 1)
break;
n >>= 1;
}
return (1 == n? 1:0);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /* Copyright 2017 Eric Aubanel
* This file contains code implementing Algorithm 4.14 from
* Elements of Parallel Computing, by Eric Aubanel, 2016, CRC Press.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* -------------------------------------------------------------------
* Implementation of reduction of n floats using CUDA
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
int isPowerOf2(int n);
//reduce n floats in array a to a partial sum for each block,
//stored in array c. Block size must be power of 2
__global__ void reductionGPU(float *a, float *c, int n){
//size of b indicated by kernel call in main (blockSize)
extern __shared__ float b[];
int gsize = blockDim.x; //block size
int nt = gsize * gridDim.x; //total number of threads
int gid = blockIdx.x; //block id
int tid = threadIdx.x; //local thread id
int id = gid*gsize + tid; //global thread id
//if n<nt, then some threads will have nothing to do
int istart;
int iend;
if(n<nt){
istart = id;
iend = id;
}
else{
//evaluate as float to avoid overflow
istart = (float)id*n/nt;
iend = (float)(id+1)*n/nt - 1;
}
if(n<nt && id>=n){
b[tid] = 0;
}else{
float psum = 0.0;
for(int i=istart; i<=iend; i++)
psum += a[i];
b[tid] = psum;
}
__syncthreads();
for(int j=gsize>>1; j>=1; j >>= 1){
if(tid<j)
b[tid] += b[tid+j];
__syncthreads();
}
c[gid] = b[0];
}
int main(int argc, char **argv){
float *a_h; //array to be reduced on host (CPU)
float *c_h; //array of partial sums on host
float *a_d; //array to be reduced on device (GPU)
float *c_d; //array of partial sums on device
hipError_t error1, error2;
struct timespec tstart, tend;
float time;
if(argc < 4){
fprintf(stderr,"usage: %s n blockSize numBlocks\n", argv[0]);
return 1;
}
int n = strtol(argv[1], NULL, 10);
int blockSize = strtol(argv[2], NULL, 10); //size of thread block on device
int numBlocks = strtol(argv[3], NULL, 10); //number of blocks on device
if(!isPowerOf2(blockSize)){
fprintf(stderr,"blockSize must be power of 2\n");
return 1;
}
//memory allocation on host and device
a_h = (float *)malloc(n*sizeof(float));
c_h = (float *)malloc(numBlocks*sizeof(float));
if(a_h == NULL || c_h == NULL){
fprintf(stderr,"couldn't allocate memory on host\n");
return 1;
}
error1 = hipMalloc((void **)&a_d, n*sizeof(float));
error2 = hipMalloc((void **)&c_d, numBlocks*sizeof(float));
if(error1 != hipSuccess || error2 != hipSuccess){
fprintf(stderr,"couldn't allocate memory on device\n");
return 1;
}
for(int i=0; i<n; i++)
a_h[i] = rand()%100;
//sequential reduction for verification and timing
clock_gettime(CLOCK_MONOTONIC, &tstart);
float sum = 0.0;
for(int i=0; i<n; i++)
sum += a_h[i];
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("CPU reduction time in s: %f\n", time);
//timing won't include transfer of array to device
hipMemcpy(a_d, a_h, n*sizeof(float), hipMemcpyHostToDevice);
clock_gettime(CLOCK_MONOTONIC, &tstart);
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error1 = hipDeviceSynchronize();// wait until GPU kernel finished
if(error1 != hipSuccess){
fprintf(stderr,"error executing kernel: %s\n", hipGetErrorString(error1));
return 1;
}
//Do not copy back to host and do CPU reduction. Do it on the GPU recersively.
while(1){
hipMemset(a_d, 0, n);
n = numBlocks;
numBlocks = n/blockSize + ((n%blockSize==0)?0:1);
hipMemcpy(a_d, c_d, n*sizeof(float), hipMemcpyDeviceToDevice);
hipMemset(c_d, 0, n*sizeof(float));
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error2 = hipDeviceSynchronize();// wait until GPU kernel finished
if(error2 != hipSuccess){
fprintf(stderr,"error executing kernel: %s\n", hipGetErrorString(error2));
return 1;
}
hipMemcpy(c_h, c_d, numBlocks*sizeof(float), hipMemcpyDeviceToHost);
if(numBlocks==1)break;
}
hipMemcpy(c_h, c_d, numBlocks*sizeof(float), hipMemcpyDeviceToHost);
float dsum = c_h[0];
printf("dsum: %f\n", dsum);
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("GPUS time in s: %f\n", time);
//not necessarily the same because of differences in roundoff error
printf("relative difference between sequential and parallel sums: %g\n",
fabs(dsum-sum)/sum);
return 0;
}
int isPowerOf2(int n){
while(n){
if(n & 1)
break;
n >>= 1;
}
return (1 == n? 1:0);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12reductionGPUPfS_i
.globl _Z12reductionGPUPfS_i
.p2align 8
.type _Z12reductionGPUPfS_i,@function
_Z12reductionGPUPfS_i:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s6, s[0:1], 0x18
s_load_b32 s5, s[0:1], 0x10
s_mov_b32 s4, s15
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
s_mul_i32 s2, s6, s3
s_cmp_gt_i32 s2, s5
s_cselect_b32 s6, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s6
v_mov_b32_e32 v2, v1
v_mov_b32_e32 v4, v1
s_cbranch_vccnz .LBB0_2
v_cvt_f32_i32_e32 v3, v1
v_cvt_f32_i32_e32 v4, s5
v_add_nc_u32_e32 v2, 1, v1
v_cvt_f32_i32_e32 v5, s2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_mul_f32_e32 v3, v4, v3
v_cvt_f32_i32_e32 v2, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_scale_f32 v11, vcc_lo, v3, v5, v3
v_mul_f32_e32 v2, v4, v2
v_div_scale_f32 v4, null, v5, v5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v7, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v9, -v4, v7, 1.0
v_fmac_f32_e32 v7, v9, v7
v_div_scale_f32 v6, null, v5, v5, v2
v_div_scale_f32 v9, s2, v2, v5, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v8, v6
s_waitcnt_depctr 0xfff
v_fma_f32 v10, -v6, v8, 1.0
v_fmac_f32_e32 v8, v10, v8
v_mul_f32_e32 v10, v11, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f32_e32 v12, v9, v8
v_fma_f32 v13, -v4, v10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v14, -v6, v12, v9
v_fmac_f32_e32 v10, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v12, v14, v8
v_fma_f32 v4, -v4, v10, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v6, v12, v9
v_div_fmas_f32 v4, v4, v7, v10
s_mov_b32 vcc_lo, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_div_fmas_f32 v6, v6, v8, v12
v_div_fixup_f32 v3, v4, v5, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fixup_f32 v2, v6, v5, v2
v_add_f32_e32 v4, -1.0, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_i32_f32_e32 v2, v3
v_cvt_i32_f32_e32 v4, v4
.LBB0_2:
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_delay_alu instid0(VALU_DEP_2)
v_cmp_le_i32_e64 s2, v2, v4
s_xor_b32 s5, s6, -1
v_mov_b32_e32 v3, 0
s_or_b32 s5, s5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s5, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_6
s_load_b64 s[6:7], s[0:1], 0x0
v_ashrrev_i32_e32 v3, 31, v2
v_add_nc_u32_e32 v5, -1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 2, v[2:3]
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v1, vcc_lo, s6, v6
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v7, vcc_lo
s_mov_b32 s6, 0
.LBB0_4:
global_load_b32 v6, v[1:2], off
v_add_nc_u32_e32 v5, 1, v5
v_add_co_u32 v1, vcc_lo, v1, 4
v_add_co_ci_u32_e32 v2, vcc_lo, 0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_i32_e64 s2, v5, v4
s_or_b32 s6, s2, s6
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v6
s_and_not1_b32 exec_lo, exec_lo, s6
s_cbranch_execnz .LBB0_4
s_or_b32 exec_lo, exec_lo, s6
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s5
v_lshl_add_u32 v1, v0, 2, 0
s_cmp_lt_u32 s3, 2
ds_store_b32 v1, v3
s_waitcnt lgkmcnt(0)
s_barrier
s_branch .LBB0_8
.p2align 6
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt lgkmcnt(0)
s_barrier
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s2
.LBB0_8:
buffer_gl0_inv
s_cbranch_scc1 .LBB0_11
s_lshr_b32 s2, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s2, v0
s_cbranch_execz .LBB0_7
v_add_nc_u32_e32 v2, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_lshl_add_u32 v2, v2, 2, 0
ds_load_b32 v2, v2
ds_load_b32 v3, v1
s_waitcnt lgkmcnt(0)
v_add_f32_e32 v2, v2, v3
ds_store_b32 v1, v2
s_branch .LBB0_7
.LBB0_11:
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
s_load_b64 s[0:1], s[0:1], 0x8
s_ashr_i32 s5, s4, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[2:3], s[4:5], 2
ds_load_b32 v0, v0
s_waitcnt lgkmcnt(0)
s_add_u32 s0, s0, s2
s_addc_u32 s1, s1, s3
global_store_b32 v1, v0, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12reductionGPUPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 15
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12reductionGPUPfS_i, .Lfunc_end0-_Z12reductionGPUPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
- .offset: 144
.size: 4
.value_kind: hidden_dynamic_lds_size
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12reductionGPUPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12reductionGPUPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 15
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* Copyright 2017 Eric Aubanel
* This file contains code implementing Algorithm 4.14 from
* Elements of Parallel Computing, by Eric Aubanel, 2016, CRC Press.
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
* -------------------------------------------------------------------
* Implementation of reduction of n floats using CUDA
*/
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
int isPowerOf2(int n);
//reduce n floats in array a to a partial sum for each block,
//stored in array c. Block size must be power of 2
__global__ void reductionGPU(float *a, float *c, int n){
//size of b indicated by kernel call in main (blockSize)
extern __shared__ float b[];
int gsize = blockDim.x; //block size
int nt = gsize * gridDim.x; //total number of threads
int gid = blockIdx.x; //block id
int tid = threadIdx.x; //local thread id
int id = gid*gsize + tid; //global thread id
//if n<nt, then some threads will have nothing to do
int istart;
int iend;
if(n<nt){
istart = id;
iend = id;
}
else{
//evaluate as float to avoid overflow
istart = (float)id*n/nt;
iend = (float)(id+1)*n/nt - 1;
}
if(n<nt && id>=n){
b[tid] = 0;
}else{
float psum = 0.0;
for(int i=istart; i<=iend; i++)
psum += a[i];
b[tid] = psum;
}
__syncthreads();
for(int j=gsize>>1; j>=1; j >>= 1){
if(tid<j)
b[tid] += b[tid+j];
__syncthreads();
}
c[gid] = b[0];
}
int main(int argc, char **argv){
float *a_h; //array to be reduced on host (CPU)
float *c_h; //array of partial sums on host
float *a_d; //array to be reduced on device (GPU)
float *c_d; //array of partial sums on device
hipError_t error1, error2;
struct timespec tstart, tend;
float time;
if(argc < 4){
fprintf(stderr,"usage: %s n blockSize numBlocks\n", argv[0]);
return 1;
}
int n = strtol(argv[1], NULL, 10);
int blockSize = strtol(argv[2], NULL, 10); //size of thread block on device
int numBlocks = strtol(argv[3], NULL, 10); //number of blocks on device
if(!isPowerOf2(blockSize)){
fprintf(stderr,"blockSize must be power of 2\n");
return 1;
}
//memory allocation on host and device
a_h = (float *)malloc(n*sizeof(float));
c_h = (float *)malloc(numBlocks*sizeof(float));
if(a_h == NULL || c_h == NULL){
fprintf(stderr,"couldn't allocate memory on host\n");
return 1;
}
error1 = hipMalloc((void **)&a_d, n*sizeof(float));
error2 = hipMalloc((void **)&c_d, numBlocks*sizeof(float));
if(error1 != hipSuccess || error2 != hipSuccess){
fprintf(stderr,"couldn't allocate memory on device\n");
return 1;
}
for(int i=0; i<n; i++)
a_h[i] = rand()%100;
//sequential reduction for verification and timing
clock_gettime(CLOCK_MONOTONIC, &tstart);
float sum = 0.0;
for(int i=0; i<n; i++)
sum += a_h[i];
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("CPU reduction time in s: %f\n", time);
//timing won't include transfer of array to device
hipMemcpy(a_d, a_h, n*sizeof(float), hipMemcpyHostToDevice);
clock_gettime(CLOCK_MONOTONIC, &tstart);
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error1 = hipDeviceSynchronize();// wait until GPU kernel finished
if(error1 != hipSuccess){
fprintf(stderr,"error executing kernel: %s\n", hipGetErrorString(error1));
return 1;
}
//Do not copy back to host and do CPU reduction. Do it on the GPU recersively.
while(1){
hipMemset(a_d, 0, n);
n = numBlocks;
numBlocks = n/blockSize + ((n%blockSize==0)?0:1);
hipMemcpy(a_d, c_d, n*sizeof(float), hipMemcpyDeviceToDevice);
hipMemset(c_d, 0, n*sizeof(float));
reductionGPU <<<numBlocks, blockSize, blockSize*sizeof(float)>>> (a_d, c_d, n);
error2 = hipDeviceSynchronize();// wait until GPU kernel finished
if(error2 != hipSuccess){
fprintf(stderr,"error executing kernel: %s\n", hipGetErrorString(error2));
return 1;
}
hipMemcpy(c_h, c_d, numBlocks*sizeof(float), hipMemcpyDeviceToHost);
if(numBlocks==1)break;
}
hipMemcpy(c_h, c_d, numBlocks*sizeof(float), hipMemcpyDeviceToHost);
float dsum = c_h[0];
printf("dsum: %f\n", dsum);
clock_gettime(CLOCK_MONOTONIC, &tend);
time = (tend.tv_sec-tstart.tv_sec) + (tend.tv_nsec-tstart.tv_nsec)*1.0e-9;
printf("GPUS time in s: %f\n", time);
//not necessarily the same because of differences in roundoff error
printf("relative difference between sequential and parallel sums: %g\n",
fabs(dsum-sum)/sum);
return 0;
}
int isPowerOf2(int n){
while(n){
if(n & 1)
break;
n >>= 1;
}
return (1 == n? 1:0);
} | .text
.file "reductionCUDA.hip"
.globl _Z27__device_stub__reductionGPUPfS_i # -- Begin function _Z27__device_stub__reductionGPUPfS_i
.p2align 4, 0x90
.type _Z27__device_stub__reductionGPUPfS_i,@function
_Z27__device_stub__reductionGPUPfS_i: # @_Z27__device_stub__reductionGPUPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12reductionGPUPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__reductionGPUPfS_i, .Lfunc_end0-_Z27__device_stub__reductionGPUPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
cmpl $3, %edi
jle .LBB1_1
# %bb.3:
movq 8(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq %r14, %rax
movq %r14, 160(%rsp) # 8-byte Spill
movl %r14d, %ecx
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
movl %ecx, %eax
testl %ecx, %ecx
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=1
movl %eax, %edx
andl $1, %edx
movl %eax, %ecx
sarl %ecx
testl %edx, %edx
je .LBB1_4
.LBB1_6: # %_Z10isPowerOf2i.exit
cmpl $1, %eax
jne .LBB1_7
# %bb.9:
movslq %ebx, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movslq %r15d, %r13
shlq $2, %r13
movq %r13, %rdi
callq malloc
testq %rbp, %rbp
je .LBB1_11
# %bb.10:
testq %rax, %rax
je .LBB1_11
# %bb.12:
movq %rax, 184(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
movq %r14, %r12
movq %r14, %rsi
callq hipMalloc
movl %eax, %r14d
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
orl %r14d, %eax
jne .LBB1_31
# %bb.13: # %.preheader100
testl %ebx, %ebx
jle .LBB1_16
# %bb.14: # %.lr.ph.preheader
movl %ebx, %r14d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_15: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB1_15
.LBB1_16: # %._crit_edge
leaq 112(%rsp), %rsi
movl $1, %edi
callq clock_gettime
testl %ebx, %ebx
jle .LBB1_17
# %bb.26: # %.lr.ph107.preheader
movl %ebx, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_27: # %.lr.ph107
# =>This Inner Loop Header: Depth=1
addss (%rbp,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB1_27
jmp .LBB1_18
.LBB1_17:
xorps %xmm0, %xmm0
.LBB1_18: # %._crit_edge108
movss %xmm0, 92(%rsp) # 4-byte Spill
movabsq $4294967296, %r14 # imm = 0x100000000
leaq 96(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
subq 112(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 120(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
movq %rbp, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 112(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movslq 160(%rsp), %rax # 4-byte Folded Reload
leaq (,%rax,4), %r8
movl %r15d, %edi
orq %r14, %rdi
movl %eax, %ebp
orq %r14, %rbp
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
movq %r8, 192(%rsp) # 8-byte Spill
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_20
# %bb.19:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl %ebx, 4(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12reductionGPUPfS_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_20:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_25
# %bb.21:
movq 184(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB1_22: # =>This Inner Loop Header: Depth=1
movslq %ebx, %rdx
movl %r15d, %ebx
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipMemset
movl %r15d, %eax
cltd
idivl 160(%rsp) # 4-byte Folded Reload
movl %eax, %r15d
cmpl $1, %edx
sbbl $-1, %r15d
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movslq %ebx, %r14
shlq $2, %r14
movq %r14, %rdx
movl $3, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq hipMemset
movq %r15, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
movq 192(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_24
# %bb.23: # in Loop: Header=BB1_22 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl %ebx, 4(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z12reductionGPUPfS_i, %edi
leaq 128(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_24: # in Loop: Header=BB1_22 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_25
# %bb.28: # in Loop: Header=BB1_22 Depth=1
movq 8(%rsp), %rsi
movslq %r15d, %r12
leaq (,%r12,4), %r14
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $1, %r12d
jne .LBB1_22
# %bb.29:
movq 8(%rsp), %rsi
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movss (%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, 160(%rsp) # 16-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leaq 96(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
subq 112(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 120(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 92(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movaps 160(%rsp), %xmm0 # 16-byte Reload
subss %xmm1, %xmm0
andps .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
xorl %eax, %eax
.LBB1_30:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_25:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
jmp .LBB1_2
.LBB1_1:
movq stderr(%rip), %rdi
movq (%r15), %rdx
movl $.L.str, %esi
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %eax
jmp .LBB1_30
.LBB1_7:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $29, %esi
jmp .LBB1_8
.LBB1_11:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $33, %esi
jmp .LBB1_8
.LBB1_31:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $35, %esi
.LBB1_8:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_30
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10isPowerOf2i # -- Begin function _Z10isPowerOf2i
.p2align 4, 0x90
.type _Z10isPowerOf2i,@function
_Z10isPowerOf2i: # @_Z10isPowerOf2i
.cfi_startproc
# %bb.0:
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %edi, %ecx
testl %edi, %edi
je .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movl %ecx, %eax
andl $1, %eax
movl %ecx, %edi
sarl %edi
testl %eax, %eax
je .LBB2_1
.LBB2_3:
xorl %eax, %eax
cmpl $1, %ecx
sete %al
retq
.Lfunc_end2:
.size _Z10isPowerOf2i, .Lfunc_end2-_Z10isPowerOf2i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12reductionGPUPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12reductionGPUPfS_i,@object # @_Z12reductionGPUPfS_i
.section .rodata,"a",@progbits
.globl _Z12reductionGPUPfS_i
.p2align 3, 0x0
_Z12reductionGPUPfS_i:
.quad _Z27__device_stub__reductionGPUPfS_i
.size _Z12reductionGPUPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: %s n blockSize numBlocks\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "blockSize must be power of 2\n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "couldn't allocate memory on host\n"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "couldn't allocate memory on device\n"
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU reduction time in s: %f\n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "error executing kernel: %s\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "dsum: %f\n"
.size .L.str.6, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPUS time in s: %f\n"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "relative difference between sequential and parallel sums: %g\n"
.size .L.str.8, 62
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12reductionGPUPfS_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__reductionGPUPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12reductionGPUPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000f2bf2_00000000-6_reductionCUDA.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10isPowerOf2i
.type _Z10isPowerOf2i, @function
_Z10isPowerOf2i:
.LFB2058:
.cfi_startproc
endbr64
testl %edi, %edi
je .L4
testb $1, %dil
jne .L4
.L5:
sarl %edi
je .L4
testb $1, %dil
je .L5
.L4:
cmpl $1, %edi
sete %al
movzbl %al, %eax
ret
.cfi_endproc
.LFE2058:
.size _Z10isPowerOf2i, .-_Z10isPowerOf2i
.globl _Z35__device_stub__Z12reductionGPUPfS_iPfS_i
.type _Z35__device_stub__Z12reductionGPUPfS_iPfS_i, @function
_Z35__device_stub__Z12reductionGPUPfS_iPfS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12reductionGPUPfS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z35__device_stub__Z12reductionGPUPfS_iPfS_i, .-_Z35__device_stub__Z12reductionGPUPfS_iPfS_i
.globl _Z12reductionGPUPfS_i
.type _Z12reductionGPUPfS_i, @function
_Z12reductionGPUPfS_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12reductionGPUPfS_iPfS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z12reductionGPUPfS_i, .-_Z12reductionGPUPfS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC1:
.string "usage: %s n blockSize numBlocks\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "blockSize must be power of 2\n"
.section .rodata.str1.8
.align 8
.LC3:
.string "couldn't allocate memory on host\n"
.align 8
.LC4:
.string "couldn't allocate memory on device\n"
.section .rodata.str1.1
.LC6:
.string "CPU reduction time in s: %f\n"
.LC7:
.string "error executing kernel: %s\n"
.LC8:
.string "dsum: %f\n"
.LC9:
.string "GPUS time in s: %f\n"
.section .rodata.str1.8
.align 8
.LC11:
.string "relative difference between sequential and parallel sums: %g\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
cmpl $3, %edi
jle .L39
movq 8(%rsi), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 40(%rsp)
movl %eax, %r14d
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, 16(%rsp)
movl %r14d, %edi
call _Z10isPowerOf2i
testl %eax, %eax
je .L40
movl %r13d, %ebp
movq 16(%rsp), %r12
movl %r12d, %ebx
movslq %r13d, %rax
salq $2, %rax
movq %rax, 24(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %r15
movq %rax, 32(%rsp)
movslq %r12d, %rax
leaq 0(,%rax,4), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
testq %r15, %r15
je .L32
testq %rax, %rax
je .L32
leaq 56(%rsp), %rdi
movq 24(%rsp), %rsi
call cudaMalloc@PLT
movl %eax, %r15d
leaq 64(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
orl %r15d, %eax
jne .L21
testl %r13d, %r13d
jle .L41
movq 32(%rsp), %rcx
movq %rcx, %r12
leal -1(%r13), %eax
movq %rcx, %r13
leaq 4(%rcx,%rax,4), %r15
.L24:
call rand@PLT
movslq %eax, %rdx
imulq $1374389535, %rdx, %rdx
sarq $37, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $100, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%r13)
addq $4, %r13
cmpq %r15, %r13
jne .L24
leaq 96(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $0x00000000, 4(%rsp)
.L25:
movss 4(%rsp), %xmm2
addss (%r12), %xmm2
movss %xmm2, 4(%rsp)
addq $4, %r12
cmpq %r15, %r12
jne .L25
.L30:
leaq 112(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC5(%rip), %xmm0
movq 112(%rsp), %rax
subq 96(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $1, %ecx
movq 24(%rsp), %rdx
movq 32(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
leaq 96(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movq 40(%rsp), %rcx
movslq %ecx, %rax
leaq 0(,%rax,4), %r15
movl %ecx, %r13d
movl %ecx, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl 16(%rsp), %eax
movl %eax, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movq %r15, %r8
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L26:
call cudaThreadSynchronize@PLT
testl %eax, %eax
je .L27
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L39:
movq (%rsi), %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
.L15:
movq 136(%rsp), %rdx
subq %fs:40, %rdx
jne .L43
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L40:
.cfi_restore_state
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L32:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L21:
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L42:
movl %ebp, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z12reductionGPUPfS_iPfS_i
jmp .L26
.L28:
call cudaThreadSynchronize@PLT
testl %eax, %eax
jne .L44
movslq %ebx, %rdx
salq $2, %rdx
movl $2, %ecx
movq 64(%rsp), %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
cmpl $1, %ebx
je .L45
.L27:
movslq %ebp, %rdx
movl $0, %esi
movq 56(%rsp), %rdi
call cudaMemset@PLT
movl %ebx, %eax
cltd
idivl %r14d
movl %ebx, %ebp
cmpl $1, %edx
sbbl $-1, %eax
movl %eax, %ebx
movslq %ebp, %r12
salq $2, %r12
movl $3, %ecx
movq %r12, %rdx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movq %r12, %rdx
movl $0, %esi
movq 64(%rsp), %rdi
call cudaMemset@PLT
movl %r13d, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl %ebx, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $0, %r9d
movq %r15, %r8
movq 84(%rsp), %rdx
movl $1, %ecx
movq 72(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L28
movl %ebp, %edx
movq 64(%rsp), %rsi
movq 56(%rsp), %rdi
call _Z35__device_stub__Z12reductionGPUPfS_iPfS_i
jmp .L28
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %eax
jmp .L15
.L45:
movl $2, %ecx
movl $4, %edx
movq 64(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movss (%rbx), %xmm0
movss %xmm0, 8(%rsp)
cvtss2sd %xmm0, %xmm0
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq 112(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movq 120(%rsp), %rax
subq 104(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
mulsd .LC5(%rip), %xmm0
movq 112(%rsp), %rax
subq 96(%rsp), %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
addsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 8(%rsp), %xmm0
movss 4(%rsp), %xmm3
subss %xmm3, %xmm0
andps .LC10(%rip), %xmm0
divss %xmm3, %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $0, %eax
jmp .L15
.L41:
leaq 96(%rsp), %rsi
movl $1, %edi
call clock_gettime@PLT
movl $0x00000000, 4(%rsp)
jmp .L30
.L43:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC12:
.string "_Z12reductionGPUPfS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _Z12reductionGPUPfS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC5:
.long -400107883
.long 1041313291
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC10:
.long 2147483647
.long 0
.long 0
.long 0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reductionCUDA.hip"
.globl _Z27__device_stub__reductionGPUPfS_i # -- Begin function _Z27__device_stub__reductionGPUPfS_i
.p2align 4, 0x90
.type _Z27__device_stub__reductionGPUPfS_i,@function
_Z27__device_stub__reductionGPUPfS_i: # @_Z27__device_stub__reductionGPUPfS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12reductionGPUPfS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__reductionGPUPfS_i, .Lfunc_end0-_Z27__device_stub__reductionGPUPfS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x3e112e0be826d695 # double 1.0000000000000001E-9
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0
.LCPI1_1:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r15
cmpl $3, %edi
jle .LBB1_1
# %bb.3:
movq 8(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 16(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%r15), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq %r14, %rax
movq %r14, 160(%rsp) # 8-byte Spill
movl %r14d, %ecx
.p2align 4, 0x90
.LBB1_4: # =>This Inner Loop Header: Depth=1
movl %ecx, %eax
testl %ecx, %ecx
je .LBB1_6
# %bb.5: # in Loop: Header=BB1_4 Depth=1
movl %eax, %edx
andl $1, %edx
movl %eax, %ecx
sarl %ecx
testl %edx, %edx
je .LBB1_4
.LBB1_6: # %_Z10isPowerOf2i.exit
cmpl $1, %eax
jne .LBB1_7
# %bb.9:
movslq %ebx, %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbp
movslq %r15d, %r13
shlq $2, %r13
movq %r13, %rdi
callq malloc
testq %rbp, %rbp
je .LBB1_11
# %bb.10:
testq %rax, %rax
je .LBB1_11
# %bb.12:
movq %rax, 184(%rsp) # 8-byte Spill
leaq 16(%rsp), %rdi
movq %r14, %r12
movq %r14, %rsi
callq hipMalloc
movl %eax, %r14d
leaq 8(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
orl %r14d, %eax
jne .LBB1_31
# %bb.13: # %.preheader100
testl %ebx, %ebx
jle .LBB1_16
# %bb.14: # %.lr.ph.preheader
movl %ebx, %r14d
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB1_15: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1374389535, %rax, %rcx # imm = 0x51EB851F
movq %rcx, %rdx
shrq $63, %rdx
sarq $37, %rcx
addl %edx, %ecx
imull $100, %ecx, %ecx
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%rbp,%r13,4)
incq %r13
cmpq %r13, %r14
jne .LBB1_15
.LBB1_16: # %._crit_edge
leaq 112(%rsp), %rsi
movl $1, %edi
callq clock_gettime
testl %ebx, %ebx
jle .LBB1_17
# %bb.26: # %.lr.ph107.preheader
movl %ebx, %eax
xorps %xmm0, %xmm0
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_27: # %.lr.ph107
# =>This Inner Loop Header: Depth=1
addss (%rbp,%rcx,4), %xmm0
incq %rcx
cmpq %rcx, %rax
jne .LBB1_27
jmp .LBB1_18
.LBB1_17:
xorps %xmm0, %xmm0
.LBB1_18: # %._crit_edge108
movss %xmm0, 92(%rsp) # 4-byte Spill
movabsq $4294967296, %r14 # imm = 0x100000000
leaq 96(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
subq 112(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 120(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movq 16(%rsp), %rdi
movq %rbp, %rsi
movq %r12, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 112(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movslq 160(%rsp), %rax # 4-byte Folded Reload
leaq (,%rax,4), %r8
movl %r15d, %edi
orq %r14, %rdi
movl %eax, %ebp
orq %r14, %rbp
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
movq %r8, 192(%rsp) # 8-byte Spill
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_20
# %bb.19:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl %ebx, 4(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z12reductionGPUPfS_i, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_20:
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_25
# %bb.21:
movq 184(%rsp), %r13 # 8-byte Reload
.p2align 4, 0x90
.LBB1_22: # =>This Inner Loop Header: Depth=1
movslq %ebx, %rdx
movl %r15d, %ebx
movq 16(%rsp), %rdi
xorl %esi, %esi
callq hipMemset
movl %r15d, %eax
cltd
idivl 160(%rsp) # 4-byte Folded Reload
movl %eax, %r15d
cmpl $1, %edx
sbbl $-1, %r15d
movq 16(%rsp), %rdi
movq 8(%rsp), %rsi
movslq %ebx, %r14
shlq $2, %r14
movq %r14, %rdx
movl $3, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %r14, %rdx
callq hipMemset
movq %r15, %rdi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl $1, %esi
movq %rbp, %rdx
movl $1, %ecx
movq 192(%rsp), %r8 # 8-byte Reload
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_24
# %bb.23: # in Loop: Header=BB1_22 Depth=1
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl %ebx, 4(%rsp)
leaq 80(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rax
movq %rax, 136(%rsp)
leaq 4(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
movl $_Z12reductionGPUPfS_i, %edi
leaq 128(%rsp), %r9
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_24: # in Loop: Header=BB1_22 Depth=1
callq hipDeviceSynchronize
testl %eax, %eax
jne .LBB1_25
# %bb.28: # in Loop: Header=BB1_22 Depth=1
movq 8(%rsp), %rsi
movslq %r15d, %r12
leaq (,%r12,4), %r14
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
cmpl $1, %r12d
jne .LBB1_22
# %bb.29:
movq 8(%rsp), %rsi
movq %r13, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movss (%r13), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, 160(%rsp) # 16-byte Spill
cvtss2sd %xmm0, %xmm0
movl $.L.str.6, %edi
movb $1, %al
callq printf
leaq 96(%rsp), %rsi
movl $1, %edi
callq clock_gettime
movq 96(%rsp), %rax
movq 104(%rsp), %rcx
subq 112(%rsp), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
subq 120(%rsp), %rcx
cvtsi2sd %rcx, %xmm1
mulsd .LCPI1_0(%rip), %xmm1
addsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.7, %edi
movb $1, %al
callq printf
movss 92(%rsp), %xmm1 # 4-byte Reload
# xmm1 = mem[0],zero,zero,zero
movaps 160(%rsp), %xmm0 # 16-byte Reload
subss %xmm1, %xmm0
andps .LCPI1_1(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
divsd %xmm1, %xmm0
movl $.L.str.8, %edi
movb $1, %al
callq printf
xorl %eax, %eax
.LBB1_30:
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_25:
.cfi_def_cfa_offset 256
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
movq %rbx, %rdi
movq %rax, %rdx
jmp .LBB1_2
.LBB1_1:
movq stderr(%rip), %rdi
movq (%r15), %rdx
movl $.L.str, %esi
.LBB1_2:
xorl %eax, %eax
callq fprintf
movl $1, %eax
jmp .LBB1_30
.LBB1_7:
movq stderr(%rip), %rcx
movl $.L.str.1, %edi
movl $29, %esi
jmp .LBB1_8
.LBB1_11:
movq stderr(%rip), %rcx
movl $.L.str.2, %edi
movl $33, %esi
jmp .LBB1_8
.LBB1_31:
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $35, %esi
.LBB1_8:
movl $1, %edx
callq fwrite@PLT
movl $1, %eax
jmp .LBB1_30
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.globl _Z10isPowerOf2i # -- Begin function _Z10isPowerOf2i
.p2align 4, 0x90
.type _Z10isPowerOf2i,@function
_Z10isPowerOf2i: # @_Z10isPowerOf2i
.cfi_startproc
# %bb.0:
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %edi, %ecx
testl %edi, %edi
je .LBB2_3
# %bb.2: # in Loop: Header=BB2_1 Depth=1
movl %ecx, %eax
andl $1, %eax
movl %ecx, %edi
sarl %edi
testl %eax, %eax
je .LBB2_1
.LBB2_3:
xorl %eax, %eax
cmpl $1, %ecx
sete %al
retq
.Lfunc_end2:
.size _Z10isPowerOf2i, .Lfunc_end2-_Z10isPowerOf2i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12reductionGPUPfS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12reductionGPUPfS_i,@object # @_Z12reductionGPUPfS_i
.section .rodata,"a",@progbits
.globl _Z12reductionGPUPfS_i
.p2align 3, 0x0
_Z12reductionGPUPfS_i:
.quad _Z27__device_stub__reductionGPUPfS_i
.size _Z12reductionGPUPfS_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "usage: %s n blockSize numBlocks\n"
.size .L.str, 33
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "blockSize must be power of 2\n"
.size .L.str.1, 30
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "couldn't allocate memory on host\n"
.size .L.str.2, 34
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "couldn't allocate memory on device\n"
.size .L.str.3, 36
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "CPU reduction time in s: %f\n"
.size .L.str.4, 29
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "error executing kernel: %s\n"
.size .L.str.5, 28
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "dsum: %f\n"
.size .L.str.6, 10
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "GPUS time in s: %f\n"
.size .L.str.7, 20
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "relative difference between sequential and parallel sums: %g\n"
.size .L.str.8, 62
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12reductionGPUPfS_i"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__reductionGPUPfS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12reductionGPUPfS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void tex_kernel(cudaTextureObject_t texture_obj, int num_samples, float* output) {
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < num_samples) {
float u = idx / static_cast<float>(num_samples);
output[idx] = tex1D<float>(texture_obj, u);
}
} | code for sm_80
Function : _Z10tex_kernelyiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F R3, c[0x0][0x168] ; /* 0x00005a0000037b06 */
/* 0x000e220000201400 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x150 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0090*/ I2F.U32 R4, R0 ; /* 0x0000000000047306 */
/* 0x000e700000201000 */
/*00a0*/ MUFU.RCP R2, R3 ; /* 0x0000000300027308 */
/* 0x001e300000001000 */
/*00b0*/ FCHK P0, R4, R3 ; /* 0x0000000304007302 */
/* 0x002e620000000000 */
/*00c0*/ FFMA R5, -R3, R2, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000102 */
/*00d0*/ FFMA R5, R2, R5, R2 ; /* 0x0000000502057223 */
/* 0x000fc80000000002 */
/*00e0*/ FFMA R2, R4, R5, RZ ; /* 0x0000000504027223 */
/* 0x000fc800000000ff */
/*00f0*/ FFMA R6, -R3, R2, R4 ; /* 0x0000000203067223 */
/* 0x000fc80000000104 */
/*0100*/ FFMA R6, R5, R6, R2 ; /* 0x0000000605067223 */
/* 0x000fe20000000002 */
/*0110*/ @!P0 BRA 0x140 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0120*/ MOV R2, 0x140 ; /* 0x0000014000027802 */
/* 0x000fe40000000f00 */
/*0130*/ CALL.REL.NOINC 0x1c0 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, -0x3e000000 ; /* 0xc2000000ff047424 */
/* 0x000fc800078e00ff */
/*0170*/ TEX.SCR.LL RZ, R7, R6, R4, 0x0, 0x58, 2D, 0x1 ; /* 0x3000580406077b60 */
/* 0x000f4200019e01ff */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*01a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x020fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ SHF.R.U32.HI R6, RZ, 0x17, R3.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011603 */
/*01d0*/ BSSY B1, 0x820 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*01e0*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0004 */
/*0200*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0003 */
/*0220*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0230*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0240*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0250*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0260*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0270*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0280*/ @!P0 BRA 0x400 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0290*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*02a0*/ FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fc80003f3c200 */
/*02b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02c0*/ @P0 BRA 0x800 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02d0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*02e0*/ @!P0 BRA 0x7e0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0300*/ FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f3d200 */
/*0310*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0320*/ @!P1 BRA !P2, 0x7e0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0330*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0340*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0350*/ @P1 BRA 0x7c0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0370*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0380*/ @P0 BRA 0x790 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*03a0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*03b0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*03c0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*03d0*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*03e0*/ @!P1 FFMA R8, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003089823 */
/* 0x000fe200000000ff */
/*03f0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0400*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*0410*/ BSSY B2, 0x780 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0420*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0430*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*0440*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0450*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0460*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0470*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*0480*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0490*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*04a0*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*04b0*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*04c0*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*04d0*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*04e0*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*04f0*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0500*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0510*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0520*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0530*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0540*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0550*/ @!P0 BRA 0x760 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0560*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0570*/ @P0 BRA 0x730 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0590*/ @P0 BRA 0x770 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*05b0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*05c0*/ @!P0 BRA 0x770 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05d0*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*05e0*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*05f0*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0600*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0610*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0620*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0630*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0640*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0650*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0660*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0670*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0680*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0690*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*06a0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*06b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06c0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*06d0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*06e0*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*06f0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0700*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0710*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0720*/ BRA 0x770 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0730*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0740*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0750*/ BRA 0x770 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0770*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x810 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*07a0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x810 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07c0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*07d0*/ BRA 0x810 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07e0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*07f0*/ BRA 0x810 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0800*/ FADD.FTZ R3, R4, R3 ; /* 0x0000000304037221 */
/* 0x000fe40000010000 */
/*0810*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0003 */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0840*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7b002007950 */
/* 0x000fea0003c3ffff */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void tex_kernel(cudaTextureObject_t texture_obj, int num_samples, float* output) {
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < num_samples) {
float u = idx / static_cast<float>(num_samples);
output[idx] = tex1D<float>(texture_obj, u);
}
} | .file "tmpxft_000ea293_00000000-6_tex_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10tex_kernelyiPfyiPf
.type _Z32__device_stub__Z10tex_kernelyiPfyiPf, @function
_Z32__device_stub__Z10tex_kernelyiPfyiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10tex_kernelyiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10tex_kernelyiPfyiPf, .-_Z32__device_stub__Z10tex_kernelyiPfyiPf
.globl _Z10tex_kernelyiPf
.type _Z10tex_kernelyiPf, @function
_Z10tex_kernelyiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10tex_kernelyiPfyiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10tex_kernelyiPf, .-_Z10tex_kernelyiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10tex_kernelyiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10tex_kernelyiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void tex_kernel(cudaTextureObject_t texture_obj, int num_samples, float* output) {
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < num_samples) {
float u = idx / static_cast<float>(num_samples);
output[idx] = tex1D<float>(texture_obj, u);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void tex_kernel(hipTextureObject_t texture_obj, int num_samples, float* output) {
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < num_samples) {
float u = idx / static_cast<float>(num_samples);
output[idx] = tex1D<float>(texture_obj, u);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void tex_kernel(hipTextureObject_t texture_obj, int num_samples, float* output) {
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < num_samples) {
float u = idx / static_cast<float>(num_samples);
output[idx] = tex1D<float>(texture_obj, u);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10tex_kernelP13__hip_textureiPf
.globl _Z10tex_kernelP13__hip_textureiPf
.p2align 8
.type _Z10tex_kernelP13__hip_textureiPf,@function
_Z10tex_kernelP13__hip_textureiPf:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_2
v_cvt_f32_u32_e32 v0, v1
v_cvt_f32_i32_e32 v2, s2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x2
s_load_b32 s0, s[2:3], 0x30
s_load_b32 s1, s[2:3], 0x38
s_load_b32 s4, s[2:3], 0x28
v_div_scale_f32 v3, null, v2, v2, v0
v_div_scale_f32 v6, vcc_lo, v0, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s1, 20
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v5
v_cvt_f32_u32_e32 v4, s4
s_cselect_b32 vcc_lo, -1, 0
s_bitcmp0_b32 s0, 15
s_cselect_b32 s0, -1, 0
v_div_fixup_f32 v0, v3, v2, v0
v_cndmask_b32_e64 v2, 1.0, v4, s0
s_clause 0x1
s_load_b128 s[8:11], s[2:3], 0x30
s_load_b256 s[0:7], s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
v_mul_f32_e32 v2, v0, v2
v_floor_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
image_sample_lz v3, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s12, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10tex_kernelP13__hip_textureiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10tex_kernelP13__hip_textureiPf, .Lfunc_end0-_Z10tex_kernelP13__hip_textureiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10tex_kernelP13__hip_textureiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10tex_kernelP13__hip_textureiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void tex_kernel(hipTextureObject_t texture_obj, int num_samples, float* output) {
unsigned int idx = blockIdx.x*blockDim.x + threadIdx.x;
if (idx < num_samples) {
float u = idx / static_cast<float>(num_samples);
output[idx] = tex1D<float>(texture_obj, u);
}
} | .text
.file "tex_kernel.hip"
.globl _Z25__device_stub__tex_kernelP13__hip_textureiPf # -- Begin function _Z25__device_stub__tex_kernelP13__hip_textureiPf
.p2align 4, 0x90
.type _Z25__device_stub__tex_kernelP13__hip_textureiPf,@function
_Z25__device_stub__tex_kernelP13__hip_textureiPf: # @_Z25__device_stub__tex_kernelP13__hip_textureiPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10tex_kernelP13__hip_textureiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__tex_kernelP13__hip_textureiPf, .Lfunc_end0-_Z25__device_stub__tex_kernelP13__hip_textureiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10tex_kernelP13__hip_textureiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10tex_kernelP13__hip_textureiPf,@object # @_Z10tex_kernelP13__hip_textureiPf
.section .rodata,"a",@progbits
.globl _Z10tex_kernelP13__hip_textureiPf
.p2align 3, 0x0
_Z10tex_kernelP13__hip_textureiPf:
.quad _Z25__device_stub__tex_kernelP13__hip_textureiPf
.size _Z10tex_kernelP13__hip_textureiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10tex_kernelP13__hip_textureiPf"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__tex_kernelP13__hip_textureiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10tex_kernelP13__hip_textureiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z10tex_kernelyiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06070 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ I2F R3, c[0x0][0x168] ; /* 0x00005a0000037b06 */
/* 0x000e220000201400 */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0080*/ BSSY B0, 0x150 ; /* 0x000000c000007945 */
/* 0x000fec0003800000 */
/*0090*/ I2F.U32 R4, R0 ; /* 0x0000000000047306 */
/* 0x000e700000201000 */
/*00a0*/ MUFU.RCP R2, R3 ; /* 0x0000000300027308 */
/* 0x001e300000001000 */
/*00b0*/ FCHK P0, R4, R3 ; /* 0x0000000304007302 */
/* 0x002e620000000000 */
/*00c0*/ FFMA R5, -R3, R2, 1 ; /* 0x3f80000003057423 */
/* 0x001fc80000000102 */
/*00d0*/ FFMA R5, R2, R5, R2 ; /* 0x0000000502057223 */
/* 0x000fc80000000002 */
/*00e0*/ FFMA R2, R4, R5, RZ ; /* 0x0000000504027223 */
/* 0x000fc800000000ff */
/*00f0*/ FFMA R6, -R3, R2, R4 ; /* 0x0000000203067223 */
/* 0x000fc80000000104 */
/*0100*/ FFMA R6, R5, R6, R2 ; /* 0x0000000605067223 */
/* 0x000fe20000000002 */
/*0110*/ @!P0 BRA 0x140 ; /* 0x0000002000008947 */
/* 0x002fea0003800000 */
/*0120*/ MOV R2, 0x140 ; /* 0x0000014000027802 */
/* 0x000fe40000000f00 */
/*0130*/ CALL.REL.NOINC 0x1c0 ; /* 0x0000008000007944 */
/* 0x000fea0003c00000 */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ IMAD.MOV.U32 R7, RZ, RZ, RZ ; /* 0x000000ffff077224 */
/* 0x000fe400078e00ff */
/*0160*/ IMAD.MOV.U32 R4, RZ, RZ, -0x3e000000 ; /* 0xc2000000ff047424 */
/* 0x000fc800078e00ff */
/*0170*/ TEX.SCR.LL RZ, R7, R6, R4, 0x0, 0x58, 2D, 0x1 ; /* 0x3000580406077b60 */
/* 0x000f4200019e01ff */
/*0180*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc800078e00ff */
/*0190*/ IMAD.WIDE.U32 R2, R0, R3, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fca00078e0003 */
/*01a0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x020fe2000c101904 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ SHF.R.U32.HI R6, RZ, 0x17, R3.reuse ; /* 0x00000017ff067819 */
/* 0x100fe20000011603 */
/*01d0*/ BSSY B1, 0x820 ; /* 0x0000064000017945 */
/* 0x000fe20003800000 */
/*01e0*/ SHF.R.U32.HI R5, RZ, 0x17, R4.reuse ; /* 0x00000017ff057819 */
/* 0x100fe20000011604 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, R4 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0004 */
/*0200*/ LOP3.LUT R6, R6, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff06067812 */
/* 0x000fe200078ec0ff */
/*0210*/ IMAD.MOV.U32 R8, RZ, RZ, R3 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0003 */
/*0220*/ LOP3.LUT R5, R5, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff05057812 */
/* 0x000fe400078ec0ff */
/*0230*/ IADD3 R11, R6, -0x1, RZ ; /* 0xffffffff060b7810 */
/* 0x000fe40007ffe0ff */
/*0240*/ IADD3 R10, R5, -0x1, RZ ; /* 0xffffffff050a7810 */
/* 0x000fc40007ffe0ff */
/*0250*/ ISETP.GT.U32.AND P0, PT, R11, 0xfd, PT ; /* 0x000000fd0b00780c */
/* 0x000fc80003f04070 */
/*0260*/ ISETP.GT.U32.OR P0, PT, R10, 0xfd, P0 ; /* 0x000000fd0a00780c */
/* 0x000fda0000704470 */
/*0270*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff098224 */
/* 0x000fe200078e00ff */
/*0280*/ @!P0 BRA 0x400 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0290*/ FSETP.GTU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fe40003f1c200 */
/*02a0*/ FSETP.GTU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fc80003f3c200 */
/*02b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000703570 */
/*02c0*/ @P0 BRA 0x800 ; /* 0x0000053000000947 */
/* 0x000fea0003800000 */
/*02d0*/ LOP3.LUT P0, RZ, R8, 0x7fffffff, R7, 0xc8, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fda000780c807 */
/*02e0*/ @!P0 BRA 0x7e0 ; /* 0x000004f000008947 */
/* 0x000fea0003800000 */
/*02f0*/ FSETP.NEU.FTZ.AND P2, PT, |R4|.reuse, +INF , PT ; /* 0x7f8000000400780b */
/* 0x040fe40003f5d200 */
/*0300*/ FSETP.NEU.FTZ.AND P1, PT, |R3|, +INF , PT ; /* 0x7f8000000300780b */
/* 0x000fe40003f3d200 */
/*0310*/ FSETP.NEU.FTZ.AND P0, PT, |R4|, +INF , PT ; /* 0x7f8000000400780b */
/* 0x000fd60003f1d200 */
/*0320*/ @!P1 BRA !P2, 0x7e0 ; /* 0x000004b000009947 */
/* 0x000fea0005000000 */
/*0330*/ LOP3.LUT P2, RZ, R7, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff07ff7812 */
/* 0x000fc8000784c0ff */
/*0340*/ PLOP3.LUT P1, PT, P1, P2, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000f24572 */
/*0350*/ @P1 BRA 0x7c0 ; /* 0x0000046000001947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT P1, RZ, R8, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff08ff7812 */
/* 0x000fc8000782c0ff */
/*0370*/ PLOP3.LUT P0, PT, P0, P1, PT, 0x2a, 0x0 ; /* 0x000000000000781c */
/* 0x000fda0000702572 */
/*0380*/ @P0 BRA 0x790 ; /* 0x0000040000000947 */
/* 0x000fea0003800000 */
/*0390*/ ISETP.GE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe40003f06270 */
/*03a0*/ ISETP.GE.AND P1, PT, R11, RZ, PT ; /* 0x000000ff0b00720c */
/* 0x000fd60003f26270 */
/*03b0*/ @P0 IMAD.MOV.U32 R9, RZ, RZ, RZ ; /* 0x000000ffff090224 */
/* 0x000fe400078e00ff */
/*03c0*/ @!P0 IMAD.MOV.U32 R9, RZ, RZ, -0x40 ; /* 0xffffffc0ff098424 */
/* 0x000fe400078e00ff */
/*03d0*/ @!P0 FFMA R7, R4, 1.84467440737095516160e+19, RZ ; /* 0x5f80000004078823 */
/* 0x000fe400000000ff */
/*03e0*/ @!P1 FFMA R8, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003089823 */
/* 0x000fe200000000ff */
/*03f0*/ @!P1 IADD3 R9, R9, 0x40, RZ ; /* 0x0000004009099810 */
/* 0x000fe40007ffe0ff */
/*0400*/ LEA R3, R6, 0xc0800000, 0x17 ; /* 0xc080000006037811 */
/* 0x000fe200078eb8ff */
/*0410*/ BSSY B2, 0x780 ; /* 0x0000036000027945 */
/* 0x000fe20003800000 */
/*0420*/ IADD3 R5, R5, -0x7f, RZ ; /* 0xffffff8105057810 */
/* 0x000fc60007ffe0ff */
/*0430*/ IMAD.IADD R8, R8, 0x1, -R3 ; /* 0x0000000108087824 */
/* 0x000fe200078e0a03 */
/*0440*/ IADD3 R6, R5.reuse, 0x7f, -R6 ; /* 0x0000007f05067810 */
/* 0x040fe20007ffe806 */
/*0450*/ IMAD R7, R5, -0x800000, R7 ; /* 0xff80000005077824 */
/* 0x000fe400078e0207 */
/*0460*/ MUFU.RCP R3, R8 ; /* 0x0000000800037308 */
/* 0x000e220000001000 */
/*0470*/ FADD.FTZ R4, -R8, -RZ ; /* 0x800000ff08047221 */
/* 0x000fe40000010100 */
/*0480*/ IMAD.IADD R6, R6, 0x1, R9 ; /* 0x0000000106067824 */
/* 0x000fe400078e0209 */
/*0490*/ FFMA R10, R3, R4, 1 ; /* 0x3f800000030a7423 */
/* 0x001fc80000000004 */
/*04a0*/ FFMA R12, R3, R10, R3 ; /* 0x0000000a030c7223 */
/* 0x000fc80000000003 */
/*04b0*/ FFMA R3, R7, R12, RZ ; /* 0x0000000c07037223 */
/* 0x000fc800000000ff */
/*04c0*/ FFMA R10, R4, R3, R7 ; /* 0x00000003040a7223 */
/* 0x000fc80000000007 */
/*04d0*/ FFMA R11, R12, R10, R3 ; /* 0x0000000a0c0b7223 */
/* 0x000fc80000000003 */
/*04e0*/ FFMA R7, R4, R11, R7 ; /* 0x0000000b04077223 */
/* 0x000fc80000000007 */
/*04f0*/ FFMA R3, R12, R7, R11 ; /* 0x000000070c037223 */
/* 0x000fca000000000b */
/*0500*/ SHF.R.U32.HI R4, RZ, 0x17, R3 ; /* 0x00000017ff047819 */
/* 0x000fc80000011603 */
/*0510*/ LOP3.LUT R4, R4, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff04047812 */
/* 0x000fca00078ec0ff */
/*0520*/ IMAD.IADD R8, R4, 0x1, R6 ; /* 0x0000000104087824 */
/* 0x000fca00078e0206 */
/*0530*/ IADD3 R4, R8, -0x1, RZ ; /* 0xffffffff08047810 */
/* 0x000fc80007ffe0ff */
/*0540*/ ISETP.GE.U32.AND P0, PT, R4, 0xfe, PT ; /* 0x000000fe0400780c */
/* 0x000fda0003f06070 */
/*0550*/ @!P0 BRA 0x760 ; /* 0x0000020000008947 */
/* 0x000fea0003800000 */
/*0560*/ ISETP.GT.AND P0, PT, R8, 0xfe, PT ; /* 0x000000fe0800780c */
/* 0x000fda0003f04270 */
/*0570*/ @P0 BRA 0x730 ; /* 0x000001b000000947 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.GE.AND P0, PT, R8, 0x1, PT ; /* 0x000000010800780c */
/* 0x000fda0003f06270 */
/*0590*/ @P0 BRA 0x770 ; /* 0x000001d000000947 */
/* 0x000fea0003800000 */
/*05a0*/ ISETP.GE.AND P0, PT, R8, -0x18, PT ; /* 0xffffffe80800780c */
/* 0x000fe40003f06270 */
/*05b0*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fd600078ec0ff */
/*05c0*/ @!P0 BRA 0x770 ; /* 0x000001a000008947 */
/* 0x000fea0003800000 */
/*05d0*/ FFMA.RZ R4, R12, R7.reuse, R11.reuse ; /* 0x000000070c047223 */
/* 0x180fe2000000c00b */
/*05e0*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f45270 */
/*05f0*/ FFMA.RM R5, R12, R7.reuse, R11.reuse ; /* 0x000000070c057223 */
/* 0x180fe2000000400b */
/*0600*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0610*/ LOP3.LUT R6, R4, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff04067812 */
/* 0x000fe200078ec0ff */
/*0620*/ FFMA.RP R4, R12, R7, R11 ; /* 0x000000070c047223 */
/* 0x000fe2000000800b */
/*0630*/ IADD3 R7, R8, 0x20, RZ ; /* 0x0000002008077810 */
/* 0x000fe20007ffe0ff */
/*0640*/ IMAD.MOV R8, RZ, RZ, -R8 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0a08 */
/*0650*/ LOP3.LUT R6, R6, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000006067812 */
/* 0x000fe400078efcff */
/*0660*/ FSETP.NEU.FTZ.AND P0, PT, R4, R5, PT ; /* 0x000000050400720b */
/* 0x000fc40003f1d000 */
/*0670*/ SHF.L.U32 R7, R6, R7, RZ ; /* 0x0000000706077219 */
/* 0x000fe400000006ff */
/*0680*/ SEL R5, R8, RZ, P2 ; /* 0x000000ff08057207 */
/* 0x000fe40001000000 */
/*0690*/ ISETP.NE.AND P1, PT, R7, RZ, P1 ; /* 0x000000ff0700720c */
/* 0x000fe40000f25270 */
/*06a0*/ SHF.R.U32.HI R5, RZ, R5, R6 ; /* 0x00000005ff057219 */
/* 0x000fe40000011606 */
/*06b0*/ PLOP3.LUT P0, PT, P0, P1, PT, 0xa8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703570 */
/*06c0*/ SHF.R.U32.HI R7, RZ, 0x1, R5 ; /* 0x00000001ff077819 */
/* 0x000fc40000011605 */
/*06d0*/ SEL R4, RZ, 0x1, !P0 ; /* 0x00000001ff047807 */
/* 0x000fc80004000000 */
/*06e0*/ LOP3.LUT R4, R4, 0x1, R7, 0xf8, !PT ; /* 0x0000000104047812 */
/* 0x000fc800078ef807 */
/*06f0*/ LOP3.LUT R4, R4, R5, RZ, 0xc0, !PT ; /* 0x0000000504047212 */
/* 0x000fca00078ec0ff */
/*0700*/ IMAD.IADD R4, R7, 0x1, R4 ; /* 0x0000000107047824 */
/* 0x000fca00078e0204 */
/*0710*/ LOP3.LUT R3, R4, R3, RZ, 0xfc, !PT ; /* 0x0000000304037212 */
/* 0x000fe200078efcff */
/*0720*/ BRA 0x770 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0730*/ LOP3.LUT R3, R3, 0x80000000, RZ, 0xc0, !PT ; /* 0x8000000003037812 */
/* 0x000fc800078ec0ff */
/*0740*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*0750*/ BRA 0x770 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD R3, R6, 0x800000, R3 ; /* 0x0080000006037824 */
/* 0x000fe400078e0203 */
/*0770*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0780*/ BRA 0x810 ; /* 0x0000008000007947 */
/* 0x000fea0003800000 */
/*0790*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fc800078e4807 */
/*07a0*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xfc, !PT ; /* 0x7f80000003037812 */
/* 0x000fe200078efcff */
/*07b0*/ BRA 0x810 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*07c0*/ LOP3.LUT R3, R8, 0x80000000, R7, 0x48, !PT ; /* 0x8000000008037812 */
/* 0x000fe200078e4807 */
/*07d0*/ BRA 0x810 ; /* 0x0000003000007947 */
/* 0x000fea0003800000 */
/*07e0*/ MUFU.RSQ R3, -QNAN ; /* 0xffc0000000037908 */
/* 0x000e220000001400 */
/*07f0*/ BRA 0x810 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0800*/ FADD.FTZ R3, R4, R3 ; /* 0x0000000304037221 */
/* 0x000fe40000010000 */
/*0810*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0820*/ IMAD.MOV.U32 R6, RZ, RZ, R3 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0003 */
/*0830*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0840*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff7b002007950 */
/* 0x000fea0003c3ffff */
/*0850*/ BRA 0x850; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0880*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0890*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*08f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z10tex_kernelP13__hip_textureiPf
.globl _Z10tex_kernelP13__hip_textureiPf
.p2align 8
.type _Z10tex_kernelP13__hip_textureiPf,@function
_Z10tex_kernelP13__hip_textureiPf:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x24
s_load_b32 s2, s[0:1], 0x8
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
s_mov_b32 s3, exec_lo
v_cmpx_gt_u32_e64 s2, v1
s_cbranch_execz .LBB0_2
v_cvt_f32_u32_e32 v0, v1
v_cvt_f32_i32_e32 v2, s2
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b64 s[12:13], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x2
s_load_b32 s0, s[2:3], 0x30
s_load_b32 s1, s[2:3], 0x38
s_load_b32 s4, s[2:3], 0x28
v_div_scale_f32 v3, null, v2, v2, v0
v_div_scale_f32 v6, vcc_lo, v0, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_waitcnt lgkmcnt(0)
s_bitcmp0_b32 s1, 20
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fmas_f32 v3, v3, v4, v5
v_cvt_f32_u32_e32 v4, s4
s_cselect_b32 vcc_lo, -1, 0
s_bitcmp0_b32 s0, 15
s_cselect_b32 s0, -1, 0
v_div_fixup_f32 v0, v3, v2, v0
v_cndmask_b32_e64 v2, 1.0, v4, s0
s_clause 0x1
s_load_b128 s[8:11], s[2:3], 0x30
s_load_b256 s[0:7], s[2:3], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
v_mul_f32_e32 v2, v0, v2
v_floor_f32_e32 v2, v2
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
image_sample_lz v3, v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_1D
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s12, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v3, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z10tex_kernelP13__hip_textureiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z10tex_kernelP13__hip_textureiPf, .Lfunc_end0-_Z10tex_kernelP13__hip_textureiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z10tex_kernelP13__hip_textureiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z10tex_kernelP13__hip_textureiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ea293_00000000-6_tex_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z10tex_kernelyiPfyiPf
.type _Z32__device_stub__Z10tex_kernelyiPfyiPf, @function
_Z32__device_stub__Z10tex_kernelyiPfyiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z10tex_kernelyiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z32__device_stub__Z10tex_kernelyiPfyiPf, .-_Z32__device_stub__Z10tex_kernelyiPfyiPf
.globl _Z10tex_kernelyiPf
.type _Z10tex_kernelyiPf, @function
_Z10tex_kernelyiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z10tex_kernelyiPfyiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z10tex_kernelyiPf, .-_Z10tex_kernelyiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10tex_kernelyiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10tex_kernelyiPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "tex_kernel.hip"
.globl _Z25__device_stub__tex_kernelP13__hip_textureiPf # -- Begin function _Z25__device_stub__tex_kernelP13__hip_textureiPf
.p2align 4, 0x90
.type _Z25__device_stub__tex_kernelP13__hip_textureiPf,@function
_Z25__device_stub__tex_kernelP13__hip_textureiPf: # @_Z25__device_stub__tex_kernelP13__hip_textureiPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10tex_kernelP13__hip_textureiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z25__device_stub__tex_kernelP13__hip_textureiPf, .Lfunc_end0-_Z25__device_stub__tex_kernelP13__hip_textureiPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10tex_kernelP13__hip_textureiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10tex_kernelP13__hip_textureiPf,@object # @_Z10tex_kernelP13__hip_textureiPf
.section .rodata,"a",@progbits
.globl _Z10tex_kernelP13__hip_textureiPf
.p2align 3, 0x0
_Z10tex_kernelP13__hip_textureiPf:
.quad _Z25__device_stub__tex_kernelP13__hip_textureiPf
.size _Z10tex_kernelP13__hip_textureiPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10tex_kernelP13__hip_textureiPf"
.size .L__unnamed_1, 34
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__tex_kernelP13__hip_textureiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10tex_kernelP13__hip_textureiPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <assert.h>
#include <stdio.h>
#include <algorithm>
#include <stdlib.h>
#include<iostream>
#include "cuda.h"
#define NUM (256*1024*1024)
#define THREADS_PER_BLOCK_X 384
#define THREADS_PER_BLOCK_Y 1
#define THREADS_PER_BLOCK_Z 1
#define PROTECT_BITS (0xFFFF0000)
__global__ void
test_kernel( int* __restrict__ buf, int protectBits, int shrinkBits)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int address;
address = (x & protectBits) | (x & shrinkBits);
buf[address] = x;
//printf("address[%d] tid:%d \n ",address,x);
}
using namespace std;
int main() {
int* hostA;
int* deviceA;
cudaEvent_t start, stop;
cudaEventCreate (&start);
cudaEventCreate (&stop);
float eventMs = 1.0f;
hostA = (int*)malloc(NUM * sizeof(int));
cudaMalloc((void**)& deviceA, NUM * sizeof(int));
cudaMemcpy(deviceA, hostA, NUM * sizeof(int), cudaMemcpyHostToDevice);
test_kernel<<<dim3(1,1,1),dim3(1,1,1),0,0>>>( deviceA , 0x0, 0x0);
for (int i = 16; i < 64 * 1024; i = i << 1) {
cudaEventRecord(start, 0);
test_kernel<<<dim3(NUM/THREADS_PER_BLOCK_X, 1, 1),dim3(THREADS_PER_BLOCK_X, 1, 1),0,0>>>(deviceA,PROTECT_BITS,i - 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&eventMs, start, stop);
printf("elapsed time:%f\n", eventMs);
int bandwidth = (double)NUM * sizeof(int) / 1024 / 1024 / 1024 / (eventMs / 1000);
printf("Shrink Size in Bytes[%ld], bandwidth %d (GB/S)\n", i*sizeof(int), bandwidth);
}
cudaFree(deviceA);
free(hostA);
return 0;
} | code for sm_80
Function : _Z11test_kernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R2, c[0x0][0x16c] ; /* 0x00005b0000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0070*/ LOP3.LUT R2, R5, c[0x0][0x168], R2, 0xe0, !PT ; /* 0x00005a0005027a12 */
/* 0x000fca00078ee002 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <assert.h>
#include <stdio.h>
#include <algorithm>
#include <stdlib.h>
#include<iostream>
#include "cuda.h"
#define NUM (256*1024*1024)
#define THREADS_PER_BLOCK_X 384
#define THREADS_PER_BLOCK_Y 1
#define THREADS_PER_BLOCK_Z 1
#define PROTECT_BITS (0xFFFF0000)
__global__ void
test_kernel( int* __restrict__ buf, int protectBits, int shrinkBits)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int address;
address = (x & protectBits) | (x & shrinkBits);
buf[address] = x;
//printf("address[%d] tid:%d \n ",address,x);
}
using namespace std;
int main() {
int* hostA;
int* deviceA;
cudaEvent_t start, stop;
cudaEventCreate (&start);
cudaEventCreate (&stop);
float eventMs = 1.0f;
hostA = (int*)malloc(NUM * sizeof(int));
cudaMalloc((void**)& deviceA, NUM * sizeof(int));
cudaMemcpy(deviceA, hostA, NUM * sizeof(int), cudaMemcpyHostToDevice);
test_kernel<<<dim3(1,1,1),dim3(1,1,1),0,0>>>( deviceA , 0x0, 0x0);
for (int i = 16; i < 64 * 1024; i = i << 1) {
cudaEventRecord(start, 0);
test_kernel<<<dim3(NUM/THREADS_PER_BLOCK_X, 1, 1),dim3(THREADS_PER_BLOCK_X, 1, 1),0,0>>>(deviceA,PROTECT_BITS,i - 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&eventMs, start, stop);
printf("elapsed time:%f\n", eventMs);
int bandwidth = (double)NUM * sizeof(int) / 1024 / 1024 / 1024 / (eventMs / 1000);
printf("Shrink Size in Bytes[%ld], bandwidth %d (GB/S)\n", i*sizeof(int), bandwidth);
}
cudaFree(deviceA);
free(hostA);
return 0;
} | .file "tmpxft_00073749_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3926:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3926:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11test_kernelPiiiPiii
.type _Z33__device_stub__Z11test_kernelPiiiPiii, @function
_Z33__device_stub__Z11test_kernelPiiiPiii:
.LFB3948:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11test_kernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3948:
.size _Z33__device_stub__Z11test_kernelPiiiPiii, .-_Z33__device_stub__Z11test_kernelPiiiPiii
.globl _Z11test_kernelPiii
.type _Z11test_kernelPiii, @function
_Z11test_kernelPiii:
.LFB3949:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11test_kernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z11test_kernelPiii, .-_Z11test_kernelPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "elapsed time:%f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Shrink Size in Bytes[%ld], bandwidth %d (GB/S)\n"
.text
.globl main
.type main, @function
main:
.LFB3923:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x3f800000, 4(%rsp)
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
movl $12, %ebp
movl $16, %ebx
leaq .LC1(%rip), %r13
leaq .LC4(%rip), %r12
jmp .L14
.L18:
movl $0, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z11test_kernelPiiiPiii
jmp .L12
.L13:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 4(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC3(%rip), %xmm1
divsd %xmm0, %xmm1
cvttsd2sil %xmm1, %ecx
movslq %ebx, %rdx
salq $2, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl %ebx, %ebx
subl $1, %ebp
je .L19
.L14:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $384, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $699050, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
leal -1(%rbx), %edx
movl $-65536, %esi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z11test_kernelPiiiPiii
jmp .L13
.L19:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z11test_kernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3951:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11test_kernelPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3951:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <assert.h>
#include <stdio.h>
#include <algorithm>
#include <stdlib.h>
#include<iostream>
#include "cuda.h"
#define NUM (256*1024*1024)
#define THREADS_PER_BLOCK_X 384
#define THREADS_PER_BLOCK_Y 1
#define THREADS_PER_BLOCK_Z 1
#define PROTECT_BITS (0xFFFF0000)
__global__ void
test_kernel( int* __restrict__ buf, int protectBits, int shrinkBits)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int address;
address = (x & protectBits) | (x & shrinkBits);
buf[address] = x;
//printf("address[%d] tid:%d \n ",address,x);
}
using namespace std;
int main() {
int* hostA;
int* deviceA;
cudaEvent_t start, stop;
cudaEventCreate (&start);
cudaEventCreate (&stop);
float eventMs = 1.0f;
hostA = (int*)malloc(NUM * sizeof(int));
cudaMalloc((void**)& deviceA, NUM * sizeof(int));
cudaMemcpy(deviceA, hostA, NUM * sizeof(int), cudaMemcpyHostToDevice);
test_kernel<<<dim3(1,1,1),dim3(1,1,1),0,0>>>( deviceA , 0x0, 0x0);
for (int i = 16; i < 64 * 1024; i = i << 1) {
cudaEventRecord(start, 0);
test_kernel<<<dim3(NUM/THREADS_PER_BLOCK_X, 1, 1),dim3(THREADS_PER_BLOCK_X, 1, 1),0,0>>>(deviceA,PROTECT_BITS,i - 1);
cudaEventRecord(stop, 0);
cudaEventSynchronize(stop);
cudaEventElapsedTime(&eventMs, start, stop);
printf("elapsed time:%f\n", eventMs);
int bandwidth = (double)NUM * sizeof(int) / 1024 / 1024 / 1024 / (eventMs / 1000);
printf("Shrink Size in Bytes[%ld], bandwidth %d (GB/S)\n", i*sizeof(int), bandwidth);
}
cudaFree(deviceA);
free(hostA);
return 0;
} | #include <assert.h>
#include <stdio.h>
#include <algorithm>
#include <stdlib.h>
#include<iostream>
#include "hip/hip_runtime.h"
#define NUM (256*1024*1024)
#define THREADS_PER_BLOCK_X 384
#define THREADS_PER_BLOCK_Y 1
#define THREADS_PER_BLOCK_Z 1
#define PROTECT_BITS (0xFFFF0000)
__global__ void
test_kernel( int* __restrict__ buf, int protectBits, int shrinkBits)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int address;
address = (x & protectBits) | (x & shrinkBits);
buf[address] = x;
//printf("address[%d] tid:%d \n ",address,x);
}
using namespace std;
int main() {
int* hostA;
int* deviceA;
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
float eventMs = 1.0f;
hostA = (int*)malloc(NUM * sizeof(int));
hipMalloc((void**)& deviceA, NUM * sizeof(int));
hipMemcpy(deviceA, hostA, NUM * sizeof(int), hipMemcpyHostToDevice);
test_kernel<<<dim3(1,1,1),dim3(1,1,1),0,0>>>( deviceA , 0x0, 0x0);
for (int i = 16; i < 64 * 1024; i = i << 1) {
hipEventRecord(start, 0);
test_kernel<<<dim3(NUM/THREADS_PER_BLOCK_X, 1, 1),dim3(THREADS_PER_BLOCK_X, 1, 1),0,0>>>(deviceA,PROTECT_BITS,i - 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&eventMs, start, stop);
printf("elapsed time:%f\n", eventMs);
int bandwidth = (double)NUM * sizeof(int) / 1024 / 1024 / 1024 / (eventMs / 1000);
printf("Shrink Size in Bytes[%ld], bandwidth %d (GB/S)\n", i*sizeof(int), bandwidth);
}
hipFree(deviceA);
free(hostA);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <assert.h>
#include <stdio.h>
#include <algorithm>
#include <stdlib.h>
#include<iostream>
#include "hip/hip_runtime.h"
#define NUM (256*1024*1024)
#define THREADS_PER_BLOCK_X 384
#define THREADS_PER_BLOCK_Y 1
#define THREADS_PER_BLOCK_Z 1
#define PROTECT_BITS (0xFFFF0000)
__global__ void
test_kernel( int* __restrict__ buf, int protectBits, int shrinkBits)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int address;
address = (x & protectBits) | (x & shrinkBits);
buf[address] = x;
//printf("address[%d] tid:%d \n ",address,x);
}
using namespace std;
int main() {
int* hostA;
int* deviceA;
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
float eventMs = 1.0f;
hostA = (int*)malloc(NUM * sizeof(int));
hipMalloc((void**)& deviceA, NUM * sizeof(int));
hipMemcpy(deviceA, hostA, NUM * sizeof(int), hipMemcpyHostToDevice);
test_kernel<<<dim3(1,1,1),dim3(1,1,1),0,0>>>( deviceA , 0x0, 0x0);
for (int i = 16; i < 64 * 1024; i = i << 1) {
hipEventRecord(start, 0);
test_kernel<<<dim3(NUM/THREADS_PER_BLOCK_X, 1, 1),dim3(THREADS_PER_BLOCK_X, 1, 1),0,0>>>(deviceA,PROTECT_BITS,i - 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&eventMs, start, stop);
printf("elapsed time:%f\n", eventMs);
int bandwidth = (double)NUM * sizeof(int) / 1024 / 1024 / 1024 / (eventMs / 1000);
printf("Shrink Size in Bytes[%ld], bandwidth %d (GB/S)\n", i*sizeof(int), bandwidth);
}
hipFree(deviceA);
free(hostA);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11test_kernelPiii
.globl _Z11test_kernelPiii
.p2align 8
.type _Z11test_kernelPiii,@function
_Z11test_kernelPiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_or_b32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, s2, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11test_kernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11test_kernelPiii, .Lfunc_end0-_Z11test_kernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: write_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11test_kernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11test_kernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <assert.h>
#include <stdio.h>
#include <algorithm>
#include <stdlib.h>
#include<iostream>
#include "hip/hip_runtime.h"
#define NUM (256*1024*1024)
#define THREADS_PER_BLOCK_X 384
#define THREADS_PER_BLOCK_Y 1
#define THREADS_PER_BLOCK_Z 1
#define PROTECT_BITS (0xFFFF0000)
__global__ void
test_kernel( int* __restrict__ buf, int protectBits, int shrinkBits)
{
int x = blockDim.x * blockIdx.x + threadIdx.x;
int address;
address = (x & protectBits) | (x & shrinkBits);
buf[address] = x;
//printf("address[%d] tid:%d \n ",address,x);
}
using namespace std;
int main() {
int* hostA;
int* deviceA;
hipEvent_t start, stop;
hipEventCreate (&start);
hipEventCreate (&stop);
float eventMs = 1.0f;
hostA = (int*)malloc(NUM * sizeof(int));
hipMalloc((void**)& deviceA, NUM * sizeof(int));
hipMemcpy(deviceA, hostA, NUM * sizeof(int), hipMemcpyHostToDevice);
test_kernel<<<dim3(1,1,1),dim3(1,1,1),0,0>>>( deviceA , 0x0, 0x0);
for (int i = 16; i < 64 * 1024; i = i << 1) {
hipEventRecord(start, 0);
test_kernel<<<dim3(NUM/THREADS_PER_BLOCK_X, 1, 1),dim3(THREADS_PER_BLOCK_X, 1, 1),0,0>>>(deviceA,PROTECT_BITS,i - 1);
hipEventRecord(stop, 0);
hipEventSynchronize(stop);
hipEventElapsedTime(&eventMs, start, stop);
printf("elapsed time:%f\n", eventMs);
int bandwidth = (double)NUM * sizeof(int) / 1024 / 1024 / 1024 / (eventMs / 1000);
printf("Shrink Size in Bytes[%ld], bandwidth %d (GB/S)\n", i*sizeof(int), bandwidth);
}
hipFree(deviceA);
free(hostA);
return 0;
} | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__test_kernelPiii # -- Begin function _Z26__device_stub__test_kernelPiii
.p2align 4, 0x90
.type _Z26__device_stub__test_kernelPiii,@function
_Z26__device_stub__test_kernelPiii: # @_Z26__device_stub__test_kernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11test_kernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__test_kernelPiii, .Lfunc_end0-_Z26__device_stub__test_kernelPiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x447a0000 # float 1000
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $1065353216, 4(%rsp) # imm = 0x3F800000
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movq 16(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, 128(%rsp) # 8-byte Spill
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movl $0, 12(%rsp)
movl $0, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11test_kernelPiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $16, %ebp
leaq 383(%rbx), %r15
addq $699049, %rbx # imm = 0xAAAA9
leaq 32(%rsp), %r14
leaq 96(%rsp), %r12
leaq 4(%rsp), %r13
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rsi
movq 24(%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
cvttsd2si %xmm1, %edx
movslq %ebp, %rsi
shlq $2, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addl %ebp, %ebp
cmpl $65536, %ebp # imm = 0x10000
jge .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 16(%rsp), %rax
leal -1(%rbp), %ecx
movq %rax, 80(%rsp)
movl $-65536, 12(%rsp) # imm = 0xFFFF0000
movl %ecx, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z11test_kernelPiii, %edi
movq %r12, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movq 16(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11test_kernelPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11test_kernelPiii,@object # @_Z11test_kernelPiii
.section .rodata,"a",@progbits
.globl _Z11test_kernelPiii
.p2align 3, 0x0
_Z11test_kernelPiii:
.quad _Z26__device_stub__test_kernelPiii
.size _Z11test_kernelPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "elapsed time:%f\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Shrink Size in Bytes[%ld], bandwidth %d (GB/S)\n"
.size .L.str.1, 48
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11test_kernelPiii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__test_kernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11test_kernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11test_kernelPiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0020*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0030*/ MOV R2, c[0x0][0x16c] ; /* 0x00005b0000027a02 */
/* 0x000fe20000000f00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0050*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R5, R5, c[0x0][0x0], R0 ; /* 0x0000000005057a24 */
/* 0x001fca00078e0200 */
/*0070*/ LOP3.LUT R2, R5, c[0x0][0x168], R2, 0xe0, !PT ; /* 0x00005a0005027a12 */
/* 0x000fca00078ee002 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11test_kernelPiii
.globl _Z11test_kernelPiii
.p2align 8
.type _Z11test_kernelPiii,@function
_Z11test_kernelPiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_or_b32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v2, s2, v1
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11test_kernelPiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11test_kernelPiii, .Lfunc_end0-_Z11test_kernelPiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .actual_access: write_only
.address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11test_kernelPiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11test_kernelPiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00073749_00000000-6_test.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3926:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3926:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z11test_kernelPiiiPiii
.type _Z33__device_stub__Z11test_kernelPiiiPiii, @function
_Z33__device_stub__Z11test_kernelPiiiPiii:
.LFB3948:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11test_kernelPiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3948:
.size _Z33__device_stub__Z11test_kernelPiiiPiii, .-_Z33__device_stub__Z11test_kernelPiiiPiii
.globl _Z11test_kernelPiii
.type _Z11test_kernelPiii, @function
_Z11test_kernelPiii:
.LFB3949:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z11test_kernelPiiiPiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3949:
.size _Z11test_kernelPiii, .-_Z11test_kernelPiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "elapsed time:%f\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC4:
.string "Shrink Size in Bytes[%ld], bandwidth %d (GB/S)\n"
.text
.globl main
.type main, @function
main:
.LFB3923:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
movl $0x3f800000, 4(%rsp)
movl $1073741824, %edi
call malloc@PLT
movq %rax, %r14
leaq 8(%rsp), %rdi
movl $1073741824, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $1073741824, %edx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L12:
movl $12, %ebp
movl $16, %ebx
leaq .LC1(%rip), %r13
leaq .LC4(%rip), %r12
jmp .L14
.L18:
movl $0, %edx
movl $0, %esi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z11test_kernelPiiiPiii
jmp .L12
.L13:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq 4(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
pxor %xmm0, %xmm0
cvtss2sd 4(%rsp), %xmm0
movq %r13, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movss 4(%rsp), %xmm0
divss .LC2(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LC3(%rip), %xmm1
divsd %xmm0, %xmm1
cvttsd2sil %xmm1, %ecx
movslq %ebx, %rdx
salq $2, %rdx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl %ebx, %ebx
subl $1, %ebp
je .L19
.L14:
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
movl $384, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $699050, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L13
leal -1(%rbx), %edx
movl $-65536, %esi
movq 8(%rsp), %rdi
call _Z33__device_stub__Z11test_kernelPiiiPiii
jmp .L13
.L19:
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L20:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3923:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z11test_kernelPiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3951:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z11test_kernelPiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3951:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long 1148846080
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC3:
.long 0
.long 1072693248
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z26__device_stub__test_kernelPiii # -- Begin function _Z26__device_stub__test_kernelPiii
.p2align 4, 0x90
.type _Z26__device_stub__test_kernelPiii,@function
_Z26__device_stub__test_kernelPiii: # @_Z26__device_stub__test_kernelPiii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z11test_kernelPiii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z26__device_stub__test_kernelPiii, .Lfunc_end0-_Z26__device_stub__test_kernelPiii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x447a0000 # float 1000
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ff0000000000000 # double 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movabsq $4294967297, %rbx # imm = 0x100000001
leaq 88(%rsp), %rdi
callq hipEventCreate
leaq 24(%rsp), %rdi
callq hipEventCreate
movl $1065353216, 4(%rsp) # imm = 0x3F800000
movl $1073741824, %edi # imm = 0x40000000
callq malloc
movq %rax, %r14
leaq 16(%rsp), %rdi
movl $1073741824, %esi # imm = 0x40000000
callq hipMalloc
movq 16(%rsp), %rdi
movl $1073741824, %edx # imm = 0x40000000
movq %r14, 128(%rsp) # 8-byte Spill
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 16(%rsp), %rax
movq %rax, 80(%rsp)
movl $0, 12(%rsp)
movl $0, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z11test_kernelPiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $16, %ebp
leaq 383(%rbx), %r15
addq $699049, %rbx # imm = 0xAAAA9
leaq 32(%rsp), %r14
leaq 96(%rsp), %r12
leaq 4(%rsp), %r13
jmp .LBB1_3
.p2align 4, 0x90
.LBB1_5: # in Loop: Header=BB1_3 Depth=1
movq 24(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq 24(%rsp), %rdi
callq hipEventSynchronize
movq 88(%rsp), %rsi
movq 24(%rsp), %rdx
movq %r13, %rdi
callq hipEventElapsedTime
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
movss 4(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
divss .LCPI1_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
divsd %xmm0, %xmm1
cvttsd2si %xmm1, %edx
movslq %ebp, %rsi
shlq $2, %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
addl %ebp, %ebp
cmpl $65536, %ebp # imm = 0x10000
jge .LBB1_6
.LBB1_3: # =>This Inner Loop Header: Depth=1
movq 88(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
movq %rbx, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4: # in Loop: Header=BB1_3 Depth=1
movq 16(%rsp), %rax
leal -1(%rbp), %ecx
movq %rax, 80(%rsp)
movl $-65536, 12(%rsp) # imm = 0xFFFF0000
movl %ecx, 8(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
movq %r14, %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
movl $_Z11test_kernelPiii, %edi
movq %r12, %r9
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_5
.LBB1_6:
movq 16(%rsp), %rdi
callq hipFree
movq 128(%rsp), %rdi # 8-byte Reload
callq free
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11test_kernelPiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11test_kernelPiii,@object # @_Z11test_kernelPiii
.section .rodata,"a",@progbits
.globl _Z11test_kernelPiii
.p2align 3, 0x0
_Z11test_kernelPiii:
.quad _Z26__device_stub__test_kernelPiii
.size _Z11test_kernelPiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "elapsed time:%f\n"
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Shrink Size in Bytes[%ld], bandwidth %d (GB/S)\n"
.size .L.str.1, 48
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z11test_kernelPiii"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__test_kernelPiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11test_kernelPiii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void convolution_global_memory_gray(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = ( mask_size-1 )/2;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (j >= paddingSize) && (j < paddedW-paddingSize) && (i >= paddingSize) && (i<paddedH-paddingSize)) {
unsigned int oPixelPos = (j - paddingSize ) * cols + (i -paddingSize);
for(int k = -paddingSize; k <= paddingSize; k++){
for(int l = -paddingSize; l<=paddingSize; l++){
unsigned int iPixelPos = (j+l)*cols+(i+k);
unsigned int coefPos = (k + paddingSize) * mask_size + (l+ paddingSize);
g[oPixelPos] += N[iPixelPos] * M[coefPos];
}
}
}
} | code for sm_80
Function : _Z30convolution_global_memory_grayPhPfS_mmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe400078e00ff */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IADD3 R2, P0, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007f1e0ff */
/*0060*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e640000002500 */
/*0070*/ IADD3.X R7, R7, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630007077a10 */
/* 0x000fc400007fe4ff */
/*0080*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe200078e0203 */
/*00a0*/ SHF.R.U64 R3, R2.reuse, 0x1, R7 ; /* 0x0000000102037819 */
/* 0x040fe40000001207 */
/*00b0*/ LOP3.LUT R2, R2, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe02027812 */
/* 0x000fc600078ec0ff */
/*00c0*/ IMAD.IADD R4, R0, 0x1, R3 ; /* 0x0000000100047824 */
/* 0x000fe200078e0203 */
/*00d0*/ IADD3 R7, -R3, c[0x0][0x180], R2 ; /* 0x0000600003077a10 */
/* 0x000fe20007ffe102 */
/*00e0*/ IMAD R5, R5, c[0x0][0x0], R6 ; /* 0x0000000005057a24 */
/* 0x002fc600078e0206 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R4.reuse, R7, PT ; /* 0x000000070400720c */
/* 0x040fe20003f06070 */
/*0100*/ IMAD.IADD R6, R5, 0x1, R3 ; /* 0x0000000105067824 */
/* 0x000fe200078e0203 */
/*0110*/ IADD3 R7, -R3, c[0x0][0x178], R2 ; /* 0x00005e0003077a10 */
/* 0x000fe40007ffe102 */
/*0120*/ ISETP.LT.OR P0, PT, R4, R3, P0 ; /* 0x000000030400720c */
/* 0x000fc80000701670 */
/*0130*/ ISETP.LT.OR P0, PT, R6, R3, P0 ; /* 0x000000030600720c */
/* 0x000fc80000701670 */
/*0140*/ ISETP.GE.U32.OR P0, PT, R6, R7, P0 ; /* 0x000000070600720c */
/* 0x000fda0000706470 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a03 */
/*0170*/ ISETP.GT.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f04270 */
/*0180*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0190*/ IMAD R5, R0, c[0x0][0x178], R5 ; /* 0x00005e0000057a24 */
/* 0x000fe200078e0205 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*01b0*/ IADD3 R14, P0, R5, c[0x0][0x170], RZ ; /* 0x00005c00050e7a10 */
/* 0x000fca0007f1e0ff */
/*01c0*/ IMAD.X R15, RZ, RZ, c[0x0][0x174], P0 ; /* 0x00005d00ff0f7624 */
/* 0x000fca00000e06ff */
/*01d0*/ LDG.E.U8 R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000162000c1e1100 */
/*01e0*/ LOP3.LUT R20, R2, 0x1, RZ, 0xfc, !PT ; /* 0x0000000102147812 */
/* 0x000fe400078efcff */
/*01f0*/ IADD3 R8, -R3.reuse, 0x1, RZ ; /* 0x0000000103087810 */
/* 0x040fe40007ffe1ff */
/*0200*/ IADD3 R9, -R3.reuse, 0x3, RZ ; /* 0x0000000303097810 */
/* 0x040fe40007ffe1ff */
/*0210*/ IADD3 R10, R3, 0x3, RZ ; /* 0x00000003030a7810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R11, R4.reuse, 0x3, RZ ; /* 0x00000003040b7810 */
/* 0x040fe40007ffe0ff */
/*0230*/ IADD3 R12, R4, 0x2, RZ ; /* 0x00000002040c7810 */
/* 0x000fc40007ffe0ff */
/*0240*/ IADD3 R13, R4, 0x1, RZ ; /* 0x00000001040d7810 */
/* 0x000fe40007ffe0ff */
/*0250*/ LOP3.LUT R20, R20, 0x3, RZ, 0xc0, !PT ; /* 0x0000000314147812 */
/* 0x001fe400078ec0ff */
/*0260*/ IMAD.IADD R25, R6, 0x1, R7 ; /* 0x0000000106197824 */
/* 0x000fc800078e0207 */
/*0270*/ IMAD R5, R0, c[0x0][0x178], R25 ; /* 0x00005e0000057a24 */
/* 0x000fca00078e0219 */
/*0280*/ IADD3 R18, P0, R5, c[0x0][0x160], RZ ; /* 0x0000580005127a10 */
/* 0x000fca0007f1e0ff */
/*0290*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff137624 */
/* 0x001fe400000e06ff */
/*02a0*/ IMAD.IADD R29, R7, 0x1, R3 ; /* 0x00000001071d7824 */
/* 0x000fc800078e0203 */
/*02b0*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x0000a2000c1e1100 */
/*02c0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ; /* 0x00000004ff167424 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD R29, R29, c[0x0][0x188], RZ ; /* 0x000062001d1d7a24 */
/* 0x000fc800078e02ff */
/*02e0*/ IMAD.WIDE.U32 R16, R29, R22, c[0x0][0x168] ; /* 0x00005a001d107625 */
/* 0x000fcc00078e0016 */
/*02f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee2000c1e1900 */
/*0300*/ LOP3.LUT R23, R26, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1a177812 */
/* 0x020fe200078ec0ff */
/*0310*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x001fe200078e0008 */
/*0320*/ ISETP.NE.AND P2, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe40003f45270 */
/*0330*/ ISETP.GE.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fe40003f06270 */
/*0340*/ I2F.U16 R23, R23 ; /* 0x0000001700177306 */
/* 0x000fe20000101000 */
/*0350*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fce0003f26070 */
/*0360*/ I2F.U16 R21, R19 ; /* 0x0000001300157306 */
/* 0x004ee40000101000 */
/*0370*/ FFMA R21, R21, R16, R23 ; /* 0x0000001015157223 */
/* 0x008fcc0000000017 */
/*0380*/ F2I.U32.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e24000020f000 */
/*0390*/ STG.E.U8 [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0011e2000c101104 */
/*03a0*/ PRMT R26, R21, 0x7610, R26 ; /* 0x00007610151a7816 */
/* 0x000fe2000000001a */
/*03b0*/ @!P2 BRA 0x580 ; /* 0x000001c00000a947 */
/* 0x000fea0003800000 */
/*03c0*/ IADD3 R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a10 */
/* 0x000fc80007ffe0ff */
/*03d0*/ IADD3 R16, P2, R5, c[0x0][0x160], RZ ; /* 0x0000580005107a10 */
/* 0x000fca0007f5e0ff */
/*03e0*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fca00010e06ff */
/*03f0*/ LDG.E.U8 R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0010a2000c1e1100 */
/*0400*/ IADD3 R19, R29, 0x1, RZ ; /* 0x000000011d137810 */
/* 0x000fca0007ffe0ff */
/*0410*/ IMAD.WIDE.U32 R18, R19, R22, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fcc00078e0016 */
/*0420*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee2000c1e1900 */
/*0430*/ LOP3.LUT R23, R26, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1a177812 */
/* 0x000fe400078ec0ff */
/*0440*/ IADD3 R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a10 */
/* 0x000fc80007ffe0ff */
/*0450*/ I2F.U16 R23, R23 ; /* 0x0000001700177306 */
/* 0x000fe20000101000 */
/*0460*/ IADD3 R26, P2, R5, c[0x0][0x160], RZ ; /* 0x00005800051a7a10 */
/* 0x000fca0007f5e0ff */
/*0470*/ IMAD.X R27, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff1b7624 */
/* 0x000fe200010e06ff */
/*0480*/ IADD3 R17, R29, 0x2, RZ ; /* 0x000000021d117810 */
/* 0x001fca0007ffe0ff */
/*0490*/ IMAD.WIDE.U32 R16, R17, R22, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fe200078e0016 */
/*04a0*/ I2F.U16 R21, R21 ; /* 0x0000001500157306 */
/* 0x004ee60000101000 */
/*04b0*/ FFMA R24, R21, R18, R23 ; /* 0x0000001215187223 */
/* 0x008fcc0000000017 */
/*04c0*/ F2I.U32.TRUNC.NTZ R24, R24 ; /* 0x0000001800187305 */
/* 0x000e24000020f000 */
/*04d0*/ STG.E.U8 [R14.64], R24 ; /* 0x000000180e007986 */
/* 0x0011e8000c101104 */
/*04e0*/ LDG.E.U8 R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000ea8000c1e1100 */
/*04f0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee2000c1e1900 */
/*0500*/ LOP3.LUT R5, R24, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff18057812 */
/* 0x000fcc00078ec0ff */
/*0510*/ I2F.U16 R5, R5 ; /* 0x0000000500057306 */
/* 0x000ff00000101000 */
/*0520*/ I2F.U16 R18, R27 ; /* 0x0000001b00127306 */
/* 0x004ee40000101000 */
/*0530*/ FFMA R19, R18, R17, R5 ; /* 0x0000001112137223 */
/* 0x008fc40000000005 */
/*0540*/ IMAD.MOV.U32 R18, RZ, RZ, R9 ; /* 0x000000ffff127224 */
/* 0x000fc800078e0009 */
/*0550*/ F2I.U32.TRUNC.NTZ R19, R19 ; /* 0x0000001300137305 */
/* 0x000e64000020f000 */
/*0560*/ STG.E.U8 [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0021e2000c101104 */
/*0570*/ PRMT R26, R19, 0x7610, R26 ; /* 0x00007610131a7816 */
/* 0x000fca000000001a */
/*0580*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0590*/ @!P1 BRA 0x9e0 ; /* 0x0000044000009947 */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.IADD R16, R11, 0x1, R18.reuse ; /* 0x000000010b107824 */
/* 0x100fe200078e0212 */
/*05b0*/ IADD3 R27, R29.reuse, R10, R18.reuse ; /* 0x0000000a1d1b7210 */
/* 0x140fe20007ffe012 */
/*05c0*/ IMAD.IADD R24, R12, 0x1, R18.reuse ; /* 0x000000010c187824 */
/* 0x101fe200078e0212 */
/*05d0*/ IADD3 R29, R29, R3, R18.reuse ; /* 0x000000031d1d7210 */
/* 0x100fe20007ffe012 */
/*05e0*/ IMAD.IADD R28, R13, 0x1, R18.reuse ; /* 0x000000010d1c7824 */
/* 0x100fe400078e0212 */
/*05f0*/ IMAD.IADD R17, R4, 0x1, R18 ; /* 0x0000000104117824 */
/* 0x000fc400078e0212 */
/*0600*/ IMAD R5, R16, c[0x0][0x178], R25.reuse ; /* 0x00005e0010057a24 */
/* 0x100fe400078e0219 */
/*0610*/ IMAD R21, R24, c[0x0][0x178], R25.reuse ; /* 0x00005e0018157a24 */
/* 0x100fe200078e0219 */
/*0620*/ IADD3 R24, R18, -0x1, RZ ; /* 0xffffffff12187810 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD R23, R28, c[0x0][0x178], R25.reuse ; /* 0x00005e001c177a24 */
/* 0x100fe400078e0219 */
/*0640*/ IMAD R25, R17, c[0x0][0x178], R25 ; /* 0x00005e0011197a24 */
/* 0x000fca00078e0219 */
/*0650*/ IADD3 R18, P1, R25, c[0x0][0x160], RZ ; /* 0x0000580019127a10 */
/* 0x000fca0007f3e0ff */
/*0660*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff137624 */
/* 0x000fca00008e06ff */
/*0670*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0010a2000c1e1100 */
/*0680*/ IMAD.WIDE.U32 R28, R29, R22, c[0x0][0x168] ; /* 0x00005a001d1c7625 */
/* 0x000fcc00078e0016 */
/*0690*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ LOP3.LUT R26, R26, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1a1a7812 */
/* 0x000fcc00078ec0ff */
/*06b0*/ I2F.U16 R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000fe20000101000 */
/*06c0*/ IADD3 R19, R27, -0x2, RZ ; /* 0xfffffffe1b137810 */
/* 0x001fce0007ffe0ff */
/*06d0*/ I2F.U16 R16, R18 ; /* 0x0000001200107306 */
/* 0x004ee40000101000 */
/*06e0*/ FFMA R26, R16, R29, R26 ; /* 0x0000001d101a7223 */
/* 0x008fe2000000001a */
/*06f0*/ IADD3 R16, P1, R23, c[0x0][0x160], RZ ; /* 0x0000580017107a10 */
/* 0x000fca0007f3e0ff */
/*0700*/ F2I.U32.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000e22000020f000 */
/*0710*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff117624 */
/* 0x000fe400008e06ff */
/*0720*/ IMAD.WIDE.U32 R28, R19, R22, c[0x0][0x168] ; /* 0x00005a00131c7625 */
/* 0x000fe200078e0016 */
/*0730*/ STG.E.U8 [R14.64], R26 ; /* 0x0000001a0e007986 */
/* 0x0011e8000c101104 */
/*0740*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002a8000c1e1100 */
/*0750*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x000e22000c1e1900 */
/*0760*/ LOP3.LUT R17, R26, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1a117812 */
/* 0x002fc800078ec0ff */
/*0770*/ I2F.U16 R19, R17 ; /* 0x0000001100137306 */
/* 0x000ff00000101000 */
/*0780*/ I2F.U16 R18, R16 ; /* 0x0000001000127306 */
/* 0x004e240000101000 */
/*0790*/ FFMA R26, R18, R29, R19 ; /* 0x0000001d121a7223 */
/* 0x001fe20000000013 */
/*07a0*/ IADD3 R18, P1, R21, c[0x0][0x160], RZ ; /* 0x0000580015127a10 */
/* 0x000fca0007f3e0ff */
/*07b0*/ F2I.U32.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000e22000020f000 */
/*07c0*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff137624 */
/* 0x000fe200008e06ff */
/*07d0*/ IADD3 R29, R27, -0x1, RZ ; /* 0xffffffff1b1d7810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ STG.E.U8 [R14.64], R26 ; /* 0x0000001a0e007986 */
/* 0x0011e8000c101104 */
/*07f0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1100 */
/*0800*/ IMAD.WIDE.U32 R28, R29, R22, c[0x0][0x168] ; /* 0x00005a001d1c7625 */
/* 0x000fcc00078e0016 */
/*0810*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x0002e4000c1e1900 */
/*0820*/ LOP3.LUT R28, R26, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1a1c7812 */
/* 0x002fc800078ec0ff */
/*0830*/ I2F.U16 R17, R28 ; /* 0x0000001c00117306 */
/* 0x000ff00000101000 */
/*0840*/ I2F.U16 R16, R18 ; /* 0x0000001200107306 */
/* 0x004ee40000101000 */
/*0850*/ FFMA R29, R16, R29, R17 ; /* 0x0000001d101d7223 */
/* 0x008fe20000000011 */
/*0860*/ IADD3 R16, P1, R5, c[0x0][0x160], RZ ; /* 0x0000580005107a10 */
/* 0x000fca0007f3e0ff */
/*0870*/ F2I.U32.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e62000020f000 */
/*0880*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff117624 */
/* 0x000fe400008e06ff */
/*0890*/ IMAD.WIDE.U32 R18, R27, R22, c[0x0][0x168] ; /* 0x00005a001b127625 */
/* 0x000fe200078e0016 */
/*08a0*/ STG.E.U8 [R14.64], R29 ; /* 0x0000001d0e007986 */
/* 0x0023e8000c101104 */
/*08b0*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0004e8000c1e1100 */
/*08c0*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f22000c1e1900 */
/*08d0*/ LOP3.LUT R26, R29, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1d1a7812 */
/* 0x001fe200078ec0ff */
/*08e0*/ IMAD R5, R22, c[0x0][0x178], R5 ; /* 0x00005e0016057a24 */
/* 0x000fe200078e0205 */
/*08f0*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fe20007ffe0ff */
/*0900*/ IMAD R21, R22.reuse, c[0x0][0x178], R21 ; /* 0x00005e0016157a24 */
/* 0x040fe200078e0215 */
/*0910*/ IADD3 R29, R27.reuse, 0x1, RZ ; /* 0x000000011b1d7810 */
/* 0x042fe20007ffe0ff */
/*0920*/ IMAD R23, R22, c[0x0][0x178], R23 ; /* 0x00005e0016177a24 */
/* 0x000fe200078e0217 */
/*0930*/ I2F.U16 R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000fe20000101000 */
/*0940*/ ISETP.GE.AND P1, PT, R24, R3, PT ; /* 0x000000031800720c */
/* 0x000fe20003f26270 */
/*0950*/ IMAD R25, R22, c[0x0][0x178], R25 ; /* 0x00005e0016197a24 */
/* 0x000fe200078e0219 */
/*0960*/ IADD3 R17, R27, 0x4, RZ ; /* 0x000000041b117810 */
/* 0x004fca0007ffe0ff */
/*0970*/ IMAD.MOV.U32 R27, RZ, RZ, R17 ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e0011 */
/*0980*/ I2F.U16 R28, R16 ; /* 0x00000010001c7306 */
/* 0x008f240000101000 */
/*0990*/ FFMA R28, R28, R19, R26 ; /* 0x000000131c1c7223 */
/* 0x010fcc000000001a */
/*09a0*/ F2I.U32.TRUNC.NTZ R28, R28 ; /* 0x0000001c001c7305 */
/* 0x000e24000020f000 */
/*09b0*/ STG.E.U8 [R14.64], R28 ; /* 0x0000001c0e007986 */
/* 0x0011e2000c101104 */
/*09c0*/ PRMT R26, R28, 0x7610, R26 ; /* 0x000076101c1a7816 */
/* 0x000fe2000000001a */
/*09d0*/ @!P1 BRA 0x650 ; /* 0xfffffc7000009947 */
/* 0x000fea000383ffff */
/*09e0*/ @!P0 BRA 0x260 ; /* 0xfffff87000008947 */
/* 0x000fea000383ffff */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void convolution_global_memory_gray(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = ( mask_size-1 )/2;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (j >= paddingSize) && (j < paddedW-paddingSize) && (i >= paddingSize) && (i<paddedH-paddingSize)) {
unsigned int oPixelPos = (j - paddingSize ) * cols + (i -paddingSize);
for(int k = -paddingSize; k <= paddingSize; k++){
for(int l = -paddingSize; l<=paddingSize; l++){
unsigned int iPixelPos = (j+l)*cols+(i+k);
unsigned int coefPos = (k + paddingSize) * mask_size + (l+ paddingSize);
g[oPixelPos] += N[iPixelPos] * M[coefPos];
}
}
}
} | .file "tmpxft_0013e06e_00000000-6_convolution_global_memory_gray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm
.type _Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm, @function
_Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z30convolution_global_memory_grayPhPfS_mmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm, .-_Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm
.globl _Z30convolution_global_memory_grayPhPfS_mmm
.type _Z30convolution_global_memory_grayPhPfS_mmm, @function
_Z30convolution_global_memory_grayPhPfS_mmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30convolution_global_memory_grayPhPfS_mmm, .-_Z30convolution_global_memory_grayPhPfS_mmm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30convolution_global_memory_grayPhPfS_mmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30convolution_global_memory_grayPhPfS_mmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void convolution_global_memory_gray(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = ( mask_size-1 )/2;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (j >= paddingSize) && (j < paddedW-paddingSize) && (i >= paddingSize) && (i<paddedH-paddingSize)) {
unsigned int oPixelPos = (j - paddingSize ) * cols + (i -paddingSize);
for(int k = -paddingSize; k <= paddingSize; k++){
for(int l = -paddingSize; l<=paddingSize; l++){
unsigned int iPixelPos = (j+l)*cols+(i+k);
unsigned int coefPos = (k + paddingSize) * mask_size + (l+ paddingSize);
g[oPixelPos] += N[iPixelPos] * M[coefPos];
}
}
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_global_memory_gray(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = ( mask_size-1 )/2;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (j >= paddingSize) && (j < paddedW-paddingSize) && (i >= paddingSize) && (i<paddedH-paddingSize)) {
unsigned int oPixelPos = (j - paddingSize ) * cols + (i -paddingSize);
for(int k = -paddingSize; k <= paddingSize; k++){
for(int l = -paddingSize; l<=paddingSize; l++){
unsigned int iPixelPos = (j+l)*cols+(i+k);
unsigned int coefPos = (k + paddingSize) * mask_size + (l+ paddingSize);
g[oPixelPos] += N[iPixelPos] * M[coefPos];
}
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_global_memory_gray(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = ( mask_size-1 )/2;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (j >= paddingSize) && (j < paddedW-paddingSize) && (i >= paddingSize) && (i<paddedH-paddingSize)) {
unsigned int oPixelPos = (j - paddingSize ) * cols + (i -paddingSize);
for(int k = -paddingSize; k <= paddingSize; k++){
for(int l = -paddingSize; l<=paddingSize; l++){
unsigned int iPixelPos = (j+l)*cols+(i+k);
unsigned int coefPos = (k + paddingSize) * mask_size + (l+ paddingSize);
g[oPixelPos] += N[iPixelPos] * M[coefPos];
}
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30convolution_global_memory_grayPhPfS_mmm
.globl _Z30convolution_global_memory_grayPhPfS_mmm
.p2align 8
.type _Z30convolution_global_memory_grayPhPfS_mmm,@function
_Z30convolution_global_memory_grayPhPfS_mmm:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b32 s6, s[0:1], 0x3c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_add_u32 s7, s4, -1
s_addc_u32 s5, s5, -1
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_lshr_b32 s6, s6, 16
v_alignbit_b32 v3, s5, s7, 1
s_mul_i32 s15, s15, s6
s_mov_b32 s6, exec_lo
v_add_nc_u32_e32 v1, s15, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s5, v3
v_add_nc_u32_e32 v2, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 v2, v3
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[2:3], 0xc
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s8, s[0:1], 0x18
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s10, s5, 1
s_sub_i32 s9, 0, s5
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s14, s14, s2
s_sub_i32 s2, s3, s5
v_add_nc_u32_e32 v0, s14, v3
s_sub_i32 s3, s8, s5
s_add_i32 s2, s2, s10
s_add_i32 s3, s3, s10
v_cmp_gt_u32_e32 vcc_lo, s2, v2
v_add_nc_u32_e32 v4, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s2, s3, v4
v_cmp_le_i32_e64 s3, s5, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_cmp_le_i32 s9, s5
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_6
s_load_b64 s[12:13], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v1, s8, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v6, v1, s8
v_mov_b32_e32 v2, 0
s_add_i32 s10, s10, 1
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, s14, v6
s_waitcnt lgkmcnt(0)
global_load_u8 v4, v5, s[12:13]
v_add_co_u32 v0, s6, s12, v5
v_add_co_ci_u32_e64 v1, null, s13, 0, s6
.p2align 6
.LBB0_3:
v_mov_b32_e32 v5, v3
s_mov_b32 s6, s11
s_mov_b32 s12, s10
.p2align 6
.LBB0_4:
global_load_u8 v6, v5, s[0:1]
s_lshl_b64 s[14:15], s[6:7], 2
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v4, v4
s_add_u32 s14, s2, s14
s_addc_u32 s15, s3, s15
s_add_i32 s12, s12, -1
global_load_b32 v7, v2, s[14:15]
s_add_i32 s6, s6, 1
s_cmp_eq_u32 s12, 0
v_add_nc_u32_e32 v5, s8, v5
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v7, v6
v_cvt_i32_f32_e32 v4, v4
global_store_b8 v[0:1], v4, off
s_cbranch_scc0 .LBB0_4
v_add_nc_u32_e32 v3, 1, v3
s_add_i32 s6, s9, 1
s_add_i32 s11, s11, s4
s_cmp_eq_u32 s9, s5
s_mov_b32 s9, s6
s_cbranch_scc0 .LBB0_3
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30convolution_global_memory_grayPhPfS_mmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30convolution_global_memory_grayPhPfS_mmm, .Lfunc_end0-_Z30convolution_global_memory_grayPhPfS_mmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30convolution_global_memory_grayPhPfS_mmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z30convolution_global_memory_grayPhPfS_mmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void convolution_global_memory_gray(unsigned char *N,float *M,unsigned char* g,std::size_t cols, std::size_t rows,std::size_t mask_size){
int paddingSize = ( mask_size-1 )/2;
unsigned int paddedH = cols + 2 * paddingSize;
unsigned int paddedW = rows + 2 * paddingSize;
int i = blockIdx.x * blockDim.x + threadIdx.x + paddingSize;
int j = blockIdx.y * blockDim.y + threadIdx.y + paddingSize;
if( (j >= paddingSize) && (j < paddedW-paddingSize) && (i >= paddingSize) && (i<paddedH-paddingSize)) {
unsigned int oPixelPos = (j - paddingSize ) * cols + (i -paddingSize);
for(int k = -paddingSize; k <= paddingSize; k++){
for(int l = -paddingSize; l<=paddingSize; l++){
unsigned int iPixelPos = (j+l)*cols+(i+k);
unsigned int coefPos = (k + paddingSize) * mask_size + (l+ paddingSize);
g[oPixelPos] += N[iPixelPos] * M[coefPos];
}
}
}
} | .text
.file "convolution_global_memory_gray.hip"
.globl _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm # -- Begin function _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm
.p2align 4, 0x90
.type _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm,@function
_Z45__device_stub__convolution_global_memory_grayPhPfS_mmm: # @_Z45__device_stub__convolution_global_memory_grayPhPfS_mmm
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z30convolution_global_memory_grayPhPfS_mmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm, .Lfunc_end0-_Z45__device_stub__convolution_global_memory_grayPhPfS_mmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30convolution_global_memory_grayPhPfS_mmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30convolution_global_memory_grayPhPfS_mmm,@object # @_Z30convolution_global_memory_grayPhPfS_mmm
.section .rodata,"a",@progbits
.globl _Z30convolution_global_memory_grayPhPfS_mmm
.p2align 3, 0x0
_Z30convolution_global_memory_grayPhPfS_mmm:
.quad _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm
.size _Z30convolution_global_memory_grayPhPfS_mmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30convolution_global_memory_grayPhPfS_mmm"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30convolution_global_memory_grayPhPfS_mmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z30convolution_global_memory_grayPhPfS_mmm
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002600 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x188] ; /* 0x00006200ff027624 */
/* 0x000fe400078e00ff */
/*0030*/ IMAD.MOV.U32 R7, RZ, RZ, 0x1 ; /* 0x00000001ff077424 */
/* 0x000fe200078e00ff */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ IADD3 R2, P0, R2, -0x1, RZ ; /* 0xffffffff02027810 */
/* 0x000fe40007f1e0ff */
/*0060*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e640000002500 */
/*0070*/ IADD3.X R7, R7, c[0x0][0x18c], RZ, P0, !PT ; /* 0x0000630007077a10 */
/* 0x000fc400007fe4ff */
/*0080*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e620000002100 */
/*0090*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fe200078e0203 */
/*00a0*/ SHF.R.U64 R3, R2.reuse, 0x1, R7 ; /* 0x0000000102037819 */
/* 0x040fe40000001207 */
/*00b0*/ LOP3.LUT R2, R2, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe02027812 */
/* 0x000fc600078ec0ff */
/*00c0*/ IMAD.IADD R4, R0, 0x1, R3 ; /* 0x0000000100047824 */
/* 0x000fe200078e0203 */
/*00d0*/ IADD3 R7, -R3, c[0x0][0x180], R2 ; /* 0x0000600003077a10 */
/* 0x000fe20007ffe102 */
/*00e0*/ IMAD R5, R5, c[0x0][0x0], R6 ; /* 0x0000000005057a24 */
/* 0x002fc600078e0206 */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R4.reuse, R7, PT ; /* 0x000000070400720c */
/* 0x040fe20003f06070 */
/*0100*/ IMAD.IADD R6, R5, 0x1, R3 ; /* 0x0000000105067824 */
/* 0x000fe200078e0203 */
/*0110*/ IADD3 R7, -R3, c[0x0][0x178], R2 ; /* 0x00005e0003077a10 */
/* 0x000fe40007ffe102 */
/*0120*/ ISETP.LT.OR P0, PT, R4, R3, P0 ; /* 0x000000030400720c */
/* 0x000fc80000701670 */
/*0130*/ ISETP.LT.OR P0, PT, R6, R3, P0 ; /* 0x000000030600720c */
/* 0x000fc80000701670 */
/*0140*/ ISETP.GE.U32.OR P0, PT, R6, R7, P0 ; /* 0x000000070600720c */
/* 0x000fda0000706470 */
/*0150*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0160*/ IMAD.MOV R7, RZ, RZ, -R3 ; /* 0x000000ffff077224 */
/* 0x000fca00078e0a03 */
/*0170*/ ISETP.GT.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fda0003f04270 */
/*0180*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0190*/ IMAD R5, R0, c[0x0][0x178], R5 ; /* 0x00005e0000057a24 */
/* 0x000fe200078e0205 */
/*01a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*01b0*/ IADD3 R14, P0, R5, c[0x0][0x170], RZ ; /* 0x00005c00050e7a10 */
/* 0x000fca0007f1e0ff */
/*01c0*/ IMAD.X R15, RZ, RZ, c[0x0][0x174], P0 ; /* 0x00005d00ff0f7624 */
/* 0x000fca00000e06ff */
/*01d0*/ LDG.E.U8 R26, [R14.64] ; /* 0x000000040e1a7981 */
/* 0x000162000c1e1100 */
/*01e0*/ LOP3.LUT R20, R2, 0x1, RZ, 0xfc, !PT ; /* 0x0000000102147812 */
/* 0x000fe400078efcff */
/*01f0*/ IADD3 R8, -R3.reuse, 0x1, RZ ; /* 0x0000000103087810 */
/* 0x040fe40007ffe1ff */
/*0200*/ IADD3 R9, -R3.reuse, 0x3, RZ ; /* 0x0000000303097810 */
/* 0x040fe40007ffe1ff */
/*0210*/ IADD3 R10, R3, 0x3, RZ ; /* 0x00000003030a7810 */
/* 0x000fe40007ffe0ff */
/*0220*/ IADD3 R11, R4.reuse, 0x3, RZ ; /* 0x00000003040b7810 */
/* 0x040fe40007ffe0ff */
/*0230*/ IADD3 R12, R4, 0x2, RZ ; /* 0x00000002040c7810 */
/* 0x000fc40007ffe0ff */
/*0240*/ IADD3 R13, R4, 0x1, RZ ; /* 0x00000001040d7810 */
/* 0x000fe40007ffe0ff */
/*0250*/ LOP3.LUT R20, R20, 0x3, RZ, 0xc0, !PT ; /* 0x0000000314147812 */
/* 0x001fe400078ec0ff */
/*0260*/ IMAD.IADD R25, R6, 0x1, R7 ; /* 0x0000000106197824 */
/* 0x000fc800078e0207 */
/*0270*/ IMAD R5, R0, c[0x0][0x178], R25 ; /* 0x00005e0000057a24 */
/* 0x000fca00078e0219 */
/*0280*/ IADD3 R18, P0, R5, c[0x0][0x160], RZ ; /* 0x0000580005127a10 */
/* 0x000fca0007f1e0ff */
/*0290*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P0 ; /* 0x00005900ff137624 */
/* 0x001fe400000e06ff */
/*02a0*/ IMAD.IADD R29, R7, 0x1, R3 ; /* 0x00000001071d7824 */
/* 0x000fc800078e0203 */
/*02b0*/ LDG.E.U8 R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x0000a2000c1e1100 */
/*02c0*/ IMAD.MOV.U32 R22, RZ, RZ, 0x4 ; /* 0x00000004ff167424 */
/* 0x000fe400078e00ff */
/*02d0*/ IMAD R29, R29, c[0x0][0x188], RZ ; /* 0x000062001d1d7a24 */
/* 0x000fc800078e02ff */
/*02e0*/ IMAD.WIDE.U32 R16, R29, R22, c[0x0][0x168] ; /* 0x00005a001d107625 */
/* 0x000fcc00078e0016 */
/*02f0*/ LDG.E R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x000ee2000c1e1900 */
/*0300*/ LOP3.LUT R23, R26, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1a177812 */
/* 0x020fe200078ec0ff */
/*0310*/ IMAD.MOV.U32 R18, RZ, RZ, R8 ; /* 0x000000ffff127224 */
/* 0x001fe200078e0008 */
/*0320*/ ISETP.NE.AND P2, PT, R20, 0x1, PT ; /* 0x000000011400780c */
/* 0x000fe40003f45270 */
/*0330*/ ISETP.GE.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fe40003f06270 */
/*0340*/ I2F.U16 R23, R23 ; /* 0x0000001700177306 */
/* 0x000fe20000101000 */
/*0350*/ ISETP.GE.U32.AND P1, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fce0003f26070 */
/*0360*/ I2F.U16 R21, R19 ; /* 0x0000001300157306 */
/* 0x004ee40000101000 */
/*0370*/ FFMA R21, R21, R16, R23 ; /* 0x0000001015157223 */
/* 0x008fcc0000000017 */
/*0380*/ F2I.U32.TRUNC.NTZ R21, R21 ; /* 0x0000001500157305 */
/* 0x000e24000020f000 */
/*0390*/ STG.E.U8 [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0011e2000c101104 */
/*03a0*/ PRMT R26, R21, 0x7610, R26 ; /* 0x00007610151a7816 */
/* 0x000fe2000000001a */
/*03b0*/ @!P2 BRA 0x580 ; /* 0x000001c00000a947 */
/* 0x000fea0003800000 */
/*03c0*/ IADD3 R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a10 */
/* 0x000fc80007ffe0ff */
/*03d0*/ IADD3 R16, P2, R5, c[0x0][0x160], RZ ; /* 0x0000580005107a10 */
/* 0x000fca0007f5e0ff */
/*03e0*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff117624 */
/* 0x000fca00010e06ff */
/*03f0*/ LDG.E.U8 R21, [R16.64] ; /* 0x0000000410157981 */
/* 0x0010a2000c1e1100 */
/*0400*/ IADD3 R19, R29, 0x1, RZ ; /* 0x000000011d137810 */
/* 0x000fca0007ffe0ff */
/*0410*/ IMAD.WIDE.U32 R18, R19, R22, c[0x0][0x168] ; /* 0x00005a0013127625 */
/* 0x000fcc00078e0016 */
/*0420*/ LDG.E R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ee2000c1e1900 */
/*0430*/ LOP3.LUT R23, R26, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1a177812 */
/* 0x000fe400078ec0ff */
/*0440*/ IADD3 R5, R5, c[0x0][0x178], RZ ; /* 0x00005e0005057a10 */
/* 0x000fc80007ffe0ff */
/*0450*/ I2F.U16 R23, R23 ; /* 0x0000001700177306 */
/* 0x000fe20000101000 */
/*0460*/ IADD3 R26, P2, R5, c[0x0][0x160], RZ ; /* 0x00005800051a7a10 */
/* 0x000fca0007f5e0ff */
/*0470*/ IMAD.X R27, RZ, RZ, c[0x0][0x164], P2 ; /* 0x00005900ff1b7624 */
/* 0x000fe200010e06ff */
/*0480*/ IADD3 R17, R29, 0x2, RZ ; /* 0x000000021d117810 */
/* 0x001fca0007ffe0ff */
/*0490*/ IMAD.WIDE.U32 R16, R17, R22, c[0x0][0x168] ; /* 0x00005a0011107625 */
/* 0x000fe200078e0016 */
/*04a0*/ I2F.U16 R21, R21 ; /* 0x0000001500157306 */
/* 0x004ee60000101000 */
/*04b0*/ FFMA R24, R21, R18, R23 ; /* 0x0000001215187223 */
/* 0x008fcc0000000017 */
/*04c0*/ F2I.U32.TRUNC.NTZ R24, R24 ; /* 0x0000001800187305 */
/* 0x000e24000020f000 */
/*04d0*/ STG.E.U8 [R14.64], R24 ; /* 0x000000180e007986 */
/* 0x0011e8000c101104 */
/*04e0*/ LDG.E.U8 R27, [R26.64] ; /* 0x000000041a1b7981 */
/* 0x000ea8000c1e1100 */
/*04f0*/ LDG.E R17, [R16.64] ; /* 0x0000000410117981 */
/* 0x000ee2000c1e1900 */
/*0500*/ LOP3.LUT R5, R24, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff18057812 */
/* 0x000fcc00078ec0ff */
/*0510*/ I2F.U16 R5, R5 ; /* 0x0000000500057306 */
/* 0x000ff00000101000 */
/*0520*/ I2F.U16 R18, R27 ; /* 0x0000001b00127306 */
/* 0x004ee40000101000 */
/*0530*/ FFMA R19, R18, R17, R5 ; /* 0x0000001112137223 */
/* 0x008fc40000000005 */
/*0540*/ IMAD.MOV.U32 R18, RZ, RZ, R9 ; /* 0x000000ffff127224 */
/* 0x000fc800078e0009 */
/*0550*/ F2I.U32.TRUNC.NTZ R19, R19 ; /* 0x0000001300137305 */
/* 0x000e64000020f000 */
/*0560*/ STG.E.U8 [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0021e2000c101104 */
/*0570*/ PRMT R26, R19, 0x7610, R26 ; /* 0x00007610131a7816 */
/* 0x000fca000000001a */
/*0580*/ IADD3 R7, R7, 0x1, RZ ; /* 0x0000000107077810 */
/* 0x000fe20007ffe0ff */
/*0590*/ @!P1 BRA 0x9e0 ; /* 0x0000044000009947 */
/* 0x000fea0003800000 */
/*05a0*/ IMAD.IADD R16, R11, 0x1, R18.reuse ; /* 0x000000010b107824 */
/* 0x100fe200078e0212 */
/*05b0*/ IADD3 R27, R29.reuse, R10, R18.reuse ; /* 0x0000000a1d1b7210 */
/* 0x140fe20007ffe012 */
/*05c0*/ IMAD.IADD R24, R12, 0x1, R18.reuse ; /* 0x000000010c187824 */
/* 0x101fe200078e0212 */
/*05d0*/ IADD3 R29, R29, R3, R18.reuse ; /* 0x000000031d1d7210 */
/* 0x100fe20007ffe012 */
/*05e0*/ IMAD.IADD R28, R13, 0x1, R18.reuse ; /* 0x000000010d1c7824 */
/* 0x100fe400078e0212 */
/*05f0*/ IMAD.IADD R17, R4, 0x1, R18 ; /* 0x0000000104117824 */
/* 0x000fc400078e0212 */
/*0600*/ IMAD R5, R16, c[0x0][0x178], R25.reuse ; /* 0x00005e0010057a24 */
/* 0x100fe400078e0219 */
/*0610*/ IMAD R21, R24, c[0x0][0x178], R25.reuse ; /* 0x00005e0018157a24 */
/* 0x100fe200078e0219 */
/*0620*/ IADD3 R24, R18, -0x1, RZ ; /* 0xffffffff12187810 */
/* 0x000fe20007ffe0ff */
/*0630*/ IMAD R23, R28, c[0x0][0x178], R25.reuse ; /* 0x00005e001c177a24 */
/* 0x100fe400078e0219 */
/*0640*/ IMAD R25, R17, c[0x0][0x178], R25 ; /* 0x00005e0011197a24 */
/* 0x000fca00078e0219 */
/*0650*/ IADD3 R18, P1, R25, c[0x0][0x160], RZ ; /* 0x0000580019127a10 */
/* 0x000fca0007f3e0ff */
/*0660*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff137624 */
/* 0x000fca00008e06ff */
/*0670*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x0010a2000c1e1100 */
/*0680*/ IMAD.WIDE.U32 R28, R29, R22, c[0x0][0x168] ; /* 0x00005a001d1c7625 */
/* 0x000fcc00078e0016 */
/*0690*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x000ee2000c1e1900 */
/*06a0*/ LOP3.LUT R26, R26, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1a1a7812 */
/* 0x000fcc00078ec0ff */
/*06b0*/ I2F.U16 R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000fe20000101000 */
/*06c0*/ IADD3 R19, R27, -0x2, RZ ; /* 0xfffffffe1b137810 */
/* 0x001fce0007ffe0ff */
/*06d0*/ I2F.U16 R16, R18 ; /* 0x0000001200107306 */
/* 0x004ee40000101000 */
/*06e0*/ FFMA R26, R16, R29, R26 ; /* 0x0000001d101a7223 */
/* 0x008fe2000000001a */
/*06f0*/ IADD3 R16, P1, R23, c[0x0][0x160], RZ ; /* 0x0000580017107a10 */
/* 0x000fca0007f3e0ff */
/*0700*/ F2I.U32.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000e22000020f000 */
/*0710*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff117624 */
/* 0x000fe400008e06ff */
/*0720*/ IMAD.WIDE.U32 R28, R19, R22, c[0x0][0x168] ; /* 0x00005a00131c7625 */
/* 0x000fe200078e0016 */
/*0730*/ STG.E.U8 [R14.64], R26 ; /* 0x0000001a0e007986 */
/* 0x0011e8000c101104 */
/*0740*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0002a8000c1e1100 */
/*0750*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x000e22000c1e1900 */
/*0760*/ LOP3.LUT R17, R26, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1a117812 */
/* 0x002fc800078ec0ff */
/*0770*/ I2F.U16 R19, R17 ; /* 0x0000001100137306 */
/* 0x000ff00000101000 */
/*0780*/ I2F.U16 R18, R16 ; /* 0x0000001000127306 */
/* 0x004e240000101000 */
/*0790*/ FFMA R26, R18, R29, R19 ; /* 0x0000001d121a7223 */
/* 0x001fe20000000013 */
/*07a0*/ IADD3 R18, P1, R21, c[0x0][0x160], RZ ; /* 0x0000580015127a10 */
/* 0x000fca0007f3e0ff */
/*07b0*/ F2I.U32.TRUNC.NTZ R26, R26 ; /* 0x0000001a001a7305 */
/* 0x000e22000020f000 */
/*07c0*/ IMAD.X R19, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff137624 */
/* 0x000fe200008e06ff */
/*07d0*/ IADD3 R29, R27, -0x1, RZ ; /* 0xffffffff1b1d7810 */
/* 0x000fe20007ffe0ff */
/*07e0*/ STG.E.U8 [R14.64], R26 ; /* 0x0000001a0e007986 */
/* 0x0011e8000c101104 */
/*07f0*/ LDG.E.U8 R18, [R18.64] ; /* 0x0000000412127981 */
/* 0x000ea2000c1e1100 */
/*0800*/ IMAD.WIDE.U32 R28, R29, R22, c[0x0][0x168] ; /* 0x00005a001d1c7625 */
/* 0x000fcc00078e0016 */
/*0810*/ LDG.E R29, [R28.64] ; /* 0x000000041c1d7981 */
/* 0x0002e4000c1e1900 */
/*0820*/ LOP3.LUT R28, R26, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1a1c7812 */
/* 0x002fc800078ec0ff */
/*0830*/ I2F.U16 R17, R28 ; /* 0x0000001c00117306 */
/* 0x000ff00000101000 */
/*0840*/ I2F.U16 R16, R18 ; /* 0x0000001200107306 */
/* 0x004ee40000101000 */
/*0850*/ FFMA R29, R16, R29, R17 ; /* 0x0000001d101d7223 */
/* 0x008fe20000000011 */
/*0860*/ IADD3 R16, P1, R5, c[0x0][0x160], RZ ; /* 0x0000580005107a10 */
/* 0x000fca0007f3e0ff */
/*0870*/ F2I.U32.TRUNC.NTZ R29, R29 ; /* 0x0000001d001d7305 */
/* 0x000e62000020f000 */
/*0880*/ IMAD.X R17, RZ, RZ, c[0x0][0x164], P1 ; /* 0x00005900ff117624 */
/* 0x000fe400008e06ff */
/*0890*/ IMAD.WIDE.U32 R18, R27, R22, c[0x0][0x168] ; /* 0x00005a001b127625 */
/* 0x000fe200078e0016 */
/*08a0*/ STG.E.U8 [R14.64], R29 ; /* 0x0000001d0e007986 */
/* 0x0023e8000c101104 */
/*08b0*/ LDG.E.U8 R16, [R16.64] ; /* 0x0000000410107981 */
/* 0x0004e8000c1e1100 */
/*08c0*/ LDG.E R19, [R18.64] ; /* 0x0000000412137981 */
/* 0x000f22000c1e1900 */
/*08d0*/ LOP3.LUT R26, R29, 0xff, RZ, 0xc0, !PT ; /* 0x000000ff1d1a7812 */
/* 0x001fe200078ec0ff */
/*08e0*/ IMAD R5, R22, c[0x0][0x178], R5 ; /* 0x00005e0016057a24 */
/* 0x000fe200078e0205 */
/*08f0*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fe20007ffe0ff */
/*0900*/ IMAD R21, R22.reuse, c[0x0][0x178], R21 ; /* 0x00005e0016157a24 */
/* 0x040fe200078e0215 */
/*0910*/ IADD3 R29, R27.reuse, 0x1, RZ ; /* 0x000000011b1d7810 */
/* 0x042fe20007ffe0ff */
/*0920*/ IMAD R23, R22, c[0x0][0x178], R23 ; /* 0x00005e0016177a24 */
/* 0x000fe200078e0217 */
/*0930*/ I2F.U16 R26, R26 ; /* 0x0000001a001a7306 */
/* 0x000fe20000101000 */
/*0940*/ ISETP.GE.AND P1, PT, R24, R3, PT ; /* 0x000000031800720c */
/* 0x000fe20003f26270 */
/*0950*/ IMAD R25, R22, c[0x0][0x178], R25 ; /* 0x00005e0016197a24 */
/* 0x000fe200078e0219 */
/*0960*/ IADD3 R17, R27, 0x4, RZ ; /* 0x000000041b117810 */
/* 0x004fca0007ffe0ff */
/*0970*/ IMAD.MOV.U32 R27, RZ, RZ, R17 ; /* 0x000000ffff1b7224 */
/* 0x000fe200078e0011 */
/*0980*/ I2F.U16 R28, R16 ; /* 0x00000010001c7306 */
/* 0x008f240000101000 */
/*0990*/ FFMA R28, R28, R19, R26 ; /* 0x000000131c1c7223 */
/* 0x010fcc000000001a */
/*09a0*/ F2I.U32.TRUNC.NTZ R28, R28 ; /* 0x0000001c001c7305 */
/* 0x000e24000020f000 */
/*09b0*/ STG.E.U8 [R14.64], R28 ; /* 0x0000001c0e007986 */
/* 0x0011e2000c101104 */
/*09c0*/ PRMT R26, R28, 0x7610, R26 ; /* 0x000076101c1a7816 */
/* 0x000fe2000000001a */
/*09d0*/ @!P1 BRA 0x650 ; /* 0xfffffc7000009947 */
/* 0x000fea000383ffff */
/*09e0*/ @!P0 BRA 0x260 ; /* 0xfffff87000008947 */
/* 0x000fea000383ffff */
/*09f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0a00*/ BRA 0xa00; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0aa0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ab0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ac0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ad0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ae0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0af0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30convolution_global_memory_grayPhPfS_mmm
.globl _Z30convolution_global_memory_grayPhPfS_mmm
.p2align 8
.type _Z30convolution_global_memory_grayPhPfS_mmm,@function
_Z30convolution_global_memory_grayPhPfS_mmm:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x28
s_load_b32 s6, s[0:1], 0x3c
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_add_u32 s7, s4, -1
s_addc_u32 s5, s5, -1
s_add_u32 s2, s0, 48
s_addc_u32 s3, s1, 0
s_lshr_b32 s6, s6, 16
v_alignbit_b32 v3, s5, s7, 1
s_mul_i32 s15, s15, s6
s_mov_b32 s6, exec_lo
v_add_nc_u32_e32 v1, s15, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_readfirstlane_b32 s5, v3
v_add_nc_u32_e32 v2, v1, v3
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_ge_i32_e64 v2, v3
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[2:3], 0xc
s_clause 0x1
s_load_b32 s3, s[0:1], 0x20
s_load_b32 s8, s[0:1], 0x18
v_and_b32_e32 v3, 0x3ff, v0
s_lshl_b32 s10, s5, 1
s_sub_i32 s9, 0, s5
s_mov_b32 s7, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1)
s_mul_i32 s14, s14, s2
s_sub_i32 s2, s3, s5
v_add_nc_u32_e32 v0, s14, v3
s_sub_i32 s3, s8, s5
s_add_i32 s2, s2, s10
s_add_i32 s3, s3, s10
v_cmp_gt_u32_e32 vcc_lo, s2, v2
v_add_nc_u32_e32 v4, s5, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e64 s2, s3, v4
v_cmp_le_i32_e64 s3, s5, v4
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s3
s_cmp_le_i32 s9, s5
s_cselect_b32 s3, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s3, s2
s_and_b32 exec_lo, exec_lo, s2
s_cbranch_execz .LBB0_6
s_load_b64 s[12:13], s[0:1], 0x10
v_mad_u64_u32 v[5:6], null, v1, s8, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v6, v1, s8
v_mov_b32_e32 v2, 0
s_add_i32 s10, s10, 1
s_mov_b32 s11, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add3_u32 v3, v3, s14, v6
s_waitcnt lgkmcnt(0)
global_load_u8 v4, v5, s[12:13]
v_add_co_u32 v0, s6, s12, v5
v_add_co_ci_u32_e64 v1, null, s13, 0, s6
.p2align 6
.LBB0_3:
v_mov_b32_e32 v5, v3
s_mov_b32 s6, s11
s_mov_b32 s12, s10
.p2align 6
.LBB0_4:
global_load_u8 v6, v5, s[0:1]
s_lshl_b64 s[14:15], s[6:7], 2
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v4, v4
s_add_u32 s14, s2, s14
s_addc_u32 s15, s3, s15
s_add_i32 s12, s12, -1
global_load_b32 v7, v2, s[14:15]
s_add_i32 s6, s6, 1
s_cmp_eq_u32 s12, 0
v_add_nc_u32_e32 v5, s8, v5
s_waitcnt vmcnt(1)
v_cvt_f32_ubyte0_e32 v6, v6
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v7, v6
v_cvt_i32_f32_e32 v4, v4
global_store_b8 v[0:1], v4, off
s_cbranch_scc0 .LBB0_4
v_add_nc_u32_e32 v3, 1, v3
s_add_i32 s6, s9, 1
s_add_i32 s11, s11, s4
s_cmp_eq_u32 s9, s5
s_mov_b32 s9, s6
s_cbranch_scc0 .LBB0_3
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30convolution_global_memory_grayPhPfS_mmm
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30convolution_global_memory_grayPhPfS_mmm, .Lfunc_end0-_Z30convolution_global_memory_grayPhPfS_mmm
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 8
.value_kind: by_value
- .offset: 40
.size: 8
.value_kind: by_value
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30convolution_global_memory_grayPhPfS_mmm
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z30convolution_global_memory_grayPhPfS_mmm.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013e06e_00000000-6_convolution_global_memory_gray.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm
.type _Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm, @function
_Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movq %rcx, 16(%rsp)
movq %r8, 8(%rsp)
movq %r9, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
movq %rsp, %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z30convolution_global_memory_grayPhPfS_mmm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm, .-_Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm
.globl _Z30convolution_global_memory_grayPhPfS_mmm
.type _Z30convolution_global_memory_grayPhPfS_mmm, @function
_Z30convolution_global_memory_grayPhPfS_mmm:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z57__device_stub__Z30convolution_global_memory_grayPhPfS_mmmPhPfS_mmm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z30convolution_global_memory_grayPhPfS_mmm, .-_Z30convolution_global_memory_grayPhPfS_mmm
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30convolution_global_memory_grayPhPfS_mmm"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30convolution_global_memory_grayPhPfS_mmm(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "convolution_global_memory_gray.hip"
.globl _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm # -- Begin function _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm
.p2align 4, 0x90
.type _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm,@function
_Z45__device_stub__convolution_global_memory_grayPhPfS_mmm: # @_Z45__device_stub__convolution_global_memory_grayPhPfS_mmm
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
movq %r8, 56(%rsp)
movq %r9, 48(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rax
movq %rax, 120(%rsp)
leaq 56(%rsp), %rax
movq %rax, 128(%rsp)
leaq 48(%rsp), %rax
movq %rax, 136(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z30convolution_global_memory_grayPhPfS_mmm, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm, .Lfunc_end0-_Z45__device_stub__convolution_global_memory_grayPhPfS_mmm
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30convolution_global_memory_grayPhPfS_mmm, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30convolution_global_memory_grayPhPfS_mmm,@object # @_Z30convolution_global_memory_grayPhPfS_mmm
.section .rodata,"a",@progbits
.globl _Z30convolution_global_memory_grayPhPfS_mmm
.p2align 3, 0x0
_Z30convolution_global_memory_grayPhPfS_mmm:
.quad _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm
.size _Z30convolution_global_memory_grayPhPfS_mmm, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30convolution_global_memory_grayPhPfS_mmm"
.size .L__unnamed_1, 44
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__convolution_global_memory_grayPhPfS_mmm
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30convolution_global_memory_grayPhPfS_mmm
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
/*1-20*/
#define BLOCK_WIDTH 2
#define BLOCK_SIZE 4
using namespace std;
/*
//BlockTranspose
__global__
void BlockTranspose(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
*/
/*BlockTranspose_Kernel*/
__global__
void BlockTranspose_Kernel(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
__syncthreads();
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
/*BlockTranspose_GPU*/
void BlockTranspose_GPU(float* h_A, int A_width, int A_height) {
int size = A_width * A_height * sizeof(float);
float *d_A;
cudaMalloc(&d_A, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
dim3 blockDim(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 gridDim(A_width / blockDim.x, A_height / blockDim.y);
BlockTranspose_Kernel <<< gridDim, blockDim >>> (h_A, A_width, A_height);
cudaMemcpy(h_A, d_A, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
}
int main() {
//Host
float *h_A;
int A_width = 8;
int A_height = 8;
h_A = (float*)malloc(A_width*A_height * sizeof(float));
//Create
for (int i = 0; i < A_width*A_height; i++) {
h_A[i] = i + 1.0f;
}
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//BlockTranspose (Main)
chrono::time_point<chrono::system_clock> BlockTranspose_GPU_Start, BlockTranspose_GPU_End;
BlockTranspose_GPU_Start = chrono::system_clock::now();
BlockTranspose_GPU(h_A, A_width, A_height);
BlockTranspose_GPU_End = chrono::system_clock::now();
cout << "BlockTranspose_GPU: " << chrono::duration_cast<chrono::nanoseconds>(BlockTranspose_GPU_End - BlockTranspose_GPU_Start).count() << "ns." << endl;
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//Free
free(h_A);
return 0;
} | code for sm_80
Function : _Z21BlockTranspose_KernelPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0060*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0070*/ LEA R0, R0, R5, 0x2 ; /* 0x0000000500007211 */
/* 0x001fc400078e10ff */
/*0080*/ LEA R3, R3, R4, 0x2 ; /* 0x0000000403037211 */
/* 0x002fca00078e10ff */
/*0090*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ LEA R7, R4, R5, 0x1 ; /* 0x0000000504077211 */
/* 0x000fe200078e08ff */
/*00d0*/ IMAD R5, R5, 0x2, R4 ; /* 0x0000000205057824 */
/* 0x000fc800078e0204 */
/*00e0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x004fe80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e280000004800 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
/*1-20*/
#define BLOCK_WIDTH 2
#define BLOCK_SIZE 4
using namespace std;
/*
//BlockTranspose
__global__
void BlockTranspose(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
*/
/*BlockTranspose_Kernel*/
__global__
void BlockTranspose_Kernel(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
__syncthreads();
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
/*BlockTranspose_GPU*/
void BlockTranspose_GPU(float* h_A, int A_width, int A_height) {
int size = A_width * A_height * sizeof(float);
float *d_A;
cudaMalloc(&d_A, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
dim3 blockDim(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 gridDim(A_width / blockDim.x, A_height / blockDim.y);
BlockTranspose_Kernel <<< gridDim, blockDim >>> (h_A, A_width, A_height);
cudaMemcpy(h_A, d_A, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
}
int main() {
//Host
float *h_A;
int A_width = 8;
int A_height = 8;
h_A = (float*)malloc(A_width*A_height * sizeof(float));
//Create
for (int i = 0; i < A_width*A_height; i++) {
h_A[i] = i + 1.0f;
}
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//BlockTranspose (Main)
chrono::time_point<chrono::system_clock> BlockTranspose_GPU_Start, BlockTranspose_GPU_End;
BlockTranspose_GPU_Start = chrono::system_clock::now();
BlockTranspose_GPU(h_A, A_width, A_height);
BlockTranspose_GPU_End = chrono::system_clock::now();
cout << "BlockTranspose_GPU: " << chrono::duration_cast<chrono::nanoseconds>(BlockTranspose_GPU_End - BlockTranspose_GPU_Start).count() << "ns." << endl;
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//Free
free(h_A);
return 0;
} | .file "tmpxft_00017d3c_00000000-6_e10.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3778:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3778:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii
.type _Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii, @function
_Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii:
.LFB3800:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21BlockTranspose_KernelPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.size _Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii, .-_Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii
.globl _Z21BlockTranspose_KernelPfii
.type _Z21BlockTranspose_KernelPfii, @function
_Z21BlockTranspose_KernelPfii:
.LFB3801:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _Z21BlockTranspose_KernelPfii, .-_Z21BlockTranspose_KernelPfii
.globl _Z18BlockTranspose_GPUPfii
.type _Z18BlockTranspose_GPUPfii, @function
_Z18BlockTranspose_GPUPfii:
.LFB3768:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movl %esi, %r12d
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %ebx
imull %edx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
shrl %eax
movl %eax, 28(%rsp)
movl %r13d, %eax
shrl %eax
movl %eax, 32(%rsp)
movl $2, 16(%rsp)
movl $2, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r13d, %edx
movl %r12d, %esi
movq %rbp, %rdi
call _Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size _Z18BlockTranspose_GPUPfii, .-_Z18BlockTranspose_GPUPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.LC2:
.string "BlockTranspose_GPU: "
.LC3:
.string "ns."
.text
.globl main
.type main, @function
main:
.LFB3769:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $256, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %eax
movss .LC0(%rip), %xmm1
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%r14,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L18
leaq 32(%r14), %rbp
leaq 288(%r14), %rax
movq %rax, 8(%rsp)
movq %rbp, %r12
leaq _ZSt4cout(%rip), %r13
leaq .LC1(%rip), %r15
jmp .L19
.L35:
call _ZSt16__throw_bad_castv@PLT
.L22:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L23:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $32, %r12
movq 8(%rsp), %rax
cmpq %rax, %r12
je .L24
.L19:
leaq -32(%r12), %rbx
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L22
movzbl 67(%rbx), %esi
jmp .L23
.L24:
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $8, %edx
movl $8, %esi
movq %r14, %rdi
call _Z18BlockTranspose_GPUPfii
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
subq %r12, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %r12
leaq .LC1(%rip), %r13
jmp .L25
.L36:
call _ZSt16__throw_bad_castv@PLT
.L28:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L29:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $32, %rbp
movq 8(%rsp), %rax
cmpq %rax, %rbp
je .L30
.L25:
leaq -32(%rbp), %rbx
.L26:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L26
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L36
cmpb $0, 56(%rbx)
je .L28
movzbl 67(%rbx), %esi
jmp .L29
.L30:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rdi
call free@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3769:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z21BlockTranspose_KernelPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z21BlockTranspose_KernelPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
/*1-20*/
#define BLOCK_WIDTH 2
#define BLOCK_SIZE 4
using namespace std;
/*
//BlockTranspose
__global__
void BlockTranspose(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
*/
/*BlockTranspose_Kernel*/
__global__
void BlockTranspose_Kernel(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
__syncthreads();
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
/*BlockTranspose_GPU*/
void BlockTranspose_GPU(float* h_A, int A_width, int A_height) {
int size = A_width * A_height * sizeof(float);
float *d_A;
cudaMalloc(&d_A, size);
cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
dim3 blockDim(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 gridDim(A_width / blockDim.x, A_height / blockDim.y);
BlockTranspose_Kernel <<< gridDim, blockDim >>> (h_A, A_width, A_height);
cudaMemcpy(h_A, d_A, size, cudaMemcpyDeviceToHost);
cudaFree(d_A);
}
int main() {
//Host
float *h_A;
int A_width = 8;
int A_height = 8;
h_A = (float*)malloc(A_width*A_height * sizeof(float));
//Create
for (int i = 0; i < A_width*A_height; i++) {
h_A[i] = i + 1.0f;
}
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//BlockTranspose (Main)
chrono::time_point<chrono::system_clock> BlockTranspose_GPU_Start, BlockTranspose_GPU_End;
BlockTranspose_GPU_Start = chrono::system_clock::now();
BlockTranspose_GPU(h_A, A_width, A_height);
BlockTranspose_GPU_End = chrono::system_clock::now();
cout << "BlockTranspose_GPU: " << chrono::duration_cast<chrono::nanoseconds>(BlockTranspose_GPU_End - BlockTranspose_GPU_Start).count() << "ns." << endl;
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//Free
free(h_A);
return 0;
} | #include <hip/hip_runtime.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
/*1-20*/
#define BLOCK_WIDTH 2
#define BLOCK_SIZE 4
using namespace std;
/*
//BlockTranspose
__global__
void BlockTranspose(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
*/
/*BlockTranspose_Kernel*/
__global__
void BlockTranspose_Kernel(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
__syncthreads();
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
/*BlockTranspose_GPU*/
void BlockTranspose_GPU(float* h_A, int A_width, int A_height) {
int size = A_width * A_height * sizeof(float);
float *d_A;
hipMalloc(&d_A, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
dim3 blockDim(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 gridDim(A_width / blockDim.x, A_height / blockDim.y);
BlockTranspose_Kernel <<< gridDim, blockDim >>> (h_A, A_width, A_height);
hipMemcpy(h_A, d_A, size, hipMemcpyDeviceToHost);
hipFree(d_A);
}
int main() {
//Host
float *h_A;
int A_width = 8;
int A_height = 8;
h_A = (float*)malloc(A_width*A_height * sizeof(float));
//Create
for (int i = 0; i < A_width*A_height; i++) {
h_A[i] = i + 1.0f;
}
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//BlockTranspose (Main)
chrono::time_point<chrono::system_clock> BlockTranspose_GPU_Start, BlockTranspose_GPU_End;
BlockTranspose_GPU_Start = chrono::system_clock::now();
BlockTranspose_GPU(h_A, A_width, A_height);
BlockTranspose_GPU_End = chrono::system_clock::now();
cout << "BlockTranspose_GPU: " << chrono::duration_cast<chrono::nanoseconds>(BlockTranspose_GPU_End - BlockTranspose_GPU_Start).count() << "ns." << endl;
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//Free
free(h_A);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
/*1-20*/
#define BLOCK_WIDTH 2
#define BLOCK_SIZE 4
using namespace std;
/*
//BlockTranspose
__global__
void BlockTranspose(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
*/
/*BlockTranspose_Kernel*/
__global__
void BlockTranspose_Kernel(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
__syncthreads();
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
/*BlockTranspose_GPU*/
void BlockTranspose_GPU(float* h_A, int A_width, int A_height) {
int size = A_width * A_height * sizeof(float);
float *d_A;
hipMalloc(&d_A, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
dim3 blockDim(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 gridDim(A_width / blockDim.x, A_height / blockDim.y);
BlockTranspose_Kernel <<< gridDim, blockDim >>> (h_A, A_width, A_height);
hipMemcpy(h_A, d_A, size, hipMemcpyDeviceToHost);
hipFree(d_A);
}
int main() {
//Host
float *h_A;
int A_width = 8;
int A_height = 8;
h_A = (float*)malloc(A_width*A_height * sizeof(float));
//Create
for (int i = 0; i < A_width*A_height; i++) {
h_A[i] = i + 1.0f;
}
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//BlockTranspose (Main)
chrono::time_point<chrono::system_clock> BlockTranspose_GPU_Start, BlockTranspose_GPU_End;
BlockTranspose_GPU_Start = chrono::system_clock::now();
BlockTranspose_GPU(h_A, A_width, A_height);
BlockTranspose_GPU_End = chrono::system_clock::now();
cout << "BlockTranspose_GPU: " << chrono::duration_cast<chrono::nanoseconds>(BlockTranspose_GPU_End - BlockTranspose_GPU_Start).count() << "ns." << endl;
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//Free
free(h_A);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21BlockTranspose_KernelPfii
.globl _Z21BlockTranspose_KernelPfii
.p2align 8
.type _Z21BlockTranspose_KernelPfii,@function
_Z21BlockTranspose_KernelPfii:
s_load_b32 s2, s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 2, v2
v_lshlrev_b32_e32 v5, 2, v3
v_lshlrev_b32_e32 v6, 2, v2
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v2, v2, 3, v5
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s2
s_lshl_b32 s2, s14, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s2, v3, v1
v_lshl_add_u32 v3, v3, 3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21BlockTranspose_KernelPfii
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21BlockTranspose_KernelPfii, .Lfunc_end0-_Z21BlockTranspose_KernelPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21BlockTranspose_KernelPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21BlockTranspose_KernelPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <cstdio>
#include <iostream>
#include <chrono>
/*1-20*/
#define BLOCK_WIDTH 2
#define BLOCK_SIZE 4
using namespace std;
/*
//BlockTranspose
__global__
void BlockTranspose(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
*/
/*BlockTranspose_Kernel*/
__global__
void BlockTranspose_Kernel(float *A_elements, int A_width, int A_height) {
__shared__ float blockA[BLOCK_WIDTH][BLOCK_WIDTH];
int baseIdx = blockIdx.x * BLOCK_SIZE + threadIdx.x;
baseIdx += (blockIdx.y * BLOCK_SIZE + threadIdx.y) * A_width;
blockA[threadIdx.y][threadIdx.x] = A_elements[baseIdx];
__syncthreads();
A_elements[baseIdx] = blockA[threadIdx.x][threadIdx.y];
}
/*BlockTranspose_GPU*/
void BlockTranspose_GPU(float* h_A, int A_width, int A_height) {
int size = A_width * A_height * sizeof(float);
float *d_A;
hipMalloc(&d_A, size);
hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
dim3 blockDim(BLOCK_WIDTH, BLOCK_WIDTH);
dim3 gridDim(A_width / blockDim.x, A_height / blockDim.y);
BlockTranspose_Kernel <<< gridDim, blockDim >>> (h_A, A_width, A_height);
hipMemcpy(h_A, d_A, size, hipMemcpyDeviceToHost);
hipFree(d_A);
}
int main() {
//Host
float *h_A;
int A_width = 8;
int A_height = 8;
h_A = (float*)malloc(A_width*A_height * sizeof(float));
//Create
for (int i = 0; i < A_width*A_height; i++) {
h_A[i] = i + 1.0f;
}
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//BlockTranspose (Main)
chrono::time_point<chrono::system_clock> BlockTranspose_GPU_Start, BlockTranspose_GPU_End;
BlockTranspose_GPU_Start = chrono::system_clock::now();
BlockTranspose_GPU(h_A, A_width, A_height);
BlockTranspose_GPU_End = chrono::system_clock::now();
cout << "BlockTranspose_GPU: " << chrono::duration_cast<chrono::nanoseconds>(BlockTranspose_GPU_End - BlockTranspose_GPU_Start).count() << "ns." << endl;
//Print BlockTranspose
for (int i = 0; i < A_height; i++) {
for (int j = 0; j < A_width; j++) {
cout << h_A[i*A_width + j] << " ";
}
cout << endl;
}
cout << endl;
//Free
free(h_A);
return 0;
} | .text
.file "e10.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z36__device_stub__BlockTranspose_KernelPfii # -- Begin function _Z36__device_stub__BlockTranspose_KernelPfii
.p2align 4, 0x90
.type _Z36__device_stub__BlockTranspose_KernelPfii,@function
_Z36__device_stub__BlockTranspose_KernelPfii: # @_Z36__device_stub__BlockTranspose_KernelPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21BlockTranspose_KernelPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z36__device_stub__BlockTranspose_KernelPfii, .Lfunc_end0-_Z36__device_stub__BlockTranspose_KernelPfii
.cfi_endproc
# -- End function
.globl _Z18BlockTranspose_GPUPfii # -- Begin function _Z18BlockTranspose_GPUPfii
.p2align 4, 0x90
.type _Z18BlockTranspose_GPUPfii,@function
_Z18BlockTranspose_GPUPfii: # @_Z18BlockTranspose_GPUPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %rbx
movl %esi, %eax
imull %edx, %eax
shll $2, %eax
movslq %eax, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, %eax
shrl %eax
movl %ebp, %edi
shrl %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 72(%rsp)
movl %r15d, 20(%rsp)
movl %ebp, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21BlockTranspose_KernelPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18BlockTranspose_GPUPfii, .Lfunc_end1-_Z18BlockTranspose_GPUPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
xorl %eax, %eax
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
addss %xmm0, %xmm1
movss %xmm1, (%rbx,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB2_1
# %bb.2: # %.preheader61.preheader
xorl %r15d, %r15d
movq %rbx, %r12
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_22: # in Loop: Header=BB2_3 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
# in Loop: Header=BB2_3 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $32, %r12
cmpq $8, %r15
je .LBB2_8
.LBB2_3: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $8, %r14
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_3 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_31
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i44
# in Loop: Header=BB2_3 Depth=1
cmpb $0, 56(%r14)
je .LBB2_22
# %bb.7: # in Loop: Header=BB2_3 Depth=1
movzbl 67(%r14), %eax
jmp .LBB2_23
.LBB2_8:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_31
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_11
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB2_12
.LBB2_11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq %rbx, %rdi
movl $8, %esi
movl $8, %edx
callq _Z18BlockTranspose_GPUPfii
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r14
movl $.L.str.2, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_31
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
cmpb $0, 56(%r15)
je .LBB2_15
# %bb.14:
movzbl 67(%r15), %eax
jmp .LBB2_16
.LBB2_15:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit42
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
movq %rbx, %r12
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_21: # in Loop: Header=BB2_17 Depth=1
movzbl 67(%r14), %eax
.LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit57
# in Loop: Header=BB2_17 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $32, %r12
cmpq $8, %r15
je .LBB2_24
.LBB2_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $8, %r14
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_17 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_31
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i54
# in Loop: Header=BB2_17 Depth=1
cmpb $0, 56(%r14)
jne .LBB2_21
# %bb.29: # in Loop: Header=BB2_17 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB2_30
.LBB2_24:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_31
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i49
cmpb $0, 56(%r14)
je .LBB2_27
# %bb.26:
movzbl 67(%r14), %eax
jmp .LBB2_28
.LBB2_27:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit52
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_31:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21BlockTranspose_KernelPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21BlockTranspose_KernelPfii,@object # @_Z21BlockTranspose_KernelPfii
.section .rodata,"a",@progbits
.globl _Z21BlockTranspose_KernelPfii
.p2align 3, 0x0
_Z21BlockTranspose_KernelPfii:
.quad _Z36__device_stub__BlockTranspose_KernelPfii
.size _Z21BlockTranspose_KernelPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "BlockTranspose_GPU: "
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ns."
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21BlockTranspose_KernelPfii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__BlockTranspose_KernelPfii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21BlockTranspose_KernelPfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z21BlockTranspose_KernelPfii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e280000002100 */
/*0050*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e680000002600 */
/*0060*/ S2R R4, SR_TID.Y ; /* 0x0000000000047919 */
/* 0x000e620000002200 */
/*0070*/ LEA R0, R0, R5, 0x2 ; /* 0x0000000500007211 */
/* 0x001fc400078e10ff */
/*0080*/ LEA R3, R3, R4, 0x2 ; /* 0x0000000403037211 */
/* 0x002fca00078e10ff */
/*0090*/ IMAD R3, R3, c[0x0][0x168], R0 ; /* 0x00005a0003037a24 */
/* 0x000fc800078e0200 */
/*00a0*/ IMAD.WIDE R2, R3, R2, c[0x0][0x160] ; /* 0x0000580003027625 */
/* 0x000fca00078e0202 */
/*00b0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ LEA R7, R4, R5, 0x1 ; /* 0x0000000504077211 */
/* 0x000fe200078e08ff */
/*00d0*/ IMAD R5, R5, 0x2, R4 ; /* 0x0000000205057824 */
/* 0x000fc800078e0204 */
/*00e0*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x004fe80000004800 */
/*00f0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0100*/ LDS R5, [R5.X4] ; /* 0x0000000005057984 */
/* 0x000e280000004800 */
/*0110*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0120*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0130*/ BRA 0x130; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21BlockTranspose_KernelPfii
.globl _Z21BlockTranspose_KernelPfii
.p2align 8
.type _Z21BlockTranspose_KernelPfii,@function
_Z21BlockTranspose_KernelPfii:
s_load_b32 s2, s[0:1], 0x8
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshl_add_u32 v1, s15, 2, v2
v_lshlrev_b32_e32 v5, 2, v3
v_lshlrev_b32_e32 v6, 2, v2
s_delay_alu instid0(VALU_DEP_2)
v_lshl_add_u32 v2, v2, 3, v5
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v1, v1, s2
s_lshl_b32 s2, s14, 2
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, s2, v3, v1
v_lshl_add_u32 v3, v3, 3, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v4, v[0:1], off
s_waitcnt vmcnt(0)
ds_store_b32 v2, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v3
s_waitcnt lgkmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21BlockTranspose_KernelPfii
.amdhsa_group_segment_fixed_size 16
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21BlockTranspose_KernelPfii, .Lfunc_end0-_Z21BlockTranspose_KernelPfii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 16
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21BlockTranspose_KernelPfii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21BlockTranspose_KernelPfii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00017d3c_00000000-6_e10.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3778:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3778:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii
.type _Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii, @function
_Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii:
.LFB3800:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
leaq 4(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z21BlockTranspose_KernelPfii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3800:
.size _Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii, .-_Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii
.globl _Z21BlockTranspose_KernelPfii
.type _Z21BlockTranspose_KernelPfii, @function
_Z21BlockTranspose_KernelPfii:
.LFB3801:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3801:
.size _Z21BlockTranspose_KernelPfii, .-_Z21BlockTranspose_KernelPfii
.globl _Z18BlockTranspose_GPUPfii
.type _Z18BlockTranspose_GPUPfii, @function
_Z18BlockTranspose_GPUPfii:
.LFB3768:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $56, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %rbp
movl %esi, %r12d
movl %edx, %r13d
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movl %esi, %ebx
imull %edx, %ebx
sall $2, %ebx
movslq %ebx, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl %r12d, %eax
shrl %eax
movl %eax, 28(%rsp)
movl %r13d, %eax
shrl %eax
movl %eax, 32(%rsp)
movl $2, 16(%rsp)
movl $2, 20(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 16(%rsp), %rdx
movl $1, %ecx
movq 28(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L15
.L12:
movl $2, %ecx
movq %rbx, %rdx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
movl %r13d, %edx
movl %r12d, %esi
movq %rbp, %rdi
call _Z43__device_stub__Z21BlockTranspose_KernelPfiiPfii
jmp .L12
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3768:
.size _Z18BlockTranspose_GPUPfii, .-_Z18BlockTranspose_GPUPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string " "
.LC2:
.string "BlockTranspose_GPU: "
.LC3:
.string "ns."
.text
.globl main
.type main, @function
main:
.LFB3769:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
movl $256, %edi
call malloc@PLT
movq %rax, %r14
movl $0, %eax
movss .LC0(%rip), %xmm1
.L18:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
addss %xmm1, %xmm0
movss %xmm0, (%r14,%rax,4)
addq $1, %rax
cmpq $64, %rax
jne .L18
leaq 32(%r14), %rbp
leaq 288(%r14), %rax
movq %rax, 8(%rsp)
movq %rbp, %r12
leaq _ZSt4cout(%rip), %r13
leaq .LC1(%rip), %r15
jmp .L19
.L35:
call _ZSt16__throw_bad_castv@PLT
.L22:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L23:
movsbl %sil, %esi
movq %r13, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $32, %r12
movq 8(%rsp), %rax
cmpq %rax, %r12
je .L24
.L19:
leaq -32(%r12), %rbx
.L20:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r13, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r15, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r12, %rbx
jne .L20
movq 0(%r13), %rax
movq -24(%rax), %rax
movq 240(%r13,%rax), %rbx
testq %rbx, %rbx
je .L35
cmpb $0, 56(%rbx)
je .L22
movzbl 67(%rbx), %esi
jmp .L23
.L24:
leaq _ZSt4cout(%rip), %r13
movq %r13, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r12
movl $8, %edx
movl $8, %esi
movq %r14, %rdi
call _Z18BlockTranspose_GPUPfii
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %rbx
leaq .LC2(%rip), %rsi
movq %r13, %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %rbx, %rsi
subq %r12, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r13, %r12
leaq .LC1(%rip), %r13
jmp .L25
.L36:
call _ZSt16__throw_bad_castv@PLT
.L28:
movq %rbx, %rdi
call _ZNKSt5ctypeIcE13_M_widen_initEv@PLT
movq (%rbx), %rax
movl $10, %esi
movq %rbx, %rdi
call *48(%rax)
movl %eax, %esi
.L29:
movsbl %sil, %esi
movq %r12, %rdi
call _ZNSo3putEc@PLT
movq %rax, %rdi
call _ZNSo5flushEv@PLT
addq $32, %rbp
movq 8(%rsp), %rax
cmpq %rax, %rbp
je .L30
.L25:
leaq -32(%rbp), %rbx
.L26:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %r13, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L26
movq (%r12), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %rbx
testq %rbx, %rbx
je .L36
cmpb $0, 56(%rbx)
je .L28
movzbl 67(%rbx), %esi
jmp .L29
.L30:
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %r14, %rdi
call free@PLT
movl $0, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3769:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z21BlockTranspose_KernelPfii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3803:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z21BlockTranspose_KernelPfii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3803:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC0:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "e10.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z36__device_stub__BlockTranspose_KernelPfii # -- Begin function _Z36__device_stub__BlockTranspose_KernelPfii
.p2align 4, 0x90
.type _Z36__device_stub__BlockTranspose_KernelPfii,@function
_Z36__device_stub__BlockTranspose_KernelPfii: # @_Z36__device_stub__BlockTranspose_KernelPfii
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 4(%rsp), %rax
movq %rax, 72(%rsp)
movq %rsp, %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z21BlockTranspose_KernelPfii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z36__device_stub__BlockTranspose_KernelPfii, .Lfunc_end0-_Z36__device_stub__BlockTranspose_KernelPfii
.cfi_endproc
# -- End function
.globl _Z18BlockTranspose_GPUPfii # -- Begin function _Z18BlockTranspose_GPUPfii
.p2align 4, 0x90
.type _Z18BlockTranspose_GPUPfii,@function
_Z18BlockTranspose_GPUPfii: # @_Z18BlockTranspose_GPUPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebp
movl %esi, %r15d
movq %rdi, %rbx
movl %esi, %eax
imull %edx, %eax
shll $2, %eax
movslq %eax, %r14
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
movq %rbx, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl %r15d, %eax
shrl %eax
movl %ebp, %edi
shrl %edi
shlq $32, %rdi
orq %rax, %rdi
movabsq $8589934594, %rdx # imm = 0x200000002
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq %rbx, 72(%rsp)
movl %r15d, 20(%rsp)
movl %ebp, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 20(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21BlockTranspose_KernelPfii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
callq hipFree
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z18BlockTranspose_GPUPfii, .Lfunc_end1-_Z18BlockTranspose_GPUPfii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI2_0:
.long 0x3f800000 # float 1
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $256, %edi # imm = 0x100
callq malloc
movq %rax, %rbx
xorl %eax, %eax
movss .LCPI2_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
xorps %xmm1, %xmm1
cvtsi2ss %eax, %xmm1
addss %xmm0, %xmm1
movss %xmm1, (%rbx,%rax,4)
incq %rax
cmpq $64, %rax
jne .LBB2_1
# %bb.2: # %.preheader61.preheader
xorl %r15d, %r15d
movq %rbx, %r12
jmp .LBB2_3
.p2align 4, 0x90
.LBB2_22: # in Loop: Header=BB2_3 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_23: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit47
# in Loop: Header=BB2_3 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $32, %r12
cmpq $8, %r15
je .LBB2_8
.LBB2_3: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_4: # Parent Loop BB2_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $8, %r14
jne .LBB2_4
# %bb.5: # in Loop: Header=BB2_3 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_31
# %bb.6: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i44
# in Loop: Header=BB2_3 Depth=1
cmpb $0, 56(%r14)
je .LBB2_22
# %bb.7: # in Loop: Header=BB2_3 Depth=1
movzbl 67(%r14), %eax
jmp .LBB2_23
.LBB2_8:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_31
# %bb.9: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB2_11
# %bb.10:
movzbl 67(%r14), %eax
jmp .LBB2_12
.LBB2_11:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_12: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r14
movq %rbx, %rdi
movl $8, %esi
movl $8, %edx
callq _Z18BlockTranspose_GPUPfii
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r15
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $20, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r14, %r15
movl $_ZSt4cout, %edi
movq %r15, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movq %rax, %r14
movl $.L.str.2, %esi
movl $3, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq (%r14), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB2_31
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i39
cmpb $0, 56(%r15)
je .LBB2_15
# %bb.14:
movzbl 67(%r15), %eax
jmp .LBB2_16
.LBB2_15:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r15), %rax
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit42
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %r15d, %r15d
movq %rbx, %r12
jmp .LBB2_17
.p2align 4, 0x90
.LBB2_21: # in Loop: Header=BB2_17 Depth=1
movzbl 67(%r14), %eax
.LBB2_30: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit57
# in Loop: Header=BB2_17 Depth=1
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
incq %r15
addq $32, %r12
cmpq $8, %r15
je .LBB2_24
.LBB2_17: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_18 Depth 2
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB2_18: # Parent Loop BB2_17 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %r14
cmpq $8, %r14
jne .LBB2_18
# %bb.19: # in Loop: Header=BB2_17 Depth=1
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_31
# %bb.20: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i54
# in Loop: Header=BB2_17 Depth=1
cmpb $0, 56(%r14)
jne .LBB2_21
# %bb.29: # in Loop: Header=BB2_17 Depth=1
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
jmp .LBB2_30
.LBB2_24:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %r14
testq %r14, %r14
je .LBB2_31
# %bb.25: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i49
cmpb $0, 56(%r14)
je .LBB2_27
# %bb.26:
movzbl 67(%r14), %eax
jmp .LBB2_28
.LBB2_27:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB2_28: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit52
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB2_31:
.cfi_def_cfa_offset 48
callq _ZSt16__throw_bad_castv
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21BlockTranspose_KernelPfii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21BlockTranspose_KernelPfii,@object # @_Z21BlockTranspose_KernelPfii
.section .rodata,"a",@progbits
.globl _Z21BlockTranspose_KernelPfii
.p2align 3, 0x0
_Z21BlockTranspose_KernelPfii:
.quad _Z36__device_stub__BlockTranspose_KernelPfii
.size _Z21BlockTranspose_KernelPfii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " "
.size .L.str, 2
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "BlockTranspose_GPU: "
.size .L.str.1, 21
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "ns."
.size .L.str.2, 4
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z21BlockTranspose_KernelPfii"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__BlockTranspose_KernelPfii
.addrsig_sym __gxx_personality_v0
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21BlockTranspose_KernelPfii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,float var_4,float var_5,float var_6,float var_7,float* var_8,float* var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32) {
if (comp > -1.5164E-37f - (+0.0f / var_4 / -1.7193E-11f - +1.7215E36f / +0.0f)) {
if (comp < var_5 + (var_6 * (+1.2714E34f + expf(sinf(+0.0f))))) {
for (int i=0; i < var_1; ++i) {
float tmp_1 = +0.0f;
comp += tmp_1 + tanhf((+0.0f / (+1.0588E-44f - +1.3267E-27f - var_7)));
comp = +1.8957E36f - -1.3050E-44f;
for (int i=0; i < var_2; ++i) {
var_8[i] = +1.9077E-41f;
comp += var_8[i] * (var_10 + (var_11 - +1.9771E0f + var_12));
var_9[i] = -0.0f;
comp += var_9[i] + (+1.3055E-17f / var_13 - tanhf((var_14 * -1.7053E-44f / var_15)));
}
for (int i=0; i < var_3; ++i) {
comp += (+1.2066E-42f / +0.0f);
float tmp_2 = -1.2245E-42f;
comp += tmp_2 - var_16 * sinf(powf((+1.7499E9f - expf((-1.6039E-12f + var_17 - var_18))), -1.1118E36f + (var_19 - (-1.5834E34f * acosf(coshf((-1.7556E11f + var_20)))))));
comp = (-0.0f + var_21 - var_22 / fmodf(+0.0f / var_23 - var_24, (+1.7953E-16f / atanf((var_25 - var_26)))));
}
if (comp <= (+1.4745E34f * var_27)) {
float tmp_3 = (var_28 - (var_29 / (var_30 / var_31 / var_32)));
comp += tmp_3 * sqrtf(-1.7494E-36f);
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float* tmp_9 = initPointer( atof(argv[9]) );
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33);
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_0001d2c8_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff
.type _Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff, @function
_Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $408, %rsp
.cfi_def_cfa_offset 416
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movl %esi, 52(%rsp)
movl %edx, 48(%rsp)
movss %xmm1, 44(%rsp)
movss %xmm2, 40(%rsp)
movss %xmm3, 36(%rsp)
movss %xmm4, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 12(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 4(%rsp), %rax
movq %rax, 224(%rsp)
leaq 416(%rsp), %rax
movq %rax, 232(%rsp)
leaq 424(%rsp), %rax
movq %rax, 240(%rsp)
leaq 432(%rsp), %rax
movq %rax, 248(%rsp)
leaq 440(%rsp), %rax
movq %rax, 256(%rsp)
leaq 448(%rsp), %rax
movq %rax, 264(%rsp)
leaq 456(%rsp), %rax
movq %rax, 272(%rsp)
leaq 464(%rsp), %rax
movq %rax, 280(%rsp)
leaq 472(%rsp), %rax
movq %rax, 288(%rsp)
leaq 480(%rsp), %rax
movq %rax, 296(%rsp)
leaq 488(%rsp), %rax
movq %rax, 304(%rsp)
leaq 496(%rsp), %rax
movq %rax, 312(%rsp)
leaq 504(%rsp), %rax
movq %rax, 320(%rsp)
leaq 512(%rsp), %rax
movq %rax, 328(%rsp)
leaq 520(%rsp), %rax
movq %rax, 336(%rsp)
leaq 528(%rsp), %rax
movq %rax, 344(%rsp)
leaq 536(%rsp), %rax
movq %rax, 352(%rsp)
leaq 544(%rsp), %rax
movq %rax, 360(%rsp)
leaq 552(%rsp), %rax
movq %rax, 368(%rsp)
leaq 560(%rsp), %rax
movq %rax, 376(%rsp)
leaq 568(%rsp), %rax
movq %rax, 384(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 424
pushq 72(%rsp)
.cfi_def_cfa_offset 432
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefiiiffffPfS_fffffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff, .-_Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff
.globl _Z7computefiiiffffPfS_fffffffffffffffffffffff
.type _Z7computefiiiffffPfS_fffffffffffffffffffffff, @function
_Z7computefiiiffffPfS_fffffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movss 328(%rsp), %xmm8
movss %xmm8, 152(%rsp)
movss 320(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiiiffffPfS_fffffffffffffffffffffff, .-_Z7computefiiiffffPfS_fffffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 208(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r15
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 240(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 248(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 256(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 264(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 244(%rsp)
movl $1, 248(%rsp)
movl $1, 232(%rsp)
movl $1, 236(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 244(%rsp), %rdx
movl $1, %ecx
movq 232(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 216(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -160(%rsp), %rsp
.cfi_def_cfa_offset 480
movss %xmm1, 152(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 312(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 320(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 328(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 336(%rsp), %xmm5
movq %r15, %r8
movq %r14, %rcx
pxor %xmm4, %xmm4
cvtsd2ss 344(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 352(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 360(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 368(%rsp), %xmm1
movl %r13d, %edx
movl %r12d, %esi
movl %ebp, %edi
call _Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff
addq $160, %rsp
.cfi_def_cfa_offset 320
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiiiffffPfS_fffffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiiiffffPfS_fffffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /* This is a automatically generated test. Do not modify */
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,float var_4,float var_5,float var_6,float var_7,float* var_8,float* var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32) {
if (comp > -1.5164E-37f - (+0.0f / var_4 / -1.7193E-11f - +1.7215E36f / +0.0f)) {
if (comp < var_5 + (var_6 * (+1.2714E34f + expf(sinf(+0.0f))))) {
for (int i=0; i < var_1; ++i) {
float tmp_1 = +0.0f;
comp += tmp_1 + tanhf((+0.0f / (+1.0588E-44f - +1.3267E-27f - var_7)));
comp = +1.8957E36f - -1.3050E-44f;
for (int i=0; i < var_2; ++i) {
var_8[i] = +1.9077E-41f;
comp += var_8[i] * (var_10 + (var_11 - +1.9771E0f + var_12));
var_9[i] = -0.0f;
comp += var_9[i] + (+1.3055E-17f / var_13 - tanhf((var_14 * -1.7053E-44f / var_15)));
}
for (int i=0; i < var_3; ++i) {
comp += (+1.2066E-42f / +0.0f);
float tmp_2 = -1.2245E-42f;
comp += tmp_2 - var_16 * sinf(powf((+1.7499E9f - expf((-1.6039E-12f + var_17 - var_18))), -1.1118E36f + (var_19 - (-1.5834E34f * acosf(coshf((-1.7556E11f + var_20)))))));
comp = (-0.0f + var_21 - var_22 / fmodf(+0.0f / var_23 - var_24, (+1.7953E-16f / atanf((var_25 - var_26)))));
}
if (comp <= (+1.4745E34f * var_27)) {
float tmp_3 = (var_28 - (var_29 / (var_30 / var_31 / var_32)));
comp += tmp_3 * sqrtf(-1.7494E-36f);
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float* tmp_9 = initPointer( atof(argv[9]) );
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33);
cudaDeviceSynchronize();
return 0;
} | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,float var_4,float var_5,float var_6,float var_7,float* var_8,float* var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32) {
if (comp > -1.5164E-37f - (+0.0f / var_4 / -1.7193E-11f - +1.7215E36f / +0.0f)) {
if (comp < var_5 + (var_6 * (+1.2714E34f + expf(sinf(+0.0f))))) {
for (int i=0; i < var_1; ++i) {
float tmp_1 = +0.0f;
comp += tmp_1 + tanhf((+0.0f / (+1.0588E-44f - +1.3267E-27f - var_7)));
comp = +1.8957E36f - -1.3050E-44f;
for (int i=0; i < var_2; ++i) {
var_8[i] = +1.9077E-41f;
comp += var_8[i] * (var_10 + (var_11 - +1.9771E0f + var_12));
var_9[i] = -0.0f;
comp += var_9[i] + (+1.3055E-17f / var_13 - tanhf((var_14 * -1.7053E-44f / var_15)));
}
for (int i=0; i < var_3; ++i) {
comp += (+1.2066E-42f / +0.0f);
float tmp_2 = -1.2245E-42f;
comp += tmp_2 - var_16 * sinf(powf((+1.7499E9f - expf((-1.6039E-12f + var_17 - var_18))), -1.1118E36f + (var_19 - (-1.5834E34f * acosf(coshf((-1.7556E11f + var_20)))))));
comp = (-0.0f + var_21 - var_22 / fmodf(+0.0f / var_23 - var_24, (+1.7953E-16f / atanf((var_25 - var_26)))));
}
if (comp <= (+1.4745E34f * var_27)) {
float tmp_3 = (var_28 - (var_29 / (var_30 / var_31 / var_32)));
comp += tmp_3 * sqrtf(-1.7494E-36f);
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float* tmp_9 = initPointer( atof(argv[9]) );
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33);
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /* This is a automatically generated test. Do not modify */
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
__global__
void compute(float comp, int var_1,int var_2,int var_3,float var_4,float var_5,float var_6,float var_7,float* var_8,float* var_9,float var_10,float var_11,float var_12,float var_13,float var_14,float var_15,float var_16,float var_17,float var_18,float var_19,float var_20,float var_21,float var_22,float var_23,float var_24,float var_25,float var_26,float var_27,float var_28,float var_29,float var_30,float var_31,float var_32) {
if (comp > -1.5164E-37f - (+0.0f / var_4 / -1.7193E-11f - +1.7215E36f / +0.0f)) {
if (comp < var_5 + (var_6 * (+1.2714E34f + expf(sinf(+0.0f))))) {
for (int i=0; i < var_1; ++i) {
float tmp_1 = +0.0f;
comp += tmp_1 + tanhf((+0.0f / (+1.0588E-44f - +1.3267E-27f - var_7)));
comp = +1.8957E36f - -1.3050E-44f;
for (int i=0; i < var_2; ++i) {
var_8[i] = +1.9077E-41f;
comp += var_8[i] * (var_10 + (var_11 - +1.9771E0f + var_12));
var_9[i] = -0.0f;
comp += var_9[i] + (+1.3055E-17f / var_13 - tanhf((var_14 * -1.7053E-44f / var_15)));
}
for (int i=0; i < var_3; ++i) {
comp += (+1.2066E-42f / +0.0f);
float tmp_2 = -1.2245E-42f;
comp += tmp_2 - var_16 * sinf(powf((+1.7499E9f - expf((-1.6039E-12f + var_17 - var_18))), -1.1118E36f + (var_19 - (-1.5834E34f * acosf(coshf((-1.7556E11f + var_20)))))));
comp = (-0.0f + var_21 - var_22 / fmodf(+0.0f / var_23 - var_24, (+1.7953E-16f / atanf((var_25 - var_26)))));
}
if (comp <= (+1.4745E34f * var_27)) {
float tmp_3 = (var_28 - (var_29 / (var_30 / var_31 / var_32)));
comp += tmp_3 * sqrtf(-1.7494E-36f);
}
}
}
}
printf("%.17g\n", comp);
}
float* initPointer(float v) {
float *ret = (float*) malloc(sizeof(float)*10);
for(int i=0; i < 10; ++i)
ret[i] = v;
return ret;
}
int main(int argc, char** argv) {
/* Program variables */
float tmp_1 = atof(argv[1]);
int tmp_2 = atoi(argv[2]);
int tmp_3 = atoi(argv[3]);
int tmp_4 = atoi(argv[4]);
float tmp_5 = atof(argv[5]);
float tmp_6 = atof(argv[6]);
float tmp_7 = atof(argv[7]);
float tmp_8 = atof(argv[8]);
float* tmp_9 = initPointer( atof(argv[9]) );
float* tmp_10 = initPointer( atof(argv[10]) );
float tmp_11 = atof(argv[11]);
float tmp_12 = atof(argv[12]);
float tmp_13 = atof(argv[13]);
float tmp_14 = atof(argv[14]);
float tmp_15 = atof(argv[15]);
float tmp_16 = atof(argv[16]);
float tmp_17 = atof(argv[17]);
float tmp_18 = atof(argv[18]);
float tmp_19 = atof(argv[19]);
float tmp_20 = atof(argv[20]);
float tmp_21 = atof(argv[21]);
float tmp_22 = atof(argv[22]);
float tmp_23 = atof(argv[23]);
float tmp_24 = atof(argv[24]);
float tmp_25 = atof(argv[25]);
float tmp_26 = atof(argv[26]);
float tmp_27 = atof(argv[27]);
float tmp_28 = atof(argv[28]);
float tmp_29 = atof(argv[29]);
float tmp_30 = atof(argv[30]);
float tmp_31 = atof(argv[31]);
float tmp_32 = atof(argv[32]);
float tmp_33 = atof(argv[33]);
compute<<<1,1>>>(tmp_1,tmp_2,tmp_3,tmp_4,tmp_5,tmp_6,tmp_7,tmp_8,tmp_9,tmp_10,tmp_11,tmp_12,tmp_13,tmp_14,tmp_15,tmp_16,tmp_17,tmp_18,tmp_19,tmp_20,tmp_21,tmp_22,tmp_23,tmp_24,tmp_25,tmp_26,tmp_27,tmp_28,tmp_29,tmp_30,tmp_31,tmp_32,tmp_33);
hipDeviceSynchronize();
return 0;
} | .text
.file "test.hip"
.globl _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff # -- Begin function _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff,@function
_Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff: # @_Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 384
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movq %rcx, 104(%rsp)
movq %r8, 96(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
leaq 384(%rsp), %rax
movq %rax, 216(%rsp)
leaq 392(%rsp), %rax
movq %rax, 224(%rsp)
leaq 400(%rsp), %rax
movq %rax, 232(%rsp)
leaq 408(%rsp), %rax
movq %rax, 240(%rsp)
leaq 416(%rsp), %rax
movq %rax, 248(%rsp)
leaq 424(%rsp), %rax
movq %rax, 256(%rsp)
leaq 432(%rsp), %rax
movq %rax, 264(%rsp)
leaq 440(%rsp), %rax
movq %rax, 272(%rsp)
leaq 448(%rsp), %rax
movq %rax, 280(%rsp)
leaq 456(%rsp), %rax
movq %rax, 288(%rsp)
leaq 464(%rsp), %rax
movq %rax, 296(%rsp)
leaq 472(%rsp), %rax
movq %rax, 304(%rsp)
leaq 480(%rsp), %rax
movq %rax, 312(%rsp)
leaq 488(%rsp), %rax
movq %rax, 320(%rsp)
leaq 496(%rsp), %rax
movq %rax, 328(%rsp)
leaq 504(%rsp), %rax
movq %rax, 336(%rsp)
leaq 512(%rsp), %rax
movq %rax, 344(%rsp)
leaq 520(%rsp), %rax
movq %rax, 352(%rsp)
leaq 528(%rsp), %rax
movq %rax, 360(%rsp)
leaq 536(%rsp), %rax
movq %rax, 368(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefiiiffffPfS_fffffffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $392, %rsp # imm = 0x188
.cfi_adjust_cfa_offset -392
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 448
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r13
movq 8(%rsi), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq strtod
movsd %xmm0, 376(%rsp) # 8-byte Spill
movq 16(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 384(%rsp) # 8-byte Spill
movq 24(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 40(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 368(%rsp) # 8-byte Spill
movq 48(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 56(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 64(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 72(%r13), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 160(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%rbp,4)
incq %rbp
cmpq $10, %rbp
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 80(%r13), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 160(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %rbp
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit70
movq 88(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 96(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 104(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 112(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 120(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 128(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 136(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 144(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 152(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 160(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 168(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 176(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 184(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 192(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 200(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 208(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 216(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 224(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 232(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 240(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 248(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 256(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 264(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp) # 4-byte Spill
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 240(%rsp) # 4-byte Spill
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 248(%rsp) # 4-byte Spill
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 368(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 376(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 152(%rsp)
movss %xmm9, 144(%rsp)
movss %xmm10, 136(%rsp)
movss %xmm11, 128(%rsp)
movss %xmm12, 120(%rsp)
movss %xmm13, 112(%rsp)
movss %xmm14, 104(%rsp)
movss %xmm15, 96(%rsp)
movss %xmm3, 88(%rsp)
movss %xmm4, 80(%rsp)
movss %xmm5, 72(%rsp)
movss %xmm6, 64(%rsp)
movss %xmm7, 56(%rsp)
movss 168(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 48(%rsp)
movss 176(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 40(%rsp)
movss 184(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 32(%rsp)
movss 192(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 24(%rsp)
movss 200(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 16(%rsp)
movss 208(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 8(%rsp)
movss 216(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, (%rsp)
movq 384(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi
movl %r14d, %esi
movl %r15d, %edx
movss 248(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 240(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movq %r12, %rcx
movq %rbp, %r8
movss 160(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 232(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 224(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.LBB2_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiiiffffPfS_fffffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiiiffffPfS_fffffffffffffffffffffff,@object # @_Z7computefiiiffffPfS_fffffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiiiffffPfS_fffffffffffffffffffffff
.p2align 3, 0x0
_Z7computefiiiffffPfS_fffffffffffffffffffffff:
.quad _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.size _Z7computefiiiffffPfS_fffffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiiiffffPfS_fffffffffffffffffffffff"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiiiffffPfS_fffffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0001d2c8_00000000-6_test.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z11initPointerf
.type _Z11initPointerf, @function
_Z11initPointerf:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movd %xmm0, %ebx
movl $40, %edi
call malloc@PLT
movq %rax, %rdx
leaq 40(%rax), %rcx
.L4:
movl %ebx, (%rdx)
addq $4, %rdx
cmpq %rcx, %rdx
jne .L4
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z11initPointerf, .-_Z11initPointerf
.globl _Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff
.type _Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff, @function
_Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff:
.LFB2083:
.cfi_startproc
endbr64
subq $408, %rsp
.cfi_def_cfa_offset 416
movss %xmm0, 60(%rsp)
movl %edi, 56(%rsp)
movl %esi, 52(%rsp)
movl %edx, 48(%rsp)
movss %xmm1, 44(%rsp)
movss %xmm2, 40(%rsp)
movss %xmm3, 36(%rsp)
movss %xmm4, 32(%rsp)
movq %rcx, 24(%rsp)
movq %r8, 16(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
movq %fs:40, %rax
movq %rax, 392(%rsp)
xorl %eax, %eax
leaq 60(%rsp), %rax
movq %rax, 128(%rsp)
leaq 56(%rsp), %rax
movq %rax, 136(%rsp)
leaq 52(%rsp), %rax
movq %rax, 144(%rsp)
leaq 48(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 32(%rsp), %rax
movq %rax, 184(%rsp)
leaq 24(%rsp), %rax
movq %rax, 192(%rsp)
leaq 16(%rsp), %rax
movq %rax, 200(%rsp)
leaq 12(%rsp), %rax
movq %rax, 208(%rsp)
leaq 8(%rsp), %rax
movq %rax, 216(%rsp)
leaq 4(%rsp), %rax
movq %rax, 224(%rsp)
leaq 416(%rsp), %rax
movq %rax, 232(%rsp)
leaq 424(%rsp), %rax
movq %rax, 240(%rsp)
leaq 432(%rsp), %rax
movq %rax, 248(%rsp)
leaq 440(%rsp), %rax
movq %rax, 256(%rsp)
leaq 448(%rsp), %rax
movq %rax, 264(%rsp)
leaq 456(%rsp), %rax
movq %rax, 272(%rsp)
leaq 464(%rsp), %rax
movq %rax, 280(%rsp)
leaq 472(%rsp), %rax
movq %rax, 288(%rsp)
leaq 480(%rsp), %rax
movq %rax, 296(%rsp)
leaq 488(%rsp), %rax
movq %rax, 304(%rsp)
leaq 496(%rsp), %rax
movq %rax, 312(%rsp)
leaq 504(%rsp), %rax
movq %rax, 320(%rsp)
leaq 512(%rsp), %rax
movq %rax, 328(%rsp)
leaq 520(%rsp), %rax
movq %rax, 336(%rsp)
leaq 528(%rsp), %rax
movq %rax, 344(%rsp)
leaq 536(%rsp), %rax
movq %rax, 352(%rsp)
leaq 544(%rsp), %rax
movq %rax, 360(%rsp)
leaq 552(%rsp), %rax
movq %rax, 368(%rsp)
leaq 560(%rsp), %rax
movq %rax, 376(%rsp)
leaq 568(%rsp), %rax
movq %rax, 384(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
movl $1, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $1, 100(%rsp)
leaq 72(%rsp), %rcx
leaq 64(%rsp), %rdx
leaq 92(%rsp), %rsi
leaq 80(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 392(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $408, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 72(%rsp)
.cfi_def_cfa_offset 424
pushq 72(%rsp)
.cfi_def_cfa_offset 432
leaq 144(%rsp), %r9
movq 108(%rsp), %rcx
movl 116(%rsp), %r8d
movq 96(%rsp), %rsi
movl 104(%rsp), %edx
leaq _Z7computefiiiffffPfS_fffffffffffffffffffffff(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 416
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff, .-_Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff
.globl _Z7computefiiiffffPfS_fffffffffffffffffffffff
.type _Z7computefiiiffffPfS_fffffffffffffffffffffff, @function
_Z7computefiiiffffPfS_fffffffffffffffffffffff:
.LFB2084:
.cfi_startproc
endbr64
subq $168, %rsp
.cfi_def_cfa_offset 176
movss 328(%rsp), %xmm8
movss %xmm8, 152(%rsp)
movss 320(%rsp), %xmm8
movss %xmm8, 144(%rsp)
movss 312(%rsp), %xmm8
movss %xmm8, 136(%rsp)
movss 304(%rsp), %xmm8
movss %xmm8, 128(%rsp)
movss 296(%rsp), %xmm8
movss %xmm8, 120(%rsp)
movss 288(%rsp), %xmm8
movss %xmm8, 112(%rsp)
movss 280(%rsp), %xmm8
movss %xmm8, 104(%rsp)
movss 272(%rsp), %xmm8
movss %xmm8, 96(%rsp)
movss 264(%rsp), %xmm8
movss %xmm8, 88(%rsp)
movss 256(%rsp), %xmm8
movss %xmm8, 80(%rsp)
movss 248(%rsp), %xmm8
movss %xmm8, 72(%rsp)
movss 240(%rsp), %xmm8
movss %xmm8, 64(%rsp)
movss 232(%rsp), %xmm8
movss %xmm8, 56(%rsp)
movss 224(%rsp), %xmm8
movss %xmm8, 48(%rsp)
movss 216(%rsp), %xmm8
movss %xmm8, 40(%rsp)
movss 208(%rsp), %xmm8
movss %xmm8, 32(%rsp)
movss 200(%rsp), %xmm8
movss %xmm8, 24(%rsp)
movss 192(%rsp), %xmm8
movss %xmm8, 16(%rsp)
movss 184(%rsp), %xmm8
movss %xmm8, 8(%rsp)
movss 176(%rsp), %xmm8
movss %xmm8, (%rsp)
call _Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff
addq $168, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z7computefiiiffffPfS_fffffffffffffffffffffff, .-_Z7computefiiiffffPfS_fffffffffffffffffffffff
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $264, %rsp
.cfi_def_cfa_offset 320
movq %rsi, %rbx
movq 8(%rsi), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 216(%rsp)
movq 16(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbp
movq 24(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r12
movq 32(%rbx), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movq 40(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 208(%rsp)
movq 48(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 200(%rsp)
movq 56(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 192(%rsp)
movq 64(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 184(%rsp)
movq 72(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r14
movq 80(%rbx), %rdi
movl $0, %esi
call strtod@PLT
cvtsd2ss %xmm0, %xmm0
call _Z11initPointerf
movq %rax, %r15
movq 88(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 176(%rsp)
movq 96(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 168(%rsp)
movq 104(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 160(%rsp)
movq 112(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 152(%rsp)
movq 120(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 144(%rsp)
movq 128(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 136(%rsp)
movq 136(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 128(%rsp)
movq 144(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 120(%rsp)
movq 152(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 112(%rsp)
movq 160(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 104(%rsp)
movq 168(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 96(%rsp)
movq 176(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 88(%rsp)
movq 184(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 80(%rsp)
movq 192(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 72(%rsp)
movq 200(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 64(%rsp)
movq 208(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 56(%rsp)
movq 216(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 48(%rsp)
movq 224(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 40(%rsp)
movq 232(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 32(%rsp)
movq 240(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 24(%rsp)
movq 248(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 16(%rsp)
movq 256(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, 8(%rsp)
movq 264(%rbx), %rdi
movl $0, %esi
call strtod@PLT
movsd %xmm0, (%rsp)
movl $1, 244(%rsp)
movl $1, 248(%rsp)
movl $1, 232(%rsp)
movl $1, 236(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 244(%rsp), %rdx
movl $1, %ecx
movq 232(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L16:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $264, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
pxor %xmm0, %xmm0
cvtsd2ss 216(%rsp), %xmm0
pxor %xmm1, %xmm1
cvtsd2ss (%rsp), %xmm1
leaq -160(%rsp), %rsp
.cfi_def_cfa_offset 480
movss %xmm1, 152(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 168(%rsp), %xmm1
movss %xmm1, 144(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 176(%rsp), %xmm1
movss %xmm1, 136(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 184(%rsp), %xmm1
movss %xmm1, 128(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 192(%rsp), %xmm1
movss %xmm1, 120(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 200(%rsp), %xmm1
movss %xmm1, 112(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 208(%rsp), %xmm1
movss %xmm1, 104(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 216(%rsp), %xmm1
movss %xmm1, 96(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 224(%rsp), %xmm1
movss %xmm1, 88(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 232(%rsp), %xmm1
movss %xmm1, 80(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 240(%rsp), %xmm1
movss %xmm1, 72(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 248(%rsp), %xmm1
movss %xmm1, 64(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 256(%rsp), %xmm1
movss %xmm1, 56(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 264(%rsp), %xmm1
movss %xmm1, 48(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 272(%rsp), %xmm1
movss %xmm1, 40(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 280(%rsp), %xmm1
movss %xmm1, 32(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 288(%rsp), %xmm1
movss %xmm1, 24(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 296(%rsp), %xmm1
movss %xmm1, 16(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 304(%rsp), %xmm1
movss %xmm1, 8(%rsp)
pxor %xmm1, %xmm1
cvtsd2ss 312(%rsp), %xmm1
movss %xmm1, (%rsp)
pxor %xmm7, %xmm7
cvtsd2ss 320(%rsp), %xmm7
pxor %xmm6, %xmm6
cvtsd2ss 328(%rsp), %xmm6
pxor %xmm5, %xmm5
cvtsd2ss 336(%rsp), %xmm5
movq %r15, %r8
movq %r14, %rcx
pxor %xmm4, %xmm4
cvtsd2ss 344(%rsp), %xmm4
pxor %xmm3, %xmm3
cvtsd2ss 352(%rsp), %xmm3
pxor %xmm2, %xmm2
cvtsd2ss 360(%rsp), %xmm2
pxor %xmm1, %xmm1
cvtsd2ss 368(%rsp), %xmm1
movl %r13d, %edx
movl %r12d, %esi
movl %ebp, %edi
call _Z59__device_stub__Z7computefiiiffffPfS_ffffffffffffffffffffffffiiiffffPfS_fffffffffffffffffffffff
addq $160, %rsp
.cfi_def_cfa_offset 320
jmp .L16
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z7computefiiiffffPfS_fffffffffffffffffffffff"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7computefiiiffffPfS_fffffffffffffffffffffff(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "test.hip"
.globl _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff # -- Begin function _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.p2align 4, 0x90
.type _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff,@function
_Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff: # @_Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.cfi_startproc
# %bb.0:
subq $376, %rsp # imm = 0x178
.cfi_def_cfa_offset 384
movss %xmm0, 44(%rsp)
movl %edi, 40(%rsp)
movl %esi, 36(%rsp)
movl %edx, 32(%rsp)
movss %xmm1, 28(%rsp)
movss %xmm2, 24(%rsp)
movss %xmm3, 20(%rsp)
movss %xmm4, 16(%rsp)
movq %rcx, 104(%rsp)
movq %r8, 96(%rsp)
movss %xmm5, 12(%rsp)
movss %xmm6, 8(%rsp)
movss %xmm7, 4(%rsp)
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 24(%rsp), %rax
movq %rax, 152(%rsp)
leaq 20(%rsp), %rax
movq %rax, 160(%rsp)
leaq 16(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 12(%rsp), %rax
movq %rax, 192(%rsp)
leaq 8(%rsp), %rax
movq %rax, 200(%rsp)
leaq 4(%rsp), %rax
movq %rax, 208(%rsp)
leaq 384(%rsp), %rax
movq %rax, 216(%rsp)
leaq 392(%rsp), %rax
movq %rax, 224(%rsp)
leaq 400(%rsp), %rax
movq %rax, 232(%rsp)
leaq 408(%rsp), %rax
movq %rax, 240(%rsp)
leaq 416(%rsp), %rax
movq %rax, 248(%rsp)
leaq 424(%rsp), %rax
movq %rax, 256(%rsp)
leaq 432(%rsp), %rax
movq %rax, 264(%rsp)
leaq 440(%rsp), %rax
movq %rax, 272(%rsp)
leaq 448(%rsp), %rax
movq %rax, 280(%rsp)
leaq 456(%rsp), %rax
movq %rax, 288(%rsp)
leaq 464(%rsp), %rax
movq %rax, 296(%rsp)
leaq 472(%rsp), %rax
movq %rax, 304(%rsp)
leaq 480(%rsp), %rax
movq %rax, 312(%rsp)
leaq 488(%rsp), %rax
movq %rax, 320(%rsp)
leaq 496(%rsp), %rax
movq %rax, 328(%rsp)
leaq 504(%rsp), %rax
movq %rax, 336(%rsp)
leaq 512(%rsp), %rax
movq %rax, 344(%rsp)
leaq 520(%rsp), %rax
movq %rax, 352(%rsp)
leaq 528(%rsp), %rax
movq %rax, 360(%rsp)
leaq 536(%rsp), %rax
movq %rax, 368(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z7computefiiiffffPfS_fffffffffffffffffffffff, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $392, %rsp # imm = 0x188
.cfi_adjust_cfa_offset -392
retq
.Lfunc_end0:
.size _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff, .Lfunc_end0-_Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.cfi_endproc
# -- End function
.globl _Z11initPointerf # -- Begin function _Z11initPointerf
.p2align 4, 0x90
.type _Z11initPointerf,@function
_Z11initPointerf: # @_Z11initPointerf
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movss %xmm0, 4(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 4(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rax,%rcx,4)
incq %rcx
cmpq $10, %rcx
jne .LBB1_1
# %bb.2:
popq %rcx
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z11initPointerf, .Lfunc_end1-_Z11initPointerf
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 448
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %r13
movq 8(%rsi), %rdi
xorl %ebp, %ebp
xorl %esi, %esi
callq strtod
movsd %xmm0, 376(%rsp) # 8-byte Spill
movq 16(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, 384(%rsp) # 8-byte Spill
movq 24(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 32(%r13), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq 40(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 368(%rsp) # 8-byte Spill
movq 48(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 360(%rsp) # 8-byte Spill
movq 56(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 248(%rsp) # 8-byte Spill
movq 64(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 240(%rsp) # 8-byte Spill
movq 72(%r13), %rdi
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 160(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %r12
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%r12,%rbp,4)
incq %rbp
cmpq $10, %rbp
jne .LBB2_1
# %bb.2: # %_Z11initPointerf.exit
movq 80(%r13), %rdi
xorl %ebx, %ebx
xorl %esi, %esi
callq strtod
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movl $40, %edi
callq malloc
movss 160(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movq %rax, %rbp
.p2align 4, 0x90
.LBB2_3: # =>This Inner Loop Header: Depth=1
movss %xmm0, (%rbp,%rbx,4)
incq %rbx
cmpq $10, %rbx
jne .LBB2_3
# %bb.4: # %_Z11initPointerf.exit70
movq 88(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 160(%rsp) # 8-byte Spill
movq 96(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 232(%rsp) # 8-byte Spill
movq 104(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 224(%rsp) # 8-byte Spill
movq 112(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 216(%rsp) # 8-byte Spill
movq 120(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 208(%rsp) # 8-byte Spill
movq 128(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 200(%rsp) # 8-byte Spill
movq 136(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 192(%rsp) # 8-byte Spill
movq 144(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 184(%rsp) # 8-byte Spill
movq 152(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 176(%rsp) # 8-byte Spill
movq 160(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 168(%rsp) # 8-byte Spill
movq 168(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 352(%rsp) # 8-byte Spill
movq 176(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 344(%rsp) # 8-byte Spill
movq 184(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 336(%rsp) # 8-byte Spill
movq 192(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 328(%rsp) # 8-byte Spill
movq 200(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 320(%rsp) # 8-byte Spill
movq 208(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 312(%rsp) # 8-byte Spill
movq 216(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 304(%rsp) # 8-byte Spill
movq 224(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 296(%rsp) # 8-byte Spill
movq 232(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 288(%rsp) # 8-byte Spill
movq 240(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 280(%rsp) # 8-byte Spill
movq 248(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 272(%rsp) # 8-byte Spill
movq 256(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 264(%rsp) # 8-byte Spill
movq 264(%r13), %rdi
xorl %esi, %esi
callq strtod
movsd %xmm0, 256(%rsp) # 8-byte Spill
movabsq $4294967297, %rdi # imm = 0x100000001
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movsd 256(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm8
movsd 264(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm9
movsd 272(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm10
movsd 280(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm11
movsd 288(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm12
movsd 296(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm13
movsd 304(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm14
movsd 312(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm15
movsd 320(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm3
movsd 328(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm4
movsd 336(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm5
movsd 344(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm6
movsd 352(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm7
movsd 168(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 168(%rsp) # 4-byte Spill
movsd 176(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 176(%rsp) # 4-byte Spill
movsd 184(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 184(%rsp) # 4-byte Spill
movsd 192(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 192(%rsp) # 4-byte Spill
movsd 200(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 200(%rsp) # 4-byte Spill
movsd 208(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 208(%rsp) # 4-byte Spill
movsd 216(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 216(%rsp) # 4-byte Spill
movsd 224(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 224(%rsp) # 4-byte Spill
movsd 232(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 232(%rsp) # 4-byte Spill
movsd 160(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 160(%rsp) # 4-byte Spill
movsd 240(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 240(%rsp) # 4-byte Spill
movsd 248(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 248(%rsp) # 4-byte Spill
movsd 360(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm2
movsd 368(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm1
movsd 376(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
cvtsd2ss %xmm0, %xmm0
movss %xmm8, 152(%rsp)
movss %xmm9, 144(%rsp)
movss %xmm10, 136(%rsp)
movss %xmm11, 128(%rsp)
movss %xmm12, 120(%rsp)
movss %xmm13, 112(%rsp)
movss %xmm14, 104(%rsp)
movss %xmm15, 96(%rsp)
movss %xmm3, 88(%rsp)
movss %xmm4, 80(%rsp)
movss %xmm5, 72(%rsp)
movss %xmm6, 64(%rsp)
movss %xmm7, 56(%rsp)
movss 168(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 48(%rsp)
movss 176(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 40(%rsp)
movss 184(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 32(%rsp)
movss 192(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 24(%rsp)
movss 200(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 16(%rsp)
movss 208(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, 8(%rsp)
movss 216(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss %xmm3, (%rsp)
movq 384(%rsp), %rdi # 8-byte Reload
# kill: def $edi killed $edi killed $rdi
movl %r14d, %esi
movl %r15d, %edx
movss 248(%rsp), %xmm3 # 4-byte Reload
# xmm3 = mem[0],zero,zero,zero
movss 240(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
movq %r12, %rcx
movq %rbp, %r8
movss 160(%rsp), %xmm5 # 4-byte Reload
# xmm5 = mem[0],zero,zero,zero
movss 232(%rsp), %xmm6 # 4-byte Reload
# xmm6 = mem[0],zero,zero,zero
movss 224(%rsp), %xmm7 # 4-byte Reload
# xmm7 = mem[0],zero,zero,zero
callq _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.LBB2_6:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $392, %rsp # imm = 0x188
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7computefiiiffffPfS_fffffffffffffffffffffff, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7computefiiiffffPfS_fffffffffffffffffffffff,@object # @_Z7computefiiiffffPfS_fffffffffffffffffffffff
.section .rodata,"a",@progbits
.globl _Z7computefiiiffffPfS_fffffffffffffffffffffff
.p2align 3, 0x0
_Z7computefiiiffffPfS_fffffffffffffffffffffff:
.quad _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.size _Z7computefiiiffffPfS_fffffffffffffffffffffff, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7computefiiiffffPfS_fffffffffffffffffffffff"
.size .L__unnamed_1, 46
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__computefiiiffffPfS_fffffffffffffffffffffff
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7computefiiiffffPfS_fffffffffffffffffffffff
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void initmem( int Ntot, float *a ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < Ntot ) a[idx] = 0;
}
__global__ void diff( int Nx, int Ny, float dx, float *a, float *da ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < (Nx-1)*(Ny-1) ) da[idx] = (1/dx)*( a[idx+Ny+1] - a[idx] );
} | code for sm_80
Function : _Z4diffiifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe4000fffe13f */
/*0060*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fc8000fffe13f */
/*0070*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R4, R0, c[0x0][0x164], RZ ; /* 0x0000590000047a10 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe400078e0207 */
/*0100*/ LDG.E R5, [R4.64+0x4] ; /* 0x0000040404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff087624 */
/* 0x000fca00078e00ff */
/*0130*/ IADD3 R3, R8, 0x1800000, RZ ; /* 0x0180000008037810 */
/* 0x000fc80007ffe0ff */
/*0140*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000003037812 */
/* 0x000fc800078ec0ff */
/*0150*/ ISETP.GT.U32.AND P0, PT, R3, 0x1ffffff, PT ; /* 0x01ffffff0300780c */
/* 0x000fe20003f04070 */
/*0160*/ FADD R2, -R2, R5 ; /* 0x0000000502027221 */
/* 0x004fd80000000100 */
/*0170*/ @P0 BRA 0x1b0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0180*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe40000000f00 */
/*0190*/ CALL.REL.NOINC 0x240 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*01a0*/ BRA 0x1f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*01b0*/ MUFU.RCP R3, c[0x0][0x168] ; /* 0x00005a0000037b08 */
/* 0x000e240000001000 */
/*01c0*/ FFMA R4, R3, R8, -1 ; /* 0xbf80000003047423 */
/* 0x001fc80000000008 */
/*01d0*/ FADD.FTZ R4, -R4, -RZ ; /* 0x800000ff04047221 */
/* 0x000fc80000010100 */
/*01e0*/ FFMA R3, R3, R4, R3 ; /* 0x0000000403037223 */
/* 0x000fe40000000003 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0200*/ FMUL R5, R2, R3 ; /* 0x0000000302057220 */
/* 0x001fe40000400000 */
/*0210*/ IMAD.WIDE R2, R0, R7, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0207 */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.SHL.U32 R5, R10, 0x2, RZ ; /* 0x000000020a057824 */
/* 0x000fca00078e00ff */
/*0260*/ SHF.R.U32.HI R3, RZ, 0x18, R5 ; /* 0x00000018ff037819 */
/* 0x000fc80000011605 */
/*0270*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05070 */
/*0280*/ @P0 BRA 0x330 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*02a0*/ @!P0 MUFU.RCP R3, c[0x0][0x168] ; /* 0x00005a0000038b08 */
/* 0x000e220000001000 */
/*02b0*/ @!P0 BRA 0x550 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*02c0*/ FFMA R5, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a057823 */
/* 0x000fc800000000ff */
/*02d0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e640000001000 */
/*02e0*/ FFMA R3, R5, R6, -1 ; /* 0xbf80000005037423 */
/* 0x003fc80000000006 */
/*02f0*/ FADD.FTZ R3, -R3, -RZ ; /* 0x800000ff03037221 */
/* 0x000fc80000010100 */
/*0300*/ FFMA R3, R6, R3, R6 ; /* 0x0000000306037223 */
/* 0x000fc80000000006 */
/*0310*/ FFMA R3, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003037823 */
/* 0x000fe200000000ff */
/*0320*/ BRA 0x550 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R5, R3, -0xfd, RZ ; /* 0xffffff0303057810 */
/* 0x000fc80007ffe0ff */
/*0340*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f04070 */
/*0350*/ @P0 BRA 0x540 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT R6, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a067812 */
/* 0x000fe200078ec0ff */
/*0370*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3 ; /* 0x00000003ff0c7424 */
/* 0x000fe200078e00ff */
/*0380*/ IADD3 R3, R3, -0xfc, RZ ; /* 0xffffff0403037810 */
/* 0x000fe40007ffe0ff */
/*0390*/ LOP3.LUT R6, R6, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000006067812 */
/* 0x000fe400078efcff */
/*03a0*/ SHF.L.U32 R11, R12, R5, RZ ; /* 0x000000050c0b7219 */
/* 0x000fe400000006ff */
/*03b0*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x000e240000001000 */
/*03c0*/ FFMA R8, R6, R7, -1 ; /* 0xbf80000006087423 */
/* 0x001fc80000000007 */
/*03d0*/ FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08087221 */
/* 0x000fc80000010100 */
/*03e0*/ FFMA.RM R9, R7.reuse, R8.reuse, R7.reuse ; /* 0x0000000807097223 */
/* 0x1c0fe40000004007 */
/*03f0*/ FFMA.RP R8, R7, R8, R7 ; /* 0x0000000807087223 */
/* 0x000fc60000008007 */
/*0400*/ LOP3.LUT R7, R9.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff09077812 */
/* 0x040fe400078ec0ff */
/*0410*/ FSETP.NEU.FTZ.AND P0, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x000fe40003f1d000 */
/*0420*/ LOP3.LUT R8, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007087812 */
/* 0x000fe400078efcff */
/*0430*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*0440*/ LOP3.LUT R6, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080b067212 */
/* 0x000fe400078ec0ff */
/*0450*/ SHF.R.U32.HI R3, RZ, R3, R8 ; /* 0x00000003ff037219 */
/* 0x000fe20000011608 */
/*0460*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*0470*/ SHF.R.U32.HI R6, RZ, R5, R6 ; /* 0x00000005ff067219 */
/* 0x000fc80000011606 */
/*0480*/ LOP3.LUT P1, RZ, R7, R5, R8, 0xf8, !PT ; /* 0x0000000507ff7212 */
/* 0x000fe4000782f808 */
/*0490*/ LOP3.LUT P0, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */
/* 0x040fe4000780c0ff */
/*04a0*/ LOP3.LUT P2, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */
/* 0x000fc8000784c0ff */
/*04b0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*04c0*/ LOP3.LUT P1, RZ, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0aff7812 */
/* 0x000fe4000782c0ff */
/*04d0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*04e0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a05 */
/*04f0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f06270 */
/*0500*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */
/* 0x000fca0007ffe0ff */
/*0510*/ @!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203039824 */
/* 0x000fca00078e00ff */
/*0520*/ LOP3.LUT R3, R3, 0x80000000, R10, 0xf8, !PT ; /* 0x8000000003037812 */
/* 0x000fe200078ef80a */
/*0530*/ BRA 0x550 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0540*/ MUFU.RCP R3, c[0x0][0x168] ; /* 0x00005a0000037b08 */
/* 0x000e240000001000 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0560*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffa9004007950 */
/* 0x000fea0003c3ffff */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7initmemiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void initmem( int Ntot, float *a ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < Ntot ) a[idx] = 0;
}
__global__ void diff( int Nx, int Ny, float dx, float *a, float *da ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < (Nx-1)*(Ny-1) ) da[idx] = (1/dx)*( a[idx+Ny+1] - a[idx] );
} | .file "tmpxft_000a99b1_00000000-6_cudafunc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7initmemiPfiPf
.type _Z27__device_stub__Z7initmemiPfiPf, @function
_Z27__device_stub__Z7initmemiPfiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7initmemiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7initmemiPfiPf, .-_Z27__device_stub__Z7initmemiPfiPf
.globl _Z7initmemiPf
.type _Z7initmemiPf, @function
_Z7initmemiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7initmemiPfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7initmemiPf, .-_Z7initmemiPf
.globl _Z28__device_stub__Z4diffiifPfS_iifPfS_
.type _Z28__device_stub__Z4diffiifPfS_iifPfS_, @function
_Z28__device_stub__Z4diffiifPfS_iifPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4diffiifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z28__device_stub__Z4diffiifPfS_iifPfS_, .-_Z28__device_stub__Z4diffiifPfS_iifPfS_
.globl _Z4diffiifPfS_
.type _Z4diffiifPfS_, @function
_Z4diffiifPfS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4diffiifPfS_iifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z4diffiifPfS_, .-_Z4diffiifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4diffiifPfS_"
.LC1:
.string "_Z7initmemiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4diffiifPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7initmemiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void initmem( int Ntot, float *a ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < Ntot ) a[idx] = 0;
}
__global__ void diff( int Nx, int Ny, float dx, float *a, float *da ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < (Nx-1)*(Ny-1) ) da[idx] = (1/dx)*( a[idx+Ny+1] - a[idx] );
} | #include <hip/hip_runtime.h>
__global__ void initmem( int Ntot, float *a ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < Ntot ) a[idx] = 0;
}
__global__ void diff( int Nx, int Ny, float dx, float *a, float *da ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < (Nx-1)*(Ny-1) ) da[idx] = (1/dx)*( a[idx+Ny+1] - a[idx] );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void initmem( int Ntot, float *a ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < Ntot ) a[idx] = 0;
}
__global__ void diff( int Nx, int Ny, float dx, float *a, float *da ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < (Nx-1)*(Ny-1) ) da[idx] = (1/dx)*( a[idx+Ny+1] - a[idx] );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7initmemiPf
.globl _Z7initmemiPf
.p2align 8
.type _Z7initmemiPf,@function
_Z7initmemiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7initmemiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7initmemiPf, .Lfunc_end0-_Z7initmemiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4diffiifPfS_
.globl _Z4diffiifPfS_
.p2align 8
.type _Z4diffiifPfS_,@function
_Z4diffiifPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_add_i32 s2, s2, -1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_add_i32 s4, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_mul_i32 s4, s4, s2
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x10
v_add_nc_u32_e32 v3, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_div_scale_f32 v7, vcc_lo, 1.0, s0, 1.0
s_clause 0x1
global_load_b32 v2, v[2:3], off offset:4
global_load_b32 v3, v[4:5], off
v_div_scale_f32 v4, null, s0, s0, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f32 v4, v4, s0, 1.0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4diffiifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4diffiifPfS_, .Lfunc_end1-_Z4diffiifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7initmemiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7initmemiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4diffiifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4diffiifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void initmem( int Ntot, float *a ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < Ntot ) a[idx] = 0;
}
__global__ void diff( int Nx, int Ny, float dx, float *a, float *da ) {
int idx = blockIdx.x*blockDim.x + threadIdx.x;
if ( idx < (Nx-1)*(Ny-1) ) da[idx] = (1/dx)*( a[idx+Ny+1] - a[idx] );
} | .text
.file "cudafunc.hip"
.globl _Z22__device_stub__initmemiPf # -- Begin function _Z22__device_stub__initmemiPf
.p2align 4, 0x90
.type _Z22__device_stub__initmemiPf,@function
_Z22__device_stub__initmemiPf: # @_Z22__device_stub__initmemiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7initmemiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__initmemiPf, .Lfunc_end0-_Z22__device_stub__initmemiPf
.cfi_endproc
# -- End function
.globl _Z19__device_stub__diffiifPfS_ # -- Begin function _Z19__device_stub__diffiifPfS_
.p2align 4, 0x90
.type _Z19__device_stub__diffiifPfS_,@function
_Z19__device_stub__diffiifPfS_: # @_Z19__device_stub__diffiifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4diffiifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z19__device_stub__diffiifPfS_, .Lfunc_end1-_Z19__device_stub__diffiifPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7initmemiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4diffiifPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7initmemiPf,@object # @_Z7initmemiPf
.section .rodata,"a",@progbits
.globl _Z7initmemiPf
.p2align 3, 0x0
_Z7initmemiPf:
.quad _Z22__device_stub__initmemiPf
.size _Z7initmemiPf, 8
.type _Z4diffiifPfS_,@object # @_Z4diffiifPfS_
.globl _Z4diffiifPfS_
.p2align 3, 0x0
_Z4diffiifPfS_:
.quad _Z19__device_stub__diffiifPfS_
.size _Z4diffiifPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7initmemiPf"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4diffiifPfS_"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__initmemiPf
.addrsig_sym _Z19__device_stub__diffiifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7initmemiPf
.addrsig_sym _Z4diffiifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4diffiifPfS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ UMOV UR5, 0x1 ; /* 0x0000000100057882 */
/* 0x000fe40000000000 */
/*0030*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0050*/ UIADD3 UR4, -UR5, UR7, URZ ; /* 0x0000000705047290 */
/* 0x000fe4000fffe13f */
/*0060*/ UIADD3 UR5, -UR5, UR6, URZ ; /* 0x0000000605057290 */
/* 0x000fc8000fffe13f */
/*0070*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fe2000f8e023f */
/*0080*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0090*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R4, R0, c[0x0][0x164], RZ ; /* 0x0000590000047a10 */
/* 0x000fe20007ffe0ff */
/*00c0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe200078e00ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*00e0*/ IMAD.WIDE R4, R4, R7, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fc800078e0207 */
/*00f0*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fe400078e0207 */
/*0100*/ LDG.E R5, [R4.64+0x4] ; /* 0x0000040404057981 */
/* 0x000ea8000c1e1900 */
/*0110*/ LDG.E R2, [R6.64] ; /* 0x0000000406027981 */
/* 0x000ea2000c1e1900 */
/*0120*/ IMAD.MOV.U32 R8, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff087624 */
/* 0x000fca00078e00ff */
/*0130*/ IADD3 R3, R8, 0x1800000, RZ ; /* 0x0180000008037810 */
/* 0x000fc80007ffe0ff */
/*0140*/ LOP3.LUT R3, R3, 0x7f800000, RZ, 0xc0, !PT ; /* 0x7f80000003037812 */
/* 0x000fc800078ec0ff */
/*0150*/ ISETP.GT.U32.AND P0, PT, R3, 0x1ffffff, PT ; /* 0x01ffffff0300780c */
/* 0x000fe20003f04070 */
/*0160*/ FADD R2, -R2, R5 ; /* 0x0000000502027221 */
/* 0x004fd80000000100 */
/*0170*/ @P0 BRA 0x1b0 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0180*/ MOV R4, 0x1a0 ; /* 0x000001a000047802 */
/* 0x000fe40000000f00 */
/*0190*/ CALL.REL.NOINC 0x240 ; /* 0x000000a000007944 */
/* 0x000fea0003c00000 */
/*01a0*/ BRA 0x1f0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*01b0*/ MUFU.RCP R3, c[0x0][0x168] ; /* 0x00005a0000037b08 */
/* 0x000e240000001000 */
/*01c0*/ FFMA R4, R3, R8, -1 ; /* 0xbf80000003047423 */
/* 0x001fc80000000008 */
/*01d0*/ FADD.FTZ R4, -R4, -RZ ; /* 0x800000ff04047221 */
/* 0x000fc80000010100 */
/*01e0*/ FFMA R3, R3, R4, R3 ; /* 0x0000000403037223 */
/* 0x000fe40000000003 */
/*01f0*/ IMAD.MOV.U32 R7, RZ, RZ, 0x4 ; /* 0x00000004ff077424 */
/* 0x000fe400078e00ff */
/*0200*/ FMUL R5, R2, R3 ; /* 0x0000000302057220 */
/* 0x001fe40000400000 */
/*0210*/ IMAD.WIDE R2, R0, R7, c[0x0][0x178] ; /* 0x00005e0000027625 */
/* 0x000fca00078e0207 */
/*0220*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0230*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0240*/ IMAD.MOV.U32 R10, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff0a7624 */
/* 0x000fc800078e00ff */
/*0250*/ IMAD.SHL.U32 R5, R10, 0x2, RZ ; /* 0x000000020a057824 */
/* 0x000fca00078e00ff */
/*0260*/ SHF.R.U32.HI R3, RZ, 0x18, R5 ; /* 0x00000018ff037819 */
/* 0x000fc80000011605 */
/*0270*/ ISETP.NE.U32.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05070 */
/*0280*/ @P0 BRA 0x330 ; /* 0x000000a000000947 */
/* 0x000fea0003800000 */
/*0290*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*02a0*/ @!P0 MUFU.RCP R3, c[0x0][0x168] ; /* 0x00005a0000038b08 */
/* 0x000e220000001000 */
/*02b0*/ @!P0 BRA 0x550 ; /* 0x0000029000008947 */
/* 0x000fea0003800000 */
/*02c0*/ FFMA R5, R10, 1.84467440737095516160e+19, RZ ; /* 0x5f8000000a057823 */
/* 0x000fc800000000ff */
/*02d0*/ MUFU.RCP R6, R5 ; /* 0x0000000500067308 */
/* 0x000e640000001000 */
/*02e0*/ FFMA R3, R5, R6, -1 ; /* 0xbf80000005037423 */
/* 0x003fc80000000006 */
/*02f0*/ FADD.FTZ R3, -R3, -RZ ; /* 0x800000ff03037221 */
/* 0x000fc80000010100 */
/*0300*/ FFMA R3, R6, R3, R6 ; /* 0x0000000306037223 */
/* 0x000fc80000000006 */
/*0310*/ FFMA R3, R3, 1.84467440737095516160e+19, RZ ; /* 0x5f80000003037823 */
/* 0x000fe200000000ff */
/*0320*/ BRA 0x550 ; /* 0x0000022000007947 */
/* 0x000fea0003800000 */
/*0330*/ IADD3 R5, R3, -0xfd, RZ ; /* 0xffffff0303057810 */
/* 0x000fc80007ffe0ff */
/*0340*/ ISETP.GT.U32.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f04070 */
/*0350*/ @P0 BRA 0x540 ; /* 0x000001e000000947 */
/* 0x000fea0003800000 */
/*0360*/ LOP3.LUT R6, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0a067812 */
/* 0x000fe200078ec0ff */
/*0370*/ IMAD.MOV.U32 R12, RZ, RZ, 0x3 ; /* 0x00000003ff0c7424 */
/* 0x000fe200078e00ff */
/*0380*/ IADD3 R3, R3, -0xfc, RZ ; /* 0xffffff0403037810 */
/* 0x000fe40007ffe0ff */
/*0390*/ LOP3.LUT R6, R6, 0x3f800000, RZ, 0xfc, !PT ; /* 0x3f80000006067812 */
/* 0x000fe400078efcff */
/*03a0*/ SHF.L.U32 R11, R12, R5, RZ ; /* 0x000000050c0b7219 */
/* 0x000fe400000006ff */
/*03b0*/ MUFU.RCP R7, R6 ; /* 0x0000000600077308 */
/* 0x000e240000001000 */
/*03c0*/ FFMA R8, R6, R7, -1 ; /* 0xbf80000006087423 */
/* 0x001fc80000000007 */
/*03d0*/ FADD.FTZ R8, -R8, -RZ ; /* 0x800000ff08087221 */
/* 0x000fc80000010100 */
/*03e0*/ FFMA.RM R9, R7.reuse, R8.reuse, R7.reuse ; /* 0x0000000807097223 */
/* 0x1c0fe40000004007 */
/*03f0*/ FFMA.RP R8, R7, R8, R7 ; /* 0x0000000807087223 */
/* 0x000fc60000008007 */
/*0400*/ LOP3.LUT R7, R9.reuse, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff09077812 */
/* 0x040fe400078ec0ff */
/*0410*/ FSETP.NEU.FTZ.AND P0, PT, R9, R8, PT ; /* 0x000000080900720b */
/* 0x000fe40003f1d000 */
/*0420*/ LOP3.LUT R8, R7, 0x800000, RZ, 0xfc, !PT ; /* 0x0080000007087812 */
/* 0x000fe400078efcff */
/*0430*/ SEL R7, RZ, 0xffffffff, !P0 ; /* 0xffffffffff077807 */
/* 0x000fe40004000000 */
/*0440*/ LOP3.LUT R6, R11, R8, RZ, 0xc0, !PT ; /* 0x000000080b067212 */
/* 0x000fe400078ec0ff */
/*0450*/ SHF.R.U32.HI R3, RZ, R3, R8 ; /* 0x00000003ff037219 */
/* 0x000fe20000011608 */
/*0460*/ IMAD.MOV R7, RZ, RZ, -R7 ; /* 0x000000ffff077224 */
/* 0x000fe200078e0a07 */
/*0470*/ SHF.R.U32.HI R6, RZ, R5, R6 ; /* 0x00000005ff067219 */
/* 0x000fc80000011606 */
/*0480*/ LOP3.LUT P1, RZ, R7, R5, R8, 0xf8, !PT ; /* 0x0000000507ff7212 */
/* 0x000fe4000782f808 */
/*0490*/ LOP3.LUT P0, RZ, R6.reuse, 0x1, RZ, 0xc0, !PT ; /* 0x0000000106ff7812 */
/* 0x040fe4000780c0ff */
/*04a0*/ LOP3.LUT P2, RZ, R6, 0x2, RZ, 0xc0, !PT ; /* 0x0000000206ff7812 */
/* 0x000fc8000784c0ff */
/*04b0*/ PLOP3.LUT P0, PT, P0, P1, P2, 0xe0, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40000703c20 */
/*04c0*/ LOP3.LUT P1, RZ, R10, 0x7fffff, RZ, 0xc0, !PT ; /* 0x007fffff0aff7812 */
/* 0x000fe4000782c0ff */
/*04d0*/ SEL R5, RZ, 0x1, !P0 ; /* 0x00000001ff057807 */
/* 0x000fca0004000000 */
/*04e0*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0a05 */
/*04f0*/ ISETP.GE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f06270 */
/*0500*/ @!P0 IADD3 R3, R3, 0x1, RZ ; /* 0x0000000103038810 */
/* 0x000fca0007ffe0ff */
/*0510*/ @!P1 IMAD.SHL.U32 R3, R3, 0x2, RZ ; /* 0x0000000203039824 */
/* 0x000fca00078e00ff */
/*0520*/ LOP3.LUT R3, R3, 0x80000000, R10, 0xf8, !PT ; /* 0x8000000003037812 */
/* 0x000fe200078ef80a */
/*0530*/ BRA 0x550 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0540*/ MUFU.RCP R3, c[0x0][0x168] ; /* 0x00005a0000037b08 */
/* 0x000e240000001000 */
/*0550*/ IMAD.MOV.U32 R5, RZ, RZ, 0x0 ; /* 0x00000000ff057424 */
/* 0x000fc800078e00ff */
/*0560*/ RET.REL.NODEC R4 0x0 ; /* 0xfffffa9004007950 */
/* 0x000fea0003c3ffff */
/*0570*/ BRA 0x570; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0580*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0590*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*05f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z7initmemiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_CTAID.X ; /* 0x0000000000027919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R2, R2, c[0x0][0x0], R3 ; /* 0x0000000002027a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x160], PT ; /* 0x0000580002007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R2, R3, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fca00078e0203 */
/*0090*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7initmemiPf
.globl _Z7initmemiPf
.p2align 8
.type _Z7initmemiPf,@function
_Z7initmemiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x1c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_mov_b32_e32 v2, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7initmemiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7initmemiPf, .Lfunc_end0-_Z7initmemiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4diffiifPfS_
.globl _Z4diffiifPfS_
.p2align 8
.type _Z4diffiifPfS_,@function
_Z4diffiifPfS_:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_add_i32 s2, s2, -1
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_add_i32 s4, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
s_mul_i32 s4, s4, s2
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[4:7], s[0:1], 0x10
v_add_nc_u32_e32 v3, s3, v1
v_ashrrev_i32_e32 v2, 31, v1
s_load_b32 s0, s[0:1], 0x8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[3:4]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v4, vcc_lo
v_add_co_u32 v4, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
v_div_scale_f32 v7, vcc_lo, 1.0, s0, 1.0
s_clause 0x1
global_load_b32 v2, v[2:3], off offset:4
global_load_b32 v3, v[4:5], off
v_div_scale_f32 v4, null, s0, s0, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v5, v4
s_waitcnt_depctr 0xfff
v_fma_f32 v6, -v4, v5, 1.0
v_fmac_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v6, v7, v5
v_fma_f32 v8, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v6, v8, v5
v_fma_f32 v4, -v4, v6, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v4, v4, v5, v6
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f32 v4, v4, s0, 1.0
s_waitcnt vmcnt(0)
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1)
v_mul_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4diffiifPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4diffiifPfS_, .Lfunc_end1-_Z4diffiifPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7initmemiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z7initmemiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4diffiifPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4diffiifPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000a99b1_00000000-6_cudafunc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z7initmemiPfiPf
.type _Z27__device_stub__Z7initmemiPfiPf, @function
_Z27__device_stub__Z7initmemiPfiPf:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7initmemiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z7initmemiPfiPf, .-_Z27__device_stub__Z7initmemiPfiPf
.globl _Z7initmemiPf
.type _Z7initmemiPf, @function
_Z7initmemiPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z7initmemiPfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7initmemiPf, .-_Z7initmemiPf
.globl _Z28__device_stub__Z4diffiifPfS_iifPfS_
.type _Z28__device_stub__Z4diffiifPfS_iifPfS_, @function
_Z28__device_stub__Z4diffiifPfS_iifPfS_:
.LFB2053:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movl %edi, 28(%rsp)
movl %esi, 24(%rsp)
movss %xmm0, 20(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 28(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 20(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4diffiifPfS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2053:
.size _Z28__device_stub__Z4diffiifPfS_iifPfS_, .-_Z28__device_stub__Z4diffiifPfS_iifPfS_
.globl _Z4diffiifPfS_
.type _Z4diffiifPfS_, @function
_Z4diffiifPfS_:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z28__device_stub__Z4diffiifPfS_iifPfS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _Z4diffiifPfS_, .-_Z4diffiifPfS_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z4diffiifPfS_"
.LC1:
.string "_Z7initmemiPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z4diffiifPfS_(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z7initmemiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2056:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cudafunc.hip"
.globl _Z22__device_stub__initmemiPf # -- Begin function _Z22__device_stub__initmemiPf
.p2align 4, 0x90
.type _Z22__device_stub__initmemiPf,@function
_Z22__device_stub__initmemiPf: # @_Z22__device_stub__initmemiPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movq %rsi, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
leaq 56(%rsp), %rax
movq %rax, 72(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7initmemiPf, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__initmemiPf, .Lfunc_end0-_Z22__device_stub__initmemiPf
.cfi_endproc
# -- End function
.globl _Z19__device_stub__diffiifPfS_ # -- Begin function _Z19__device_stub__diffiifPfS_
.p2align 4, 0x90
.type _Z19__device_stub__diffiifPfS_,@function
_Z19__device_stub__diffiifPfS_: # @_Z19__device_stub__diffiifPfS_
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %rdx, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 64(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4diffiifPfS_, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z19__device_stub__diffiifPfS_, .Lfunc_end1-_Z19__device_stub__diffiifPfS_
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7initmemiPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4diffiifPfS_, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7initmemiPf,@object # @_Z7initmemiPf
.section .rodata,"a",@progbits
.globl _Z7initmemiPf
.p2align 3, 0x0
_Z7initmemiPf:
.quad _Z22__device_stub__initmemiPf
.size _Z7initmemiPf, 8
.type _Z4diffiifPfS_,@object # @_Z4diffiifPfS_
.globl _Z4diffiifPfS_
.p2align 3, 0x0
_Z4diffiifPfS_:
.quad _Z19__device_stub__diffiifPfS_
.size _Z4diffiifPfS_, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7initmemiPf"
.size .L__unnamed_1, 14
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z4diffiifPfS_"
.size .L__unnamed_2, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__initmemiPf
.addrsig_sym _Z19__device_stub__diffiifPfS_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7initmemiPf
.addrsig_sym _Z4diffiifPfS_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void helloWorld() {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
printf("Hello World! My ThreadId is %2d\n", i);
}
int main() {
helloWorld<<<1, 256>>>();
cudaDeviceSynchronize();
return 0;
} | code for sm_80
Function : _Z10helloWorldv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R2, 0x0 ; /* 0x0000000000027802 */
/* 0x000fe20000000f00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0040*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe20007ffe0ff */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe400078e00ff */
/*0070*/ IADD3 R6, P0, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fca0007f1e0ff */
/*0080*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P0 ; /* 0x00000900ff077624 */
/* 0x000fe400000e06ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*00a0*/ LDC.64 R2, c[0x4][R2] ; /* 0x0100000002027b82 */
/* 0x000e260000000a00 */
/*00b0*/ STL [R1], R0 ; /* 0x0000000001007387 */
/* 0x0003e40000100800 */
/*00c0*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*00d0*/ MOV R11, 0x140 ; /* 0x00000140000b7802 */
/* 0x000fe40000000f00 */
/*00e0*/ MOV R20, 0xc0 ; /* 0x000000c000147802 */
/* 0x000fe40000000f00 */
/*00f0*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*0100*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x002fe40000000f00 */
/*0110*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*0120*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*0130*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x001fea0003c00000 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void helloWorld() {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
printf("Hello World! My ThreadId is %2d\n", i);
}
int main() {
helloWorld<<<1, 256>>>();
cudaDeviceSynchronize();
return 0;
} | .file "tmpxft_000ce53e_00000000-6_exercise_1_joel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10helloWorldvv
.type _Z29__device_stub__Z10helloWorldvv, @function
_Z29__device_stub__Z10helloWorldvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10helloWorldv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10helloWorldvv, .-_Z29__device_stub__Z10helloWorldvv
.globl _Z10helloWorldv
.type _Z10helloWorldv, @function
_Z10helloWorldv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10helloWorldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10helloWorldv, .-_Z10helloWorldv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10helloWorldvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10helloWorldv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10helloWorldv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void helloWorld() {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
printf("Hello World! My ThreadId is %2d\n", i);
}
int main() {
helloWorld<<<1, 256>>>();
cudaDeviceSynchronize();
return 0;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void helloWorld() {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
printf("Hello World! My ThreadId is %2d\n", i);
}
int main() {
helloWorld<<<1, 256>>>();
hipDeviceSynchronize();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void helloWorld() {
const int i = blockIdx.x * blockDim.x + threadIdx.x;
printf("Hello World! My ThreadId is %2d\n", i);
}
int main() {
helloWorld<<<1, 256>>>();
hipDeviceSynchronize();
return 0;
} | .text
.file "exercise_1_joel.hip"
.globl _Z25__device_stub__helloWorldv # -- Begin function _Z25__device_stub__helloWorldv
.p2align 4, 0x90
.type _Z25__device_stub__helloWorldv,@function
_Z25__device_stub__helloWorldv: # @_Z25__device_stub__helloWorldv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloWorldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__helloWorldv, .Lfunc_end0-_Z25__device_stub__helloWorldv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloWorldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10helloWorldv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10helloWorldv,@object # @_Z10helloWorldv
.section .rodata,"a",@progbits
.globl _Z10helloWorldv
.p2align 3, 0x0
_Z10helloWorldv:
.quad _Z25__device_stub__helloWorldv
.size _Z10helloWorldv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10helloWorldv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__helloWorldv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10helloWorldv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ce53e_00000000-6_exercise_1_joel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z29__device_stub__Z10helloWorldvv
.type _Z29__device_stub__Z10helloWorldvv, @function
_Z29__device_stub__Z10helloWorldvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z10helloWorldv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z29__device_stub__Z10helloWorldvv, .-_Z29__device_stub__Z10helloWorldvv
.globl _Z10helloWorldv
.type _Z10helloWorldv, @function
_Z10helloWorldv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z10helloWorldvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z10helloWorldv, .-_Z10helloWorldv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $256, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z29__device_stub__Z10helloWorldvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z10helloWorldv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z10helloWorldv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "exercise_1_joel.hip"
.globl _Z25__device_stub__helloWorldv # -- Begin function _Z25__device_stub__helloWorldv
.p2align 4, 0x90
.type _Z25__device_stub__helloWorldv,@function
_Z25__device_stub__helloWorldv: # @_Z25__device_stub__helloWorldv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloWorldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z25__device_stub__helloWorldv, .Lfunc_end0-_Z25__device_stub__helloWorldv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 255(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z10helloWorldv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10helloWorldv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z10helloWorldv,@object # @_Z10helloWorldv
.section .rodata,"a",@progbits
.globl _Z10helloWorldv
.p2align 3, 0x0
_Z10helloWorldv:
.quad _Z25__device_stub__helloWorldv
.size _Z10helloWorldv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z10helloWorldv"
.size .L__unnamed_1, 16
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z25__device_stub__helloWorldv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z10helloWorldv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //=====================================================================
// MAIN FUNCTION
//=====================================================================
__device__ void kernel_ecc(float timeinst, float* d_initvalu, float *d_finavalu, int valu_offset,
float* d_params) {
//=====================================================================
// VARIABLES
//=====================================================================
// input parameters
float cycleLength;
// variable references // GET VARIABLES FROM MEMORY AND SAVE LOCALLY !!!!!!!!!!!!!!!!!!
int offset_1;
int offset_2;
int offset_3;
int offset_4;
int offset_5;
int offset_6;
int offset_7;
int offset_8;
int offset_9;
int offset_10;
int offset_11;
int offset_12;
int offset_13;
int offset_14;
int offset_15;
int offset_16;
int offset_17;
int offset_18;
int offset_19;
int offset_20;
int offset_21;
int offset_22;
int offset_23;
int offset_24;
int offset_25;
int offset_26;
int offset_27;
int offset_28;
int offset_29;
int offset_30;
int offset_31;
int offset_32;
int offset_33;
int offset_34;
int offset_35;
int offset_36;
int offset_37;
int offset_38;
int offset_39;
int offset_40;
int offset_41;
int offset_42;
int offset_43;
int offset_44;
int offset_45;
int offset_46;
// stored input array
float d_initvalu_1;
float d_initvalu_2;
float d_initvalu_3;
float d_initvalu_4;
float d_initvalu_5;
float d_initvalu_6;
float d_initvalu_7;
float d_initvalu_8;
float d_initvalu_9;
float d_initvalu_10;
float d_initvalu_11;
float d_initvalu_12;
float d_initvalu_13;
float d_initvalu_14;
float d_initvalu_15;
float d_initvalu_16;
float d_initvalu_17;
float d_initvalu_18;
float d_initvalu_19;
float d_initvalu_20;
float d_initvalu_21;
// float d_initvalu_22;
float d_initvalu_23;
float d_initvalu_24;
float d_initvalu_25;
float d_initvalu_26;
float d_initvalu_27;
float d_initvalu_28;
float d_initvalu_29;
float d_initvalu_30;
float d_initvalu_31;
float d_initvalu_32;
float d_initvalu_33;
float d_initvalu_34;
float d_initvalu_35;
float d_initvalu_36;
float d_initvalu_37;
float d_initvalu_38;
float d_initvalu_39;
float d_initvalu_40;
// float d_initvalu_41;
// float d_initvalu_42;
// float d_initvalu_43;
// float d_initvalu_44;
// float d_initvalu_45;
// float d_initvalu_46;
// matlab constants undefined in c
float pi;
// Constants
float R; // [J/kmol*K]
float Frdy; // [C/mol]
float Temp; // [K] 310
float FoRT; //
float Cmem; // [F] membrane capacitance
float Qpow;
// Cell geometry
float cellLength; // cell length [um]
float cellRadius; // cell radius [um]
// float junctionLength; // junc length [um]
// float junctionRadius; // junc radius [um]
// float distSLcyto; // dist. SL to cytosol [um]
// float distJuncSL; // dist. junc to SL [um]
// float DcaJuncSL; // Dca junc to SL [cm^2/sec]
// float DcaSLcyto; // Dca SL to cyto [cm^2/sec]
// float DnaJuncSL; // Dna junc to SL [cm^2/sec]
// float DnaSLcyto; // Dna SL to cyto [cm^2/sec]
float Vcell; // [L]
float Vmyo;
float Vsr;
float Vsl;
float Vjunc;
// float SAjunc; // [um^2]
// float SAsl; // [um^2]
float J_ca_juncsl; // [L/msec]
float J_ca_slmyo; // [L/msec]
float J_na_juncsl; // [L/msec]
float J_na_slmyo; // [L/msec]
// Fractional currents in compartments
float Fjunc;
float Fsl;
float Fjunc_CaL;
float Fsl_CaL;
// Fixed ion concentrations
float Cli; // Intracellular Cl [mM]
float Clo; // Extracellular Cl [mM]
float Ko; // Extracellular K [mM]
float Nao; // Extracellular Na [mM]
float Cao; // Extracellular Ca [mM]
float Mgi; // Intracellular Mg [mM]
// Nernst Potentials
float ena_junc; // [mV]
float ena_sl; // [mV]
float ek; // [mV]
float eca_junc; // [mV]
float eca_sl; // [mV]
float ecl; // [mV]
// Na transport parameters
float GNa; // [mS/uF]
float GNaB; // [mS/uF]
float IbarNaK; // [uA/uF]
float KmNaip; // [mM]
float KmKo; // [mM]
// float Q10NaK;
// float Q10KmNai;
// K current parameters
float pNaK;
float GtoSlow; // [mS/uF]
float GtoFast; // [mS/uF]
float gkp;
// Cl current parameters
float GClCa; // [mS/uF]
float GClB; // [mS/uF]
float KdClCa; // [mM] // [mM]
// I_Ca parameters
float pNa; // [cm/sec]
float pCa; // [cm/sec]
float pK; // [cm/sec]
// float KmCa; // [mM]
float Q10CaL;
// Ca transport parameters
float IbarNCX; // [uA/uF]
float KmCai; // [mM]
float KmCao; // [mM]
float KmNai; // [mM]
float KmNao; // [mM]
float ksat; // [none]
float nu; // [none]
float Kdact; // [mM]
float Q10NCX; // [none]
float IbarSLCaP; // [uA/uF]
float KmPCa; // [mM]
float GCaB; // [uA/uF]
float Q10SLCaP; // [none] // [none]
// SR flux parameters
float Q10SRCaP; // [none]
float Vmax_SRCaP; // [mM/msec] (mmol/L cytosol/msec)
float Kmf; // [mM]
float Kmr; // [mM]L cytosol
float hillSRCaP; // [mM]
float ks; // [1/ms]
float koCa; // [mM^-2 1/ms]
float kom; // [1/ms]
float kiCa; // [1/mM/ms]
float kim; // [1/ms]
float ec50SR; // [mM]
// Buffering parameters
float Bmax_Naj; // [mM]
float Bmax_Nasl; // [mM]
float koff_na; // [1/ms]
float kon_na; // [1/mM/ms]
float Bmax_TnClow; // [mM], TnC low affinity
float koff_tncl; // [1/ms]
float kon_tncl; // [1/mM/ms]
float Bmax_TnChigh; // [mM], TnC high affinity
float koff_tnchca; // [1/ms]
float kon_tnchca; // [1/mM/ms]
float koff_tnchmg; // [1/ms]
float kon_tnchmg; // [1/mM/ms]
// float Bmax_CaM; // [mM], CaM buffering
// float koff_cam; // [1/ms]
// float kon_cam; // [1/mM/ms]
float Bmax_myosin; // [mM], Myosin buffering
float koff_myoca; // [1/ms]
float kon_myoca; // [1/mM/ms]
float koff_myomg; // [1/ms]
float kon_myomg; // [1/mM/ms]
float Bmax_SR; // [mM]
float koff_sr; // [1/ms]
float kon_sr; // [1/mM/ms]
float Bmax_SLlowsl; // [mM], SL buffering
float Bmax_SLlowj; // [mM]
float koff_sll; // [1/ms]
float kon_sll; // [1/mM/ms]
float Bmax_SLhighsl; // [mM]
float Bmax_SLhighj; // [mM]
float koff_slh; // [1/ms]
float kon_slh; // [1/mM/ms]
float Bmax_Csqn; // 140e-3*Vmyo/Vsr; [mM]
float koff_csqn; // [1/ms]
float kon_csqn; // [1/mM/ms]
// I_Na: Fast Na Current
float am;
float bm;
float ah;
float bh;
float aj;
float bj;
float I_Na_junc;
float I_Na_sl;
// float I_Na;
// I_nabk: Na Background Current
float I_nabk_junc;
float I_nabk_sl;
// float I_nabk;
// I_nak: Na/K Pump Current
float sigma;
float fnak;
float I_nak_junc;
float I_nak_sl;
float I_nak;
// I_kr: Rapidly Activating K Current
float gkr;
float xrss;
float tauxr;
float rkr;
float I_kr;
// I_ks: Slowly Activating K Current
float pcaks_junc;
float pcaks_sl;
float gks_junc;
float gks_sl;
float eks;
float xsss;
float tauxs;
float I_ks_junc;
float I_ks_sl;
float I_ks;
// I_kp: Plateau K current
float kp_kp;
float I_kp_junc;
float I_kp_sl;
float I_kp;
// I_to: Transient Outward K Current (slow and fast components)
float xtoss;
float ytoss;
float rtoss;
float tauxtos;
float tauytos;
float taurtos;
float I_tos;
//
float tauxtof;
float tauytof;
float I_tof;
float I_to;
// I_ki: Time-Independent K Current
float aki;
float bki;
float kiss;
float I_ki;
// I_ClCa: Ca-activated Cl Current, I_Clbk: background Cl Current
float I_ClCa_junc;
float I_ClCa_sl;
float I_ClCa;
float I_Clbk;
// I_Ca: L-type Calcium Current
float dss;
float taud;
float fss;
float tauf;
//
float ibarca_j;
float ibarca_sl;
float ibark;
float ibarna_j;
float ibarna_sl;
float I_Ca_junc;
float I_Ca_sl;
float I_Ca;
float I_CaK;
float I_CaNa_junc;
float I_CaNa_sl;
// float I_CaNa;
// float I_Catot;
// I_ncx: Na/Ca Exchanger flux
float Ka_junc;
float Ka_sl;
float s1_junc;
float s1_sl;
float s2_junc;
float s3_junc;
float s2_sl;
float s3_sl;
float I_ncx_junc;
float I_ncx_sl;
float I_ncx;
// I_pca: Sarcolemmal Ca Pump Current
float I_pca_junc;
float I_pca_sl;
float I_pca;
// I_cabk: Ca Background Current
float I_cabk_junc;
float I_cabk_sl;
float I_cabk;
// SR fluxes: Calcium Release, SR Ca pump, SR Ca leak
float MaxSR;
float MinSR;
float kCaSR;
float koSRCa;
float kiSRCa;
float RI;
float J_SRCarel; // [mM/ms]
float J_serca;
float J_SRleak; // [mM/ms]
// Cytosolic Ca Buffers
float J_CaB_cytosol;
// Junctional and SL Ca Buffers
float J_CaB_junction;
float J_CaB_sl;
// SR Ca Concentrations
float oneovervsr;
// Sodium Concentrations
float I_Na_tot_junc; // [uA/uF]
float I_Na_tot_sl; // [uA/uF]
float oneovervsl;
// Potassium Concentration
float I_K_tot;
// Calcium Concentrations
float I_Ca_tot_junc; // [uA/uF]
float I_Ca_tot_sl; // [uA/uF]
// float junc_sl;
// float sl_junc;
// float sl_myo;
// float myo_sl;
// Simulation type
int state; // 0-none; 1-pace; 2-vclamp
float I_app;
float V_hold;
float V_test;
float V_clamp;
float R_clamp;
// Membrane Potential
float I_Na_tot; // [uA/uF]
float I_Cl_tot; // [uA/uF]
float I_Ca_tot;
float I_tot;
//=====================================================================
// EXECUTION
//=====================================================================
// input parameters
cycleLength = d_params[15];
// variable references
offset_1 = valu_offset;
offset_2 = valu_offset + 1;
offset_3 = valu_offset + 2;
offset_4 = valu_offset + 3;
offset_5 = valu_offset + 4;
offset_6 = valu_offset + 5;
offset_7 = valu_offset + 6;
offset_8 = valu_offset + 7;
offset_9 = valu_offset + 8;
offset_10 = valu_offset + 9;
offset_11 = valu_offset + 10;
offset_12 = valu_offset + 11;
offset_13 = valu_offset + 12;
offset_14 = valu_offset + 13;
offset_15 = valu_offset + 14;
offset_16 = valu_offset + 15;
offset_17 = valu_offset + 16;
offset_18 = valu_offset + 17;
offset_19 = valu_offset + 18;
offset_20 = valu_offset + 19;
offset_21 = valu_offset + 20;
offset_22 = valu_offset + 21;
offset_23 = valu_offset + 22;
offset_24 = valu_offset + 23;
offset_25 = valu_offset + 24;
offset_26 = valu_offset + 25;
offset_27 = valu_offset + 26;
offset_28 = valu_offset + 27;
offset_29 = valu_offset + 28;
offset_30 = valu_offset + 29;
offset_31 = valu_offset + 30;
offset_32 = valu_offset + 31;
offset_33 = valu_offset + 32;
offset_34 = valu_offset + 33;
offset_35 = valu_offset + 34;
offset_36 = valu_offset + 35;
offset_37 = valu_offset + 36;
offset_38 = valu_offset + 37;
offset_39 = valu_offset + 38;
offset_40 = valu_offset + 39;
offset_41 = valu_offset + 40;
offset_42 = valu_offset + 41;
offset_43 = valu_offset + 42;
offset_44 = valu_offset + 43;
offset_45 = valu_offset + 44;
offset_46 = valu_offset + 45;
// stored input array
d_initvalu_1 = d_initvalu[offset_1];
d_initvalu_2 = d_initvalu[offset_2];
d_initvalu_3 = d_initvalu[offset_3];
d_initvalu_4 = d_initvalu[offset_4];
d_initvalu_5 = d_initvalu[offset_5];
d_initvalu_6 = d_initvalu[offset_6];
d_initvalu_7 = d_initvalu[offset_7];
d_initvalu_8 = d_initvalu[offset_8];
d_initvalu_9 = d_initvalu[offset_9];
d_initvalu_10 = d_initvalu[offset_10];
d_initvalu_11 = d_initvalu[offset_11];
d_initvalu_12 = d_initvalu[offset_12];
d_initvalu_13 = d_initvalu[offset_13];
d_initvalu_14 = d_initvalu[offset_14];
d_initvalu_15 = d_initvalu[offset_15];
d_initvalu_16 = d_initvalu[offset_16];
d_initvalu_17 = d_initvalu[offset_17];
d_initvalu_18 = d_initvalu[offset_18];
d_initvalu_19 = d_initvalu[offset_19];
d_initvalu_20 = d_initvalu[offset_20];
d_initvalu_21 = d_initvalu[offset_21];
// d_initvalu_22 = d_initvalu[offset_22];
d_initvalu_23 = d_initvalu[offset_23];
d_initvalu_24 = d_initvalu[offset_24];
d_initvalu_25 = d_initvalu[offset_25];
d_initvalu_26 = d_initvalu[offset_26];
d_initvalu_27 = d_initvalu[offset_27];
d_initvalu_28 = d_initvalu[offset_28];
d_initvalu_29 = d_initvalu[offset_29];
d_initvalu_30 = d_initvalu[offset_30];
d_initvalu_31 = d_initvalu[offset_31];
d_initvalu_32 = d_initvalu[offset_32];
d_initvalu_33 = d_initvalu[offset_33];
d_initvalu_34 = d_initvalu[offset_34];
d_initvalu_35 = d_initvalu[offset_35];
d_initvalu_36 = d_initvalu[offset_36];
d_initvalu_37 = d_initvalu[offset_37];
d_initvalu_38 = d_initvalu[offset_38];
d_initvalu_39 = d_initvalu[offset_39];
d_initvalu_40 = d_initvalu[offset_40];
// d_initvalu_41 = d_initvalu[offset_41];
// d_initvalu_42 = d_initvalu[offset_42];
// d_initvalu_43 = d_initvalu[offset_43];
// d_initvalu_44 = d_initvalu[offset_44];
// d_initvalu_45 = d_initvalu[offset_45];
// d_initvalu_46 = d_initvalu[offset_46];
// matlab constants undefined in c
pi = 3.1416;
// Constants
R = 8314; // [J/kmol*K]
Frdy = 96485; // [C/mol]
Temp = 310; // [K] 310
FoRT = Frdy / R / Temp; //
Cmem = 1.3810e-10; // [F] membrane capacitance
Qpow = (Temp - 310) / 10;
// Cell geometry
cellLength = 100; // cell length [um]
cellRadius = 10.25; // cell radius [um]
// junctionLength = 160e-3; // junc length [um]
// junctionRadius = 15e-3; // junc radius [um]
// distSLcyto = 0.45; // dist. SL to cytosol [um]
// distJuncSL = 0.5; // dist. junc to SL [um]
// DcaJuncSL = 1.64e-6; // Dca junc to SL [cm^2/sec]
// DcaSLcyto = 1.22e-6; // Dca SL to cyto [cm^2/sec]
// DnaJuncSL = 1.09e-5; // Dna junc to SL [cm^2/sec]
// DnaSLcyto = 1.79e-5; // Dna SL to cyto [cm^2/sec]
Vcell = pi * pow(cellRadius, 2) * cellLength * 1e-15; // [L]
Vmyo = 0.65 * Vcell;
Vsr = 0.035 * Vcell;
Vsl = 0.02 * Vcell;
Vjunc = 0.0539 * 0.01 * Vcell;
// SAjunc = 20150*pi*2*junctionLength*junctionRadius; // [um^2]
// SAsl = pi*2*cellRadius*cellLength; // [um^2]
J_ca_juncsl = 1 / 1.2134e12; // [L/msec]
J_ca_slmyo = 1 / 2.68510e11; // [L/msec]
J_na_juncsl = 1 / (1.6382e12 / 3 * 100); // [L/msec]
J_na_slmyo = 1 / (1.8308e10 / 3 * 100); // [L/msec]
// Fractional currents in compartments
Fjunc = 0.11;
Fsl = 1 - Fjunc;
Fjunc_CaL = 0.9;
Fsl_CaL = 1 - Fjunc_CaL;
// Fixed ion concentrations
Cli = 15; // Intracellular Cl [mM]
Clo = 150; // Extracellular Cl [mM]
Ko = 5.4; // Extracellular K [mM]
Nao = 140; // Extracellular Na [mM]
Cao = 1.8; // Extracellular Ca [mM]
Mgi = 1; // Intracellular Mg [mM]
// Nernst Potentials
ena_junc = (1 / FoRT) * log(Nao / d_initvalu_32); // [mV]
ena_sl = (1 / FoRT) * log(Nao / d_initvalu_33); // [mV]
ek = (1 / FoRT) * log(Ko / d_initvalu_35); // [mV]
eca_junc = (1 / FoRT / 2) * log(Cao / d_initvalu_36); // [mV]
eca_sl = (1 / FoRT / 2) * log(Cao / d_initvalu_37); // [mV]
ecl = (1 / FoRT) * log(Cli / Clo); // [mV]
// Na transport parameters
GNa = 16.0; // [mS/uF]
GNaB = 0.297e-3; // [mS/uF]
IbarNaK = 1.90719; // [uA/uF]
KmNaip = 11; // [mM]
KmKo = 1.5; // [mM]
// Q10NaK = 1.63;
// Q10KmNai = 1.39;
// K current parameters
pNaK = 0.01833;
GtoSlow = 0.06; // [mS/uF]
GtoFast = 0.02; // [mS/uF]
gkp = 0.001;
// Cl current parameters
GClCa = 0.109625; // [mS/uF]
GClB = 9e-3; // [mS/uF]
KdClCa = 100e-3; // [mM]
// I_Ca parameters
pNa = 1.5e-8; // [cm/sec]
pCa = 5.4e-4; // [cm/sec]
pK = 2.7e-7; // [cm/sec]
// KmCa = 0.6e-3; // [mM]
Q10CaL = 1.8;
// Ca transport parameters
IbarNCX = 9.0; // [uA/uF]
KmCai = 3.59e-3; // [mM]
KmCao = 1.3; // [mM]
KmNai = 12.29; // [mM]
KmNao = 87.5; // [mM]
ksat = 0.27; // [none]
nu = 0.35; // [none]
Kdact = 0.256e-3; // [mM]
Q10NCX = 1.57; // [none]
IbarSLCaP = 0.0673; // [uA/uF]
KmPCa = 0.5e-3; // [mM]
GCaB = 2.513e-4; // [uA/uF]
Q10SLCaP = 2.35; // [none]
// SR flux parameters
Q10SRCaP = 2.6; // [none]
Vmax_SRCaP = 2.86e-4; // [mM/msec] (mmol/L cytosol/msec)
Kmf = 0.246e-3; // [mM]
Kmr = 1.7; // [mM]L cytosol
hillSRCaP = 1.787; // [mM]
ks = 25; // [1/ms]
koCa = 10; // [mM^-2 1/ms]
kom = 0.06; // [1/ms]
kiCa = 0.5; // [1/mM/ms]
kim = 0.005; // [1/ms]
ec50SR = 0.45; // [mM]
// Buffering parameters
Bmax_Naj = 7.561; // [mM]
Bmax_Nasl = 1.65; // [mM]
koff_na = 1e-3; // [1/ms]
kon_na = 0.1e-3; // [1/mM/ms]
Bmax_TnClow = 70e-3; // [mM], TnC low affinity
koff_tncl = 19.6e-3; // [1/ms]
kon_tncl = 32.7; // [1/mM/ms]
Bmax_TnChigh = 140e-3; // [mM], TnC high affinity
koff_tnchca = 0.032e-3; // [1/ms]
kon_tnchca = 2.37; // [1/mM/ms]
koff_tnchmg = 3.33e-3; // [1/ms]
kon_tnchmg = 3e-3; // [1/mM/ms]
// Bmax_CaM = 24e-3; // [mM], CaM buffering
// koff_cam = 238e-3; // [1/ms]
// kon_cam = 34; // [1/mM/ms]
Bmax_myosin = 140e-3; // [mM], Myosin buffering
koff_myoca = 0.46e-3; // [1/ms]
kon_myoca = 13.8; // [1/mM/ms]
koff_myomg = 0.057e-3; // [1/ms]
kon_myomg = 0.0157; // [1/mM/ms]
Bmax_SR = 19 * 0.9e-3; // [mM]
koff_sr = 60e-3; // [1/ms]
kon_sr = 100; // [1/mM/ms]
Bmax_SLlowsl = 37.38e-3 * Vmyo / Vsl; // [mM], SL buffering
Bmax_SLlowj = 4.62e-3 * Vmyo / Vjunc * 0.1; // [mM]
koff_sll = 1300e-3; // [1/ms]
kon_sll = 100; // [1/mM/ms]
Bmax_SLhighsl = 13.35e-3 * Vmyo / Vsl; // [mM]
Bmax_SLhighj = 1.65e-3 * Vmyo / Vjunc * 0.1; // [mM]
koff_slh = 30e-3; // [1/ms]
kon_slh = 100; // [1/mM/ms]
Bmax_Csqn = 2.7; // 140e-3*Vmyo/Vsr; [mM]
koff_csqn = 65; // [1/ms]
kon_csqn = 100; // [1/mM/ms]
// I_Na: Fast Na Current
am = 0.32 * (d_initvalu_39 + 47.13) / (1 - exp(-0.1 * (d_initvalu_39 + 47.13)));
bm = 0.08 * exp(-d_initvalu_39 / 11);
if (d_initvalu_39 >= -40) {
ah = 0;
aj = 0;
bh = 1 / (0.13 * (1 + exp(-(d_initvalu_39 + 10.66) / 11.1)));
bj = 0.3 * exp(-2.535e-7 * d_initvalu_39) / (1 + exp(-0.1 * (d_initvalu_39 + 32)));
} else {
ah = 0.135 * exp((80 + d_initvalu_39) / -6.8);
bh = 3.56 * exp(0.079 * d_initvalu_39) + 3.1e5 * exp(0.35 * d_initvalu_39);
aj = (-127140 * exp(0.2444 * d_initvalu_39) - 3.474e-5 * exp(-0.04391 * d_initvalu_39))
* (d_initvalu_39 + 37.78) / (1 + exp(0.311 * (d_initvalu_39 + 79.23)));
bj = 0.1212 * exp(-0.01052 * d_initvalu_39) / (1 + exp(-0.1378 * (d_initvalu_39 + 40.14)));
}
d_finavalu[offset_1] = am * (1 - d_initvalu_1) - bm * d_initvalu_1;
d_finavalu[offset_2] = ah * (1 - d_initvalu_2) - bh * d_initvalu_2;
d_finavalu[offset_3] = aj * (1 - d_initvalu_3) - bj * d_initvalu_3;
I_Na_junc = Fjunc * GNa * pow(d_initvalu_1, 3) * d_initvalu_2 * d_initvalu_3
* (d_initvalu_39 - ena_junc);
I_Na_sl = Fsl * GNa * pow(d_initvalu_1, 3) * d_initvalu_2 * d_initvalu_3
* (d_initvalu_39 - ena_sl);
// I_Na = I_Na_junc+I_Na_sl;
// I_nabk: Na Background Current
I_nabk_junc = Fjunc * GNaB * (d_initvalu_39 - ena_junc);
I_nabk_sl = Fsl * GNaB * (d_initvalu_39 - ena_sl);
// I_nabk = I_nabk_junc+I_nabk_sl;
// I_nak: Na/K Pump Current
sigma = (exp(Nao / 67.3) - 1) / 7;
fnak =
1
/ (1 + 0.1245 * exp(-0.1 * d_initvalu_39 * FoRT)
+ 0.0365 * sigma * exp(-d_initvalu_39 * FoRT));
I_nak_junc = Fjunc * IbarNaK * fnak * Ko / (1 + pow((KmNaip / d_initvalu_32), 4)) / (Ko + KmKo);
I_nak_sl = Fsl * IbarNaK * fnak * Ko / (1 + pow((KmNaip / d_initvalu_33), 4)) / (Ko + KmKo);
I_nak = I_nak_junc + I_nak_sl;
// I_kr: Rapidly Activating K Current
gkr = 0.03 * sqrt(Ko / 5.4);
xrss = 1 / (1 + exp(-(d_initvalu_39 + 50) / 7.5));
tauxr = 1
/ (0.00138 * (d_initvalu_39 + 7) / (1 - exp(-0.123 * (d_initvalu_39 + 7)))
+ 6.1e-4 * (d_initvalu_39 + 10) / (exp(0.145 * (d_initvalu_39 + 10)) - 1));
d_finavalu[offset_12] = (xrss - d_initvalu_12) / tauxr;
rkr = 1 / (1 + exp((d_initvalu_39 + 33) / 22.4));
I_kr = gkr * d_initvalu_12 * rkr * (d_initvalu_39 - ek);
// I_ks: Slowly Activating K Current
pcaks_junc = -log10(d_initvalu_36) + 3.0;
pcaks_sl = -log10(d_initvalu_37) + 3.0;
gks_junc = 0.07 * (0.057 + 0.19 / (1 + exp((-7.2 + pcaks_junc) / 0.6)));
gks_sl = 0.07 * (0.057 + 0.19 / (1 + exp((-7.2 + pcaks_sl) / 0.6)));
eks = (1 / FoRT) * log((Ko + pNaK * Nao) / (d_initvalu_35 + pNaK * d_initvalu_34));
xsss = 1 / (1 + exp(-(d_initvalu_39 - 1.5) / 16.7));
tauxs = 1
/ (7.19e-5 * (d_initvalu_39 + 30) / (1 - exp(-0.148 * (d_initvalu_39 + 30)))
+ 1.31e-4 * (d_initvalu_39 + 30) / (exp(0.0687 * (d_initvalu_39 + 30)) - 1));
d_finavalu[offset_13] = (xsss - d_initvalu_13) / tauxs;
I_ks_junc = Fjunc * gks_junc * pow(d_initvalu_12, 2) * (d_initvalu_39 - eks);
I_ks_sl = Fsl * gks_sl * pow(d_initvalu_13, 2) * (d_initvalu_39 - eks);
I_ks = I_ks_junc + I_ks_sl;
// I_kp: Plateau K current
kp_kp = 1 / (1 + exp(7.488 - d_initvalu_39 / 5.98));
I_kp_junc = Fjunc * gkp * kp_kp * (d_initvalu_39 - ek);
I_kp_sl = Fsl * gkp * kp_kp * (d_initvalu_39 - ek);
I_kp = I_kp_junc + I_kp_sl;
// I_to: Transient Outward K Current (slow and fast components)
xtoss = 1 / (1 + exp(-(d_initvalu_39 + 3.0) / 15));
ytoss = 1 / (1 + exp((d_initvalu_39 + 33.5) / 10));
rtoss = 1 / (1 + exp((d_initvalu_39 + 33.5) / 10));
tauxtos = 9 / (1 + exp((d_initvalu_39 + 3.0) / 15)) + 0.5;
tauytos = 3e3 / (1 + exp((d_initvalu_39 + 60.0) / 10)) + 30;
taurtos = 2800 / (1 + exp((d_initvalu_39 + 60.0) / 10)) + 220;
d_finavalu[offset_8] = (xtoss - d_initvalu_8) / tauxtos;
d_finavalu[offset_9] = (ytoss - d_initvalu_9) / tauytos;
d_finavalu[offset_40] = (rtoss - d_initvalu_40) / taurtos;
I_tos = GtoSlow * d_initvalu_8 * (d_initvalu_9 + 0.5 * d_initvalu_40) * (d_initvalu_39 - ek); // [uA/uF]
//
tauxtof = 3.5 * exp(-d_initvalu_39 * d_initvalu_39 / 30 / 30) + 1.5;
tauytof = 20.0 / (1 + exp((d_initvalu_39 + 33.5) / 10)) + 20.0;
d_finavalu[offset_10] = (xtoss - d_initvalu_10) / tauxtof;
d_finavalu[offset_11] = (ytoss - d_initvalu_11) / tauytof;
I_tof = GtoFast * d_initvalu_10 * d_initvalu_11 * (d_initvalu_39 - ek);
I_to = I_tos + I_tof;
// I_ki: Time-Independent K Current
aki = 1.02 / (1 + exp(0.2385 * (d_initvalu_39 - ek - 59.215)));
bki = (0.49124 * exp(0.08032 * (d_initvalu_39 + 5.476 - ek))
+ exp(0.06175 * (d_initvalu_39 - ek - 594.31)))
/ (1 + exp(-0.5143 * (d_initvalu_39 - ek + 4.753)));
kiss = aki / (aki + bki);
I_ki = 0.9 * sqrt(Ko / 5.4) * kiss * (d_initvalu_39 - ek);
// I_ClCa: Ca-activated Cl Current, I_Clbk: background Cl Current
I_ClCa_junc = Fjunc * GClCa / (1 + KdClCa / d_initvalu_36) * (d_initvalu_39 - ecl);
I_ClCa_sl = Fsl * GClCa / (1 + KdClCa / d_initvalu_37) * (d_initvalu_39 - ecl);
I_ClCa = I_ClCa_junc + I_ClCa_sl;
I_Clbk = GClB * (d_initvalu_39 - ecl);
// I_Ca: L-type Calcium Current
dss = 1 / (1 + exp(-(d_initvalu_39 + 14.5) / 6.0));
taud = dss * (1 - exp(-(d_initvalu_39 + 14.5) / 6.0)) / (0.035 * (d_initvalu_39 + 14.5));
fss = 1 / (1 + exp((d_initvalu_39 + 35.06) / 3.6)) + 0.6 / (1 + exp((50 - d_initvalu_39) / 20));
tauf = 1 / (0.0197 * exp(-pow(0.0337 * (d_initvalu_39 + 14.5), 2)) + 0.02);
d_finavalu[offset_4] = (dss - d_initvalu_4) / taud;
d_finavalu[offset_5] = (fss - d_initvalu_5) / tauf;
d_finavalu[offset_6] = 1.7 * d_initvalu_36 * (1 - d_initvalu_6) - 11.9e-3 * d_initvalu_6; // fCa_junc
d_finavalu[offset_7] = 1.7 * d_initvalu_37 * (1 - d_initvalu_7) - 11.9e-3 * d_initvalu_7; // fCa_sl
//
ibarca_j = pCa * 4 * (d_initvalu_39 * Frdy * FoRT)
* (0.341 * d_initvalu_36 * exp(2 * d_initvalu_39 * FoRT) - 0.341 * Cao)
/ (exp(2 * d_initvalu_39 * FoRT) - 1);
ibarca_sl = pCa * 4 * (d_initvalu_39 * Frdy * FoRT)
* (0.341 * d_initvalu_37 * exp(2 * d_initvalu_39 * FoRT) - 0.341 * Cao)
/ (exp(2 * d_initvalu_39 * FoRT) - 1);
ibark = pK * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_35 * exp(d_initvalu_39 * FoRT) - 0.75 * Ko)
/ (exp(d_initvalu_39 * FoRT) - 1);
ibarna_j = pNa * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_32 * exp(d_initvalu_39 * FoRT) - 0.75 * Nao)
/ (exp(d_initvalu_39 * FoRT) - 1);
ibarna_sl = pNa * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_33 * exp(d_initvalu_39 * FoRT) - 0.75 * Nao)
/ (exp(d_initvalu_39 * FoRT) - 1);
I_Ca_junc = (Fjunc_CaL * ibarca_j * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_6)
* pow(Q10CaL, Qpow)) * 0.45;
I_Ca_sl = (Fsl_CaL * ibarca_sl * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_7)
* pow(Q10CaL, Qpow)) * 0.45;
I_Ca = I_Ca_junc + I_Ca_sl;
d_finavalu[offset_43] = -I_Ca * Cmem / (Vmyo * 2 * Frdy) * 1e3;
I_CaK = (ibark * d_initvalu_4 * d_initvalu_5
* (Fjunc_CaL * (1 - d_initvalu_6) + Fsl_CaL * (1 - d_initvalu_7)) * pow(Q10CaL, Qpow)) * 0.45;
I_CaNa_junc = (Fjunc_CaL * ibarna_j * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_6)
* pow(Q10CaL, Qpow)) * 0.45;
I_CaNa_sl = (Fsl_CaL * ibarna_sl * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_7)
* pow(Q10CaL, Qpow)) * 0.45;
// I_CaNa = I_CaNa_junc+I_CaNa_sl;
// I_Catot = I_Ca+I_CaK+I_CaNa;
// I_ncx: Na/Ca Exchanger flux
Ka_junc = 1 / (1 + pow((Kdact / d_initvalu_36), 3));
Ka_sl = 1 / (1 + pow((Kdact / d_initvalu_37), 3));
s1_junc = exp(nu * d_initvalu_39 * FoRT) * pow(d_initvalu_32, 3) * Cao;
s1_sl = exp(nu * d_initvalu_39 * FoRT) * pow(d_initvalu_33, 3) * Cao;
s2_junc = exp((nu - 1) * d_initvalu_39 * FoRT) * pow(Nao, 3) * d_initvalu_36;
s3_junc = (KmCai * pow(Nao, 3) * (1 + pow((d_initvalu_32 / KmNai), 3))
+ pow(KmNao, 3) * d_initvalu_36 + pow(KmNai, 3) * Cao * (1 + d_initvalu_36 / KmCai)
+ KmCao * pow(d_initvalu_32, 3) + pow(d_initvalu_32, 3) * Cao + pow(Nao, 3) * d_initvalu_36)
* (1 + ksat * exp((nu - 1) * d_initvalu_39 * FoRT));
s2_sl = exp((nu - 1) * d_initvalu_39 * FoRT) * pow(Nao, 3) * d_initvalu_37;
s3_sl = (KmCai * pow(Nao, 3) * (1 + pow((d_initvalu_33 / KmNai), 3))
+ pow(KmNao, 3) * d_initvalu_37 + pow(KmNai, 3) * Cao * (1 + d_initvalu_37 / KmCai)
+ KmCao * pow(d_initvalu_33, 3) + pow(d_initvalu_33, 3) * Cao + pow(Nao, 3) * d_initvalu_37)
* (1 + ksat * exp((nu - 1) * d_initvalu_39 * FoRT));
I_ncx_junc = Fjunc * IbarNCX * pow(Q10NCX, Qpow) * Ka_junc * (s1_junc - s2_junc) / s3_junc;
I_ncx_sl = Fsl * IbarNCX * pow(Q10NCX, Qpow) * Ka_sl * (s1_sl - s2_sl) / s3_sl;
I_ncx = I_ncx_junc + I_ncx_sl;
d_finavalu[offset_45] = 2 * I_ncx * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// I_pca: Sarcolemmal Ca Pump Current
I_pca_junc = Fjunc * pow(Q10SLCaP, Qpow) * IbarSLCaP * pow(d_initvalu_36, float(1.6))
/ (pow(KmPCa, float(1.6)) + pow(d_initvalu_36, float(1.6)));
I_pca_sl = Fsl * pow(Q10SLCaP, Qpow) * IbarSLCaP * pow(d_initvalu_37, float(1.6))
/ (pow(KmPCa, float(1.6)) + pow(d_initvalu_37, float(1.6)));
I_pca = I_pca_junc + I_pca_sl;
d_finavalu[offset_44] = -I_pca * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// I_cabk: Ca Background Current
I_cabk_junc = Fjunc * GCaB * (d_initvalu_39 - eca_junc);
I_cabk_sl = Fsl * GCaB * (d_initvalu_39 - eca_sl);
I_cabk = I_cabk_junc + I_cabk_sl;
d_finavalu[offset_46] = -I_cabk * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// SR fluxes: Calcium Release, SR Ca pump, SR Ca leak
MaxSR = 15;
MinSR = 1;
kCaSR = MaxSR - (MaxSR - MinSR) / (1 + pow(ec50SR / d_initvalu_31, float(2.5)));
koSRCa = koCa / kCaSR;
kiSRCa = kiCa * kCaSR;
RI = 1 - d_initvalu_14 - d_initvalu_15 - d_initvalu_16;
d_finavalu[offset_14] = (kim * RI - kiSRCa * d_initvalu_36 * d_initvalu_14)
- (koSRCa * pow(d_initvalu_36, 2) * d_initvalu_14 - kom * d_initvalu_15); // R
d_finavalu[offset_15] = (koSRCa * pow(d_initvalu_36, 2) * d_initvalu_14 - kom * d_initvalu_15)
- (kiSRCa * d_initvalu_36 * d_initvalu_15 - kim * d_initvalu_16); // O
d_finavalu[offset_16] = (kiSRCa * d_initvalu_36 * d_initvalu_15 - kim * d_initvalu_16)
- (kom * d_initvalu_16 - koSRCa * pow(d_initvalu_36, 2) * RI); // I
J_SRCarel = ks * d_initvalu_15 * (d_initvalu_31 - d_initvalu_36); // [mM/ms]
J_serca = pow(Q10SRCaP, Qpow) * Vmax_SRCaP
* (pow((d_initvalu_38 / Kmf), hillSRCaP) - pow((d_initvalu_31 / Kmr), hillSRCaP))
/ (1 + pow((d_initvalu_38 / Kmf), hillSRCaP) + pow((d_initvalu_31 / Kmr), hillSRCaP));
J_SRleak = 5.348e-6 * (d_initvalu_31 - d_initvalu_36); // [mM/ms]
// Sodium and Calcium Buffering
d_finavalu[offset_17] = kon_na * d_initvalu_32 * (Bmax_Naj - d_initvalu_17)
- koff_na * d_initvalu_17; // NaBj [mM/ms]
d_finavalu[offset_18] = kon_na * d_initvalu_33 * (Bmax_Nasl - d_initvalu_18)
- koff_na * d_initvalu_18; // NaBsl [mM/ms]
// Cytosolic Ca Buffers
d_finavalu[offset_19] = kon_tncl * d_initvalu_38 * (Bmax_TnClow - d_initvalu_19)
- koff_tncl * d_initvalu_19; // TnCL [mM/ms]
d_finavalu[offset_20] = kon_tnchca * d_initvalu_38
* (Bmax_TnChigh - d_initvalu_20 - d_initvalu_21) - koff_tnchca * d_initvalu_20; // TnCHc [mM/ms]
d_finavalu[offset_21] = kon_tnchmg * Mgi * (Bmax_TnChigh - d_initvalu_20 - d_initvalu_21)
- koff_tnchmg * d_initvalu_21; // TnCHm [mM/ms]
d_finavalu[offset_22] = 0; // CaM [mM/ms]
d_finavalu[offset_23] = kon_myoca * d_initvalu_38 * (Bmax_myosin - d_initvalu_23 - d_initvalu_24)
- koff_myoca * d_initvalu_23; // Myosin_ca [mM/ms]
d_finavalu[offset_24] = kon_myomg * Mgi * (Bmax_myosin - d_initvalu_23 - d_initvalu_24)
- koff_myomg * d_initvalu_24; // Myosin_mg [mM/ms]
d_finavalu[offset_25] = kon_sr * d_initvalu_38 * (Bmax_SR - d_initvalu_25)
- koff_sr * d_initvalu_25; // SRB [mM/ms]
J_CaB_cytosol = d_finavalu[offset_19] + d_finavalu[offset_20] + d_finavalu[offset_21]
+ d_finavalu[offset_22] + d_finavalu[offset_23] + d_finavalu[offset_24]
+ d_finavalu[offset_25];
// Junctional and SL Ca Buffers
d_finavalu[offset_26] = kon_sll * d_initvalu_36 * (Bmax_SLlowj - d_initvalu_26)
- koff_sll * d_initvalu_26; // SLLj [mM/ms]
d_finavalu[offset_27] = kon_sll * d_initvalu_37 * (Bmax_SLlowsl - d_initvalu_27)
- koff_sll * d_initvalu_27; // SLLsl [mM/ms]
d_finavalu[offset_28] = kon_slh * d_initvalu_36 * (Bmax_SLhighj - d_initvalu_28)
- koff_slh * d_initvalu_28; // SLHj [mM/ms]
d_finavalu[offset_29] = kon_slh * d_initvalu_37 * (Bmax_SLhighsl - d_initvalu_29)
- koff_slh * d_initvalu_29; // SLHsl [mM/ms]
J_CaB_junction = d_finavalu[offset_26] + d_finavalu[offset_28];
J_CaB_sl = d_finavalu[offset_27] + d_finavalu[offset_29];
// SR Ca Concentrations
d_finavalu[offset_30] = kon_csqn * d_initvalu_31 * (Bmax_Csqn - d_initvalu_30)
- koff_csqn * d_initvalu_30; // Csqn [mM/ms]
oneovervsr = 1 / Vsr;
d_finavalu[offset_31] = J_serca * Vmyo * oneovervsr - (J_SRleak * Vmyo * oneovervsr + J_SRCarel)
- d_finavalu[offset_30]; // Ca_sr [mM/ms] %Ratio 3 leak current
// Sodium Concentrations
I_Na_tot_junc = I_Na_junc + I_nabk_junc + 3 * I_ncx_junc + 3 * I_nak_junc + I_CaNa_junc;// [uA/uF]
I_Na_tot_sl = I_Na_sl + I_nabk_sl + 3 * I_ncx_sl + 3 * I_nak_sl + I_CaNa_sl; // [uA/uF]
d_finavalu[offset_32] = -I_Na_tot_junc * Cmem / (Vjunc * Frdy)
+ J_na_juncsl / Vjunc * (d_initvalu_33 - d_initvalu_32) - d_finavalu[offset_17];
oneovervsl = 1 / Vsl;
d_finavalu[offset_33] = -I_Na_tot_sl * Cmem * oneovervsl / Frdy
+ J_na_juncsl * oneovervsl * (d_initvalu_32 - d_initvalu_33)
+ J_na_slmyo * oneovervsl * (d_initvalu_34 - d_initvalu_33) - d_finavalu[offset_18];
d_finavalu[offset_34] = J_na_slmyo / Vmyo * (d_initvalu_33 - d_initvalu_34); // [mM/msec]
// Potassium Concentration
I_K_tot = I_to + I_kr + I_ks + I_ki - 2 * I_nak + I_CaK + I_kp; // [uA/uF]
d_finavalu[offset_35] = 0; // [mM/msec]
// Calcium Concentrations
I_Ca_tot_junc = I_Ca_junc + I_cabk_junc + I_pca_junc - 2 * I_ncx_junc; // [uA/uF]
I_Ca_tot_sl = I_Ca_sl + I_cabk_sl + I_pca_sl - 2 * I_ncx_sl; // [uA/uF]
d_finavalu[offset_36] = -I_Ca_tot_junc * Cmem / (Vjunc * 2 * Frdy)
+ J_ca_juncsl / Vjunc * (d_initvalu_37 - d_initvalu_36) - J_CaB_junction
+ (J_SRCarel) * Vsr / Vjunc + J_SRleak * Vmyo / Vjunc; // Ca_j
d_finavalu[offset_37] = -I_Ca_tot_sl * Cmem / (Vsl * 2 * Frdy)
+ J_ca_juncsl / Vsl * (d_initvalu_36 - d_initvalu_37)
+ J_ca_slmyo / Vsl * (d_initvalu_38 - d_initvalu_37) - J_CaB_sl; // Ca_sl
d_finavalu[offset_38] = -J_serca - J_CaB_cytosol
+ J_ca_slmyo / Vmyo * (d_initvalu_37 - d_initvalu_38);
// junc_sl=J_ca_juncsl/Vsl*(d_initvalu_36-d_initvalu_37);
// sl_junc=J_ca_juncsl/Vjunc*(d_initvalu_37-d_initvalu_36);
// sl_myo=J_ca_slmyo/Vsl*(d_initvalu_38-d_initvalu_37);
// myo_sl=J_ca_slmyo/Vmyo*(d_initvalu_37-d_initvalu_38);
// Simulation type
state = 1;
switch (state) {
case 0:
I_app = 0;
break;
case 1: // pace w/ current injection at cycleLength 'cycleLength'
if (fmod(timeinst, cycleLength) <= 5) {
I_app = 9.5;
} else {
I_app = 0.0;
}
break;
case 2:
V_hold = -55;
V_test = 0;
if (timeinst > 0.5 & timeinst < 200.5) {
V_clamp = V_test;
} else {
V_clamp = V_hold;
}
R_clamp = 0.04;
I_app = (V_clamp - d_initvalu_39) / R_clamp;
break;
}
// Membrane Potential
I_Na_tot = I_Na_tot_junc + I_Na_tot_sl; // [uA/uF]
I_Cl_tot = I_ClCa + I_Clbk; // [uA/uF]
I_Ca_tot = I_Ca_tot_junc + I_Ca_tot_sl;
I_tot = I_Na_tot + I_Cl_tot + I_Ca_tot + I_K_tot;
d_finavalu[offset_39] = -(I_tot - I_app);
// Set unused output values to 0 (MATLAB does it by default)
d_finavalu[offset_41] = 0;
d_finavalu[offset_42] = 0;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //=====================================================================
// MAIN FUNCTION
//=====================================================================
__device__ void kernel_ecc(float timeinst, float* d_initvalu, float *d_finavalu, int valu_offset,
float* d_params) {
//=====================================================================
// VARIABLES
//=====================================================================
// input parameters
float cycleLength;
// variable references // GET VARIABLES FROM MEMORY AND SAVE LOCALLY !!!!!!!!!!!!!!!!!!
int offset_1;
int offset_2;
int offset_3;
int offset_4;
int offset_5;
int offset_6;
int offset_7;
int offset_8;
int offset_9;
int offset_10;
int offset_11;
int offset_12;
int offset_13;
int offset_14;
int offset_15;
int offset_16;
int offset_17;
int offset_18;
int offset_19;
int offset_20;
int offset_21;
int offset_22;
int offset_23;
int offset_24;
int offset_25;
int offset_26;
int offset_27;
int offset_28;
int offset_29;
int offset_30;
int offset_31;
int offset_32;
int offset_33;
int offset_34;
int offset_35;
int offset_36;
int offset_37;
int offset_38;
int offset_39;
int offset_40;
int offset_41;
int offset_42;
int offset_43;
int offset_44;
int offset_45;
int offset_46;
// stored input array
float d_initvalu_1;
float d_initvalu_2;
float d_initvalu_3;
float d_initvalu_4;
float d_initvalu_5;
float d_initvalu_6;
float d_initvalu_7;
float d_initvalu_8;
float d_initvalu_9;
float d_initvalu_10;
float d_initvalu_11;
float d_initvalu_12;
float d_initvalu_13;
float d_initvalu_14;
float d_initvalu_15;
float d_initvalu_16;
float d_initvalu_17;
float d_initvalu_18;
float d_initvalu_19;
float d_initvalu_20;
float d_initvalu_21;
// float d_initvalu_22;
float d_initvalu_23;
float d_initvalu_24;
float d_initvalu_25;
float d_initvalu_26;
float d_initvalu_27;
float d_initvalu_28;
float d_initvalu_29;
float d_initvalu_30;
float d_initvalu_31;
float d_initvalu_32;
float d_initvalu_33;
float d_initvalu_34;
float d_initvalu_35;
float d_initvalu_36;
float d_initvalu_37;
float d_initvalu_38;
float d_initvalu_39;
float d_initvalu_40;
// float d_initvalu_41;
// float d_initvalu_42;
// float d_initvalu_43;
// float d_initvalu_44;
// float d_initvalu_45;
// float d_initvalu_46;
// matlab constants undefined in c
float pi;
// Constants
float R; // [J/kmol*K]
float Frdy; // [C/mol]
float Temp; // [K] 310
float FoRT; //
float Cmem; // [F] membrane capacitance
float Qpow;
// Cell geometry
float cellLength; // cell length [um]
float cellRadius; // cell radius [um]
// float junctionLength; // junc length [um]
// float junctionRadius; // junc radius [um]
// float distSLcyto; // dist. SL to cytosol [um]
// float distJuncSL; // dist. junc to SL [um]
// float DcaJuncSL; // Dca junc to SL [cm^2/sec]
// float DcaSLcyto; // Dca SL to cyto [cm^2/sec]
// float DnaJuncSL; // Dna junc to SL [cm^2/sec]
// float DnaSLcyto; // Dna SL to cyto [cm^2/sec]
float Vcell; // [L]
float Vmyo;
float Vsr;
float Vsl;
float Vjunc;
// float SAjunc; // [um^2]
// float SAsl; // [um^2]
float J_ca_juncsl; // [L/msec]
float J_ca_slmyo; // [L/msec]
float J_na_juncsl; // [L/msec]
float J_na_slmyo; // [L/msec]
// Fractional currents in compartments
float Fjunc;
float Fsl;
float Fjunc_CaL;
float Fsl_CaL;
// Fixed ion concentrations
float Cli; // Intracellular Cl [mM]
float Clo; // Extracellular Cl [mM]
float Ko; // Extracellular K [mM]
float Nao; // Extracellular Na [mM]
float Cao; // Extracellular Ca [mM]
float Mgi; // Intracellular Mg [mM]
// Nernst Potentials
float ena_junc; // [mV]
float ena_sl; // [mV]
float ek; // [mV]
float eca_junc; // [mV]
float eca_sl; // [mV]
float ecl; // [mV]
// Na transport parameters
float GNa; // [mS/uF]
float GNaB; // [mS/uF]
float IbarNaK; // [uA/uF]
float KmNaip; // [mM]
float KmKo; // [mM]
// float Q10NaK;
// float Q10KmNai;
// K current parameters
float pNaK;
float GtoSlow; // [mS/uF]
float GtoFast; // [mS/uF]
float gkp;
// Cl current parameters
float GClCa; // [mS/uF]
float GClB; // [mS/uF]
float KdClCa; // [mM] // [mM]
// I_Ca parameters
float pNa; // [cm/sec]
float pCa; // [cm/sec]
float pK; // [cm/sec]
// float KmCa; // [mM]
float Q10CaL;
// Ca transport parameters
float IbarNCX; // [uA/uF]
float KmCai; // [mM]
float KmCao; // [mM]
float KmNai; // [mM]
float KmNao; // [mM]
float ksat; // [none]
float nu; // [none]
float Kdact; // [mM]
float Q10NCX; // [none]
float IbarSLCaP; // [uA/uF]
float KmPCa; // [mM]
float GCaB; // [uA/uF]
float Q10SLCaP; // [none] // [none]
// SR flux parameters
float Q10SRCaP; // [none]
float Vmax_SRCaP; // [mM/msec] (mmol/L cytosol/msec)
float Kmf; // [mM]
float Kmr; // [mM]L cytosol
float hillSRCaP; // [mM]
float ks; // [1/ms]
float koCa; // [mM^-2 1/ms]
float kom; // [1/ms]
float kiCa; // [1/mM/ms]
float kim; // [1/ms]
float ec50SR; // [mM]
// Buffering parameters
float Bmax_Naj; // [mM]
float Bmax_Nasl; // [mM]
float koff_na; // [1/ms]
float kon_na; // [1/mM/ms]
float Bmax_TnClow; // [mM], TnC low affinity
float koff_tncl; // [1/ms]
float kon_tncl; // [1/mM/ms]
float Bmax_TnChigh; // [mM], TnC high affinity
float koff_tnchca; // [1/ms]
float kon_tnchca; // [1/mM/ms]
float koff_tnchmg; // [1/ms]
float kon_tnchmg; // [1/mM/ms]
// float Bmax_CaM; // [mM], CaM buffering
// float koff_cam; // [1/ms]
// float kon_cam; // [1/mM/ms]
float Bmax_myosin; // [mM], Myosin buffering
float koff_myoca; // [1/ms]
float kon_myoca; // [1/mM/ms]
float koff_myomg; // [1/ms]
float kon_myomg; // [1/mM/ms]
float Bmax_SR; // [mM]
float koff_sr; // [1/ms]
float kon_sr; // [1/mM/ms]
float Bmax_SLlowsl; // [mM], SL buffering
float Bmax_SLlowj; // [mM]
float koff_sll; // [1/ms]
float kon_sll; // [1/mM/ms]
float Bmax_SLhighsl; // [mM]
float Bmax_SLhighj; // [mM]
float koff_slh; // [1/ms]
float kon_slh; // [1/mM/ms]
float Bmax_Csqn; // 140e-3*Vmyo/Vsr; [mM]
float koff_csqn; // [1/ms]
float kon_csqn; // [1/mM/ms]
// I_Na: Fast Na Current
float am;
float bm;
float ah;
float bh;
float aj;
float bj;
float I_Na_junc;
float I_Na_sl;
// float I_Na;
// I_nabk: Na Background Current
float I_nabk_junc;
float I_nabk_sl;
// float I_nabk;
// I_nak: Na/K Pump Current
float sigma;
float fnak;
float I_nak_junc;
float I_nak_sl;
float I_nak;
// I_kr: Rapidly Activating K Current
float gkr;
float xrss;
float tauxr;
float rkr;
float I_kr;
// I_ks: Slowly Activating K Current
float pcaks_junc;
float pcaks_sl;
float gks_junc;
float gks_sl;
float eks;
float xsss;
float tauxs;
float I_ks_junc;
float I_ks_sl;
float I_ks;
// I_kp: Plateau K current
float kp_kp;
float I_kp_junc;
float I_kp_sl;
float I_kp;
// I_to: Transient Outward K Current (slow and fast components)
float xtoss;
float ytoss;
float rtoss;
float tauxtos;
float tauytos;
float taurtos;
float I_tos;
//
float tauxtof;
float tauytof;
float I_tof;
float I_to;
// I_ki: Time-Independent K Current
float aki;
float bki;
float kiss;
float I_ki;
// I_ClCa: Ca-activated Cl Current, I_Clbk: background Cl Current
float I_ClCa_junc;
float I_ClCa_sl;
float I_ClCa;
float I_Clbk;
// I_Ca: L-type Calcium Current
float dss;
float taud;
float fss;
float tauf;
//
float ibarca_j;
float ibarca_sl;
float ibark;
float ibarna_j;
float ibarna_sl;
float I_Ca_junc;
float I_Ca_sl;
float I_Ca;
float I_CaK;
float I_CaNa_junc;
float I_CaNa_sl;
// float I_CaNa;
// float I_Catot;
// I_ncx: Na/Ca Exchanger flux
float Ka_junc;
float Ka_sl;
float s1_junc;
float s1_sl;
float s2_junc;
float s3_junc;
float s2_sl;
float s3_sl;
float I_ncx_junc;
float I_ncx_sl;
float I_ncx;
// I_pca: Sarcolemmal Ca Pump Current
float I_pca_junc;
float I_pca_sl;
float I_pca;
// I_cabk: Ca Background Current
float I_cabk_junc;
float I_cabk_sl;
float I_cabk;
// SR fluxes: Calcium Release, SR Ca pump, SR Ca leak
float MaxSR;
float MinSR;
float kCaSR;
float koSRCa;
float kiSRCa;
float RI;
float J_SRCarel; // [mM/ms]
float J_serca;
float J_SRleak; // [mM/ms]
// Cytosolic Ca Buffers
float J_CaB_cytosol;
// Junctional and SL Ca Buffers
float J_CaB_junction;
float J_CaB_sl;
// SR Ca Concentrations
float oneovervsr;
// Sodium Concentrations
float I_Na_tot_junc; // [uA/uF]
float I_Na_tot_sl; // [uA/uF]
float oneovervsl;
// Potassium Concentration
float I_K_tot;
// Calcium Concentrations
float I_Ca_tot_junc; // [uA/uF]
float I_Ca_tot_sl; // [uA/uF]
// float junc_sl;
// float sl_junc;
// float sl_myo;
// float myo_sl;
// Simulation type
int state; // 0-none; 1-pace; 2-vclamp
float I_app;
float V_hold;
float V_test;
float V_clamp;
float R_clamp;
// Membrane Potential
float I_Na_tot; // [uA/uF]
float I_Cl_tot; // [uA/uF]
float I_Ca_tot;
float I_tot;
//=====================================================================
// EXECUTION
//=====================================================================
// input parameters
cycleLength = d_params[15];
// variable references
offset_1 = valu_offset;
offset_2 = valu_offset + 1;
offset_3 = valu_offset + 2;
offset_4 = valu_offset + 3;
offset_5 = valu_offset + 4;
offset_6 = valu_offset + 5;
offset_7 = valu_offset + 6;
offset_8 = valu_offset + 7;
offset_9 = valu_offset + 8;
offset_10 = valu_offset + 9;
offset_11 = valu_offset + 10;
offset_12 = valu_offset + 11;
offset_13 = valu_offset + 12;
offset_14 = valu_offset + 13;
offset_15 = valu_offset + 14;
offset_16 = valu_offset + 15;
offset_17 = valu_offset + 16;
offset_18 = valu_offset + 17;
offset_19 = valu_offset + 18;
offset_20 = valu_offset + 19;
offset_21 = valu_offset + 20;
offset_22 = valu_offset + 21;
offset_23 = valu_offset + 22;
offset_24 = valu_offset + 23;
offset_25 = valu_offset + 24;
offset_26 = valu_offset + 25;
offset_27 = valu_offset + 26;
offset_28 = valu_offset + 27;
offset_29 = valu_offset + 28;
offset_30 = valu_offset + 29;
offset_31 = valu_offset + 30;
offset_32 = valu_offset + 31;
offset_33 = valu_offset + 32;
offset_34 = valu_offset + 33;
offset_35 = valu_offset + 34;
offset_36 = valu_offset + 35;
offset_37 = valu_offset + 36;
offset_38 = valu_offset + 37;
offset_39 = valu_offset + 38;
offset_40 = valu_offset + 39;
offset_41 = valu_offset + 40;
offset_42 = valu_offset + 41;
offset_43 = valu_offset + 42;
offset_44 = valu_offset + 43;
offset_45 = valu_offset + 44;
offset_46 = valu_offset + 45;
// stored input array
d_initvalu_1 = d_initvalu[offset_1];
d_initvalu_2 = d_initvalu[offset_2];
d_initvalu_3 = d_initvalu[offset_3];
d_initvalu_4 = d_initvalu[offset_4];
d_initvalu_5 = d_initvalu[offset_5];
d_initvalu_6 = d_initvalu[offset_6];
d_initvalu_7 = d_initvalu[offset_7];
d_initvalu_8 = d_initvalu[offset_8];
d_initvalu_9 = d_initvalu[offset_9];
d_initvalu_10 = d_initvalu[offset_10];
d_initvalu_11 = d_initvalu[offset_11];
d_initvalu_12 = d_initvalu[offset_12];
d_initvalu_13 = d_initvalu[offset_13];
d_initvalu_14 = d_initvalu[offset_14];
d_initvalu_15 = d_initvalu[offset_15];
d_initvalu_16 = d_initvalu[offset_16];
d_initvalu_17 = d_initvalu[offset_17];
d_initvalu_18 = d_initvalu[offset_18];
d_initvalu_19 = d_initvalu[offset_19];
d_initvalu_20 = d_initvalu[offset_20];
d_initvalu_21 = d_initvalu[offset_21];
// d_initvalu_22 = d_initvalu[offset_22];
d_initvalu_23 = d_initvalu[offset_23];
d_initvalu_24 = d_initvalu[offset_24];
d_initvalu_25 = d_initvalu[offset_25];
d_initvalu_26 = d_initvalu[offset_26];
d_initvalu_27 = d_initvalu[offset_27];
d_initvalu_28 = d_initvalu[offset_28];
d_initvalu_29 = d_initvalu[offset_29];
d_initvalu_30 = d_initvalu[offset_30];
d_initvalu_31 = d_initvalu[offset_31];
d_initvalu_32 = d_initvalu[offset_32];
d_initvalu_33 = d_initvalu[offset_33];
d_initvalu_34 = d_initvalu[offset_34];
d_initvalu_35 = d_initvalu[offset_35];
d_initvalu_36 = d_initvalu[offset_36];
d_initvalu_37 = d_initvalu[offset_37];
d_initvalu_38 = d_initvalu[offset_38];
d_initvalu_39 = d_initvalu[offset_39];
d_initvalu_40 = d_initvalu[offset_40];
// d_initvalu_41 = d_initvalu[offset_41];
// d_initvalu_42 = d_initvalu[offset_42];
// d_initvalu_43 = d_initvalu[offset_43];
// d_initvalu_44 = d_initvalu[offset_44];
// d_initvalu_45 = d_initvalu[offset_45];
// d_initvalu_46 = d_initvalu[offset_46];
// matlab constants undefined in c
pi = 3.1416;
// Constants
R = 8314; // [J/kmol*K]
Frdy = 96485; // [C/mol]
Temp = 310; // [K] 310
FoRT = Frdy / R / Temp; //
Cmem = 1.3810e-10; // [F] membrane capacitance
Qpow = (Temp - 310) / 10;
// Cell geometry
cellLength = 100; // cell length [um]
cellRadius = 10.25; // cell radius [um]
// junctionLength = 160e-3; // junc length [um]
// junctionRadius = 15e-3; // junc radius [um]
// distSLcyto = 0.45; // dist. SL to cytosol [um]
// distJuncSL = 0.5; // dist. junc to SL [um]
// DcaJuncSL = 1.64e-6; // Dca junc to SL [cm^2/sec]
// DcaSLcyto = 1.22e-6; // Dca SL to cyto [cm^2/sec]
// DnaJuncSL = 1.09e-5; // Dna junc to SL [cm^2/sec]
// DnaSLcyto = 1.79e-5; // Dna SL to cyto [cm^2/sec]
Vcell = pi * pow(cellRadius, 2) * cellLength * 1e-15; // [L]
Vmyo = 0.65 * Vcell;
Vsr = 0.035 * Vcell;
Vsl = 0.02 * Vcell;
Vjunc = 0.0539 * 0.01 * Vcell;
// SAjunc = 20150*pi*2*junctionLength*junctionRadius; // [um^2]
// SAsl = pi*2*cellRadius*cellLength; // [um^2]
J_ca_juncsl = 1 / 1.2134e12; // [L/msec]
J_ca_slmyo = 1 / 2.68510e11; // [L/msec]
J_na_juncsl = 1 / (1.6382e12 / 3 * 100); // [L/msec]
J_na_slmyo = 1 / (1.8308e10 / 3 * 100); // [L/msec]
// Fractional currents in compartments
Fjunc = 0.11;
Fsl = 1 - Fjunc;
Fjunc_CaL = 0.9;
Fsl_CaL = 1 - Fjunc_CaL;
// Fixed ion concentrations
Cli = 15; // Intracellular Cl [mM]
Clo = 150; // Extracellular Cl [mM]
Ko = 5.4; // Extracellular K [mM]
Nao = 140; // Extracellular Na [mM]
Cao = 1.8; // Extracellular Ca [mM]
Mgi = 1; // Intracellular Mg [mM]
// Nernst Potentials
ena_junc = (1 / FoRT) * log(Nao / d_initvalu_32); // [mV]
ena_sl = (1 / FoRT) * log(Nao / d_initvalu_33); // [mV]
ek = (1 / FoRT) * log(Ko / d_initvalu_35); // [mV]
eca_junc = (1 / FoRT / 2) * log(Cao / d_initvalu_36); // [mV]
eca_sl = (1 / FoRT / 2) * log(Cao / d_initvalu_37); // [mV]
ecl = (1 / FoRT) * log(Cli / Clo); // [mV]
// Na transport parameters
GNa = 16.0; // [mS/uF]
GNaB = 0.297e-3; // [mS/uF]
IbarNaK = 1.90719; // [uA/uF]
KmNaip = 11; // [mM]
KmKo = 1.5; // [mM]
// Q10NaK = 1.63;
// Q10KmNai = 1.39;
// K current parameters
pNaK = 0.01833;
GtoSlow = 0.06; // [mS/uF]
GtoFast = 0.02; // [mS/uF]
gkp = 0.001;
// Cl current parameters
GClCa = 0.109625; // [mS/uF]
GClB = 9e-3; // [mS/uF]
KdClCa = 100e-3; // [mM]
// I_Ca parameters
pNa = 1.5e-8; // [cm/sec]
pCa = 5.4e-4; // [cm/sec]
pK = 2.7e-7; // [cm/sec]
// KmCa = 0.6e-3; // [mM]
Q10CaL = 1.8;
// Ca transport parameters
IbarNCX = 9.0; // [uA/uF]
KmCai = 3.59e-3; // [mM]
KmCao = 1.3; // [mM]
KmNai = 12.29; // [mM]
KmNao = 87.5; // [mM]
ksat = 0.27; // [none]
nu = 0.35; // [none]
Kdact = 0.256e-3; // [mM]
Q10NCX = 1.57; // [none]
IbarSLCaP = 0.0673; // [uA/uF]
KmPCa = 0.5e-3; // [mM]
GCaB = 2.513e-4; // [uA/uF]
Q10SLCaP = 2.35; // [none]
// SR flux parameters
Q10SRCaP = 2.6; // [none]
Vmax_SRCaP = 2.86e-4; // [mM/msec] (mmol/L cytosol/msec)
Kmf = 0.246e-3; // [mM]
Kmr = 1.7; // [mM]L cytosol
hillSRCaP = 1.787; // [mM]
ks = 25; // [1/ms]
koCa = 10; // [mM^-2 1/ms]
kom = 0.06; // [1/ms]
kiCa = 0.5; // [1/mM/ms]
kim = 0.005; // [1/ms]
ec50SR = 0.45; // [mM]
// Buffering parameters
Bmax_Naj = 7.561; // [mM]
Bmax_Nasl = 1.65; // [mM]
koff_na = 1e-3; // [1/ms]
kon_na = 0.1e-3; // [1/mM/ms]
Bmax_TnClow = 70e-3; // [mM], TnC low affinity
koff_tncl = 19.6e-3; // [1/ms]
kon_tncl = 32.7; // [1/mM/ms]
Bmax_TnChigh = 140e-3; // [mM], TnC high affinity
koff_tnchca = 0.032e-3; // [1/ms]
kon_tnchca = 2.37; // [1/mM/ms]
koff_tnchmg = 3.33e-3; // [1/ms]
kon_tnchmg = 3e-3; // [1/mM/ms]
// Bmax_CaM = 24e-3; // [mM], CaM buffering
// koff_cam = 238e-3; // [1/ms]
// kon_cam = 34; // [1/mM/ms]
Bmax_myosin = 140e-3; // [mM], Myosin buffering
koff_myoca = 0.46e-3; // [1/ms]
kon_myoca = 13.8; // [1/mM/ms]
koff_myomg = 0.057e-3; // [1/ms]
kon_myomg = 0.0157; // [1/mM/ms]
Bmax_SR = 19 * 0.9e-3; // [mM]
koff_sr = 60e-3; // [1/ms]
kon_sr = 100; // [1/mM/ms]
Bmax_SLlowsl = 37.38e-3 * Vmyo / Vsl; // [mM], SL buffering
Bmax_SLlowj = 4.62e-3 * Vmyo / Vjunc * 0.1; // [mM]
koff_sll = 1300e-3; // [1/ms]
kon_sll = 100; // [1/mM/ms]
Bmax_SLhighsl = 13.35e-3 * Vmyo / Vsl; // [mM]
Bmax_SLhighj = 1.65e-3 * Vmyo / Vjunc * 0.1; // [mM]
koff_slh = 30e-3; // [1/ms]
kon_slh = 100; // [1/mM/ms]
Bmax_Csqn = 2.7; // 140e-3*Vmyo/Vsr; [mM]
koff_csqn = 65; // [1/ms]
kon_csqn = 100; // [1/mM/ms]
// I_Na: Fast Na Current
am = 0.32 * (d_initvalu_39 + 47.13) / (1 - exp(-0.1 * (d_initvalu_39 + 47.13)));
bm = 0.08 * exp(-d_initvalu_39 / 11);
if (d_initvalu_39 >= -40) {
ah = 0;
aj = 0;
bh = 1 / (0.13 * (1 + exp(-(d_initvalu_39 + 10.66) / 11.1)));
bj = 0.3 * exp(-2.535e-7 * d_initvalu_39) / (1 + exp(-0.1 * (d_initvalu_39 + 32)));
} else {
ah = 0.135 * exp((80 + d_initvalu_39) / -6.8);
bh = 3.56 * exp(0.079 * d_initvalu_39) + 3.1e5 * exp(0.35 * d_initvalu_39);
aj = (-127140 * exp(0.2444 * d_initvalu_39) - 3.474e-5 * exp(-0.04391 * d_initvalu_39))
* (d_initvalu_39 + 37.78) / (1 + exp(0.311 * (d_initvalu_39 + 79.23)));
bj = 0.1212 * exp(-0.01052 * d_initvalu_39) / (1 + exp(-0.1378 * (d_initvalu_39 + 40.14)));
}
d_finavalu[offset_1] = am * (1 - d_initvalu_1) - bm * d_initvalu_1;
d_finavalu[offset_2] = ah * (1 - d_initvalu_2) - bh * d_initvalu_2;
d_finavalu[offset_3] = aj * (1 - d_initvalu_3) - bj * d_initvalu_3;
I_Na_junc = Fjunc * GNa * pow(d_initvalu_1, 3) * d_initvalu_2 * d_initvalu_3
* (d_initvalu_39 - ena_junc);
I_Na_sl = Fsl * GNa * pow(d_initvalu_1, 3) * d_initvalu_2 * d_initvalu_3
* (d_initvalu_39 - ena_sl);
// I_Na = I_Na_junc+I_Na_sl;
// I_nabk: Na Background Current
I_nabk_junc = Fjunc * GNaB * (d_initvalu_39 - ena_junc);
I_nabk_sl = Fsl * GNaB * (d_initvalu_39 - ena_sl);
// I_nabk = I_nabk_junc+I_nabk_sl;
// I_nak: Na/K Pump Current
sigma = (exp(Nao / 67.3) - 1) / 7;
fnak =
1
/ (1 + 0.1245 * exp(-0.1 * d_initvalu_39 * FoRT)
+ 0.0365 * sigma * exp(-d_initvalu_39 * FoRT));
I_nak_junc = Fjunc * IbarNaK * fnak * Ko / (1 + pow((KmNaip / d_initvalu_32), 4)) / (Ko + KmKo);
I_nak_sl = Fsl * IbarNaK * fnak * Ko / (1 + pow((KmNaip / d_initvalu_33), 4)) / (Ko + KmKo);
I_nak = I_nak_junc + I_nak_sl;
// I_kr: Rapidly Activating K Current
gkr = 0.03 * sqrt(Ko / 5.4);
xrss = 1 / (1 + exp(-(d_initvalu_39 + 50) / 7.5));
tauxr = 1
/ (0.00138 * (d_initvalu_39 + 7) / (1 - exp(-0.123 * (d_initvalu_39 + 7)))
+ 6.1e-4 * (d_initvalu_39 + 10) / (exp(0.145 * (d_initvalu_39 + 10)) - 1));
d_finavalu[offset_12] = (xrss - d_initvalu_12) / tauxr;
rkr = 1 / (1 + exp((d_initvalu_39 + 33) / 22.4));
I_kr = gkr * d_initvalu_12 * rkr * (d_initvalu_39 - ek);
// I_ks: Slowly Activating K Current
pcaks_junc = -log10(d_initvalu_36) + 3.0;
pcaks_sl = -log10(d_initvalu_37) + 3.0;
gks_junc = 0.07 * (0.057 + 0.19 / (1 + exp((-7.2 + pcaks_junc) / 0.6)));
gks_sl = 0.07 * (0.057 + 0.19 / (1 + exp((-7.2 + pcaks_sl) / 0.6)));
eks = (1 / FoRT) * log((Ko + pNaK * Nao) / (d_initvalu_35 + pNaK * d_initvalu_34));
xsss = 1 / (1 + exp(-(d_initvalu_39 - 1.5) / 16.7));
tauxs = 1
/ (7.19e-5 * (d_initvalu_39 + 30) / (1 - exp(-0.148 * (d_initvalu_39 + 30)))
+ 1.31e-4 * (d_initvalu_39 + 30) / (exp(0.0687 * (d_initvalu_39 + 30)) - 1));
d_finavalu[offset_13] = (xsss - d_initvalu_13) / tauxs;
I_ks_junc = Fjunc * gks_junc * pow(d_initvalu_12, 2) * (d_initvalu_39 - eks);
I_ks_sl = Fsl * gks_sl * pow(d_initvalu_13, 2) * (d_initvalu_39 - eks);
I_ks = I_ks_junc + I_ks_sl;
// I_kp: Plateau K current
kp_kp = 1 / (1 + exp(7.488 - d_initvalu_39 / 5.98));
I_kp_junc = Fjunc * gkp * kp_kp * (d_initvalu_39 - ek);
I_kp_sl = Fsl * gkp * kp_kp * (d_initvalu_39 - ek);
I_kp = I_kp_junc + I_kp_sl;
// I_to: Transient Outward K Current (slow and fast components)
xtoss = 1 / (1 + exp(-(d_initvalu_39 + 3.0) / 15));
ytoss = 1 / (1 + exp((d_initvalu_39 + 33.5) / 10));
rtoss = 1 / (1 + exp((d_initvalu_39 + 33.5) / 10));
tauxtos = 9 / (1 + exp((d_initvalu_39 + 3.0) / 15)) + 0.5;
tauytos = 3e3 / (1 + exp((d_initvalu_39 + 60.0) / 10)) + 30;
taurtos = 2800 / (1 + exp((d_initvalu_39 + 60.0) / 10)) + 220;
d_finavalu[offset_8] = (xtoss - d_initvalu_8) / tauxtos;
d_finavalu[offset_9] = (ytoss - d_initvalu_9) / tauytos;
d_finavalu[offset_40] = (rtoss - d_initvalu_40) / taurtos;
I_tos = GtoSlow * d_initvalu_8 * (d_initvalu_9 + 0.5 * d_initvalu_40) * (d_initvalu_39 - ek); // [uA/uF]
//
tauxtof = 3.5 * exp(-d_initvalu_39 * d_initvalu_39 / 30 / 30) + 1.5;
tauytof = 20.0 / (1 + exp((d_initvalu_39 + 33.5) / 10)) + 20.0;
d_finavalu[offset_10] = (xtoss - d_initvalu_10) / tauxtof;
d_finavalu[offset_11] = (ytoss - d_initvalu_11) / tauytof;
I_tof = GtoFast * d_initvalu_10 * d_initvalu_11 * (d_initvalu_39 - ek);
I_to = I_tos + I_tof;
// I_ki: Time-Independent K Current
aki = 1.02 / (1 + exp(0.2385 * (d_initvalu_39 - ek - 59.215)));
bki = (0.49124 * exp(0.08032 * (d_initvalu_39 + 5.476 - ek))
+ exp(0.06175 * (d_initvalu_39 - ek - 594.31)))
/ (1 + exp(-0.5143 * (d_initvalu_39 - ek + 4.753)));
kiss = aki / (aki + bki);
I_ki = 0.9 * sqrt(Ko / 5.4) * kiss * (d_initvalu_39 - ek);
// I_ClCa: Ca-activated Cl Current, I_Clbk: background Cl Current
I_ClCa_junc = Fjunc * GClCa / (1 + KdClCa / d_initvalu_36) * (d_initvalu_39 - ecl);
I_ClCa_sl = Fsl * GClCa / (1 + KdClCa / d_initvalu_37) * (d_initvalu_39 - ecl);
I_ClCa = I_ClCa_junc + I_ClCa_sl;
I_Clbk = GClB * (d_initvalu_39 - ecl);
// I_Ca: L-type Calcium Current
dss = 1 / (1 + exp(-(d_initvalu_39 + 14.5) / 6.0));
taud = dss * (1 - exp(-(d_initvalu_39 + 14.5) / 6.0)) / (0.035 * (d_initvalu_39 + 14.5));
fss = 1 / (1 + exp((d_initvalu_39 + 35.06) / 3.6)) + 0.6 / (1 + exp((50 - d_initvalu_39) / 20));
tauf = 1 / (0.0197 * exp(-pow(0.0337 * (d_initvalu_39 + 14.5), 2)) + 0.02);
d_finavalu[offset_4] = (dss - d_initvalu_4) / taud;
d_finavalu[offset_5] = (fss - d_initvalu_5) / tauf;
d_finavalu[offset_6] = 1.7 * d_initvalu_36 * (1 - d_initvalu_6) - 11.9e-3 * d_initvalu_6; // fCa_junc
d_finavalu[offset_7] = 1.7 * d_initvalu_37 * (1 - d_initvalu_7) - 11.9e-3 * d_initvalu_7; // fCa_sl
//
ibarca_j = pCa * 4 * (d_initvalu_39 * Frdy * FoRT)
* (0.341 * d_initvalu_36 * exp(2 * d_initvalu_39 * FoRT) - 0.341 * Cao)
/ (exp(2 * d_initvalu_39 * FoRT) - 1);
ibarca_sl = pCa * 4 * (d_initvalu_39 * Frdy * FoRT)
* (0.341 * d_initvalu_37 * exp(2 * d_initvalu_39 * FoRT) - 0.341 * Cao)
/ (exp(2 * d_initvalu_39 * FoRT) - 1);
ibark = pK * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_35 * exp(d_initvalu_39 * FoRT) - 0.75 * Ko)
/ (exp(d_initvalu_39 * FoRT) - 1);
ibarna_j = pNa * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_32 * exp(d_initvalu_39 * FoRT) - 0.75 * Nao)
/ (exp(d_initvalu_39 * FoRT) - 1);
ibarna_sl = pNa * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_33 * exp(d_initvalu_39 * FoRT) - 0.75 * Nao)
/ (exp(d_initvalu_39 * FoRT) - 1);
I_Ca_junc = (Fjunc_CaL * ibarca_j * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_6)
* pow(Q10CaL, Qpow)) * 0.45;
I_Ca_sl = (Fsl_CaL * ibarca_sl * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_7)
* pow(Q10CaL, Qpow)) * 0.45;
I_Ca = I_Ca_junc + I_Ca_sl;
d_finavalu[offset_43] = -I_Ca * Cmem / (Vmyo * 2 * Frdy) * 1e3;
I_CaK = (ibark * d_initvalu_4 * d_initvalu_5
* (Fjunc_CaL * (1 - d_initvalu_6) + Fsl_CaL * (1 - d_initvalu_7)) * pow(Q10CaL, Qpow)) * 0.45;
I_CaNa_junc = (Fjunc_CaL * ibarna_j * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_6)
* pow(Q10CaL, Qpow)) * 0.45;
I_CaNa_sl = (Fsl_CaL * ibarna_sl * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_7)
* pow(Q10CaL, Qpow)) * 0.45;
// I_CaNa = I_CaNa_junc+I_CaNa_sl;
// I_Catot = I_Ca+I_CaK+I_CaNa;
// I_ncx: Na/Ca Exchanger flux
Ka_junc = 1 / (1 + pow((Kdact / d_initvalu_36), 3));
Ka_sl = 1 / (1 + pow((Kdact / d_initvalu_37), 3));
s1_junc = exp(nu * d_initvalu_39 * FoRT) * pow(d_initvalu_32, 3) * Cao;
s1_sl = exp(nu * d_initvalu_39 * FoRT) * pow(d_initvalu_33, 3) * Cao;
s2_junc = exp((nu - 1) * d_initvalu_39 * FoRT) * pow(Nao, 3) * d_initvalu_36;
s3_junc = (KmCai * pow(Nao, 3) * (1 + pow((d_initvalu_32 / KmNai), 3))
+ pow(KmNao, 3) * d_initvalu_36 + pow(KmNai, 3) * Cao * (1 + d_initvalu_36 / KmCai)
+ KmCao * pow(d_initvalu_32, 3) + pow(d_initvalu_32, 3) * Cao + pow(Nao, 3) * d_initvalu_36)
* (1 + ksat * exp((nu - 1) * d_initvalu_39 * FoRT));
s2_sl = exp((nu - 1) * d_initvalu_39 * FoRT) * pow(Nao, 3) * d_initvalu_37;
s3_sl = (KmCai * pow(Nao, 3) * (1 + pow((d_initvalu_33 / KmNai), 3))
+ pow(KmNao, 3) * d_initvalu_37 + pow(KmNai, 3) * Cao * (1 + d_initvalu_37 / KmCai)
+ KmCao * pow(d_initvalu_33, 3) + pow(d_initvalu_33, 3) * Cao + pow(Nao, 3) * d_initvalu_37)
* (1 + ksat * exp((nu - 1) * d_initvalu_39 * FoRT));
I_ncx_junc = Fjunc * IbarNCX * pow(Q10NCX, Qpow) * Ka_junc * (s1_junc - s2_junc) / s3_junc;
I_ncx_sl = Fsl * IbarNCX * pow(Q10NCX, Qpow) * Ka_sl * (s1_sl - s2_sl) / s3_sl;
I_ncx = I_ncx_junc + I_ncx_sl;
d_finavalu[offset_45] = 2 * I_ncx * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// I_pca: Sarcolemmal Ca Pump Current
I_pca_junc = Fjunc * pow(Q10SLCaP, Qpow) * IbarSLCaP * pow(d_initvalu_36, float(1.6))
/ (pow(KmPCa, float(1.6)) + pow(d_initvalu_36, float(1.6)));
I_pca_sl = Fsl * pow(Q10SLCaP, Qpow) * IbarSLCaP * pow(d_initvalu_37, float(1.6))
/ (pow(KmPCa, float(1.6)) + pow(d_initvalu_37, float(1.6)));
I_pca = I_pca_junc + I_pca_sl;
d_finavalu[offset_44] = -I_pca * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// I_cabk: Ca Background Current
I_cabk_junc = Fjunc * GCaB * (d_initvalu_39 - eca_junc);
I_cabk_sl = Fsl * GCaB * (d_initvalu_39 - eca_sl);
I_cabk = I_cabk_junc + I_cabk_sl;
d_finavalu[offset_46] = -I_cabk * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// SR fluxes: Calcium Release, SR Ca pump, SR Ca leak
MaxSR = 15;
MinSR = 1;
kCaSR = MaxSR - (MaxSR - MinSR) / (1 + pow(ec50SR / d_initvalu_31, float(2.5)));
koSRCa = koCa / kCaSR;
kiSRCa = kiCa * kCaSR;
RI = 1 - d_initvalu_14 - d_initvalu_15 - d_initvalu_16;
d_finavalu[offset_14] = (kim * RI - kiSRCa * d_initvalu_36 * d_initvalu_14)
- (koSRCa * pow(d_initvalu_36, 2) * d_initvalu_14 - kom * d_initvalu_15); // R
d_finavalu[offset_15] = (koSRCa * pow(d_initvalu_36, 2) * d_initvalu_14 - kom * d_initvalu_15)
- (kiSRCa * d_initvalu_36 * d_initvalu_15 - kim * d_initvalu_16); // O
d_finavalu[offset_16] = (kiSRCa * d_initvalu_36 * d_initvalu_15 - kim * d_initvalu_16)
- (kom * d_initvalu_16 - koSRCa * pow(d_initvalu_36, 2) * RI); // I
J_SRCarel = ks * d_initvalu_15 * (d_initvalu_31 - d_initvalu_36); // [mM/ms]
J_serca = pow(Q10SRCaP, Qpow) * Vmax_SRCaP
* (pow((d_initvalu_38 / Kmf), hillSRCaP) - pow((d_initvalu_31 / Kmr), hillSRCaP))
/ (1 + pow((d_initvalu_38 / Kmf), hillSRCaP) + pow((d_initvalu_31 / Kmr), hillSRCaP));
J_SRleak = 5.348e-6 * (d_initvalu_31 - d_initvalu_36); // [mM/ms]
// Sodium and Calcium Buffering
d_finavalu[offset_17] = kon_na * d_initvalu_32 * (Bmax_Naj - d_initvalu_17)
- koff_na * d_initvalu_17; // NaBj [mM/ms]
d_finavalu[offset_18] = kon_na * d_initvalu_33 * (Bmax_Nasl - d_initvalu_18)
- koff_na * d_initvalu_18; // NaBsl [mM/ms]
// Cytosolic Ca Buffers
d_finavalu[offset_19] = kon_tncl * d_initvalu_38 * (Bmax_TnClow - d_initvalu_19)
- koff_tncl * d_initvalu_19; // TnCL [mM/ms]
d_finavalu[offset_20] = kon_tnchca * d_initvalu_38
* (Bmax_TnChigh - d_initvalu_20 - d_initvalu_21) - koff_tnchca * d_initvalu_20; // TnCHc [mM/ms]
d_finavalu[offset_21] = kon_tnchmg * Mgi * (Bmax_TnChigh - d_initvalu_20 - d_initvalu_21)
- koff_tnchmg * d_initvalu_21; // TnCHm [mM/ms]
d_finavalu[offset_22] = 0; // CaM [mM/ms]
d_finavalu[offset_23] = kon_myoca * d_initvalu_38 * (Bmax_myosin - d_initvalu_23 - d_initvalu_24)
- koff_myoca * d_initvalu_23; // Myosin_ca [mM/ms]
d_finavalu[offset_24] = kon_myomg * Mgi * (Bmax_myosin - d_initvalu_23 - d_initvalu_24)
- koff_myomg * d_initvalu_24; // Myosin_mg [mM/ms]
d_finavalu[offset_25] = kon_sr * d_initvalu_38 * (Bmax_SR - d_initvalu_25)
- koff_sr * d_initvalu_25; // SRB [mM/ms]
J_CaB_cytosol = d_finavalu[offset_19] + d_finavalu[offset_20] + d_finavalu[offset_21]
+ d_finavalu[offset_22] + d_finavalu[offset_23] + d_finavalu[offset_24]
+ d_finavalu[offset_25];
// Junctional and SL Ca Buffers
d_finavalu[offset_26] = kon_sll * d_initvalu_36 * (Bmax_SLlowj - d_initvalu_26)
- koff_sll * d_initvalu_26; // SLLj [mM/ms]
d_finavalu[offset_27] = kon_sll * d_initvalu_37 * (Bmax_SLlowsl - d_initvalu_27)
- koff_sll * d_initvalu_27; // SLLsl [mM/ms]
d_finavalu[offset_28] = kon_slh * d_initvalu_36 * (Bmax_SLhighj - d_initvalu_28)
- koff_slh * d_initvalu_28; // SLHj [mM/ms]
d_finavalu[offset_29] = kon_slh * d_initvalu_37 * (Bmax_SLhighsl - d_initvalu_29)
- koff_slh * d_initvalu_29; // SLHsl [mM/ms]
J_CaB_junction = d_finavalu[offset_26] + d_finavalu[offset_28];
J_CaB_sl = d_finavalu[offset_27] + d_finavalu[offset_29];
// SR Ca Concentrations
d_finavalu[offset_30] = kon_csqn * d_initvalu_31 * (Bmax_Csqn - d_initvalu_30)
- koff_csqn * d_initvalu_30; // Csqn [mM/ms]
oneovervsr = 1 / Vsr;
d_finavalu[offset_31] = J_serca * Vmyo * oneovervsr - (J_SRleak * Vmyo * oneovervsr + J_SRCarel)
- d_finavalu[offset_30]; // Ca_sr [mM/ms] %Ratio 3 leak current
// Sodium Concentrations
I_Na_tot_junc = I_Na_junc + I_nabk_junc + 3 * I_ncx_junc + 3 * I_nak_junc + I_CaNa_junc;// [uA/uF]
I_Na_tot_sl = I_Na_sl + I_nabk_sl + 3 * I_ncx_sl + 3 * I_nak_sl + I_CaNa_sl; // [uA/uF]
d_finavalu[offset_32] = -I_Na_tot_junc * Cmem / (Vjunc * Frdy)
+ J_na_juncsl / Vjunc * (d_initvalu_33 - d_initvalu_32) - d_finavalu[offset_17];
oneovervsl = 1 / Vsl;
d_finavalu[offset_33] = -I_Na_tot_sl * Cmem * oneovervsl / Frdy
+ J_na_juncsl * oneovervsl * (d_initvalu_32 - d_initvalu_33)
+ J_na_slmyo * oneovervsl * (d_initvalu_34 - d_initvalu_33) - d_finavalu[offset_18];
d_finavalu[offset_34] = J_na_slmyo / Vmyo * (d_initvalu_33 - d_initvalu_34); // [mM/msec]
// Potassium Concentration
I_K_tot = I_to + I_kr + I_ks + I_ki - 2 * I_nak + I_CaK + I_kp; // [uA/uF]
d_finavalu[offset_35] = 0; // [mM/msec]
// Calcium Concentrations
I_Ca_tot_junc = I_Ca_junc + I_cabk_junc + I_pca_junc - 2 * I_ncx_junc; // [uA/uF]
I_Ca_tot_sl = I_Ca_sl + I_cabk_sl + I_pca_sl - 2 * I_ncx_sl; // [uA/uF]
d_finavalu[offset_36] = -I_Ca_tot_junc * Cmem / (Vjunc * 2 * Frdy)
+ J_ca_juncsl / Vjunc * (d_initvalu_37 - d_initvalu_36) - J_CaB_junction
+ (J_SRCarel) * Vsr / Vjunc + J_SRleak * Vmyo / Vjunc; // Ca_j
d_finavalu[offset_37] = -I_Ca_tot_sl * Cmem / (Vsl * 2 * Frdy)
+ J_ca_juncsl / Vsl * (d_initvalu_36 - d_initvalu_37)
+ J_ca_slmyo / Vsl * (d_initvalu_38 - d_initvalu_37) - J_CaB_sl; // Ca_sl
d_finavalu[offset_38] = -J_serca - J_CaB_cytosol
+ J_ca_slmyo / Vmyo * (d_initvalu_37 - d_initvalu_38);
// junc_sl=J_ca_juncsl/Vsl*(d_initvalu_36-d_initvalu_37);
// sl_junc=J_ca_juncsl/Vjunc*(d_initvalu_37-d_initvalu_36);
// sl_myo=J_ca_slmyo/Vsl*(d_initvalu_38-d_initvalu_37);
// myo_sl=J_ca_slmyo/Vmyo*(d_initvalu_37-d_initvalu_38);
// Simulation type
state = 1;
switch (state) {
case 0:
I_app = 0;
break;
case 1: // pace w/ current injection at cycleLength 'cycleLength'
if (fmod(timeinst, cycleLength) <= 5) {
I_app = 9.5;
} else {
I_app = 0.0;
}
break;
case 2:
V_hold = -55;
V_test = 0;
if (timeinst > 0.5 & timeinst < 200.5) {
V_clamp = V_test;
} else {
V_clamp = V_hold;
}
R_clamp = 0.04;
I_app = (V_clamp - d_initvalu_39) / R_clamp;
break;
}
// Membrane Potential
I_Na_tot = I_Na_tot_junc + I_Na_tot_sl; // [uA/uF]
I_Cl_tot = I_ClCa + I_Clbk; // [uA/uF]
I_Ca_tot = I_Ca_tot_junc + I_Ca_tot_sl;
I_tot = I_Na_tot + I_Cl_tot + I_Ca_tot + I_K_tot;
d_finavalu[offset_39] = -(I_tot - I_app);
// Set unused output values to 0 (MATLAB does it by default)
d_finavalu[offset_41] = 0;
d_finavalu[offset_42] = 0;
} | .file "tmpxft_0016c05c_00000000-6_kernel_ecc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10kernel_eccfPfS_iS_
.type _Z10kernel_eccfPfS_iS_, @function
_Z10kernel_eccfPfS_iS_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10kernel_eccfPfS_iS_, .-_Z10kernel_eccfPfS_iS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
//=====================================================================
// MAIN FUNCTION
//=====================================================================
__device__ void kernel_ecc(float timeinst, float* d_initvalu, float *d_finavalu, int valu_offset,
float* d_params) {
//=====================================================================
// VARIABLES
//=====================================================================
// input parameters
float cycleLength;
// variable references // GET VARIABLES FROM MEMORY AND SAVE LOCALLY !!!!!!!!!!!!!!!!!!
int offset_1;
int offset_2;
int offset_3;
int offset_4;
int offset_5;
int offset_6;
int offset_7;
int offset_8;
int offset_9;
int offset_10;
int offset_11;
int offset_12;
int offset_13;
int offset_14;
int offset_15;
int offset_16;
int offset_17;
int offset_18;
int offset_19;
int offset_20;
int offset_21;
int offset_22;
int offset_23;
int offset_24;
int offset_25;
int offset_26;
int offset_27;
int offset_28;
int offset_29;
int offset_30;
int offset_31;
int offset_32;
int offset_33;
int offset_34;
int offset_35;
int offset_36;
int offset_37;
int offset_38;
int offset_39;
int offset_40;
int offset_41;
int offset_42;
int offset_43;
int offset_44;
int offset_45;
int offset_46;
// stored input array
float d_initvalu_1;
float d_initvalu_2;
float d_initvalu_3;
float d_initvalu_4;
float d_initvalu_5;
float d_initvalu_6;
float d_initvalu_7;
float d_initvalu_8;
float d_initvalu_9;
float d_initvalu_10;
float d_initvalu_11;
float d_initvalu_12;
float d_initvalu_13;
float d_initvalu_14;
float d_initvalu_15;
float d_initvalu_16;
float d_initvalu_17;
float d_initvalu_18;
float d_initvalu_19;
float d_initvalu_20;
float d_initvalu_21;
// float d_initvalu_22;
float d_initvalu_23;
float d_initvalu_24;
float d_initvalu_25;
float d_initvalu_26;
float d_initvalu_27;
float d_initvalu_28;
float d_initvalu_29;
float d_initvalu_30;
float d_initvalu_31;
float d_initvalu_32;
float d_initvalu_33;
float d_initvalu_34;
float d_initvalu_35;
float d_initvalu_36;
float d_initvalu_37;
float d_initvalu_38;
float d_initvalu_39;
float d_initvalu_40;
// float d_initvalu_41;
// float d_initvalu_42;
// float d_initvalu_43;
// float d_initvalu_44;
// float d_initvalu_45;
// float d_initvalu_46;
// matlab constants undefined in c
float pi;
// Constants
float R; // [J/kmol*K]
float Frdy; // [C/mol]
float Temp; // [K] 310
float FoRT; //
float Cmem; // [F] membrane capacitance
float Qpow;
// Cell geometry
float cellLength; // cell length [um]
float cellRadius; // cell radius [um]
// float junctionLength; // junc length [um]
// float junctionRadius; // junc radius [um]
// float distSLcyto; // dist. SL to cytosol [um]
// float distJuncSL; // dist. junc to SL [um]
// float DcaJuncSL; // Dca junc to SL [cm^2/sec]
// float DcaSLcyto; // Dca SL to cyto [cm^2/sec]
// float DnaJuncSL; // Dna junc to SL [cm^2/sec]
// float DnaSLcyto; // Dna SL to cyto [cm^2/sec]
float Vcell; // [L]
float Vmyo;
float Vsr;
float Vsl;
float Vjunc;
// float SAjunc; // [um^2]
// float SAsl; // [um^2]
float J_ca_juncsl; // [L/msec]
float J_ca_slmyo; // [L/msec]
float J_na_juncsl; // [L/msec]
float J_na_slmyo; // [L/msec]
// Fractional currents in compartments
float Fjunc;
float Fsl;
float Fjunc_CaL;
float Fsl_CaL;
// Fixed ion concentrations
float Cli; // Intracellular Cl [mM]
float Clo; // Extracellular Cl [mM]
float Ko; // Extracellular K [mM]
float Nao; // Extracellular Na [mM]
float Cao; // Extracellular Ca [mM]
float Mgi; // Intracellular Mg [mM]
// Nernst Potentials
float ena_junc; // [mV]
float ena_sl; // [mV]
float ek; // [mV]
float eca_junc; // [mV]
float eca_sl; // [mV]
float ecl; // [mV]
// Na transport parameters
float GNa; // [mS/uF]
float GNaB; // [mS/uF]
float IbarNaK; // [uA/uF]
float KmNaip; // [mM]
float KmKo; // [mM]
// float Q10NaK;
// float Q10KmNai;
// K current parameters
float pNaK;
float GtoSlow; // [mS/uF]
float GtoFast; // [mS/uF]
float gkp;
// Cl current parameters
float GClCa; // [mS/uF]
float GClB; // [mS/uF]
float KdClCa; // [mM] // [mM]
// I_Ca parameters
float pNa; // [cm/sec]
float pCa; // [cm/sec]
float pK; // [cm/sec]
// float KmCa; // [mM]
float Q10CaL;
// Ca transport parameters
float IbarNCX; // [uA/uF]
float KmCai; // [mM]
float KmCao; // [mM]
float KmNai; // [mM]
float KmNao; // [mM]
float ksat; // [none]
float nu; // [none]
float Kdact; // [mM]
float Q10NCX; // [none]
float IbarSLCaP; // [uA/uF]
float KmPCa; // [mM]
float GCaB; // [uA/uF]
float Q10SLCaP; // [none] // [none]
// SR flux parameters
float Q10SRCaP; // [none]
float Vmax_SRCaP; // [mM/msec] (mmol/L cytosol/msec)
float Kmf; // [mM]
float Kmr; // [mM]L cytosol
float hillSRCaP; // [mM]
float ks; // [1/ms]
float koCa; // [mM^-2 1/ms]
float kom; // [1/ms]
float kiCa; // [1/mM/ms]
float kim; // [1/ms]
float ec50SR; // [mM]
// Buffering parameters
float Bmax_Naj; // [mM]
float Bmax_Nasl; // [mM]
float koff_na; // [1/ms]
float kon_na; // [1/mM/ms]
float Bmax_TnClow; // [mM], TnC low affinity
float koff_tncl; // [1/ms]
float kon_tncl; // [1/mM/ms]
float Bmax_TnChigh; // [mM], TnC high affinity
float koff_tnchca; // [1/ms]
float kon_tnchca; // [1/mM/ms]
float koff_tnchmg; // [1/ms]
float kon_tnchmg; // [1/mM/ms]
// float Bmax_CaM; // [mM], CaM buffering
// float koff_cam; // [1/ms]
// float kon_cam; // [1/mM/ms]
float Bmax_myosin; // [mM], Myosin buffering
float koff_myoca; // [1/ms]
float kon_myoca; // [1/mM/ms]
float koff_myomg; // [1/ms]
float kon_myomg; // [1/mM/ms]
float Bmax_SR; // [mM]
float koff_sr; // [1/ms]
float kon_sr; // [1/mM/ms]
float Bmax_SLlowsl; // [mM], SL buffering
float Bmax_SLlowj; // [mM]
float koff_sll; // [1/ms]
float kon_sll; // [1/mM/ms]
float Bmax_SLhighsl; // [mM]
float Bmax_SLhighj; // [mM]
float koff_slh; // [1/ms]
float kon_slh; // [1/mM/ms]
float Bmax_Csqn; // 140e-3*Vmyo/Vsr; [mM]
float koff_csqn; // [1/ms]
float kon_csqn; // [1/mM/ms]
// I_Na: Fast Na Current
float am;
float bm;
float ah;
float bh;
float aj;
float bj;
float I_Na_junc;
float I_Na_sl;
// float I_Na;
// I_nabk: Na Background Current
float I_nabk_junc;
float I_nabk_sl;
// float I_nabk;
// I_nak: Na/K Pump Current
float sigma;
float fnak;
float I_nak_junc;
float I_nak_sl;
float I_nak;
// I_kr: Rapidly Activating K Current
float gkr;
float xrss;
float tauxr;
float rkr;
float I_kr;
// I_ks: Slowly Activating K Current
float pcaks_junc;
float pcaks_sl;
float gks_junc;
float gks_sl;
float eks;
float xsss;
float tauxs;
float I_ks_junc;
float I_ks_sl;
float I_ks;
// I_kp: Plateau K current
float kp_kp;
float I_kp_junc;
float I_kp_sl;
float I_kp;
// I_to: Transient Outward K Current (slow and fast components)
float xtoss;
float ytoss;
float rtoss;
float tauxtos;
float tauytos;
float taurtos;
float I_tos;
//
float tauxtof;
float tauytof;
float I_tof;
float I_to;
// I_ki: Time-Independent K Current
float aki;
float bki;
float kiss;
float I_ki;
// I_ClCa: Ca-activated Cl Current, I_Clbk: background Cl Current
float I_ClCa_junc;
float I_ClCa_sl;
float I_ClCa;
float I_Clbk;
// I_Ca: L-type Calcium Current
float dss;
float taud;
float fss;
float tauf;
//
float ibarca_j;
float ibarca_sl;
float ibark;
float ibarna_j;
float ibarna_sl;
float I_Ca_junc;
float I_Ca_sl;
float I_Ca;
float I_CaK;
float I_CaNa_junc;
float I_CaNa_sl;
// float I_CaNa;
// float I_Catot;
// I_ncx: Na/Ca Exchanger flux
float Ka_junc;
float Ka_sl;
float s1_junc;
float s1_sl;
float s2_junc;
float s3_junc;
float s2_sl;
float s3_sl;
float I_ncx_junc;
float I_ncx_sl;
float I_ncx;
// I_pca: Sarcolemmal Ca Pump Current
float I_pca_junc;
float I_pca_sl;
float I_pca;
// I_cabk: Ca Background Current
float I_cabk_junc;
float I_cabk_sl;
float I_cabk;
// SR fluxes: Calcium Release, SR Ca pump, SR Ca leak
float MaxSR;
float MinSR;
float kCaSR;
float koSRCa;
float kiSRCa;
float RI;
float J_SRCarel; // [mM/ms]
float J_serca;
float J_SRleak; // [mM/ms]
// Cytosolic Ca Buffers
float J_CaB_cytosol;
// Junctional and SL Ca Buffers
float J_CaB_junction;
float J_CaB_sl;
// SR Ca Concentrations
float oneovervsr;
// Sodium Concentrations
float I_Na_tot_junc; // [uA/uF]
float I_Na_tot_sl; // [uA/uF]
float oneovervsl;
// Potassium Concentration
float I_K_tot;
// Calcium Concentrations
float I_Ca_tot_junc; // [uA/uF]
float I_Ca_tot_sl; // [uA/uF]
// float junc_sl;
// float sl_junc;
// float sl_myo;
// float myo_sl;
// Simulation type
int state; // 0-none; 1-pace; 2-vclamp
float I_app;
float V_hold;
float V_test;
float V_clamp;
float R_clamp;
// Membrane Potential
float I_Na_tot; // [uA/uF]
float I_Cl_tot; // [uA/uF]
float I_Ca_tot;
float I_tot;
//=====================================================================
// EXECUTION
//=====================================================================
// input parameters
cycleLength = d_params[15];
// variable references
offset_1 = valu_offset;
offset_2 = valu_offset + 1;
offset_3 = valu_offset + 2;
offset_4 = valu_offset + 3;
offset_5 = valu_offset + 4;
offset_6 = valu_offset + 5;
offset_7 = valu_offset + 6;
offset_8 = valu_offset + 7;
offset_9 = valu_offset + 8;
offset_10 = valu_offset + 9;
offset_11 = valu_offset + 10;
offset_12 = valu_offset + 11;
offset_13 = valu_offset + 12;
offset_14 = valu_offset + 13;
offset_15 = valu_offset + 14;
offset_16 = valu_offset + 15;
offset_17 = valu_offset + 16;
offset_18 = valu_offset + 17;
offset_19 = valu_offset + 18;
offset_20 = valu_offset + 19;
offset_21 = valu_offset + 20;
offset_22 = valu_offset + 21;
offset_23 = valu_offset + 22;
offset_24 = valu_offset + 23;
offset_25 = valu_offset + 24;
offset_26 = valu_offset + 25;
offset_27 = valu_offset + 26;
offset_28 = valu_offset + 27;
offset_29 = valu_offset + 28;
offset_30 = valu_offset + 29;
offset_31 = valu_offset + 30;
offset_32 = valu_offset + 31;
offset_33 = valu_offset + 32;
offset_34 = valu_offset + 33;
offset_35 = valu_offset + 34;
offset_36 = valu_offset + 35;
offset_37 = valu_offset + 36;
offset_38 = valu_offset + 37;
offset_39 = valu_offset + 38;
offset_40 = valu_offset + 39;
offset_41 = valu_offset + 40;
offset_42 = valu_offset + 41;
offset_43 = valu_offset + 42;
offset_44 = valu_offset + 43;
offset_45 = valu_offset + 44;
offset_46 = valu_offset + 45;
// stored input array
d_initvalu_1 = d_initvalu[offset_1];
d_initvalu_2 = d_initvalu[offset_2];
d_initvalu_3 = d_initvalu[offset_3];
d_initvalu_4 = d_initvalu[offset_4];
d_initvalu_5 = d_initvalu[offset_5];
d_initvalu_6 = d_initvalu[offset_6];
d_initvalu_7 = d_initvalu[offset_7];
d_initvalu_8 = d_initvalu[offset_8];
d_initvalu_9 = d_initvalu[offset_9];
d_initvalu_10 = d_initvalu[offset_10];
d_initvalu_11 = d_initvalu[offset_11];
d_initvalu_12 = d_initvalu[offset_12];
d_initvalu_13 = d_initvalu[offset_13];
d_initvalu_14 = d_initvalu[offset_14];
d_initvalu_15 = d_initvalu[offset_15];
d_initvalu_16 = d_initvalu[offset_16];
d_initvalu_17 = d_initvalu[offset_17];
d_initvalu_18 = d_initvalu[offset_18];
d_initvalu_19 = d_initvalu[offset_19];
d_initvalu_20 = d_initvalu[offset_20];
d_initvalu_21 = d_initvalu[offset_21];
// d_initvalu_22 = d_initvalu[offset_22];
d_initvalu_23 = d_initvalu[offset_23];
d_initvalu_24 = d_initvalu[offset_24];
d_initvalu_25 = d_initvalu[offset_25];
d_initvalu_26 = d_initvalu[offset_26];
d_initvalu_27 = d_initvalu[offset_27];
d_initvalu_28 = d_initvalu[offset_28];
d_initvalu_29 = d_initvalu[offset_29];
d_initvalu_30 = d_initvalu[offset_30];
d_initvalu_31 = d_initvalu[offset_31];
d_initvalu_32 = d_initvalu[offset_32];
d_initvalu_33 = d_initvalu[offset_33];
d_initvalu_34 = d_initvalu[offset_34];
d_initvalu_35 = d_initvalu[offset_35];
d_initvalu_36 = d_initvalu[offset_36];
d_initvalu_37 = d_initvalu[offset_37];
d_initvalu_38 = d_initvalu[offset_38];
d_initvalu_39 = d_initvalu[offset_39];
d_initvalu_40 = d_initvalu[offset_40];
// d_initvalu_41 = d_initvalu[offset_41];
// d_initvalu_42 = d_initvalu[offset_42];
// d_initvalu_43 = d_initvalu[offset_43];
// d_initvalu_44 = d_initvalu[offset_44];
// d_initvalu_45 = d_initvalu[offset_45];
// d_initvalu_46 = d_initvalu[offset_46];
// matlab constants undefined in c
pi = 3.1416;
// Constants
R = 8314; // [J/kmol*K]
Frdy = 96485; // [C/mol]
Temp = 310; // [K] 310
FoRT = Frdy / R / Temp; //
Cmem = 1.3810e-10; // [F] membrane capacitance
Qpow = (Temp - 310) / 10;
// Cell geometry
cellLength = 100; // cell length [um]
cellRadius = 10.25; // cell radius [um]
// junctionLength = 160e-3; // junc length [um]
// junctionRadius = 15e-3; // junc radius [um]
// distSLcyto = 0.45; // dist. SL to cytosol [um]
// distJuncSL = 0.5; // dist. junc to SL [um]
// DcaJuncSL = 1.64e-6; // Dca junc to SL [cm^2/sec]
// DcaSLcyto = 1.22e-6; // Dca SL to cyto [cm^2/sec]
// DnaJuncSL = 1.09e-5; // Dna junc to SL [cm^2/sec]
// DnaSLcyto = 1.79e-5; // Dna SL to cyto [cm^2/sec]
Vcell = pi * pow(cellRadius, 2) * cellLength * 1e-15; // [L]
Vmyo = 0.65 * Vcell;
Vsr = 0.035 * Vcell;
Vsl = 0.02 * Vcell;
Vjunc = 0.0539 * 0.01 * Vcell;
// SAjunc = 20150*pi*2*junctionLength*junctionRadius; // [um^2]
// SAsl = pi*2*cellRadius*cellLength; // [um^2]
J_ca_juncsl = 1 / 1.2134e12; // [L/msec]
J_ca_slmyo = 1 / 2.68510e11; // [L/msec]
J_na_juncsl = 1 / (1.6382e12 / 3 * 100); // [L/msec]
J_na_slmyo = 1 / (1.8308e10 / 3 * 100); // [L/msec]
// Fractional currents in compartments
Fjunc = 0.11;
Fsl = 1 - Fjunc;
Fjunc_CaL = 0.9;
Fsl_CaL = 1 - Fjunc_CaL;
// Fixed ion concentrations
Cli = 15; // Intracellular Cl [mM]
Clo = 150; // Extracellular Cl [mM]
Ko = 5.4; // Extracellular K [mM]
Nao = 140; // Extracellular Na [mM]
Cao = 1.8; // Extracellular Ca [mM]
Mgi = 1; // Intracellular Mg [mM]
// Nernst Potentials
ena_junc = (1 / FoRT) * log(Nao / d_initvalu_32); // [mV]
ena_sl = (1 / FoRT) * log(Nao / d_initvalu_33); // [mV]
ek = (1 / FoRT) * log(Ko / d_initvalu_35); // [mV]
eca_junc = (1 / FoRT / 2) * log(Cao / d_initvalu_36); // [mV]
eca_sl = (1 / FoRT / 2) * log(Cao / d_initvalu_37); // [mV]
ecl = (1 / FoRT) * log(Cli / Clo); // [mV]
// Na transport parameters
GNa = 16.0; // [mS/uF]
GNaB = 0.297e-3; // [mS/uF]
IbarNaK = 1.90719; // [uA/uF]
KmNaip = 11; // [mM]
KmKo = 1.5; // [mM]
// Q10NaK = 1.63;
// Q10KmNai = 1.39;
// K current parameters
pNaK = 0.01833;
GtoSlow = 0.06; // [mS/uF]
GtoFast = 0.02; // [mS/uF]
gkp = 0.001;
// Cl current parameters
GClCa = 0.109625; // [mS/uF]
GClB = 9e-3; // [mS/uF]
KdClCa = 100e-3; // [mM]
// I_Ca parameters
pNa = 1.5e-8; // [cm/sec]
pCa = 5.4e-4; // [cm/sec]
pK = 2.7e-7; // [cm/sec]
// KmCa = 0.6e-3; // [mM]
Q10CaL = 1.8;
// Ca transport parameters
IbarNCX = 9.0; // [uA/uF]
KmCai = 3.59e-3; // [mM]
KmCao = 1.3; // [mM]
KmNai = 12.29; // [mM]
KmNao = 87.5; // [mM]
ksat = 0.27; // [none]
nu = 0.35; // [none]
Kdact = 0.256e-3; // [mM]
Q10NCX = 1.57; // [none]
IbarSLCaP = 0.0673; // [uA/uF]
KmPCa = 0.5e-3; // [mM]
GCaB = 2.513e-4; // [uA/uF]
Q10SLCaP = 2.35; // [none]
// SR flux parameters
Q10SRCaP = 2.6; // [none]
Vmax_SRCaP = 2.86e-4; // [mM/msec] (mmol/L cytosol/msec)
Kmf = 0.246e-3; // [mM]
Kmr = 1.7; // [mM]L cytosol
hillSRCaP = 1.787; // [mM]
ks = 25; // [1/ms]
koCa = 10; // [mM^-2 1/ms]
kom = 0.06; // [1/ms]
kiCa = 0.5; // [1/mM/ms]
kim = 0.005; // [1/ms]
ec50SR = 0.45; // [mM]
// Buffering parameters
Bmax_Naj = 7.561; // [mM]
Bmax_Nasl = 1.65; // [mM]
koff_na = 1e-3; // [1/ms]
kon_na = 0.1e-3; // [1/mM/ms]
Bmax_TnClow = 70e-3; // [mM], TnC low affinity
koff_tncl = 19.6e-3; // [1/ms]
kon_tncl = 32.7; // [1/mM/ms]
Bmax_TnChigh = 140e-3; // [mM], TnC high affinity
koff_tnchca = 0.032e-3; // [1/ms]
kon_tnchca = 2.37; // [1/mM/ms]
koff_tnchmg = 3.33e-3; // [1/ms]
kon_tnchmg = 3e-3; // [1/mM/ms]
// Bmax_CaM = 24e-3; // [mM], CaM buffering
// koff_cam = 238e-3; // [1/ms]
// kon_cam = 34; // [1/mM/ms]
Bmax_myosin = 140e-3; // [mM], Myosin buffering
koff_myoca = 0.46e-3; // [1/ms]
kon_myoca = 13.8; // [1/mM/ms]
koff_myomg = 0.057e-3; // [1/ms]
kon_myomg = 0.0157; // [1/mM/ms]
Bmax_SR = 19 * 0.9e-3; // [mM]
koff_sr = 60e-3; // [1/ms]
kon_sr = 100; // [1/mM/ms]
Bmax_SLlowsl = 37.38e-3 * Vmyo / Vsl; // [mM], SL buffering
Bmax_SLlowj = 4.62e-3 * Vmyo / Vjunc * 0.1; // [mM]
koff_sll = 1300e-3; // [1/ms]
kon_sll = 100; // [1/mM/ms]
Bmax_SLhighsl = 13.35e-3 * Vmyo / Vsl; // [mM]
Bmax_SLhighj = 1.65e-3 * Vmyo / Vjunc * 0.1; // [mM]
koff_slh = 30e-3; // [1/ms]
kon_slh = 100; // [1/mM/ms]
Bmax_Csqn = 2.7; // 140e-3*Vmyo/Vsr; [mM]
koff_csqn = 65; // [1/ms]
kon_csqn = 100; // [1/mM/ms]
// I_Na: Fast Na Current
am = 0.32 * (d_initvalu_39 + 47.13) / (1 - exp(-0.1 * (d_initvalu_39 + 47.13)));
bm = 0.08 * exp(-d_initvalu_39 / 11);
if (d_initvalu_39 >= -40) {
ah = 0;
aj = 0;
bh = 1 / (0.13 * (1 + exp(-(d_initvalu_39 + 10.66) / 11.1)));
bj = 0.3 * exp(-2.535e-7 * d_initvalu_39) / (1 + exp(-0.1 * (d_initvalu_39 + 32)));
} else {
ah = 0.135 * exp((80 + d_initvalu_39) / -6.8);
bh = 3.56 * exp(0.079 * d_initvalu_39) + 3.1e5 * exp(0.35 * d_initvalu_39);
aj = (-127140 * exp(0.2444 * d_initvalu_39) - 3.474e-5 * exp(-0.04391 * d_initvalu_39))
* (d_initvalu_39 + 37.78) / (1 + exp(0.311 * (d_initvalu_39 + 79.23)));
bj = 0.1212 * exp(-0.01052 * d_initvalu_39) / (1 + exp(-0.1378 * (d_initvalu_39 + 40.14)));
}
d_finavalu[offset_1] = am * (1 - d_initvalu_1) - bm * d_initvalu_1;
d_finavalu[offset_2] = ah * (1 - d_initvalu_2) - bh * d_initvalu_2;
d_finavalu[offset_3] = aj * (1 - d_initvalu_3) - bj * d_initvalu_3;
I_Na_junc = Fjunc * GNa * pow(d_initvalu_1, 3) * d_initvalu_2 * d_initvalu_3
* (d_initvalu_39 - ena_junc);
I_Na_sl = Fsl * GNa * pow(d_initvalu_1, 3) * d_initvalu_2 * d_initvalu_3
* (d_initvalu_39 - ena_sl);
// I_Na = I_Na_junc+I_Na_sl;
// I_nabk: Na Background Current
I_nabk_junc = Fjunc * GNaB * (d_initvalu_39 - ena_junc);
I_nabk_sl = Fsl * GNaB * (d_initvalu_39 - ena_sl);
// I_nabk = I_nabk_junc+I_nabk_sl;
// I_nak: Na/K Pump Current
sigma = (exp(Nao / 67.3) - 1) / 7;
fnak =
1
/ (1 + 0.1245 * exp(-0.1 * d_initvalu_39 * FoRT)
+ 0.0365 * sigma * exp(-d_initvalu_39 * FoRT));
I_nak_junc = Fjunc * IbarNaK * fnak * Ko / (1 + pow((KmNaip / d_initvalu_32), 4)) / (Ko + KmKo);
I_nak_sl = Fsl * IbarNaK * fnak * Ko / (1 + pow((KmNaip / d_initvalu_33), 4)) / (Ko + KmKo);
I_nak = I_nak_junc + I_nak_sl;
// I_kr: Rapidly Activating K Current
gkr = 0.03 * sqrt(Ko / 5.4);
xrss = 1 / (1 + exp(-(d_initvalu_39 + 50) / 7.5));
tauxr = 1
/ (0.00138 * (d_initvalu_39 + 7) / (1 - exp(-0.123 * (d_initvalu_39 + 7)))
+ 6.1e-4 * (d_initvalu_39 + 10) / (exp(0.145 * (d_initvalu_39 + 10)) - 1));
d_finavalu[offset_12] = (xrss - d_initvalu_12) / tauxr;
rkr = 1 / (1 + exp((d_initvalu_39 + 33) / 22.4));
I_kr = gkr * d_initvalu_12 * rkr * (d_initvalu_39 - ek);
// I_ks: Slowly Activating K Current
pcaks_junc = -log10(d_initvalu_36) + 3.0;
pcaks_sl = -log10(d_initvalu_37) + 3.0;
gks_junc = 0.07 * (0.057 + 0.19 / (1 + exp((-7.2 + pcaks_junc) / 0.6)));
gks_sl = 0.07 * (0.057 + 0.19 / (1 + exp((-7.2 + pcaks_sl) / 0.6)));
eks = (1 / FoRT) * log((Ko + pNaK * Nao) / (d_initvalu_35 + pNaK * d_initvalu_34));
xsss = 1 / (1 + exp(-(d_initvalu_39 - 1.5) / 16.7));
tauxs = 1
/ (7.19e-5 * (d_initvalu_39 + 30) / (1 - exp(-0.148 * (d_initvalu_39 + 30)))
+ 1.31e-4 * (d_initvalu_39 + 30) / (exp(0.0687 * (d_initvalu_39 + 30)) - 1));
d_finavalu[offset_13] = (xsss - d_initvalu_13) / tauxs;
I_ks_junc = Fjunc * gks_junc * pow(d_initvalu_12, 2) * (d_initvalu_39 - eks);
I_ks_sl = Fsl * gks_sl * pow(d_initvalu_13, 2) * (d_initvalu_39 - eks);
I_ks = I_ks_junc + I_ks_sl;
// I_kp: Plateau K current
kp_kp = 1 / (1 + exp(7.488 - d_initvalu_39 / 5.98));
I_kp_junc = Fjunc * gkp * kp_kp * (d_initvalu_39 - ek);
I_kp_sl = Fsl * gkp * kp_kp * (d_initvalu_39 - ek);
I_kp = I_kp_junc + I_kp_sl;
// I_to: Transient Outward K Current (slow and fast components)
xtoss = 1 / (1 + exp(-(d_initvalu_39 + 3.0) / 15));
ytoss = 1 / (1 + exp((d_initvalu_39 + 33.5) / 10));
rtoss = 1 / (1 + exp((d_initvalu_39 + 33.5) / 10));
tauxtos = 9 / (1 + exp((d_initvalu_39 + 3.0) / 15)) + 0.5;
tauytos = 3e3 / (1 + exp((d_initvalu_39 + 60.0) / 10)) + 30;
taurtos = 2800 / (1 + exp((d_initvalu_39 + 60.0) / 10)) + 220;
d_finavalu[offset_8] = (xtoss - d_initvalu_8) / tauxtos;
d_finavalu[offset_9] = (ytoss - d_initvalu_9) / tauytos;
d_finavalu[offset_40] = (rtoss - d_initvalu_40) / taurtos;
I_tos = GtoSlow * d_initvalu_8 * (d_initvalu_9 + 0.5 * d_initvalu_40) * (d_initvalu_39 - ek); // [uA/uF]
//
tauxtof = 3.5 * exp(-d_initvalu_39 * d_initvalu_39 / 30 / 30) + 1.5;
tauytof = 20.0 / (1 + exp((d_initvalu_39 + 33.5) / 10)) + 20.0;
d_finavalu[offset_10] = (xtoss - d_initvalu_10) / tauxtof;
d_finavalu[offset_11] = (ytoss - d_initvalu_11) / tauytof;
I_tof = GtoFast * d_initvalu_10 * d_initvalu_11 * (d_initvalu_39 - ek);
I_to = I_tos + I_tof;
// I_ki: Time-Independent K Current
aki = 1.02 / (1 + exp(0.2385 * (d_initvalu_39 - ek - 59.215)));
bki = (0.49124 * exp(0.08032 * (d_initvalu_39 + 5.476 - ek))
+ exp(0.06175 * (d_initvalu_39 - ek - 594.31)))
/ (1 + exp(-0.5143 * (d_initvalu_39 - ek + 4.753)));
kiss = aki / (aki + bki);
I_ki = 0.9 * sqrt(Ko / 5.4) * kiss * (d_initvalu_39 - ek);
// I_ClCa: Ca-activated Cl Current, I_Clbk: background Cl Current
I_ClCa_junc = Fjunc * GClCa / (1 + KdClCa / d_initvalu_36) * (d_initvalu_39 - ecl);
I_ClCa_sl = Fsl * GClCa / (1 + KdClCa / d_initvalu_37) * (d_initvalu_39 - ecl);
I_ClCa = I_ClCa_junc + I_ClCa_sl;
I_Clbk = GClB * (d_initvalu_39 - ecl);
// I_Ca: L-type Calcium Current
dss = 1 / (1 + exp(-(d_initvalu_39 + 14.5) / 6.0));
taud = dss * (1 - exp(-(d_initvalu_39 + 14.5) / 6.0)) / (0.035 * (d_initvalu_39 + 14.5));
fss = 1 / (1 + exp((d_initvalu_39 + 35.06) / 3.6)) + 0.6 / (1 + exp((50 - d_initvalu_39) / 20));
tauf = 1 / (0.0197 * exp(-pow(0.0337 * (d_initvalu_39 + 14.5), 2)) + 0.02);
d_finavalu[offset_4] = (dss - d_initvalu_4) / taud;
d_finavalu[offset_5] = (fss - d_initvalu_5) / tauf;
d_finavalu[offset_6] = 1.7 * d_initvalu_36 * (1 - d_initvalu_6) - 11.9e-3 * d_initvalu_6; // fCa_junc
d_finavalu[offset_7] = 1.7 * d_initvalu_37 * (1 - d_initvalu_7) - 11.9e-3 * d_initvalu_7; // fCa_sl
//
ibarca_j = pCa * 4 * (d_initvalu_39 * Frdy * FoRT)
* (0.341 * d_initvalu_36 * exp(2 * d_initvalu_39 * FoRT) - 0.341 * Cao)
/ (exp(2 * d_initvalu_39 * FoRT) - 1);
ibarca_sl = pCa * 4 * (d_initvalu_39 * Frdy * FoRT)
* (0.341 * d_initvalu_37 * exp(2 * d_initvalu_39 * FoRT) - 0.341 * Cao)
/ (exp(2 * d_initvalu_39 * FoRT) - 1);
ibark = pK * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_35 * exp(d_initvalu_39 * FoRT) - 0.75 * Ko)
/ (exp(d_initvalu_39 * FoRT) - 1);
ibarna_j = pNa * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_32 * exp(d_initvalu_39 * FoRT) - 0.75 * Nao)
/ (exp(d_initvalu_39 * FoRT) - 1);
ibarna_sl = pNa * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_33 * exp(d_initvalu_39 * FoRT) - 0.75 * Nao)
/ (exp(d_initvalu_39 * FoRT) - 1);
I_Ca_junc = (Fjunc_CaL * ibarca_j * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_6)
* pow(Q10CaL, Qpow)) * 0.45;
I_Ca_sl = (Fsl_CaL * ibarca_sl * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_7)
* pow(Q10CaL, Qpow)) * 0.45;
I_Ca = I_Ca_junc + I_Ca_sl;
d_finavalu[offset_43] = -I_Ca * Cmem / (Vmyo * 2 * Frdy) * 1e3;
I_CaK = (ibark * d_initvalu_4 * d_initvalu_5
* (Fjunc_CaL * (1 - d_initvalu_6) + Fsl_CaL * (1 - d_initvalu_7)) * pow(Q10CaL, Qpow)) * 0.45;
I_CaNa_junc = (Fjunc_CaL * ibarna_j * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_6)
* pow(Q10CaL, Qpow)) * 0.45;
I_CaNa_sl = (Fsl_CaL * ibarna_sl * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_7)
* pow(Q10CaL, Qpow)) * 0.45;
// I_CaNa = I_CaNa_junc+I_CaNa_sl;
// I_Catot = I_Ca+I_CaK+I_CaNa;
// I_ncx: Na/Ca Exchanger flux
Ka_junc = 1 / (1 + pow((Kdact / d_initvalu_36), 3));
Ka_sl = 1 / (1 + pow((Kdact / d_initvalu_37), 3));
s1_junc = exp(nu * d_initvalu_39 * FoRT) * pow(d_initvalu_32, 3) * Cao;
s1_sl = exp(nu * d_initvalu_39 * FoRT) * pow(d_initvalu_33, 3) * Cao;
s2_junc = exp((nu - 1) * d_initvalu_39 * FoRT) * pow(Nao, 3) * d_initvalu_36;
s3_junc = (KmCai * pow(Nao, 3) * (1 + pow((d_initvalu_32 / KmNai), 3))
+ pow(KmNao, 3) * d_initvalu_36 + pow(KmNai, 3) * Cao * (1 + d_initvalu_36 / KmCai)
+ KmCao * pow(d_initvalu_32, 3) + pow(d_initvalu_32, 3) * Cao + pow(Nao, 3) * d_initvalu_36)
* (1 + ksat * exp((nu - 1) * d_initvalu_39 * FoRT));
s2_sl = exp((nu - 1) * d_initvalu_39 * FoRT) * pow(Nao, 3) * d_initvalu_37;
s3_sl = (KmCai * pow(Nao, 3) * (1 + pow((d_initvalu_33 / KmNai), 3))
+ pow(KmNao, 3) * d_initvalu_37 + pow(KmNai, 3) * Cao * (1 + d_initvalu_37 / KmCai)
+ KmCao * pow(d_initvalu_33, 3) + pow(d_initvalu_33, 3) * Cao + pow(Nao, 3) * d_initvalu_37)
* (1 + ksat * exp((nu - 1) * d_initvalu_39 * FoRT));
I_ncx_junc = Fjunc * IbarNCX * pow(Q10NCX, Qpow) * Ka_junc * (s1_junc - s2_junc) / s3_junc;
I_ncx_sl = Fsl * IbarNCX * pow(Q10NCX, Qpow) * Ka_sl * (s1_sl - s2_sl) / s3_sl;
I_ncx = I_ncx_junc + I_ncx_sl;
d_finavalu[offset_45] = 2 * I_ncx * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// I_pca: Sarcolemmal Ca Pump Current
I_pca_junc = Fjunc * pow(Q10SLCaP, Qpow) * IbarSLCaP * pow(d_initvalu_36, float(1.6))
/ (pow(KmPCa, float(1.6)) + pow(d_initvalu_36, float(1.6)));
I_pca_sl = Fsl * pow(Q10SLCaP, Qpow) * IbarSLCaP * pow(d_initvalu_37, float(1.6))
/ (pow(KmPCa, float(1.6)) + pow(d_initvalu_37, float(1.6)));
I_pca = I_pca_junc + I_pca_sl;
d_finavalu[offset_44] = -I_pca * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// I_cabk: Ca Background Current
I_cabk_junc = Fjunc * GCaB * (d_initvalu_39 - eca_junc);
I_cabk_sl = Fsl * GCaB * (d_initvalu_39 - eca_sl);
I_cabk = I_cabk_junc + I_cabk_sl;
d_finavalu[offset_46] = -I_cabk * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// SR fluxes: Calcium Release, SR Ca pump, SR Ca leak
MaxSR = 15;
MinSR = 1;
kCaSR = MaxSR - (MaxSR - MinSR) / (1 + pow(ec50SR / d_initvalu_31, float(2.5)));
koSRCa = koCa / kCaSR;
kiSRCa = kiCa * kCaSR;
RI = 1 - d_initvalu_14 - d_initvalu_15 - d_initvalu_16;
d_finavalu[offset_14] = (kim * RI - kiSRCa * d_initvalu_36 * d_initvalu_14)
- (koSRCa * pow(d_initvalu_36, 2) * d_initvalu_14 - kom * d_initvalu_15); // R
d_finavalu[offset_15] = (koSRCa * pow(d_initvalu_36, 2) * d_initvalu_14 - kom * d_initvalu_15)
- (kiSRCa * d_initvalu_36 * d_initvalu_15 - kim * d_initvalu_16); // O
d_finavalu[offset_16] = (kiSRCa * d_initvalu_36 * d_initvalu_15 - kim * d_initvalu_16)
- (kom * d_initvalu_16 - koSRCa * pow(d_initvalu_36, 2) * RI); // I
J_SRCarel = ks * d_initvalu_15 * (d_initvalu_31 - d_initvalu_36); // [mM/ms]
J_serca = pow(Q10SRCaP, Qpow) * Vmax_SRCaP
* (pow((d_initvalu_38 / Kmf), hillSRCaP) - pow((d_initvalu_31 / Kmr), hillSRCaP))
/ (1 + pow((d_initvalu_38 / Kmf), hillSRCaP) + pow((d_initvalu_31 / Kmr), hillSRCaP));
J_SRleak = 5.348e-6 * (d_initvalu_31 - d_initvalu_36); // [mM/ms]
// Sodium and Calcium Buffering
d_finavalu[offset_17] = kon_na * d_initvalu_32 * (Bmax_Naj - d_initvalu_17)
- koff_na * d_initvalu_17; // NaBj [mM/ms]
d_finavalu[offset_18] = kon_na * d_initvalu_33 * (Bmax_Nasl - d_initvalu_18)
- koff_na * d_initvalu_18; // NaBsl [mM/ms]
// Cytosolic Ca Buffers
d_finavalu[offset_19] = kon_tncl * d_initvalu_38 * (Bmax_TnClow - d_initvalu_19)
- koff_tncl * d_initvalu_19; // TnCL [mM/ms]
d_finavalu[offset_20] = kon_tnchca * d_initvalu_38
* (Bmax_TnChigh - d_initvalu_20 - d_initvalu_21) - koff_tnchca * d_initvalu_20; // TnCHc [mM/ms]
d_finavalu[offset_21] = kon_tnchmg * Mgi * (Bmax_TnChigh - d_initvalu_20 - d_initvalu_21)
- koff_tnchmg * d_initvalu_21; // TnCHm [mM/ms]
d_finavalu[offset_22] = 0; // CaM [mM/ms]
d_finavalu[offset_23] = kon_myoca * d_initvalu_38 * (Bmax_myosin - d_initvalu_23 - d_initvalu_24)
- koff_myoca * d_initvalu_23; // Myosin_ca [mM/ms]
d_finavalu[offset_24] = kon_myomg * Mgi * (Bmax_myosin - d_initvalu_23 - d_initvalu_24)
- koff_myomg * d_initvalu_24; // Myosin_mg [mM/ms]
d_finavalu[offset_25] = kon_sr * d_initvalu_38 * (Bmax_SR - d_initvalu_25)
- koff_sr * d_initvalu_25; // SRB [mM/ms]
J_CaB_cytosol = d_finavalu[offset_19] + d_finavalu[offset_20] + d_finavalu[offset_21]
+ d_finavalu[offset_22] + d_finavalu[offset_23] + d_finavalu[offset_24]
+ d_finavalu[offset_25];
// Junctional and SL Ca Buffers
d_finavalu[offset_26] = kon_sll * d_initvalu_36 * (Bmax_SLlowj - d_initvalu_26)
- koff_sll * d_initvalu_26; // SLLj [mM/ms]
d_finavalu[offset_27] = kon_sll * d_initvalu_37 * (Bmax_SLlowsl - d_initvalu_27)
- koff_sll * d_initvalu_27; // SLLsl [mM/ms]
d_finavalu[offset_28] = kon_slh * d_initvalu_36 * (Bmax_SLhighj - d_initvalu_28)
- koff_slh * d_initvalu_28; // SLHj [mM/ms]
d_finavalu[offset_29] = kon_slh * d_initvalu_37 * (Bmax_SLhighsl - d_initvalu_29)
- koff_slh * d_initvalu_29; // SLHsl [mM/ms]
J_CaB_junction = d_finavalu[offset_26] + d_finavalu[offset_28];
J_CaB_sl = d_finavalu[offset_27] + d_finavalu[offset_29];
// SR Ca Concentrations
d_finavalu[offset_30] = kon_csqn * d_initvalu_31 * (Bmax_Csqn - d_initvalu_30)
- koff_csqn * d_initvalu_30; // Csqn [mM/ms]
oneovervsr = 1 / Vsr;
d_finavalu[offset_31] = J_serca * Vmyo * oneovervsr - (J_SRleak * Vmyo * oneovervsr + J_SRCarel)
- d_finavalu[offset_30]; // Ca_sr [mM/ms] %Ratio 3 leak current
// Sodium Concentrations
I_Na_tot_junc = I_Na_junc + I_nabk_junc + 3 * I_ncx_junc + 3 * I_nak_junc + I_CaNa_junc;// [uA/uF]
I_Na_tot_sl = I_Na_sl + I_nabk_sl + 3 * I_ncx_sl + 3 * I_nak_sl + I_CaNa_sl; // [uA/uF]
d_finavalu[offset_32] = -I_Na_tot_junc * Cmem / (Vjunc * Frdy)
+ J_na_juncsl / Vjunc * (d_initvalu_33 - d_initvalu_32) - d_finavalu[offset_17];
oneovervsl = 1 / Vsl;
d_finavalu[offset_33] = -I_Na_tot_sl * Cmem * oneovervsl / Frdy
+ J_na_juncsl * oneovervsl * (d_initvalu_32 - d_initvalu_33)
+ J_na_slmyo * oneovervsl * (d_initvalu_34 - d_initvalu_33) - d_finavalu[offset_18];
d_finavalu[offset_34] = J_na_slmyo / Vmyo * (d_initvalu_33 - d_initvalu_34); // [mM/msec]
// Potassium Concentration
I_K_tot = I_to + I_kr + I_ks + I_ki - 2 * I_nak + I_CaK + I_kp; // [uA/uF]
d_finavalu[offset_35] = 0; // [mM/msec]
// Calcium Concentrations
I_Ca_tot_junc = I_Ca_junc + I_cabk_junc + I_pca_junc - 2 * I_ncx_junc; // [uA/uF]
I_Ca_tot_sl = I_Ca_sl + I_cabk_sl + I_pca_sl - 2 * I_ncx_sl; // [uA/uF]
d_finavalu[offset_36] = -I_Ca_tot_junc * Cmem / (Vjunc * 2 * Frdy)
+ J_ca_juncsl / Vjunc * (d_initvalu_37 - d_initvalu_36) - J_CaB_junction
+ (J_SRCarel) * Vsr / Vjunc + J_SRleak * Vmyo / Vjunc; // Ca_j
d_finavalu[offset_37] = -I_Ca_tot_sl * Cmem / (Vsl * 2 * Frdy)
+ J_ca_juncsl / Vsl * (d_initvalu_36 - d_initvalu_37)
+ J_ca_slmyo / Vsl * (d_initvalu_38 - d_initvalu_37) - J_CaB_sl; // Ca_sl
d_finavalu[offset_38] = -J_serca - J_CaB_cytosol
+ J_ca_slmyo / Vmyo * (d_initvalu_37 - d_initvalu_38);
// junc_sl=J_ca_juncsl/Vsl*(d_initvalu_36-d_initvalu_37);
// sl_junc=J_ca_juncsl/Vjunc*(d_initvalu_37-d_initvalu_36);
// sl_myo=J_ca_slmyo/Vsl*(d_initvalu_38-d_initvalu_37);
// myo_sl=J_ca_slmyo/Vmyo*(d_initvalu_37-d_initvalu_38);
// Simulation type
state = 1;
switch (state) {
case 0:
I_app = 0;
break;
case 1: // pace w/ current injection at cycleLength 'cycleLength'
if (fmod(timeinst, cycleLength) <= 5) {
I_app = 9.5;
} else {
I_app = 0.0;
}
break;
case 2:
V_hold = -55;
V_test = 0;
if (timeinst > 0.5 & timeinst < 200.5) {
V_clamp = V_test;
} else {
V_clamp = V_hold;
}
R_clamp = 0.04;
I_app = (V_clamp - d_initvalu_39) / R_clamp;
break;
}
// Membrane Potential
I_Na_tot = I_Na_tot_junc + I_Na_tot_sl; // [uA/uF]
I_Cl_tot = I_ClCa + I_Clbk; // [uA/uF]
I_Ca_tot = I_Ca_tot_junc + I_Ca_tot_sl;
I_tot = I_Na_tot + I_Cl_tot + I_Ca_tot + I_K_tot;
d_finavalu[offset_39] = -(I_tot - I_app);
// Set unused output values to 0 (MATLAB does it by default)
d_finavalu[offset_41] = 0;
d_finavalu[offset_42] = 0;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
//=====================================================================
// MAIN FUNCTION
//=====================================================================
__device__ void kernel_ecc(float timeinst, float* d_initvalu, float *d_finavalu, int valu_offset,
float* d_params) {
//=====================================================================
// VARIABLES
//=====================================================================
// input parameters
float cycleLength;
// variable references // GET VARIABLES FROM MEMORY AND SAVE LOCALLY !!!!!!!!!!!!!!!!!!
int offset_1;
int offset_2;
int offset_3;
int offset_4;
int offset_5;
int offset_6;
int offset_7;
int offset_8;
int offset_9;
int offset_10;
int offset_11;
int offset_12;
int offset_13;
int offset_14;
int offset_15;
int offset_16;
int offset_17;
int offset_18;
int offset_19;
int offset_20;
int offset_21;
int offset_22;
int offset_23;
int offset_24;
int offset_25;
int offset_26;
int offset_27;
int offset_28;
int offset_29;
int offset_30;
int offset_31;
int offset_32;
int offset_33;
int offset_34;
int offset_35;
int offset_36;
int offset_37;
int offset_38;
int offset_39;
int offset_40;
int offset_41;
int offset_42;
int offset_43;
int offset_44;
int offset_45;
int offset_46;
// stored input array
float d_initvalu_1;
float d_initvalu_2;
float d_initvalu_3;
float d_initvalu_4;
float d_initvalu_5;
float d_initvalu_6;
float d_initvalu_7;
float d_initvalu_8;
float d_initvalu_9;
float d_initvalu_10;
float d_initvalu_11;
float d_initvalu_12;
float d_initvalu_13;
float d_initvalu_14;
float d_initvalu_15;
float d_initvalu_16;
float d_initvalu_17;
float d_initvalu_18;
float d_initvalu_19;
float d_initvalu_20;
float d_initvalu_21;
// float d_initvalu_22;
float d_initvalu_23;
float d_initvalu_24;
float d_initvalu_25;
float d_initvalu_26;
float d_initvalu_27;
float d_initvalu_28;
float d_initvalu_29;
float d_initvalu_30;
float d_initvalu_31;
float d_initvalu_32;
float d_initvalu_33;
float d_initvalu_34;
float d_initvalu_35;
float d_initvalu_36;
float d_initvalu_37;
float d_initvalu_38;
float d_initvalu_39;
float d_initvalu_40;
// float d_initvalu_41;
// float d_initvalu_42;
// float d_initvalu_43;
// float d_initvalu_44;
// float d_initvalu_45;
// float d_initvalu_46;
// matlab constants undefined in c
float pi;
// Constants
float R; // [J/kmol*K]
float Frdy; // [C/mol]
float Temp; // [K] 310
float FoRT; //
float Cmem; // [F] membrane capacitance
float Qpow;
// Cell geometry
float cellLength; // cell length [um]
float cellRadius; // cell radius [um]
// float junctionLength; // junc length [um]
// float junctionRadius; // junc radius [um]
// float distSLcyto; // dist. SL to cytosol [um]
// float distJuncSL; // dist. junc to SL [um]
// float DcaJuncSL; // Dca junc to SL [cm^2/sec]
// float DcaSLcyto; // Dca SL to cyto [cm^2/sec]
// float DnaJuncSL; // Dna junc to SL [cm^2/sec]
// float DnaSLcyto; // Dna SL to cyto [cm^2/sec]
float Vcell; // [L]
float Vmyo;
float Vsr;
float Vsl;
float Vjunc;
// float SAjunc; // [um^2]
// float SAsl; // [um^2]
float J_ca_juncsl; // [L/msec]
float J_ca_slmyo; // [L/msec]
float J_na_juncsl; // [L/msec]
float J_na_slmyo; // [L/msec]
// Fractional currents in compartments
float Fjunc;
float Fsl;
float Fjunc_CaL;
float Fsl_CaL;
// Fixed ion concentrations
float Cli; // Intracellular Cl [mM]
float Clo; // Extracellular Cl [mM]
float Ko; // Extracellular K [mM]
float Nao; // Extracellular Na [mM]
float Cao; // Extracellular Ca [mM]
float Mgi; // Intracellular Mg [mM]
// Nernst Potentials
float ena_junc; // [mV]
float ena_sl; // [mV]
float ek; // [mV]
float eca_junc; // [mV]
float eca_sl; // [mV]
float ecl; // [mV]
// Na transport parameters
float GNa; // [mS/uF]
float GNaB; // [mS/uF]
float IbarNaK; // [uA/uF]
float KmNaip; // [mM]
float KmKo; // [mM]
// float Q10NaK;
// float Q10KmNai;
// K current parameters
float pNaK;
float GtoSlow; // [mS/uF]
float GtoFast; // [mS/uF]
float gkp;
// Cl current parameters
float GClCa; // [mS/uF]
float GClB; // [mS/uF]
float KdClCa; // [mM] // [mM]
// I_Ca parameters
float pNa; // [cm/sec]
float pCa; // [cm/sec]
float pK; // [cm/sec]
// float KmCa; // [mM]
float Q10CaL;
// Ca transport parameters
float IbarNCX; // [uA/uF]
float KmCai; // [mM]
float KmCao; // [mM]
float KmNai; // [mM]
float KmNao; // [mM]
float ksat; // [none]
float nu; // [none]
float Kdact; // [mM]
float Q10NCX; // [none]
float IbarSLCaP; // [uA/uF]
float KmPCa; // [mM]
float GCaB; // [uA/uF]
float Q10SLCaP; // [none] // [none]
// SR flux parameters
float Q10SRCaP; // [none]
float Vmax_SRCaP; // [mM/msec] (mmol/L cytosol/msec)
float Kmf; // [mM]
float Kmr; // [mM]L cytosol
float hillSRCaP; // [mM]
float ks; // [1/ms]
float koCa; // [mM^-2 1/ms]
float kom; // [1/ms]
float kiCa; // [1/mM/ms]
float kim; // [1/ms]
float ec50SR; // [mM]
// Buffering parameters
float Bmax_Naj; // [mM]
float Bmax_Nasl; // [mM]
float koff_na; // [1/ms]
float kon_na; // [1/mM/ms]
float Bmax_TnClow; // [mM], TnC low affinity
float koff_tncl; // [1/ms]
float kon_tncl; // [1/mM/ms]
float Bmax_TnChigh; // [mM], TnC high affinity
float koff_tnchca; // [1/ms]
float kon_tnchca; // [1/mM/ms]
float koff_tnchmg; // [1/ms]
float kon_tnchmg; // [1/mM/ms]
// float Bmax_CaM; // [mM], CaM buffering
// float koff_cam; // [1/ms]
// float kon_cam; // [1/mM/ms]
float Bmax_myosin; // [mM], Myosin buffering
float koff_myoca; // [1/ms]
float kon_myoca; // [1/mM/ms]
float koff_myomg; // [1/ms]
float kon_myomg; // [1/mM/ms]
float Bmax_SR; // [mM]
float koff_sr; // [1/ms]
float kon_sr; // [1/mM/ms]
float Bmax_SLlowsl; // [mM], SL buffering
float Bmax_SLlowj; // [mM]
float koff_sll; // [1/ms]
float kon_sll; // [1/mM/ms]
float Bmax_SLhighsl; // [mM]
float Bmax_SLhighj; // [mM]
float koff_slh; // [1/ms]
float kon_slh; // [1/mM/ms]
float Bmax_Csqn; // 140e-3*Vmyo/Vsr; [mM]
float koff_csqn; // [1/ms]
float kon_csqn; // [1/mM/ms]
// I_Na: Fast Na Current
float am;
float bm;
float ah;
float bh;
float aj;
float bj;
float I_Na_junc;
float I_Na_sl;
// float I_Na;
// I_nabk: Na Background Current
float I_nabk_junc;
float I_nabk_sl;
// float I_nabk;
// I_nak: Na/K Pump Current
float sigma;
float fnak;
float I_nak_junc;
float I_nak_sl;
float I_nak;
// I_kr: Rapidly Activating K Current
float gkr;
float xrss;
float tauxr;
float rkr;
float I_kr;
// I_ks: Slowly Activating K Current
float pcaks_junc;
float pcaks_sl;
float gks_junc;
float gks_sl;
float eks;
float xsss;
float tauxs;
float I_ks_junc;
float I_ks_sl;
float I_ks;
// I_kp: Plateau K current
float kp_kp;
float I_kp_junc;
float I_kp_sl;
float I_kp;
// I_to: Transient Outward K Current (slow and fast components)
float xtoss;
float ytoss;
float rtoss;
float tauxtos;
float tauytos;
float taurtos;
float I_tos;
//
float tauxtof;
float tauytof;
float I_tof;
float I_to;
// I_ki: Time-Independent K Current
float aki;
float bki;
float kiss;
float I_ki;
// I_ClCa: Ca-activated Cl Current, I_Clbk: background Cl Current
float I_ClCa_junc;
float I_ClCa_sl;
float I_ClCa;
float I_Clbk;
// I_Ca: L-type Calcium Current
float dss;
float taud;
float fss;
float tauf;
//
float ibarca_j;
float ibarca_sl;
float ibark;
float ibarna_j;
float ibarna_sl;
float I_Ca_junc;
float I_Ca_sl;
float I_Ca;
float I_CaK;
float I_CaNa_junc;
float I_CaNa_sl;
// float I_CaNa;
// float I_Catot;
// I_ncx: Na/Ca Exchanger flux
float Ka_junc;
float Ka_sl;
float s1_junc;
float s1_sl;
float s2_junc;
float s3_junc;
float s2_sl;
float s3_sl;
float I_ncx_junc;
float I_ncx_sl;
float I_ncx;
// I_pca: Sarcolemmal Ca Pump Current
float I_pca_junc;
float I_pca_sl;
float I_pca;
// I_cabk: Ca Background Current
float I_cabk_junc;
float I_cabk_sl;
float I_cabk;
// SR fluxes: Calcium Release, SR Ca pump, SR Ca leak
float MaxSR;
float MinSR;
float kCaSR;
float koSRCa;
float kiSRCa;
float RI;
float J_SRCarel; // [mM/ms]
float J_serca;
float J_SRleak; // [mM/ms]
// Cytosolic Ca Buffers
float J_CaB_cytosol;
// Junctional and SL Ca Buffers
float J_CaB_junction;
float J_CaB_sl;
// SR Ca Concentrations
float oneovervsr;
// Sodium Concentrations
float I_Na_tot_junc; // [uA/uF]
float I_Na_tot_sl; // [uA/uF]
float oneovervsl;
// Potassium Concentration
float I_K_tot;
// Calcium Concentrations
float I_Ca_tot_junc; // [uA/uF]
float I_Ca_tot_sl; // [uA/uF]
// float junc_sl;
// float sl_junc;
// float sl_myo;
// float myo_sl;
// Simulation type
int state; // 0-none; 1-pace; 2-vclamp
float I_app;
float V_hold;
float V_test;
float V_clamp;
float R_clamp;
// Membrane Potential
float I_Na_tot; // [uA/uF]
float I_Cl_tot; // [uA/uF]
float I_Ca_tot;
float I_tot;
//=====================================================================
// EXECUTION
//=====================================================================
// input parameters
cycleLength = d_params[15];
// variable references
offset_1 = valu_offset;
offset_2 = valu_offset + 1;
offset_3 = valu_offset + 2;
offset_4 = valu_offset + 3;
offset_5 = valu_offset + 4;
offset_6 = valu_offset + 5;
offset_7 = valu_offset + 6;
offset_8 = valu_offset + 7;
offset_9 = valu_offset + 8;
offset_10 = valu_offset + 9;
offset_11 = valu_offset + 10;
offset_12 = valu_offset + 11;
offset_13 = valu_offset + 12;
offset_14 = valu_offset + 13;
offset_15 = valu_offset + 14;
offset_16 = valu_offset + 15;
offset_17 = valu_offset + 16;
offset_18 = valu_offset + 17;
offset_19 = valu_offset + 18;
offset_20 = valu_offset + 19;
offset_21 = valu_offset + 20;
offset_22 = valu_offset + 21;
offset_23 = valu_offset + 22;
offset_24 = valu_offset + 23;
offset_25 = valu_offset + 24;
offset_26 = valu_offset + 25;
offset_27 = valu_offset + 26;
offset_28 = valu_offset + 27;
offset_29 = valu_offset + 28;
offset_30 = valu_offset + 29;
offset_31 = valu_offset + 30;
offset_32 = valu_offset + 31;
offset_33 = valu_offset + 32;
offset_34 = valu_offset + 33;
offset_35 = valu_offset + 34;
offset_36 = valu_offset + 35;
offset_37 = valu_offset + 36;
offset_38 = valu_offset + 37;
offset_39 = valu_offset + 38;
offset_40 = valu_offset + 39;
offset_41 = valu_offset + 40;
offset_42 = valu_offset + 41;
offset_43 = valu_offset + 42;
offset_44 = valu_offset + 43;
offset_45 = valu_offset + 44;
offset_46 = valu_offset + 45;
// stored input array
d_initvalu_1 = d_initvalu[offset_1];
d_initvalu_2 = d_initvalu[offset_2];
d_initvalu_3 = d_initvalu[offset_3];
d_initvalu_4 = d_initvalu[offset_4];
d_initvalu_5 = d_initvalu[offset_5];
d_initvalu_6 = d_initvalu[offset_6];
d_initvalu_7 = d_initvalu[offset_7];
d_initvalu_8 = d_initvalu[offset_8];
d_initvalu_9 = d_initvalu[offset_9];
d_initvalu_10 = d_initvalu[offset_10];
d_initvalu_11 = d_initvalu[offset_11];
d_initvalu_12 = d_initvalu[offset_12];
d_initvalu_13 = d_initvalu[offset_13];
d_initvalu_14 = d_initvalu[offset_14];
d_initvalu_15 = d_initvalu[offset_15];
d_initvalu_16 = d_initvalu[offset_16];
d_initvalu_17 = d_initvalu[offset_17];
d_initvalu_18 = d_initvalu[offset_18];
d_initvalu_19 = d_initvalu[offset_19];
d_initvalu_20 = d_initvalu[offset_20];
d_initvalu_21 = d_initvalu[offset_21];
// d_initvalu_22 = d_initvalu[offset_22];
d_initvalu_23 = d_initvalu[offset_23];
d_initvalu_24 = d_initvalu[offset_24];
d_initvalu_25 = d_initvalu[offset_25];
d_initvalu_26 = d_initvalu[offset_26];
d_initvalu_27 = d_initvalu[offset_27];
d_initvalu_28 = d_initvalu[offset_28];
d_initvalu_29 = d_initvalu[offset_29];
d_initvalu_30 = d_initvalu[offset_30];
d_initvalu_31 = d_initvalu[offset_31];
d_initvalu_32 = d_initvalu[offset_32];
d_initvalu_33 = d_initvalu[offset_33];
d_initvalu_34 = d_initvalu[offset_34];
d_initvalu_35 = d_initvalu[offset_35];
d_initvalu_36 = d_initvalu[offset_36];
d_initvalu_37 = d_initvalu[offset_37];
d_initvalu_38 = d_initvalu[offset_38];
d_initvalu_39 = d_initvalu[offset_39];
d_initvalu_40 = d_initvalu[offset_40];
// d_initvalu_41 = d_initvalu[offset_41];
// d_initvalu_42 = d_initvalu[offset_42];
// d_initvalu_43 = d_initvalu[offset_43];
// d_initvalu_44 = d_initvalu[offset_44];
// d_initvalu_45 = d_initvalu[offset_45];
// d_initvalu_46 = d_initvalu[offset_46];
// matlab constants undefined in c
pi = 3.1416;
// Constants
R = 8314; // [J/kmol*K]
Frdy = 96485; // [C/mol]
Temp = 310; // [K] 310
FoRT = Frdy / R / Temp; //
Cmem = 1.3810e-10; // [F] membrane capacitance
Qpow = (Temp - 310) / 10;
// Cell geometry
cellLength = 100; // cell length [um]
cellRadius = 10.25; // cell radius [um]
// junctionLength = 160e-3; // junc length [um]
// junctionRadius = 15e-3; // junc radius [um]
// distSLcyto = 0.45; // dist. SL to cytosol [um]
// distJuncSL = 0.5; // dist. junc to SL [um]
// DcaJuncSL = 1.64e-6; // Dca junc to SL [cm^2/sec]
// DcaSLcyto = 1.22e-6; // Dca SL to cyto [cm^2/sec]
// DnaJuncSL = 1.09e-5; // Dna junc to SL [cm^2/sec]
// DnaSLcyto = 1.79e-5; // Dna SL to cyto [cm^2/sec]
Vcell = pi * pow(cellRadius, 2) * cellLength * 1e-15; // [L]
Vmyo = 0.65 * Vcell;
Vsr = 0.035 * Vcell;
Vsl = 0.02 * Vcell;
Vjunc = 0.0539 * 0.01 * Vcell;
// SAjunc = 20150*pi*2*junctionLength*junctionRadius; // [um^2]
// SAsl = pi*2*cellRadius*cellLength; // [um^2]
J_ca_juncsl = 1 / 1.2134e12; // [L/msec]
J_ca_slmyo = 1 / 2.68510e11; // [L/msec]
J_na_juncsl = 1 / (1.6382e12 / 3 * 100); // [L/msec]
J_na_slmyo = 1 / (1.8308e10 / 3 * 100); // [L/msec]
// Fractional currents in compartments
Fjunc = 0.11;
Fsl = 1 - Fjunc;
Fjunc_CaL = 0.9;
Fsl_CaL = 1 - Fjunc_CaL;
// Fixed ion concentrations
Cli = 15; // Intracellular Cl [mM]
Clo = 150; // Extracellular Cl [mM]
Ko = 5.4; // Extracellular K [mM]
Nao = 140; // Extracellular Na [mM]
Cao = 1.8; // Extracellular Ca [mM]
Mgi = 1; // Intracellular Mg [mM]
// Nernst Potentials
ena_junc = (1 / FoRT) * log(Nao / d_initvalu_32); // [mV]
ena_sl = (1 / FoRT) * log(Nao / d_initvalu_33); // [mV]
ek = (1 / FoRT) * log(Ko / d_initvalu_35); // [mV]
eca_junc = (1 / FoRT / 2) * log(Cao / d_initvalu_36); // [mV]
eca_sl = (1 / FoRT / 2) * log(Cao / d_initvalu_37); // [mV]
ecl = (1 / FoRT) * log(Cli / Clo); // [mV]
// Na transport parameters
GNa = 16.0; // [mS/uF]
GNaB = 0.297e-3; // [mS/uF]
IbarNaK = 1.90719; // [uA/uF]
KmNaip = 11; // [mM]
KmKo = 1.5; // [mM]
// Q10NaK = 1.63;
// Q10KmNai = 1.39;
// K current parameters
pNaK = 0.01833;
GtoSlow = 0.06; // [mS/uF]
GtoFast = 0.02; // [mS/uF]
gkp = 0.001;
// Cl current parameters
GClCa = 0.109625; // [mS/uF]
GClB = 9e-3; // [mS/uF]
KdClCa = 100e-3; // [mM]
// I_Ca parameters
pNa = 1.5e-8; // [cm/sec]
pCa = 5.4e-4; // [cm/sec]
pK = 2.7e-7; // [cm/sec]
// KmCa = 0.6e-3; // [mM]
Q10CaL = 1.8;
// Ca transport parameters
IbarNCX = 9.0; // [uA/uF]
KmCai = 3.59e-3; // [mM]
KmCao = 1.3; // [mM]
KmNai = 12.29; // [mM]
KmNao = 87.5; // [mM]
ksat = 0.27; // [none]
nu = 0.35; // [none]
Kdact = 0.256e-3; // [mM]
Q10NCX = 1.57; // [none]
IbarSLCaP = 0.0673; // [uA/uF]
KmPCa = 0.5e-3; // [mM]
GCaB = 2.513e-4; // [uA/uF]
Q10SLCaP = 2.35; // [none]
// SR flux parameters
Q10SRCaP = 2.6; // [none]
Vmax_SRCaP = 2.86e-4; // [mM/msec] (mmol/L cytosol/msec)
Kmf = 0.246e-3; // [mM]
Kmr = 1.7; // [mM]L cytosol
hillSRCaP = 1.787; // [mM]
ks = 25; // [1/ms]
koCa = 10; // [mM^-2 1/ms]
kom = 0.06; // [1/ms]
kiCa = 0.5; // [1/mM/ms]
kim = 0.005; // [1/ms]
ec50SR = 0.45; // [mM]
// Buffering parameters
Bmax_Naj = 7.561; // [mM]
Bmax_Nasl = 1.65; // [mM]
koff_na = 1e-3; // [1/ms]
kon_na = 0.1e-3; // [1/mM/ms]
Bmax_TnClow = 70e-3; // [mM], TnC low affinity
koff_tncl = 19.6e-3; // [1/ms]
kon_tncl = 32.7; // [1/mM/ms]
Bmax_TnChigh = 140e-3; // [mM], TnC high affinity
koff_tnchca = 0.032e-3; // [1/ms]
kon_tnchca = 2.37; // [1/mM/ms]
koff_tnchmg = 3.33e-3; // [1/ms]
kon_tnchmg = 3e-3; // [1/mM/ms]
// Bmax_CaM = 24e-3; // [mM], CaM buffering
// koff_cam = 238e-3; // [1/ms]
// kon_cam = 34; // [1/mM/ms]
Bmax_myosin = 140e-3; // [mM], Myosin buffering
koff_myoca = 0.46e-3; // [1/ms]
kon_myoca = 13.8; // [1/mM/ms]
koff_myomg = 0.057e-3; // [1/ms]
kon_myomg = 0.0157; // [1/mM/ms]
Bmax_SR = 19 * 0.9e-3; // [mM]
koff_sr = 60e-3; // [1/ms]
kon_sr = 100; // [1/mM/ms]
Bmax_SLlowsl = 37.38e-3 * Vmyo / Vsl; // [mM], SL buffering
Bmax_SLlowj = 4.62e-3 * Vmyo / Vjunc * 0.1; // [mM]
koff_sll = 1300e-3; // [1/ms]
kon_sll = 100; // [1/mM/ms]
Bmax_SLhighsl = 13.35e-3 * Vmyo / Vsl; // [mM]
Bmax_SLhighj = 1.65e-3 * Vmyo / Vjunc * 0.1; // [mM]
koff_slh = 30e-3; // [1/ms]
kon_slh = 100; // [1/mM/ms]
Bmax_Csqn = 2.7; // 140e-3*Vmyo/Vsr; [mM]
koff_csqn = 65; // [1/ms]
kon_csqn = 100; // [1/mM/ms]
// I_Na: Fast Na Current
am = 0.32 * (d_initvalu_39 + 47.13) / (1 - exp(-0.1 * (d_initvalu_39 + 47.13)));
bm = 0.08 * exp(-d_initvalu_39 / 11);
if (d_initvalu_39 >= -40) {
ah = 0;
aj = 0;
bh = 1 / (0.13 * (1 + exp(-(d_initvalu_39 + 10.66) / 11.1)));
bj = 0.3 * exp(-2.535e-7 * d_initvalu_39) / (1 + exp(-0.1 * (d_initvalu_39 + 32)));
} else {
ah = 0.135 * exp((80 + d_initvalu_39) / -6.8);
bh = 3.56 * exp(0.079 * d_initvalu_39) + 3.1e5 * exp(0.35 * d_initvalu_39);
aj = (-127140 * exp(0.2444 * d_initvalu_39) - 3.474e-5 * exp(-0.04391 * d_initvalu_39))
* (d_initvalu_39 + 37.78) / (1 + exp(0.311 * (d_initvalu_39 + 79.23)));
bj = 0.1212 * exp(-0.01052 * d_initvalu_39) / (1 + exp(-0.1378 * (d_initvalu_39 + 40.14)));
}
d_finavalu[offset_1] = am * (1 - d_initvalu_1) - bm * d_initvalu_1;
d_finavalu[offset_2] = ah * (1 - d_initvalu_2) - bh * d_initvalu_2;
d_finavalu[offset_3] = aj * (1 - d_initvalu_3) - bj * d_initvalu_3;
I_Na_junc = Fjunc * GNa * pow(d_initvalu_1, 3) * d_initvalu_2 * d_initvalu_3
* (d_initvalu_39 - ena_junc);
I_Na_sl = Fsl * GNa * pow(d_initvalu_1, 3) * d_initvalu_2 * d_initvalu_3
* (d_initvalu_39 - ena_sl);
// I_Na = I_Na_junc+I_Na_sl;
// I_nabk: Na Background Current
I_nabk_junc = Fjunc * GNaB * (d_initvalu_39 - ena_junc);
I_nabk_sl = Fsl * GNaB * (d_initvalu_39 - ena_sl);
// I_nabk = I_nabk_junc+I_nabk_sl;
// I_nak: Na/K Pump Current
sigma = (exp(Nao / 67.3) - 1) / 7;
fnak =
1
/ (1 + 0.1245 * exp(-0.1 * d_initvalu_39 * FoRT)
+ 0.0365 * sigma * exp(-d_initvalu_39 * FoRT));
I_nak_junc = Fjunc * IbarNaK * fnak * Ko / (1 + pow((KmNaip / d_initvalu_32), 4)) / (Ko + KmKo);
I_nak_sl = Fsl * IbarNaK * fnak * Ko / (1 + pow((KmNaip / d_initvalu_33), 4)) / (Ko + KmKo);
I_nak = I_nak_junc + I_nak_sl;
// I_kr: Rapidly Activating K Current
gkr = 0.03 * sqrt(Ko / 5.4);
xrss = 1 / (1 + exp(-(d_initvalu_39 + 50) / 7.5));
tauxr = 1
/ (0.00138 * (d_initvalu_39 + 7) / (1 - exp(-0.123 * (d_initvalu_39 + 7)))
+ 6.1e-4 * (d_initvalu_39 + 10) / (exp(0.145 * (d_initvalu_39 + 10)) - 1));
d_finavalu[offset_12] = (xrss - d_initvalu_12) / tauxr;
rkr = 1 / (1 + exp((d_initvalu_39 + 33) / 22.4));
I_kr = gkr * d_initvalu_12 * rkr * (d_initvalu_39 - ek);
// I_ks: Slowly Activating K Current
pcaks_junc = -log10(d_initvalu_36) + 3.0;
pcaks_sl = -log10(d_initvalu_37) + 3.0;
gks_junc = 0.07 * (0.057 + 0.19 / (1 + exp((-7.2 + pcaks_junc) / 0.6)));
gks_sl = 0.07 * (0.057 + 0.19 / (1 + exp((-7.2 + pcaks_sl) / 0.6)));
eks = (1 / FoRT) * log((Ko + pNaK * Nao) / (d_initvalu_35 + pNaK * d_initvalu_34));
xsss = 1 / (1 + exp(-(d_initvalu_39 - 1.5) / 16.7));
tauxs = 1
/ (7.19e-5 * (d_initvalu_39 + 30) / (1 - exp(-0.148 * (d_initvalu_39 + 30)))
+ 1.31e-4 * (d_initvalu_39 + 30) / (exp(0.0687 * (d_initvalu_39 + 30)) - 1));
d_finavalu[offset_13] = (xsss - d_initvalu_13) / tauxs;
I_ks_junc = Fjunc * gks_junc * pow(d_initvalu_12, 2) * (d_initvalu_39 - eks);
I_ks_sl = Fsl * gks_sl * pow(d_initvalu_13, 2) * (d_initvalu_39 - eks);
I_ks = I_ks_junc + I_ks_sl;
// I_kp: Plateau K current
kp_kp = 1 / (1 + exp(7.488 - d_initvalu_39 / 5.98));
I_kp_junc = Fjunc * gkp * kp_kp * (d_initvalu_39 - ek);
I_kp_sl = Fsl * gkp * kp_kp * (d_initvalu_39 - ek);
I_kp = I_kp_junc + I_kp_sl;
// I_to: Transient Outward K Current (slow and fast components)
xtoss = 1 / (1 + exp(-(d_initvalu_39 + 3.0) / 15));
ytoss = 1 / (1 + exp((d_initvalu_39 + 33.5) / 10));
rtoss = 1 / (1 + exp((d_initvalu_39 + 33.5) / 10));
tauxtos = 9 / (1 + exp((d_initvalu_39 + 3.0) / 15)) + 0.5;
tauytos = 3e3 / (1 + exp((d_initvalu_39 + 60.0) / 10)) + 30;
taurtos = 2800 / (1 + exp((d_initvalu_39 + 60.0) / 10)) + 220;
d_finavalu[offset_8] = (xtoss - d_initvalu_8) / tauxtos;
d_finavalu[offset_9] = (ytoss - d_initvalu_9) / tauytos;
d_finavalu[offset_40] = (rtoss - d_initvalu_40) / taurtos;
I_tos = GtoSlow * d_initvalu_8 * (d_initvalu_9 + 0.5 * d_initvalu_40) * (d_initvalu_39 - ek); // [uA/uF]
//
tauxtof = 3.5 * exp(-d_initvalu_39 * d_initvalu_39 / 30 / 30) + 1.5;
tauytof = 20.0 / (1 + exp((d_initvalu_39 + 33.5) / 10)) + 20.0;
d_finavalu[offset_10] = (xtoss - d_initvalu_10) / tauxtof;
d_finavalu[offset_11] = (ytoss - d_initvalu_11) / tauytof;
I_tof = GtoFast * d_initvalu_10 * d_initvalu_11 * (d_initvalu_39 - ek);
I_to = I_tos + I_tof;
// I_ki: Time-Independent K Current
aki = 1.02 / (1 + exp(0.2385 * (d_initvalu_39 - ek - 59.215)));
bki = (0.49124 * exp(0.08032 * (d_initvalu_39 + 5.476 - ek))
+ exp(0.06175 * (d_initvalu_39 - ek - 594.31)))
/ (1 + exp(-0.5143 * (d_initvalu_39 - ek + 4.753)));
kiss = aki / (aki + bki);
I_ki = 0.9 * sqrt(Ko / 5.4) * kiss * (d_initvalu_39 - ek);
// I_ClCa: Ca-activated Cl Current, I_Clbk: background Cl Current
I_ClCa_junc = Fjunc * GClCa / (1 + KdClCa / d_initvalu_36) * (d_initvalu_39 - ecl);
I_ClCa_sl = Fsl * GClCa / (1 + KdClCa / d_initvalu_37) * (d_initvalu_39 - ecl);
I_ClCa = I_ClCa_junc + I_ClCa_sl;
I_Clbk = GClB * (d_initvalu_39 - ecl);
// I_Ca: L-type Calcium Current
dss = 1 / (1 + exp(-(d_initvalu_39 + 14.5) / 6.0));
taud = dss * (1 - exp(-(d_initvalu_39 + 14.5) / 6.0)) / (0.035 * (d_initvalu_39 + 14.5));
fss = 1 / (1 + exp((d_initvalu_39 + 35.06) / 3.6)) + 0.6 / (1 + exp((50 - d_initvalu_39) / 20));
tauf = 1 / (0.0197 * exp(-pow(0.0337 * (d_initvalu_39 + 14.5), 2)) + 0.02);
d_finavalu[offset_4] = (dss - d_initvalu_4) / taud;
d_finavalu[offset_5] = (fss - d_initvalu_5) / tauf;
d_finavalu[offset_6] = 1.7 * d_initvalu_36 * (1 - d_initvalu_6) - 11.9e-3 * d_initvalu_6; // fCa_junc
d_finavalu[offset_7] = 1.7 * d_initvalu_37 * (1 - d_initvalu_7) - 11.9e-3 * d_initvalu_7; // fCa_sl
//
ibarca_j = pCa * 4 * (d_initvalu_39 * Frdy * FoRT)
* (0.341 * d_initvalu_36 * exp(2 * d_initvalu_39 * FoRT) - 0.341 * Cao)
/ (exp(2 * d_initvalu_39 * FoRT) - 1);
ibarca_sl = pCa * 4 * (d_initvalu_39 * Frdy * FoRT)
* (0.341 * d_initvalu_37 * exp(2 * d_initvalu_39 * FoRT) - 0.341 * Cao)
/ (exp(2 * d_initvalu_39 * FoRT) - 1);
ibark = pK * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_35 * exp(d_initvalu_39 * FoRT) - 0.75 * Ko)
/ (exp(d_initvalu_39 * FoRT) - 1);
ibarna_j = pNa * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_32 * exp(d_initvalu_39 * FoRT) - 0.75 * Nao)
/ (exp(d_initvalu_39 * FoRT) - 1);
ibarna_sl = pNa * (d_initvalu_39 * Frdy * FoRT)
* (0.75 * d_initvalu_33 * exp(d_initvalu_39 * FoRT) - 0.75 * Nao)
/ (exp(d_initvalu_39 * FoRT) - 1);
I_Ca_junc = (Fjunc_CaL * ibarca_j * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_6)
* pow(Q10CaL, Qpow)) * 0.45;
I_Ca_sl = (Fsl_CaL * ibarca_sl * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_7)
* pow(Q10CaL, Qpow)) * 0.45;
I_Ca = I_Ca_junc + I_Ca_sl;
d_finavalu[offset_43] = -I_Ca * Cmem / (Vmyo * 2 * Frdy) * 1e3;
I_CaK = (ibark * d_initvalu_4 * d_initvalu_5
* (Fjunc_CaL * (1 - d_initvalu_6) + Fsl_CaL * (1 - d_initvalu_7)) * pow(Q10CaL, Qpow)) * 0.45;
I_CaNa_junc = (Fjunc_CaL * ibarna_j * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_6)
* pow(Q10CaL, Qpow)) * 0.45;
I_CaNa_sl = (Fsl_CaL * ibarna_sl * d_initvalu_4 * d_initvalu_5 * (1 - d_initvalu_7)
* pow(Q10CaL, Qpow)) * 0.45;
// I_CaNa = I_CaNa_junc+I_CaNa_sl;
// I_Catot = I_Ca+I_CaK+I_CaNa;
// I_ncx: Na/Ca Exchanger flux
Ka_junc = 1 / (1 + pow((Kdact / d_initvalu_36), 3));
Ka_sl = 1 / (1 + pow((Kdact / d_initvalu_37), 3));
s1_junc = exp(nu * d_initvalu_39 * FoRT) * pow(d_initvalu_32, 3) * Cao;
s1_sl = exp(nu * d_initvalu_39 * FoRT) * pow(d_initvalu_33, 3) * Cao;
s2_junc = exp((nu - 1) * d_initvalu_39 * FoRT) * pow(Nao, 3) * d_initvalu_36;
s3_junc = (KmCai * pow(Nao, 3) * (1 + pow((d_initvalu_32 / KmNai), 3))
+ pow(KmNao, 3) * d_initvalu_36 + pow(KmNai, 3) * Cao * (1 + d_initvalu_36 / KmCai)
+ KmCao * pow(d_initvalu_32, 3) + pow(d_initvalu_32, 3) * Cao + pow(Nao, 3) * d_initvalu_36)
* (1 + ksat * exp((nu - 1) * d_initvalu_39 * FoRT));
s2_sl = exp((nu - 1) * d_initvalu_39 * FoRT) * pow(Nao, 3) * d_initvalu_37;
s3_sl = (KmCai * pow(Nao, 3) * (1 + pow((d_initvalu_33 / KmNai), 3))
+ pow(KmNao, 3) * d_initvalu_37 + pow(KmNai, 3) * Cao * (1 + d_initvalu_37 / KmCai)
+ KmCao * pow(d_initvalu_33, 3) + pow(d_initvalu_33, 3) * Cao + pow(Nao, 3) * d_initvalu_37)
* (1 + ksat * exp((nu - 1) * d_initvalu_39 * FoRT));
I_ncx_junc = Fjunc * IbarNCX * pow(Q10NCX, Qpow) * Ka_junc * (s1_junc - s2_junc) / s3_junc;
I_ncx_sl = Fsl * IbarNCX * pow(Q10NCX, Qpow) * Ka_sl * (s1_sl - s2_sl) / s3_sl;
I_ncx = I_ncx_junc + I_ncx_sl;
d_finavalu[offset_45] = 2 * I_ncx * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// I_pca: Sarcolemmal Ca Pump Current
I_pca_junc = Fjunc * pow(Q10SLCaP, Qpow) * IbarSLCaP * pow(d_initvalu_36, float(1.6))
/ (pow(KmPCa, float(1.6)) + pow(d_initvalu_36, float(1.6)));
I_pca_sl = Fsl * pow(Q10SLCaP, Qpow) * IbarSLCaP * pow(d_initvalu_37, float(1.6))
/ (pow(KmPCa, float(1.6)) + pow(d_initvalu_37, float(1.6)));
I_pca = I_pca_junc + I_pca_sl;
d_finavalu[offset_44] = -I_pca * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// I_cabk: Ca Background Current
I_cabk_junc = Fjunc * GCaB * (d_initvalu_39 - eca_junc);
I_cabk_sl = Fsl * GCaB * (d_initvalu_39 - eca_sl);
I_cabk = I_cabk_junc + I_cabk_sl;
d_finavalu[offset_46] = -I_cabk * Cmem / (Vmyo * 2 * Frdy) * 1e3;
// SR fluxes: Calcium Release, SR Ca pump, SR Ca leak
MaxSR = 15;
MinSR = 1;
kCaSR = MaxSR - (MaxSR - MinSR) / (1 + pow(ec50SR / d_initvalu_31, float(2.5)));
koSRCa = koCa / kCaSR;
kiSRCa = kiCa * kCaSR;
RI = 1 - d_initvalu_14 - d_initvalu_15 - d_initvalu_16;
d_finavalu[offset_14] = (kim * RI - kiSRCa * d_initvalu_36 * d_initvalu_14)
- (koSRCa * pow(d_initvalu_36, 2) * d_initvalu_14 - kom * d_initvalu_15); // R
d_finavalu[offset_15] = (koSRCa * pow(d_initvalu_36, 2) * d_initvalu_14 - kom * d_initvalu_15)
- (kiSRCa * d_initvalu_36 * d_initvalu_15 - kim * d_initvalu_16); // O
d_finavalu[offset_16] = (kiSRCa * d_initvalu_36 * d_initvalu_15 - kim * d_initvalu_16)
- (kom * d_initvalu_16 - koSRCa * pow(d_initvalu_36, 2) * RI); // I
J_SRCarel = ks * d_initvalu_15 * (d_initvalu_31 - d_initvalu_36); // [mM/ms]
J_serca = pow(Q10SRCaP, Qpow) * Vmax_SRCaP
* (pow((d_initvalu_38 / Kmf), hillSRCaP) - pow((d_initvalu_31 / Kmr), hillSRCaP))
/ (1 + pow((d_initvalu_38 / Kmf), hillSRCaP) + pow((d_initvalu_31 / Kmr), hillSRCaP));
J_SRleak = 5.348e-6 * (d_initvalu_31 - d_initvalu_36); // [mM/ms]
// Sodium and Calcium Buffering
d_finavalu[offset_17] = kon_na * d_initvalu_32 * (Bmax_Naj - d_initvalu_17)
- koff_na * d_initvalu_17; // NaBj [mM/ms]
d_finavalu[offset_18] = kon_na * d_initvalu_33 * (Bmax_Nasl - d_initvalu_18)
- koff_na * d_initvalu_18; // NaBsl [mM/ms]
// Cytosolic Ca Buffers
d_finavalu[offset_19] = kon_tncl * d_initvalu_38 * (Bmax_TnClow - d_initvalu_19)
- koff_tncl * d_initvalu_19; // TnCL [mM/ms]
d_finavalu[offset_20] = kon_tnchca * d_initvalu_38
* (Bmax_TnChigh - d_initvalu_20 - d_initvalu_21) - koff_tnchca * d_initvalu_20; // TnCHc [mM/ms]
d_finavalu[offset_21] = kon_tnchmg * Mgi * (Bmax_TnChigh - d_initvalu_20 - d_initvalu_21)
- koff_tnchmg * d_initvalu_21; // TnCHm [mM/ms]
d_finavalu[offset_22] = 0; // CaM [mM/ms]
d_finavalu[offset_23] = kon_myoca * d_initvalu_38 * (Bmax_myosin - d_initvalu_23 - d_initvalu_24)
- koff_myoca * d_initvalu_23; // Myosin_ca [mM/ms]
d_finavalu[offset_24] = kon_myomg * Mgi * (Bmax_myosin - d_initvalu_23 - d_initvalu_24)
- koff_myomg * d_initvalu_24; // Myosin_mg [mM/ms]
d_finavalu[offset_25] = kon_sr * d_initvalu_38 * (Bmax_SR - d_initvalu_25)
- koff_sr * d_initvalu_25; // SRB [mM/ms]
J_CaB_cytosol = d_finavalu[offset_19] + d_finavalu[offset_20] + d_finavalu[offset_21]
+ d_finavalu[offset_22] + d_finavalu[offset_23] + d_finavalu[offset_24]
+ d_finavalu[offset_25];
// Junctional and SL Ca Buffers
d_finavalu[offset_26] = kon_sll * d_initvalu_36 * (Bmax_SLlowj - d_initvalu_26)
- koff_sll * d_initvalu_26; // SLLj [mM/ms]
d_finavalu[offset_27] = kon_sll * d_initvalu_37 * (Bmax_SLlowsl - d_initvalu_27)
- koff_sll * d_initvalu_27; // SLLsl [mM/ms]
d_finavalu[offset_28] = kon_slh * d_initvalu_36 * (Bmax_SLhighj - d_initvalu_28)
- koff_slh * d_initvalu_28; // SLHj [mM/ms]
d_finavalu[offset_29] = kon_slh * d_initvalu_37 * (Bmax_SLhighsl - d_initvalu_29)
- koff_slh * d_initvalu_29; // SLHsl [mM/ms]
J_CaB_junction = d_finavalu[offset_26] + d_finavalu[offset_28];
J_CaB_sl = d_finavalu[offset_27] + d_finavalu[offset_29];
// SR Ca Concentrations
d_finavalu[offset_30] = kon_csqn * d_initvalu_31 * (Bmax_Csqn - d_initvalu_30)
- koff_csqn * d_initvalu_30; // Csqn [mM/ms]
oneovervsr = 1 / Vsr;
d_finavalu[offset_31] = J_serca * Vmyo * oneovervsr - (J_SRleak * Vmyo * oneovervsr + J_SRCarel)
- d_finavalu[offset_30]; // Ca_sr [mM/ms] %Ratio 3 leak current
// Sodium Concentrations
I_Na_tot_junc = I_Na_junc + I_nabk_junc + 3 * I_ncx_junc + 3 * I_nak_junc + I_CaNa_junc;// [uA/uF]
I_Na_tot_sl = I_Na_sl + I_nabk_sl + 3 * I_ncx_sl + 3 * I_nak_sl + I_CaNa_sl; // [uA/uF]
d_finavalu[offset_32] = -I_Na_tot_junc * Cmem / (Vjunc * Frdy)
+ J_na_juncsl / Vjunc * (d_initvalu_33 - d_initvalu_32) - d_finavalu[offset_17];
oneovervsl = 1 / Vsl;
d_finavalu[offset_33] = -I_Na_tot_sl * Cmem * oneovervsl / Frdy
+ J_na_juncsl * oneovervsl * (d_initvalu_32 - d_initvalu_33)
+ J_na_slmyo * oneovervsl * (d_initvalu_34 - d_initvalu_33) - d_finavalu[offset_18];
d_finavalu[offset_34] = J_na_slmyo / Vmyo * (d_initvalu_33 - d_initvalu_34); // [mM/msec]
// Potassium Concentration
I_K_tot = I_to + I_kr + I_ks + I_ki - 2 * I_nak + I_CaK + I_kp; // [uA/uF]
d_finavalu[offset_35] = 0; // [mM/msec]
// Calcium Concentrations
I_Ca_tot_junc = I_Ca_junc + I_cabk_junc + I_pca_junc - 2 * I_ncx_junc; // [uA/uF]
I_Ca_tot_sl = I_Ca_sl + I_cabk_sl + I_pca_sl - 2 * I_ncx_sl; // [uA/uF]
d_finavalu[offset_36] = -I_Ca_tot_junc * Cmem / (Vjunc * 2 * Frdy)
+ J_ca_juncsl / Vjunc * (d_initvalu_37 - d_initvalu_36) - J_CaB_junction
+ (J_SRCarel) * Vsr / Vjunc + J_SRleak * Vmyo / Vjunc; // Ca_j
d_finavalu[offset_37] = -I_Ca_tot_sl * Cmem / (Vsl * 2 * Frdy)
+ J_ca_juncsl / Vsl * (d_initvalu_36 - d_initvalu_37)
+ J_ca_slmyo / Vsl * (d_initvalu_38 - d_initvalu_37) - J_CaB_sl; // Ca_sl
d_finavalu[offset_38] = -J_serca - J_CaB_cytosol
+ J_ca_slmyo / Vmyo * (d_initvalu_37 - d_initvalu_38);
// junc_sl=J_ca_juncsl/Vsl*(d_initvalu_36-d_initvalu_37);
// sl_junc=J_ca_juncsl/Vjunc*(d_initvalu_37-d_initvalu_36);
// sl_myo=J_ca_slmyo/Vsl*(d_initvalu_38-d_initvalu_37);
// myo_sl=J_ca_slmyo/Vmyo*(d_initvalu_37-d_initvalu_38);
// Simulation type
state = 1;
switch (state) {
case 0:
I_app = 0;
break;
case 1: // pace w/ current injection at cycleLength 'cycleLength'
if (fmod(timeinst, cycleLength) <= 5) {
I_app = 9.5;
} else {
I_app = 0.0;
}
break;
case 2:
V_hold = -55;
V_test = 0;
if (timeinst > 0.5 & timeinst < 200.5) {
V_clamp = V_test;
} else {
V_clamp = V_hold;
}
R_clamp = 0.04;
I_app = (V_clamp - d_initvalu_39) / R_clamp;
break;
}
// Membrane Potential
I_Na_tot = I_Na_tot_junc + I_Na_tot_sl; // [uA/uF]
I_Cl_tot = I_ClCa + I_Clbk; // [uA/uF]
I_Ca_tot = I_Ca_tot_junc + I_Ca_tot_sl;
I_tot = I_Na_tot + I_Cl_tot + I_Ca_tot + I_K_tot;
d_finavalu[offset_39] = -(I_tot - I_app);
// Set unused output values to 0 (MATLAB does it by default)
d_finavalu[offset_41] = 0;
d_finavalu[offset_42] = 0;
} | .text
.file "kernel_ecc.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0016c05c_00000000-6_kernel_ecc.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z10kernel_eccfPfS_iS_
.type _Z10kernel_eccfPfS_iS_, @function
_Z10kernel_eccfPfS_iS_:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z10kernel_eccfPfS_iS_, .-_Z10kernel_eccfPfS_iS_
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel_ecc.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <string.h>
int log2 (int i)
{
int r = 0;
while (i >>= 1) r++;
return r;
}
int bit_reverse (int w, int bits)
{
int r = 0;
for (int i = 0; i < bits; i++)
{
int bit = (w & (1 << i)) >> i;
r |= bit << (bits - i - 1);
}
return r;
}
__global__ void simple_histo (int* d_bins, const int* d_in, const int BIN_COUNT)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int bin = d_in[index] % BIN_COUNT;
atomicAdd(&(d_bins[bin]), 1);
}
int main (int argc, char **argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev);
cudaDeviceProp devProps;
if (cudaGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %zdB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 65536;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 16;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = bit_reverse(i, log2(ARRAY_SIZE));
}
int h_bins[BIN_COUNT];
memset(h_bins, 0, BIN_BYTES);
// declare GPU memory pointers
int *d_in, *d_bins;
// allocate GPU memory
cudaMalloc(&d_in, ARRAY_BYTES);
if (d_in == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
cudaMalloc(&d_bins, BIN_BYTES);
if (d_bins == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
// transfer the arrays to the GPU
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_bins, h_bins, BIN_BYTES, cudaMemcpyHostToDevice);
simple_histo<<<ARRAY_SIZE / 64, 64>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
cudaMemcpy(h_bins, d_bins, BIN_BYTES, cudaMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_bins);
return 0;
} | code for sm_80
Function : _Z12simple_histoPiPKii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IABS R9, c[0x0][0x170] ; /* 0x00005c0000097a13 */
/* 0x000fc80000000000 */
/*0090*/ I2F.RP R0, R9 ; /* 0x0000000900007306 */
/* 0x000e300000209400 */
/*00a0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00e0*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a05 */
/*00f0*/ IMAD R11, R6, R9, RZ ; /* 0x00000009060b7224 */
/* 0x000fca00078e02ff */
/*0100*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fe200078e0004 */
/*0110*/ IABS R6, R2 ; /* 0x0000000200067213 */
/* 0x004fe40000000000 */
/*0120*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f46270 */
/*0130*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0150*/ IMAD R0, R9, R5, R6 ; /* 0x0000000509007224 */
/* 0x000fe400078e0206 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*0170*/ ISETP.GT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04070 */
/*0180*/ @!P0 IADD3 R0, R0, -R9, RZ ; /* 0x8000000900008210 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f24070 */
/*01b0*/ @!P1 IMAD.IADD R0, R0, 0x1, -R9 ; /* 0x0000000100009824 */
/* 0x000fca00078e0a09 */
/*01c0*/ @!P2 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000a210 */
/* 0x000fe40007ffe1ff */
/*01d0*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff008a12 */
/* 0x000fca00078e33ff */
/*01e0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*01f0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <string.h>
int log2 (int i)
{
int r = 0;
while (i >>= 1) r++;
return r;
}
int bit_reverse (int w, int bits)
{
int r = 0;
for (int i = 0; i < bits; i++)
{
int bit = (w & (1 << i)) >> i;
r |= bit << (bits - i - 1);
}
return r;
}
__global__ void simple_histo (int* d_bins, const int* d_in, const int BIN_COUNT)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int bin = d_in[index] % BIN_COUNT;
atomicAdd(&(d_bins[bin]), 1);
}
int main (int argc, char **argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev);
cudaDeviceProp devProps;
if (cudaGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %zdB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 65536;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 16;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = bit_reverse(i, log2(ARRAY_SIZE));
}
int h_bins[BIN_COUNT];
memset(h_bins, 0, BIN_BYTES);
// declare GPU memory pointers
int *d_in, *d_bins;
// allocate GPU memory
cudaMalloc(&d_in, ARRAY_BYTES);
if (d_in == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
cudaMalloc(&d_bins, BIN_BYTES);
if (d_bins == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
// transfer the arrays to the GPU
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_bins, h_bins, BIN_BYTES, cudaMemcpyHostToDevice);
simple_histo<<<ARRAY_SIZE / 64, 64>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
cudaMemcpy(h_bins, d_bins, BIN_BYTES, cudaMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_bins);
return 0;
} | .file "tmpxft_000ccd4f_00000000-6_histo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4log2i
.type _Z4log2i, @function
_Z4log2i:
.LFB2057:
.cfi_startproc
endbr64
sarl %edi
je .L6
movl $0, %eax
.L5:
addl $1, %eax
sarl %edi
jne .L5
ret
.L6:
movl %edi, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z4log2i, .-_Z4log2i
.globl _Z11bit_reverseii
.type _Z11bit_reverseii, @function
_Z11bit_reverseii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L11
movl $0, %edx
movl $0, %r8d
movl $1, %r10d
leal -1(%rsi), %r9d
.L10:
movl %r10d, %eax
movl %edx, %ecx
sall %cl, %eax
andl %edi, %eax
sarl %cl, %eax
movl %r9d, %ecx
subl %edx, %ecx
sall %cl, %eax
orl %eax, %r8d
addl $1, %edx
cmpl %edx, %esi
jne .L10
.L8:
movl %r8d, %eax
ret
.L11:
movl $0, %r8d
jmp .L8
.cfi_endproc
.LFE2058:
.size _Z11bit_reverseii, .-_Z11bit_reverseii
.globl _Z36__device_stub__Z12simple_histoPiPKiiPiPKii
.type _Z36__device_stub__Z12simple_histoPiPKiiPiPKii, @function
_Z36__device_stub__Z12simple_histoPiPKiiPiPKii:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12simple_histoPiPKii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z12simple_histoPiPKiiPiPKii, .-_Z36__device_stub__Z12simple_histoPiPKiiPiPKii
.globl _Z12simple_histoPiPKii
.type _Z12simple_histoPiPKii, @function
_Z12simple_histoPiPKii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12simple_histoPiPKiiPiPKii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12simple_histoPiPKii, .-_Z12simple_histoPiPKii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "error: no devices supporting CUDA.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Using device %d:\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "%s; global mem: %zdB; compute v%d.%d; clock: %d kHz\n"
.section .rodata.str1.1
.LC3:
.string "Failed to alloc GPU mem\n"
.LC4:
.string "bin %d: count %d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -262144(%rsp), %r11
.cfi_def_cfa 11, 262168
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1176, %rsp
.cfi_def_cfa_offset 263344
movq %fs:40, %rax
movq %rax, 263304(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 4(%rsp)
je .L33
movl $0, %edi
call cudaSetDevice@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
je .L34
.L23:
movl $65536, %edi
call _Z4log2i
movl %eax, %ebp
movl $0, %ebx
.L24:
movl %ebp, %esi
movl %ebx, %edi
call _Z11bit_reverseii
movl %eax, 1152(%rsp,%rbx,4)
addq $1, %rbx
cmpq $65536, %rbx
jne .L24
pxor %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movaps %xmm0, 64(%rsp)
movaps %xmm0, 80(%rsp)
movaps %xmm0, 96(%rsp)
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
cmpq $0, 8(%rsp)
je .L35
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
cmpq $0, 16(%rsp)
je .L36
leaq 1152(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1024, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L27:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC4(%rip), %rbp
.L28:
movl 48(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L28
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 263304(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $263320, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 112(%rsp), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 263352
movl 468(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 263360
movl 492(%rsp), %r9d
movl 488(%rsp), %r8d
movl 416(%rsp), %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 263344
jmp .L23
.L35:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl $16, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z12simple_histoPiPKiiPiPKii
jmp .L27
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12simple_histoPiPKii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simple_histoPiPKii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
#include <cuda.h>
#include <string.h>
int log2 (int i)
{
int r = 0;
while (i >>= 1) r++;
return r;
}
int bit_reverse (int w, int bits)
{
int r = 0;
for (int i = 0; i < bits; i++)
{
int bit = (w & (1 << i)) >> i;
r |= bit << (bits - i - 1);
}
return r;
}
__global__ void simple_histo (int* d_bins, const int* d_in, const int BIN_COUNT)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int bin = d_in[index] % BIN_COUNT;
atomicAdd(&(d_bins[bin]), 1);
}
int main (int argc, char **argv)
{
int deviceCount;
cudaGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
cudaSetDevice(dev);
cudaDeviceProp devProps;
if (cudaGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %zdB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 65536;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 16;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = bit_reverse(i, log2(ARRAY_SIZE));
}
int h_bins[BIN_COUNT];
memset(h_bins, 0, BIN_BYTES);
// declare GPU memory pointers
int *d_in, *d_bins;
// allocate GPU memory
cudaMalloc(&d_in, ARRAY_BYTES);
if (d_in == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
cudaMalloc(&d_bins, BIN_BYTES);
if (d_bins == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
// transfer the arrays to the GPU
cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice);
cudaMemcpy(d_bins, h_bins, BIN_BYTES, cudaMemcpyHostToDevice);
simple_histo<<<ARRAY_SIZE / 64, 64>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
cudaMemcpy(h_bins, d_bins, BIN_BYTES, cudaMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
cudaFree(d_in);
cudaFree(d_bins);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
int log2 (int i)
{
int r = 0;
while (i >>= 1) r++;
return r;
}
int bit_reverse (int w, int bits)
{
int r = 0;
for (int i = 0; i < bits; i++)
{
int bit = (w & (1 << i)) >> i;
r |= bit << (bits - i - 1);
}
return r;
}
__global__ void simple_histo (int* d_bins, const int* d_in, const int BIN_COUNT)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int bin = d_in[index] % BIN_COUNT;
atomicAdd(&(d_bins[bin]), 1);
}
int main (int argc, char **argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev);
hipDeviceProp_t devProps;
if (hipGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %zdB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 65536;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 16;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = bit_reverse(i, log2(ARRAY_SIZE));
}
int h_bins[BIN_COUNT];
memset(h_bins, 0, BIN_BYTES);
// declare GPU memory pointers
int *d_in, *d_bins;
// allocate GPU memory
hipMalloc(&d_in, ARRAY_BYTES);
if (d_in == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
hipMalloc(&d_bins, BIN_BYTES);
if (d_bins == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
// transfer the arrays to the GPU
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_bins, h_bins, BIN_BYTES, hipMemcpyHostToDevice);
simple_histo<<<ARRAY_SIZE / 64, 64>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
hipMemcpy(h_bins, d_bins, BIN_BYTES, hipMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
hipFree(d_in);
hipFree(d_bins);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
int log2 (int i)
{
int r = 0;
while (i >>= 1) r++;
return r;
}
int bit_reverse (int w, int bits)
{
int r = 0;
for (int i = 0; i < bits; i++)
{
int bit = (w & (1 << i)) >> i;
r |= bit << (bits - i - 1);
}
return r;
}
__global__ void simple_histo (int* d_bins, const int* d_in, const int BIN_COUNT)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int bin = d_in[index] % BIN_COUNT;
atomicAdd(&(d_bins[bin]), 1);
}
int main (int argc, char **argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev);
hipDeviceProp_t devProps;
if (hipGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %zdB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 65536;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 16;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = bit_reverse(i, log2(ARRAY_SIZE));
}
int h_bins[BIN_COUNT];
memset(h_bins, 0, BIN_BYTES);
// declare GPU memory pointers
int *d_in, *d_bins;
// allocate GPU memory
hipMalloc(&d_in, ARRAY_BYTES);
if (d_in == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
hipMalloc(&d_bins, BIN_BYTES);
if (d_bins == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
// transfer the arrays to the GPU
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_bins, h_bins, BIN_BYTES, hipMemcpyHostToDevice);
simple_histo<<<ARRAY_SIZE / 64, 64>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
hipMemcpy(h_bins, d_bins, BIN_BYTES, hipMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
hipFree(d_in);
hipFree(d_bins);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12simple_histoPiPKii
.globl _Z12simple_histoPiPKii
.p2align 8
.type _Z12simple_histoPiPKii,@function
_Z12simple_histoPiPKii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s1, s0, 31
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_add_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s0, s1
s_sub_i32 s1, 0, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_cvt_f32_u32_e32 v1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v0
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_add_nc_u32 v0, v0, v3
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v3
v_mul_lo_u32 v2, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_dual_mov_b32 v2, 1 :: v_dual_add_nc_u32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v1, v1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v1
v_subrev_nc_u32_e32 v1, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_subrev_nc_u32_e32 v1, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12simple_histoPiPKii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12simple_histoPiPKii, .Lfunc_end0-_Z12simple_histoPiPKii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12simple_histoPiPKii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12simple_histoPiPKii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <string.h>
int log2 (int i)
{
int r = 0;
while (i >>= 1) r++;
return r;
}
int bit_reverse (int w, int bits)
{
int r = 0;
for (int i = 0; i < bits; i++)
{
int bit = (w & (1 << i)) >> i;
r |= bit << (bits - i - 1);
}
return r;
}
__global__ void simple_histo (int* d_bins, const int* d_in, const int BIN_COUNT)
{
int index = threadIdx.x + blockDim.x * blockIdx.x;
int bin = d_in[index] % BIN_COUNT;
atomicAdd(&(d_bins[bin]), 1);
}
int main (int argc, char **argv)
{
int deviceCount;
hipGetDeviceCount(&deviceCount);
if (deviceCount == 0) {
fprintf(stderr, "error: no devices supporting CUDA.\n");
exit(EXIT_FAILURE);
}
int dev = 0;
hipSetDevice(dev);
hipDeviceProp_t devProps;
if (hipGetDeviceProperties(&devProps, dev) == 0)
{
printf("Using device %d:\n", dev);
printf("%s; global mem: %zdB; compute v%d.%d; clock: %d kHz\n",
devProps.name, (int)devProps.totalGlobalMem,
(int)devProps.major, (int)devProps.minor,
(int)devProps.clockRate);
}
const int ARRAY_SIZE = 65536;
const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
const int BIN_COUNT = 16;
const int BIN_BYTES = BIN_COUNT * sizeof(int);
int h_in[ARRAY_SIZE];
for (int i = 0; i < ARRAY_SIZE; i++) {
h_in[i] = bit_reverse(i, log2(ARRAY_SIZE));
}
int h_bins[BIN_COUNT];
memset(h_bins, 0, BIN_BYTES);
// declare GPU memory pointers
int *d_in, *d_bins;
// allocate GPU memory
hipMalloc(&d_in, ARRAY_BYTES);
if (d_in == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
hipMalloc(&d_bins, BIN_BYTES);
if (d_bins == NULL) {
fprintf(stderr, "Failed to alloc GPU mem\n");
exit(EXIT_FAILURE);
}
// transfer the arrays to the GPU
hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice);
hipMemcpy(d_bins, h_bins, BIN_BYTES, hipMemcpyHostToDevice);
simple_histo<<<ARRAY_SIZE / 64, 64>>>(d_bins, d_in, BIN_COUNT);
// copy back the sum from GPU
hipMemcpy(h_bins, d_bins, BIN_BYTES, hipMemcpyDeviceToHost);
for(int i = 0; i < BIN_COUNT; i++) {
printf("bin %d: count %d\n", i, h_bins[i]);
}
// free GPU memory allocation
hipFree(d_in);
hipFree(d_bins);
return 0;
} | .text
.file "histo.hip"
.globl _Z4log2i # -- Begin function _Z4log2i
.p2align 4, 0x90
.type _Z4log2i,@function
_Z4log2i: # @_Z4log2i
.cfi_startproc
# %bb.0:
xorl %eax, %eax
cmpl $2, %edi
jb .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
sarl %edi
incl %eax
cmpl $1, %edi
ja .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z4log2i, .Lfunc_end0-_Z4log2i
.cfi_endproc
# -- End function
.globl _Z11bit_reverseii # -- Begin function _Z11bit_reverseii
.p2align 4, 0x90
.type _Z11bit_reverseii,@function
_Z11bit_reverseii: # @_Z11bit_reverseii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_1
# %bb.3: # %.lr.ph.preheader
decl %esi
xorl %eax, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, %r8d
movl %edx, %ecx
shll %cl, %r8d
andl %edi, %r8d
sarl %cl, %r8d
movl %esi, %ecx
shll %cl, %r8d
orl %r8d, %eax
incl %edx
addl $-1, %esi
jb .LBB1_4
# %bb.2: # %._crit_edge
retq
.LBB1_1:
xorl %eax, %eax
retq
.Lfunc_end1:
.size _Z11bit_reverseii, .Lfunc_end1-_Z11bit_reverseii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__simple_histoPiPKii # -- Begin function _Z27__device_stub__simple_histoPiPKii
.p2align 4, 0x90
.type _Z27__device_stub__simple_histoPiPKii,@function
_Z27__device_stub__simple_histoPiPKii: # @_Z27__device_stub__simple_histoPiPKii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12simple_histoPiPKii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z27__device_stub__simple_histoPiPKii, .Lfunc_end2-_Z27__device_stub__simple_histoPiPKii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $263808, %rsp # imm = 0x40680
.cfi_def_cfa_offset 263824
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 24(%rsp)
je .LBB3_1
# %bb.3:
xorl %edi, %edi
callq hipSetDevice
leaq 192(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movl 552(%rsp), %ecx
movl 556(%rsp), %r8d
movl 480(%rsp), %edx
movl 540(%rsp), %r9d
leaq 192(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB3_5:
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_6: # %.lr.ph.i.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_7 Depth 2
movl $15, %eax
xorl %edi, %edi
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i14
# Parent Loop BB3_6 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, %r8d
movl %edx, %ecx
shll %cl, %r8d
andl %esi, %r8d
shrl %cl, %r8d
movl %eax, %ecx
shll %cl, %r8d
orl %r8d, %edi
incl %edx
decl %eax
cmpl $16, %edx
jne .LBB3_7
# %bb.8: # %_Z11bit_reverseii.exit
# in Loop: Header=BB3_6 Depth=1
movl %edi, 1664(%rsp,%rsi,4)
incq %rsi
cmpq $65536, %rsi # imm = 0x10000
jne .LBB3_6
# %bb.9:
xorps %xmm0, %xmm0
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
cmpq $0, 16(%rsp)
je .LBB3_10
# %bb.11:
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
cmpq $0, 8(%rsp)
je .LBB3_10
# %bb.12:
movq 16(%rsp), %rdi
leaq 1664(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967360, %rdx # imm = 0x100000040
leaq 960(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $16, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12simple_histoPiPKii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_14:
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_15: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rbx,4), %edx
movl $.L.str.4, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB3_15
# %bb.16:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $263808, %rsp # imm = 0x40680
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_10:
.cfi_def_cfa_offset 263824
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $24, %esi
jmp .LBB3_2
.LBB3_1:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $35, %esi
.LBB3_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simple_histoPiPKii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12simple_histoPiPKii,@object # @_Z12simple_histoPiPKii
.section .rodata,"a",@progbits
.globl _Z12simple_histoPiPKii
.p2align 3, 0x0
_Z12simple_histoPiPKii:
.quad _Z27__device_stub__simple_histoPiPKii
.size _Z12simple_histoPiPKii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error: no devices supporting CUDA.\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Using device %d:\n"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to alloc GPU mem\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "bin %d: count %d\n"
.size .L.str.4, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12simple_histoPiPKii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__simple_histoPiPKii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12simple_histoPiPKii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12simple_histoPiPKii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0050*/ IMAD R2, R3, c[0x0][0x0], R2 ; /* 0x0000000003027a24 */
/* 0x001fca00078e0202 */
/*0060*/ IMAD.WIDE R2, R2, R7, c[0x0][0x168] ; /* 0x00005a0002027625 */
/* 0x000fcc00078e0207 */
/*0070*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IABS R9, c[0x0][0x170] ; /* 0x00005c0000097a13 */
/* 0x000fc80000000000 */
/*0090*/ I2F.RP R0, R9 ; /* 0x0000000900007306 */
/* 0x000e300000209400 */
/*00a0*/ MUFU.RCP R0, R0 ; /* 0x0000000000007308 */
/* 0x001e240000001000 */
/*00b0*/ IADD3 R4, R0, 0xffffffe, RZ ; /* 0x0ffffffe00047810 */
/* 0x001fcc0007ffe0ff */
/*00c0*/ F2I.FTZ.U32.TRUNC.NTZ R5, R4 ; /* 0x0000000400057305 */
/* 0x000064000021f000 */
/*00d0*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x001fe200000001ff */
/*00e0*/ IMAD.MOV R6, RZ, RZ, -R5 ; /* 0x000000ffff067224 */
/* 0x002fc800078e0a05 */
/*00f0*/ IMAD R11, R6, R9, RZ ; /* 0x00000009060b7224 */
/* 0x000fca00078e02ff */
/*0100*/ IMAD.HI.U32 R5, R5, R11, R4 ; /* 0x0000000b05057227 */
/* 0x000fe200078e0004 */
/*0110*/ IABS R6, R2 ; /* 0x0000000200067213 */
/* 0x004fe40000000000 */
/*0120*/ ISETP.GE.AND P2, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x000fc60003f46270 */
/*0130*/ IMAD.HI.U32 R5, R5, R6, RZ ; /* 0x0000000605057227 */
/* 0x000fc800078e00ff */
/*0140*/ IMAD.MOV R5, RZ, RZ, -R5 ; /* 0x000000ffff057224 */
/* 0x000fc800078e0a05 */
/*0150*/ IMAD R0, R9, R5, R6 ; /* 0x0000000509007224 */
/* 0x000fe400078e0206 */
/*0160*/ IMAD.MOV.U32 R5, RZ, RZ, 0x1 ; /* 0x00000001ff057424 */
/* 0x000fc600078e00ff */
/*0170*/ ISETP.GT.U32.AND P0, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f04070 */
/*0180*/ @!P0 IADD3 R0, R0, -R9, RZ ; /* 0x8000000900008210 */
/* 0x000fe40007ffe0ff */
/*0190*/ ISETP.NE.AND P0, PT, RZ, c[0x0][0x170], PT ; /* 0x00005c00ff007a0c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.GT.U32.AND P1, PT, R9, R0, PT ; /* 0x000000000900720c */
/* 0x000fda0003f24070 */
/*01b0*/ @!P1 IMAD.IADD R0, R0, 0x1, -R9 ; /* 0x0000000100009824 */
/* 0x000fca00078e0a09 */
/*01c0*/ @!P2 IADD3 R0, -R0, RZ, RZ ; /* 0x000000ff0000a210 */
/* 0x000fe40007ffe1ff */
/*01d0*/ @!P0 LOP3.LUT R0, RZ, c[0x0][0x170], RZ, 0x33, !PT ; /* 0x00005c00ff008a12 */
/* 0x000fca00078e33ff */
/*01e0*/ IMAD.WIDE R2, R0, R7, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fca00078e0207 */
/*01f0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x000fe2000c10e184 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12simple_histoPiPKii
.globl _Z12simple_histoPiPKii
.p2align 8
.type _Z12simple_histoPiPKii,@function
_Z12simple_histoPiPKii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x24
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b32 s0, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_ashr_i32 s1, s0, 31
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_add_i32 s0, s0, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s0, s0, s1
s_sub_i32 s1, 0, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
global_load_b32 v0, v[0:1], off
v_cvt_f32_u32_e32 v1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v1, v1
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v0
s_waitcnt_depctr 0xfff
v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_add_nc_u32 v0, v0, v3
v_cvt_u32_f32_e32 v1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v0, v0, v3
v_mul_lo_u32 v2, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v2
v_dual_mov_b32 v2, 1 :: v_dual_add_nc_u32 v1, v1, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v1, v0, v1
v_mul_lo_u32 v1, v1, s0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v1
v_subrev_nc_u32_e32 v1, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_subrev_nc_u32_e32 v1, s0, v0
v_cmp_le_u32_e32 vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, v0, v1, vcc_lo
v_xor_b32_e32 v0, v0, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v0, v0, v3
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_co_u32 v0, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
global_atomic_add_u32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12simple_histoPiPKii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12simple_histoPiPKii, .Lfunc_end0-_Z12simple_histoPiPKii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12simple_histoPiPKii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12simple_histoPiPKii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ccd4f_00000000-6_histo.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z4log2i
.type _Z4log2i, @function
_Z4log2i:
.LFB2057:
.cfi_startproc
endbr64
sarl %edi
je .L6
movl $0, %eax
.L5:
addl $1, %eax
sarl %edi
jne .L5
ret
.L6:
movl %edi, %eax
ret
.cfi_endproc
.LFE2057:
.size _Z4log2i, .-_Z4log2i
.globl _Z11bit_reverseii
.type _Z11bit_reverseii, @function
_Z11bit_reverseii:
.LFB2058:
.cfi_startproc
endbr64
testl %esi, %esi
jle .L11
movl $0, %edx
movl $0, %r8d
movl $1, %r10d
leal -1(%rsi), %r9d
.L10:
movl %r10d, %eax
movl %edx, %ecx
sall %cl, %eax
andl %edi, %eax
sarl %cl, %eax
movl %r9d, %ecx
subl %edx, %ecx
sall %cl, %eax
orl %eax, %r8d
addl $1, %edx
cmpl %edx, %esi
jne .L10
.L8:
movl %r8d, %eax
ret
.L11:
movl $0, %r8d
jmp .L8
.cfi_endproc
.LFE2058:
.size _Z11bit_reverseii, .-_Z11bit_reverseii
.globl _Z36__device_stub__Z12simple_histoPiPKiiPiPKii
.type _Z36__device_stub__Z12simple_histoPiPKiiPiPKii, @function
_Z36__device_stub__Z12simple_histoPiPKiiPiPKii:
.LFB2084:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12simple_histoPiPKii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z36__device_stub__Z12simple_histoPiPKiiPiPKii, .-_Z36__device_stub__Z12simple_histoPiPKiiPiPKii
.globl _Z12simple_histoPiPKii
.type _Z12simple_histoPiPKii, @function
_Z12simple_histoPiPKii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z12simple_histoPiPKiiPiPKii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z12simple_histoPiPKii, .-_Z12simple_histoPiPKii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "error: no devices supporting CUDA.\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string "Using device %d:\n"
.section .rodata.str1.8
.align 8
.LC2:
.string "%s; global mem: %zdB; compute v%d.%d; clock: %d kHz\n"
.section .rodata.str1.1
.LC3:
.string "Failed to alloc GPU mem\n"
.LC4:
.string "bin %d: count %d\n"
.text
.globl main
.type main, @function
main:
.LFB2059:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
leaq -262144(%rsp), %r11
.cfi_def_cfa 11, 262168
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $1176, %rsp
.cfi_def_cfa_offset 263344
movq %fs:40, %rax
movq %rax, 263304(%rsp)
xorl %eax, %eax
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
cmpl $0, 4(%rsp)
je .L33
movl $0, %edi
call cudaSetDevice@PLT
leaq 112(%rsp), %rdi
movl $0, %esi
call cudaGetDeviceProperties_v2@PLT
testl %eax, %eax
je .L34
.L23:
movl $65536, %edi
call _Z4log2i
movl %eax, %ebp
movl $0, %ebx
.L24:
movl %ebp, %esi
movl %ebx, %edi
call _Z11bit_reverseii
movl %eax, 1152(%rsp,%rbx,4)
addq $1, %rbx
cmpq $65536, %rbx
jne .L24
pxor %xmm0, %xmm0
movaps %xmm0, 48(%rsp)
movaps %xmm0, 64(%rsp)
movaps %xmm0, 80(%rsp)
movaps %xmm0, 96(%rsp)
leaq 8(%rsp), %rdi
movl $262144, %esi
call cudaMalloc@PLT
cmpq $0, 8(%rsp)
je .L35
leaq 16(%rsp), %rdi
movl $64, %esi
call cudaMalloc@PLT
cmpq $0, 16(%rsp)
je .L36
leaq 1152(%rsp), %rsi
movl $1, %ecx
movl $262144, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $64, %edx
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $64, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1024, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L37
.L27:
leaq 48(%rsp), %rdi
movl $2, %ecx
movl $64, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %ebx
leaq .LC4(%rip), %rbp
.L28:
movl 48(%rsp,%rbx,4), %ecx
movl %ebx, %edx
movq %rbp, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpq $16, %rbx
jne .L28
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 263304(%rsp), %rax
subq %fs:40, %rax
jne .L38
movl $0, %eax
addq $263320, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.L33:
.cfi_restore_state
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L34:
movl $0, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 112(%rsp), %rdx
subq $8, %rsp
.cfi_def_cfa_offset 263352
movl 468(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 263360
movl 492(%rsp), %r9d
movl 488(%rsp), %r8d
movl 416(%rsp), %ecx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $16, %rsp
.cfi_def_cfa_offset 263344
jmp .L23
.L35:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl $16, %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z12simple_histoPiPKiiPiPKii
jmp .L27
.L38:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size main, .-main
.section .rodata.str1.1
.LC5:
.string "_Z12simple_histoPiPKii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z12simple_histoPiPKii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histo.hip"
.globl _Z4log2i # -- Begin function _Z4log2i
.p2align 4, 0x90
.type _Z4log2i,@function
_Z4log2i: # @_Z4log2i
.cfi_startproc
# %bb.0:
xorl %eax, %eax
cmpl $2, %edi
jb .LBB0_3
# %bb.1: # %.lr.ph.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
sarl %edi
incl %eax
cmpl $1, %edi
ja .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z4log2i, .Lfunc_end0-_Z4log2i
.cfi_endproc
# -- End function
.globl _Z11bit_reverseii # -- Begin function _Z11bit_reverseii
.p2align 4, 0x90
.type _Z11bit_reverseii,@function
_Z11bit_reverseii: # @_Z11bit_reverseii
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB1_1
# %bb.3: # %.lr.ph.preheader
decl %esi
xorl %eax, %eax
xorl %edx, %edx
.p2align 4, 0x90
.LBB1_4: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl $1, %r8d
movl %edx, %ecx
shll %cl, %r8d
andl %edi, %r8d
sarl %cl, %r8d
movl %esi, %ecx
shll %cl, %r8d
orl %r8d, %eax
incl %edx
addl $-1, %esi
jb .LBB1_4
# %bb.2: # %._crit_edge
retq
.LBB1_1:
xorl %eax, %eax
retq
.Lfunc_end1:
.size _Z11bit_reverseii, .Lfunc_end1-_Z11bit_reverseii
.cfi_endproc
# -- End function
.globl _Z27__device_stub__simple_histoPiPKii # -- Begin function _Z27__device_stub__simple_histoPiPKii
.p2align 4, 0x90
.type _Z27__device_stub__simple_histoPiPKii,@function
_Z27__device_stub__simple_histoPiPKii: # @_Z27__device_stub__simple_histoPiPKii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12simple_histoPiPKii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z27__device_stub__simple_histoPiPKii, .Lfunc_end2-_Z27__device_stub__simple_histoPiPKii
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $263808, %rsp # imm = 0x40680
.cfi_def_cfa_offset 263824
.cfi_offset %rbx, -16
leaq 24(%rsp), %rdi
callq hipGetDeviceCount
cmpl $0, 24(%rsp)
je .LBB3_1
# %bb.3:
xorl %edi, %edi
callq hipSetDevice
leaq 192(%rsp), %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movl $.L.str.1, %edi
xorl %esi, %esi
xorl %eax, %eax
callq printf
movl 552(%rsp), %ecx
movl 556(%rsp), %r8d
movl 480(%rsp), %edx
movl 540(%rsp), %r9d
leaq 192(%rsp), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
.LBB3_5:
xorl %esi, %esi
.p2align 4, 0x90
.LBB3_6: # %.lr.ph.i.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_7 Depth 2
movl $15, %eax
xorl %edi, %edi
xorl %edx, %edx
.p2align 4, 0x90
.LBB3_7: # %.lr.ph.i14
# Parent Loop BB3_6 Depth=1
# => This Inner Loop Header: Depth=2
movl $1, %r8d
movl %edx, %ecx
shll %cl, %r8d
andl %esi, %r8d
shrl %cl, %r8d
movl %eax, %ecx
shll %cl, %r8d
orl %r8d, %edi
incl %edx
decl %eax
cmpl $16, %edx
jne .LBB3_7
# %bb.8: # %_Z11bit_reverseii.exit
# in Loop: Header=BB3_6 Depth=1
movl %edi, 1664(%rsp,%rsi,4)
incq %rsi
cmpq $65536, %rsi # imm = 0x10000
jne .LBB3_6
# %bb.9:
xorps %xmm0, %xmm0
movaps %xmm0, 176(%rsp)
movaps %xmm0, 160(%rsp)
movaps %xmm0, 144(%rsp)
movaps %xmm0, 128(%rsp)
leaq 16(%rsp), %rdi
movl $262144, %esi # imm = 0x40000
callq hipMalloc
cmpq $0, 16(%rsp)
je .LBB3_10
# %bb.11:
leaq 8(%rsp), %rdi
movl $64, %esi
callq hipMalloc
cmpq $0, 8(%rsp)
je .LBB3_10
# %bb.12:
movq 16(%rsp), %rdi
leaq 1664(%rsp), %rsi
movl $262144, %edx # imm = 0x40000
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
leaq 128(%rsp), %rsi
movl $64, %edx
movl $1, %ecx
callq hipMemcpy
movabsq $4294967360, %rdx # imm = 0x100000040
leaq 960(%rdx), %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_14
# %bb.13:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movq %rcx, 80(%rsp)
movl $16, 28(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z12simple_histoPiPKii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_14:
movq 8(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $64, %edx
movl $2, %ecx
callq hipMemcpy
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB3_15: # =>This Inner Loop Header: Depth=1
movl 128(%rsp,%rbx,4), %edx
movl $.L.str.4, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
incq %rbx
cmpq $16, %rbx
jne .LBB3_15
# %bb.16:
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $263808, %rsp # imm = 0x40680
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB3_10:
.cfi_def_cfa_offset 263824
movq stderr(%rip), %rcx
movl $.L.str.3, %edi
movl $24, %esi
jmp .LBB3_2
.LBB3_1:
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $35, %esi
.LBB3_2:
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12simple_histoPiPKii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12simple_histoPiPKii,@object # @_Z12simple_histoPiPKii
.section .rodata,"a",@progbits
.globl _Z12simple_histoPiPKii
.p2align 3, 0x0
_Z12simple_histoPiPKii:
.quad _Z27__device_stub__simple_histoPiPKii
.size _Z12simple_histoPiPKii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "error: no devices supporting CUDA.\n"
.size .L.str, 36
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Using device %d:\n"
.size .L.str.1, 18
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "%s
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to alloc GPU mem\n"
.size .L.str.3, 25
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "bin %d: count %d\n"
.size .L.str.4, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z12simple_histoPiPKii"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__simple_histoPiPKii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12simple_histoPiPKii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /***************************************************
* Module that multiply a matrix by the transpose of other
* Author: Alonso Vidales <alonso.vidales@tras2.es>
*
* To be compiled with nvcc -ptx matrix_mult_trans.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_mult_trans.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixMulTrans(double* C, double* A, double* B, int wA, int resW, int resH, int resultWidth, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * resultWidth + x;
//printf("Thread %d - %d: %d. Final: x: %d y: %d Size: %d\n", threadIdx.x, threadIdx.y, resultPos, x, y, resultSize);
if (resultPos < resultSize && x < resultWidth) {
// value stores the element that is
// computed by the thread
double value = 0;
for (int i = 0; i < wA; ++i)
{
value += A[y * wA + i] * B[x * wA + i];
//printf("Pos %d - %d, thread %d - %d : pos: %d %d H: %d Pos: %d Val: %f\n", blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, x, y, resultWidth, resultPos, value);
}
// Write the matrix to device memory each
// thread writes one element
C[resultPos] = value;
}
}
#ifdef __cplusplus
}
#endif | code for sm_80
Function : matrixMulTrans
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x001fc400078e0203 */
/*0060*/ IMAD R3, R2, c[0x0][0x180], R5 ; /* 0x0000600002037a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R2, R3, c[0x0][0x184], R0 ; /* 0x0000610003027a24 */
/* 0x000fca00078e0200 */
/*0080*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x188], PT ; /* 0x0000620002007a0c */
/* 0x000fc80003f06270 */
/*0090*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x184], P0 ; /* 0x0000610000007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fc6000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbb0 ; /* 0x00000ab000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R5, R4.reuse, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x040fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0120*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*0130*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fda0003f06070 */
/*0150*/ @!P0 BRA 0xa20 ; /* 0x000008c000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0180*/ IMAD R6, R3, c[0x0][0x178], RZ ; /* 0x00005e0003067a24 */
/* 0x000fe200078e02ff */
/*0190*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*01a0*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01b0*/ IMAD R25, R0, c[0x0][0x178], RZ ; /* 0x00005e0000197a24 */
/* 0x000fe200078e02ff */
/*01c0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*01d0*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fcc00078e0207 */
/*01f0*/ @!P0 BRA 0x890 ; /* 0x0000069000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0220*/ @!P1 BRA 0x610 ; /* 0x000003e000009947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*0250*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x001ea2000c1e1b00 */
/*0260*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fc6000f8e00ff */
/*0270*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee2000c1e1b00 */
/*0280*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fc600078e0208 */
/*0290*/ LDG.E.64 R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000f28000c1e1b00 */
/*02a0*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea8000c1e1b00 */
/*02b0*/ LDG.E.64 R12, [R8.64+0x8] ; /* 0x00000804080c7981 */
/* 0x000ee8000c1e1b00 */
/*02c0*/ LDG.E.64 R14, [R8.64+0x10] ; /* 0x00001004080e7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ DFMA R20, R22, R10, R20 ; /* 0x0000000a1614722b */
/* 0x0060c60000000014 */
/*02e0*/ LDG.E.64 R22, [R6.64+0x18] ; /* 0x0000180406167981 */
/* 0x001ea8000c1e1b00 */
/*02f0*/ LDG.E.64 R10, [R8.64+0x18] ; /* 0x00001804080a7981 */
/* 0x000ea2000c1e1b00 */
/*0300*/ DFMA R16, R12, R16, R20 ; /* 0x000000100c10722b */
/* 0x0081060000000014 */
/*0310*/ LDG.E.64 R20, [R6.64+0x20] ; /* 0x0000200406147981 */
/* 0x001ee8000c1e1b00 */
/*0320*/ LDG.E.64 R12, [R8.64+0x20] ; /* 0x00002004080c7981 */
/* 0x000ee2000c1e1b00 */
/*0330*/ DFMA R18, R14, R18, R16 ; /* 0x000000120e12722b */
/* 0x0100860000000010 */
/*0340*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001f28000c1e1b00 */
/*0350*/ LDG.E.64 R16, [R8.64+0x28] ; /* 0x0000280408107981 */
/* 0x000f22000c1e1b00 */
/*0360*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x0040c60000000012 */
/*0370*/ LDG.E.64 R18, [R6.64+0x30] ; /* 0x0000300406127981 */
/* 0x001ea8000c1e1b00 */
/*0380*/ LDG.E.64 R10, [R8.64+0x30] ; /* 0x00003004080a7981 */
/* 0x000ea2000c1e1b00 */
/*0390*/ DFMA R20, R12, R20, R22 ; /* 0x000000140c14722b */
/* 0x0081060000000016 */
/*03a0*/ LDG.E.64 R22, [R6.64+0x38] ; /* 0x0000380406167981 */
/* 0x001ee8000c1e1b00 */
/*03b0*/ LDG.E.64 R12, [R8.64+0x38] ; /* 0x00003804080c7981 */
/* 0x000ee2000c1e1b00 */
/*03c0*/ DFMA R14, R16, R14, R20 ; /* 0x0000000e100e722b */
/* 0x0100860000000014 */
/*03d0*/ LDG.E.64 R20, [R6.64+0x40] ; /* 0x0000400406147981 */
/* 0x001f28000c1e1b00 */
/*03e0*/ LDG.E.64 R16, [R8.64+0x40] ; /* 0x0000400408107981 */
/* 0x000f22000c1e1b00 */
/*03f0*/ DFMA R18, R10, R18, R14 ; /* 0x000000120a12722b */
/* 0x0040c6000000000e */
/*0400*/ LDG.E.64 R14, [R6.64+0x48] ; /* 0x00004804060e7981 */
/* 0x001ea8000c1e1b00 */
/*0410*/ LDG.E.64 R10, [R8.64+0x48] ; /* 0x00004804080a7981 */
/* 0x000ea2000c1e1b00 */
/*0420*/ DFMA R22, R12, R22, R18 ; /* 0x000000160c16722b */
/* 0x0081060000000012 */
/*0430*/ LDG.E.64 R18, [R6.64+0x50] ; /* 0x0000500406127981 */
/* 0x001ee8000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R8.64+0x50] ; /* 0x00005004080c7981 */
/* 0x000ee2000c1e1b00 */
/*0450*/ DFMA R20, R16, R20, R22 ; /* 0x000000141014722b */
/* 0x0100860000000016 */
/*0460*/ LDG.E.64 R22, [R6.64+0x58] ; /* 0x0000580406167981 */
/* 0x001f28000c1e1b00 */
/*0470*/ LDG.E.64 R16, [R8.64+0x58] ; /* 0x0000580408107981 */
/* 0x000f22000c1e1b00 */
/*0480*/ DFMA R14, R10, R14, R20 ; /* 0x0000000e0a0e722b */
/* 0x0040c60000000014 */
/*0490*/ LDG.E.64 R10, [R6.64+0x60] ; /* 0x00006004060a7981 */
/* 0x001ea8000c1e1b00 */
/*04a0*/ LDG.E.64 R20, [R8.64+0x60] ; /* 0x0000600408147981 */
/* 0x000ea2000c1e1b00 */
/*04b0*/ DFMA R18, R12, R18, R14 ; /* 0x000000120c12722b */
/* 0x008106000000000e */
/*04c0*/ LDG.E.64 R12, [R6.64+0x68] ; /* 0x00006804060c7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R14, [R8.64+0x68] ; /* 0x00006804080e7981 */
/* 0x000ee2000c1e1b00 */
/*04e0*/ DFMA R22, R16, R22, R18 ; /* 0x000000161016722b */
/* 0x0100860000000012 */
/*04f0*/ LDG.E.64 R16, [R6.64+0x70] ; /* 0x0000700406107981 */
/* 0x001f28000c1e1b00 */
/*0500*/ LDG.E.64 R18, [R8.64+0x70] ; /* 0x0000700408127981 */
/* 0x000f22000c1e1b00 */
/*0510*/ DFMA R10, R20, R10, R22 ; /* 0x0000000a140a722b */
/* 0x0040c60000000016 */
/*0520*/ LDG.E.64 R20, [R6.64+0x78] ; /* 0x0000780406147981 */
/* 0x0010a8000c1e1b00 */
/*0530*/ LDG.E.64 R22, [R8.64+0x78] ; /* 0x0000780408167981 */
/* 0x000ea2000c1e1b00 */
/*0540*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe20007ffe0ff */
/*0550*/ DFMA R10, R14, R12, R10 ; /* 0x0000000c0e0a722b */
/* 0x008306000000000a */
/*0560*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0570*/ IADD3 R12, P2, R6, 0x80, RZ ; /* 0x00000080060c7810 */
/* 0x002fe20007f5e0ff */
/*0580*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0590*/ DFMA R10, R18, R16, R10 ; /* 0x00000010120a722b */
/* 0x010ea4000000000a */
/*05a0*/ IADD3.X R13, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fe200017fe4ff */
/*05b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05c0*/ IADD3 R24, R24, 0x10, RZ ; /* 0x0000001018187810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x001fe400078e000c */
/*05e0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*05f0*/ DFMA R20, R22, R20, R10 ; /* 0x000000141614722b */
/* 0x004062000000000a */
/*0600*/ @P1 BRA 0x240 ; /* 0xfffffc3000001947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0620*/ @!P1 BRA 0x870 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0630*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0640*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*0650*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea6000c1e1b00 */
/*0660*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fe200078e0208 */
/*0670*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*0680*/ LDG.E.64 R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ea8000c1e1b00 */
/*0690*/ LDG.E.64 R10, [R8.64+0x8] ; /* 0x00000804080a7981 */
/* 0x001ee8000c1e1b00 */
/*06a0*/ LDG.E.64 R22, [R6.64+0x10] ; /* 0x0000100406167981 */
/* 0x000f28000c1e1b00 */
/*06b0*/ LDG.E.64 R14, [R8.64+0x10] ; /* 0x00001004080e7981 */
/* 0x000f22000c1e1b00 */
/*06c0*/ DFMA R12, R18, R12, R20 ; /* 0x0000000c120c722b */
/* 0x0060c60000000014 */
/*06d0*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x001ea8000c1e1b00 */
/*06e0*/ LDG.E.64 R20, [R8.64+0x18] ; /* 0x0000180408147981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ DFMA R16, R10, R16, R12 ; /* 0x000000100a10722b */
/* 0x008106000000000c */
/*0700*/ LDG.E.64 R10, [R6.64+0x20] ; /* 0x00002004060a7981 */
/* 0x001ee8000c1e1b00 */
/*0710*/ LDG.E.64 R12, [R8.64+0x20] ; /* 0x00002004080c7981 */
/* 0x000ee2000c1e1b00 */
/*0720*/ DFMA R22, R14, R22, R16 ; /* 0x000000160e16722b */
/* 0x0100860000000010 */
/*0730*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001f28000c1e1b00 */
/*0740*/ LDG.E.64 R16, [R8.64+0x28] ; /* 0x0000280408107981 */
/* 0x000f22000c1e1b00 */
/*0750*/ DFMA R18, R20, R18, R22 ; /* 0x000000121412722b */
/* 0x0040c60000000016 */
/*0760*/ LDG.E.64 R20, [R6.64+0x30] ; /* 0x0000300406147981 */
/* 0x001ea8000c1e1b00 */
/*0770*/ LDG.E.64 R22, [R8.64+0x30] ; /* 0x0000300408167981 */
/* 0x000ea2000c1e1b00 */
/*0780*/ DFMA R12, R12, R10, R18 ; /* 0x0000000a0c0c722b */
/* 0x0081060000000012 */
/*0790*/ LDG.E.64 R10, [R6.64+0x38] ; /* 0x00003804060a7981 */
/* 0x001ee8000c1e1b00 */
/*07a0*/ LDG.E.64 R18, [R8.64+0x38] ; /* 0x0000380408127981 */
/* 0x000ee2000c1e1b00 */
/*07b0*/ DFMA R12, R16, R14, R12 ; /* 0x0000000e100c722b */
/* 0x010ea2000000000c */
/*07c0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*07d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*07e0*/ IADD3 R24, R24, 0x8, RZ ; /* 0x0000000818187810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0800*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0810*/ DFMA R20, R22, R20, R12 ; /* 0x000000141614722b */
/* 0x0040c4000000000c */
/*0820*/ IADD3 R12, P1, R6, 0x40, RZ ; /* 0x00000040060c7810 */
/* 0x001fca0007f3e0ff */
/*0830*/ IMAD.X R13, RZ, RZ, R7, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0607 */
/*0840*/ DFMA R20, R18, R10, R20 ; /* 0x0000000a1214722b */
/* 0x0080620000000014 */
/*0850*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000c */
/*0860*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000d */
/*0870*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x003fda0000705670 */
/*0880*/ @!P0 BRA 0xa20 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0890*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*08a0*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fe2000f8e00ff */
/*08b0*/ LDG.E.64 R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea6000c1e1b00 */
/*08c0*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fe200078e0208 */
/*08d0*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ee8000c1e1b00 */
/*08e0*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea8000c1e1b00 */
/*08f0*/ LDG.E.64 R12, [R8.64+0x8] ; /* 0x00000804080c7981 */
/* 0x000ee8000c1e1b00 */
/*0900*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f28000c1e1b00 */
/*0910*/ LDG.E.64 R16, [R8.64+0x10] ; /* 0x0000100408107981 */
/* 0x000f22000c1e1b00 */
/*0920*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*0930*/ DFMA R18, R22, R18, R20 ; /* 0x000000121612722b */
/* 0x0040c40000000014 */
/*0940*/ LDG.E.64 R20, [R6.64+0x18] ; /* 0x0000180406147981 */
/* 0x0010a8000c1e1b00 */
/*0950*/ LDG.E.64 R22, [R8.64+0x18] ; /* 0x0000180408167981 */
/* 0x000ea2000c1e1b00 */
/*0960*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0970*/ DFMA R10, R12, R10, R18 ; /* 0x0000000a0c0a722b */
/* 0x0083240000000012 */
/*0980*/ IADD3 R12, P1, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x002fe20007f3e0ff */
/*0990*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fc6000ff1e03f */
/*09a0*/ DFMA R10, R16, R14, R10 ; /* 0x0000000e100a722b */
/* 0x010ea2000000000a */
/*09b0*/ IMAD.X R13, RZ, RZ, R7, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0607 */
/*09c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*09d0*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x001fe20000000f00 */
/*09f0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0a00*/ DFMA R20, R22, R20, R10 ; /* 0x000000141614722b */
/* 0x004064000000000a */
/*0a10*/ @P0 BRA 0x890 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0a20*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0a30*/ @!P0 BRA 0xbb0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0a40*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe400078e00ff */
/*0a50*/ IMAD R6, R0, c[0x0][0x178], R24.reuse ; /* 0x00005e0000067a24 */
/* 0x100fe400078e0218 */
/*0a60*/ IMAD R8, R3, c[0x0][0x178], R24 ; /* 0x00005e0003087a24 */
/* 0x000fe400078e0218 */
/*0a70*/ IMAD.WIDE R6, R6, R9, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0209 */
/*0a80*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0209 */
/*0a90*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fc60000000f00 */
/*0aa0*/ IMAD.MOV.U32 R10, RZ, RZ, R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0007 */
/*0ab0*/ MOV R3, R9 ; /* 0x0000000900037202 */
/* 0x000fe20000000f00 */
/*0ac0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0008 */
/*0ad0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe200078e0005 */
/*0ae0*/ MOV R8, R0 ; /* 0x0000000000087202 */
/* 0x000fe20000000f00 */
/*0af0*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000a */
/*0b00*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0003 */
/*0b10*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*0b20*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0b30*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0b40*/ IADD3 R5, P1, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007f3e0ff */
/*0b50*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0b60*/ IADD3 R0, P2, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe20007f5e0ff */
/*0b70*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc600008e060a */
/*0b80*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*0b90*/ DFMA R20, R6, R8, R20 ; /* 0x000000080614722b */
/* 0x00604c0000000014 */
/*0ba0*/ @P0 BRA 0xad0 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0bc0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0bd0*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x002fe2000c101b04 */
/*0be0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bf0*/ BRA 0xbf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /***************************************************
* Module that multiply a matrix by the transpose of other
* Author: Alonso Vidales <alonso.vidales@tras2.es>
*
* To be compiled with nvcc -ptx matrix_mult_trans.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_mult_trans.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixMulTrans(double* C, double* A, double* B, int wA, int resW, int resH, int resultWidth, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * resultWidth + x;
//printf("Thread %d - %d: %d. Final: x: %d y: %d Size: %d\n", threadIdx.x, threadIdx.y, resultPos, x, y, resultSize);
if (resultPos < resultSize && x < resultWidth) {
// value stores the element that is
// computed by the thread
double value = 0;
for (int i = 0; i < wA; ++i)
{
value += A[y * wA + i] * B[x * wA + i];
//printf("Pos %d - %d, thread %d - %d : pos: %d %d H: %d Pos: %d Val: %f\n", blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, x, y, resultWidth, resultPos, value);
}
// Write the matrix to device memory each
// thread writes one element
C[resultPos] = value;
}
}
#ifdef __cplusplus
}
#endif | .file "tmpxft_00112e26_00000000-6_matrix_mult_trans.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii
.type _Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii, @function
_Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq matrixMulTrans(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii, .-_Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii
.globl matrixMulTrans
.type matrixMulTrans, @function
matrixMulTrans:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size matrixMulTrans, .-matrixMulTrans
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrixMulTrans"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq matrixMulTrans(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /***************************************************
* Module that multiply a matrix by the transpose of other
* Author: Alonso Vidales <alonso.vidales@tras2.es>
*
* To be compiled with nvcc -ptx matrix_mult_trans.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_mult_trans.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixMulTrans(double* C, double* A, double* B, int wA, int resW, int resH, int resultWidth, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * resultWidth + x;
//printf("Thread %d - %d: %d. Final: x: %d y: %d Size: %d\n", threadIdx.x, threadIdx.y, resultPos, x, y, resultSize);
if (resultPos < resultSize && x < resultWidth) {
// value stores the element that is
// computed by the thread
double value = 0;
for (int i = 0; i < wA; ++i)
{
value += A[y * wA + i] * B[x * wA + i];
//printf("Pos %d - %d, thread %d - %d : pos: %d %d H: %d Pos: %d Val: %f\n", blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, x, y, resultWidth, resultPos, value);
}
// Write the matrix to device memory each
// thread writes one element
C[resultPos] = value;
}
}
#ifdef __cplusplus
}
#endif | #include <hip/hip_runtime.h>
/***************************************************
* Module that multiply a matrix by the transpose of other
* Author: Alonso Vidales <alonso.vidales@tras2.es>
*
* To be compiled with nvcc -ptx matrix_mult_trans.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_mult_trans.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixMulTrans(double* C, double* A, double* B, int wA, int resW, int resH, int resultWidth, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * resultWidth + x;
//printf("Thread %d - %d: %d. Final: x: %d y: %d Size: %d\n", threadIdx.x, threadIdx.y, resultPos, x, y, resultSize);
if (resultPos < resultSize && x < resultWidth) {
// value stores the element that is
// computed by the thread
double value = 0;
for (int i = 0; i < wA; ++i)
{
value += A[y * wA + i] * B[x * wA + i];
//printf("Pos %d - %d, thread %d - %d : pos: %d %d H: %d Pos: %d Val: %f\n", blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, x, y, resultWidth, resultPos, value);
}
// Write the matrix to device memory each
// thread writes one element
C[resultPos] = value;
}
}
#ifdef __cplusplus
}
#endif |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/***************************************************
* Module that multiply a matrix by the transpose of other
* Author: Alonso Vidales <alonso.vidales@tras2.es>
*
* To be compiled with nvcc -ptx matrix_mult_trans.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_mult_trans.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixMulTrans(double* C, double* A, double* B, int wA, int resW, int resH, int resultWidth, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * resultWidth + x;
//printf("Thread %d - %d: %d. Final: x: %d y: %d Size: %d\n", threadIdx.x, threadIdx.y, resultPos, x, y, resultSize);
if (resultPos < resultSize && x < resultWidth) {
// value stores the element that is
// computed by the thread
double value = 0;
for (int i = 0; i < wA; ++i)
{
value += A[y * wA + i] * B[x * wA + i];
//printf("Pos %d - %d, thread %d - %d : pos: %d %d H: %d Pos: %d Val: %f\n", blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, x, y, resultWidth, resultPos, value);
}
// Write the matrix to device memory each
// thread writes one element
C[resultPos] = value;
}
}
#ifdef __cplusplus
}
#endif | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected matrixMulTrans
.globl matrixMulTrans
.p2align 8
.type matrixMulTrans,@function
matrixMulTrans:
s_load_b128 s[4:7], s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s6, v2
v_mad_u64_u32 v[0:1], null, v3, s6, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s7, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v1, v2, s2
v_mul_lo_u32 v4, v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[1:2]
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v9, vcc_lo
.LBB0_3:
global_load_b64 v[8:9], v[6:7], off
global_load_b64 v[10:11], v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[8:9], v[10:11], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrixMulTrans
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size matrixMulTrans, .Lfunc_end0-matrixMulTrans
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrixMulTrans
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrixMulTrans.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/***************************************************
* Module that multiply a matrix by the transpose of other
* Author: Alonso Vidales <alonso.vidales@tras2.es>
*
* To be compiled with nvcc -ptx matrix_mult_trans.cu
* Debug: nvcc -arch=sm_20 -ptx matrix_mult_trans.cu
*
**************************************************/
//#include <stdio.h>
#ifdef __cplusplus
extern "C" {
#endif
// CUDA Kernel
__global__ void matrixMulTrans(double* C, double* A, double* B, int wA, int resW, int resH, int resultWidth, int resultSize)
{
int x = threadIdx.x + (blockIdx.x * resW);
int y = threadIdx.y + (blockIdx.y * resH);
int resultPos = y * resultWidth + x;
//printf("Thread %d - %d: %d. Final: x: %d y: %d Size: %d\n", threadIdx.x, threadIdx.y, resultPos, x, y, resultSize);
if (resultPos < resultSize && x < resultWidth) {
// value stores the element that is
// computed by the thread
double value = 0;
for (int i = 0; i < wA; ++i)
{
value += A[y * wA + i] * B[x * wA + i];
//printf("Pos %d - %d, thread %d - %d : pos: %d %d H: %d Pos: %d Val: %f\n", blockIdx.x, blockIdx.y, threadIdx.x, threadIdx.y, x, y, resultWidth, resultPos, value);
}
// Write the matrix to device memory each
// thread writes one element
C[resultPos] = value;
}
}
#ifdef __cplusplus
}
#endif | .text
.file "matrix_mult_trans.hip"
.globl __device_stub__matrixMulTrans # -- Begin function __device_stub__matrixMulTrans
.p2align 4, 0x90
.type __device_stub__matrixMulTrans,@function
__device_stub__matrixMulTrans: # @__device_stub__matrixMulTrans
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $matrixMulTrans, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__matrixMulTrans, .Lfunc_end0-__device_stub__matrixMulTrans
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrixMulTrans, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type matrixMulTrans,@object # @matrixMulTrans
.section .rodata,"a",@progbits
.globl matrixMulTrans
.p2align 3, 0x0
matrixMulTrans:
.quad __device_stub__matrixMulTrans
.size matrixMulTrans, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "matrixMulTrans"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__matrixMulTrans
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym matrixMulTrans
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : matrixMulTrans
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0030*/ S2R R2, SR_CTAID.Y ; /* 0x0000000000027919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R0, R0, c[0x0][0x17c], R3 ; /* 0x00005f0000007a24 */
/* 0x001fc400078e0203 */
/*0060*/ IMAD R3, R2, c[0x0][0x180], R5 ; /* 0x0000600002037a24 */
/* 0x002fc800078e0205 */
/*0070*/ IMAD R2, R3, c[0x0][0x184], R0 ; /* 0x0000610003027a24 */
/* 0x000fca00078e0200 */
/*0080*/ ISETP.GE.AND P0, PT, R2, c[0x0][0x188], PT ; /* 0x0000620002007a0c */
/* 0x000fc80003f06270 */
/*0090*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x184], P0 ; /* 0x0000610000007a0c */
/* 0x000fda0000706670 */
/*00a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff047624 */
/* 0x000fe200078e00ff */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00d0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fc6000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xbb0 ; /* 0x00000ab000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R5, R4.reuse, -0x1, RZ ; /* 0xffffffff04057810 */
/* 0x040fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fe200078e00ff */
/*0120*/ LOP3.LUT R4, R4, 0x3, RZ, 0xc0, !PT ; /* 0x0000000304047812 */
/* 0x000fe200078ec0ff */
/*0130*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R5, 0x3, PT ; /* 0x000000030500780c */
/* 0x000fda0003f06070 */
/*0150*/ @!P0 BRA 0xa20 ; /* 0x000008c000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R5, -R4, c[0x0][0x178], RZ ; /* 0x00005e0004057a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ HFMA2.MMA R7, -RZ, RZ, 0, 4.76837158203125e-07 ; /* 0x00000008ff077435 */
/* 0x000fe200000001ff */
/*0180*/ IMAD R6, R3, c[0x0][0x178], RZ ; /* 0x00005e0003067a24 */
/* 0x000fe200078e02ff */
/*0190*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*01a0*/ ISETP.GT.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f04270 */
/*01b0*/ IMAD R25, R0, c[0x0][0x178], RZ ; /* 0x00005e0000197a24 */
/* 0x000fe200078e02ff */
/*01c0*/ CS2R R20, SRZ ; /* 0x0000000000147805 */
/* 0x000fe2000001ff00 */
/*01d0*/ IMAD.MOV.U32 R24, RZ, RZ, RZ ; /* 0x000000ffff187224 */
/* 0x000fc800078e00ff */
/*01e0*/ IMAD.WIDE R6, R6, R7, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fcc00078e0207 */
/*01f0*/ @!P0 BRA 0x890 ; /* 0x0000069000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0220*/ @!P1 BRA 0x610 ; /* 0x000003e000009947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*0250*/ LDG.E.64 R10, [R6.64] ; /* 0x00000004060a7981 */
/* 0x001ea2000c1e1b00 */
/*0260*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fc6000f8e00ff */
/*0270*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee2000c1e1b00 */
/*0280*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fc600078e0208 */
/*0290*/ LDG.E.64 R18, [R6.64+0x10] ; /* 0x0000100406127981 */
/* 0x000f28000c1e1b00 */
/*02a0*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea8000c1e1b00 */
/*02b0*/ LDG.E.64 R12, [R8.64+0x8] ; /* 0x00000804080c7981 */
/* 0x000ee8000c1e1b00 */
/*02c0*/ LDG.E.64 R14, [R8.64+0x10] ; /* 0x00001004080e7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ DFMA R20, R22, R10, R20 ; /* 0x0000000a1614722b */
/* 0x0060c60000000014 */
/*02e0*/ LDG.E.64 R22, [R6.64+0x18] ; /* 0x0000180406167981 */
/* 0x001ea8000c1e1b00 */
/*02f0*/ LDG.E.64 R10, [R8.64+0x18] ; /* 0x00001804080a7981 */
/* 0x000ea2000c1e1b00 */
/*0300*/ DFMA R16, R12, R16, R20 ; /* 0x000000100c10722b */
/* 0x0081060000000014 */
/*0310*/ LDG.E.64 R20, [R6.64+0x20] ; /* 0x0000200406147981 */
/* 0x001ee8000c1e1b00 */
/*0320*/ LDG.E.64 R12, [R8.64+0x20] ; /* 0x00002004080c7981 */
/* 0x000ee2000c1e1b00 */
/*0330*/ DFMA R18, R14, R18, R16 ; /* 0x000000120e12722b */
/* 0x0100860000000010 */
/*0340*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001f28000c1e1b00 */
/*0350*/ LDG.E.64 R16, [R8.64+0x28] ; /* 0x0000280408107981 */
/* 0x000f22000c1e1b00 */
/*0360*/ DFMA R22, R10, R22, R18 ; /* 0x000000160a16722b */
/* 0x0040c60000000012 */
/*0370*/ LDG.E.64 R18, [R6.64+0x30] ; /* 0x0000300406127981 */
/* 0x001ea8000c1e1b00 */
/*0380*/ LDG.E.64 R10, [R8.64+0x30] ; /* 0x00003004080a7981 */
/* 0x000ea2000c1e1b00 */
/*0390*/ DFMA R20, R12, R20, R22 ; /* 0x000000140c14722b */
/* 0x0081060000000016 */
/*03a0*/ LDG.E.64 R22, [R6.64+0x38] ; /* 0x0000380406167981 */
/* 0x001ee8000c1e1b00 */
/*03b0*/ LDG.E.64 R12, [R8.64+0x38] ; /* 0x00003804080c7981 */
/* 0x000ee2000c1e1b00 */
/*03c0*/ DFMA R14, R16, R14, R20 ; /* 0x0000000e100e722b */
/* 0x0100860000000014 */
/*03d0*/ LDG.E.64 R20, [R6.64+0x40] ; /* 0x0000400406147981 */
/* 0x001f28000c1e1b00 */
/*03e0*/ LDG.E.64 R16, [R8.64+0x40] ; /* 0x0000400408107981 */
/* 0x000f22000c1e1b00 */
/*03f0*/ DFMA R18, R10, R18, R14 ; /* 0x000000120a12722b */
/* 0x0040c6000000000e */
/*0400*/ LDG.E.64 R14, [R6.64+0x48] ; /* 0x00004804060e7981 */
/* 0x001ea8000c1e1b00 */
/*0410*/ LDG.E.64 R10, [R8.64+0x48] ; /* 0x00004804080a7981 */
/* 0x000ea2000c1e1b00 */
/*0420*/ DFMA R22, R12, R22, R18 ; /* 0x000000160c16722b */
/* 0x0081060000000012 */
/*0430*/ LDG.E.64 R18, [R6.64+0x50] ; /* 0x0000500406127981 */
/* 0x001ee8000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R8.64+0x50] ; /* 0x00005004080c7981 */
/* 0x000ee2000c1e1b00 */
/*0450*/ DFMA R20, R16, R20, R22 ; /* 0x000000141014722b */
/* 0x0100860000000016 */
/*0460*/ LDG.E.64 R22, [R6.64+0x58] ; /* 0x0000580406167981 */
/* 0x001f28000c1e1b00 */
/*0470*/ LDG.E.64 R16, [R8.64+0x58] ; /* 0x0000580408107981 */
/* 0x000f22000c1e1b00 */
/*0480*/ DFMA R14, R10, R14, R20 ; /* 0x0000000e0a0e722b */
/* 0x0040c60000000014 */
/*0490*/ LDG.E.64 R10, [R6.64+0x60] ; /* 0x00006004060a7981 */
/* 0x001ea8000c1e1b00 */
/*04a0*/ LDG.E.64 R20, [R8.64+0x60] ; /* 0x0000600408147981 */
/* 0x000ea2000c1e1b00 */
/*04b0*/ DFMA R18, R12, R18, R14 ; /* 0x000000120c12722b */
/* 0x008106000000000e */
/*04c0*/ LDG.E.64 R12, [R6.64+0x68] ; /* 0x00006804060c7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R14, [R8.64+0x68] ; /* 0x00006804080e7981 */
/* 0x000ee2000c1e1b00 */
/*04e0*/ DFMA R22, R16, R22, R18 ; /* 0x000000161016722b */
/* 0x0100860000000012 */
/*04f0*/ LDG.E.64 R16, [R6.64+0x70] ; /* 0x0000700406107981 */
/* 0x001f28000c1e1b00 */
/*0500*/ LDG.E.64 R18, [R8.64+0x70] ; /* 0x0000700408127981 */
/* 0x000f22000c1e1b00 */
/*0510*/ DFMA R10, R20, R10, R22 ; /* 0x0000000a140a722b */
/* 0x0040c60000000016 */
/*0520*/ LDG.E.64 R20, [R6.64+0x78] ; /* 0x0000780406147981 */
/* 0x0010a8000c1e1b00 */
/*0530*/ LDG.E.64 R22, [R8.64+0x78] ; /* 0x0000780408167981 */
/* 0x000ea2000c1e1b00 */
/*0540*/ IADD3 R5, R5, -0x10, RZ ; /* 0xfffffff005057810 */
/* 0x000fe20007ffe0ff */
/*0550*/ DFMA R10, R14, R12, R10 ; /* 0x0000000c0e0a722b */
/* 0x008306000000000a */
/*0560*/ ISETP.GT.AND P1, PT, R5, 0xc, PT ; /* 0x0000000c0500780c */
/* 0x000fe40003f24270 */
/*0570*/ IADD3 R12, P2, R6, 0x80, RZ ; /* 0x00000080060c7810 */
/* 0x002fe20007f5e0ff */
/*0580*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0590*/ DFMA R10, R18, R16, R10 ; /* 0x00000010120a722b */
/* 0x010ea4000000000a */
/*05a0*/ IADD3.X R13, RZ, R7, RZ, P2, !PT ; /* 0x00000007ff0d7210 */
/* 0x000fe200017fe4ff */
/*05b0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*05c0*/ IADD3 R24, R24, 0x10, RZ ; /* 0x0000001018187810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x001fe400078e000c */
/*05e0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*05f0*/ DFMA R20, R22, R20, R10 ; /* 0x000000141614722b */
/* 0x004062000000000a */
/*0600*/ @P1 BRA 0x240 ; /* 0xfffffc3000001947 */
/* 0x000fea000383ffff */
/*0610*/ ISETP.GT.AND P1, PT, R5, 0x4, PT ; /* 0x000000040500780c */
/* 0x000fda0003f24270 */
/*0620*/ @!P1 BRA 0x870 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*0630*/ MOV R9, UR7 ; /* 0x0000000700097c02 */
/* 0x000fe20008000f00 */
/*0640*/ IMAD.U32 R8, RZ, RZ, UR6 ; /* 0x00000006ff087e24 */
/* 0x000fe2000f8e00ff */
/*0650*/ LDG.E.64 R12, [R6.64] ; /* 0x00000004060c7981 */
/* 0x000ea6000c1e1b00 */
/*0660*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fe200078e0208 */
/*0670*/ LDG.E.64 R16, [R6.64+0x8] ; /* 0x0000080406107981 */
/* 0x000ee8000c1e1b00 */
/*0680*/ LDG.E.64 R18, [R8.64] ; /* 0x0000000408127981 */
/* 0x000ea8000c1e1b00 */
/*0690*/ LDG.E.64 R10, [R8.64+0x8] ; /* 0x00000804080a7981 */
/* 0x001ee8000c1e1b00 */
/*06a0*/ LDG.E.64 R22, [R6.64+0x10] ; /* 0x0000100406167981 */
/* 0x000f28000c1e1b00 */
/*06b0*/ LDG.E.64 R14, [R8.64+0x10] ; /* 0x00001004080e7981 */
/* 0x000f22000c1e1b00 */
/*06c0*/ DFMA R12, R18, R12, R20 ; /* 0x0000000c120c722b */
/* 0x0060c60000000014 */
/*06d0*/ LDG.E.64 R18, [R6.64+0x18] ; /* 0x0000180406127981 */
/* 0x001ea8000c1e1b00 */
/*06e0*/ LDG.E.64 R20, [R8.64+0x18] ; /* 0x0000180408147981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ DFMA R16, R10, R16, R12 ; /* 0x000000100a10722b */
/* 0x008106000000000c */
/*0700*/ LDG.E.64 R10, [R6.64+0x20] ; /* 0x00002004060a7981 */
/* 0x001ee8000c1e1b00 */
/*0710*/ LDG.E.64 R12, [R8.64+0x20] ; /* 0x00002004080c7981 */
/* 0x000ee2000c1e1b00 */
/*0720*/ DFMA R22, R14, R22, R16 ; /* 0x000000160e16722b */
/* 0x0100860000000010 */
/*0730*/ LDG.E.64 R14, [R6.64+0x28] ; /* 0x00002804060e7981 */
/* 0x001f28000c1e1b00 */
/*0740*/ LDG.E.64 R16, [R8.64+0x28] ; /* 0x0000280408107981 */
/* 0x000f22000c1e1b00 */
/*0750*/ DFMA R18, R20, R18, R22 ; /* 0x000000121412722b */
/* 0x0040c60000000016 */
/*0760*/ LDG.E.64 R20, [R6.64+0x30] ; /* 0x0000300406147981 */
/* 0x001ea8000c1e1b00 */
/*0770*/ LDG.E.64 R22, [R8.64+0x30] ; /* 0x0000300408167981 */
/* 0x000ea2000c1e1b00 */
/*0780*/ DFMA R12, R12, R10, R18 ; /* 0x0000000a0c0c722b */
/* 0x0081060000000012 */
/*0790*/ LDG.E.64 R10, [R6.64+0x38] ; /* 0x00003804060a7981 */
/* 0x001ee8000c1e1b00 */
/*07a0*/ LDG.E.64 R18, [R8.64+0x38] ; /* 0x0000380408127981 */
/* 0x000ee2000c1e1b00 */
/*07b0*/ DFMA R12, R16, R14, R12 ; /* 0x0000000e100c722b */
/* 0x010ea2000000000c */
/*07c0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*07d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*07e0*/ IADD3 R24, R24, 0x8, RZ ; /* 0x0000000818187810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ IADD3 R5, R5, -0x8, RZ ; /* 0xfffffff805057810 */
/* 0x000fe20007ffe0ff */
/*0800*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0810*/ DFMA R20, R22, R20, R12 ; /* 0x000000141614722b */
/* 0x0040c4000000000c */
/*0820*/ IADD3 R12, P1, R6, 0x40, RZ ; /* 0x00000040060c7810 */
/* 0x001fca0007f3e0ff */
/*0830*/ IMAD.X R13, RZ, RZ, R7, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0607 */
/*0840*/ DFMA R20, R18, R10, R20 ; /* 0x0000000a1214722b */
/* 0x0080620000000014 */
/*0850*/ IMAD.MOV.U32 R6, RZ, RZ, R12 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000c */
/*0860*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000d */
/*0870*/ ISETP.NE.OR P0, PT, R5, RZ, P0 ; /* 0x000000ff0500720c */
/* 0x003fda0000705670 */
/*0880*/ @!P0 BRA 0xa20 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0890*/ MOV R8, UR6 ; /* 0x0000000600087c02 */
/* 0x000fe20008000f00 */
/*08a0*/ IMAD.U32 R9, RZ, RZ, UR7 ; /* 0x00000007ff097e24 */
/* 0x000fe2000f8e00ff */
/*08b0*/ LDG.E.64 R18, [R6.64] ; /* 0x0000000406127981 */
/* 0x000ea6000c1e1b00 */
/*08c0*/ IMAD.WIDE R8, R25, 0x8, R8 ; /* 0x0000000819087825 */
/* 0x000fe200078e0208 */
/*08d0*/ LDG.E.64 R10, [R6.64+0x8] ; /* 0x00000804060a7981 */
/* 0x000ee8000c1e1b00 */
/*08e0*/ LDG.E.64 R22, [R8.64] ; /* 0x0000000408167981 */
/* 0x000ea8000c1e1b00 */
/*08f0*/ LDG.E.64 R12, [R8.64+0x8] ; /* 0x00000804080c7981 */
/* 0x000ee8000c1e1b00 */
/*0900*/ LDG.E.64 R14, [R6.64+0x10] ; /* 0x00001004060e7981 */
/* 0x000f28000c1e1b00 */
/*0910*/ LDG.E.64 R16, [R8.64+0x10] ; /* 0x0000100408107981 */
/* 0x000f22000c1e1b00 */
/*0920*/ IADD3 R5, R5, -0x4, RZ ; /* 0xfffffffc05057810 */
/* 0x000fe20007ffe0ff */
/*0930*/ DFMA R18, R22, R18, R20 ; /* 0x000000121612722b */
/* 0x0040c40000000014 */
/*0940*/ LDG.E.64 R20, [R6.64+0x18] ; /* 0x0000180406147981 */
/* 0x0010a8000c1e1b00 */
/*0950*/ LDG.E.64 R22, [R8.64+0x18] ; /* 0x0000180408167981 */
/* 0x000ea2000c1e1b00 */
/*0960*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0970*/ DFMA R10, R12, R10, R18 ; /* 0x0000000a0c0a722b */
/* 0x0083240000000012 */
/*0980*/ IADD3 R12, P1, R6, 0x20, RZ ; /* 0x00000020060c7810 */
/* 0x002fe20007f3e0ff */
/*0990*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fc6000ff1e03f */
/*09a0*/ DFMA R10, R16, R14, R10 ; /* 0x0000000e100a722b */
/* 0x010ea2000000000a */
/*09b0*/ IMAD.X R13, RZ, RZ, R7, P1 ; /* 0x000000ffff0d7224 */
/* 0x000fe200008e0607 */
/*09c0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*09d0*/ IADD3 R24, R24, 0x4, RZ ; /* 0x0000000418187810 */
/* 0x000fe40007ffe0ff */
/*09e0*/ MOV R6, R12 ; /* 0x0000000c00067202 */
/* 0x001fe20000000f00 */
/*09f0*/ IMAD.MOV.U32 R7, RZ, RZ, R13 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000d */
/*0a00*/ DFMA R20, R22, R20, R10 ; /* 0x000000141614722b */
/* 0x004064000000000a */
/*0a10*/ @P0 BRA 0x890 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0a20*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fda0003f05270 */
/*0a30*/ @!P0 BRA 0xbb0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0a40*/ IMAD.MOV.U32 R9, RZ, RZ, 0x8 ; /* 0x00000008ff097424 */
/* 0x000fe400078e00ff */
/*0a50*/ IMAD R6, R0, c[0x0][0x178], R24.reuse ; /* 0x00005e0000067a24 */
/* 0x100fe400078e0218 */
/*0a60*/ IMAD R8, R3, c[0x0][0x178], R24 ; /* 0x00005e0003087a24 */
/* 0x000fe400078e0218 */
/*0a70*/ IMAD.WIDE R6, R6, R9, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fc800078e0209 */
/*0a80*/ IMAD.WIDE R8, R8, R9, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0209 */
/*0a90*/ MOV R5, R6 ; /* 0x0000000600057202 */
/* 0x000fc60000000f00 */
/*0aa0*/ IMAD.MOV.U32 R10, RZ, RZ, R7 ; /* 0x000000ffff0a7224 */
/* 0x000fe200078e0007 */
/*0ab0*/ MOV R3, R9 ; /* 0x0000000900037202 */
/* 0x000fe20000000f00 */
/*0ac0*/ IMAD.MOV.U32 R0, RZ, RZ, R8 ; /* 0x000000ffff007224 */
/* 0x000fc800078e0008 */
/*0ad0*/ IMAD.MOV.U32 R6, RZ, RZ, R5 ; /* 0x000000ffff067224 */
/* 0x001fe200078e0005 */
/*0ae0*/ MOV R8, R0 ; /* 0x0000000000087202 */
/* 0x000fe20000000f00 */
/*0af0*/ IMAD.MOV.U32 R7, RZ, RZ, R10 ; /* 0x000000ffff077224 */
/* 0x000fe400078e000a */
/*0b00*/ IMAD.MOV.U32 R9, RZ, RZ, R3 ; /* 0x000000ffff097224 */
/* 0x000fc800078e0003 */
/*0b10*/ LDG.E.64 R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea8000c1e1b00 */
/*0b20*/ LDG.E.64 R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea2000c1e1b00 */
/*0b30*/ IADD3 R4, R4, -0x1, RZ ; /* 0xffffffff04047810 */
/* 0x000fe40007ffe0ff */
/*0b40*/ IADD3 R5, P1, R5, 0x8, RZ ; /* 0x0000000805057810 */
/* 0x000fe40007f3e0ff */
/*0b50*/ ISETP.NE.AND P0, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f05270 */
/*0b60*/ IADD3 R0, P2, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe20007f5e0ff */
/*0b70*/ IMAD.X R10, RZ, RZ, R10, P1 ; /* 0x000000ffff0a7224 */
/* 0x000fc600008e060a */
/*0b80*/ IADD3.X R3, RZ, R3, RZ, P2, !PT ; /* 0x00000003ff037210 */
/* 0x000fe200017fe4ff */
/*0b90*/ DFMA R20, R6, R8, R20 ; /* 0x000000080614722b */
/* 0x00604c0000000014 */
/*0ba0*/ @P0 BRA 0xad0 ; /* 0xffffff2000000947 */
/* 0x000fea000383ffff */
/*0bb0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x8 ; /* 0x00000008ff037424 */
/* 0x000fc800078e00ff */
/*0bc0*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0bd0*/ STG.E.64 [R2.64], R20 ; /* 0x0000001402007986 */
/* 0x002fe2000c101b04 */
/*0be0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0bf0*/ BRA 0xbf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0c00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0c70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected matrixMulTrans
.globl matrixMulTrans
.p2align 8
.type matrixMulTrans,@function
matrixMulTrans:
s_load_b128 s[4:7], s[0:1], 0x1c
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[2:3], null, s14, s4, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s5, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e64 s2, s6, v2
v_mad_u64_u32 v[0:1], null, v3, s6, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_gt_i32_e32 vcc_lo, s7, v0
s_and_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_6
s_load_b32 s2, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x8
v_mul_lo_u32 v1, v2, s2
v_mul_lo_u32 v4, v3, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[6:7], 3, v[1:2]
v_lshlrev_b64 v[8:9], 3, v[4:5]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s6, v6
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v7, vcc_lo
v_add_co_u32 v6, vcc_lo, s4, v8
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v9, vcc_lo
.LBB0_3:
global_load_b64 v[8:9], v[6:7], off
global_load_b64 v[10:11], v[4:5], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
v_add_co_u32 v6, vcc_lo, v6, 8
v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
s_add_i32 s2, s2, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s2, 0
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[8:9], v[10:11], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 3, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel matrixMulTrans
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 44
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size matrixMulTrans, .Lfunc_end0-matrixMulTrans
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 44
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: matrixMulTrans
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: matrixMulTrans.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00112e26_00000000-6_matrix_mult_trans.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii
.type _Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii, @function
_Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii:
.LFB2051:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 208(%rsp), %rax
movq %rax, 160(%rsp)
leaq 216(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq matrixMulTrans(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii, .-_Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii
.globl matrixMulTrans
.type matrixMulTrans, @function
matrixMulTrans:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z43__device_stub__Z14matrixMulTransPdS_S_iiiiiPdS_S_iiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size matrixMulTrans, .-matrixMulTrans
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "matrixMulTrans"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq matrixMulTrans(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_mult_trans.hip"
.globl __device_stub__matrixMulTrans # -- Begin function __device_stub__matrixMulTrans
.p2align 4, 0x90
.type __device_stub__matrixMulTrans,@function
__device_stub__matrixMulTrans: # @__device_stub__matrixMulTrans
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 176(%rsp), %rax
movq %rax, 144(%rsp)
leaq 184(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $matrixMulTrans, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size __device_stub__matrixMulTrans, .Lfunc_end0-__device_stub__matrixMulTrans
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $matrixMulTrans, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type matrixMulTrans,@object # @matrixMulTrans
.section .rodata,"a",@progbits
.globl matrixMulTrans
.p2align 3, 0x0
matrixMulTrans:
.quad __device_stub__matrixMulTrans
.size matrixMulTrans, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "matrixMulTrans"
.size .L__unnamed_1, 15
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__matrixMulTrans
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym matrixMulTrans
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <iostream>
#include <fstream>
#include <cmath>
#include <cstdlib>
#include <string>
#include <iomanip>
#define T_P_B 1024
///////////////////////////// Global variables /////////////////////////////////
std::string dimension; // grid dimension
float k; // k-step
int timesteps; // num of timesteps
int width, height, depth; // grid size
float startTemp, fixedTemp; // node start temp
int heat_x, heat_y, heat_z, // fixed heater vars
heat_w, heat_h, heat_d;
float *d_old, *d_new, *d_heaters, // grids for values
*g_old, *g_new, *heaters;
///////////////////////////// CUDA Functions ///////////////////////////////////
__global__ void heat_sim(float *oldg, float * newg, float *fixed,
int width, int height, int depth, float k)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
float left, right, up, down, above, below;
float old = oldg[idx];
if (idx < (width*height*depth))
{
if (fixed[idx] != 0) newg[idx] = fixed[idx];
else if (fixed[idx] == 0)
{
// x-, x+
((idx%width) == 0) ? (left = old) : (left = oldg[idx-1]);
((idx%width) == (width-1)) ? (right = old) : (right = oldg[idx+1]);
// y-, y+
(idx%(width*height) < width) ? (up = old) : (up = oldg[idx - width]);
(idx%(width*height) >= ((height-1)*width))
? (down = old) : (down = oldg[idx + width]);
// z-, z+
if (depth <= 1)
{
above = 0.0;
below = 0.0;
newg[idx] = oldg[idx] + k*(up+down+left+right-(4.0*oldg[idx]));
}
else if (depth > 1)
{
if (idx < (width*height)) above = old;
else above = oldg[idx - (width*height)];
if (idx >= ((depth-1)*(width*height))) below = old;
else below = oldg[idx + (width*height)];
newg[idx] = oldg[idx] + k*(up+down+left
+right+above+below-(6.0*oldg[idx]));
}
}
}
}
__global__ void grid_cpy(float *oldg, float *newg, int size)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < size)
oldg[idx] = newg[idx];
}
///////////////////////////// End CUDA Functions ///////////////////////////////
int main(int argc, char * argv[])
{
///////////////////////////// Config file parser ///////////////////////////////
std::ifstream conf(argv[1]);
if (conf.is_open())
{
std::string line;
while (getline(conf, line)){
if ((line[0] == '#') || line.empty() || line[0] == '\r')
continue;
// get dimension
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
dimension = line.substr(0,2);
// get k value
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
k = std::stof(line);
// get timesteps
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
timesteps = std::stoi(line);
// get grid size
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
int comma = line.find(',');
width = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
if (dimension == "2D"){
height = std::stoi(line);
depth = 1;
}
else if (dimension == "3D"){
comma = line.find(',');
height = std::stoi(line.substr(0, comma));
depth = std::stoi(line.substr(comma+1));
}
// get block start temp
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
startTemp = std::stof(line);
// create heaters
heaters = new float[width*height*depth];
std::fill(heaters, heaters+(width*height*depth), 0);
while(getline(conf, line)){
if (line[0] == '#' || line.empty() || line[0] == '\r')
continue;
int comma = line.find(',');
heat_x = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_y = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
if (dimension == "2D"){
heat_w = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_h = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
heat_d = 1;
heat_z = 0;
fixedTemp = std::stof(line);
}
else if (dimension == "3D"){
heat_z = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_w = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_h = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_d = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
fixedTemp = std::stof(line);
}
for (int i = heat_x+width*heat_y;
i < heat_x+heat_w+width*heat_y; i++)
for (int j = 0; j < heat_h; j++)
for (int k = heat_z; k < heat_z+heat_d; k++)
heaters[i+(j*width)+(k*width*height)] = fixedTemp;
}
}
}
else std::cerr << "Couldn't open config file.";
////////////////////////// End config file parser //////////////////////////////
int dim = width*height*depth;
// set up host grids
g_old = new float[dim];
g_new = new float[dim];
std::fill(g_new, g_new+dim, 0);
std::fill(g_old, g_old+dim, 0);
for (int i = 0; i < dim; i++)
{
g_old[i] = startTemp;
if (heaters[i] != 0) g_old[i] = heaters[i];
}
// allocate blockSize - must be at least one block
int blockSize = ceil(float(dim)/float(T_P_B));
// allocate device memory in 1D array
cudaMalloc((void**)&d_new, dim*sizeof(float));
cudaMalloc((void**)&d_old, dim*sizeof(float));
cudaMalloc((void**)&d_heaters, dim*sizeof(float));
// copy filled arrays from host to device
cudaMemcpy(d_old, g_old, dim*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_new, g_new, dim*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_heaters, heaters, dim*sizeof(float), cudaMemcpyHostToDevice);
// run kernels
for (int t = 0; t < timesteps; t++)
{
heat_sim<<<blockSize, T_P_B>>> (d_old, d_new, d_heaters,
width, height, depth, k);
cudaDeviceSynchronize();
grid_cpy<<< blockSize, T_P_B>>> (d_old, d_new, dim);
cudaDeviceSynchronize();
}
// copy data back from device to host
cudaMemcpy(g_new, d_new, dim*sizeof(float), cudaMemcpyDeviceToHost);
// print out to csv
std::ofstream csv("../heatOutput.csv", std::ios::out);
if (csv.is_open()){
for (int i = 0; i < dim; i++)
{
if (i%width == width-1) csv << g_new[i] << std::endl;
else csv << g_new[i] << ", ";
if (i%(width*height) == (width*height)-1) csv << std::endl;
}
}
else
std::cout << "Unable to open file, try again." << std::endl;
csv.close();
// deallocate all memory
delete[] g_old;
delete[] g_new;
delete[] heaters;
cudaFree(d_old);
cudaFree(d_new);
cudaFree(d_heaters);
} | code for sm_80
Function : _Z8grid_cpyPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8heat_simPfS_S_iiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff077624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x000fc800078e02ff */
/*0050*/ IMAD R8, R7, c[0x0][0x180], RZ ; /* 0x0000600007087a24 */
/* 0x000fe400078e02ff */
/*0060*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R6, R8, PT ; /* 0x000000080600720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe20000011406 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ SHF.L.U32 R2, R6.reuse, 0x2, RZ ; /* 0x0000000206027819 */
/* 0x040fe400000006ff */
/*00c0*/ SHF.L.U64.HI R3, R6, 0x2, R3 ; /* 0x0000000206037819 */
/* 0x000fe40000010203 */
/*00d0*/ IADD3 R4, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R5, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0003057a10 */
/* 0x000fcc00007fe4ff */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R2, P1, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fc80007f3e0ff */
/*0110*/ IADD3.X R3, R3, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0003037a10 */
/* 0x000fe40000ffe4ff */
/*0120*/ FSETP.NEU.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x004fda0003f0d000 */
/*0130*/ @P0 BRA 0x780 ; /* 0x0000064000000947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.WIDE R4, R6, R9, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fca00078e0209 */
/*0160*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IABS R10, R7 ; /* 0x00000007000a7213 */
/* 0x000fe40000000000 */
/*0180*/ IABS R11, c[0x0][0x178] ; /* 0x00005e00000b7a13 */
/* 0x000fe40000000000 */
/*0190*/ I2F.RP R17, R10 ; /* 0x0000000a00117306 */
/* 0x000e220000209400 */
/*01a0*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fce0003f45270 */
/*01b0*/ I2F.RP R16, R11 ; /* 0x0000000b00107306 */
/* 0x000e700000209400 */
/*01c0*/ MUFU.RCP R17, R17 ; /* 0x0000001100117308 */
/* 0x001e300000001000 */
/*01d0*/ MUFU.RCP R16, R16 ; /* 0x0000001000107308 */
/* 0x002e620000001000 */
/*01e0*/ IADD3 R14, R17, 0xffffffe, RZ ; /* 0x0ffffffe110e7810 */
/* 0x001fc40007ffe0ff */
/*01f0*/ IABS R17, R6 ; /* 0x0000000600117213 */
/* 0x000fca0000000000 */
/*0200*/ F2I.FTZ.U32.TRUNC.NTZ R15, R14 ; /* 0x0000000e000f7305 */
/* 0x0000e2000021f000 */
/*0210*/ IADD3 R12, R16, 0xffffffe, RZ ; /* 0x0ffffffe100c7810 */
/* 0x002fe40007ffe0ff */
/*0220*/ IABS R16, R7 ; /* 0x0000000700107213 */
/* 0x000fca0000000000 */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; /* 0x0000000c000d7305 */
/* 0x000322000021f000 */
/*0240*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e00ff */
/*0250*/ IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0a10 */
/*0260*/ IMAD.MOV R19, RZ, RZ, -R15 ; /* 0x000000ffff137224 */
/* 0x008fe200078e0a0f */
/*0270*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x002fc600000001ff */
/*0280*/ IMAD R19, R19, R10, RZ ; /* 0x0000000a13137224 */
/* 0x000fe200078e02ff */
/*0290*/ IADD3 R18, RZ, -R13, RZ ; /* 0x8000000dff127210 */
/* 0x010fc60007ffe0ff */
/*02a0*/ IMAD.HI.U32 R14, R15, R19, R14 ; /* 0x000000130f0e7227 */
/* 0x000fc800078e000e */
/*02b0*/ IMAD R15, R18, R11, RZ ; /* 0x0000000b120f7224 */
/* 0x000fe400078e02ff */
/*02c0*/ IMAD.HI.U32 R14, R14, R17, RZ ; /* 0x000000110e0e7227 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.HI.U32 R12, R13, R15, R12 ; /* 0x0000000f0d0c7227 */
/* 0x000fc800078e000c */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, R16 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0010 */
/*02f0*/ IMAD.HI.U32 R12, R12, R17, RZ ; /* 0x000000110c0c7227 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD R13, R14, R13, R17 ; /* 0x0000000d0e0d7224 */
/* 0x000fe400078e0211 */
/*0310*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0a0c */
/*0320*/ ISETP.GT.U32.AND P1, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fe20003f24070 */
/*0330*/ IMAD R12, R11, R12, R17 ; /* 0x0000000c0b0c7224 */
/* 0x000fca00078e0211 */
/*0340*/ ISETP.GT.U32.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fce0003f04070 */
/*0350*/ @!P1 IADD3 R13, R13, -R10, RZ ; /* 0x8000000a0d0d9210 */
/* 0x000fc80007ffe0ff */
/*0360*/ ISETP.GT.U32.AND P1, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fe40003f24070 */
/*0370*/ @!P0 IMAD.IADD R12, R12, 0x1, -R11 ; /* 0x000000010c0c8824 */
/* 0x000fe200078e0a0b */
/*0380*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f06270 */
/*0390*/ ISETP.GT.U32.AND P3, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fcc0003f64070 */
/*03a0*/ @!P1 IMAD.IADD R13, R13, 0x1, -R10 ; /* 0x000000010d0d9824 */
/* 0x000fe200078e0a0a */
/*03b0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25270 */
/*03c0*/ IADD3 R10, R7, -c[0x0][0x178], RZ ; /* 0x80005e00070a7a10 */
/* 0x000fe40007ffe0ff */
/*03d0*/ @!P0 IADD3 R13, -R13, RZ, RZ ; /* 0x000000ff0d0d8210 */
/* 0x000fe40007ffe1ff */
/*03e0*/ @!P2 LOP3.LUT R13, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff0da212 */
/* 0x000fe200078e33ff */
/*03f0*/ @!P3 IMAD.IADD R12, R12, 0x1, -R11 ; /* 0x000000010c0cb824 */
/* 0x000fc600078e0a0b */
/*0400*/ ISETP.GE.AND P2, PT, R13.reuse, c[0x0][0x178], PT ; /* 0x00005e000d007a0c */
/* 0x040fe40003f46270 */
/*0410*/ ISETP.GE.AND P3, PT, R13, R10, PT ; /* 0x0000000a0d00720c */
/* 0x000fe20003f66270 */
/*0420*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0d7624 */
/* 0x000fe200078e00ff */
/*0430*/ @!P0 IADD3 R12, -R12, RZ, RZ ; /* 0x000000ff0c0c8210 */
/* 0x000fe40007ffe1ff */
/*0440*/ @!P1 LOP3.LUT R12, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff0c9a12 */
/* 0x000fe400078e33ff */
/*0450*/ IADD3 R10, R13, -0x1, RZ ; /* 0xffffffff0d0a7810 */
/* 0x000fe40007ffe0ff */
/*0460*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc40003f05270 */
/*0470*/ ISETP.NE.AND P1, PT, R12, R10, PT ; /* 0x0000000a0c00720c */
/* 0x000fe40003f25270 */
/*0480*/ @P2 IADD3 R10, R6, -c[0x0][0x178], RZ ; /* 0x80005e00060a2a10 */
/* 0x000fe20007ffe0ff */
/*0490*/ @!P3 IMAD.WIDE R12, R13, 0x4, R4 ; /* 0x000000040d0cb825 */
/* 0x000fc800078e0204 */
/*04a0*/ @P2 IMAD.WIDE R10, R10, R9, c[0x0][0x160] ; /* 0x000058000a0a2625 */
/* 0x000fc800078e0209 */
/*04b0*/ IMAD.MOV.U32 R17, RZ, RZ, R0.reuse ; /* 0x000000ffff117224 */
/* 0x104fe400078e0000 */
/*04c0*/ IMAD.MOV.U32 R16, RZ, RZ, R0.reuse ; /* 0x000000ffff107224 */
/* 0x100fe400078e0000 */
/*04d0*/ IMAD.MOV.U32 R15, RZ, RZ, R0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0000 */
/*04e0*/ @!P3 LDG.E R17, [R12.64] ; /* 0x000000040c11b981 */
/* 0x000162000c1e1900 */
/*04f0*/ MOV R14, R0 ; /* 0x00000000000e7202 */
/* 0x000fc60000000f00 */
/*0500*/ @P2 LDG.E R16, [R10.64] ; /* 0x000000040a102981 */
/* 0x000168000c1e1900 */
/*0510*/ @P1 LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f1981 */
/* 0x000162000c1e1900 */
/*0520*/ MOV R18, c[0x0][0x180] ; /* 0x0000600000127a02 */
/* 0x000fc60000000f00 */
/*0530*/ @P0 LDG.E R14, [R4.64+-0x4] ; /* 0xfffffc04040e0981 */
/* 0x000162000c1e1900 */
/*0540*/ ISETP.GE.AND P0, PT, R18, 0x2, PT ; /* 0x000000021200780c */
/* 0x000fda0003f06270 */
/*0550*/ @!P0 BRA 0x6d0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0560*/ ISETP.GE.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x001fe20003f06270 */
/*0570*/ IMAD.IADD R11, R8, 0x1, -R7 ; /* 0x00000001080b7824 */
/* 0x000fca00078e0a07 */
/*0580*/ ISETP.GE.AND P1, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fce0003f26270 */
/*0590*/ @P0 IADD3 R8, R6, -R7, RZ ; /* 0x8000000706080210 */
/* 0x000fe20007ffe0ff */
/*05a0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0000 */
/*05b0*/ @P0 IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008080625 */
/* 0x000fc800078e0209 */
/*05c0*/ @!P1 IMAD.WIDE R4, R7, 0x4, R4 ; /* 0x0000000407049825 */
/* 0x000fe200078e0204 */
/*05d0*/ MOV R7, R0 ; /* 0x0000000000077202 */
/* 0x000fe20000000f00 */
/*05e0*/ @P0 LDG.E R6, [R8.64] ; /* 0x0000000408060981 */
/* 0x000eaa000c1e1900 */
/*05f0*/ @!P1 LDG.E R7, [R4.64] ; /* 0x0000000404079981 */
/* 0x000ee2000c1e1900 */
/*0600*/ FADD R11, R17, R16 ; /* 0x00000010110b7221 */
/* 0x020fc80000000000 */
/*0610*/ FADD R10, R11, R14 ; /* 0x0000000e0b0a7221 */
/* 0x000fc80000000000 */
/*0620*/ FADD R13, R10, R15 ; /* 0x0000000f0a0d7221 */
/* 0x000fe40000000000 */
/*0630*/ F2F.F64.F32 R10, R0 ; /* 0x00000000000a7310 */
/* 0x000fe40000201800 */
/*0640*/ FADD R6, R13, R6 ; /* 0x000000060d067221 */
/* 0x004fcc0000000000 */
/*0650*/ F2F.F64.F32 R12, c[0x0][0x184] ; /* 0x00006100000c7b10 */
/* 0x000fe20000201800 */
/*0660*/ FADD R14, R6, R7 ; /* 0x00000007060e7221 */
/* 0x008fce0000000000 */
/*0670*/ F2F.F64.F32 R6, R14 ; /* 0x0000000e00067310 */
/* 0x000e240000201800 */
/*0680*/ DFMA R6, R10, -6, R6 ; /* 0xc01800000a06782b */
/* 0x001e0c0000000006 */
/*0690*/ DFMA R6, R6, R12, R10 ; /* 0x0000000c0606722b */
/* 0x001e14000000000a */
/*06a0*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*06b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*06c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06d0*/ FADD R5, R17, R16 ; /* 0x0000001011057221 */
/* 0x021fe20000000000 */
/*06e0*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x000fe60000201800 */
/*06f0*/ FADD R14, R5, R14 ; /* 0x0000000e050e7221 */
/* 0x000fc80000000000 */
/*0700*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x000fe20000000000 */
/*0710*/ F2F.F64.F32 R8, c[0x0][0x184] ; /* 0x0000610000087b10 */
/* 0x000ff00000201800 */
/*0720*/ F2F.F64.F32 R4, R14 ; /* 0x0000000e00047310 */
/* 0x000e240000201800 */
/*0730*/ DFMA R4, R6, -4, R4 ; /* 0xc01000000604782b */
/* 0x001e0c0000000004 */
/*0740*/ DFMA R4, R4, R8, R6 ; /* 0x000000080404722b */
/* 0x001e140000000006 */
/*0750*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*0760*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0790*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07a0*/ BRA 0x7a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <fstream>
#include <cmath>
#include <cstdlib>
#include <string>
#include <iomanip>
#define T_P_B 1024
///////////////////////////// Global variables /////////////////////////////////
std::string dimension; // grid dimension
float k; // k-step
int timesteps; // num of timesteps
int width, height, depth; // grid size
float startTemp, fixedTemp; // node start temp
int heat_x, heat_y, heat_z, // fixed heater vars
heat_w, heat_h, heat_d;
float *d_old, *d_new, *d_heaters, // grids for values
*g_old, *g_new, *heaters;
///////////////////////////// CUDA Functions ///////////////////////////////////
__global__ void heat_sim(float *oldg, float * newg, float *fixed,
int width, int height, int depth, float k)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
float left, right, up, down, above, below;
float old = oldg[idx];
if (idx < (width*height*depth))
{
if (fixed[idx] != 0) newg[idx] = fixed[idx];
else if (fixed[idx] == 0)
{
// x-, x+
((idx%width) == 0) ? (left = old) : (left = oldg[idx-1]);
((idx%width) == (width-1)) ? (right = old) : (right = oldg[idx+1]);
// y-, y+
(idx%(width*height) < width) ? (up = old) : (up = oldg[idx - width]);
(idx%(width*height) >= ((height-1)*width))
? (down = old) : (down = oldg[idx + width]);
// z-, z+
if (depth <= 1)
{
above = 0.0;
below = 0.0;
newg[idx] = oldg[idx] + k*(up+down+left+right-(4.0*oldg[idx]));
}
else if (depth > 1)
{
if (idx < (width*height)) above = old;
else above = oldg[idx - (width*height)];
if (idx >= ((depth-1)*(width*height))) below = old;
else below = oldg[idx + (width*height)];
newg[idx] = oldg[idx] + k*(up+down+left
+right+above+below-(6.0*oldg[idx]));
}
}
}
}
__global__ void grid_cpy(float *oldg, float *newg, int size)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < size)
oldg[idx] = newg[idx];
}
///////////////////////////// End CUDA Functions ///////////////////////////////
int main(int argc, char * argv[])
{
///////////////////////////// Config file parser ///////////////////////////////
std::ifstream conf(argv[1]);
if (conf.is_open())
{
std::string line;
while (getline(conf, line)){
if ((line[0] == '#') || line.empty() || line[0] == '\r')
continue;
// get dimension
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
dimension = line.substr(0,2);
// get k value
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
k = std::stof(line);
// get timesteps
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
timesteps = std::stoi(line);
// get grid size
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
int comma = line.find(',');
width = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
if (dimension == "2D"){
height = std::stoi(line);
depth = 1;
}
else if (dimension == "3D"){
comma = line.find(',');
height = std::stoi(line.substr(0, comma));
depth = std::stoi(line.substr(comma+1));
}
// get block start temp
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
startTemp = std::stof(line);
// create heaters
heaters = new float[width*height*depth];
std::fill(heaters, heaters+(width*height*depth), 0);
while(getline(conf, line)){
if (line[0] == '#' || line.empty() || line[0] == '\r')
continue;
int comma = line.find(',');
heat_x = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_y = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
if (dimension == "2D"){
heat_w = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_h = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
heat_d = 1;
heat_z = 0;
fixedTemp = std::stof(line);
}
else if (dimension == "3D"){
heat_z = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_w = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_h = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_d = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
fixedTemp = std::stof(line);
}
for (int i = heat_x+width*heat_y;
i < heat_x+heat_w+width*heat_y; i++)
for (int j = 0; j < heat_h; j++)
for (int k = heat_z; k < heat_z+heat_d; k++)
heaters[i+(j*width)+(k*width*height)] = fixedTemp;
}
}
}
else std::cerr << "Couldn't open config file.";
////////////////////////// End config file parser //////////////////////////////
int dim = width*height*depth;
// set up host grids
g_old = new float[dim];
g_new = new float[dim];
std::fill(g_new, g_new+dim, 0);
std::fill(g_old, g_old+dim, 0);
for (int i = 0; i < dim; i++)
{
g_old[i] = startTemp;
if (heaters[i] != 0) g_old[i] = heaters[i];
}
// allocate blockSize - must be at least one block
int blockSize = ceil(float(dim)/float(T_P_B));
// allocate device memory in 1D array
cudaMalloc((void**)&d_new, dim*sizeof(float));
cudaMalloc((void**)&d_old, dim*sizeof(float));
cudaMalloc((void**)&d_heaters, dim*sizeof(float));
// copy filled arrays from host to device
cudaMemcpy(d_old, g_old, dim*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_new, g_new, dim*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_heaters, heaters, dim*sizeof(float), cudaMemcpyHostToDevice);
// run kernels
for (int t = 0; t < timesteps; t++)
{
heat_sim<<<blockSize, T_P_B>>> (d_old, d_new, d_heaters,
width, height, depth, k);
cudaDeviceSynchronize();
grid_cpy<<< blockSize, T_P_B>>> (d_old, d_new, dim);
cudaDeviceSynchronize();
}
// copy data back from device to host
cudaMemcpy(g_new, d_new, dim*sizeof(float), cudaMemcpyDeviceToHost);
// print out to csv
std::ofstream csv("../heatOutput.csv", std::ios::out);
if (csv.is_open()){
for (int i = 0; i < dim; i++)
{
if (i%width == width-1) csv << g_new[i] << std::endl;
else csv << g_new[i] << ", ";
if (i%(width*height) == (width*height)-1) csv << std::endl;
}
}
else
std::cout << "Unable to open file, try again." << std::endl;
csv.close();
// deallocate all memory
delete[] g_old;
delete[] g_new;
delete[] heaters;
cudaFree(d_old);
cudaFree(d_new);
cudaFree(d_heaters);
} | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <cmath>
#include <cstdlib>
#include <string>
#include <iomanip>
#define T_P_B 1024
///////////////////////////// Global variables /////////////////////////////////
std::string dimension; // grid dimension
float k; // k-step
int timesteps; // num of timesteps
int width, height, depth; // grid size
float startTemp, fixedTemp; // node start temp
int heat_x, heat_y, heat_z, // fixed heater vars
heat_w, heat_h, heat_d;
float *d_old, *d_new, *d_heaters, // grids for values
*g_old, *g_new, *heaters;
///////////////////////////// CUDA Functions ///////////////////////////////////
__global__ void heat_sim(float *oldg, float * newg, float *fixed,
int width, int height, int depth, float k)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
float left, right, up, down, above, below;
float old = oldg[idx];
if (idx < (width*height*depth))
{
if (fixed[idx] != 0) newg[idx] = fixed[idx];
else if (fixed[idx] == 0)
{
// x-, x+
((idx%width) == 0) ? (left = old) : (left = oldg[idx-1]);
((idx%width) == (width-1)) ? (right = old) : (right = oldg[idx+1]);
// y-, y+
(idx%(width*height) < width) ? (up = old) : (up = oldg[idx - width]);
(idx%(width*height) >= ((height-1)*width))
? (down = old) : (down = oldg[idx + width]);
// z-, z+
if (depth <= 1)
{
above = 0.0;
below = 0.0;
newg[idx] = oldg[idx] + k*(up+down+left+right-(4.0*oldg[idx]));
}
else if (depth > 1)
{
if (idx < (width*height)) above = old;
else above = oldg[idx - (width*height)];
if (idx >= ((depth-1)*(width*height))) below = old;
else below = oldg[idx + (width*height)];
newg[idx] = oldg[idx] + k*(up+down+left
+right+above+below-(6.0*oldg[idx]));
}
}
}
}
__global__ void grid_cpy(float *oldg, float *newg, int size)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < size)
oldg[idx] = newg[idx];
}
///////////////////////////// End CUDA Functions ///////////////////////////////
int main(int argc, char * argv[])
{
///////////////////////////// Config file parser ///////////////////////////////
std::ifstream conf(argv[1]);
if (conf.is_open())
{
std::string line;
while (getline(conf, line)){
if ((line[0] == '#') || line.empty() || line[0] == '\r')
continue;
// get dimension
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
dimension = line.substr(0,2);
// get k value
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
k = std::stof(line);
// get timesteps
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
timesteps = std::stoi(line);
// get grid size
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
int comma = line.find(',');
width = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
if (dimension == "2D"){
height = std::stoi(line);
depth = 1;
}
else if (dimension == "3D"){
comma = line.find(',');
height = std::stoi(line.substr(0, comma));
depth = std::stoi(line.substr(comma+1));
}
// get block start temp
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
startTemp = std::stof(line);
// create heaters
heaters = new float[width*height*depth];
std::fill(heaters, heaters+(width*height*depth), 0);
while(getline(conf, line)){
if (line[0] == '#' || line.empty() || line[0] == '\r')
continue;
int comma = line.find(',');
heat_x = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_y = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
if (dimension == "2D"){
heat_w = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_h = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
heat_d = 1;
heat_z = 0;
fixedTemp = std::stof(line);
}
else if (dimension == "3D"){
heat_z = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_w = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_h = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_d = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
fixedTemp = std::stof(line);
}
for (int i = heat_x+width*heat_y;
i < heat_x+heat_w+width*heat_y; i++)
for (int j = 0; j < heat_h; j++)
for (int k = heat_z; k < heat_z+heat_d; k++)
heaters[i+(j*width)+(k*width*height)] = fixedTemp;
}
}
}
else std::cerr << "Couldn't open config file.";
////////////////////////// End config file parser //////////////////////////////
int dim = width*height*depth;
// set up host grids
g_old = new float[dim];
g_new = new float[dim];
std::fill(g_new, g_new+dim, 0);
std::fill(g_old, g_old+dim, 0);
for (int i = 0; i < dim; i++)
{
g_old[i] = startTemp;
if (heaters[i] != 0) g_old[i] = heaters[i];
}
// allocate blockSize - must be at least one block
int blockSize = ceil(float(dim)/float(T_P_B));
// allocate device memory in 1D array
hipMalloc((void**)&d_new, dim*sizeof(float));
hipMalloc((void**)&d_old, dim*sizeof(float));
hipMalloc((void**)&d_heaters, dim*sizeof(float));
// copy filled arrays from host to device
hipMemcpy(d_old, g_old, dim*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_new, g_new, dim*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_heaters, heaters, dim*sizeof(float), hipMemcpyHostToDevice);
// run kernels
for (int t = 0; t < timesteps; t++)
{
heat_sim<<<blockSize, T_P_B>>> (d_old, d_new, d_heaters,
width, height, depth, k);
hipDeviceSynchronize();
grid_cpy<<< blockSize, T_P_B>>> (d_old, d_new, dim);
hipDeviceSynchronize();
}
// copy data back from device to host
hipMemcpy(g_new, d_new, dim*sizeof(float), hipMemcpyDeviceToHost);
// print out to csv
std::ofstream csv("../heatOutput.csv", std::ios::out);
if (csv.is_open()){
for (int i = 0; i < dim; i++)
{
if (i%width == width-1) csv << g_new[i] << std::endl;
else csv << g_new[i] << ", ";
if (i%(width*height) == (width*height)-1) csv << std::endl;
}
}
else
std::cout << "Unable to open file, try again." << std::endl;
csv.close();
// deallocate all memory
delete[] g_old;
delete[] g_new;
delete[] heaters;
hipFree(d_old);
hipFree(d_new);
hipFree(d_heaters);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <iostream>
#include <fstream>
#include <cmath>
#include <cstdlib>
#include <string>
#include <iomanip>
#define T_P_B 1024
///////////////////////////// Global variables /////////////////////////////////
std::string dimension; // grid dimension
float k; // k-step
int timesteps; // num of timesteps
int width, height, depth; // grid size
float startTemp, fixedTemp; // node start temp
int heat_x, heat_y, heat_z, // fixed heater vars
heat_w, heat_h, heat_d;
float *d_old, *d_new, *d_heaters, // grids for values
*g_old, *g_new, *heaters;
///////////////////////////// CUDA Functions ///////////////////////////////////
__global__ void heat_sim(float *oldg, float * newg, float *fixed,
int width, int height, int depth, float k)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
float left, right, up, down, above, below;
float old = oldg[idx];
if (idx < (width*height*depth))
{
if (fixed[idx] != 0) newg[idx] = fixed[idx];
else if (fixed[idx] == 0)
{
// x-, x+
((idx%width) == 0) ? (left = old) : (left = oldg[idx-1]);
((idx%width) == (width-1)) ? (right = old) : (right = oldg[idx+1]);
// y-, y+
(idx%(width*height) < width) ? (up = old) : (up = oldg[idx - width]);
(idx%(width*height) >= ((height-1)*width))
? (down = old) : (down = oldg[idx + width]);
// z-, z+
if (depth <= 1)
{
above = 0.0;
below = 0.0;
newg[idx] = oldg[idx] + k*(up+down+left+right-(4.0*oldg[idx]));
}
else if (depth > 1)
{
if (idx < (width*height)) above = old;
else above = oldg[idx - (width*height)];
if (idx >= ((depth-1)*(width*height))) below = old;
else below = oldg[idx + (width*height)];
newg[idx] = oldg[idx] + k*(up+down+left
+right+above+below-(6.0*oldg[idx]));
}
}
}
}
__global__ void grid_cpy(float *oldg, float *newg, int size)
{
int idx = threadIdx.x + blockIdx.x * blockDim.x;
if (idx < size)
oldg[idx] = newg[idx];
}
///////////////////////////// End CUDA Functions ///////////////////////////////
int main(int argc, char * argv[])
{
///////////////////////////// Config file parser ///////////////////////////////
std::ifstream conf(argv[1]);
if (conf.is_open())
{
std::string line;
while (getline(conf, line)){
if ((line[0] == '#') || line.empty() || line[0] == '\r')
continue;
// get dimension
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
dimension = line.substr(0,2);
// get k value
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
k = std::stof(line);
// get timesteps
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
timesteps = std::stoi(line);
// get grid size
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
int comma = line.find(',');
width = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
if (dimension == "2D"){
height = std::stoi(line);
depth = 1;
}
else if (dimension == "3D"){
comma = line.find(',');
height = std::stoi(line.substr(0, comma));
depth = std::stoi(line.substr(comma+1));
}
// get block start temp
getline(conf, line);
while ((line[0] == '#') || line.empty() || line[0] == '\r')
getline(conf,line);
startTemp = std::stof(line);
// create heaters
heaters = new float[width*height*depth];
std::fill(heaters, heaters+(width*height*depth), 0);
while(getline(conf, line)){
if (line[0] == '#' || line.empty() || line[0] == '\r')
continue;
int comma = line.find(',');
heat_x = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_y = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
if (dimension == "2D"){
heat_w = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_h = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
heat_d = 1;
heat_z = 0;
fixedTemp = std::stof(line);
}
else if (dimension == "3D"){
heat_z = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_w = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_h = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
comma = line.find(',');
heat_d = std::stoi(line.substr(0, comma));
line = line.substr(comma+1);
fixedTemp = std::stof(line);
}
for (int i = heat_x+width*heat_y;
i < heat_x+heat_w+width*heat_y; i++)
for (int j = 0; j < heat_h; j++)
for (int k = heat_z; k < heat_z+heat_d; k++)
heaters[i+(j*width)+(k*width*height)] = fixedTemp;
}
}
}
else std::cerr << "Couldn't open config file.";
////////////////////////// End config file parser //////////////////////////////
int dim = width*height*depth;
// set up host grids
g_old = new float[dim];
g_new = new float[dim];
std::fill(g_new, g_new+dim, 0);
std::fill(g_old, g_old+dim, 0);
for (int i = 0; i < dim; i++)
{
g_old[i] = startTemp;
if (heaters[i] != 0) g_old[i] = heaters[i];
}
// allocate blockSize - must be at least one block
int blockSize = ceil(float(dim)/float(T_P_B));
// allocate device memory in 1D array
hipMalloc((void**)&d_new, dim*sizeof(float));
hipMalloc((void**)&d_old, dim*sizeof(float));
hipMalloc((void**)&d_heaters, dim*sizeof(float));
// copy filled arrays from host to device
hipMemcpy(d_old, g_old, dim*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_new, g_new, dim*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_heaters, heaters, dim*sizeof(float), hipMemcpyHostToDevice);
// run kernels
for (int t = 0; t < timesteps; t++)
{
heat_sim<<<blockSize, T_P_B>>> (d_old, d_new, d_heaters,
width, height, depth, k);
hipDeviceSynchronize();
grid_cpy<<< blockSize, T_P_B>>> (d_old, d_new, dim);
hipDeviceSynchronize();
}
// copy data back from device to host
hipMemcpy(g_new, d_new, dim*sizeof(float), hipMemcpyDeviceToHost);
// print out to csv
std::ofstream csv("../heatOutput.csv", std::ios::out);
if (csv.is_open()){
for (int i = 0; i < dim; i++)
{
if (i%width == width-1) csv << g_new[i] << std::endl;
else csv << g_new[i] << ", ";
if (i%(width*height) == (width*height)-1) csv << std::endl;
}
}
else
std::cout << "Unable to open file, try again." << std::endl;
csv.close();
// deallocate all memory
delete[] g_old;
delete[] g_new;
delete[] heaters;
hipFree(d_old);
hipFree(d_new);
hipFree(d_heaters);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8heat_simPfS_S_iiif
.globl _Z8heat_simPfS_S_iiif
.p2align 8
.type _Z8heat_simPfS_S_iiif,@function
_Z8heat_simPfS_S_iiif:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s9, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s8, s5, s4
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s8, s9
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_23
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, -1
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 0, v7
s_cbranch_execz .LBB0_21
v_cmp_eq_f32_e32 vcc_lo, 0, v7
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_20
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_ashr_i32 s10, s4, 31
v_ashrrev_i32_e32 v7, 31, v1
s_add_i32 s11, s4, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s10, s11, s10
v_cvt_f32_u32_e32 v5, s10
s_sub_i32 s11, 0, s10
v_add_nc_u32_e32 v8, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
v_xor_b32_e32 v8, v8, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
global_load_b32 v0, v[3:4], off
v_cvt_u32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s11, v5
v_mul_hi_u32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v6
v_mul_hi_u32 v5, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s10
v_sub_nc_u32_e32 v5, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s10, v5
v_cmp_le_u32_e32 vcc_lo, s10, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s10, v5
v_cmp_le_u32_e32 vcc_lo, s10, v5
s_mov_b32 s10, exec_lo
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v7
v_sub_nc_u32_e32 v6, v5, v7
s_waitcnt vmcnt(0)
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_ne_u32_e32 0, v6
s_cbranch_execz .LBB0_5
global_load_b32 v5, v[3:4], off offset:-4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s10, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s10, v6
v_mov_b32_e32 v6, v0
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_7
global_load_b32 v6, v[3:4], off offset:4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s10
s_ashr_i32 s10, s8, 31
v_ashrrev_i32_e32 v7, 31, v1
s_add_i32 s11, s8, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s10, s11, s10
v_add_nc_u32_e32 v8, v1, v7
v_cvt_f32_u32_e32 v3, s10
s_sub_i32 s11, 0, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v8, v8, v7
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v4, s11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v4
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v8, v3
v_mul_lo_u32 v3, v3, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v8, v3
v_subrev_nc_u32_e32 v4, s10, v3
v_cmp_le_u32_e32 vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s10, v3
v_cmp_le_u32_e32 vcc_lo, s10, v3
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_xor_b32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v3, v7
v_mov_b32_e32 v3, v0
v_cmpx_le_i32_e64 s4, v4
s_cbranch_execz .LBB0_9
v_subrev_nc_u32_e32 v7, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v3, v[7:8], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s5, s4
v_cmp_gt_i32_e32 vcc_lo, s5, v4
v_mov_b32_e32 v4, v0
s_mov_b32 s5, -1
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v7, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v4, v[7:8], off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s10
s_load_b32 s4, s[0:1], 0x24
s_cmp_gt_i32 s9, 1
s_cbranch_scc0 .LBB0_17
v_mov_b32_e32 v7, v0
s_mov_b32 s5, exec_lo
v_cmpx_le_i32_e64 s8, v1
s_cbranch_execz .LBB0_14
v_subrev_nc_u32_e32 v7, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v7, v[7:8], off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s5, s9, -1
v_mov_b32_e32 v8, v0
s_mul_i32 s5, s5, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_16
v_add_nc_u32_e32 v8, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v8, v[8:9], off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, v3, v4
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[11:12], s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v5, v9
v_add_f32_e32 v9, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v9, v7
v_add_f32_e32 v9, v7, v8
v_cvt_f64_f32_e32 v[7:8], v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[9:10], v9
v_fma_f64 v[9:10], v[7:8], 0xc0180000, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[9:10], v[11:12], v[7:8]
v_cvt_f32_f64_e32 v7, v[7:8]
s_branch .LBB0_19
.LBB0_17:
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccz .LBB0_19
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[7:8], s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v5, v3
v_add_f32_e32 v5, v6, v3
v_cvt_f64_f32_e32 v[3:4], v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[5:6], v5
v_fma_f64 v[5:6], v[3:4], -4.0, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[5:6], v[7:8], v[3:4]
v_cvt_f32_f64_e32 v7, v[3:4]
.LBB0_19:
s_mov_b32 s2, exec_lo
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s3, s2, exec_lo
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_23
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v7, off
.LBB0_23:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8heat_simPfS_S_iiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8heat_simPfS_S_iiif, .Lfunc_end0-_Z8heat_simPfS_S_iiif
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8grid_cpyPfS_i
.globl _Z8grid_cpyPfS_i
.p2align 8
.type _Z8grid_cpyPfS_i,@function
_Z8grid_cpyPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8grid_cpyPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8grid_cpyPfS_i, .Lfunc_end1-_Z8grid_cpyPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8heat_simPfS_S_iiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8heat_simPfS_S_iiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8grid_cpyPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8grid_cpyPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8grid_cpyPfS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e280000002100 */
/*0020*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e240000002500 */
/*0030*/ IMAD R4, R3, c[0x0][0x0], R4 ; /* 0x0000000003047a24 */
/* 0x001fca00078e0204 */
/*0040*/ ISETP.GE.AND P0, PT, R4, c[0x0][0x170], PT ; /* 0x00005c0004007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0080*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00a0*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0205 */
/*00b0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00d0*/ BRA 0xd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z8heat_simPfS_S_iiif
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R6, SR_CTAID.X ; /* 0x0000000000067919 */
/* 0x000e220000002500 */
/*0020*/ IMAD.MOV.U32 R7, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff077624 */
/* 0x000fc600078e00ff */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e220000002100 */
/*0040*/ IMAD R7, R7, c[0x0][0x178], RZ ; /* 0x00005e0007077a24 */
/* 0x000fc800078e02ff */
/*0050*/ IMAD R8, R7, c[0x0][0x180], RZ ; /* 0x0000600007087a24 */
/* 0x000fe400078e02ff */
/*0060*/ IMAD R6, R6, c[0x0][0x0], R3 ; /* 0x0000000006067a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R6, R8, PT ; /* 0x000000080600720c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0090*/ SHF.R.S32.HI R3, RZ, 0x1f, R6 ; /* 0x0000001fff037819 */
/* 0x000fe20000011406 */
/*00a0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00b0*/ SHF.L.U32 R2, R6.reuse, 0x2, RZ ; /* 0x0000000206027819 */
/* 0x040fe400000006ff */
/*00c0*/ SHF.L.U64.HI R3, R6, 0x2, R3 ; /* 0x0000000206037819 */
/* 0x000fe40000010203 */
/*00d0*/ IADD3 R4, P0, R2, c[0x0][0x170], RZ ; /* 0x00005c0002047a10 */
/* 0x000fc80007f1e0ff */
/*00e0*/ IADD3.X R5, R3, c[0x0][0x174], RZ, P0, !PT ; /* 0x00005d0003057a10 */
/* 0x000fcc00007fe4ff */
/*00f0*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0100*/ IADD3 R2, P1, R2, c[0x0][0x168], RZ ; /* 0x00005a0002027a10 */
/* 0x000fc80007f3e0ff */
/*0110*/ IADD3.X R3, R3, c[0x0][0x16c], RZ, P1, !PT ; /* 0x00005b0003037a10 */
/* 0x000fe40000ffe4ff */
/*0120*/ FSETP.NEU.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720b */
/* 0x004fda0003f0d000 */
/*0130*/ @P0 BRA 0x780 ; /* 0x0000064000000947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.MOV.U32 R9, RZ, RZ, 0x4 ; /* 0x00000004ff097424 */
/* 0x000fc800078e00ff */
/*0150*/ IMAD.WIDE R4, R6, R9, c[0x0][0x160] ; /* 0x0000580006047625 */
/* 0x000fca00078e0209 */
/*0160*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x000ea2000c1e1900 */
/*0170*/ IABS R10, R7 ; /* 0x00000007000a7213 */
/* 0x000fe40000000000 */
/*0180*/ IABS R11, c[0x0][0x178] ; /* 0x00005e00000b7a13 */
/* 0x000fe40000000000 */
/*0190*/ I2F.RP R17, R10 ; /* 0x0000000a00117306 */
/* 0x000e220000209400 */
/*01a0*/ ISETP.NE.AND P2, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fce0003f45270 */
/*01b0*/ I2F.RP R16, R11 ; /* 0x0000000b00107306 */
/* 0x000e700000209400 */
/*01c0*/ MUFU.RCP R17, R17 ; /* 0x0000001100117308 */
/* 0x001e300000001000 */
/*01d0*/ MUFU.RCP R16, R16 ; /* 0x0000001000107308 */
/* 0x002e620000001000 */
/*01e0*/ IADD3 R14, R17, 0xffffffe, RZ ; /* 0x0ffffffe110e7810 */
/* 0x001fc40007ffe0ff */
/*01f0*/ IABS R17, R6 ; /* 0x0000000600117213 */
/* 0x000fca0000000000 */
/*0200*/ F2I.FTZ.U32.TRUNC.NTZ R15, R14 ; /* 0x0000000e000f7305 */
/* 0x0000e2000021f000 */
/*0210*/ IADD3 R12, R16, 0xffffffe, RZ ; /* 0x0ffffffe100c7810 */
/* 0x002fe40007ffe0ff */
/*0220*/ IABS R16, R7 ; /* 0x0000000700107213 */
/* 0x000fca0000000000 */
/*0230*/ F2I.FTZ.U32.TRUNC.NTZ R13, R12 ; /* 0x0000000c000d7305 */
/* 0x000322000021f000 */
/*0240*/ IMAD.MOV.U32 R14, RZ, RZ, RZ ; /* 0x000000ffff0e7224 */
/* 0x001fe400078e00ff */
/*0250*/ IMAD.MOV R16, RZ, RZ, -R16 ; /* 0x000000ffff107224 */
/* 0x000fe400078e0a10 */
/*0260*/ IMAD.MOV R19, RZ, RZ, -R15 ; /* 0x000000ffff137224 */
/* 0x008fe200078e0a0f */
/*0270*/ HFMA2.MMA R12, -RZ, RZ, 0, 0 ; /* 0x00000000ff0c7435 */
/* 0x002fc600000001ff */
/*0280*/ IMAD R19, R19, R10, RZ ; /* 0x0000000a13137224 */
/* 0x000fe200078e02ff */
/*0290*/ IADD3 R18, RZ, -R13, RZ ; /* 0x8000000dff127210 */
/* 0x010fc60007ffe0ff */
/*02a0*/ IMAD.HI.U32 R14, R15, R19, R14 ; /* 0x000000130f0e7227 */
/* 0x000fc800078e000e */
/*02b0*/ IMAD R15, R18, R11, RZ ; /* 0x0000000b120f7224 */
/* 0x000fe400078e02ff */
/*02c0*/ IMAD.HI.U32 R14, R14, R17, RZ ; /* 0x000000110e0e7227 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.HI.U32 R12, R13, R15, R12 ; /* 0x0000000f0d0c7227 */
/* 0x000fc800078e000c */
/*02e0*/ IMAD.MOV.U32 R13, RZ, RZ, R16 ; /* 0x000000ffff0d7224 */
/* 0x000fe400078e0010 */
/*02f0*/ IMAD.HI.U32 R12, R12, R17, RZ ; /* 0x000000110c0c7227 */
/* 0x000fc800078e00ff */
/*0300*/ IMAD R13, R14, R13, R17 ; /* 0x0000000d0e0d7224 */
/* 0x000fe400078e0211 */
/*0310*/ IMAD.MOV R12, RZ, RZ, -R12 ; /* 0x000000ffff0c7224 */
/* 0x000fc600078e0a0c */
/*0320*/ ISETP.GT.U32.AND P1, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fe20003f24070 */
/*0330*/ IMAD R12, R11, R12, R17 ; /* 0x0000000c0b0c7224 */
/* 0x000fca00078e0211 */
/*0340*/ ISETP.GT.U32.AND P0, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fce0003f04070 */
/*0350*/ @!P1 IADD3 R13, R13, -R10, RZ ; /* 0x8000000a0d0d9210 */
/* 0x000fc80007ffe0ff */
/*0360*/ ISETP.GT.U32.AND P1, PT, R10, R13, PT ; /* 0x0000000d0a00720c */
/* 0x000fe40003f24070 */
/*0370*/ @!P0 IMAD.IADD R12, R12, 0x1, -R11 ; /* 0x000000010c0c8824 */
/* 0x000fe200078e0a0b */
/*0380*/ ISETP.GE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fc80003f06270 */
/*0390*/ ISETP.GT.U32.AND P3, PT, R11, R12, PT ; /* 0x0000000c0b00720c */
/* 0x000fcc0003f64070 */
/*03a0*/ @!P1 IMAD.IADD R13, R13, 0x1, -R10 ; /* 0x000000010d0d9824 */
/* 0x000fe200078e0a0a */
/*03b0*/ ISETP.NE.AND P1, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe40003f25270 */
/*03c0*/ IADD3 R10, R7, -c[0x0][0x178], RZ ; /* 0x80005e00070a7a10 */
/* 0x000fe40007ffe0ff */
/*03d0*/ @!P0 IADD3 R13, -R13, RZ, RZ ; /* 0x000000ff0d0d8210 */
/* 0x000fe40007ffe1ff */
/*03e0*/ @!P2 LOP3.LUT R13, RZ, R7, RZ, 0x33, !PT ; /* 0x00000007ff0da212 */
/* 0x000fe200078e33ff */
/*03f0*/ @!P3 IMAD.IADD R12, R12, 0x1, -R11 ; /* 0x000000010c0cb824 */
/* 0x000fc600078e0a0b */
/*0400*/ ISETP.GE.AND P2, PT, R13.reuse, c[0x0][0x178], PT ; /* 0x00005e000d007a0c */
/* 0x040fe40003f46270 */
/*0410*/ ISETP.GE.AND P3, PT, R13, R10, PT ; /* 0x0000000a0d00720c */
/* 0x000fe20003f66270 */
/*0420*/ IMAD.MOV.U32 R13, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff0d7624 */
/* 0x000fe200078e00ff */
/*0430*/ @!P0 IADD3 R12, -R12, RZ, RZ ; /* 0x000000ff0c0c8210 */
/* 0x000fe40007ffe1ff */
/*0440*/ @!P1 LOP3.LUT R12, RZ, c[0x0][0x178], RZ, 0x33, !PT ; /* 0x00005e00ff0c9a12 */
/* 0x000fe400078e33ff */
/*0450*/ IADD3 R10, R13, -0x1, RZ ; /* 0xffffffff0d0a7810 */
/* 0x000fe40007ffe0ff */
/*0460*/ ISETP.NE.AND P0, PT, R12, RZ, PT ; /* 0x000000ff0c00720c */
/* 0x000fc40003f05270 */
/*0470*/ ISETP.NE.AND P1, PT, R12, R10, PT ; /* 0x0000000a0c00720c */
/* 0x000fe40003f25270 */
/*0480*/ @P2 IADD3 R10, R6, -c[0x0][0x178], RZ ; /* 0x80005e00060a2a10 */
/* 0x000fe20007ffe0ff */
/*0490*/ @!P3 IMAD.WIDE R12, R13, 0x4, R4 ; /* 0x000000040d0cb825 */
/* 0x000fc800078e0204 */
/*04a0*/ @P2 IMAD.WIDE R10, R10, R9, c[0x0][0x160] ; /* 0x000058000a0a2625 */
/* 0x000fc800078e0209 */
/*04b0*/ IMAD.MOV.U32 R17, RZ, RZ, R0.reuse ; /* 0x000000ffff117224 */
/* 0x104fe400078e0000 */
/*04c0*/ IMAD.MOV.U32 R16, RZ, RZ, R0.reuse ; /* 0x000000ffff107224 */
/* 0x100fe400078e0000 */
/*04d0*/ IMAD.MOV.U32 R15, RZ, RZ, R0 ; /* 0x000000ffff0f7224 */
/* 0x000fe400078e0000 */
/*04e0*/ @!P3 LDG.E R17, [R12.64] ; /* 0x000000040c11b981 */
/* 0x000162000c1e1900 */
/*04f0*/ MOV R14, R0 ; /* 0x00000000000e7202 */
/* 0x000fc60000000f00 */
/*0500*/ @P2 LDG.E R16, [R10.64] ; /* 0x000000040a102981 */
/* 0x000168000c1e1900 */
/*0510*/ @P1 LDG.E R15, [R4.64+0x4] ; /* 0x00000404040f1981 */
/* 0x000162000c1e1900 */
/*0520*/ MOV R18, c[0x0][0x180] ; /* 0x0000600000127a02 */
/* 0x000fc60000000f00 */
/*0530*/ @P0 LDG.E R14, [R4.64+-0x4] ; /* 0xfffffc04040e0981 */
/* 0x000162000c1e1900 */
/*0540*/ ISETP.GE.AND P0, PT, R18, 0x2, PT ; /* 0x000000021200780c */
/* 0x000fda0003f06270 */
/*0550*/ @!P0 BRA 0x6d0 ; /* 0x0000017000008947 */
/* 0x000fea0003800000 */
/*0560*/ ISETP.GE.AND P0, PT, R6, R7, PT ; /* 0x000000070600720c */
/* 0x001fe20003f06270 */
/*0570*/ IMAD.IADD R11, R8, 0x1, -R7 ; /* 0x00000001080b7824 */
/* 0x000fca00078e0a07 */
/*0580*/ ISETP.GE.AND P1, PT, R6, R11, PT ; /* 0x0000000b0600720c */
/* 0x000fce0003f26270 */
/*0590*/ @P0 IADD3 R8, R6, -R7, RZ ; /* 0x8000000706080210 */
/* 0x000fe20007ffe0ff */
/*05a0*/ IMAD.MOV.U32 R6, RZ, RZ, R0 ; /* 0x000000ffff067224 */
/* 0x000fc800078e0000 */
/*05b0*/ @P0 IMAD.WIDE R8, R8, R9, c[0x0][0x160] ; /* 0x0000580008080625 */
/* 0x000fc800078e0209 */
/*05c0*/ @!P1 IMAD.WIDE R4, R7, 0x4, R4 ; /* 0x0000000407049825 */
/* 0x000fe200078e0204 */
/*05d0*/ MOV R7, R0 ; /* 0x0000000000077202 */
/* 0x000fe20000000f00 */
/*05e0*/ @P0 LDG.E R6, [R8.64] ; /* 0x0000000408060981 */
/* 0x000eaa000c1e1900 */
/*05f0*/ @!P1 LDG.E R7, [R4.64] ; /* 0x0000000404079981 */
/* 0x000ee2000c1e1900 */
/*0600*/ FADD R11, R17, R16 ; /* 0x00000010110b7221 */
/* 0x020fc80000000000 */
/*0610*/ FADD R10, R11, R14 ; /* 0x0000000e0b0a7221 */
/* 0x000fc80000000000 */
/*0620*/ FADD R13, R10, R15 ; /* 0x0000000f0a0d7221 */
/* 0x000fe40000000000 */
/*0630*/ F2F.F64.F32 R10, R0 ; /* 0x00000000000a7310 */
/* 0x000fe40000201800 */
/*0640*/ FADD R6, R13, R6 ; /* 0x000000060d067221 */
/* 0x004fcc0000000000 */
/*0650*/ F2F.F64.F32 R12, c[0x0][0x184] ; /* 0x00006100000c7b10 */
/* 0x000fe20000201800 */
/*0660*/ FADD R14, R6, R7 ; /* 0x00000007060e7221 */
/* 0x008fce0000000000 */
/*0670*/ F2F.F64.F32 R6, R14 ; /* 0x0000000e00067310 */
/* 0x000e240000201800 */
/*0680*/ DFMA R6, R10, -6, R6 ; /* 0xc01800000a06782b */
/* 0x001e0c0000000006 */
/*0690*/ DFMA R6, R6, R12, R10 ; /* 0x0000000c0606722b */
/* 0x001e14000000000a */
/*06a0*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*06b0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe2000c101904 */
/*06c0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06d0*/ FADD R5, R17, R16 ; /* 0x0000001011057221 */
/* 0x021fe20000000000 */
/*06e0*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x000fe60000201800 */
/*06f0*/ FADD R14, R5, R14 ; /* 0x0000000e050e7221 */
/* 0x000fc80000000000 */
/*0700*/ FADD R14, R14, R15 ; /* 0x0000000f0e0e7221 */
/* 0x000fe20000000000 */
/*0710*/ F2F.F64.F32 R8, c[0x0][0x184] ; /* 0x0000610000087b10 */
/* 0x000ff00000201800 */
/*0720*/ F2F.F64.F32 R4, R14 ; /* 0x0000000e00047310 */
/* 0x000e240000201800 */
/*0730*/ DFMA R4, R6, -4, R4 ; /* 0xc01000000604782b */
/* 0x001e0c0000000004 */
/*0740*/ DFMA R4, R4, R8, R6 ; /* 0x000000080404722b */
/* 0x001e140000000006 */
/*0750*/ F2F.F32.F64 R5, R4 ; /* 0x0000000400057310 */
/* 0x001e240000301000 */
/*0760*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101904 */
/*0770*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0780*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0790*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07a0*/ BRA 0x7a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8heat_simPfS_S_iiif
.globl _Z8heat_simPfS_S_iiif
.p2align 8
.type _Z8heat_simPfS_S_iiif,@function
_Z8heat_simPfS_S_iiif:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s9, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_mul_i32 s8, s5, s4
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mul_i32 s2, s8, s9
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s2, v1
s_and_saveexec_b32 s2, vcc_lo
s_cbranch_execz .LBB0_23
s_load_b64 s[2:3], s[0:1], 0x10
v_ashrrev_i32_e32 v2, 31, v1
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_mov_b32 s2, 0
s_mov_b32 s3, -1
global_load_b32 v7, v[3:4], off
s_waitcnt vmcnt(0)
v_cmpx_eq_f32_e32 0, v7
s_cbranch_execz .LBB0_21
v_cmp_eq_f32_e32 vcc_lo, 0, v7
s_and_saveexec_b32 s7, vcc_lo
s_cbranch_execz .LBB0_20
s_load_b64 s[2:3], s[0:1], 0x0
v_lshlrev_b64 v[3:4], 2, v[1:2]
s_ashr_i32 s10, s4, 31
v_ashrrev_i32_e32 v7, 31, v1
s_add_i32 s11, s4, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s10, s11, s10
v_cvt_f32_u32_e32 v5, s10
s_sub_i32 s11, 0, s10
v_add_nc_u32_e32 v8, v1, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_rcp_iflag_f32_e32 v5, v5
v_xor_b32_e32 v8, v8, v7
s_waitcnt lgkmcnt(0)
v_add_co_u32 v3, vcc_lo, s2, v3
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v5, 0x4f7ffffe, v5
global_load_b32 v0, v[3:4], off
v_cvt_u32_f32_e32 v5, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v6, s11, v5
v_mul_hi_u32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v5, v5, v6
v_mul_hi_u32 v5, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_lo_u32 v5, v5, s10
v_sub_nc_u32_e32 v5, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s10, v5
v_cmp_le_u32_e32 vcc_lo, s10, v5
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_subrev_nc_u32_e32 v6, s10, v5
v_cmp_le_u32_e32 vcc_lo, s10, v5
s_mov_b32 s10, exec_lo
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_xor_b32_e32 v5, v5, v7
v_sub_nc_u32_e32 v6, v5, v7
s_waitcnt vmcnt(0)
v_mov_b32_e32 v5, v0
s_delay_alu instid0(VALU_DEP_2)
v_cmpx_ne_u32_e32 0, v6
s_cbranch_execz .LBB0_5
global_load_b32 v5, v[3:4], off offset:-4
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s10, s4, -1
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_ne_u32_e32 vcc_lo, s10, v6
v_mov_b32_e32 v6, v0
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_7
global_load_b32 v6, v[3:4], off offset:4
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s10
s_ashr_i32 s10, s8, 31
v_ashrrev_i32_e32 v7, 31, v1
s_add_i32 s11, s8, s10
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_xor_b32 s10, s11, s10
v_add_nc_u32_e32 v8, v1, v7
v_cvt_f32_u32_e32 v3, s10
s_sub_i32 s11, 0, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_xor_b32_e32 v8, v8, v7
v_rcp_iflag_f32_e32 v3, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v3, 0x4f7ffffe, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v3, v3
v_mul_lo_u32 v4, s11, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v4, v3, v4
v_add_nc_u32_e32 v3, v3, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_hi_u32 v3, v8, v3
v_mul_lo_u32 v3, v3, s10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v3, v8, v3
v_subrev_nc_u32_e32 v4, s10, v3
v_cmp_le_u32_e32 vcc_lo, s10, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_subrev_nc_u32_e32 v4, s10, v3
v_cmp_le_u32_e32 vcc_lo, s10, v3
s_mov_b32 s10, exec_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, v3, v4, vcc_lo
v_xor_b32_e32 v3, v3, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_nc_u32_e32 v4, v3, v7
v_mov_b32_e32 v3, v0
v_cmpx_le_i32_e64 s4, v4
s_cbranch_execz .LBB0_9
v_subrev_nc_u32_e32 v7, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v3, v[7:8], off
.LBB0_9:
s_or_b32 exec_lo, exec_lo, s10
s_add_i32 s5, s5, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s5, s5, s4
v_cmp_gt_i32_e32 vcc_lo, s5, v4
v_mov_b32_e32 v4, v0
s_mov_b32 s5, -1
s_and_saveexec_b32 s10, vcc_lo
s_cbranch_execz .LBB0_11
v_add_nc_u32_e32 v7, s4, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v4, v[7:8], off
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s10
s_load_b32 s4, s[0:1], 0x24
s_cmp_gt_i32 s9, 1
s_cbranch_scc0 .LBB0_17
v_mov_b32_e32 v7, v0
s_mov_b32 s5, exec_lo
v_cmpx_le_i32_e64 s8, v1
s_cbranch_execz .LBB0_14
v_subrev_nc_u32_e32 v7, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v7, v[7:8], off
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s5
s_add_i32 s5, s9, -1
v_mov_b32_e32 v8, v0
s_mul_i32 s5, s5, s8
s_delay_alu instid0(SALU_CYCLE_1)
v_cmp_gt_i32_e32 vcc_lo, s5, v1
s_and_saveexec_b32 s5, vcc_lo
s_cbranch_execz .LBB0_16
v_add_nc_u32_e32 v8, s8, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v9, 31, v8
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v8, vcc_lo, s2, v8
v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
global_load_b32 v8, v[8:9], off
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s5
s_waitcnt vmcnt(0)
v_add_f32_e32 v9, v3, v4
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[11:12], s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v5, v9
v_add_f32_e32 v9, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v9, v7
v_add_f32_e32 v9, v7, v8
v_cvt_f64_f32_e32 v[7:8], v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[9:10], v9
v_fma_f64 v[9:10], v[7:8], 0xc0180000, v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[7:8], v[9:10], v[11:12], v[7:8]
v_cvt_f32_f64_e32 v7, v[7:8]
s_branch .LBB0_19
.LBB0_17:
s_and_b32 vcc_lo, exec_lo, s5
s_cbranch_vccz .LBB0_19
s_waitcnt vmcnt(0)
v_add_f32_e32 v3, v3, v4
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[7:8], s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v5, v3
v_add_f32_e32 v5, v6, v3
v_cvt_f64_f32_e32 v[3:4], v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[5:6], v5
v_fma_f64 v[5:6], v[3:4], -4.0, v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[3:4], v[5:6], v[7:8], v[3:4]
v_cvt_f32_f64_e32 v7, v[3:4]
.LBB0_19:
s_mov_b32 s2, exec_lo
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s7
s_delay_alu instid0(SALU_CYCLE_1)
s_or_not1_b32 s3, s2, exec_lo
.LBB0_21:
s_or_b32 exec_lo, exec_lo, s6
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 exec_lo, exec_lo, s3
s_cbranch_execz .LBB0_23
s_load_b64 s[0:1], s[0:1], 0x8
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v7, off
.LBB0_23:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8heat_simPfS_S_iiif
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 13
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8heat_simPfS_S_iiif, .Lfunc_end0-_Z8heat_simPfS_S_iiif
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z8grid_cpyPfS_i
.globl _Z8grid_cpyPfS_i
.p2align 8
.type _Z8grid_cpyPfS_i,@function
_Z8grid_cpyPfS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB1_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB1_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8grid_cpyPfS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z8grid_cpyPfS_i, .Lfunc_end1-_Z8grid_cpyPfS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8heat_simPfS_S_iiif
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8heat_simPfS_S_iiif.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 13
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8grid_cpyPfS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8grid_cpyPfS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gpu_maskPointCloud(float4* verts, const int width, const int height, const int* mask) {
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= width || y >= height)
return;
const int index = x + y*width;
int m = mask[index];
if (m == 0) {
verts[index].w = -1;
}
} | code for sm_80
Function : _Z18gpu_maskPointCloudP6float4iiPKi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, -0x40800000 ; /* 0xbf800000ff057424 */
/* 0x000fe200078e00ff */
/*0130*/ LEA R2, P0, R0, c[0x0][0x160], 0x4 ; /* 0x0000580000027a11 */
/* 0x000fc800078020ff */
/*0140*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x4, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f2403 */
/*0150*/ STG.E [R2.64+0xc], R5 ; /* 0x00000c0502007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void gpu_maskPointCloud(float4* verts, const int width, const int height, const int* mask) {
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= width || y >= height)
return;
const int index = x + y*width;
int m = mask[index];
if (m == 0) {
verts[index].w = -1;
}
} | .file "tmpxft_00062d11_00000000-6_gpu_maskPointCloud.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi
.type _Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi, @function
_Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18gpu_maskPointCloudP6float4iiPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi, .-_Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi
.globl _Z18gpu_maskPointCloudP6float4iiPKi
.type _Z18gpu_maskPointCloudP6float4iiPKi, @function
_Z18gpu_maskPointCloudP6float4iiPKi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18gpu_maskPointCloudP6float4iiPKi, .-_Z18gpu_maskPointCloudP6float4iiPKi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18gpu_maskPointCloudP6float4iiPKi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18gpu_maskPointCloudP6float4iiPKi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void gpu_maskPointCloud(float4* verts, const int width, const int height, const int* mask) {
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= width || y >= height)
return;
const int index = x + y*width;
int m = mask[index];
if (m == 0) {
verts[index].w = -1;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_maskPointCloud(float4* verts, const int width, const int height, const int* mask) {
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= width || y >= height)
return;
const int index = x + y*width;
int m = mask[index];
if (m == 0) {
verts[index].w = -1;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_maskPointCloud(float4* verts, const int width, const int height, const int* mask) {
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= width || y >= height)
return;
const int index = x + y*width;
int m = mask[index];
if (m == 0) {
verts[index].w = -1;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.globl _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.p2align 8
.type _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi,@function
_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 4, v[0:1]
v_mov_b32_e32 v2, -1.0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off offset:12
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi, .Lfunc_end0-_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void gpu_maskPointCloud(float4* verts, const int width, const int height, const int* mask) {
const int x = blockIdx.x*blockDim.x + threadIdx.x;
const int y = blockIdx.y*blockDim.y + threadIdx.y;
if (x >= width || y >= height)
return;
const int index = x + y*width;
int m = mask[index];
if (m == 0) {
verts[index].w = -1;
}
} | .text
.file "gpu_maskPointCloud.hip"
.globl _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi # -- Begin function _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.p2align 4, 0x90
.type _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi,@function
_Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi: # @_Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi, .Lfunc_end0-_Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi,@object # @_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.section .rodata,"a",@progbits
.globl _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.p2align 3, 0x0
_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi:
.quad _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.size _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z18gpu_maskPointCloudP6float4iiPKi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x16c], PT ; /* 0x00005b0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x168], P0 ; /* 0x00005a0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R3, c[0x0][0x168], R0 ; /* 0x00005a0003007a24 */
/* 0x000fe200078e0200 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x170] ; /* 0x00005c0000027625 */
/* 0x000fcc00078e0205 */
/*00e0*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f05270 */
/*0100*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0110*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe20000011400 */
/*0120*/ IMAD.MOV.U32 R5, RZ, RZ, -0x40800000 ; /* 0xbf800000ff057424 */
/* 0x000fe200078e00ff */
/*0130*/ LEA R2, P0, R0, c[0x0][0x160], 0x4 ; /* 0x0000580000027a11 */
/* 0x000fc800078020ff */
/*0140*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x4, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f2403 */
/*0150*/ STG.E [R2.64+0xc], R5 ; /* 0x00000c0502007986 */
/* 0x000fe2000c101904 */
/*0160*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0170*/ BRA 0x170; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.globl _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.p2align 8
.type _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi,@function
_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x8
v_and_b32_e32 v1, 0x3ff, v0
v_bfe_u32 v0, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
v_mad_u64_u32 v[2:3], null, s14, s3, v[1:2]
v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_i32_e32 vcc_lo, s4, v2
v_cmp_gt_i32_e64 s2, s5, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, vcc_lo, s2
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x10
v_mad_u64_u32 v[0:1], null, v3, s4, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[2:3], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 0, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
v_lshlrev_b64 v[0:1], 4, v[0:1]
v_mov_b32_e32 v2, -1.0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off offset:12
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi, .Lfunc_end0-_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00062d11_00000000-6_gpu_maskPointCloud.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi
.type _Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi, @function
_Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movl %edx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 16(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z18gpu_maskPointCloudP6float4iiPKi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi, .-_Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi
.globl _Z18gpu_maskPointCloudP6float4iiPKi
.type _Z18gpu_maskPointCloudP6float4iiPKi, @function
_Z18gpu_maskPointCloudP6float4iiPKi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z18gpu_maskPointCloudP6float4iiPKiP6float4iiPKi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z18gpu_maskPointCloudP6float4iiPKi, .-_Z18gpu_maskPointCloudP6float4iiPKi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z18gpu_maskPointCloudP6float4iiPKi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z18gpu_maskPointCloudP6float4iiPKi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "gpu_maskPointCloud.hip"
.globl _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi # -- Begin function _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.p2align 4, 0x90
.type _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi,@function
_Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi: # @_Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movl %edx, 8(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 8(%rsp), %rax
movq %rax, 96(%rsp)
leaq 64(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi, .Lfunc_end0-_Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi,@object # @_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.section .rodata,"a",@progbits
.globl _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.p2align 3, 0x0
_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi:
.quad _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.size _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi"
.size .L__unnamed_1, 53
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z33__device_stub__gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z18gpu_maskPointCloudP15HIP_vector_typeIfLj4EEiiPKi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void histo_kernal(char *buffer, long size, int *histo )
{
__shared__ int temp[256];
temp[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
int offset = blockDim.x * gridDim.x;
int z;
while (i < size)
{
z = buffer[i];
atomicAdd( &temp[z], 1);
i += offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
} | code for sm_80
Function : _Z12histo_kernalPclPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ STS [R4.X4], RZ ; /* 0x000000ff04007388 */
/* 0x0011e20000004800 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R4 ; /* 0x0000000003007a24 */
/* 0x002fc600078e0204 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0080*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0090*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06300 */
/*00a0*/ @P0 BRA 0x190 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0002 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0000 */
/*00d0*/ IADD3 R2, P0, R5, c[0x0][0x160], RZ ; /* 0x0000580005027a10 */
/* 0x001fc80007f1e0ff */
/*00e0*/ IADD3.X R3, R6, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590006037a10 */
/* 0x000fca00007fe4ff */
/*00f0*/ LDG.E.S8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1300 */
/*0100*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*0110*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0120*/ IMAD R5, R5, c[0x0][0xc], R0 ; /* 0x0000030005057a24 */
/* 0x000fc800078e0200 */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, R5.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0005 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fe40003f06070 */
/*0150*/ SHF.R.S32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fc80000011405 */
/*0160*/ ISETP.GE.AND.EX P0, PT, R6, c[0x0][0x16c], PT, P0 ; /* 0x00005b0006007a0c */
/* 0x000fe20003f06300 */
/*0170*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0180*/ @!P0 BRA 0xd0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0190*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x001fe20003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*01c0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fe200078e0003 */
/*01d0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e280000004800 */
/*01e0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void histo_kernal(char *buffer, long size, int *histo )
{
__shared__ int temp[256];
temp[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
int offset = blockDim.x * gridDim.x;
int z;
while (i < size)
{
z = buffer[i];
atomicAdd( &temp[z], 1);
i += offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
} | .file "tmpxft_001778d1_00000000-6_histo_kernal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12histo_kernalPclPiPclPi
.type _Z35__device_stub__Z12histo_kernalPclPiPclPi, @function
_Z35__device_stub__Z12histo_kernalPclPiPclPi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12histo_kernalPclPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12histo_kernalPclPiPclPi, .-_Z35__device_stub__Z12histo_kernalPclPiPclPi
.globl _Z12histo_kernalPclPi
.type _Z12histo_kernalPclPi, @function
_Z12histo_kernalPclPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12histo_kernalPclPiPclPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12histo_kernalPclPi, .-_Z12histo_kernalPclPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12histo_kernalPclPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12histo_kernalPclPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void histo_kernal(char *buffer, long size, int *histo )
{
__shared__ int temp[256];
temp[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
int offset = blockDim.x * gridDim.x;
int z;
while (i < size)
{
z = buffer[i];
atomicAdd( &temp[z], 1);
i += offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histo_kernal(char *buffer, long size, int *histo )
{
__shared__ int temp[256];
temp[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
int offset = blockDim.x * gridDim.x;
int z;
while (i < size)
{
z = buffer[i];
atomicAdd( &temp[z], 1);
i += offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histo_kernal(char *buffer, long size, int *histo )
{
__shared__ int temp[256];
temp[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
int offset = blockDim.x * gridDim.x;
int z;
while (i < size)
{
z = buffer[i];
atomicAdd( &temp[z], 1);
i += offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12histo_kernalPclPi
.globl _Z12histo_kernalPclPi
.p2align 8
.type _Z12histo_kernalPclPi,@function
_Z12histo_kernalPclPi:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
v_lshlrev_b32_e32 v5, 2, v0
v_mov_b32_e32 v3, 0
ds_store_b32 v5, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s7, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s8, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v6, 1
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s7, v[0:1]
s_mul_i32 s7, s8, s7
s_ashr_i32 s8, s7, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_sub_co_u32 v3, vcc_lo, v3, s7
v_subrev_co_ci_u32_e32 v4, vcc_lo, s8, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s8, v4, vcc_lo
global_load_i8 v1, v[1:2], off
v_ashrrev_i32_e32 v2, 31, v3
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[3:4]
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v1
ds_add_u32 v1, v6
v_mov_b32_e32 v1, v3
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v5
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12histo_kernalPclPi
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12histo_kernalPclPi, .Lfunc_end0-_Z12histo_kernalPclPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12histo_kernalPclPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12histo_kernalPclPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void histo_kernal(char *buffer, long size, int *histo )
{
__shared__ int temp[256];
temp[threadIdx.x] = 0;
__syncthreads();
int i = threadIdx.x + blockIdx.x * blockDim.x;
int offset = blockDim.x * gridDim.x;
int z;
while (i < size)
{
z = buffer[i];
atomicAdd( &temp[z], 1);
i += offset;
}
__syncthreads();
atomicAdd( &(histo[threadIdx.x]), temp[threadIdx.x] );
} | .text
.file "histo_kernal.hip"
.globl _Z27__device_stub__histo_kernalPclPi # -- Begin function _Z27__device_stub__histo_kernalPclPi
.p2align 4, 0x90
.type _Z27__device_stub__histo_kernalPclPi,@function
_Z27__device_stub__histo_kernalPclPi: # @_Z27__device_stub__histo_kernalPclPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12histo_kernalPclPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__histo_kernalPclPi, .Lfunc_end0-_Z27__device_stub__histo_kernalPclPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12histo_kernalPclPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12histo_kernalPclPi,@object # @_Z12histo_kernalPclPi
.section .rodata,"a",@progbits
.globl _Z12histo_kernalPclPi
.p2align 3, 0x0
_Z12histo_kernalPclPi:
.quad _Z27__device_stub__histo_kernalPclPi
.size _Z12histo_kernalPclPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12histo_kernalPclPi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__histo_kernalPclPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12histo_kernalPclPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z12histo_kernalPclPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e680000002500 */
/*0040*/ STS [R4.X4], RZ ; /* 0x000000ff04007388 */
/* 0x0011e20000004800 */
/*0050*/ IMAD R0, R3, c[0x0][0x0], R4 ; /* 0x0000000003007a24 */
/* 0x002fc600078e0204 */
/*0060*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe40000010000 */
/*0070*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fe40003f06070 */
/*0080*/ SHF.R.S32.HI R2, RZ, 0x1f, R0 ; /* 0x0000001fff027819 */
/* 0x000fc80000011400 */
/*0090*/ ISETP.GE.AND.EX P0, PT, R2, c[0x0][0x16c], PT, P0 ; /* 0x00005b0002007a0c */
/* 0x000fda0003f06300 */
/*00a0*/ @P0 BRA 0x190 ; /* 0x000000e000000947 */
/* 0x000fea0003800000 */
/*00b0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x001fe400078e0002 */
/*00c0*/ IMAD.MOV.U32 R5, RZ, RZ, R0 ; /* 0x000000ffff057224 */
/* 0x000fca00078e0000 */
/*00d0*/ IADD3 R2, P0, R5, c[0x0][0x160], RZ ; /* 0x0000580005027a10 */
/* 0x001fc80007f1e0ff */
/*00e0*/ IADD3.X R3, R6, c[0x0][0x164], RZ, P0, !PT ; /* 0x0000590006037a10 */
/* 0x000fca00007fe4ff */
/*00f0*/ LDG.E.S8 R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea2000c1e1300 */
/*0100*/ MOV R5, c[0x0][0x0] ; /* 0x0000000000057a02 */
/* 0x000fe20000000f00 */
/*0110*/ YIELD ; /* 0x0000000000007946 */
/* 0x000fe80003800000 */
/*0120*/ IMAD R5, R5, c[0x0][0xc], R0 ; /* 0x0000030005057a24 */
/* 0x000fc800078e0200 */
/*0130*/ IMAD.MOV.U32 R0, RZ, RZ, R5.reuse ; /* 0x000000ffff007224 */
/* 0x100fe200078e0005 */
/*0140*/ ISETP.GE.U32.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fe40003f06070 */
/*0150*/ SHF.R.S32.HI R6, RZ, 0x1f, R5 ; /* 0x0000001fff067819 */
/* 0x000fc80000011405 */
/*0160*/ ISETP.GE.AND.EX P0, PT, R6, c[0x0][0x16c], PT, P0 ; /* 0x00005b0006007a0c */
/* 0x000fe20003f06300 */
/*0170*/ ATOMS.POPC.INC.32 RZ, [R2.X4+URZ] ; /* 0x0000000002ff7f8c */
/* 0x0041d8000d00403f */
/*0180*/ @!P0 BRA 0xd0 ; /* 0xffffff4000008947 */
/* 0x000fea000383ffff */
/*0190*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x001fe20003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*01b0*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fd400000001ff */
/*01c0*/ IMAD.WIDE.U32 R2, R4, R3, c[0x0][0x170] ; /* 0x00005c0004027625 */
/* 0x000fe200078e0003 */
/*01d0*/ LDS R5, [R4.X4] ; /* 0x0000000004057984 */
/* 0x000e280000004800 */
/*01e0*/ RED.E.ADD.STRONG.GPU [R2.64], R5 ; /* 0x000000050200798e */
/* 0x001fe2000c10e184 */
/*01f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0200*/ BRA 0x200; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z12histo_kernalPclPi
.globl _Z12histo_kernalPclPi
.p2align 8
.type _Z12histo_kernalPclPi,@function
_Z12histo_kernalPclPi:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[2:3], s[0:1], 0x8
s_add_u32 s4, s0, 24
s_addc_u32 s5, s1, 0
v_lshlrev_b32_e32 v5, 2, v0
v_mov_b32_e32 v3, 0
ds_store_b32 v5, v3
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_and_b32 s7, s6, 0xffff
s_mov_b32 s6, exec_lo
v_mad_u64_u32 v[1:2], null, s15, s7, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_cmpx_gt_i64_e64 s[2:3], v[1:2]
s_cbranch_execz .LBB0_3
s_load_b32 s8, s[4:5], 0x0
s_load_b64 s[4:5], s[0:1], 0x0
v_mov_b32_e32 v6, 1
s_mov_b32 s9, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s15, s15, s8
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s15, s7, v[0:1]
s_mul_i32 s7, s8, s7
s_ashr_i32 s8, s7, 31
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v4, 31, v3
v_sub_co_u32 v3, vcc_lo, v3, s7
v_subrev_co_ci_u32_e32 v4, vcc_lo, s8, v4, vcc_lo
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_add_co_u32 v1, vcc_lo, s4, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
v_add_co_u32 v3, vcc_lo, v3, s7
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v4, vcc_lo, s8, v4, vcc_lo
global_load_i8 v1, v[1:2], off
v_ashrrev_i32_e32 v2, 31, v3
v_cmp_le_i64_e32 vcc_lo, s[2:3], v[3:4]
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_lshlrev_b32_e32 v1, 2, v1
ds_add_u32 v1, v6
v_mov_b32_e32 v1, v3
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s6
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v5
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
global_atomic_add_u32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z12histo_kernalPclPi
.amdhsa_group_segment_fixed_size 1024
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z12histo_kernalPclPi, .Lfunc_end0-_Z12histo_kernalPclPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 8
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 1024
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z12histo_kernalPclPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z12histo_kernalPclPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001778d1_00000000-6_histo_kernal.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z12histo_kernalPclPiPclPi
.type _Z35__device_stub__Z12histo_kernalPclPiPclPi, @function
_Z35__device_stub__Z12histo_kernalPclPiPclPi:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z12histo_kernalPclPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z12histo_kernalPclPiPclPi, .-_Z35__device_stub__Z12histo_kernalPclPiPclPi
.globl _Z12histo_kernalPclPi
.type _Z12histo_kernalPclPi, @function
_Z12histo_kernalPclPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z12histo_kernalPclPiPclPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z12histo_kernalPclPi, .-_Z12histo_kernalPclPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z12histo_kernalPclPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z12histo_kernalPclPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "histo_kernal.hip"
.globl _Z27__device_stub__histo_kernalPclPi # -- Begin function _Z27__device_stub__histo_kernalPclPi
.p2align 4, 0x90
.type _Z27__device_stub__histo_kernalPclPi,@function
_Z27__device_stub__histo_kernalPclPi: # @_Z27__device_stub__histo_kernalPclPi
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z12histo_kernalPclPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z27__device_stub__histo_kernalPclPi, .Lfunc_end0-_Z27__device_stub__histo_kernalPclPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z12histo_kernalPclPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z12histo_kernalPclPi,@object # @_Z12histo_kernalPclPi
.section .rodata,"a",@progbits
.globl _Z12histo_kernalPclPi
.p2align 3, 0x0
_Z12histo_kernalPclPi:
.quad _Z27__device_stub__histo_kernalPclPi
.size _Z12histo_kernalPclPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z12histo_kernalPclPi"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z27__device_stub__histo_kernalPclPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z12histo_kernalPclPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void add(int a,int b,int *c)
{
*c=a+b;
} | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void add(int a,int b,int *c)
{
*c=a+b;
} | .file "tmpxft_00192fda_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void add(int a,int b,int *c)
{
*c=a+b;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int a,int b,int *c)
{
*c=a+b;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int a,int b,int *c)
{
*c=a+b;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void add(int a,int b,int *c)
{
*c=a+b;
} | .text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00192fda_00000000-6_add.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z3addiiPi, .-_Z3addiiPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "add.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void gpuDot(float* dot, float* a, float* b, int N)
{
__shared__ float cache[THREADS_PER_BLOCK];
int tid = blockIdx.x*blockDim.x + threadIdx.x;
int cacheIdx = threadIdx.x;
float temp = 0;
while (tid < N)
{
temp += a[tid] * b[tid];
tid += blockDim.x * gridDim.x;
}
cache[cacheIdx]=temp;
__syncthreads();
int i = blockDim.x/2;
while (i != 0)
{
if (cacheIdx < i)
cache[cacheIdx] += cache[cacheIdx + i];
__syncthreads();
i /= 2;
}
if (cacheIdx == 0)
dot[blockIdx.x] = cache[0];
} | code for sm_80
Function : _Z6gpuDotPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0030*/ BSSY B0, 0x150 ; /* 0x0000011000007945 */
/* 0x000fe20003800000 */
/*0040*/ HFMA2.MMA R6, -RZ, RZ, 0, 0 ; /* 0x00000000ff067435 */
/* 0x000fe200000001ff */
/*0050*/ S2R R8, SR_TID.X ; /* 0x0000000000087919 */
/* 0x000e240000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x0], R8 ; /* 0x0000000007007a24 */
/* 0x001fca00078e0208 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fda0003f06270 */
/*0080*/ @P0 BRA 0x140 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0090*/ IMAD.MOV.U32 R6, RZ, RZ, RZ ; /* 0x000000ffff067224 */
/* 0x000fe400078e00ff */
/*00a0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*00b0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0205 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fe400078e0205 */
/*00d0*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea8000c1e1900 */
/*00e0*/ LDG.E R5, [R4.64] ; /* 0x0000000604057981 */
/* 0x000ea2000c1e1900 */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, c[0x0][0x0] ; /* 0x00000000ff097624 */
/* 0x000fc800078e00ff */
/*0100*/ IMAD R0, R9, c[0x0][0xc], R0 ; /* 0x0000030009007a24 */
/* 0x000fca00078e0200 */
/*0110*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe20003f06270 */
/*0120*/ FFMA R6, R5, R2, R6 ; /* 0x0000000205067223 */
/* 0x004fd80000000006 */
/*0130*/ @!P0 BRA 0xa0 ; /* 0xffffff6000008947 */
/* 0x000fea000383ffff */
/*0140*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0150*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe20000000800 */
/*0160*/ STS [R8.X4], R6 ; /* 0x0000000608007388 */
/* 0x0001e20000004800 */
/*0170*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fc60008011604 */
/*0180*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0190*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f05270 */
/*01a0*/ ISETP.NE.AND P1, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fda000bf25270 */
/*01b0*/ @!P1 BRA 0x2a0 ; /* 0x000000e000009947 */
/* 0x000fea0003800000 */
/*01c0*/ SHF.L.U32 R0, R8, 0x2, RZ ; /* 0x0000000208007819 */
/* 0x001fe200000006ff */
/*01d0*/ IMAD.U32 R3, RZ, RZ, UR4 ; /* 0x00000004ff037e24 */
/* 0x000fca000f8e00ff */
/*01e0*/ ISETP.GE.AND P1, PT, R8, R3, PT ; /* 0x000000030800720c */
/* 0x000fda0003f26270 */
/*01f0*/ @!P1 LEA R2, R3.reuse, R0, 0x2 ; /* 0x0000000003029211 */
/* 0x040fe200078e10ff */
/*0200*/ @!P1 LDS R4, [R8.X4] ; /* 0x0000000008049984 */
/* 0x000fe80000004800 */
/*0210*/ @!P1 LDS R5, [R2] ; /* 0x0000000002059984 */
/* 0x000e240000000800 */
/*0220*/ @!P1 FADD R4, R4, R5 ; /* 0x0000000504049221 */
/* 0x001fe20000000000 */
/*0230*/ IADD3 R5, R3.reuse, 0x1, RZ ; /* 0x0000000103057810 */
/* 0x040fe40007ffe0ff */
/*0240*/ LEA.HI R3, R3, R3, RZ, 0x1 ; /* 0x0000000303037211 */
/* 0x000fc400078f08ff */
/*0250*/ @!P1 STS [R8.X4], R4 ; /* 0x0000000408009388 */
/* 0x0001e80000004800 */
/*0260*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0270*/ ISETP.GT.U32.AND P1, PT, R5, 0x2, PT ; /* 0x000000020500780c */
/* 0x000fe40003f24070 */
/*0280*/ SHF.R.S32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fd60000011403 */
/*0290*/ @P1 BRA 0x1e0 ; /* 0xffffff4000001947 */
/* 0x001fea000383ffff */
/*02a0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x001fea0003800000 */
/*02b0*/ LDS R5, [RZ] ; /* 0x00000000ff057984 */
/* 0x000e220000000800 */
/*02c0*/ IMAD.MOV.U32 R2, RZ, RZ, 0x4 ; /* 0x00000004ff027424 */
/* 0x000fc800078e00ff */
/*02d0*/ IMAD.WIDE.U32 R2, R7, R2, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0002 */
/*02e0*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x001fe2000c101906 */
/*02f0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0300*/ BRA 0x300; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0310*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
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