system stringclasses 7 values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /*
* BC_PointwiseDotproduct.cu
*
* Created on: Feb 6, 2018
* Author: joseph
*/
#ifndef BC_POINTWISEDOTPRODUCT_CU_
#define BC_POINTWISEDOTPRODUCT_CU_
namespace BC {
#ifdef __CUDACC__
#define __BC_gcpu__ __host__ __device__
#define BLACKCAT_GPU_ENABLED
#else
#define __BC_gcpu__
#endif
template<class, class> class Matrix;
template<class, class> class Vector;
template<class, class> class expression;
template<class T, class functor_type>
struct pointwise_accessor : expression<T, pointwise_accessor<T, functor_type>> {
//Evaluates a single row*column operation of two tensors
functor_type lv;
functor_type rv;
T* evaluation;
};
template<class T, class ml>
Vector<T, ml> operator * (const Matrix<T, ml>&, const Vector<T, ml>&) {
}
}
#endif /* BC_POINTWISEDOTPRODUCT_CU_ */ | .file "tmpxft_001adacd_00000000-6_BC_PointwiseDotproduct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /*
* BC_PointwiseDotproduct.cu
*
* Created on: Feb 6, 2018
* Author: joseph
*/
#ifndef BC_POINTWISEDOTPRODUCT_CU_
#define BC_POINTWISEDOTPRODUCT_CU_
namespace BC {
#ifdef __CUDACC__
#define __BC_gcpu__ __host__ __device__
#define BLACKCAT_GPU_ENABLED
#else
#define __BC_gcpu__
#endif
template<class, class> class Matrix;
template<class, class> class Vector;
template<class, class> class expression;
template<class T, class functor_type>
struct pointwise_accessor : expression<T, pointwise_accessor<T, functor_type>> {
//Evaluates a single row*column operation of two tensors
functor_type lv;
functor_type rv;
T* evaluation;
};
template<class T, class ml>
Vector<T, ml> operator * (const Matrix<T, ml>&, const Vector<T, ml>&) {
}
}
#endif /* BC_POINTWISEDOTPRODUCT_CU_ */ | /*
* BC_PointwiseDotproduct.cu
*
* Created on: Feb 6, 2018
* Author: joseph
*/
#ifndef BC_POINTWISEDOTPRODUCT_CU_
#define BC_POINTWISEDOTPRODUCT_CU_
namespace BC {
#ifdef __HIPCC__
#define __BC_gcpu__ __host__ __device__
#define BLACKCAT_GPU_ENABLED
#else
#define __BC_gcpu__
#endif
template<class, class> class Matrix;
template<class, class> class Vector;
template<class, class> class expression;
template<class T, class functor_type>
struct pointwise_accessor : expression<T, pointwise_accessor<T, functor_type>> {
//Evaluates a single row*column operation of two tensors
functor_type lv;
functor_type rv;
T* evaluation;
};
template<class T, class ml>
Vector<T, ml> operator * (const Matrix<T, ml>&, const Vector<T, ml>&) {
}
}
#endif /* BC_POINTWISEDOTPRODUCT_CU_ */ |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /*
* BC_PointwiseDotproduct.cu
*
* Created on: Feb 6, 2018
* Author: joseph
*/
#ifndef BC_POINTWISEDOTPRODUCT_CU_
#define BC_POINTWISEDOTPRODUCT_CU_
namespace BC {
#ifdef __HIPCC__
#define __BC_gcpu__ __host__ __device__
#define BLACKCAT_GPU_ENABLED
#else
#define __BC_gcpu__
#endif
template<class, class> class Matrix;
template<class, class> class Vector;
template<class, class> class expression;
template<class T, class functor_type>
struct pointwise_accessor : expression<T, pointwise_accessor<T, functor_type>> {
//Evaluates a single row*column operation of two tensors
functor_type lv;
functor_type rv;
T* evaluation;
};
template<class T, class ml>
Vector<T, ml> operator * (const Matrix<T, ml>&, const Vector<T, ml>&) {
}
}
#endif /* BC_POINTWISEDOTPRODUCT_CU_ */ | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /*
* BC_PointwiseDotproduct.cu
*
* Created on: Feb 6, 2018
* Author: joseph
*/
#ifndef BC_POINTWISEDOTPRODUCT_CU_
#define BC_POINTWISEDOTPRODUCT_CU_
namespace BC {
#ifdef __HIPCC__
#define __BC_gcpu__ __host__ __device__
#define BLACKCAT_GPU_ENABLED
#else
#define __BC_gcpu__
#endif
template<class, class> class Matrix;
template<class, class> class Vector;
template<class, class> class expression;
template<class T, class functor_type>
struct pointwise_accessor : expression<T, pointwise_accessor<T, functor_type>> {
//Evaluates a single row*column operation of two tensors
functor_type lv;
functor_type rv;
T* evaluation;
};
template<class T, class ml>
Vector<T, ml> operator * (const Matrix<T, ml>&, const Vector<T, ml>&) {
}
}
#endif /* BC_POINTWISEDOTPRODUCT_CU_ */ | .text
.file "BC_PointwiseDotproduct.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001adacd_00000000-6_BC_PointwiseDotproduct.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "BC_PointwiseDotproduct.hip"
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda.h>
#include <cuda_runtime.h>
#include <curand_kernel.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <time.h>
#include <string.h>
#define PI 3.1415926536
#define e 2.718281828459
#define N 64*64
#define THREADS_PER_BLOCK 64
struct timeval tic(){
struct timeval tv;
gettimeofday(&tv,NULL);
return tv;
}
typedef struct Patches
{
int index;
float central;
float* patchArray;
}Patch;
double toc(struct timeval begin){
struct timeval end;
gettimeofday(&end,NULL);
double stime = ((double)(end.tv_sec-begin.tv_sec)*1000)+((double)(end.tv_usec-begin.tv_usec)/1000);
stime = stime / 1000;
return (stime);
}
float* readFile(int n, int m, char *file_path){
FILE* ptrFile = fopen(file_path, "r");
float *I = (float*)malloc(n*m*sizeof(float));
if (!ptrFile){
printf("Error Reading File\n");
exit (0);
}
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
fscanf(ptrFile,"%f,", &I[n*i+j]);
}
}
fclose(ptrFile);
return I;
}
void toTXT(float* array,char *output, int n, int m){
FILE *fp;
fp=fopen(output,"w");
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
if(j<m-1){
fprintf(fp,"%lf,",array[n*i+j]);
}else if(j==m-1){
fprintf(fp,"%lf",array[n*i+j]);
}
}
fprintf(fp,"\n",array[n*i]);
}
fclose(fp);
printf("File %s saved.\n", output);
}
__global__ void normalization(float* A, float* B, float min, float max){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<N)
B[i] = (A[i] - min) / max;
}
float AWGN_generator() //https://www.embeddedrelated.com/showcode/311.php
{/* Generates additive white Gaussian Noise samples with zero mean and a standard deviation of 1. */
float dev = 0.03162; //var = 0.01
float temp1;
float temp2;
float result;
int p = 1;
while( p > 0 )
{
temp2 = ( rand() / ( (float)RAND_MAX ) ); /* rand() function generates an
integer between 0 and RAND_MAX,
which is defined in stdlib.h.
*/
if ( temp2 == 0 )
{// temp2 is >= (RAND_MAX / 2)
p = 1;
}// end if
else
{// temp2 is < (RAND_MAX / 2)
p = -1;
}// end else
}// end while()
temp1 = cos( ( 2.0 * (float)PI ) * rand() / ( (float)RAND_MAX ) );
result = sqrt( -2.0 * log( temp2 ) ) * temp1;
return result * dev; // return the generated random sample to the caller
}// end AWGN_generator()
Patch* makePatches(float* J, int n, int m, Patch* allPatches, int patchSizeH, int patchSizeW){
int mdW = (patchSizeW - 1)/2;
int mdH = (patchSizeH - 1)/2;
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
for(int w=0; w<patchSizeW; w++){
for(int h=0; h<patchSizeH; h++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = 0;
}
}
allPatches[n*j+i].central = J[n*j+i];
allPatches[n*j+i].index = n*j+i;
if(i==0 && j==0){
for(int w=mdW; w<patchSizeW; w++){
for(int h=mdH; h<patchSizeH; h++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = J[(n*j+i)-(mdW-w)*n-(mdH-h)];
}
}
}else if(i>0 && j==0){
for(int h=0; h<patchSizeH-1; h++){
for(int w=0; w<patchSizeW; w++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = allPatches[n*j+(i-1)].patchArray[patchSizeH*w+(h+1)];
}
}
for(int w=mdW; w<patchSizeW; w++){
if((n-1-i) >= mdH){
allPatches[n*j+i].patchArray[patchSizeH*w+(patchSizeH-1)] = J[(n*j+i)-(mdW-w)*n+mdH];
}else if((n-1-i) < mdH){
allPatches[n*j+i].patchArray[patchSizeH*w+(patchSizeH-1)] = 0;
}
}
}else if(j>0){
for(int w=0; w<patchSizeW-1; w++){
for(int h=0; h<patchSizeH; h++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = allPatches[n*(j-1)+i].patchArray[patchSizeH*(w+1)+h];
}
}
int a,b;
if(i>=mdH && (n-1-i)>=mdH){
a = 0;
b = patchSizeH;
}else if(i<mdH && (n-1-i)>=mdH){
a = mdH - i;
b = patchSizeH;
}else if(i<mdH && (n-1-i)<mdH){
a = mdH - i;
b = mdH + (n-i);
}else if(i>=mdH && (n-1-i)<mdH){
a = 0;
b = mdH + (n-i);
}
for(int h=a; h<b; h++){
if((m-1-j) >= mdW){
allPatches[n*j+i].patchArray[patchSizeH*(patchSizeW-1)+h] = J[(n*j+i)+mdW*n-(mdH-h)];
}else if((m-1-j) < mdW){
allPatches[n*j+i].patchArray[patchSizeH*(patchSizeW-1)+h] = 0;
}
}
}
}
}
return allPatches;
}
float* computeG_a(int patchSizeH, int patchSizeW, float patchSigma){
float* gauss = (float*)malloc(patchSizeH*patchSizeW*sizeof(float));
for (int i = 0; i < patchSizeH; i++) {
for (int j = 0; j < patchSizeW; j++) {
float y = i - (patchSizeH - 1) / 2.0;
float x = j - (patchSizeW - 1) / 2.0;
gauss[patchSizeW*i+j] = (1/2.0) * exp(-(x * x + y * y) / (2.0 * PI * patchSigma * patchSigma));
}
}
return gauss;
}
__global__ void dist(float *W,float *p_i, float *P, float *V, int pSize, float filtSigma){
float d = 0;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if(k<N){
for (int i = 0; i < pSize; i++) {
d += V[i] * pow(p_i[i] - P[pSize*k+i],2);
}
d = sqrt(d);
W[k] = exp(-pow(d,2) / filtSigma);
d=0;
}
}
__global__ void dim(float *w, float *z){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<N){
w[i] = w[i] / *z;
}
}
int main(int argc, char *argv[]){
int n = atoi(argv[1]);
int m = atoi(argv[2]);
int patchSizeH = atoi(argv[3]);
int patchSizeW = atoi(argv[4]);
char* file_path;
file_path=(char*)malloc(strlen(argv[5])*sizeof(char));
memcpy(file_path,argv[5],strlen(argv[5]));
float patchSigma =5/3;
float filtSigma =0.01 ;
float *I, *I_norm, *J, *If;
float *dev_I, *dev_I_norm, *dev_J, *dev_gauss;
float *P, *dev_P, *w;
int size = N * sizeof(float);
int sizePatch = patchSizeH * patchSizeW * sizeof(float);
int pSize = patchSizeH * patchSizeW;
//allocate memory for device copies
cudaMalloc(&dev_I, size);
cudaMalloc(&dev_I_norm, size);
cudaMalloc(&dev_J, size);
cudaMalloc(&dev_gauss, sizePatch);
cudaMalloc(&dev_P, N*pSize*sizeof(float));
I = (float*)malloc(size);
I_norm = (float*)malloc(size);
J = (float*)malloc(size);
If = (float*)malloc(size);
Patch* allPatches;
allPatches = (Patch*)malloc(n*m*sizeof(Patch));
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
allPatches[n*j+i].patchArray = (float*)malloc(patchSizeH*patchSizeW*sizeof(float));
}
}
w = (float*)malloc(N*N*sizeof(float));
float* gauss = (float*)malloc(sizePatch);
float* Z = (float*)malloc(size);
struct timeval tStart;
I = readFile(n,m,file_path);
//find min of 'I' and max of 'I-min'
float min = INFINITY;
float max = -1.0;
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
if(I[n*i+j]<min) min= I[n*i+j];
}
}
for(int i=0; i<n*m; i++){
if((I[i]-min)>max) max = I[i]-min;
}
cudaMemcpy(dev_I, I, size, cudaMemcpyHostToDevice);
normalization<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(dev_I, dev_I_norm, min, max);
cudaMemcpy(I_norm, dev_I_norm, size, cudaMemcpyDeviceToHost);
for(int i=0; i<n*m; i++){
J[i] = I_norm[i] + AWGN_generator();
}
toTXT(I_norm,"normCuda.txt",n,m);
toTXT(J,"JCuda.txt",n,m);
allPatches = makePatches(J,n,m,allPatches,patchSizeH,patchSizeW);
//pass all the elements of 'allPatches' to 'P' array(NxpSize)
P = (float*)malloc(N*pSize*sizeof(float));
for(int i=0; i<N; i++){
for(int j=0; j<pSize; j++){
P[pSize*i+j] = allPatches[i].patchArray[j];
}
}
cudaMemcpy(dev_P, P, N*sizePatch, cudaMemcpyHostToDevice);
gauss = computeG_a(patchSizeH, patchSizeW, patchSigma);
cudaMemcpy(dev_gauss, gauss, sizePatch, cudaMemcpyHostToDevice);
float *patch_i = (float*)malloc(sizePatch);
float *dev_patchI;
cudaMalloc(&dev_patchI, sizePatch);
float *wi_j = (float*)malloc(N*sizeof(float));
float *dev_wij;
cudaMalloc(&dev_wij, N*sizeof(float));
tStart = tic();
for(int i=0; i<N; i++){
for(int j=0; j<pSize; j++){
patch_i[j] = P[pSize*i +j];
}
cudaMemcpy(dev_patchI, patch_i, sizePatch, cudaMemcpyHostToDevice);
dist<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(dev_wij, dev_patchI,dev_P, dev_gauss,pSize,filtSigma);
cudaMemcpy(wi_j, dev_wij, size, cudaMemcpyDeviceToHost);
for(int j=0; j<N;j++){
Z[i] += wi_j[j];
w[N*i+j] = wi_j[j];
}
}
cudaFree(dev_patchI);
cudaFree(dev_gauss);
float *dev_Z;
cudaMalloc(&dev_Z, sizeof(float));
for(int i=0; i<N; i++){
for(int j=0; j<N;j++){
wi_j[j] = w[N*i+j];
}
cudaMemcpy(dev_wij, wi_j,size, cudaMemcpyHostToDevice);
cudaMemcpy(dev_Z, &Z[i], sizeof(float), cudaMemcpyHostToDevice);
dim<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(dev_wij,dev_Z);
cudaMemcpy(wi_j, dev_wij, size,cudaMemcpyDeviceToHost);
for(int j=0; j<N;j++){
w[N*i+j] = wi_j[j];
If[i] += w[N*i+j] * J[j];
}
}
double time = toc(tStart);
toTXT(If,"IfCuda.txt",n,m);
float* Dif = (float*)malloc(N*sizeof(float));
for(int i=0; i<N; i++){
Dif[i] =If[i] - J[i];
}
toTXT(Dif,"DifCuda.txt",n,m);
printf("Time: %f sec", time);
cudaFree(dev_I); cudaFree(dev_I_norm); cudaFree(dev_J); cudaFree(dev_P); cudaFree(dev_wij); cudaFree(dev_Z);
free(I); free(I_norm); free(J); free(patch_i); free(gauss); free(wi_j); free(Z); free(If); free(Dif); free(w);
free(allPatches->patchArray);
free(allPatches);
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <time.h>
#include <string.h>
#define PI 3.1415926536
#define e 2.718281828459
#define N 64*64
#define THREADS_PER_BLOCK 64
struct timeval tic(){
struct timeval tv;
gettimeofday(&tv,NULL);
return tv;
}
typedef struct Patches
{
int index;
float central;
float* patchArray;
}Patch;
double toc(struct timeval begin){
struct timeval end;
gettimeofday(&end,NULL);
double stime = ((double)(end.tv_sec-begin.tv_sec)*1000)+((double)(end.tv_usec-begin.tv_usec)/1000);
stime = stime / 1000;
return (stime);
}
float* readFile(int n, int m, char *file_path){
FILE* ptrFile = fopen(file_path, "r");
float *I = (float*)malloc(n*m*sizeof(float));
if (!ptrFile){
printf("Error Reading File\n");
exit (0);
}
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
fscanf(ptrFile,"%f,", &I[n*i+j]);
}
}
fclose(ptrFile);
return I;
}
void toTXT(float* array,char *output, int n, int m){
FILE *fp;
fp=fopen(output,"w");
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
if(j<m-1){
fprintf(fp,"%lf,",array[n*i+j]);
}else if(j==m-1){
fprintf(fp,"%lf",array[n*i+j]);
}
}
fprintf(fp,"\n",array[n*i]);
}
fclose(fp);
printf("File %s saved.\n", output);
}
__global__ void normalization(float* A, float* B, float min, float max){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<N)
B[i] = (A[i] - min) / max;
}
float AWGN_generator() //https://www.embeddedrelated.com/showcode/311.php
{/* Generates additive white Gaussian Noise samples with zero mean and a standard deviation of 1. */
float dev = 0.03162; //var = 0.01
float temp1;
float temp2;
float result;
int p = 1;
while( p > 0 )
{
temp2 = ( rand() / ( (float)RAND_MAX ) ); /* rand() function generates an
integer between 0 and RAND_MAX,
which is defined in stdlib.h.
*/
if ( temp2 == 0 )
{// temp2 is >= (RAND_MAX / 2)
p = 1;
}// end if
else
{// temp2 is < (RAND_MAX / 2)
p = -1;
}// end else
}// end while()
temp1 = cos( ( 2.0 * (float)PI ) * rand() / ( (float)RAND_MAX ) );
result = sqrt( -2.0 * log( temp2 ) ) * temp1;
return result * dev; // return the generated random sample to the caller
}// end AWGN_generator()
Patch* makePatches(float* J, int n, int m, Patch* allPatches, int patchSizeH, int patchSizeW){
int mdW = (patchSizeW - 1)/2;
int mdH = (patchSizeH - 1)/2;
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
for(int w=0; w<patchSizeW; w++){
for(int h=0; h<patchSizeH; h++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = 0;
}
}
allPatches[n*j+i].central = J[n*j+i];
allPatches[n*j+i].index = n*j+i;
if(i==0 && j==0){
for(int w=mdW; w<patchSizeW; w++){
for(int h=mdH; h<patchSizeH; h++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = J[(n*j+i)-(mdW-w)*n-(mdH-h)];
}
}
}else if(i>0 && j==0){
for(int h=0; h<patchSizeH-1; h++){
for(int w=0; w<patchSizeW; w++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = allPatches[n*j+(i-1)].patchArray[patchSizeH*w+(h+1)];
}
}
for(int w=mdW; w<patchSizeW; w++){
if((n-1-i) >= mdH){
allPatches[n*j+i].patchArray[patchSizeH*w+(patchSizeH-1)] = J[(n*j+i)-(mdW-w)*n+mdH];
}else if((n-1-i) < mdH){
allPatches[n*j+i].patchArray[patchSizeH*w+(patchSizeH-1)] = 0;
}
}
}else if(j>0){
for(int w=0; w<patchSizeW-1; w++){
for(int h=0; h<patchSizeH; h++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = allPatches[n*(j-1)+i].patchArray[patchSizeH*(w+1)+h];
}
}
int a,b;
if(i>=mdH && (n-1-i)>=mdH){
a = 0;
b = patchSizeH;
}else if(i<mdH && (n-1-i)>=mdH){
a = mdH - i;
b = patchSizeH;
}else if(i<mdH && (n-1-i)<mdH){
a = mdH - i;
b = mdH + (n-i);
}else if(i>=mdH && (n-1-i)<mdH){
a = 0;
b = mdH + (n-i);
}
for(int h=a; h<b; h++){
if((m-1-j) >= mdW){
allPatches[n*j+i].patchArray[patchSizeH*(patchSizeW-1)+h] = J[(n*j+i)+mdW*n-(mdH-h)];
}else if((m-1-j) < mdW){
allPatches[n*j+i].patchArray[patchSizeH*(patchSizeW-1)+h] = 0;
}
}
}
}
}
return allPatches;
}
float* computeG_a(int patchSizeH, int patchSizeW, float patchSigma){
float* gauss = (float*)malloc(patchSizeH*patchSizeW*sizeof(float));
for (int i = 0; i < patchSizeH; i++) {
for (int j = 0; j < patchSizeW; j++) {
float y = i - (patchSizeH - 1) / 2.0;
float x = j - (patchSizeW - 1) / 2.0;
gauss[patchSizeW*i+j] = (1/2.0) * exp(-(x * x + y * y) / (2.0 * PI * patchSigma * patchSigma));
}
}
return gauss;
}
__global__ void dist(float *W,float *p_i, float *P, float *V, int pSize, float filtSigma){
float d = 0;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if(k<N){
for (int i = 0; i < pSize; i++) {
d += V[i] * pow(p_i[i] - P[pSize*k+i],2);
}
d = sqrt(d);
W[k] = exp(-pow(d,2) / filtSigma);
d=0;
}
}
__global__ void dim(float *w, float *z){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<N){
w[i] = w[i] / *z;
}
}
int main(int argc, char *argv[]){
int n = atoi(argv[1]);
int m = atoi(argv[2]);
int patchSizeH = atoi(argv[3]);
int patchSizeW = atoi(argv[4]);
char* file_path;
file_path=(char*)malloc(strlen(argv[5])*sizeof(char));
memcpy(file_path,argv[5],strlen(argv[5]));
float patchSigma =5/3;
float filtSigma =0.01 ;
float *I, *I_norm, *J, *If;
float *dev_I, *dev_I_norm, *dev_J, *dev_gauss;
float *P, *dev_P, *w;
int size = N * sizeof(float);
int sizePatch = patchSizeH * patchSizeW * sizeof(float);
int pSize = patchSizeH * patchSizeW;
//allocate memory for device copies
hipMalloc(&dev_I, size);
hipMalloc(&dev_I_norm, size);
hipMalloc(&dev_J, size);
hipMalloc(&dev_gauss, sizePatch);
hipMalloc(&dev_P, N*pSize*sizeof(float));
I = (float*)malloc(size);
I_norm = (float*)malloc(size);
J = (float*)malloc(size);
If = (float*)malloc(size);
Patch* allPatches;
allPatches = (Patch*)malloc(n*m*sizeof(Patch));
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
allPatches[n*j+i].patchArray = (float*)malloc(patchSizeH*patchSizeW*sizeof(float));
}
}
w = (float*)malloc(N*N*sizeof(float));
float* gauss = (float*)malloc(sizePatch);
float* Z = (float*)malloc(size);
struct timeval tStart;
I = readFile(n,m,file_path);
//find min of 'I' and max of 'I-min'
float min = INFINITY;
float max = -1.0;
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
if(I[n*i+j]<min) min= I[n*i+j];
}
}
for(int i=0; i<n*m; i++){
if((I[i]-min)>max) max = I[i]-min;
}
hipMemcpy(dev_I, I, size, hipMemcpyHostToDevice);
normalization<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(dev_I, dev_I_norm, min, max);
hipMemcpy(I_norm, dev_I_norm, size, hipMemcpyDeviceToHost);
for(int i=0; i<n*m; i++){
J[i] = I_norm[i] + AWGN_generator();
}
toTXT(I_norm,"normCuda.txt",n,m);
toTXT(J,"JCuda.txt",n,m);
allPatches = makePatches(J,n,m,allPatches,patchSizeH,patchSizeW);
//pass all the elements of 'allPatches' to 'P' array(NxpSize)
P = (float*)malloc(N*pSize*sizeof(float));
for(int i=0; i<N; i++){
for(int j=0; j<pSize; j++){
P[pSize*i+j] = allPatches[i].patchArray[j];
}
}
hipMemcpy(dev_P, P, N*sizePatch, hipMemcpyHostToDevice);
gauss = computeG_a(patchSizeH, patchSizeW, patchSigma);
hipMemcpy(dev_gauss, gauss, sizePatch, hipMemcpyHostToDevice);
float *patch_i = (float*)malloc(sizePatch);
float *dev_patchI;
hipMalloc(&dev_patchI, sizePatch);
float *wi_j = (float*)malloc(N*sizeof(float));
float *dev_wij;
hipMalloc(&dev_wij, N*sizeof(float));
tStart = tic();
for(int i=0; i<N; i++){
for(int j=0; j<pSize; j++){
patch_i[j] = P[pSize*i +j];
}
hipMemcpy(dev_patchI, patch_i, sizePatch, hipMemcpyHostToDevice);
dist<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(dev_wij, dev_patchI,dev_P, dev_gauss,pSize,filtSigma);
hipMemcpy(wi_j, dev_wij, size, hipMemcpyDeviceToHost);
for(int j=0; j<N;j++){
Z[i] += wi_j[j];
w[N*i+j] = wi_j[j];
}
}
hipFree(dev_patchI);
hipFree(dev_gauss);
float *dev_Z;
hipMalloc(&dev_Z, sizeof(float));
for(int i=0; i<N; i++){
for(int j=0; j<N;j++){
wi_j[j] = w[N*i+j];
}
hipMemcpy(dev_wij, wi_j,size, hipMemcpyHostToDevice);
hipMemcpy(dev_Z, &Z[i], sizeof(float), hipMemcpyHostToDevice);
dim<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(dev_wij,dev_Z);
hipMemcpy(wi_j, dev_wij, size,hipMemcpyDeviceToHost);
for(int j=0; j<N;j++){
w[N*i+j] = wi_j[j];
If[i] += w[N*i+j] * J[j];
}
}
double time = toc(tStart);
toTXT(If,"IfCuda.txt",n,m);
float* Dif = (float*)malloc(N*sizeof(float));
for(int i=0; i<N; i++){
Dif[i] =If[i] - J[i];
}
toTXT(Dif,"DifCuda.txt",n,m);
printf("Time: %f sec", time);
hipFree(dev_I); hipFree(dev_I_norm); hipFree(dev_J); hipFree(dev_P); hipFree(dev_wij); hipFree(dev_Z);
free(I); free(I_norm); free(J); free(patch_i); free(gauss); free(wi_j); free(Z); free(If); free(Dif); free(w);
free(allPatches->patchArray);
free(allPatches);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <time.h>
#include <string.h>
#define PI 3.1415926536
#define e 2.718281828459
#define N 64*64
#define THREADS_PER_BLOCK 64
struct timeval tic(){
struct timeval tv;
gettimeofday(&tv,NULL);
return tv;
}
typedef struct Patches
{
int index;
float central;
float* patchArray;
}Patch;
double toc(struct timeval begin){
struct timeval end;
gettimeofday(&end,NULL);
double stime = ((double)(end.tv_sec-begin.tv_sec)*1000)+((double)(end.tv_usec-begin.tv_usec)/1000);
stime = stime / 1000;
return (stime);
}
float* readFile(int n, int m, char *file_path){
FILE* ptrFile = fopen(file_path, "r");
float *I = (float*)malloc(n*m*sizeof(float));
if (!ptrFile){
printf("Error Reading File\n");
exit (0);
}
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
fscanf(ptrFile,"%f,", &I[n*i+j]);
}
}
fclose(ptrFile);
return I;
}
void toTXT(float* array,char *output, int n, int m){
FILE *fp;
fp=fopen(output,"w");
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
if(j<m-1){
fprintf(fp,"%lf,",array[n*i+j]);
}else if(j==m-1){
fprintf(fp,"%lf",array[n*i+j]);
}
}
fprintf(fp,"\n",array[n*i]);
}
fclose(fp);
printf("File %s saved.\n", output);
}
__global__ void normalization(float* A, float* B, float min, float max){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<N)
B[i] = (A[i] - min) / max;
}
float AWGN_generator() //https://www.embeddedrelated.com/showcode/311.php
{/* Generates additive white Gaussian Noise samples with zero mean and a standard deviation of 1. */
float dev = 0.03162; //var = 0.01
float temp1;
float temp2;
float result;
int p = 1;
while( p > 0 )
{
temp2 = ( rand() / ( (float)RAND_MAX ) ); /* rand() function generates an
integer between 0 and RAND_MAX,
which is defined in stdlib.h.
*/
if ( temp2 == 0 )
{// temp2 is >= (RAND_MAX / 2)
p = 1;
}// end if
else
{// temp2 is < (RAND_MAX / 2)
p = -1;
}// end else
}// end while()
temp1 = cos( ( 2.0 * (float)PI ) * rand() / ( (float)RAND_MAX ) );
result = sqrt( -2.0 * log( temp2 ) ) * temp1;
return result * dev; // return the generated random sample to the caller
}// end AWGN_generator()
Patch* makePatches(float* J, int n, int m, Patch* allPatches, int patchSizeH, int patchSizeW){
int mdW = (patchSizeW - 1)/2;
int mdH = (patchSizeH - 1)/2;
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
for(int w=0; w<patchSizeW; w++){
for(int h=0; h<patchSizeH; h++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = 0;
}
}
allPatches[n*j+i].central = J[n*j+i];
allPatches[n*j+i].index = n*j+i;
if(i==0 && j==0){
for(int w=mdW; w<patchSizeW; w++){
for(int h=mdH; h<patchSizeH; h++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = J[(n*j+i)-(mdW-w)*n-(mdH-h)];
}
}
}else if(i>0 && j==0){
for(int h=0; h<patchSizeH-1; h++){
for(int w=0; w<patchSizeW; w++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = allPatches[n*j+(i-1)].patchArray[patchSizeH*w+(h+1)];
}
}
for(int w=mdW; w<patchSizeW; w++){
if((n-1-i) >= mdH){
allPatches[n*j+i].patchArray[patchSizeH*w+(patchSizeH-1)] = J[(n*j+i)-(mdW-w)*n+mdH];
}else if((n-1-i) < mdH){
allPatches[n*j+i].patchArray[patchSizeH*w+(patchSizeH-1)] = 0;
}
}
}else if(j>0){
for(int w=0; w<patchSizeW-1; w++){
for(int h=0; h<patchSizeH; h++){
allPatches[n*j+i].patchArray[patchSizeH*w+h] = allPatches[n*(j-1)+i].patchArray[patchSizeH*(w+1)+h];
}
}
int a,b;
if(i>=mdH && (n-1-i)>=mdH){
a = 0;
b = patchSizeH;
}else if(i<mdH && (n-1-i)>=mdH){
a = mdH - i;
b = patchSizeH;
}else if(i<mdH && (n-1-i)<mdH){
a = mdH - i;
b = mdH + (n-i);
}else if(i>=mdH && (n-1-i)<mdH){
a = 0;
b = mdH + (n-i);
}
for(int h=a; h<b; h++){
if((m-1-j) >= mdW){
allPatches[n*j+i].patchArray[patchSizeH*(patchSizeW-1)+h] = J[(n*j+i)+mdW*n-(mdH-h)];
}else if((m-1-j) < mdW){
allPatches[n*j+i].patchArray[patchSizeH*(patchSizeW-1)+h] = 0;
}
}
}
}
}
return allPatches;
}
float* computeG_a(int patchSizeH, int patchSizeW, float patchSigma){
float* gauss = (float*)malloc(patchSizeH*patchSizeW*sizeof(float));
for (int i = 0; i < patchSizeH; i++) {
for (int j = 0; j < patchSizeW; j++) {
float y = i - (patchSizeH - 1) / 2.0;
float x = j - (patchSizeW - 1) / 2.0;
gauss[patchSizeW*i+j] = (1/2.0) * exp(-(x * x + y * y) / (2.0 * PI * patchSigma * patchSigma));
}
}
return gauss;
}
__global__ void dist(float *W,float *p_i, float *P, float *V, int pSize, float filtSigma){
float d = 0;
int k = blockIdx.x * blockDim.x + threadIdx.x;
if(k<N){
for (int i = 0; i < pSize; i++) {
d += V[i] * pow(p_i[i] - P[pSize*k+i],2);
}
d = sqrt(d);
W[k] = exp(-pow(d,2) / filtSigma);
d=0;
}
}
__global__ void dim(float *w, float *z){
int i = blockIdx.x * blockDim.x + threadIdx.x;
if(i<N){
w[i] = w[i] / *z;
}
}
int main(int argc, char *argv[]){
int n = atoi(argv[1]);
int m = atoi(argv[2]);
int patchSizeH = atoi(argv[3]);
int patchSizeW = atoi(argv[4]);
char* file_path;
file_path=(char*)malloc(strlen(argv[5])*sizeof(char));
memcpy(file_path,argv[5],strlen(argv[5]));
float patchSigma =5/3;
float filtSigma =0.01 ;
float *I, *I_norm, *J, *If;
float *dev_I, *dev_I_norm, *dev_J, *dev_gauss;
float *P, *dev_P, *w;
int size = N * sizeof(float);
int sizePatch = patchSizeH * patchSizeW * sizeof(float);
int pSize = patchSizeH * patchSizeW;
//allocate memory for device copies
hipMalloc(&dev_I, size);
hipMalloc(&dev_I_norm, size);
hipMalloc(&dev_J, size);
hipMalloc(&dev_gauss, sizePatch);
hipMalloc(&dev_P, N*pSize*sizeof(float));
I = (float*)malloc(size);
I_norm = (float*)malloc(size);
J = (float*)malloc(size);
If = (float*)malloc(size);
Patch* allPatches;
allPatches = (Patch*)malloc(n*m*sizeof(Patch));
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
allPatches[n*j+i].patchArray = (float*)malloc(patchSizeH*patchSizeW*sizeof(float));
}
}
w = (float*)malloc(N*N*sizeof(float));
float* gauss = (float*)malloc(sizePatch);
float* Z = (float*)malloc(size);
struct timeval tStart;
I = readFile(n,m,file_path);
//find min of 'I' and max of 'I-min'
float min = INFINITY;
float max = -1.0;
for(int i=0; i<n; i++){
for(int j=0; j<m; j++){
if(I[n*i+j]<min) min= I[n*i+j];
}
}
for(int i=0; i<n*m; i++){
if((I[i]-min)>max) max = I[i]-min;
}
hipMemcpy(dev_I, I, size, hipMemcpyHostToDevice);
normalization<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(dev_I, dev_I_norm, min, max);
hipMemcpy(I_norm, dev_I_norm, size, hipMemcpyDeviceToHost);
for(int i=0; i<n*m; i++){
J[i] = I_norm[i] + AWGN_generator();
}
toTXT(I_norm,"normCuda.txt",n,m);
toTXT(J,"JCuda.txt",n,m);
allPatches = makePatches(J,n,m,allPatches,patchSizeH,patchSizeW);
//pass all the elements of 'allPatches' to 'P' array(NxpSize)
P = (float*)malloc(N*pSize*sizeof(float));
for(int i=0; i<N; i++){
for(int j=0; j<pSize; j++){
P[pSize*i+j] = allPatches[i].patchArray[j];
}
}
hipMemcpy(dev_P, P, N*sizePatch, hipMemcpyHostToDevice);
gauss = computeG_a(patchSizeH, patchSizeW, patchSigma);
hipMemcpy(dev_gauss, gauss, sizePatch, hipMemcpyHostToDevice);
float *patch_i = (float*)malloc(sizePatch);
float *dev_patchI;
hipMalloc(&dev_patchI, sizePatch);
float *wi_j = (float*)malloc(N*sizeof(float));
float *dev_wij;
hipMalloc(&dev_wij, N*sizeof(float));
tStart = tic();
for(int i=0; i<N; i++){
for(int j=0; j<pSize; j++){
patch_i[j] = P[pSize*i +j];
}
hipMemcpy(dev_patchI, patch_i, sizePatch, hipMemcpyHostToDevice);
dist<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(dev_wij, dev_patchI,dev_P, dev_gauss,pSize,filtSigma);
hipMemcpy(wi_j, dev_wij, size, hipMemcpyDeviceToHost);
for(int j=0; j<N;j++){
Z[i] += wi_j[j];
w[N*i+j] = wi_j[j];
}
}
hipFree(dev_patchI);
hipFree(dev_gauss);
float *dev_Z;
hipMalloc(&dev_Z, sizeof(float));
for(int i=0; i<N; i++){
for(int j=0; j<N;j++){
wi_j[j] = w[N*i+j];
}
hipMemcpy(dev_wij, wi_j,size, hipMemcpyHostToDevice);
hipMemcpy(dev_Z, &Z[i], sizeof(float), hipMemcpyHostToDevice);
dim<<<N/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(dev_wij,dev_Z);
hipMemcpy(wi_j, dev_wij, size,hipMemcpyDeviceToHost);
for(int j=0; j<N;j++){
w[N*i+j] = wi_j[j];
If[i] += w[N*i+j] * J[j];
}
}
double time = toc(tStart);
toTXT(If,"IfCuda.txt",n,m);
float* Dif = (float*)malloc(N*sizeof(float));
for(int i=0; i<N; i++){
Dif[i] =If[i] - J[i];
}
toTXT(Dif,"DifCuda.txt",n,m);
printf("Time: %f sec", time);
hipFree(dev_I); hipFree(dev_I_norm); hipFree(dev_J); hipFree(dev_P); hipFree(dev_wij); hipFree(dev_Z);
free(I); free(I_norm); free(J); free(patch_i); free(gauss); free(wi_j); free(Z); free(If); free(Dif); free(w);
free(allPatches->patchArray);
free(allPatches);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13normalizationPfS_ff
.globl _Z13normalizationPfS_ff
.p2align 8
.type _Z13normalizationPfS_ff,@function
_Z13normalizationPfS_ff:
s_load_b32 s2, s[0:1], 0x24
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x1000, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_subrev_f32_e32 v2, s0, v2
v_div_scale_f32 v3, null, s1, s1, v2
v_div_scale_f32 v6, vcc_lo, v2, s1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
v_fmac_f32_e32 v4, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v5, v6, v4
v_fma_f32 v7, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v5, v7, v4
v_fma_f32 v3, -v3, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_div_fmas_f32 v3, v3, v4, v5
v_add_co_u32 v0, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
v_div_fixup_f32 v2, v3, s1, v2
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13normalizationPfS_ff
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13normalizationPfS_ff, .Lfunc_end0-_Z13normalizationPfS_ff
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z4distPfS_S_S_if
.globl _Z4distPfS_S_S_if
.p2align 8
.type _Z4distPfS_S_S_if,@function
_Z4distPfS_S_S_if:
s_load_b32 s2, s[0:1], 0x34
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x1000, v1
s_cbranch_execz .LBB1_6
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s3, 1
s_cbranch_scc1 .LBB1_4
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x8
s_load_b64 s[8:9], s[0:1], 0x18
v_mul_lo_u32 v2, v1, s3
v_mov_b32_e32 v0, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_mov_b32 s6, 0x3e76c4e1
.LBB1_3:
global_load_b32 v4, v[2:3], off
s_load_b32 s2, s[4:5], 0x0
s_load_b32 s7, s[8:9], 0x0
s_add_i32 s3, s3, -1
s_add_u32 s8, s8, 4
s_addc_u32 s9, s9, 0
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s3, 0
s_waitcnt vmcnt(0) lgkmcnt(0)
v_sub_f32_e32 v4, s2, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_frexp_mant_f32_e64 v5, |v4|
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v5
v_cndmask_b32_e64 v7, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v5, v5, v7
v_add_f32_e32 v7, 1.0, v5
v_frexp_exp_i32_f32_e32 v6, v4
v_cmp_neq_f32_e64 s2, 0x7f800000, |v4|
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_rcp_f32_e32 v9, v7
v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f32_i32_e32 v6, v6
v_dual_add_f32 v8, -1.0, v5 :: v_dual_mul_f32 v11, 0x3f317218, v6
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v12, v8, v9
v_add_f32_e32 v10, -1.0, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v10
v_fma_f32 v10, v6, 0x3f317218, -v11
v_fmac_f32_e32 v10, 0xb102e308, v6
v_mul_f32_e32 v6, v7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, v12, v7, -v6
v_fmac_f32_e32 v7, v12, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v6, v7
v_sub_f32_e32 v13, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v13
v_dual_sub_f32 v6, v5, v6 :: v_dual_sub_f32 v5, v8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v7
v_add_f32_e32 v5, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v13, v5
v_mul_f32_e32 v5, v9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v12, v5
v_sub_f32_e32 v7, v6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v8, v6, v6 :: v_dual_sub_f32 v5, v5, v7
v_fma_f32 v7, v6, v6, -v8
v_ldexp_f32 v9, v6, 1
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v12, v5, v5
v_ldexp_f32 v13, v5, 1
v_fmac_f32_e32 v7, v6, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, v8, v7
v_fmaak_f32 v14, s6, v12, 0x3e91f4c4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmaak_f32 v14, v12, v14, 0x3ecccdef
v_sub_f32_e32 v8, v12, v8
v_dual_mul_f32 v15, v6, v12 :: v_dual_mul_f32 v16, v12, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v7, v8
v_fma_f32 v8, v12, v6, -v15
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v8, v12, v5
v_fma_f32 v5, v12, v14, -v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v8, v7, v6
v_fmac_f32_e32 v5, v7, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v16, v5
v_sub_f32_e32 v14, v7, v16
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v5, v5, v14
v_dual_add_f32 v5, 0x31739010, v5 :: v_dual_add_f32 v6, v15, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v6, v15
v_dual_add_f32 v15, 0x3f2aaaaa, v7 :: v_dual_sub_f32 v8, v8, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v12, 0xbf2aaaaa, v15
v_sub_f32_e32 v7, v7, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v7
v_add_f32_e32 v7, v15, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v12, v15, v7
v_dual_mul_f32 v14, v6, v7 :: v_dual_add_f32 v5, v5, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v12, v6, v7, -v14
v_fmac_f32_e32 v12, v6, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v12, v8, v7
v_add_f32_e32 v5, v14, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v9, v5
v_sub_f32_e32 v7, v5, v14
v_dual_sub_f32 v7, v12, v7 :: v_dual_sub_f32 v8, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v7, v13, v7
v_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v8, v11, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, v7, v5
v_sub_f32_e32 v7, v8, v11
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v6, v5
v_dual_sub_f32 v7, v10, v7 :: v_dual_add_f32 v10, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v9, v6 :: v_dual_sub_f32 v11, v10, v8
v_dual_sub_f32 v5, v5, v6 :: v_dual_sub_f32 v6, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v8, v6 :: v_dual_sub_f32 v9, v9, v11
v_dual_add_f32 v11, v7, v5 :: v_dual_add_f32 v6, v9, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v11, v7
v_add_f32_e32 v6, v11, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v11, v8
v_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v8, v10, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v7, v9
v_sub_f32_e32 v9, v8, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v6, v6, v9 :: v_dual_add_f32 v5, v5, v7
v_add_f32_e32 v5, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v8, v5
v_sub_f32_e32 v7, v6, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_sub_f32 v5, v5, v7 :: v_dual_add_f32 v8, v6, v6
v_mul_f32_e32 v9, 0, v6
v_fma_f32 v6, v6, 2.0, -v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v9, 2.0, v5
v_cmp_class_f32_e64 vcc_lo, v8, 0x204
v_add_f32_e32 v5, v6, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v8, v5
v_cndmask_b32_e32 v7, v6, v8, vcc_lo
v_sub_f32_e32 v6, v6, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v7
v_sub_f32_e32 v5, v5, v6
v_cndmask_b32_e64 v9, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v7|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v10, v7, v9
v_cndmask_b32_e32 v5, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_mul_f32_e32 v11, 0x3fb8aa3b, v10
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v10
v_add_f32_e32 v5, v9, v5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v12, v10, 0x3fb8aa3b, -v11
v_rndne_f32_e32 v13, v11
v_dual_fmac_f32 v12, 0x32a5705f, v10 :: v_dual_sub_f32 v11, v11, v13
v_cvt_i32_f32_e32 v8, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v11, v11, v12
v_exp_f32_e32 v11, v11
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v11, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v10
v_cndmask_b32_e32 v6, 0x7f800000, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v5, v6, v5, v6
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v6
v_cndmask_b32_e32 v5, v5, v6, vcc_lo
v_add_co_u32 v2, vcc_lo, v2, 4
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v5, 0x7f800000, |v5|, s2
v_cmp_neq_f32_e64 s2, 0, v4
v_cndmask_b32_e64 v4, 0, v5, s2
s_delay_alu instid0(VALU_DEP_1)
v_fmac_f32_e32 v0, s7, v4
s_cbranch_scc0 .LBB1_3
s_branch .LBB1_5
.LBB1_4:
v_mov_b32_e32 v0, 0
.LBB1_5:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v2, 0x4f800000, v0
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
v_cndmask_b32_e32 v0, v0, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v2, v0
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v3, -1, v2
v_add_nc_u32_e32 v4, 1, v2
v_fma_f32 v5, -v3, v2, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v6, -v4, v2, v0
v_cmp_ge_f32_e64 s2, 0, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v2, v2, v3, s2
v_cmp_lt_f32_e64 s2, 0, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v2, v2, v4, s2
s_mov_b32 s2, 0x3e76c4e1
v_mul_f32_e32 v3, 0x37800000, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v0, 0x260
v_cndmask_b32_e32 v0, v2, v0, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_frexp_mant_f32_e64 v2, |v0|
v_cmp_neq_f32_e64 s3, 0x7f800000, |v0|
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
v_cndmask_b32_e64 v3, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ldexp_f32 v2, v2, v3
v_add_f32_e32 v3, 1.0, v2
v_add_f32_e32 v5, -1.0, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, -1.0, v3
v_sub_f32_e32 v2, v2, v7
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v8, v3, v6
v_fma_f32 v3, v6, v3, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v3, v6, v2
v_add_f32_e32 v2, v8, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v7, v5, v2 :: v_dual_sub_f32 v8, v2, v8
v_sub_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v3, v8, v3 :: v_dual_sub_f32 v2, v5, v2
v_add_f32_e32 v2, v3, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v7, v2
v_mul_f32_e32 v2, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v3, v6, v2
v_sub_f32_e32 v4, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v5, v3, v3 :: v_dual_sub_f32 v2, v2, v4
v_fma_f32 v4, v3, v3, -v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v2, v2
v_fmac_f32_e32 v4, v3, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v6, v5, v4
v_fmaak_f32 v7, s2, v6, 0x3e91f4c4
v_sub_f32_e32 v5, v6, v5
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmaak_f32 v7, v6, v7, 0x3ecccdef :: v_dual_sub_f32 v4, v4, v5
v_mul_f32_e32 v10, v3, v6
v_mul_f32_e32 v8, v6, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, v6, v3, -v10
v_fma_f32 v5, v6, v7, -v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v11, v6, v2
v_ldexp_f32 v2, v2, 1
v_fmac_f32_e32 v5, v4, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v11, v4, v3
v_ldexp_f32 v3, v3, 1
v_dual_add_f32 v7, v8, v5 :: v_dual_add_f32 v6, v10, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v8, v7, v8 :: v_dual_add_f32 v9, 0x3f2aaaaa, v7
v_dual_sub_f32 v5, v5, v8 :: v_dual_add_f32 v8, 0xbf2aaaaa, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v5, 0x31739010, v5
v_sub_f32_e32 v7, v7, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v5, v7
v_add_f32_e32 v4, v9, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v7, v9, v4
v_sub_f32_e32 v9, v6, v10
v_add_f32_e32 v5, v5, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v9, v11, v9 :: v_dual_mul_f32 v8, v6, v4
v_fma_f32 v7, v6, v4, -v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v7, v6, v5
v_frexp_exp_i32_f32_e32 v5, v0
v_fmac_f32_e32 v7, v9, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_subrev_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
v_add_f32_e32 v5, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f32_i32_e32 v4, v4
v_sub_f32_e32 v8, v5, v8
v_add_f32_e32 v6, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v7, v8
v_dual_mul_f32 v9, 0x3f317218, v4 :: v_dual_add_f32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, v4, 0x3f317218, -v9
v_dual_sub_f32 v3, v6, v3 :: v_dual_fmamk_f32 v4, v4, 0xb102e308, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v5, v3
v_add_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v5, v6, v2
v_sub_f32_e32 v6, v5, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v3, v9, v4 :: v_dual_sub_f32 v2, v2, v6
v_sub_f32_e32 v9, v3, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v4, v9
v_dual_add_f32 v7, v3, v5 :: v_dual_add_f32 v6, v4, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v7, v3
v_sub_f32_e32 v10, v7, v8
v_sub_f32_e32 v5, v5, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v3, v3, v10
v_add_f32_e32 v3, v5, v3
v_sub_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v2, v2, v5
v_add_f32_e32 v3, v6, v3
v_sub_f32_e32 v6, v6, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v8, v7, v3
v_sub_f32_e32 v4, v4, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v5, v8, v7 :: v_dual_add_f32 v2, v2, v4
v_sub_f32_e32 v3, v3, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v2, v3
v_add_f32_e32 v3, v8, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v4, v3, v8
v_dual_sub_f32 v2, v2, v4 :: v_dual_add_f32 v5, v3, v3
v_mul_f32_e32 v6, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v3, v3, 2.0, -v5
v_fmac_f32_e32 v6, 2.0, v2
v_cmp_class_f32_e64 vcc_lo, v5, 0x204
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v3, v6
v_add_f32_e32 v3, v5, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v4, v3, v5, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
v_cndmask_b32_e64 v6, 0, 0x37000000, vcc_lo
v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v4, v6
v_mul_f32_e32 v8, 0x3fb8aa3b, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v9, v7, 0x3fb8aa3b, -v8
v_rndne_f32_e32 v10, v8
v_dual_fmac_f32 v9, 0x32a5705f, v7 :: v_dual_sub_f32 v8, v8, v10
v_sub_f32_e32 v3, v3, v5
v_cvt_i32_f32_e32 v5, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v8, v8, v9
v_sub_f32_e32 v2, v2, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_exp_f32_e32 v8, v8
v_cndmask_b32_e32 v2, 0, v2, vcc_lo
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f32_e32 v2, v6, v2
s_waitcnt_depctr 0xfff
v_ldexp_f32 v3, v8, v5
v_cndmask_b32_e32 v3, 0, v3, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v3, 0x7f800000, v3, vcc_lo
v_fma_f32 v2, v3, v2, v3
v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v2, v2, v3, vcc_lo
v_cmp_neq_f32_e32 vcc_lo, 0, v0
v_cndmask_b32_e64 v2, 0x7f800000, |v2|, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v0, 0, v2, vcc_lo
s_waitcnt lgkmcnt(0)
v_div_scale_f32 v2, null, s2, s2, -v0
v_div_scale_f32 v5, vcc_lo, -v0, s2, -v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v3, v2
s_waitcnt_depctr 0xfff
v_fma_f32 v4, -v2, v3, 1.0
v_fmac_f32_e32 v3, v4, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v4, v5, v3
v_fma_f32 v6, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v6, v3
v_fma_f32 v2, -v2, v4, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v2, v2, v3, v4
v_div_fixup_f32 v3, v2, s2, -v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v0, 0x3fb8aa3b, v3
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v3
v_fma_f32 v2, v3, 0x3fb8aa3b, -v0
v_rndne_f32_e32 v4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fmac_f32_e32 v2, 0x32a5705f, v3
v_sub_f32_e32 v0, v0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v0, v0, v2
v_cvt_i32_f32_e32 v2, v4
v_exp_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_ldexp_f32 v0, v0, v2
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v4, 0, v0, vcc_lo
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, 0x7f800000, v4, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_4)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v2, off
.LBB1_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4distPfS_S_S_if
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 17
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z4distPfS_S_S_if, .Lfunc_end1-_Z4distPfS_S_S_if
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z3dimPfS_
.globl _Z3dimPfS_
.p2align 8
.type _Z3dimPfS_,@function
_Z3dimPfS_:
s_load_b32 s2, s[0:1], 0x1c
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 0x1000, v1
s_cbranch_execz .LBB2_2
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_load_b32 s0, s[2:3], 0x0
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0) lgkmcnt(0)
v_div_scale_f32 v3, null, s0, s0, v2
v_rcp_f32_e32 v4, v3
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_div_scale_f32 v5, vcc_lo, v2, s0, v2
v_mul_f32_e32 v6, v5, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v6, v5
v_fmac_f32_e32 v6, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v6, v5
v_div_fmas_f32 v3, v3, v4, v6
s_delay_alu instid0(VALU_DEP_1)
v_div_fixup_f32 v2, v3, s0, v2
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3dimPfS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z3dimPfS_, .Lfunc_end2-_Z3dimPfS_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13normalizationPfS_ff
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13normalizationPfS_ff.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4distPfS_S_S_if
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4distPfS_S_S_if.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 17
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3dimPfS_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3dimPfS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* kernelFunctions.cpp - Functions used by the device (the GPU)
* in the (obviously) GPU implementaiton of our algorithm.
*/
#include <iostream>
__global__
void kernel_internalMemcpy(double *dest, const double *from, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for (int idx = start_idx; idx < max_val; idx += stride)
dest[idx] = from[idx];
}
/**
* KernelConvolve - Computes the discrete convolution C=Filter*Image.
* The dimensions of the image and C are both W x H, while the dimension
* of the filter is f_W x f_H.
*/
__global__
void kernel_convolve(const double *Filter, const double *Image, double *C, const unsigned W,
const unsigned H, const unsigned f_W, const unsigned f_H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
// will not execute if start_idx<max_val
for (int c_idx = start_idx; c_idx < max_val; c_idx += stride)
{
C[c_idx] = 0;
// get the single c_idx term in 2D terms
unsigned i = c_idx / (3*W); // image and filter height index
unsigned j_tmp = c_idx % (3*W); // image width index
unsigned j = j_tmp/3; // filter width index
unsigned pixel = j_tmp%3;
unsigned n_max = (W < f_W+j) ? W : f_W+j;
unsigned m_max = (H < f_H+i) ? H : f_H+i;
for (int m=i; m<m_max; ++m)
for (int n=j; n<n_max; ++n)
C[c_idx] += Filter[ (m-i)*f_W+(n-j) ] * Image[m*3*W + pixel+3*n];
}
}
/**
* KernelElementWiseDivision - Executes an elementwise division C = A/B.
* The dimensions of A, B, and C are all assumed to be W x H.
*/
__global__
void kernel_elementWiseDivision(const double *A, const double *B, double *C, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for (int idx=start_idx; idx < max_val; idx += stride)
C[idx] = (B[idx] == 0) ? 1 : A[idx]/B[idx];
}
/**
* KernelElementWiseMultiplication - Executes an elementwise multiplication C = A*B.
* The dimensions of A, B, and C are all assumed to be W x H.
*/
__global__
void kernel_elementWiseMultiplication(const double *A, const double *B, double *C, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for(int idx = start_idx; idx < max_val; idx += stride)
C[idx] = A[idx]*B[idx];
} | .file "tmpxft_0008b4a1_00000000-6_kernelFunctions.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj
.type _Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj, @function
_Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj:
.LFB3693:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21kernel_internalMemcpyPdPKdjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3693:
.size _Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj, .-_Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj
.globl _Z21kernel_internalMemcpyPdPKdjj
.type _Z21kernel_internalMemcpyPdPKdjj, @function
_Z21kernel_internalMemcpyPdPKdjj:
.LFB3694:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3694:
.size _Z21kernel_internalMemcpyPdPKdjj, .-_Z21kernel_internalMemcpyPdPKdjj
.globl _Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj
.type _Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj, @function
_Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj:
.LFB3695:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15kernel_convolvePKdS0_Pdjjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj, .-_Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj
.globl _Z15kernel_convolvePKdS0_Pdjjjj
.type _Z15kernel_convolvePKdS0_Pdjjjj, @function
_Z15kernel_convolvePKdS0_Pdjjjj:
.LFB3696:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z15kernel_convolvePKdS0_Pdjjjj, .-_Z15kernel_convolvePKdS0_Pdjjjj
.globl _Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj
.type _Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj, @function
_Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26kernel_elementWiseDivisionPKdS0_Pdjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj, .-_Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj
.globl _Z26kernel_elementWiseDivisionPKdS0_Pdjj
.type _Z26kernel_elementWiseDivisionPKdS0_Pdjj, @function
_Z26kernel_elementWiseDivisionPKdS0_Pdjj:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z26kernel_elementWiseDivisionPKdS0_Pdjj, .-_Z26kernel_elementWiseDivisionPKdS0_Pdjj
.globl _Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj
.type _Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj, @function
_Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj, .-_Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj
.globl _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.type _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, @function
_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, .-_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj"
.align 8
.LC1:
.string "_Z26kernel_elementWiseDivisionPKdS0_Pdjj"
.align 8
.LC2:
.string "_Z15kernel_convolvePKdS0_Pdjjjj"
.align 8
.LC3:
.string "_Z21kernel_internalMemcpyPdPKdjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z26kernel_elementWiseDivisionPKdS0_Pdjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kernel_convolvePKdS0_Pdjjjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z21kernel_internalMemcpyPdPKdjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* kernelFunctions.cpp - Functions used by the device (the GPU)
* in the (obviously) GPU implementaiton of our algorithm.
*/
#include <iostream>
__global__
void kernel_internalMemcpy(double *dest, const double *from, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for (int idx = start_idx; idx < max_val; idx += stride)
dest[idx] = from[idx];
}
/**
* KernelConvolve - Computes the discrete convolution C=Filter*Image.
* The dimensions of the image and C are both W x H, while the dimension
* of the filter is f_W x f_H.
*/
__global__
void kernel_convolve(const double *Filter, const double *Image, double *C, const unsigned W,
const unsigned H, const unsigned f_W, const unsigned f_H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
// will not execute if start_idx<max_val
for (int c_idx = start_idx; c_idx < max_val; c_idx += stride)
{
C[c_idx] = 0;
// get the single c_idx term in 2D terms
unsigned i = c_idx / (3*W); // image and filter height index
unsigned j_tmp = c_idx % (3*W); // image width index
unsigned j = j_tmp/3; // filter width index
unsigned pixel = j_tmp%3;
unsigned n_max = (W < f_W+j) ? W : f_W+j;
unsigned m_max = (H < f_H+i) ? H : f_H+i;
for (int m=i; m<m_max; ++m)
for (int n=j; n<n_max; ++n)
C[c_idx] += Filter[ (m-i)*f_W+(n-j) ] * Image[m*3*W + pixel+3*n];
}
}
/**
* KernelElementWiseDivision - Executes an elementwise division C = A/B.
* The dimensions of A, B, and C are all assumed to be W x H.
*/
__global__
void kernel_elementWiseDivision(const double *A, const double *B, double *C, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for (int idx=start_idx; idx < max_val; idx += stride)
C[idx] = (B[idx] == 0) ? 1 : A[idx]/B[idx];
}
/**
* KernelElementWiseMultiplication - Executes an elementwise multiplication C = A*B.
* The dimensions of A, B, and C are all assumed to be W x H.
*/
__global__
void kernel_elementWiseMultiplication(const double *A, const double *B, double *C, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for(int idx = start_idx; idx < max_val; idx += stride)
C[idx] = A[idx]*B[idx];
} | /**
* kernelFunctions.cpp - Functions used by the device (the GPU)
* in the (obviously) GPU implementaiton of our algorithm.
*/
#include <hip/hip_runtime.h>
#include <iostream>
__global__
void kernel_internalMemcpy(double *dest, const double *from, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for (int idx = start_idx; idx < max_val; idx += stride)
dest[idx] = from[idx];
}
/**
* KernelConvolve - Computes the discrete convolution C=Filter*Image.
* The dimensions of the image and C are both W x H, while the dimension
* of the filter is f_W x f_H.
*/
__global__
void kernel_convolve(const double *Filter, const double *Image, double *C, const unsigned W,
const unsigned H, const unsigned f_W, const unsigned f_H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
// will not execute if start_idx<max_val
for (int c_idx = start_idx; c_idx < max_val; c_idx += stride)
{
C[c_idx] = 0;
// get the single c_idx term in 2D terms
unsigned i = c_idx / (3*W); // image and filter height index
unsigned j_tmp = c_idx % (3*W); // image width index
unsigned j = j_tmp/3; // filter width index
unsigned pixel = j_tmp%3;
unsigned n_max = (W < f_W+j) ? W : f_W+j;
unsigned m_max = (H < f_H+i) ? H : f_H+i;
for (int m=i; m<m_max; ++m)
for (int n=j; n<n_max; ++n)
C[c_idx] += Filter[ (m-i)*f_W+(n-j) ] * Image[m*3*W + pixel+3*n];
}
}
/**
* KernelElementWiseDivision - Executes an elementwise division C = A/B.
* The dimensions of A, B, and C are all assumed to be W x H.
*/
__global__
void kernel_elementWiseDivision(const double *A, const double *B, double *C, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for (int idx=start_idx; idx < max_val; idx += stride)
C[idx] = (B[idx] == 0) ? 1 : A[idx]/B[idx];
}
/**
* KernelElementWiseMultiplication - Executes an elementwise multiplication C = A*B.
* The dimensions of A, B, and C are all assumed to be W x H.
*/
__global__
void kernel_elementWiseMultiplication(const double *A, const double *B, double *C, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for(int idx = start_idx; idx < max_val; idx += stride)
C[idx] = A[idx]*B[idx];
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* kernelFunctions.cpp - Functions used by the device (the GPU)
* in the (obviously) GPU implementaiton of our algorithm.
*/
#include <hip/hip_runtime.h>
#include <iostream>
__global__
void kernel_internalMemcpy(double *dest, const double *from, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for (int idx = start_idx; idx < max_val; idx += stride)
dest[idx] = from[idx];
}
/**
* KernelConvolve - Computes the discrete convolution C=Filter*Image.
* The dimensions of the image and C are both W x H, while the dimension
* of the filter is f_W x f_H.
*/
__global__
void kernel_convolve(const double *Filter, const double *Image, double *C, const unsigned W,
const unsigned H, const unsigned f_W, const unsigned f_H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
// will not execute if start_idx<max_val
for (int c_idx = start_idx; c_idx < max_val; c_idx += stride)
{
C[c_idx] = 0;
// get the single c_idx term in 2D terms
unsigned i = c_idx / (3*W); // image and filter height index
unsigned j_tmp = c_idx % (3*W); // image width index
unsigned j = j_tmp/3; // filter width index
unsigned pixel = j_tmp%3;
unsigned n_max = (W < f_W+j) ? W : f_W+j;
unsigned m_max = (H < f_H+i) ? H : f_H+i;
for (int m=i; m<m_max; ++m)
for (int n=j; n<n_max; ++n)
C[c_idx] += Filter[ (m-i)*f_W+(n-j) ] * Image[m*3*W + pixel+3*n];
}
}
/**
* KernelElementWiseDivision - Executes an elementwise division C = A/B.
* The dimensions of A, B, and C are all assumed to be W x H.
*/
__global__
void kernel_elementWiseDivision(const double *A, const double *B, double *C, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for (int idx=start_idx; idx < max_val; idx += stride)
C[idx] = (B[idx] == 0) ? 1 : A[idx]/B[idx];
}
/**
* KernelElementWiseMultiplication - Executes an elementwise multiplication C = A*B.
* The dimensions of A, B, and C are all assumed to be W x H.
*/
__global__
void kernel_elementWiseMultiplication(const double *A, const double *B, double *C, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for(int idx = start_idx; idx < max_val; idx += stride)
C[idx] = A[idx]*B[idx];
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z21kernel_internalMemcpyPdPKdjj
.globl _Z21kernel_internalMemcpyPdPKdjj
.p2align 8
.type _Z21kernel_internalMemcpyPdPKdjj,@function
_Z21kernel_internalMemcpyPdPKdjj:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x24
s_load_b64 s[4:5], s[0:1], 0x10
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s6, 0xffff
s_mul_i32 s8, s4, s5
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_mul_i32 s8, s8, 3
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB0_3
s_load_b32 s2, s[2:3], 0x0
s_load_b128 s[4:7], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s2, s9
s_mov_b32 s2, 0
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s8, v1
v_add_co_u32 v2, s0, s4, v2
global_load_b64 v[4:5], v[4:5], off
v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
s_or_b32 s2, vcc_lo, s2
s_waitcnt vmcnt(0)
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s2
s_cbranch_execnz .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z21kernel_internalMemcpyPdPKdjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z21kernel_internalMemcpyPdPKdjj, .Lfunc_end0-_Z21kernel_internalMemcpyPdPKdjj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z15kernel_convolvePKdS0_Pdjjjj
.globl _Z15kernel_convolvePKdS0_Pdjjjj
.p2align 8
.type _Z15kernel_convolvePKdS0_Pdjjjj,@function
_Z15kernel_convolvePKdS0_Pdjjjj:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x34
s_load_b64 s[2:3], s[0:1], 0x18
s_add_u32 s4, s0, 40
s_addc_u32 s5, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s12, s6, 0xffff
s_mul_i32 s14, s2, s3
v_mad_u64_u32 v[1:2], null, s15, s12, v[0:1]
s_mul_i32 s14, s14, 3
s_mov_b32 s6, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s14, v1
s_cbranch_execz .LBB1_9
s_mul_i32 s15, s2, 3
s_load_b32 s13, s[4:5], 0x0
v_cvt_f32_u32_e32 v0, s15
s_sub_i32 s6, 0, s15
s_mov_b32 s16, 0
v_mov_b32_e32 v3, 0
v_mov_b32_e32 v11, 0
v_rcp_iflag_f32_e32 v0, v0
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v0, 0x4f7ffffe, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_u32_f32_e32 v0, v0
v_mul_lo_u32 v2, s6, v0
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[8:9], s[0:1], 0x10
s_load_b64 s[10:11], s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s13, s12
s_mov_b32 s13, 0
v_mul_hi_u32 v2, v0, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v0, v0, v2
s_branch .LBB1_3
.LBB1_2:
s_set_inst_prefetch_distance 0x2
s_or_b32 exec_lo, exec_lo, s17
v_add_nc_u32_e32 v1, s1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_u32_e32 vcc_lo, s14, v1
s_or_b32 s16, vcc_lo, s16
s_and_not1_b32 exec_lo, exec_lo, s16
s_cbranch_execz .LBB1_9
.LBB1_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_hi_u32 v2, v1, v0
s_mov_b32 s17, exec_lo
v_mul_lo_u32 v4, v2, s15
v_add_nc_u32_e32 v5, 1, v2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v1, v4
v_subrev_nc_u32_e32 v6, s15, v4
v_cmp_le_u32_e32 vcc_lo, s15, v4
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v2, v2, v5, vcc_lo
v_cndmask_b32_e32 v4, v4, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v5, 1, v2
v_cmp_le_u32_e32 vcc_lo, s15, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v12, v2, v5, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
v_add_nc_u32_e32 v4, s11, v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 3, v[1:2]
v_min_u32_e32 v2, s3, v4
v_mov_b32_e32 v4, v3
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v5, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
global_store_b64 v[5:6], v[3:4], off
v_cmpx_lt_u32_e64 v12, v2
s_cbranch_execz .LBB1_2
v_mul_lo_u32 v4, v12, s15
s_mov_b32 s18, 0
s_mov_b32 s19, 0
v_mov_b32_e32 v14, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_nc_u32_e32 v4, v1, v4
v_mul_hi_u32 v4, v4, 0xaaaaaaab
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshrrev_b32_e32 v4, 1, v4
v_add_nc_u32_e32 v7, s10, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_min_u32_e32 v13, s2, v7
v_cmp_lt_u32_e32 vcc_lo, v4, v13
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_6
.p2align 6
.LBB1_5:
s_or_b32 exec_lo, exec_lo, s20
v_add_nc_u32_e32 v12, 1, v12
v_add_nc_u32_e32 v14, s15, v14
s_add_i32 s19, s19, s10
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_u32_e64 s0, v12, v2
s_or_b32 s18, s0, s18
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s18
s_cbranch_execz .LBB1_2
.LBB1_6:
s_and_saveexec_b32 s20, vcc_lo
s_cbranch_execz .LBB1_5
global_load_b64 v[7:8], v[5:6], off
v_mov_b32_e32 v9, v14
v_mov_b32_e32 v15, v4
s_mov_b32 s21, 0
s_mov_b32 s12, s19
.p2align 6
.LBB1_8:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_dual_mov_b32 v10, 0 :: v_dual_add_nc_u32 v15, 1, v15
s_lshl_b64 s[22:23], s[12:13], 3
s_add_u32 s22, s4, s22
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[16:17], 3, v[9:10]
s_addc_u32 s23, s5, s23
v_add_nc_u32_e32 v9, 3, v9
s_add_i32 s12, s12, 1
v_add_co_u32 v16, s0, s6, v16
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v17, s0, s7, v17, s0
v_cmp_ge_u32_e64 s0, v15, v13
global_load_b64 v[18:19], v11, s[22:23]
global_load_b64 v[16:17], v[16:17], off
s_or_b32 s21, s0, s21
s_waitcnt vmcnt(0)
v_fma_f64 v[7:8], v[18:19], v[16:17], v[7:8]
global_store_b64 v[5:6], v[7:8], off
s_and_not1_b32 exec_lo, exec_lo, s21
s_cbranch_execnz .LBB1_8
s_branch .LBB1_5
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z15kernel_convolvePKdS0_Pdjjjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 24
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z15kernel_convolvePKdS0_Pdjjjj, .Lfunc_end1-_Z15kernel_convolvePKdS0_Pdjjjj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z26kernel_elementWiseDivisionPKdS0_Pdjj
.globl _Z26kernel_elementWiseDivisionPKdS0_Pdjj
.p2align 8
.type _Z26kernel_elementWiseDivisionPKdS0_Pdjj,@function
_Z26kernel_elementWiseDivisionPKdS0_Pdjj:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s6, 0xffff
s_mul_i32 s8, s4, s5
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_mul_i32 s8, s8, 3
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB2_5
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
s_branch .LBB2_3
.LBB2_2:
s_or_b32 exec_lo, exec_lo, s0
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
v_cmp_le_u32_e32 vcc_lo, s8, v1
global_store_b64 v[2:3], v[6:7], off
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execz .LBB2_5
.LBB2_3:
v_ashrrev_i32_e32 v2, 31, v1
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0x3ff00000
s_mov_b32 s0, exec_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_co_u32 v4, vcc_lo, s6, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
global_load_b64 v[4:5], v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_neq_f64_e32 0, v[4:5]
s_cbranch_execz .LBB2_2
v_add_co_u32 v6, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
global_load_b64 v[6:7], v[6:7], off
s_waitcnt vmcnt(0)
v_div_scale_f64 v[8:9], null, v[4:5], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[10:11], v[8:9]
s_waitcnt_depctr 0xfff
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
v_div_scale_f64 v[12:13], vcc_lo, v[6:7], v[4:5], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[14:15], v[12:13], v[10:11]
v_fma_f64 v[8:9], -v[8:9], v[14:15], v[12:13]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[14:15]
v_div_fixup_f64 v[6:7], v[8:9], v[4:5], v[6:7]
s_branch .LBB2_2
.LBB2_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26kernel_elementWiseDivisionPKdS0_Pdjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 16
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z26kernel_elementWiseDivisionPKdS0_Pdjj, .Lfunc_end2-_Z26kernel_elementWiseDivisionPKdS0_Pdjj
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.globl _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.p2align 8
.type _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj,@function
_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj:
s_clause 0x1
s_load_b32 s6, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_add_u32 s2, s0, 32
s_addc_u32 s3, s1, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s9, s6, 0xffff
s_mul_i32 s8, s4, s5
v_mad_u64_u32 v[1:2], null, s15, s9, v[0:1]
s_mul_i32 s8, s8, 3
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u32_e64 s8, v1
s_cbranch_execz .LBB3_3
s_load_b32 s10, s[2:3], 0x0
s_clause 0x1
s_load_b128 s[4:7], s[0:1], 0x0
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_mul_i32 s1, s10, s9
s_mov_b32 s9, 0
.p2align 6
.LBB3_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 3, v[1:2]
v_add_nc_u32_e32 v1, s1, v1
v_add_co_u32 v4, vcc_lo, s4, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_add_co_u32 v6, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
v_cmp_le_u32_e32 vcc_lo, s8, v1
global_load_b64 v[4:5], v[4:5], off
global_load_b64 v[6:7], v[6:7], off
v_add_co_u32 v2, s0, s2, v2
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, s3, v3, s0
s_or_b32 s9, vcc_lo, s9
s_waitcnt vmcnt(0)
v_mul_f64 v[4:5], v[4:5], v[6:7]
global_store_b64 v[2:3], v[4:5], off
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB3_2
.LBB3_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, .Lfunc_end3-_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z21kernel_internalMemcpyPdPKdjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z21kernel_internalMemcpyPdPKdjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 36
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z15kernel_convolvePKdS0_Pdjjjj
.private_segment_fixed_size: 0
.sgpr_count: 26
.sgpr_spill_count: 0
.symbol: _Z15kernel_convolvePKdS0_Pdjjjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26kernel_elementWiseDivisionPKdS0_Pdjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26kernel_elementWiseDivisionPKdS0_Pdjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 16
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* kernelFunctions.cpp - Functions used by the device (the GPU)
* in the (obviously) GPU implementaiton of our algorithm.
*/
#include <hip/hip_runtime.h>
#include <iostream>
__global__
void kernel_internalMemcpy(double *dest, const double *from, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for (int idx = start_idx; idx < max_val; idx += stride)
dest[idx] = from[idx];
}
/**
* KernelConvolve - Computes the discrete convolution C=Filter*Image.
* The dimensions of the image and C are both W x H, while the dimension
* of the filter is f_W x f_H.
*/
__global__
void kernel_convolve(const double *Filter, const double *Image, double *C, const unsigned W,
const unsigned H, const unsigned f_W, const unsigned f_H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
// will not execute if start_idx<max_val
for (int c_idx = start_idx; c_idx < max_val; c_idx += stride)
{
C[c_idx] = 0;
// get the single c_idx term in 2D terms
unsigned i = c_idx / (3*W); // image and filter height index
unsigned j_tmp = c_idx % (3*W); // image width index
unsigned j = j_tmp/3; // filter width index
unsigned pixel = j_tmp%3;
unsigned n_max = (W < f_W+j) ? W : f_W+j;
unsigned m_max = (H < f_H+i) ? H : f_H+i;
for (int m=i; m<m_max; ++m)
for (int n=j; n<n_max; ++n)
C[c_idx] += Filter[ (m-i)*f_W+(n-j) ] * Image[m*3*W + pixel+3*n];
}
}
/**
* KernelElementWiseDivision - Executes an elementwise division C = A/B.
* The dimensions of A, B, and C are all assumed to be W x H.
*/
__global__
void kernel_elementWiseDivision(const double *A, const double *B, double *C, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for (int idx=start_idx; idx < max_val; idx += stride)
C[idx] = (B[idx] == 0) ? 1 : A[idx]/B[idx];
}
/**
* KernelElementWiseMultiplication - Executes an elementwise multiplication C = A*B.
* The dimensions of A, B, and C are all assumed to be W x H.
*/
__global__
void kernel_elementWiseMultiplication(const double *A, const double *B, double *C, const unsigned W, const unsigned H)
{
const unsigned start_idx = blockDim.x * blockIdx.x + threadIdx.x;
const unsigned stride = blockDim.x * gridDim.x;
const unsigned max_val = 3*H*W;
for(int idx = start_idx; idx < max_val; idx += stride)
C[idx] = A[idx]*B[idx];
} | .text
.file "kernelFunctions.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z36__device_stub__kernel_internalMemcpyPdPKdjj # -- Begin function _Z36__device_stub__kernel_internalMemcpyPdPKdjj
.p2align 4, 0x90
.type _Z36__device_stub__kernel_internalMemcpyPdPKdjj,@function
_Z36__device_stub__kernel_internalMemcpyPdPKdjj: # @_Z36__device_stub__kernel_internalMemcpyPdPKdjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21kernel_internalMemcpyPdPKdjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__kernel_internalMemcpyPdPKdjj, .Lfunc_end0-_Z36__device_stub__kernel_internalMemcpyPdPKdjj
.cfi_endproc
# -- End function
.globl _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj # -- Begin function _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj
.p2align 4, 0x90
.type _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj,@function
_Z30__device_stub__kernel_convolvePKdS0_Pdjjjj: # @_Z30__device_stub__kernel_convolvePKdS0_Pdjjjj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15kernel_convolvePKdS0_Pdjjjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj, .Lfunc_end1-_Z30__device_stub__kernel_convolvePKdS0_Pdjjjj
.cfi_endproc
# -- End function
.globl _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj # -- Begin function _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj
.p2align 4, 0x90
.type _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj,@function
_Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj: # @_Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_elementWiseDivisionPKdS0_Pdjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj, .Lfunc_end2-_Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj
.cfi_endproc
# -- End function
.globl _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj # -- Begin function _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj
.p2align 4, 0x90
.type _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj,@function
_Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj: # @_Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj, .Lfunc_end3-_Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21kernel_internalMemcpyPdPKdjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernel_convolvePKdS0_Pdjjjj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26kernel_elementWiseDivisionPKdS0_Pdjj, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21kernel_internalMemcpyPdPKdjj,@object # @_Z21kernel_internalMemcpyPdPKdjj
.section .rodata,"a",@progbits
.globl _Z21kernel_internalMemcpyPdPKdjj
.p2align 3, 0x0
_Z21kernel_internalMemcpyPdPKdjj:
.quad _Z36__device_stub__kernel_internalMemcpyPdPKdjj
.size _Z21kernel_internalMemcpyPdPKdjj, 8
.type _Z15kernel_convolvePKdS0_Pdjjjj,@object # @_Z15kernel_convolvePKdS0_Pdjjjj
.globl _Z15kernel_convolvePKdS0_Pdjjjj
.p2align 3, 0x0
_Z15kernel_convolvePKdS0_Pdjjjj:
.quad _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj
.size _Z15kernel_convolvePKdS0_Pdjjjj, 8
.type _Z26kernel_elementWiseDivisionPKdS0_Pdjj,@object # @_Z26kernel_elementWiseDivisionPKdS0_Pdjj
.globl _Z26kernel_elementWiseDivisionPKdS0_Pdjj
.p2align 3, 0x0
_Z26kernel_elementWiseDivisionPKdS0_Pdjj:
.quad _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj
.size _Z26kernel_elementWiseDivisionPKdS0_Pdjj, 8
.type _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj,@object # @_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.globl _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.p2align 3, 0x0
_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj:
.quad _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj
.size _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21kernel_internalMemcpyPdPKdjj"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15kernel_convolvePKdS0_Pdjjjj"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z26kernel_elementWiseDivisionPKdS0_Pdjj"
.size .L__unnamed_3, 41
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj"
.size .L__unnamed_4, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__kernel_internalMemcpyPdPKdjj
.addrsig_sym _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj
.addrsig_sym _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj
.addrsig_sym _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21kernel_internalMemcpyPdPKdjj
.addrsig_sym _Z15kernel_convolvePKdS0_Pdjjjj
.addrsig_sym _Z26kernel_elementWiseDivisionPKdS0_Pdjj
.addrsig_sym _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0008b4a1_00000000-6_kernelFunctions.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3671:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3671:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj
.type _Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj, @function
_Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj:
.LFB3693:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z21kernel_internalMemcpyPdPKdjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3693:
.size _Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj, .-_Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj
.globl _Z21kernel_internalMemcpyPdPKdjj
.type _Z21kernel_internalMemcpyPdPKdjj, @function
_Z21kernel_internalMemcpyPdPKdjj:
.LFB3694:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z21kernel_internalMemcpyPdPKdjjPdPKdjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3694:
.size _Z21kernel_internalMemcpyPdPKdjj, .-_Z21kernel_internalMemcpyPdPKdjj
.globl _Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj
.type _Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj, @function
_Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj:
.LFB3695:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
leaq 192(%rsp), %rax
movq %rax, 160(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z15kernel_convolvePKdS0_Pdjjjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3695:
.size _Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj, .-_Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj
.globl _Z15kernel_convolvePKdS0_Pdjjjj
.type _Z15kernel_convolvePKdS0_Pdjjjj, @function
_Z15kernel_convolvePKdS0_Pdjjjj:
.LFB3696:
.cfi_startproc
endbr64
subq $16, %rsp
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z45__device_stub__Z15kernel_convolvePKdS0_PdjjjjPKdS0_Pdjjjj
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3696:
.size _Z15kernel_convolvePKdS0_Pdjjjj, .-_Z15kernel_convolvePKdS0_Pdjjjj
.globl _Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj
.type _Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj, @function
_Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj:
.LFB3697:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26kernel_elementWiseDivisionPKdS0_Pdjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3697:
.size _Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj, .-_Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj
.globl _Z26kernel_elementWiseDivisionPKdS0_Pdjj
.type _Z26kernel_elementWiseDivisionPKdS0_Pdjj, @function
_Z26kernel_elementWiseDivisionPKdS0_Pdjj:
.LFB3698:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z54__device_stub__Z26kernel_elementWiseDivisionPKdS0_PdjjPKdS0_Pdjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3698:
.size _Z26kernel_elementWiseDivisionPKdS0_Pdjj, .-_Z26kernel_elementWiseDivisionPKdS0_Pdjj
.globl _Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj
.type _Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj, @function
_Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj:
.LFB3699:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3699:
.size _Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj, .-_Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj
.globl _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.type _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, @function
_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj:
.LFB3700:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z60__device_stub__Z32kernel_elementWiseMultiplicationPKdS0_PdjjPKdS0_Pdjj
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3700:
.size _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, .-_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj"
.align 8
.LC1:
.string "_Z26kernel_elementWiseDivisionPKdS0_Pdjj"
.align 8
.LC2:
.string "_Z15kernel_convolvePKdS0_Pdjjjj"
.align 8
.LC3:
.string "_Z21kernel_internalMemcpyPdPKdjj"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3702:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z26kernel_elementWiseDivisionPKdS0_Pdjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z15kernel_convolvePKdS0_Pdjjjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z21kernel_internalMemcpyPdPKdjj(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3702:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernelFunctions.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z36__device_stub__kernel_internalMemcpyPdPKdjj # -- Begin function _Z36__device_stub__kernel_internalMemcpyPdPKdjj
.p2align 4, 0x90
.type _Z36__device_stub__kernel_internalMemcpyPdPKdjj,@function
_Z36__device_stub__kernel_internalMemcpyPdPKdjj: # @_Z36__device_stub__kernel_internalMemcpyPdPKdjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z21kernel_internalMemcpyPdPKdjj, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z36__device_stub__kernel_internalMemcpyPdPKdjj, .Lfunc_end0-_Z36__device_stub__kernel_internalMemcpyPdPKdjj
.cfi_endproc
# -- End function
.globl _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj # -- Begin function _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj
.p2align 4, 0x90
.type _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj,@function
_Z30__device_stub__kernel_convolvePKdS0_Pdjjjj: # @_Z30__device_stub__kernel_convolvePKdS0_Pdjjjj
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 160(%rsp), %rax
movq %rax, 144(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z15kernel_convolvePKdS0_Pdjjjj, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end1:
.size _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj, .Lfunc_end1-_Z30__device_stub__kernel_convolvePKdS0_Pdjjjj
.cfi_endproc
# -- End function
.globl _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj # -- Begin function _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj
.p2align 4, 0x90
.type _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj,@function
_Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj: # @_Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_elementWiseDivisionPKdS0_Pdjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj, .Lfunc_end2-_Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj
.cfi_endproc
# -- End function
.globl _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj # -- Begin function _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj
.p2align 4, 0x90
.type _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj,@function
_Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj: # @_Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end3:
.size _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj, .Lfunc_end3-_Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z21kernel_internalMemcpyPdPKdjj, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z15kernel_convolvePKdS0_Pdjjjj, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26kernel_elementWiseDivisionPKdS0_Pdjj, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z21kernel_internalMemcpyPdPKdjj,@object # @_Z21kernel_internalMemcpyPdPKdjj
.section .rodata,"a",@progbits
.globl _Z21kernel_internalMemcpyPdPKdjj
.p2align 3, 0x0
_Z21kernel_internalMemcpyPdPKdjj:
.quad _Z36__device_stub__kernel_internalMemcpyPdPKdjj
.size _Z21kernel_internalMemcpyPdPKdjj, 8
.type _Z15kernel_convolvePKdS0_Pdjjjj,@object # @_Z15kernel_convolvePKdS0_Pdjjjj
.globl _Z15kernel_convolvePKdS0_Pdjjjj
.p2align 3, 0x0
_Z15kernel_convolvePKdS0_Pdjjjj:
.quad _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj
.size _Z15kernel_convolvePKdS0_Pdjjjj, 8
.type _Z26kernel_elementWiseDivisionPKdS0_Pdjj,@object # @_Z26kernel_elementWiseDivisionPKdS0_Pdjj
.globl _Z26kernel_elementWiseDivisionPKdS0_Pdjj
.p2align 3, 0x0
_Z26kernel_elementWiseDivisionPKdS0_Pdjj:
.quad _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj
.size _Z26kernel_elementWiseDivisionPKdS0_Pdjj, 8
.type _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj,@object # @_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.globl _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.p2align 3, 0x0
_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj:
.quad _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj
.size _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z21kernel_internalMemcpyPdPKdjj"
.size .L__unnamed_1, 33
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z15kernel_convolvePKdS0_Pdjjjj"
.size .L__unnamed_2, 32
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z26kernel_elementWiseDivisionPKdS0_Pdjj"
.size .L__unnamed_3, 41
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z32kernel_elementWiseMultiplicationPKdS0_Pdjj"
.size .L__unnamed_4, 47
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z36__device_stub__kernel_internalMemcpyPdPKdjj
.addrsig_sym _Z30__device_stub__kernel_convolvePKdS0_Pdjjjj
.addrsig_sym _Z41__device_stub__kernel_elementWiseDivisionPKdS0_Pdjj
.addrsig_sym _Z47__device_stub__kernel_elementWiseMultiplicationPKdS0_Pdjj
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z21kernel_internalMemcpyPdPKdjj
.addrsig_sym _Z15kernel_convolvePKdS0_Pdjjjj
.addrsig_sym _Z26kernel_elementWiseDivisionPKdS0_Pdjj
.addrsig_sym _Z32kernel_elementWiseMultiplicationPKdS0_Pdjj
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Matrix multiplication: AxB=C
//CUDA kernel. Each thread takes care of one cell of C matrix
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
}
extern "C" void matmul_wrapper(int n, double h_a[], double h_b[], double h_c[])
{
// Device input matrices
double *d_a;
double *d_b;
// Device output matrices
double *d_c;
//Size, in bytes, of each array
size_t bytes = n*n*sizeof(double);
// Allocate memory for each matrix on GPU
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
printf(" C Memory allocated \n");
// Copy host matrices to device
cudaMemcpy(d_a,h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b, bytes, cudaMemcpyHostToDevice);
printf(" C Data sent to GPU \n");
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 32;
// Number of thread blocks in grid
gridSize = (int)ceil((double)n/blockSize);
dim3 dimBlock(blockSize,blockSize);
dim3 dimGrid(gridSize,gridSize);
printf(" GridSize: %d\n", gridSize);
printf(" BlockSize: %d\n", blockSize);
// Execute the kernel
matmul<<<dimGrid, dimBlock>>>(d_a,d_b,d_c, n);
printf(" C Kernel executed \n");
// Copy array back to host
cudaMemcpy(h_c, d_c, bytes, cudaMemcpyDeviceToHost);
// CHECK RESULTS for 3x3 MATRIX
// printf("%f %f %f\n",h_a[0],h_a[1],h_a[2]);
// printf("%f %f %f\n",h_a[3],h_a[4],h_a[5]);
// printf("%f %f %f\n",h_a[6],h_a[7],h_a[8]);
// printf("\n");
// printf("%f %f %f\n",h_b[0],h_b[1],h_b[2]);
// printf("%f %f %f\n",h_b[3],h_b[4],h_b[5]);
// printf("%f %f %f\n",h_b[6],h_b[7],h_b[8]);
// printf("\n");
// printf("%f %f %f\n",h_c[0],h_c[1],h_c[2]);
// printf("%f %f %f\n",h_c[3],h_c[4],h_c[5]);
// printf("%f %f %f\n",h_c[6],h_c[7],h_c[8]);
// Release device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf(" C =============== \n");
} | code for sm_80
Function : _Z6matmulPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Matrix multiplication: AxB=C
//CUDA kernel. Each thread takes care of one cell of C matrix
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
}
extern "C" void matmul_wrapper(int n, double h_a[], double h_b[], double h_c[])
{
// Device input matrices
double *d_a;
double *d_b;
// Device output matrices
double *d_c;
//Size, in bytes, of each array
size_t bytes = n*n*sizeof(double);
// Allocate memory for each matrix on GPU
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
printf(" C Memory allocated \n");
// Copy host matrices to device
cudaMemcpy(d_a,h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b, bytes, cudaMemcpyHostToDevice);
printf(" C Data sent to GPU \n");
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 32;
// Number of thread blocks in grid
gridSize = (int)ceil((double)n/blockSize);
dim3 dimBlock(blockSize,blockSize);
dim3 dimGrid(gridSize,gridSize);
printf(" GridSize: %d\n", gridSize);
printf(" BlockSize: %d\n", blockSize);
// Execute the kernel
matmul<<<dimGrid, dimBlock>>>(d_a,d_b,d_c, n);
printf(" C Kernel executed \n");
// Copy array back to host
cudaMemcpy(h_c, d_c, bytes, cudaMemcpyDeviceToHost);
// CHECK RESULTS for 3x3 MATRIX
// printf("%f %f %f\n",h_a[0],h_a[1],h_a[2]);
// printf("%f %f %f\n",h_a[3],h_a[4],h_a[5]);
// printf("%f %f %f\n",h_a[6],h_a[7],h_a[8]);
// printf("\n");
// printf("%f %f %f\n",h_b[0],h_b[1],h_b[2]);
// printf("%f %f %f\n",h_b[3],h_b[4],h_b[5]);
// printf("%f %f %f\n",h_b[6],h_b[7],h_b[8]);
// printf("\n");
// printf("%f %f %f\n",h_c[0],h_c[1],h_c[2]);
// printf("%f %f %f\n",h_c[3],h_c[4],h_c[5]);
// printf("%f %f %f\n",h_c[6],h_c[7],h_c[8]);
// Release device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf(" C =============== \n");
} | .file "tmpxft_000d43ab_00000000-6_matMulWrapperF2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6matmulPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matmulPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
.globl _Z6matmulPdS_S_i
.type _Z6matmulPdS_S_i, @function
_Z6matmulPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6matmulPdS_S_i, .-_Z6matmulPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " C Memory allocated \n"
.LC1:
.string " C Data sent to GPU \n"
.LC6:
.string " GridSize: %d\n"
.LC7:
.string " BlockSize: %d\n"
.LC8:
.string " C Kernel executed \n"
.LC9:
.string " C =============== \n"
.text
.globl matmul_wrapper
.type matmul_wrapper, @function
matmul_wrapper:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movq %rsi, %r14
movq %rdx, %r13
movq %rcx, %r12
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edi, %ebx
imull %edi, %ebx
movslq %ebx, %rbx
salq $3, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC2(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC10(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L12
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L12:
cvttsd2sil %xmm3, %edx
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl %edx, 44(%rsp)
movl %edx, 48(%rsp)
movl $1, 52(%rsp)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size matmul_wrapper, .-matmul_wrapper
.section .rodata.str1.1
.LC11:
.string "_Z6matmulPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmulPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1067450368
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC10:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Matrix multiplication: AxB=C
//CUDA kernel. Each thread takes care of one cell of C matrix
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
}
extern "C" void matmul_wrapper(int n, double h_a[], double h_b[], double h_c[])
{
// Device input matrices
double *d_a;
double *d_b;
// Device output matrices
double *d_c;
//Size, in bytes, of each array
size_t bytes = n*n*sizeof(double);
// Allocate memory for each matrix on GPU
cudaMalloc(&d_a, bytes);
cudaMalloc(&d_b, bytes);
cudaMalloc(&d_c, bytes);
printf(" C Memory allocated \n");
// Copy host matrices to device
cudaMemcpy(d_a,h_a, bytes, cudaMemcpyHostToDevice);
cudaMemcpy(d_b,h_b, bytes, cudaMemcpyHostToDevice);
printf(" C Data sent to GPU \n");
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 32;
// Number of thread blocks in grid
gridSize = (int)ceil((double)n/blockSize);
dim3 dimBlock(blockSize,blockSize);
dim3 dimGrid(gridSize,gridSize);
printf(" GridSize: %d\n", gridSize);
printf(" BlockSize: %d\n", blockSize);
// Execute the kernel
matmul<<<dimGrid, dimBlock>>>(d_a,d_b,d_c, n);
printf(" C Kernel executed \n");
// Copy array back to host
cudaMemcpy(h_c, d_c, bytes, cudaMemcpyDeviceToHost);
// CHECK RESULTS for 3x3 MATRIX
// printf("%f %f %f\n",h_a[0],h_a[1],h_a[2]);
// printf("%f %f %f\n",h_a[3],h_a[4],h_a[5]);
// printf("%f %f %f\n",h_a[6],h_a[7],h_a[8]);
// printf("\n");
// printf("%f %f %f\n",h_b[0],h_b[1],h_b[2]);
// printf("%f %f %f\n",h_b[3],h_b[4],h_b[5]);
// printf("%f %f %f\n",h_b[6],h_b[7],h_b[8]);
// printf("\n");
// printf("%f %f %f\n",h_c[0],h_c[1],h_c[2]);
// printf("%f %f %f\n",h_c[3],h_c[4],h_c[5]);
// printf("%f %f %f\n",h_c[6],h_c[7],h_c[8]);
// Release device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
printf(" C =============== \n");
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Matrix multiplication: AxB=C
//CUDA kernel. Each thread takes care of one cell of C matrix
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
}
extern "C" void matmul_wrapper(int n, double h_a[], double h_b[], double h_c[])
{
// Device input matrices
double *d_a;
double *d_b;
// Device output matrices
double *d_c;
//Size, in bytes, of each array
size_t bytes = n*n*sizeof(double);
// Allocate memory for each matrix on GPU
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
printf(" C Memory allocated \n");
// Copy host matrices to device
hipMemcpy(d_a,h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b, bytes, hipMemcpyHostToDevice);
printf(" C Data sent to GPU \n");
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 32;
// Number of thread blocks in grid
gridSize = (int)ceil((double)n/blockSize);
dim3 dimBlock(blockSize,blockSize);
dim3 dimGrid(gridSize,gridSize);
printf(" GridSize: %d\n", gridSize);
printf(" BlockSize: %d\n", blockSize);
// Execute the kernel
matmul<<<dimGrid, dimBlock>>>(d_a,d_b,d_c, n);
printf(" C Kernel executed \n");
// Copy array back to host
hipMemcpy(h_c, d_c, bytes, hipMemcpyDeviceToHost);
// CHECK RESULTS for 3x3 MATRIX
// printf("%f %f %f\n",h_a[0],h_a[1],h_a[2]);
// printf("%f %f %f\n",h_a[3],h_a[4],h_a[5]);
// printf("%f %f %f\n",h_a[6],h_a[7],h_a[8]);
// printf("\n");
// printf("%f %f %f\n",h_b[0],h_b[1],h_b[2]);
// printf("%f %f %f\n",h_b[3],h_b[4],h_b[5]);
// printf("%f %f %f\n",h_b[6],h_b[7],h_b[8]);
// printf("\n");
// printf("%f %f %f\n",h_c[0],h_c[1],h_c[2]);
// printf("%f %f %f\n",h_c[3],h_c[4],h_c[5]);
// printf("%f %f %f\n",h_c[6],h_c[7],h_c[8]);
// Release device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf(" C =============== \n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Matrix multiplication: AxB=C
//CUDA kernel. Each thread takes care of one cell of C matrix
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
}
extern "C" void matmul_wrapper(int n, double h_a[], double h_b[], double h_c[])
{
// Device input matrices
double *d_a;
double *d_b;
// Device output matrices
double *d_c;
//Size, in bytes, of each array
size_t bytes = n*n*sizeof(double);
// Allocate memory for each matrix on GPU
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
printf(" C Memory allocated \n");
// Copy host matrices to device
hipMemcpy(d_a,h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b, bytes, hipMemcpyHostToDevice);
printf(" C Data sent to GPU \n");
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 32;
// Number of thread blocks in grid
gridSize = (int)ceil((double)n/blockSize);
dim3 dimBlock(blockSize,blockSize);
dim3 dimGrid(gridSize,gridSize);
printf(" GridSize: %d\n", gridSize);
printf(" BlockSize: %d\n", blockSize);
// Execute the kernel
matmul<<<dimGrid, dimBlock>>>(d_a,d_b,d_c, n);
printf(" C Kernel executed \n");
// Copy array back to host
hipMemcpy(h_c, d_c, bytes, hipMemcpyDeviceToHost);
// CHECK RESULTS for 3x3 MATRIX
// printf("%f %f %f\n",h_a[0],h_a[1],h_a[2]);
// printf("%f %f %f\n",h_a[3],h_a[4],h_a[5]);
// printf("%f %f %f\n",h_a[6],h_a[7],h_a[8]);
// printf("\n");
// printf("%f %f %f\n",h_b[0],h_b[1],h_b[2]);
// printf("%f %f %f\n",h_b[3],h_b[4],h_b[5]);
// printf("%f %f %f\n",h_b[6],h_b[7],h_b[8]);
// printf("\n");
// printf("%f %f %f\n",h_c[0],h_c[1],h_c[2]);
// printf("%f %f %f\n",h_c[3],h_c[4],h_c[5]);
// printf("%f %f %f\n",h_c[6],h_c[7],h_c[8]);
// Release device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf(" C =============== \n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPdS_S_i
.globl _Z6matmulPdS_S_i
.p2align 8
.type _Z6matmulPdS_S_i,@function
_Z6matmulPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmulPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmulPdS_S_i, .Lfunc_end0-_Z6matmulPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmulPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmulPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
// Matrix multiplication: AxB=C
//CUDA kernel. Each thread takes care of one cell of C matrix
__global__ void matmul(double *a, double *b, double *c, int n)
{
// Get global thread ID
int Col = blockIdx.x*blockDim.x+threadIdx.x;
int Row = blockIdx.y*blockDim.y+threadIdx.y;
// Not out of bounds
if((Col<n) && (Row<n)) {// Mutliply matrices
// c[Row*n + Col] = 0;
double sum = 0.0;
for(int k=0;k<n;k++) {
// c[Row*n + Col] += a[Row*n+k]*b[k*n+Col];
sum += a[Row*n+k]*b[k*n+Col];
}
c[Row*n + Col] = sum;
}
}
extern "C" void matmul_wrapper(int n, double h_a[], double h_b[], double h_c[])
{
// Device input matrices
double *d_a;
double *d_b;
// Device output matrices
double *d_c;
//Size, in bytes, of each array
size_t bytes = n*n*sizeof(double);
// Allocate memory for each matrix on GPU
hipMalloc(&d_a, bytes);
hipMalloc(&d_b, bytes);
hipMalloc(&d_c, bytes);
printf(" C Memory allocated \n");
// Copy host matrices to device
hipMemcpy(d_a,h_a, bytes, hipMemcpyHostToDevice);
hipMemcpy(d_b,h_b, bytes, hipMemcpyHostToDevice);
printf(" C Data sent to GPU \n");
int blockSize, gridSize;
// Number of threads in each thread block
blockSize = 32;
// Number of thread blocks in grid
gridSize = (int)ceil((double)n/blockSize);
dim3 dimBlock(blockSize,blockSize);
dim3 dimGrid(gridSize,gridSize);
printf(" GridSize: %d\n", gridSize);
printf(" BlockSize: %d\n", blockSize);
// Execute the kernel
matmul<<<dimGrid, dimBlock>>>(d_a,d_b,d_c, n);
printf(" C Kernel executed \n");
// Copy array back to host
hipMemcpy(h_c, d_c, bytes, hipMemcpyDeviceToHost);
// CHECK RESULTS for 3x3 MATRIX
// printf("%f %f %f\n",h_a[0],h_a[1],h_a[2]);
// printf("%f %f %f\n",h_a[3],h_a[4],h_a[5]);
// printf("%f %f %f\n",h_a[6],h_a[7],h_a[8]);
// printf("\n");
// printf("%f %f %f\n",h_b[0],h_b[1],h_b[2]);
// printf("%f %f %f\n",h_b[3],h_b[4],h_b[5]);
// printf("%f %f %f\n",h_b[6],h_b[7],h_b[8]);
// printf("\n");
// printf("%f %f %f\n",h_c[0],h_c[1],h_c[2]);
// printf("%f %f %f\n",h_c[3],h_c[4],h_c[5]);
// printf("%f %f %f\n",h_c[6],h_c[7],h_c[8]);
// Release device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
printf(" C =============== \n");
} | .text
.file "matMulWrapperF2.hip"
.globl _Z21__device_stub__matmulPdS_S_i # -- Begin function _Z21__device_stub__matmulPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matmulPdS_S_i,@function
_Z21__device_stub__matmulPdS_S_i: # @_Z21__device_stub__matmulPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matmulPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matmulPdS_S_i, .Lfunc_end0-_Z21__device_stub__matmulPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function matmul_wrapper
.LCPI1_0:
.quad 0x3fa0000000000000 # double 0.03125
.text
.globl matmul_wrapper
.p2align 4, 0x90
.type matmul_wrapper,@function
matmul_wrapper: # @matmul_wrapper
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r12
movl %edi, %ebp
movl %edi, %r14d
imull %r14d, %r14d
shlq $3, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
cvtsi2sd %ebp, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %esi
movq %rsi, %r15
shlq $32, %r15
orq %rsi, %r15
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $32, %esi
xorl %eax, %eax
callq printf
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matmulPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr.2, %edi
callq puts@PLT
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr.3, %edi
callq puts@PLT
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size matmul_wrapper, .Lfunc_end1-matmul_wrapper
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmulPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmulPdS_S_i,@object # @_Z6matmulPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6matmulPdS_S_i
.p2align 3, 0x0
_Z6matmulPdS_S_i:
.quad _Z21__device_stub__matmulPdS_S_i
.size _Z6matmulPdS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz " GridSize: %d\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " BlockSize: %d\n"
.size .L.str.3, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matmulPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " C Memory allocated "
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " C Data sent to GPU "
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " C Kernel executed "
.size .Lstr.2, 20
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " C =============== "
.size .Lstr.3, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmulPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmulPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6matmulPdS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*0020*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e280000002200 */
/*0030*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e680000002500 */
/*0040*/ S2R R5, SR_TID.X ; /* 0x0000000000057919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R3, R3, c[0x0][0x4], R2 ; /* 0x0000010003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R5 ; /* 0x0000000000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD R3, R3, c[0x0][0x178], RZ ; /* 0x00005e0003037a24 */
/* 0x000fe200078e02ff */
/*00d0*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*00e0*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fda0003f06270 */
/*00f0*/ @!P0 BRA 0xc40 ; /* 0x00000b4000008947 */
/* 0x000fea0003800000 */
/*0100*/ IADD3 R4, R2.reuse, -0x1, RZ ; /* 0xffffffff02047810 */
/* 0x040fe20007ffe0ff */
/*0110*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*0120*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe400078ec0ff */
/*0130*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe20003f06070 */
/*0140*/ HFMA2.MMA R4, -RZ, RZ, 0, 0 ; /* 0x00000000ff047435 */
/* 0x000fd800000001ff */
/*0150*/ @!P0 BRA 0xb00 ; /* 0x000009a000008947 */
/* 0x000fea0003800000 */
/*0160*/ IADD3 R26, -R5, c[0x0][0x178], RZ ; /* 0x00005e00051a7a10 */
/* 0x000fe20007ffe1ff */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ MOV R23, 0x8 ; /* 0x0000000800177802 */
/* 0x000fe20000000f00 */
/*0190*/ CS2R R8, SRZ ; /* 0x0000000000087805 */
/* 0x000fe2000001ff00 */
/*01a0*/ ISETP.GT.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe40003f04270 */
/*01b0*/ MOV R4, RZ ; /* 0x000000ff00047202 */
/* 0x000fe20000000f00 */
/*01c0*/ IMAD.WIDE R22, R0, R23, c[0x0][0x168] ; /* 0x00005a0000167625 */
/* 0x000fd400078e0217 */
/*01d0*/ @!P0 BRA 0x970 ; /* 0x0000079000008947 */
/* 0x000fea0003800000 */
/*01e0*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe40003f24270 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0200*/ @!P1 BRA 0x6b0 ; /* 0x000004a000009947 */
/* 0x000fea0003800000 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0220*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fe20008000f00 */
/*0230*/ IMAD.U32 R28, RZ, RZ, UR6 ; /* 0x00000006ff1c7e24 */
/* 0x000fe2000f8e00ff */
/*0240*/ LDG.E.64 R18, [R22.64] ; /* 0x0000000416127981 */
/* 0x001ea6000c1e1b00 */
/*0250*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0260*/ LDG.E.64 R6, [R28.64] ; /* 0x000000041c067981 */
/* 0x000ea2000c1e1b00 */
/*0270*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fc600078e0216 */
/*0280*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0290*/ LDG.E.64 R16, [R20.64] ; /* 0x0000000414107981 */
/* 0x0000e8000c1e1b00 */
/*02a0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000f22000c1e1b00 */
/*02b0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*02c0*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*02d0*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*02e0*/ DFMA R8, R18, R6, R8 ; /* 0x000000061208722b */
/* 0x0060c80000000008 */
/*02f0*/ LDG.E.64 R6, [R24.64] ; /* 0x0000000418067981 */
/* 0x0010a8000c1e1b00 */
/*0300*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000ea2000c1e1b00 */
/*0310*/ DFMA R12, R16, R12, R8 ; /* 0x0000000c100c722b */
/* 0x0083060000000008 */
/*0320*/ LDG.E.64 R16, [R28.64+0x20] ; /* 0x000020041c107981 */
/* 0x002ee2000c1e1b00 */
/*0330*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*0340*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x000ee2000c1e1b00 */
/*0350*/ IMAD.WIDE R22, R2.reuse, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x040fe200078e0218 */
/*0360*/ DFMA R14, R10, R14, R12 ; /* 0x0000000e0a0e722b */
/* 0x0100a4000000000c */
/*0370*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x001f28000c1e1b00 */
/*0380*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000f22000c1e1b00 */
/*0390*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*03a0*/ DFMA R18, R6, R18, R14 ; /* 0x000000120612722b */
/* 0x0040c4000000000e */
/*03b0*/ LDG.E.64 R14, [R28.64+0x30] ; /* 0x000030041c0e7981 */
/* 0x001ea8000c1e1b00 */
/*03c0*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000a2000c1e1b00 */
/*03d0*/ DFMA R16, R8, R16, R18 ; /* 0x000000100810722b */
/* 0x0083060000000012 */
/*03e0*/ LDG.E.64 R18, [R28.64+0x38] ; /* 0x000038041c127981 */
/* 0x002ee2000c1e1b00 */
/*03f0*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0400*/ LDG.E.64 R8, [R20.64] ; /* 0x0000000414087981 */
/* 0x000ee2000c1e1b00 */
/*0410*/ IMAD.WIDE R24, R2.reuse, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x040fe200078e0214 */
/*0420*/ DFMA R10, R12, R10, R16 ; /* 0x0000000a0c0a722b */
/* 0x0100a40000000010 */
/*0430*/ LDG.E.64 R16, [R28.64+0x40] ; /* 0x000040041c107981 */
/* 0x001f28000c1e1b00 */
/*0440*/ LDG.E.64 R12, [R24.64] ; /* 0x00000004180c7981 */
/* 0x000122000c1e1b00 */
/*0450*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fc600078e0218 */
/*0460*/ LDG.E.64 R24, [R28.64+0x58] ; /* 0x000058041c187981 */
/* 0x001f62000c1e1b00 */
/*0470*/ DFMA R14, R6, R14, R10 ; /* 0x0000000e060e722b */
/* 0x0040c6000000000a */
/*0480*/ LDG.E.64 R10, [R28.64+0x48] ; /* 0x000048041c0a7981 */
/* 0x001ea8000c1e1b00 */
/*0490*/ LDG.E.64 R6, [R22.64] ; /* 0x0000000416067981 */
/* 0x0000a4000c1e1b00 */
/*04a0*/ IMAD.WIDE R22, R2.reuse, 0x8, R22 ; /* 0x0000000802167825 */
/* 0x041fe200078e0216 */
/*04b0*/ DFMA R18, R8, R18, R14 ; /* 0x000000120812722b */
/* 0x008124000000000e */
/*04c0*/ LDG.E.64 R14, [R28.64+0x50] ; /* 0x000050041c0e7981 */
/* 0x001ee8000c1e1b00 */
/*04d0*/ LDG.E.64 R8, [R22.64] ; /* 0x0000000416087981 */
/* 0x0000e2000c1e1b00 */
/*04e0*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*04f0*/ DFMA R16, R12, R16, R18 ; /* 0x000000100c10722b */
/* 0x0102880000000012 */
/*0500*/ LDG.E.64 R12, [R20.64] ; /* 0x00000004140c7981 */
/* 0x002364000c1e1b00 */
/*0510*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*0520*/ LDG.E.64 R22, [R20.64] ; /* 0x0000000414167981 */
/* 0x001122000c1e1b00 */
/*0530*/ IMAD.WIDE R18, R2.reuse, 0x8, R20 ; /* 0x0000000802127825 */
/* 0x040fe200078e0214 */
/*0540*/ DFMA R10, R6, R10, R16 ; /* 0x0000000a060a722b */
/* 0x0042e40000000010 */
/*0550*/ LDG.E.64 R6, [R28.64+0x60] ; /* 0x000060041c067981 */
/* 0x002f26000c1e1b00 */
/*0560*/ IMAD.WIDE R16, R2, 0x8, R18 ; /* 0x0000000802107825 */
/* 0x000fe200078e0212 */
/*0570*/ DFMA R14, R8, R14, R10 ; /* 0x0000000e080e722b */
/* 0x008364000000000a */
/*0580*/ LDG.E.64 R8, [R28.64+0x68] ; /* 0x000068041c087981 */
/* 0x002ea8000c1e1b00 */
/*0590*/ LDG.E.64 R10, [R18.64] ; /* 0x00000004120a7981 */
/* 0x0002a2000c1e1b00 */
/*05a0*/ DFMA R24, R12, R24, R14 ; /* 0x000000180c18722b */
/* 0x020706000000000e */
/*05b0*/ LDG.E.64 R12, [R28.64+0x70] ; /* 0x000070041c0c7981 */
/* 0x008ee8000c1e1b00 */
/*05c0*/ LDG.E.64 R14, [R16.64] ; /* 0x00000004100e7981 */
/* 0x000ae8000c1e1b00 */
/*05d0*/ LDG.E.64 R18, [R28.64+0x78] ; /* 0x000078041c127981 */
/* 0x002ee2000c1e1b00 */
/*05e0*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x020fca00078e0210 */
/*05f0*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x001f62000c1e1b00 */
/*0600*/ IADD3 R26, R26, -0x10, RZ ; /* 0xfffffff01a1a7810 */
/* 0x000fc80007ffe0ff */
/*0610*/ ISETP.GT.AND P1, PT, R26, 0xc, PT ; /* 0x0000000c1a00780c */
/* 0x000fe20003f24270 */
/*0620*/ UIADD3 UR6, UP0, UR6, 0x80, URZ ; /* 0x0000008006067890 */
/* 0x000fe2000ff1e03f */
/*0630*/ IADD3 R4, R4, 0x10, RZ ; /* 0x0000001004047810 */
/* 0x000fc60007ffe0ff */
/*0640*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0650*/ DFMA R6, R22, R6, R24 ; /* 0x000000061606722b */
/* 0x0100a40000000018 */
/*0660*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x001fc800078e0210 */
/*0670*/ DFMA R6, R10, R8, R6 ; /* 0x000000080a06722b */
/* 0x004ecc0000000006 */
/*0680*/ DFMA R6, R14, R12, R6 ; /* 0x0000000c0e06722b */
/* 0x008f4c0000000006 */
/*0690*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200620000000006 */
/*06a0*/ @P1 BRA 0x220 ; /* 0xfffffb7000001947 */
/* 0x000fea000383ffff */
/*06b0*/ ISETP.GT.AND P1, PT, R26, 0x4, PT ; /* 0x000000041a00780c */
/* 0x000fda0003f24270 */
/*06c0*/ @!P1 BRA 0x950 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*06d0*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*06e0*/ LDG.E.64 R16, [R22.64] ; /* 0x0000000416107981 */
/* 0x000ea2000c1e1b00 */
/*06f0*/ MOV R29, UR7 ; /* 0x00000007001d7c02 */
/* 0x000fca0008000f00 */
/*0700*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fca00078e021c */
/*0710*/ LDG.E.64 R14, [R28.64] ; /* 0x000000041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*0720*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x001fc600078e0216 */
/*0730*/ LDG.E.64 R12, [R28.64+0x8] ; /* 0x000008041c0c7981 */
/* 0x000ee8000c1e1b00 */
/*0740*/ LDG.E.64 R6, [R20.64] ; /* 0x0000000414067981 */
/* 0x0000e8000c1e1b00 */
/*0750*/ LDG.E.64 R18, [R28.64+0x10] ; /* 0x000010041c127981 */
/* 0x000f22000c1e1b00 */
/*0760*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x001fca00078e0214 */
/*0770*/ LDG.E.64 R10, [R20.64] ; /* 0x00000004140a7981 */
/* 0x000f22000c1e1b00 */
/*0780*/ IMAD.WIDE R24, R2, 0x8, R20 ; /* 0x0000000802187825 */
/* 0x000fe200078e0214 */
/*0790*/ DFMA R8, R16, R14, R8 ; /* 0x0000000e1008722b */
/* 0x0060c80000000008 */
/*07a0*/ LDG.E.64 R16, [R24.64] ; /* 0x0000000418107981 */
/* 0x0010a8000c1e1b00 */
/*07b0*/ LDG.E.64 R14, [R28.64+0x18] ; /* 0x000018041c0e7981 */
/* 0x000ea2000c1e1b00 */
/*07c0*/ DFMA R12, R6, R12, R8 ; /* 0x0000000c060c722b */
/* 0x0083060000000008 */
/*07d0*/ LDG.E.64 R6, [R28.64+0x20] ; /* 0x000020041c067981 */
/* 0x002ee2000c1e1b00 */
/*07e0*/ IMAD.WIDE R24, R2, 0x8, R24 ; /* 0x0000000802187825 */
/* 0x001fca00078e0218 */
/*07f0*/ LDG.E.64 R8, [R24.64] ; /* 0x0000000418087981 */
/* 0x0000e2000c1e1b00 */
/*0800*/ IMAD.WIDE R22, R2, 0x8, R24 ; /* 0x0000000802167825 */
/* 0x000fe200078e0218 */
/*0810*/ DFMA R18, R10, R18, R12 ; /* 0x000000120a12722b */
/* 0x01028a000000000c */
/*0820*/ IMAD.WIDE R20, R2, 0x8, R22 ; /* 0x0000000802147825 */
/* 0x000fe200078e0216 */
/*0830*/ LDG.E.64 R10, [R28.64+0x28] ; /* 0x000028041c0a7981 */
/* 0x002f28000c1e1b00 */
/*0840*/ LDG.E.64 R12, [R22.64] ; /* 0x00000004160c7981 */
/* 0x000328000c1e1b00 */
/*0850*/ LDG.E.64 R22, [R28.64+0x38] ; /* 0x000038041c167981 */
/* 0x002f62000c1e1b00 */
/*0860*/ DFMA R14, R16, R14, R18 ; /* 0x0000000e100e722b */
/* 0x0042c60000000012 */
/*0870*/ LDG.E.64 R16, [R28.64+0x30] ; /* 0x000030041c107981 */
/* 0x002ea8000c1e1b00 */
/*0880*/ LDG.E.64 R18, [R20.64] ; /* 0x0000000414127981 */
/* 0x0002a4000c1e1b00 */
/*0890*/ IMAD.WIDE R20, R2, 0x8, R20 ; /* 0x0000000802147825 */
/* 0x002fca00078e0214 */
/*08a0*/ LDG.E.64 R24, [R20.64] ; /* 0x0000000414187981 */
/* 0x001f62000c1e1b00 */
/*08b0*/ DFMA R6, R8, R6, R14 ; /* 0x000000060806722b */
/* 0x008f0c000000000e */
/*08c0*/ DFMA R6, R12, R10, R6 ; /* 0x0000000a0c06722b */
/* 0x010ea20000000006 */
/*08d0*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*08e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*08f0*/ IADD3 R4, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007ffe0ff */
/*0900*/ IADD3 R26, R26, -0x8, RZ ; /* 0xfffffff81a1a7810 */
/* 0x000fe20007ffe0ff */
/*0910*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0920*/ DFMA R6, R18, R16, R6 ; /* 0x000000101206722b */
/* 0x004f4c0000000006 */
/*0930*/ DFMA R8, R24, R22, R6 ; /* 0x000000161808722b */
/* 0x0200640000000006 */
/*0940*/ IMAD.WIDE R22, R2, 0x8, R20 ; /* 0x0000000802167825 */
/* 0x001fc800078e0214 */
/*0950*/ ISETP.NE.OR P0, PT, R26, RZ, P0 ; /* 0x000000ff1a00720c */
/* 0x002fda0000705670 */
/*0960*/ @!P0 BRA 0xb00 ; /* 0x0000019000008947 */
/* 0x000fea0003800000 */
/*0970*/ MOV R28, UR6 ; /* 0x00000006001c7c02 */
/* 0x000fe20008000f00 */
/*0980*/ IMAD.U32 R29, RZ, RZ, UR7 ; /* 0x00000007ff1d7e24 */
/* 0x000fe2000f8e00ff */
/*0990*/ LDG.E.64 R24, [R22.64] ; /* 0x0000000416187981 */
/* 0x0002a6000c1e1b00 */
/*09a0*/ IMAD.WIDE R28, R3, 0x8, R28 ; /* 0x00000008031c7825 */
/* 0x000fc800078e021c */
/*09b0*/ IMAD.WIDE R10, R2.reuse, 0x8, R22 ; /* 0x00000008020a7825 */
/* 0x040fe200078e0216 */
/*09c0*/ LDG.E.64 R14, [R28.64+0x10] ; /* 0x000010041c0e7981 */
/* 0x000ee8000c1e1b00 */
/*09d0*/ LDG.E.64 R22, [R28.64] ; /* 0x000000041c167981 */
/* 0x002ea2000c1e1b00 */
/*09e0*/ IMAD.WIDE R16, R2, 0x8, R10 ; /* 0x0000000802107825 */
/* 0x000fc600078e020a */
/*09f0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x001128000c1e1b00 */
/*0a00*/ LDG.E.64 R12, [R16.64] ; /* 0x00000004100c7981 */
/* 0x0002e8000c1e1b00 */
/*0a10*/ LDG.E.64 R18, [R28.64+0x18] ; /* 0x000018041c127981 */
/* 0x000f68000c1e1b00 */
/*0a20*/ LDG.E.64 R10, [R28.64+0x8] ; /* 0x000008041c0a7981 */
/* 0x001f22000c1e1b00 */
/*0a30*/ IMAD.WIDE R16, R2, 0x8, R16 ; /* 0x0000000802107825 */
/* 0x002fca00078e0210 */
/*0a40*/ LDG.E.64 R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000f62000c1e1b00 */
/*0a50*/ IADD3 R26, R26, -0x4, RZ ; /* 0xfffffffc1a1a7810 */
/* 0x000fc80007ffe0ff */
/*0a60*/ ISETP.NE.AND P0, PT, R26, RZ, PT ; /* 0x000000ff1a00720c */
/* 0x000fe20003f05270 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ IADD3 R4, R4, 0x4, RZ ; /* 0x0000000404047810 */
/* 0x000fc60007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ DFMA R22, R24, R22, R8 ; /* 0x000000161816722b */
/* 0x004f0c0000000008 */
/*0ab0*/ DFMA R6, R6, R10, R22 ; /* 0x0000000a0606722b */
/* 0x010ecc0000000016 */
/*0ac0*/ DFMA R6, R12, R14, R6 ; /* 0x0000000e0c06722b */
/* 0x008f620000000006 */
/*0ad0*/ IMAD.WIDE R22, R2, 0x8, R16 ; /* 0x0000000802167825 */
/* 0x000fca00078e0210 */
/*0ae0*/ DFMA R8, R20, R18, R6 ; /* 0x000000121408722b */
/* 0x0200640000000006 */
/*0af0*/ @P0 BRA 0x970 ; /* 0xfffffe7000000947 */
/* 0x003fea000383ffff */
/*0b00*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0b10*/ @!P0 BRA 0xc40 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0b20*/ IADD3 R6, R3, R4, RZ ; /* 0x0000000403067210 */
/* 0x001fe20007ffe0ff */
/*0b30*/ IMAD R4, R4, c[0x0][0x178], R0 ; /* 0x00005e0004047a24 */
/* 0x000fe200078e0200 */
/*0b40*/ MOV R11, 0x8 ; /* 0x00000008000b7802 */
/* 0x000fca0000000f00 */
/*0b50*/ IMAD.WIDE R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fc800078e020b */
/*0b60*/ IMAD.WIDE R10, R4, R11, c[0x0][0x168] ; /* 0x00005a00040a7625 */
/* 0x000fe200078e020b */
/*0b70*/ MOV R4, R6 ; /* 0x0000000600047202 */
/* 0x000fe40000000f00 */
/*0b80*/ MOV R15, R7 ; /* 0x00000007000f7202 */
/* 0x000fc60000000f00 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x001fe200078e0004 */
/*0ba0*/ MOV R13, R15 ; /* 0x0000000f000d7202 */
/* 0x000fe20000000f00 */
/*0bb0*/ LDG.E.64 R6, [R10.64] ; /* 0x000000040a067981 */
/* 0x0000aa000c1e1b00 */
/*0bc0*/ LDG.E.64 R12, [R12.64] ; /* 0x000000040c0c7981 */
/* 0x000ea2000c1e1b00 */
/*0bd0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fc40007ffe0ff */
/*0be0*/ IADD3 R4, P1, R4, 0x8, RZ ; /* 0x0000000804047810 */
/* 0x000fe40007f3e0ff */
/*0bf0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fe20003f05270 */
/*0c00*/ IMAD.WIDE R10, R2, 0x8, R10 ; /* 0x00000008020a7825 */
/* 0x001fe200078e020a */
/*0c10*/ IADD3.X R15, RZ, R15, RZ, P1, !PT ; /* 0x0000000fff0f7210 */
/* 0x000fe20000ffe4ff */
/*0c20*/ DFMA R8, R6, R12, R8 ; /* 0x0000000c0608722b */
/* 0x0060540000000008 */
/*0c30*/ @P0 BRA 0xb90 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0c40*/ IADD3 R3, R0, R3, RZ ; /* 0x0000000300037210 */
/* 0x000fe40007ffe0ff */
/*0c50*/ MOV R2, 0x8 ; /* 0x0000000800027802 */
/* 0x000fca0000000f00 */
/*0c60*/ IMAD.WIDE R2, R3, R2, c[0x0][0x170] ; /* 0x00005c0003027625 */
/* 0x000fca00078e0202 */
/*0c70*/ STG.E.64 [R2.64], R8 ; /* 0x0000000802007986 */
/* 0x002fe2000c101b04 */
/*0c80*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0c90*/ BRA 0xc90; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ca0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6matmulPdS_S_i
.globl _Z6matmulPdS_S_i
.p2align 8
.type _Z6matmulPdS_S_i,@function
_Z6matmulPdS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s3, 0xffff
s_lshr_b32 s3, s3, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v1, s2
s_mov_b32 s3, s2
v_mov_b32_e32 v6, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[4:5], 3, v[2:3]
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s4, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v7, 31, v6
s_add_i32 s3, s3, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_eq_u32 s3, 0
v_lshlrev_b64 v[7:8], 3, v[6:7]
v_add_nc_u32_e32 v6, s2, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v8, vcc_lo
global_load_b64 v[9:10], v[4:5], off
global_load_b64 v[7:8], v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 8
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fma_f64 v[2:3], v[9:10], v[7:8], v[2:3]
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
.LBB0_5:
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[4:5], null, v1, s2, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v5, 31, v4
v_lshlrev_b64 v[0:1], 3, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[2:3], off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matmulPdS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6matmulPdS_S_i, .Lfunc_end0-_Z6matmulPdS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matmulPdS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matmulPdS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000d43ab_00000000-6_matMulWrapperF2.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
.type _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i, @function
_Z30__device_stub__Z6matmulPdS_S_iPdS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matmulPdS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i, .-_Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
.globl _Z6matmulPdS_S_i
.type _Z6matmulPdS_S_i, @function
_Z6matmulPdS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z6matmulPdS_S_i, .-_Z6matmulPdS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " C Memory allocated \n"
.LC1:
.string " C Data sent to GPU \n"
.LC6:
.string " GridSize: %d\n"
.LC7:
.string " BlockSize: %d\n"
.LC8:
.string " C Kernel executed \n"
.LC9:
.string " C =============== \n"
.text
.globl matmul_wrapper
.type matmul_wrapper, @function
matmul_wrapper:
.LFB2057:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movl %edi, %ebp
movq %rsi, %r14
movq %rdx, %r13
movq %rcx, %r12
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl %edi, %ebx
imull %edi, %ebx
movslq %ebx, %rbx
salq $3, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r13, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
pxor %xmm0, %xmm0
cvtsi2sdl %ebp, %xmm0
mulsd .LC2(%rip), %xmm0
movapd %xmm0, %xmm3
movsd .LC10(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC3(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L12
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC5(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L12:
cvttsd2sil %xmm3, %edx
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $1, 40(%rsp)
movl %edx, 44(%rsp)
movl %edx, 48(%rsp)
movl $1, 52(%rsp)
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $32, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 40(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movq 44(%rsp), %rdi
movl 52(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L16
.L13:
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $2, %ecx
movq %rbx, %rdx
movq 24(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L17
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L16:
.cfi_restore_state
movl %ebp, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z6matmulPdS_S_iPdS_S_i
jmp .L13
.L17:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size matmul_wrapper, .-matmul_wrapper
.section .rodata.str1.1
.LC11:
.string "_Z6matmulPdS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matmulPdS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC2:
.long 0
.long 1067450368
.align 8
.LC3:
.long 0
.long 1127219200
.align 8
.LC5:
.long 0
.long 1072693248
.align 8
.LC10:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matMulWrapperF2.hip"
.globl _Z21__device_stub__matmulPdS_S_i # -- Begin function _Z21__device_stub__matmulPdS_S_i
.p2align 4, 0x90
.type _Z21__device_stub__matmulPdS_S_i,@function
_Z21__device_stub__matmulPdS_S_i: # @_Z21__device_stub__matmulPdS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matmulPdS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__matmulPdS_S_i, .Lfunc_end0-_Z21__device_stub__matmulPdS_S_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function matmul_wrapper
.LCPI1_0:
.quad 0x3fa0000000000000 # double 0.03125
.text
.globl matmul_wrapper
.p2align 4, 0x90
.type matmul_wrapper,@function
matmul_wrapper: # @matmul_wrapper
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rcx, %rbx
movq %rdx, %r15
movq %rsi, %r12
movl %edi, %ebp
movl %edi, %r14d
imull %r14d, %r14d
shlq $3, %r14
leaq 24(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 16(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
leaq 8(%rsp), %rdi
movq %r14, %rsi
callq hipMalloc
movl $.Lstr, %edi
callq puts@PLT
movq 24(%rsp), %rdi
movq %r12, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movq %r15, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
movl $.Lstr.1, %edi
callq puts@PLT
cvtsi2sd %ebp, %xmm0
mulsd .LCPI1_0(%rip), %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %esi
movq %rsi, %r15
shlq $32, %r15
orq %rsi, %r15
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
callq printf
movl $.L.str.3, %edi
movl $32, %esi
xorl %eax, %eax
callq printf
movabsq $137438953504, %rdx # imm = 0x2000000020
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl %ebp, 36(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z6matmulPdS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
movl $.Lstr.2, %edi
callq puts@PLT
movq 8(%rsp), %rsi
movq %rbx, %rdi
movq %r14, %rdx
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $.Lstr.3, %edi
callq puts@PLT
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size matmul_wrapper, .Lfunc_end1-matmul_wrapper
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matmulPdS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6matmulPdS_S_i,@object # @_Z6matmulPdS_S_i
.section .rodata,"a",@progbits
.globl _Z6matmulPdS_S_i
.p2align 3, 0x0
_Z6matmulPdS_S_i:
.quad _Z21__device_stub__matmulPdS_S_i
.size _Z6matmulPdS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz " GridSize: %d\n"
.size .L.str.2, 17
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " BlockSize: %d\n"
.size .L.str.3, 18
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6matmulPdS_S_i"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz " C Memory allocated "
.size .Lstr, 21
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz " C Data sent to GPU "
.size .Lstr.1, 21
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz " C Kernel executed "
.size .Lstr.2, 20
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz " C =============== "
.size .Lstr.3, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__matmulPdS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6matmulPdS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void rectified_linear_backprop_upd_kernel( float4 * __restrict input_errors, const float4 * __restrict output_errors, const uint4 * __restrict bits_buffer, float negative_slope, bool add_update_to_destination, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = output_errors[elem_id];
uint4 bits = bits_buffer[elem_id >> 5];
int lane_id = elem_id & 31;
unsigned int mask = (1 << lane_id);
if ((bits.x & mask) == 0)
val.x *= negative_slope;
if ((bits.y & mask) == 0)
val.y *= negative_slope;
if ((bits.z & mask) == 0)
val.z *= negative_slope;
if ((bits.w & mask) == 0)
val.w *= negative_slope;
if (add_update_to_destination)
{
float4 prv = input_errors[elem_id];
val.x += prv.x;
val.y += prv.y;
val.z += prv.z;
val.w += prv.w;
}
input_errors[elem_id] = val;
}
} | code for sm_80
Function : _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R17, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff117435 */
/* 0x000fe200000001ff */
/*0070*/ SHF.R.S32.HI R4, RZ, 0x5, R0 ; /* 0x00000005ff047819 */
/* 0x000fe20000011400 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ULDC.S8 UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fcc0000000200 */
/*00a0*/ IMAD.WIDE R4, R4, R17, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0211 */
/*00b0*/ ISETP.NE.AND P4, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fca000bf85270 */
/*00c0*/ LDG.E.128.CONSTANT R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e9d00 */
/*00d0*/ IMAD.WIDE R2, R0, R17, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0211 */
/*00e0*/ IMAD.WIDE R16, R0, R17, c[0x0][0x160] ; /* 0x0000580000107625 */
/* 0x000fe200078e0211 */
/*00f0*/ LDG.E.128.CONSTANT R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ee8000c1e9d00 */
/*0100*/ @P4 LDG.E.128 R12, [R16.64] ; /* 0x00000006100c4981 */
/* 0x000f22000c1e1d00 */
/*0110*/ HFMA2.MMA R19, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff137435 */
/* 0x000fd400000001ff */
/*0120*/ SHF.L.W.U32 R0, R19, R0, RZ ; /* 0x0000000013007219 */
/* 0x000fc80000000eff */
/*0130*/ LOP3.LUT P0, RZ, R4, R0.reuse, RZ, 0xc0, !PT ; /* 0x0000000004ff7212 */
/* 0x084fe4000780c0ff */
/*0140*/ LOP3.LUT P1, RZ, R5, R0.reuse, RZ, 0xc0, !PT ; /* 0x0000000005ff7212 */
/* 0x080fe4000782c0ff */
/*0150*/ LOP3.LUT P2, RZ, R6, R0.reuse, RZ, 0xc0, !PT ; /* 0x0000000006ff7212 */
/* 0x080fe4000784c0ff */
/*0160*/ LOP3.LUT P3, RZ, R7, R0, RZ, 0xc0, !PT ; /* 0x0000000007ff7212 */
/* 0x000fce000786c0ff */
/*0170*/ @!P0 FMUL R8, R8, c[0x0][0x178] ; /* 0x00005e0008088a20 */
/* 0x008fe40000400000 */
/*0180*/ @!P1 FMUL R9, R9, c[0x0][0x178] ; /* 0x00005e0009099a20 */
/* 0x000fe40000400000 */
/*0190*/ @!P2 FMUL R10, R10, c[0x0][0x178] ; /* 0x00005e000a0aaa20 */
/* 0x000fe40000400000 */
/*01a0*/ @!P3 FMUL R11, R11, c[0x0][0x178] ; /* 0x00005e000b0bba20 */
/* 0x000fe40000400000 */
/*01b0*/ @P4 FADD R8, R8, R12 ; /* 0x0000000c08084221 */
/* 0x010fe40000000000 */
/*01c0*/ @P4 FADD R9, R9, R13 ; /* 0x0000000d09094221 */
/* 0x000fc40000000000 */
/*01d0*/ @P4 FADD R10, R10, R14 ; /* 0x0000000e0a0a4221 */
/* 0x000fe40000000000 */
/*01e0*/ @P4 FADD R11, R11, R15 ; /* 0x0000000f0b0b4221 */
/* 0x000fca0000000000 */
/*01f0*/ STG.E.128 [R16.64], R8 ; /* 0x0000000810007986 */
/* 0x000fe2000c101d06 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void rectified_linear_backprop_upd_kernel( float4 * __restrict input_errors, const float4 * __restrict output_errors, const uint4 * __restrict bits_buffer, float negative_slope, bool add_update_to_destination, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = output_errors[elem_id];
uint4 bits = bits_buffer[elem_id >> 5];
int lane_id = elem_id & 31;
unsigned int mask = (1 << lane_id);
if ((bits.x & mask) == 0)
val.x *= negative_slope;
if ((bits.y & mask) == 0)
val.y *= negative_slope;
if ((bits.z & mask) == 0)
val.z *= negative_slope;
if ((bits.w & mask) == 0)
val.w *= negative_slope;
if (add_update_to_destination)
{
float4 prv = input_errors[elem_id];
val.x += prv.x;
val.y += prv.y;
val.z += prv.z;
val.w += prv.w;
}
input_errors[elem_id] = val;
}
} | .file "tmpxft_0006842f_00000000-6_rectified_linear_backprop_upd_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi
.type _Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi, @function
_Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 12(%rsp)
movl %r8d, 4(%rsp)
movb %cl, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi, .-_Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi
.globl _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi
.type _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi, @function
_Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %cl, %ecx
call _Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi, .-_Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void rectified_linear_backprop_upd_kernel( float4 * __restrict input_errors, const float4 * __restrict output_errors, const uint4 * __restrict bits_buffer, float negative_slope, bool add_update_to_destination, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = output_errors[elem_id];
uint4 bits = bits_buffer[elem_id >> 5];
int lane_id = elem_id & 31;
unsigned int mask = (1 << lane_id);
if ((bits.x & mask) == 0)
val.x *= negative_slope;
if ((bits.y & mask) == 0)
val.y *= negative_slope;
if ((bits.z & mask) == 0)
val.z *= negative_slope;
if ((bits.w & mask) == 0)
val.w *= negative_slope;
if (add_update_to_destination)
{
float4 prv = input_errors[elem_id];
val.x += prv.x;
val.y += prv.y;
val.z += prv.z;
val.w += prv.w;
}
input_errors[elem_id] = val;
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rectified_linear_backprop_upd_kernel( float4 * __restrict input_errors, const float4 * __restrict output_errors, const uint4 * __restrict bits_buffer, float negative_slope, bool add_update_to_destination, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = output_errors[elem_id];
uint4 bits = bits_buffer[elem_id >> 5];
int lane_id = elem_id & 31;
unsigned int mask = (1 << lane_id);
if ((bits.x & mask) == 0)
val.x *= negative_slope;
if ((bits.y & mask) == 0)
val.y *= negative_slope;
if ((bits.z & mask) == 0)
val.z *= negative_slope;
if ((bits.w & mask) == 0)
val.w *= negative_slope;
if (add_update_to_destination)
{
float4 prv = input_errors[elem_id];
val.x += prv.x;
val.y += prv.y;
val.z += prv.z;
val.w += prv.w;
}
input_errors[elem_id] = val;
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rectified_linear_backprop_upd_kernel( float4 * __restrict input_errors, const float4 * __restrict output_errors, const uint4 * __restrict bits_buffer, float negative_slope, bool add_update_to_destination, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = output_errors[elem_id];
uint4 bits = bits_buffer[elem_id >> 5];
int lane_id = elem_id & 31;
unsigned int mask = (1 << lane_id);
if ((bits.x & mask) == 0)
val.x *= negative_slope;
if ((bits.y & mask) == 0)
val.y *= negative_slope;
if ((bits.z & mask) == 0)
val.z *= negative_slope;
if ((bits.w & mask) == 0)
val.w *= negative_slope;
if (add_update_to_destination)
{
float4 prv = input_errors[elem_id];
val.x += prv.x;
val.y += prv.y;
val.z += prv.z;
val.w += prv.w;
}
input_errors[elem_id] = val;
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.globl _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.p2align 8
.type _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi,@function
_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 5, v1
v_lshlrev_b32_e64 v0, v1, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 4, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_bitcmp0_b32 s7, 0
global_load_b128 v[6:9], v[4:5], off
v_lshlrev_b64 v[4:5], 4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
global_load_b128 v[10:13], v[2:3], off
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v6, v0
v_and_b32_e32 v2, v7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e64 v1, 1.0, s6, vcc_lo
v_and_b32_e32 v3, v8, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 1.0, s6, vcc_lo
v_and_b32_e32 v0, v9, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
v_cndmask_b32_e64 v3, 1.0, s6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_waitcnt vmcnt(0)
v_dual_mul_f32 v0, v10, v1 :: v_dual_mul_f32 v1, v11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v12, v3
v_cndmask_b32_e64 v6, 1.0, s6, vcc_lo
v_mul_f32_e32 v3, v13, v6
s_cbranch_scc1 .LBB0_3
v_add_co_u32 v6, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
global_load_b128 v[6:9], v[6:7], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v6 :: v_dual_add_f32 v1, v1, v7
v_dual_add_f32 v2, v2, v8 :: v_dual_add_f32 v3, v3, v9
.LBB0_3:
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_store_b128 v[4:5], v[0:3], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi, .Lfunc_end0-_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 1
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void rectified_linear_backprop_upd_kernel( float4 * __restrict input_errors, const float4 * __restrict output_errors, const uint4 * __restrict bits_buffer, float negative_slope, bool add_update_to_destination, int elem_count)
{
int elem_id = blockDim.x * blockIdx.x + threadIdx.x;
if (elem_id < elem_count)
{
float4 val = output_errors[elem_id];
uint4 bits = bits_buffer[elem_id >> 5];
int lane_id = elem_id & 31;
unsigned int mask = (1 << lane_id);
if ((bits.x & mask) == 0)
val.x *= negative_slope;
if ((bits.y & mask) == 0)
val.y *= negative_slope;
if ((bits.z & mask) == 0)
val.z *= negative_slope;
if ((bits.w & mask) == 0)
val.w *= negative_slope;
if (add_update_to_destination)
{
float4 prv = input_errors[elem_id];
val.x += prv.x;
val.y += prv.y;
val.z += prv.z;
val.w += prv.w;
}
input_errors[elem_id] = val;
}
} | .text
.file "rectified_linear_backprop_upd_kernel.hip"
.globl _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi # -- Begin function _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.p2align 4, 0x90
.type _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi,@function
_Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi: # @_Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movb %cl, 15(%rsp)
movl %r8d, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 15(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi, .Lfunc_end0-_Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi,@object # @_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.section .rodata,"a",@progbits
.globl _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.p2align 3, 0x0
_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi:
.quad _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.size _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi"
.size .L__unnamed_1, 85
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ HFMA2.MMA R17, -RZ, RZ, 0, 9.5367431640625e-07 ; /* 0x00000010ff117435 */
/* 0x000fe200000001ff */
/*0070*/ SHF.R.S32.HI R4, RZ, 0x5, R0 ; /* 0x00000005ff047819 */
/* 0x000fe20000011400 */
/*0080*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0090*/ ULDC.S8 UR4, c[0x0][0x17c] ; /* 0x00005f0000047ab9 */
/* 0x000fcc0000000200 */
/*00a0*/ IMAD.WIDE R4, R4, R17, c[0x0][0x170] ; /* 0x00005c0004047625 */
/* 0x000fe200078e0211 */
/*00b0*/ ISETP.NE.AND P4, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fca000bf85270 */
/*00c0*/ LDG.E.128.CONSTANT R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea2000c1e9d00 */
/*00d0*/ IMAD.WIDE R2, R0, R17, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fc800078e0211 */
/*00e0*/ IMAD.WIDE R16, R0, R17, c[0x0][0x160] ; /* 0x0000580000107625 */
/* 0x000fe200078e0211 */
/*00f0*/ LDG.E.128.CONSTANT R8, [R2.64] ; /* 0x0000000602087981 */
/* 0x000ee8000c1e9d00 */
/*0100*/ @P4 LDG.E.128 R12, [R16.64] ; /* 0x00000006100c4981 */
/* 0x000f22000c1e1d00 */
/*0110*/ HFMA2.MMA R19, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff137435 */
/* 0x000fd400000001ff */
/*0120*/ SHF.L.W.U32 R0, R19, R0, RZ ; /* 0x0000000013007219 */
/* 0x000fc80000000eff */
/*0130*/ LOP3.LUT P0, RZ, R4, R0.reuse, RZ, 0xc0, !PT ; /* 0x0000000004ff7212 */
/* 0x084fe4000780c0ff */
/*0140*/ LOP3.LUT P1, RZ, R5, R0.reuse, RZ, 0xc0, !PT ; /* 0x0000000005ff7212 */
/* 0x080fe4000782c0ff */
/*0150*/ LOP3.LUT P2, RZ, R6, R0.reuse, RZ, 0xc0, !PT ; /* 0x0000000006ff7212 */
/* 0x080fe4000784c0ff */
/*0160*/ LOP3.LUT P3, RZ, R7, R0, RZ, 0xc0, !PT ; /* 0x0000000007ff7212 */
/* 0x000fce000786c0ff */
/*0170*/ @!P0 FMUL R8, R8, c[0x0][0x178] ; /* 0x00005e0008088a20 */
/* 0x008fe40000400000 */
/*0180*/ @!P1 FMUL R9, R9, c[0x0][0x178] ; /* 0x00005e0009099a20 */
/* 0x000fe40000400000 */
/*0190*/ @!P2 FMUL R10, R10, c[0x0][0x178] ; /* 0x00005e000a0aaa20 */
/* 0x000fe40000400000 */
/*01a0*/ @!P3 FMUL R11, R11, c[0x0][0x178] ; /* 0x00005e000b0bba20 */
/* 0x000fe40000400000 */
/*01b0*/ @P4 FADD R8, R8, R12 ; /* 0x0000000c08084221 */
/* 0x010fe40000000000 */
/*01c0*/ @P4 FADD R9, R9, R13 ; /* 0x0000000d09094221 */
/* 0x000fc40000000000 */
/*01d0*/ @P4 FADD R10, R10, R14 ; /* 0x0000000e0a0a4221 */
/* 0x000fe40000000000 */
/*01e0*/ @P4 FADD R11, R11, R15 ; /* 0x0000000f0b0b4221 */
/* 0x000fca0000000000 */
/*01f0*/ STG.E.128 [R16.64], R8 ; /* 0x0000000810007986 */
/* 0x000fe2000c101d06 */
/*0200*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0210*/ BRA 0x210; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0280*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0290*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*02f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.globl _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.p2align 8
.type _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi,@function
_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x34
s_load_b32 s3, s[0:1], 0x20
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_4
s_load_b256 s[0:7], s[0:1], 0x0
v_ashrrev_i32_e32 v2, 5, v1
v_lshlrev_b32_e64 v0, v1, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 4, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
v_ashrrev_i32_e32 v2, 31, v1
s_bitcmp0_b32 s7, 0
global_load_b128 v[6:9], v[4:5], off
v_lshlrev_b64 v[4:5], 4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s2, v4
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v5, vcc_lo
global_load_b128 v[10:13], v[2:3], off
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v6, v0
v_and_b32_e32 v2, v7, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_eq_u32_e32 vcc_lo, 0, v1
v_cndmask_b32_e64 v1, 1.0, s6, vcc_lo
v_and_b32_e32 v3, v8, v0
v_cmp_eq_u32_e32 vcc_lo, 0, v2
v_cndmask_b32_e64 v2, 1.0, s6, vcc_lo
v_and_b32_e32 v0, v9, v0
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cmp_eq_u32_e32 vcc_lo, 0, v3
v_cndmask_b32_e64 v3, 1.0, s6, vcc_lo
v_cmp_eq_u32_e32 vcc_lo, 0, v0
s_waitcnt vmcnt(0)
v_dual_mul_f32 v0, v10, v1 :: v_dual_mul_f32 v1, v11, v2
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f32_e32 v2, v12, v3
v_cndmask_b32_e64 v6, 1.0, s6, vcc_lo
v_mul_f32_e32 v3, v13, v6
s_cbranch_scc1 .LBB0_3
v_add_co_u32 v6, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
global_load_b128 v[6:9], v[6:7], off
s_waitcnt vmcnt(0)
v_dual_add_f32 v0, v0, v6 :: v_dual_add_f32 v1, v1, v7
v_dual_add_f32 v2, v2, v8 :: v_dual_add_f32 v3, v3, v9
.LBB0_3:
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_store_b128 v[4:5], v[0:3], off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 14
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi, .Lfunc_end0-_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .actual_access: read_only
.address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 1
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 14
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006842f_00000000-6_rectified_linear_backprop_upd_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi
.type _Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi, @function
_Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi:
.LFB2051:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movss %xmm0, 12(%rsp)
movl %r8d, 4(%rsp)
movb %cl, 8(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
movq %rdx, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 8(%rsp), %rax
movq %rax, 144(%rsp)
leaq 4(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi, .-_Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi
.globl _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi
.type _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi, @function
_Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl %cl, %ecx
call _Z77__device_stub__Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbiP6float4PKS_PK5uint4fbi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi, .-_Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z36rectified_linear_backprop_upd_kernelP6float4PKS_PK5uint4fbi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "rectified_linear_backprop_upd_kernel.hip"
.globl _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi # -- Begin function _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.p2align 4, 0x90
.type _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi,@function
_Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi: # @_Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movss %xmm0, 20(%rsp)
movb %cl, 15(%rsp)
movl %r8d, 16(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 15(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi, .Lfunc_end0-_Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi,@object # @_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.section .rodata,"a",@progbits
.globl _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.p2align 3, 0x0
_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi:
.quad _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.size _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi"
.size .L__unnamed_1, 85
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z51__device_stub__rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z36rectified_linear_backprop_upd_kernelP15HIP_vector_typeIfLj4EEPKS0_PKS_IjLj4EEfbi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cmath>
#include <unistd.h>
#include <iostream>
#include <cuda_runtime_api.h>
#define N 257
using namespace std;
// Assumes that the block and grid sizes divide the width of array
// Doesn't to bounds checking
// Potential trouble!
// Use with: dim3 block(32, 32); dim3 grid(8, 8);
__global__ void matcpyBad(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
out[x + y * width] = in[x + y * width];
}
// Use with: dim3 block(32, 32); dim3 grid(8, 2);
__global__ void matcpyBadWithLoop(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
out[idx] = in[idx];
}
}
// Works with different blocks sizes
__global__ void matcpy(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int idx = x + y * blockDim.x * gridDim.x;
if (idx < size) {
out[idx] = in[idx];
}
}
__global__ void matcpyWithLoop(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
if (idx < size) {
out[idx] = in[idx];
}
}
}
int main() {
size_t size = N * N * sizeof(float);
dim3 block(32, 32);
dim3 grid((N - 1) / block.x + 1, (N - 1) / (4 * block.y) + 1);
float in[N * N];
float out[N * N] = {0.0f};
for (int i = 0; i < N * N; i++) {
in[i] = i;
}
float *dIn;
float *dOut;
cudaMalloc((void **)&dIn, size);
cudaMalloc((void **)&dOut, size);
cudaMemcpy(dIn, in, size, cudaMemcpyHostToDevice);
matcpyWithLoop<<<grid, block>>>(dIn, N * N, dOut);
cudaMemcpy(out, dOut, size, cudaMemcpyDeviceToHost);
bool areEqual = true;
for (int i = 0; i < N * N; i++) {
areEqual &= abs(in[i] - out[i]) < 0.00001;
}
if (areEqual) {
cout << "copy successful" << endl;
} else {
cout << "copy failed" << endl;
}
// usleep(1000000);
return 0;
} | code for sm_80
Function : _Z14matcpyWithLoopPKfiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ULDC UR4, c[0x0][0x4] ; /* 0x0000010000047ab9 */
/* 0x000fe40000000800 */
/*0020*/ ULDC UR5, c[0x0][0x10] ; /* 0x0000040000057ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc8000f8e023f */
/*0040*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fcc000800063f */
/*0050*/ ISETP.NE.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fda000bf05270 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*00b0*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*00c0*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000ea20000002100 */
/*00d0*/ IMAD R0, R3, c[0x0][0x4], R0 ; /* 0x0000010003007a24 */
/* 0x001fca00078e0200 */
/*00e0*/ IADD3 R2, R0, R7, RZ ; /* 0x0000000700027210 */
/* 0x000fe20007ffe0ff */
/*00f0*/ BSSY B0, 0x1c0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0100*/ IADD3 R7, R7, UR4, RZ ; /* 0x0000000407077c10 */
/* 0x000fc6000fffe0ff */
/*0110*/ IMAD R2, R2, c[0x0][0xc], R9 ; /* 0x0000030002027a24 */
/* 0x002fe200078e0209 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R7, UR5, PT ; /* 0x0000000507007c0c */
/* 0x000fc6000bf26070 */
/*0130*/ IMAD R5, R2, c[0x0][0x0], R11 ; /* 0x0000000002057a24 */
/* 0x005fca00078e020b */
/*0140*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*0150*/ @P0 BRA 0x1b0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0160*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fd400000001ff */
/*0170*/ IMAD.WIDE R2, R5, R4, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0204 */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0190*/ IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fca00078e0204 */
/*01a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041e4000c101906 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ @!P1 BRA 0xe0 ; /* 0xffffff1000009947 */
/* 0x000fea000383ffff */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6matcpyPKfiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R7 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0207 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0205 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17matcpyBadWithLoopPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ULDC UR4, c[0x0][0x4] ; /* 0x0000010000047ab9 */
/* 0x000fe40000000800 */
/*0020*/ ULDC UR5, c[0x0][0x10] ; /* 0x0000040000057ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc8000f8e023f */
/*0040*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fcc000800063f */
/*0050*/ ISETP.NE.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fda000bf05270 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*00b0*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*00c0*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000ea20000002100 */
/*00d0*/ IMAD R0, R3, c[0x0][0x4], R0 ; /* 0x0000010003007a24 */
/* 0x001fca00078e0200 */
/*00e0*/ IADD3 R2, R0, R7, RZ ; /* 0x0000000700027210 */
/* 0x000fe40007ffe0ff */
/*00f0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x001fc60000000f00 */
/*0100*/ IMAD R2, R2, c[0x0][0xc], R9 ; /* 0x0000030002027a24 */
/* 0x002fc800078e0209 */
/*0110*/ IMAD R4, R2, c[0x0][0x0], R11 ; /* 0x0000000002047a24 */
/* 0x004fc800078e020b */
/*0120*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R7, R7, UR4, RZ ; /* 0x0000000407077c10 */
/* 0x000fe2000fffe0ff */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0205 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R7, UR5, PT ; /* 0x0000000507007c0c */
/* 0x000fe4000bf06070 */
/*0170*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041f6000c101906 */
/*0180*/ @!P0 BRA 0xe0 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9matcpyBadPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fce00078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cmath>
#include <unistd.h>
#include <iostream>
#include <cuda_runtime_api.h>
#define N 257
using namespace std;
// Assumes that the block and grid sizes divide the width of array
// Doesn't to bounds checking
// Potential trouble!
// Use with: dim3 block(32, 32); dim3 grid(8, 8);
__global__ void matcpyBad(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
out[x + y * width] = in[x + y * width];
}
// Use with: dim3 block(32, 32); dim3 grid(8, 2);
__global__ void matcpyBadWithLoop(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
out[idx] = in[idx];
}
}
// Works with different blocks sizes
__global__ void matcpy(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int idx = x + y * blockDim.x * gridDim.x;
if (idx < size) {
out[idx] = in[idx];
}
}
__global__ void matcpyWithLoop(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
if (idx < size) {
out[idx] = in[idx];
}
}
}
int main() {
size_t size = N * N * sizeof(float);
dim3 block(32, 32);
dim3 grid((N - 1) / block.x + 1, (N - 1) / (4 * block.y) + 1);
float in[N * N];
float out[N * N] = {0.0f};
for (int i = 0; i < N * N; i++) {
in[i] = i;
}
float *dIn;
float *dOut;
cudaMalloc((void **)&dIn, size);
cudaMalloc((void **)&dOut, size);
cudaMemcpy(dIn, in, size, cudaMemcpyHostToDevice);
matcpyWithLoop<<<grid, block>>>(dIn, N * N, dOut);
cudaMemcpy(out, dOut, size, cudaMemcpyDeviceToHost);
bool areEqual = true;
for (int i = 0; i < N * N; i++) {
areEqual &= abs(in[i] - out[i]) < 0.00001;
}
if (areEqual) {
cout << "copy successful" << endl;
} else {
cout << "copy failed" << endl;
}
// usleep(1000000);
return 0;
} | .file "tmpxft_0000ab26_00000000-6_matcpy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3685:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3685:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9matcpyBadPKfPfPKfPf
.type _Z31__device_stub__Z9matcpyBadPKfPfPKfPf, @function
_Z31__device_stub__Z9matcpyBadPKfPfPKfPf:
.LFB3707:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9matcpyBadPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3707:
.size _Z31__device_stub__Z9matcpyBadPKfPfPKfPf, .-_Z31__device_stub__Z9matcpyBadPKfPfPKfPf
.globl _Z9matcpyBadPKfPf
.type _Z9matcpyBadPKfPf, @function
_Z9matcpyBadPKfPf:
.LFB3708:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9matcpyBadPKfPfPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _Z9matcpyBadPKfPf, .-_Z9matcpyBadPKfPf
.globl _Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf
.type _Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf, @function
_Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf:
.LFB3709:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17matcpyBadWithLoopPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3709:
.size _Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf, .-_Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf
.globl _Z17matcpyBadWithLoopPKfPf
.type _Z17matcpyBadWithLoopPKfPf, @function
_Z17matcpyBadWithLoopPKfPf:
.LFB3710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3710:
.size _Z17matcpyBadWithLoopPKfPf, .-_Z17matcpyBadWithLoopPKfPf
.globl _Z29__device_stub__Z6matcpyPKfiPfPKfiPf
.type _Z29__device_stub__Z6matcpyPKfiPfPKfiPf, @function
_Z29__device_stub__Z6matcpyPKfiPfPKfiPf:
.LFB3711:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matcpyPKfiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3711:
.size _Z29__device_stub__Z6matcpyPKfiPfPKfiPf, .-_Z29__device_stub__Z6matcpyPKfiPfPKfiPf
.globl _Z6matcpyPKfiPf
.type _Z6matcpyPKfiPf, @function
_Z6matcpyPKfiPf:
.LFB3712:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6matcpyPKfiPfPKfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3712:
.size _Z6matcpyPKfiPf, .-_Z6matcpyPKfiPf
.globl _Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf
.type _Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf, @function
_Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf:
.LFB3713:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matcpyWithLoopPKfiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3713:
.size _Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf, .-_Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf
.globl _Z14matcpyWithLoopPKfiPf
.type _Z14matcpyWithLoopPKfiPf, @function
_Z14matcpyWithLoopPKfiPf:
.LFB3714:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3714:
.size _Z14matcpyWithLoopPKfiPf, .-_Z14matcpyWithLoopPKfiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "copy successful"
.LC3:
.string "copy failed"
.text
.globl main
.type main, @function
main:
.LFB3682:
.cfi_startproc
endbr64
leaq -528384(%rsp), %r11
.cfi_def_cfa 11, 528392
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 528480
movq %fs:40, %rax
movq %rax, 528456(%rsp)
xorl %eax, %eax
movl $1, 32(%rsp)
movl $9, 36(%rsp)
movl $3, 40(%rsp)
movl $1, 44(%rsp)
leaq 264256(%rsp), %rdi
movl $264196, %edx
movl $0, %esi
call memset@PLT
movl $0, %eax
.L36:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $66049, %rax
jne .L36
leaq 8(%rsp), %rdi
movl $264196, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $264196, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $264196, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 24(%rsp)
movl $32, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L37:
leaq 264256(%rsp), %rdi
movl $2, %ecx
movl $264196, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %eax
movl $1, %edx
leaq 264256(%rsp), %rsi
movss .LC0(%rip), %xmm2
movsd .LC1(%rip), %xmm1
.L38:
movss 48(%rsp,%rax), %xmm0
subss (%rax,%rsi), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm0, %xmm1
seta %cl
andl %ecx, %edx
addq $4, %rax
cmpq $264196, %rax
jne .L38
testb %dl, %dl
je .L39
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L40:
movq 528456(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $528472, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq 16(%rsp), %rdx
movl $66049, %esi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf
jmp .L37
.L39:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L40
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3682:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14matcpyWithLoopPKfiPf"
.LC5:
.string "_Z6matcpyPKfiPf"
.LC6:
.string "_Z17matcpyBadWithLoopPKfPf"
.LC7:
.string "_Z9matcpyBadPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3716:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matcpyWithLoopPKfiPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matcpyPKfiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matcpyBadWithLoopPKfPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matcpyBadPKfPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3716:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cmath>
#include <unistd.h>
#include <iostream>
#include <cuda_runtime_api.h>
#define N 257
using namespace std;
// Assumes that the block and grid sizes divide the width of array
// Doesn't to bounds checking
// Potential trouble!
// Use with: dim3 block(32, 32); dim3 grid(8, 8);
__global__ void matcpyBad(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
out[x + y * width] = in[x + y * width];
}
// Use with: dim3 block(32, 32); dim3 grid(8, 2);
__global__ void matcpyBadWithLoop(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
out[idx] = in[idx];
}
}
// Works with different blocks sizes
__global__ void matcpy(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int idx = x + y * blockDim.x * gridDim.x;
if (idx < size) {
out[idx] = in[idx];
}
}
__global__ void matcpyWithLoop(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
if (idx < size) {
out[idx] = in[idx];
}
}
}
int main() {
size_t size = N * N * sizeof(float);
dim3 block(32, 32);
dim3 grid((N - 1) / block.x + 1, (N - 1) / (4 * block.y) + 1);
float in[N * N];
float out[N * N] = {0.0f};
for (int i = 0; i < N * N; i++) {
in[i] = i;
}
float *dIn;
float *dOut;
cudaMalloc((void **)&dIn, size);
cudaMalloc((void **)&dOut, size);
cudaMemcpy(dIn, in, size, cudaMemcpyHostToDevice);
matcpyWithLoop<<<grid, block>>>(dIn, N * N, dOut);
cudaMemcpy(out, dOut, size, cudaMemcpyDeviceToHost);
bool areEqual = true;
for (int i = 0; i < N * N; i++) {
areEqual &= abs(in[i] - out[i]) < 0.00001;
}
if (areEqual) {
cout << "copy successful" << endl;
} else {
cout << "copy failed" << endl;
}
// usleep(1000000);
return 0;
} | #include <hip/hip_runtime.h>
#include <cmath>
#include <unistd.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
#define N 257
using namespace std;
// Assumes that the block and grid sizes divide the width of array
// Doesn't to bounds checking
// Potential trouble!
// Use with: dim3 block(32, 32); dim3 grid(8, 8);
__global__ void matcpyBad(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
out[x + y * width] = in[x + y * width];
}
// Use with: dim3 block(32, 32); dim3 grid(8, 2);
__global__ void matcpyBadWithLoop(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
out[idx] = in[idx];
}
}
// Works with different blocks sizes
__global__ void matcpy(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int idx = x + y * blockDim.x * gridDim.x;
if (idx < size) {
out[idx] = in[idx];
}
}
__global__ void matcpyWithLoop(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
if (idx < size) {
out[idx] = in[idx];
}
}
}
int main() {
size_t size = N * N * sizeof(float);
dim3 block(32, 32);
dim3 grid((N - 1) / block.x + 1, (N - 1) / (4 * block.y) + 1);
float in[N * N];
float out[N * N] = {0.0f};
for (int i = 0; i < N * N; i++) {
in[i] = i;
}
float *dIn;
float *dOut;
hipMalloc((void **)&dIn, size);
hipMalloc((void **)&dOut, size);
hipMemcpy(dIn, in, size, hipMemcpyHostToDevice);
matcpyWithLoop<<<grid, block>>>(dIn, N * N, dOut);
hipMemcpy(out, dOut, size, hipMemcpyDeviceToHost);
bool areEqual = true;
for (int i = 0; i < N * N; i++) {
areEqual &= abs(in[i] - out[i]) < 0.00001;
}
if (areEqual) {
cout << "copy successful" << endl;
} else {
cout << "copy failed" << endl;
}
// usleep(1000000);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <unistd.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
#define N 257
using namespace std;
// Assumes that the block and grid sizes divide the width of array
// Doesn't to bounds checking
// Potential trouble!
// Use with: dim3 block(32, 32); dim3 grid(8, 8);
__global__ void matcpyBad(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
out[x + y * width] = in[x + y * width];
}
// Use with: dim3 block(32, 32); dim3 grid(8, 2);
__global__ void matcpyBadWithLoop(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
out[idx] = in[idx];
}
}
// Works with different blocks sizes
__global__ void matcpy(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int idx = x + y * blockDim.x * gridDim.x;
if (idx < size) {
out[idx] = in[idx];
}
}
__global__ void matcpyWithLoop(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
if (idx < size) {
out[idx] = in[idx];
}
}
}
int main() {
size_t size = N * N * sizeof(float);
dim3 block(32, 32);
dim3 grid((N - 1) / block.x + 1, (N - 1) / (4 * block.y) + 1);
float in[N * N];
float out[N * N] = {0.0f};
for (int i = 0; i < N * N; i++) {
in[i] = i;
}
float *dIn;
float *dOut;
hipMalloc((void **)&dIn, size);
hipMalloc((void **)&dOut, size);
hipMemcpy(dIn, in, size, hipMemcpyHostToDevice);
matcpyWithLoop<<<grid, block>>>(dIn, N * N, dOut);
hipMemcpy(out, dOut, size, hipMemcpyDeviceToHost);
bool areEqual = true;
for (int i = 0; i < N * N; i++) {
areEqual &= abs(in[i] - out[i]) < 0.00001;
}
if (areEqual) {
cout << "copy successful" << endl;
} else {
cout << "copy failed" << endl;
}
// usleep(1000000);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matcpyBadPKfPf
.globl _Z9matcpyBadPKfPf
.p2align 8
.type _Z9matcpyBadPKfPf,@function
_Z9matcpyBadPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s2, s[14:15]
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matcpyBadPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matcpyBadPKfPf, .Lfunc_end0-_Z9matcpyBadPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17matcpyBadWithLoopPKfPf
.globl _Z17matcpyBadWithLoopPKfPf
.p2align 8
.type _Z17matcpyBadWithLoopPKfPf,@function
_Z17matcpyBadWithLoopPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x14
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s5, s7
s_lshl_b32 s5, s4, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB1_3
s_clause 0x1
s_load_b32 s8, s[2:3], 0x0
s_load_b32 s9, s[2:3], 0xc
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s7, v[1:2]
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s8, v2, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s7, s9, 0xffff
s_mul_i32 s8, s4, s8
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s7, v[2:3]
s_mul_i32 s7, s8, s7
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s6, s6, s4
s_cmp_ge_u32 s6, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s7, v0
v_add_co_u32 v3, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matcpyBadWithLoopPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17matcpyBadWithLoopPKfPf, .Lfunc_end1-_Z17matcpyBadWithLoopPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6matcpyPKfiPf
.globl _Z6matcpyPKfiPf
.p2align 8
.type _Z6matcpyPKfiPf,@function
_Z6matcpyPKfiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b32 s4, s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB2_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matcpyPKfiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6matcpyPKfiPf, .Lfunc_end2-_Z6matcpyPKfiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14matcpyWithLoopPKfiPf
.globl _Z14matcpyWithLoopPKfiPf
.p2align 8
.type _Z14matcpyWithLoopPKfiPf,@function
_Z14matcpyWithLoopPKfiPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x1c
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s5, s7
s_lshl_b32 s5, s4, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB3_5
s_clause 0x1
s_load_b32 s8, s[2:3], 0x0
s_load_b32 s9, s[2:3], 0xc
v_bfe_u32 v1, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s7, v[1:2]
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s8, v2, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s9, s9, 0xffff
s_mul_i32 s8, s4, s8
s_mul_i32 s8, s8, s9
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s9, v[2:3]
s_branch .LBB3_3
.p2align 6
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v0, s8, v0
s_add_i32 s6, s6, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s5
s_cbranch_scc1 .LBB3_5
.LBB3_3:
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s7, v0
s_cbranch_execz .LBB3_2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
s_branch .LBB3_2
.LBB3_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matcpyWithLoopPKfiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z14matcpyWithLoopPKfiPf, .Lfunc_end3-_Z14matcpyWithLoopPKfiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matcpyBadPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matcpyBadPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matcpyBadWithLoopPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matcpyBadWithLoopPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matcpyPKfiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matcpyPKfiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matcpyWithLoopPKfiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matcpyWithLoopPKfiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <cmath>
#include <unistd.h>
#include <iostream>
#include <hip/hip_runtime_api.h>
#define N 257
using namespace std;
// Assumes that the block and grid sizes divide the width of array
// Doesn't to bounds checking
// Potential trouble!
// Use with: dim3 block(32, 32); dim3 grid(8, 8);
__global__ void matcpyBad(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
out[x + y * width] = in[x + y * width];
}
// Use with: dim3 block(32, 32); dim3 grid(8, 2);
__global__ void matcpyBadWithLoop(const float *in, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
out[idx] = in[idx];
}
}
// Works with different blocks sizes
__global__ void matcpy(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int idx = x + y * blockDim.x * gridDim.x;
if (idx < size) {
out[idx] = in[idx];
}
}
__global__ void matcpyWithLoop(const float *in, int size, float *out) {
int x = threadIdx.x + blockIdx.x * blockDim.x;
int y = threadIdx.y + blockIdx.y * blockDim.y;
int width = blockDim.x * gridDim.x;
for (int j = 0; j < 4 * blockDim.y * gridDim.y; j += blockDim.y * gridDim.y) {
int idx = (y + j) * width + x;
if (idx < size) {
out[idx] = in[idx];
}
}
}
int main() {
size_t size = N * N * sizeof(float);
dim3 block(32, 32);
dim3 grid((N - 1) / block.x + 1, (N - 1) / (4 * block.y) + 1);
float in[N * N];
float out[N * N] = {0.0f};
for (int i = 0; i < N * N; i++) {
in[i] = i;
}
float *dIn;
float *dOut;
hipMalloc((void **)&dIn, size);
hipMalloc((void **)&dOut, size);
hipMemcpy(dIn, in, size, hipMemcpyHostToDevice);
matcpyWithLoop<<<grid, block>>>(dIn, N * N, dOut);
hipMemcpy(out, dOut, size, hipMemcpyDeviceToHost);
bool areEqual = true;
for (int i = 0; i < N * N; i++) {
areEqual &= abs(in[i] - out[i]) < 0.00001;
}
if (areEqual) {
cout << "copy successful" << endl;
} else {
cout << "copy failed" << endl;
}
// usleep(1000000);
return 0;
} | .text
.file "matcpy.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__matcpyBadPKfPf # -- Begin function _Z24__device_stub__matcpyBadPKfPf
.p2align 4, 0x90
.type _Z24__device_stub__matcpyBadPKfPf,@function
_Z24__device_stub__matcpyBadPKfPf: # @_Z24__device_stub__matcpyBadPKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9matcpyBadPKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__matcpyBadPKfPf, .Lfunc_end0-_Z24__device_stub__matcpyBadPKfPf
.cfi_endproc
# -- End function
.globl _Z32__device_stub__matcpyBadWithLoopPKfPf # -- Begin function _Z32__device_stub__matcpyBadWithLoopPKfPf
.p2align 4, 0x90
.type _Z32__device_stub__matcpyBadWithLoopPKfPf,@function
_Z32__device_stub__matcpyBadWithLoopPKfPf: # @_Z32__device_stub__matcpyBadWithLoopPKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17matcpyBadWithLoopPKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z32__device_stub__matcpyBadWithLoopPKfPf, .Lfunc_end1-_Z32__device_stub__matcpyBadWithLoopPKfPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__matcpyPKfiPf # -- Begin function _Z21__device_stub__matcpyPKfiPf
.p2align 4, 0x90
.type _Z21__device_stub__matcpyPKfiPf,@function
_Z21__device_stub__matcpyPKfiPf: # @_Z21__device_stub__matcpyPKfiPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matcpyPKfiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z21__device_stub__matcpyPKfiPf, .Lfunc_end2-_Z21__device_stub__matcpyPKfiPf
.cfi_endproc
# -- End function
.globl _Z29__device_stub__matcpyWithLoopPKfiPf # -- Begin function _Z29__device_stub__matcpyWithLoopPKfiPf
.p2align 4, 0x90
.type _Z29__device_stub__matcpyWithLoopPKfiPf,@function
_Z29__device_stub__matcpyWithLoopPKfiPf: # @_Z29__device_stub__matcpyWithLoopPKfiPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14matcpyWithLoopPKfiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z29__device_stub__matcpyWithLoopPKfiPf, .Lfunc_end3-_Z29__device_stub__matcpyWithLoopPKfiPf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $528544, %rsp # imm = 0x810A0
.cfi_def_cfa_offset 528560
.cfi_offset %rbx, -16
leaq 128(%rsp), %rdi
xorl %ebx, %ebx
movl $264196, %edx # imm = 0x40804
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, 264336(%rsp,%rbx,4)
incq %rbx
cmpq $66049, %rbx # imm = 0x10201
jne .LBB4_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $264196, %esi # imm = 0x40804
callq hipMalloc
leaq 16(%rsp), %rdi
movl $264196, %esi # imm = 0x40804
callq hipMalloc
movq 24(%rsp), %rdi
leaq 264336(%rsp), %rsi
movl $264196, %edx # imm = 0x40804
movl $1, %ecx
callq hipMemcpy
movabsq $12884901897, %rdi # imm = 0x300000009
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movl $66049, 12(%rsp) # imm = 0x10201
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14matcpyWithLoopPKfiPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movq 16(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $264196, %edx # imm = 0x40804
movl $2, %ecx
callq hipMemcpy
movb $1, %al
xorl %ecx, %ecx
movaps .LCPI4_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movss 264336(%rsp,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 128(%rsp,%rcx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm1
seta %dl
andb %dl, %al
incq %rcx
cmpq $66049, %rcx # imm = 0x10201
jne .LBB4_5
# %bb.6:
movl $_ZSt4cout, %edi
testb %al, %al
je .LBB4_10
# %bb.7:
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_15
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_13
.LBB4_9:
movzbl 67(%rbx), %eax
jmp .LBB4_14
.LBB4_10:
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%rbx)
jne .LBB4_9
.LBB4_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $528544, %rsp # imm = 0x810A0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB4_15:
.cfi_def_cfa_offset 528560
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matcpyBadPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matcpyBadWithLoopPKfPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matcpyPKfiPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matcpyWithLoopPKfiPf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matcpyBadPKfPf,@object # @_Z9matcpyBadPKfPf
.section .rodata,"a",@progbits
.globl _Z9matcpyBadPKfPf
.p2align 3, 0x0
_Z9matcpyBadPKfPf:
.quad _Z24__device_stub__matcpyBadPKfPf
.size _Z9matcpyBadPKfPf, 8
.type _Z17matcpyBadWithLoopPKfPf,@object # @_Z17matcpyBadWithLoopPKfPf
.globl _Z17matcpyBadWithLoopPKfPf
.p2align 3, 0x0
_Z17matcpyBadWithLoopPKfPf:
.quad _Z32__device_stub__matcpyBadWithLoopPKfPf
.size _Z17matcpyBadWithLoopPKfPf, 8
.type _Z6matcpyPKfiPf,@object # @_Z6matcpyPKfiPf
.globl _Z6matcpyPKfiPf
.p2align 3, 0x0
_Z6matcpyPKfiPf:
.quad _Z21__device_stub__matcpyPKfiPf
.size _Z6matcpyPKfiPf, 8
.type _Z14matcpyWithLoopPKfiPf,@object # @_Z14matcpyWithLoopPKfiPf
.globl _Z14matcpyWithLoopPKfiPf
.p2align 3, 0x0
_Z14matcpyWithLoopPKfiPf:
.quad _Z29__device_stub__matcpyWithLoopPKfiPf
.size _Z14matcpyWithLoopPKfiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "copy successful"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "copy failed"
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matcpyBadPKfPf"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17matcpyBadWithLoopPKfPf"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6matcpyPKfiPf"
.size .L__unnamed_3, 16
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z14matcpyWithLoopPKfiPf"
.size .L__unnamed_4, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matcpyBadPKfPf
.addrsig_sym _Z32__device_stub__matcpyBadWithLoopPKfPf
.addrsig_sym _Z21__device_stub__matcpyPKfiPf
.addrsig_sym _Z29__device_stub__matcpyWithLoopPKfiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matcpyBadPKfPf
.addrsig_sym _Z17matcpyBadWithLoopPKfPf
.addrsig_sym _Z6matcpyPKfiPf
.addrsig_sym _Z14matcpyWithLoopPKfiPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14matcpyWithLoopPKfiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ULDC UR4, c[0x0][0x4] ; /* 0x0000010000047ab9 */
/* 0x000fe40000000800 */
/*0020*/ ULDC UR5, c[0x0][0x10] ; /* 0x0000040000057ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc8000f8e023f */
/*0040*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fcc000800063f */
/*0050*/ ISETP.NE.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fda000bf05270 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*00b0*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*00c0*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000ea20000002100 */
/*00d0*/ IMAD R0, R3, c[0x0][0x4], R0 ; /* 0x0000010003007a24 */
/* 0x001fca00078e0200 */
/*00e0*/ IADD3 R2, R0, R7, RZ ; /* 0x0000000700027210 */
/* 0x000fe20007ffe0ff */
/*00f0*/ BSSY B0, 0x1c0 ; /* 0x000000c000007945 */
/* 0x000fe20003800000 */
/*0100*/ IADD3 R7, R7, UR4, RZ ; /* 0x0000000407077c10 */
/* 0x000fc6000fffe0ff */
/*0110*/ IMAD R2, R2, c[0x0][0xc], R9 ; /* 0x0000030002027a24 */
/* 0x002fe200078e0209 */
/*0120*/ ISETP.GE.U32.AND P1, PT, R7, UR5, PT ; /* 0x0000000507007c0c */
/* 0x000fc6000bf26070 */
/*0130*/ IMAD R5, R2, c[0x0][0x0], R11 ; /* 0x0000000002057a24 */
/* 0x005fca00078e020b */
/*0140*/ ISETP.GE.AND P0, PT, R5, c[0x0][0x168], PT ; /* 0x00005a0005007a0c */
/* 0x000fda0003f06270 */
/*0150*/ @P0 BRA 0x1b0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0160*/ HFMA2.MMA R4, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff047435 */
/* 0x000fd400000001ff */
/*0170*/ IMAD.WIDE R2, R5, R4, c[0x0][0x160] ; /* 0x0000580005027625 */
/* 0x000fcc00078e0204 */
/*0180*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0190*/ IMAD.WIDE R4, R5, R4, c[0x0][0x170] ; /* 0x00005c0005047625 */
/* 0x000fca00078e0204 */
/*01a0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041e4000c101906 */
/*01b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*01c0*/ @!P1 BRA 0xe0 ; /* 0xffffff1000009947 */
/* 0x000fea000383ffff */
/*01d0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01e0*/ BRA 0x1e0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z6matcpyPKfiPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e280000002200 */
/*0030*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x001fc800078e0205 */
/*0060*/ IMAD R0, R0, c[0x0][0xc], R7 ; /* 0x0000030000007a24 */
/* 0x002fc800078e0207 */
/*0070*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fca00078e0203 */
/*0080*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x168], PT ; /* 0x00005a0000007a0c */
/* 0x000fda0003f06270 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*00b0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*00c0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00d0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00e0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fca00078e0205 */
/*00f0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*0100*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0110*/ BRA 0x110; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z17matcpyBadWithLoopPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ ULDC UR4, c[0x0][0x4] ; /* 0x0000010000047ab9 */
/* 0x000fe40000000800 */
/*0020*/ ULDC UR5, c[0x0][0x10] ; /* 0x0000040000057ab9 */
/* 0x000fe40000000800 */
/*0030*/ UIMAD UR4, UR4, UR5, URZ ; /* 0x00000005040472a4 */
/* 0x000fc8000f8e023f */
/*0040*/ USHF.L.U32 UR5, UR4, 0x2, URZ ; /* 0x0000000204057899 */
/* 0x000fcc000800063f */
/*0050*/ ISETP.NE.AND P0, PT, RZ, UR5, PT ; /* 0x00000005ff007c0c */
/* 0x000fda000bf05270 */
/*0060*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0070*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0080*/ HFMA2.MMA R7, -RZ, RZ, 0, 0 ; /* 0x00000000ff077435 */
/* 0x000fe200000001ff */
/*0090*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*00a0*/ S2R R3, SR_CTAID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002600 */
/*00b0*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*00c0*/ S2R R11, SR_TID.X ; /* 0x00000000000b7919 */
/* 0x000ea20000002100 */
/*00d0*/ IMAD R0, R3, c[0x0][0x4], R0 ; /* 0x0000010003007a24 */
/* 0x001fca00078e0200 */
/*00e0*/ IADD3 R2, R0, R7, RZ ; /* 0x0000000700027210 */
/* 0x000fe40007ffe0ff */
/*00f0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x001fc60000000f00 */
/*0100*/ IMAD R2, R2, c[0x0][0xc], R9 ; /* 0x0000030002027a24 */
/* 0x002fc800078e0209 */
/*0110*/ IMAD R4, R2, c[0x0][0x0], R11 ; /* 0x0000000002047a24 */
/* 0x004fc800078e020b */
/*0120*/ IMAD.WIDE R2, R4, R5, c[0x0][0x160] ; /* 0x0000580004027625 */
/* 0x000fcc00078e0205 */
/*0130*/ LDG.E R3, [R2.64] ; /* 0x0000000602037981 */
/* 0x000ea2000c1e1900 */
/*0140*/ IADD3 R7, R7, UR4, RZ ; /* 0x0000000407077c10 */
/* 0x000fe2000fffe0ff */
/*0150*/ IMAD.WIDE R4, R4, R5, c[0x0][0x168] ; /* 0x00005a0004047625 */
/* 0x000fc600078e0205 */
/*0160*/ ISETP.GE.U32.AND P0, PT, R7, UR5, PT ; /* 0x0000000507007c0c */
/* 0x000fe4000bf06070 */
/*0170*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041f6000c101906 */
/*0180*/ @!P0 BRA 0xe0 ; /* 0xffffff5000008947 */
/* 0x000fea000383ffff */
/*0190*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01a0*/ BRA 0x1a0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9matcpyBadPKfPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e220000002200 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e280000002600 */
/*0040*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e680000002500 */
/*0050*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000ea20000002100 */
/*0060*/ IMAD R0, R7, c[0x0][0x4], R0 ; /* 0x0000010007007a24 */
/* 0x001fc800078e0200 */
/*0070*/ IMAD R0, R0, c[0x0][0xc], R5 ; /* 0x0000030000007a24 */
/* 0x002fe200078e0205 */
/*0080*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*0090*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x004fce00078e0203 */
/*00a0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fcc00078e0205 */
/*00b0*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fca00078e0205 */
/*00d0*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101904 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matcpyBadPKfPf
.globl _Z9matcpyBadPKfPf
.p2align 8
.type _Z9matcpyBadPKfPf,@function
_Z9matcpyBadPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s2, s[0:1], 0x10
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s4, 16
s_and_b32 s4, s4, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[3:4], null, v2, s2, s[14:15]
s_load_b128 s[0:3], s[0:1], 0x0
v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matcpyBadPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matcpyBadPKfPf, .Lfunc_end0-_Z9matcpyBadPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z17matcpyBadWithLoopPKfPf
.globl _Z17matcpyBadWithLoopPKfPf
.p2align 8
.type _Z17matcpyBadWithLoopPKfPf,@function
_Z17matcpyBadWithLoopPKfPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x1c
s_load_b32 s5, s[0:1], 0x14
s_add_u32 s2, s0, 16
s_addc_u32 s3, s1, 0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s5, s7
s_lshl_b32 s5, s4, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB1_3
s_clause 0x1
s_load_b32 s8, s[2:3], 0x0
s_load_b32 s9, s[2:3], 0xc
v_bfe_u32 v1, v0, 10, 10
s_load_b128 s[0:3], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s7, v[1:2]
s_waitcnt lgkmcnt(0)
v_mad_u64_u32 v[3:4], null, s8, v2, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s7, s9, 0xffff
s_mul_i32 s8, s4, s8
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s7, v[2:3]
s_mul_i32 s7, s8, s7
.p2align 6
.LBB1_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s6, s6, s4
s_cmp_ge_u32 s6, s5
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_nc_u32_e32 v0, s7, v0
v_add_co_u32 v3, vcc_lo, s0, v1
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v4, vcc_lo, s1, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s2, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z17matcpyBadWithLoopPKfPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 272
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z17matcpyBadWithLoopPKfPf, .Lfunc_end1-_Z17matcpyBadWithLoopPKfPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z6matcpyPKfiPf
.globl _Z6matcpyPKfiPf
.p2align 8
.type _Z6matcpyPKfiPf,@function
_Z6matcpyPKfiPf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s4, v[1:2]
s_load_b32 s4, s[0:1], 0x8
v_mad_u64_u32 v[3:4], null, v2, s3, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
s_mov_b32 s2, exec_lo
s_waitcnt lgkmcnt(0)
v_cmpx_gt_i32_e64 s4, v0
s_cbranch_execz .LBB2_2
s_load_b64 s[2:3], s[0:1], 0x0
v_ashrrev_i32_e32 v1, 31, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB2_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6matcpyPKfiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end2:
.size _Z6matcpyPKfiPf, .Lfunc_end2-_Z6matcpyPKfiPf
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z14matcpyWithLoopPKfiPf
.globl _Z14matcpyWithLoopPKfiPf
.p2align 8
.type _Z14matcpyWithLoopPKfiPf,@function
_Z14matcpyWithLoopPKfiPf:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x24
s_load_b32 s5, s[0:1], 0x1c
s_add_u32 s2, s0, 24
s_addc_u32 s3, s1, 0
s_mov_b32 s6, 0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s7, s4, 16
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_mul_i32 s4, s5, s7
s_lshl_b32 s5, s4, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s5, 0
s_cbranch_scc1 .LBB3_5
s_clause 0x1
s_load_b32 s8, s[2:3], 0x0
s_load_b32 s9, s[2:3], 0xc
v_bfe_u32 v1, v0, 10, 10
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, s15, s7, v[1:2]
s_clause 0x2
s_load_b64 s[2:3], s[0:1], 0x0
s_load_b32 s7, s[0:1], 0x8
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
v_mad_u64_u32 v[3:4], null, s8, v2, s[14:15]
v_and_b32_e32 v2, 0x3ff, v0
s_and_b32 s9, s9, 0xffff
s_mul_i32 s8, s4, s8
s_mul_i32 s8, s8, s9
s_delay_alu instid0(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, v3, s9, v[2:3]
s_branch .LBB3_3
.p2align 6
.LBB3_2:
s_or_b32 exec_lo, exec_lo, s9
v_add_nc_u32_e32 v0, s8, v0
s_add_i32 s6, s6, s4
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_u32 s6, s5
s_cbranch_scc1 .LBB3_5
.LBB3_3:
s_mov_b32 s9, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s7, v0
s_cbranch_execz .LBB3_2
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[1:2], 2, v[0:1]
v_add_co_u32 v3, vcc_lo, s2, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v4, vcc_lo, s3, v2, vcc_lo
v_add_co_u32 v1, vcc_lo, s0, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
global_load_b32 v3, v[3:4], off
s_waitcnt vmcnt(0)
global_store_b32 v[1:2], v3, off
s_branch .LBB3_2
.LBB3_5:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14matcpyWithLoopPKfiPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 5
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end3:
.size _Z14matcpyWithLoopPKfiPf, .Lfunc_end3-_Z14matcpyWithLoopPKfiPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matcpyBadPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matcpyBadPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: hidden_block_count_x
- .offset: 20
.size: 4
.value_kind: hidden_block_count_y
- .offset: 24
.size: 4
.value_kind: hidden_block_count_z
- .offset: 28
.size: 2
.value_kind: hidden_group_size_x
- .offset: 30
.size: 2
.value_kind: hidden_group_size_y
- .offset: 32
.size: 2
.value_kind: hidden_group_size_z
- .offset: 34
.size: 2
.value_kind: hidden_remainder_x
- .offset: 36
.size: 2
.value_kind: hidden_remainder_y
- .offset: 38
.size: 2
.value_kind: hidden_remainder_z
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 80
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 272
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z17matcpyBadWithLoopPKfPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z17matcpyBadWithLoopPKfPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6matcpyPKfiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6matcpyPKfiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14matcpyWithLoopPKfiPf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z14matcpyWithLoopPKfiPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 5
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0000ab26_00000000-6_matcpy.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3685:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3685:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z9matcpyBadPKfPfPKfPf
.type _Z31__device_stub__Z9matcpyBadPKfPfPKfPf, @function
_Z31__device_stub__Z9matcpyBadPKfPfPKfPf:
.LFB3707:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9matcpyBadPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3707:
.size _Z31__device_stub__Z9matcpyBadPKfPfPKfPf, .-_Z31__device_stub__Z9matcpyBadPKfPfPKfPf
.globl _Z9matcpyBadPKfPf
.type _Z9matcpyBadPKfPf, @function
_Z9matcpyBadPKfPf:
.LFB3708:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z9matcpyBadPKfPfPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3708:
.size _Z9matcpyBadPKfPf, .-_Z9matcpyBadPKfPf
.globl _Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf
.type _Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf, @function
_Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf:
.LFB3709:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z17matcpyBadWithLoopPKfPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3709:
.size _Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf, .-_Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf
.globl _Z17matcpyBadWithLoopPKfPf
.type _Z17matcpyBadWithLoopPKfPf, @function
_Z17matcpyBadWithLoopPKfPf:
.LFB3710:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z17matcpyBadWithLoopPKfPfPKfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3710:
.size _Z17matcpyBadWithLoopPKfPf, .-_Z17matcpyBadWithLoopPKfPf
.globl _Z29__device_stub__Z6matcpyPKfiPfPKfiPf
.type _Z29__device_stub__Z6matcpyPKfiPfPKfiPf, @function
_Z29__device_stub__Z6matcpyPKfiPfPKfiPf:
.LFB3711:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L23
.L19:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L24
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L23:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6matcpyPKfiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L19
.L24:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3711:
.size _Z29__device_stub__Z6matcpyPKfiPfPKfiPf, .-_Z29__device_stub__Z6matcpyPKfiPfPKfiPf
.globl _Z6matcpyPKfiPf
.type _Z6matcpyPKfiPf, @function
_Z6matcpyPKfiPf:
.LFB3712:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z29__device_stub__Z6matcpyPKfiPfPKfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3712:
.size _Z6matcpyPKfiPf, .-_Z6matcpyPKfiPf
.globl _Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf
.type _Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf, @function
_Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf:
.LFB3713:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movl %esi, 20(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 20(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L31
.L27:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L32
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L31:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14matcpyWithLoopPKfiPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L27
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3713:
.size _Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf, .-_Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf
.globl _Z14matcpyWithLoopPKfiPf
.type _Z14matcpyWithLoopPKfiPf, @function
_Z14matcpyWithLoopPKfiPf:
.LFB3714:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3714:
.size _Z14matcpyWithLoopPKfiPf, .-_Z14matcpyWithLoopPKfiPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC2:
.string "copy successful"
.LC3:
.string "copy failed"
.text
.globl main
.type main, @function
main:
.LFB3682:
.cfi_startproc
endbr64
leaq -528384(%rsp), %r11
.cfi_def_cfa 11, 528392
.LPSRL0:
subq $4096, %rsp
orq $0, (%rsp)
cmpq %r11, %rsp
jne .LPSRL0
.cfi_def_cfa_register 7
subq $88, %rsp
.cfi_def_cfa_offset 528480
movq %fs:40, %rax
movq %rax, 528456(%rsp)
xorl %eax, %eax
movl $1, 32(%rsp)
movl $9, 36(%rsp)
movl $3, 40(%rsp)
movl $1, 44(%rsp)
leaq 264256(%rsp), %rdi
movl $264196, %edx
movl $0, %esi
call memset@PLT
movl $0, %eax
.L36:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 48(%rsp,%rax,4)
addq $1, %rax
cmpq $66049, %rax
jne .L36
leaq 8(%rsp), %rdi
movl $264196, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $264196, %esi
call cudaMalloc@PLT
leaq 48(%rsp), %rsi
movl $1, %ecx
movl $264196, %edx
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 24(%rsp)
movl $32, 28(%rsp)
movl 32(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 24(%rsp), %rdx
movq 36(%rsp), %rdi
movl 44(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L45
.L37:
leaq 264256(%rsp), %rdi
movl $2, %ecx
movl $264196, %edx
movq 16(%rsp), %rsi
call cudaMemcpy@PLT
movl $0, %eax
movl $1, %edx
leaq 264256(%rsp), %rsi
movss .LC0(%rip), %xmm2
movsd .LC1(%rip), %xmm1
.L38:
movss 48(%rsp,%rax), %xmm0
subss (%rax,%rsi), %xmm0
andps %xmm2, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm0, %xmm1
seta %cl
andl %ecx, %edx
addq $4, %rax
cmpq $264196, %rax
jne .L38
testb %dl, %dl
je .L39
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.L40:
movq 528456(%rsp), %rax
subq %fs:40, %rax
jne .L46
movl $0, %eax
addq $528472, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L45:
.cfi_restore_state
movq 16(%rsp), %rdx
movl $66049, %esi
movq 8(%rsp), %rdi
call _Z38__device_stub__Z14matcpyWithLoopPKfiPfPKfiPf
jmp .L37
.L39:
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
jmp .L40
.L46:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3682:
.size main, .-main
.section .rodata.str1.1
.LC4:
.string "_Z14matcpyWithLoopPKfiPf"
.LC5:
.string "_Z6matcpyPKfiPf"
.LC6:
.string "_Z17matcpyBadWithLoopPKfPf"
.LC7:
.string "_Z9matcpyBadPKfPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3716:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z14matcpyWithLoopPKfiPf(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _Z6matcpyPKfiPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z17matcpyBadWithLoopPKfPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matcpyBadPKfPf(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3716:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC0:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC1:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matcpy.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z24__device_stub__matcpyBadPKfPf # -- Begin function _Z24__device_stub__matcpyBadPKfPf
.p2align 4, 0x90
.type _Z24__device_stub__matcpyBadPKfPf,@function
_Z24__device_stub__matcpyBadPKfPf: # @_Z24__device_stub__matcpyBadPKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9matcpyBadPKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z24__device_stub__matcpyBadPKfPf, .Lfunc_end0-_Z24__device_stub__matcpyBadPKfPf
.cfi_endproc
# -- End function
.globl _Z32__device_stub__matcpyBadWithLoopPKfPf # -- Begin function _Z32__device_stub__matcpyBadWithLoopPKfPf
.p2align 4, 0x90
.type _Z32__device_stub__matcpyBadWithLoopPKfPf,@function
_Z32__device_stub__matcpyBadWithLoopPKfPf: # @_Z32__device_stub__matcpyBadWithLoopPKfPf
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z17matcpyBadWithLoopPKfPf, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z32__device_stub__matcpyBadWithLoopPKfPf, .Lfunc_end1-_Z32__device_stub__matcpyBadWithLoopPKfPf
.cfi_endproc
# -- End function
.globl _Z21__device_stub__matcpyPKfiPf # -- Begin function _Z21__device_stub__matcpyPKfiPf
.p2align 4, 0x90
.type _Z21__device_stub__matcpyPKfiPf,@function
_Z21__device_stub__matcpyPKfiPf: # @_Z21__device_stub__matcpyPKfiPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6matcpyPKfiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z21__device_stub__matcpyPKfiPf, .Lfunc_end2-_Z21__device_stub__matcpyPKfiPf
.cfi_endproc
# -- End function
.globl _Z29__device_stub__matcpyWithLoopPKfiPf # -- Begin function _Z29__device_stub__matcpyWithLoopPKfiPf
.p2align 4, 0x90
.type _Z29__device_stub__matcpyWithLoopPKfiPf,@function
_Z29__device_stub__matcpyWithLoopPKfiPf: # @_Z29__device_stub__matcpyWithLoopPKfiPf
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movl %esi, 12(%rsp)
movq %rdx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 12(%rsp), %rax
movq %rax, 88(%rsp)
leaq 64(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14matcpyWithLoopPKfiPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end3:
.size _Z29__device_stub__matcpyWithLoopPKfiPf, .Lfunc_end3-_Z29__device_stub__matcpyWithLoopPKfiPf
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function main
.LCPI4_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI4_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $528544, %rsp # imm = 0x810A0
.cfi_def_cfa_offset 528560
.cfi_offset %rbx, -16
leaq 128(%rsp), %rdi
xorl %ebx, %ebx
movl $264196, %edx # imm = 0x40804
xorl %esi, %esi
callq memset@PLT
.p2align 4, 0x90
.LBB4_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
movss %xmm0, 264336(%rsp,%rbx,4)
incq %rbx
cmpq $66049, %rbx # imm = 0x10201
jne .LBB4_1
# %bb.2:
leaq 24(%rsp), %rdi
movl $264196, %esi # imm = 0x40804
callq hipMalloc
leaq 16(%rsp), %rdi
movl $264196, %esi # imm = 0x40804
callq hipMalloc
movq 24(%rsp), %rdi
leaq 264336(%rsp), %rsi
movl $264196, %edx # imm = 0x40804
movl $1, %ecx
callq hipMemcpy
movabsq $12884901897, %rdi # imm = 0x300000009
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB4_4
# %bb.3:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 88(%rsp)
movl $66049, 12(%rsp) # imm = 0x10201
movq %rcx, 80(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 12(%rsp), %rax
movq %rax, 104(%rsp)
leaq 80(%rsp), %rax
movq %rax, 112(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z14matcpyWithLoopPKfiPf, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB4_4:
movq 16(%rsp), %rsi
leaq 128(%rsp), %rdi
movl $264196, %edx # imm = 0x40804
movl $2, %ecx
callq hipMemcpy
movb $1, %al
xorl %ecx, %ecx
movaps .LCPI4_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI4_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB4_5: # =>This Inner Loop Header: Depth=1
movss 264336(%rsp,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss 128(%rsp,%rcx,4), %xmm2
andps %xmm0, %xmm2
cvtss2sd %xmm2, %xmm2
ucomisd %xmm2, %xmm1
seta %dl
andb %dl, %al
incq %rcx
cmpq $66049, %rcx # imm = 0x10201
jne .LBB4_5
# %bb.6:
movl $_ZSt4cout, %edi
testb %al, %al
je .LBB4_10
# %bb.7:
movl $.L.str, %esi
movl $15, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_15
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB4_13
.LBB4_9:
movzbl 67(%rbx), %eax
jmp .LBB4_14
.LBB4_10:
movl $.L.str.1, %esi
movl $11, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB4_15
# %bb.11: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i23
cmpb $0, 56(%rbx)
jne .LBB4_9
.LBB4_13:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB4_14: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $528544, %rsp # imm = 0x810A0
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.LBB4_15:
.cfi_def_cfa_offset 528560
callq _ZSt16__throw_bad_castv
.Lfunc_end4:
.size main, .Lfunc_end4-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB5_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB5_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matcpyBadPKfPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z17matcpyBadWithLoopPKfPf, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6matcpyPKfiPf, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14matcpyWithLoopPKfiPf, %esi
movl $.L__unnamed_4, %edx
movl $.L__unnamed_4, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end5:
.size __hip_module_ctor, .Lfunc_end5-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB6_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB6_2:
retq
.Lfunc_end6:
.size __hip_module_dtor, .Lfunc_end6-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matcpyBadPKfPf,@object # @_Z9matcpyBadPKfPf
.section .rodata,"a",@progbits
.globl _Z9matcpyBadPKfPf
.p2align 3, 0x0
_Z9matcpyBadPKfPf:
.quad _Z24__device_stub__matcpyBadPKfPf
.size _Z9matcpyBadPKfPf, 8
.type _Z17matcpyBadWithLoopPKfPf,@object # @_Z17matcpyBadWithLoopPKfPf
.globl _Z17matcpyBadWithLoopPKfPf
.p2align 3, 0x0
_Z17matcpyBadWithLoopPKfPf:
.quad _Z32__device_stub__matcpyBadWithLoopPKfPf
.size _Z17matcpyBadWithLoopPKfPf, 8
.type _Z6matcpyPKfiPf,@object # @_Z6matcpyPKfiPf
.globl _Z6matcpyPKfiPf
.p2align 3, 0x0
_Z6matcpyPKfiPf:
.quad _Z21__device_stub__matcpyPKfiPf
.size _Z6matcpyPKfiPf, 8
.type _Z14matcpyWithLoopPKfiPf,@object # @_Z14matcpyWithLoopPKfiPf
.globl _Z14matcpyWithLoopPKfiPf
.p2align 3, 0x0
_Z14matcpyWithLoopPKfiPf:
.quad _Z29__device_stub__matcpyWithLoopPKfiPf
.size _Z14matcpyWithLoopPKfiPf, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "copy successful"
.size .L.str, 16
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "copy failed"
.size .L.str.1, 12
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9matcpyBadPKfPf"
.size .L__unnamed_1, 18
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z17matcpyBadWithLoopPKfPf"
.size .L__unnamed_2, 27
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z6matcpyPKfiPf"
.size .L__unnamed_3, 16
.type .L__unnamed_4,@object # @3
.L__unnamed_4:
.asciz "_Z14matcpyWithLoopPKfiPf"
.size .L__unnamed_4, 25
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matcpyBadPKfPf
.addrsig_sym _Z32__device_stub__matcpyBadWithLoopPKfPf
.addrsig_sym _Z21__device_stub__matcpyPKfiPf
.addrsig_sym _Z29__device_stub__matcpyWithLoopPKfiPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matcpyBadPKfPf
.addrsig_sym _Z17matcpyBadWithLoopPKfPf
.addrsig_sym _Z6matcpyPKfiPf
.addrsig_sym _Z14matcpyWithLoopPKfiPf
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | __global__ void doublify(float *a)
{
int idx = threadIdx.x + threadIdx.y*4;
a[idx] *= 2;
} | code for sm_80
Function : _Z8doublifyPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ LEA R2, R3, R2, 0x2 ; /* 0x0000000203027211 */
/* 0x001fca00078e10ff */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FADD R5, R0, R0 ; /* 0x0000000000057221 */
/* 0x004fca0000000000 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | __global__ void doublify(float *a)
{
int idx = threadIdx.x + threadIdx.y*4;
a[idx] *= 2;
} | .file "tmpxft_0013510f_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8doublifyPfPf
.type _Z27__device_stub__Z8doublifyPfPf, @function
_Z27__device_stub__Z8doublifyPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8doublifyPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z8doublifyPfPf, .-_Z27__device_stub__Z8doublifyPfPf
.globl _Z8doublifyPf
.type _Z8doublifyPf, @function
_Z8doublifyPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8doublifyPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8doublifyPf, .-_Z8doublifyPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8doublifyPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8doublifyPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | __global__ void doublify(float *a)
{
int idx = threadIdx.x + threadIdx.y*4;
a[idx] *= 2;
} | #include <hip/hip_runtime.h>
__global__ void doublify(float *a)
{
int idx = threadIdx.x + threadIdx.y*4;
a[idx] *= 2;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
__global__ void doublify(float *a)
{
int idx = threadIdx.x + threadIdx.y*4;
a[idx] *= 2;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8doublifyPf
.globl _Z8doublifyPf
.p2align 8
.type _Z8doublifyPf,@function
_Z8doublifyPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshrrev_b32_e32 v1, 8, v0
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 0xffc, v1
v_add_lshl_u32 v0, v1, v0, 2
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8doublifyPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8doublifyPf, .Lfunc_end0-_Z8doublifyPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8doublifyPf
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z8doublifyPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
__global__ void doublify(float *a)
{
int idx = threadIdx.x + threadIdx.y*4;
a[idx] *= 2;
} | .text
.file "simple.hip"
.globl _Z23__device_stub__doublifyPf # -- Begin function _Z23__device_stub__doublifyPf
.p2align 4, 0x90
.type _Z23__device_stub__doublifyPf,@function
_Z23__device_stub__doublifyPf: # @_Z23__device_stub__doublifyPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8doublifyPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__doublifyPf, .Lfunc_end0-_Z23__device_stub__doublifyPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8doublifyPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8doublifyPf,@object # @_Z8doublifyPf
.section .rodata,"a",@progbits
.globl _Z8doublifyPf
.p2align 3, 0x0
_Z8doublifyPf:
.quad _Z23__device_stub__doublifyPf
.size _Z8doublifyPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8doublifyPf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__doublifyPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8doublifyPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8doublifyPf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e240000002200 */
/*0050*/ LEA R2, R3, R2, 0x2 ; /* 0x0000000203027211 */
/* 0x001fca00078e10ff */
/*0060*/ IMAD.WIDE R2, R2, R5, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0205 */
/*0070*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0080*/ FADD R5, R0, R0 ; /* 0x0000000000057221 */
/* 0x004fca0000000000 */
/*0090*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8doublifyPf
.globl _Z8doublifyPf
.p2align 8
.type _Z8doublifyPf,@function
_Z8doublifyPf:
s_load_b64 s[0:1], s[0:1], 0x0
v_lshrrev_b32_e32 v1, 8, v0
v_and_b32_e32 v0, 0x3ff, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, 0xffc, v1
v_add_lshl_u32 v0, v1, v0, 2
s_waitcnt lgkmcnt(0)
global_load_b32 v1, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_f32_e32 v1, v1, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8doublifyPf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 8
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 2
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8doublifyPf, .Lfunc_end0-_Z8doublifyPf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 8
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8doublifyPf
.private_segment_fixed_size: 0
.sgpr_count: 2
.sgpr_spill_count: 0
.symbol: _Z8doublifyPf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013510f_00000000-6_simple.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z8doublifyPfPf
.type _Z27__device_stub__Z8doublifyPfPf, @function
_Z27__device_stub__Z8doublifyPfPf:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z8doublifyPf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z27__device_stub__Z8doublifyPfPf, .-_Z27__device_stub__Z8doublifyPfPf
.globl _Z8doublifyPf
.type _Z8doublifyPf, @function
_Z8doublifyPf:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z8doublifyPfPf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z8doublifyPf, .-_Z8doublifyPf
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8doublifyPf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8doublifyPf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "simple.hip"
.globl _Z23__device_stub__doublifyPf # -- Begin function _Z23__device_stub__doublifyPf
.p2align 4, 0x90
.type _Z23__device_stub__doublifyPf,@function
_Z23__device_stub__doublifyPf: # @_Z23__device_stub__doublifyPf
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z8doublifyPf, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z23__device_stub__doublifyPf, .Lfunc_end0-_Z23__device_stub__doublifyPf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8doublifyPf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8doublifyPf,@object # @_Z8doublifyPf
.section .rodata,"a",@progbits
.globl _Z8doublifyPf
.p2align 3, 0x0
_Z8doublifyPf:
.quad _Z23__device_stub__doublifyPf
.size _Z8doublifyPf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z8doublifyPf"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__doublifyPf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8doublifyPf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <iostream>
#include <string>
#include <vector>
#include <fstream>
#include <sstream>
#include <cuda.h>
#define THREAD_COUNT 1024
// Max device memory : 4 GB
#define MAX_MEMORY ((long long)4e9)
void read_graph(std::string fname, int *&row_ptr, int *&col_ind, int &num_nodes, int &num_edges, bool zero_based = false)
{
std::ifstream input(fname.c_str());
if (input.fail())
throw "No file is found in the current path!";
// read graph
std::string line = "%";
while (line.find("%") != std::string::npos)
{
getline(input, line);
}
std::istringstream ss(line.c_str());
ss >> num_nodes >> num_nodes >> num_edges;
int edge_cnt = 0;
int v1, v2;
std::vector< std::vector<int> > adj_list(num_nodes);
for (int i = 0; i < num_edges; i++)
{
getline(input, line);
std::istringstream inp(line.c_str());
inp >> v1 >> v2;
if (!zero_based)
{
v1--; // make it 0 based
v2--;
}
if (v1 != v2)
{
adj_list[v1].push_back(v2); // add the edge v1->v2
adj_list[v2].push_back(v1); // add the edge v2->v1
edge_cnt++;
}
}
input.close();
num_edges = edge_cnt;
cudaMallocHost((void **)&row_ptr, sizeof(int) * (num_nodes + 1));
cudaMallocHost((void **)&col_ind, sizeof(int) * (2 * num_edges));
row_ptr[0] = 0;
int index = 0;
for (int v = 0; v < num_nodes; v++)
{
row_ptr[v + 1] = adj_list[v].size(); // assign number of edges going from node v
for (int i = 0; i < (int)adj_list[v].size(); i++)
{
col_ind[index] = adj_list[v][i]; // put all edges in order wrt row_ptr
index++;
}
}
for (int v = 1; v < num_nodes + 1; v++)
{ // cumulative sum
row_ptr[v] += row_ptr[v - 1];
}
}
__global__
void cent_kernel(float *results, int *dist, int *sigma, float *delta, int *rp, int *ci, int n) {
__shared__ int level;
__shared__ int improved;
for(int s = blockIdx.x; s < n; s += gridDim.x) {
if(threadIdx.x == 0) {
results[s] = rp[s + 1] - rp[s]; // degree 1
level = 0;
improved = 1;
dist[blockIdx.x * n + s] = 0;
sigma[blockIdx.x * n + s] = 1;
}
__syncthreads();
// BFS
while(improved == 1) {
if(threadIdx.x == 0) improved = 0;
for(int node = threadIdx.x; node < n; node += blockDim.x) {
for(int edge = rp[node]; edge < rp[node + 1]; edge++) {
int &adj = ci[edge];
if(dist[(blockIdx.x * n) + adj] == level && dist[(blockIdx.x * n) + node] == -1) {
dist[(blockIdx.x * n) + node] = level + 1;
improved = 1;
}
if(dist[(blockIdx.x * n) + adj] == level && dist[(blockIdx.x * n) + node] == level + 1) {
sigma[(blockIdx.x * n) + node] += (float) sigma[(blockIdx.x * n) + adj];
}
}
}
if(threadIdx.x == 0) level++;
__syncthreads();
}
int dist_sum = 0;
int dist2_cnt = 0;
// DISTANCE ADDER
if(threadIdx.x == 0) {
for(int i = 0; i < n; i++) {
if(dist[(blockIdx.x * n) + i] > 0) {
if(dist[(blockIdx.x * n) + i] <= 2) dist2_cnt++;
dist_sum += dist[(blockIdx.x * n) + i];
}
}
results[n + s] = dist2_cnt; // degree 2
results[2 * n + s] = (float) n / dist_sum; // closeness cent.
}
while(level > 0) {
for(int node = threadIdx.x; node < n; node += blockDim.x) {
if(dist[blockIdx.x * n + node] == level){
for(int edge = rp[node]; edge < rp[node + 1]; edge++) {
int adj = ci[edge];
if(dist[(blockIdx.x * n) + adj] + 1 == dist[(blockIdx.x * n) + node]) {
atomicAdd(&delta[(blockIdx.x * n) + adj], (sigma[(blockIdx.x * n) + adj] * 1.0) / sigma[(blockIdx.x * n) + node] * (1 + delta[(blockIdx.x * n) + node]));
}
}
atomicAdd(&results[3 * n + node], delta[(blockIdx.x * n) + node] / 2);
}
}
if(threadIdx.x == 0) level--;
__syncthreads();
}
for(int i = 0; i < n; i++) {
dist[(blockIdx.x * n) + i] = -1;
sigma[(blockIdx.x * n) + i] = 0;
delta[(blockIdx.x * n) + i] = 0;
}
}
}
float* compute_centralities(int *rp, int *ci, int n, float &time_taken) {
const int BLOCK_COUNT = MAX_MEMORY / (4 * 3 * n);
int *sigma, *dist;
float *delta, *d_results;
cudaMalloc((void **)&d_results, sizeof(float) * n * 4);
cudaMalloc((void **)&sigma, sizeof(int) * n * BLOCK_COUNT);
cudaMalloc((void **)&dist, sizeof(int) * n * BLOCK_COUNT);
cudaMalloc((void **)&delta, sizeof(float) * n * BLOCK_COUNT);
cudaMemset(dist, -1, sizeof(int) * n * BLOCK_COUNT);
cudaMemset(sigma, 0, sizeof(int) * n * BLOCK_COUNT);
cudaMemset(delta, 0, sizeof(float) * n * BLOCK_COUNT);
cudaMemset(d_results, 0, sizeof(float) * 4 * n);
cudaEvent_t start, end;
cudaEventCreate(&start);
cudaEventCreate(&end);
cudaEventRecord(start);
cent_kernel<<<BLOCK_COUNT, THREAD_COUNT>>>(d_results, dist, sigma, delta, rp, ci, n);
cudaDeviceSynchronize();
cudaEventRecord(end);
cudaEventSynchronize(end);
cudaEventElapsedTime(&time_taken, start, end);
float *results;
cudaMallocHost((void **)&results, sizeof(float) * n * 4);
cudaMemcpy(results, d_results, sizeof(float) * n * 4, cudaMemcpyDeviceToHost);
cudaFree(sigma);
cudaFree(dist);
cudaFree(delta);
cudaFree(d_results);
cudaDeviceSynchronize();
return results;
}
int main()
{
cudaSetDevice(0);
std::string filename = "../data/wave.mtx";
int *row_ptr, *col_ind;
int num_nodes, num_edges;
read_graph(filename, row_ptr, col_ind, num_nodes, num_edges);
printf("[INFO] Graph is read: %s.\n", filename.c_str());
int *rp;
int *ci;
cudaMalloc((void **)&rp, sizeof(int) * (num_nodes + 1));
cudaMalloc((void **)&ci, sizeof(int) * (num_edges * 2));
printf("[INFO] CUDA memory parameters are allocated for kernel function.\n");
cudaMemcpy(rp, row_ptr, sizeof(int) * (num_nodes + 1), cudaMemcpyHostToDevice);
cudaMemcpy(ci, col_ind, sizeof(int) * (num_edges * 2), cudaMemcpyHostToDevice);
printf("[INFO] CUDA memory parameters are set for kernel function.\n");
float time_taken;
float *results = compute_centralities(rp, ci, num_nodes, time_taken);
printf("[INFO] Kernel function is finished.\n");
printf("Centrality Results:\n");
for (int i = 0; i < num_nodes; i++)
{
printf("%.5f; %.5f; %.5f; %.5f\n ", results[i], results[num_nodes + i], results[2 * num_nodes + i], results[3 * num_nodes + i]);
}
printf("[INFO] Kernel call is ended in: %.5f ms.\n", time_taken);
cudaFreeHost(results);
cudaFreeHost(row_ptr);
cudaFreeHost(col_ind);
cudaFree(rp);
cudaFree(ci);
return 0;
} | #include <iostream>
#include <string>
#include <vector>
#include <fstream>
#include <sstream>
#include <hip/hip_runtime.h>
#define THREAD_COUNT 1024
// Max device memory : 4 GB
#define MAX_MEMORY ((long long)4e9)
void read_graph(std::string fname, int *&row_ptr, int *&col_ind, int &num_nodes, int &num_edges, bool zero_based = false)
{
std::ifstream input(fname.c_str());
if (input.fail())
throw "No file is found in the current path!";
// read graph
std::string line = "%";
while (line.find("%") != std::string::npos)
{
getline(input, line);
}
std::istringstream ss(line.c_str());
ss >> num_nodes >> num_nodes >> num_edges;
int edge_cnt = 0;
int v1, v2;
std::vector< std::vector<int> > adj_list(num_nodes);
for (int i = 0; i < num_edges; i++)
{
getline(input, line);
std::istringstream inp(line.c_str());
inp >> v1 >> v2;
if (!zero_based)
{
v1--; // make it 0 based
v2--;
}
if (v1 != v2)
{
adj_list[v1].push_back(v2); // add the edge v1->v2
adj_list[v2].push_back(v1); // add the edge v2->v1
edge_cnt++;
}
}
input.close();
num_edges = edge_cnt;
hipHostMalloc((void **)&row_ptr, sizeof(int) * (num_nodes + 1), hipHostMallocDefault);
hipHostMalloc((void **)&col_ind, sizeof(int) * (2 * num_edges), hipHostMallocDefault);
row_ptr[0] = 0;
int index = 0;
for (int v = 0; v < num_nodes; v++)
{
row_ptr[v + 1] = adj_list[v].size(); // assign number of edges going from node v
for (int i = 0; i < (int)adj_list[v].size(); i++)
{
col_ind[index] = adj_list[v][i]; // put all edges in order wrt row_ptr
index++;
}
}
for (int v = 1; v < num_nodes + 1; v++)
{ // cumulative sum
row_ptr[v] += row_ptr[v - 1];
}
}
__global__
void cent_kernel(float *results, int *dist, int *sigma, float *delta, int *rp, int *ci, int n) {
__shared__ int level;
__shared__ int improved;
for(int s = blockIdx.x; s < n; s += gridDim.x) {
if(threadIdx.x == 0) {
results[s] = rp[s + 1] - rp[s]; // degree 1
level = 0;
improved = 1;
dist[blockIdx.x * n + s] = 0;
sigma[blockIdx.x * n + s] = 1;
}
__syncthreads();
// BFS
while(improved == 1) {
if(threadIdx.x == 0) improved = 0;
for(int node = threadIdx.x; node < n; node += blockDim.x) {
for(int edge = rp[node]; edge < rp[node + 1]; edge++) {
int &adj = ci[edge];
if(dist[(blockIdx.x * n) + adj] == level && dist[(blockIdx.x * n) + node] == -1) {
dist[(blockIdx.x * n) + node] = level + 1;
improved = 1;
}
if(dist[(blockIdx.x * n) + adj] == level && dist[(blockIdx.x * n) + node] == level + 1) {
sigma[(blockIdx.x * n) + node] += (float) sigma[(blockIdx.x * n) + adj];
}
}
}
if(threadIdx.x == 0) level++;
__syncthreads();
}
int dist_sum = 0;
int dist2_cnt = 0;
// DISTANCE ADDER
if(threadIdx.x == 0) {
for(int i = 0; i < n; i++) {
if(dist[(blockIdx.x * n) + i] > 0) {
if(dist[(blockIdx.x * n) + i] <= 2) dist2_cnt++;
dist_sum += dist[(blockIdx.x * n) + i];
}
}
results[n + s] = dist2_cnt; // degree 2
results[2 * n + s] = (float) n / dist_sum; // closeness cent.
}
while(level > 0) {
for(int node = threadIdx.x; node < n; node += blockDim.x) {
if(dist[blockIdx.x * n + node] == level){
for(int edge = rp[node]; edge < rp[node + 1]; edge++) {
int adj = ci[edge];
if(dist[(blockIdx.x * n) + adj] + 1 == dist[(blockIdx.x * n) + node]) {
atomicAdd(&delta[(blockIdx.x * n) + adj], (sigma[(blockIdx.x * n) + adj] * 1.0) / sigma[(blockIdx.x * n) + node] * (1 + delta[(blockIdx.x * n) + node]));
}
}
atomicAdd(&results[3 * n + node], delta[(blockIdx.x * n) + node] / 2);
}
}
if(threadIdx.x == 0) level--;
__syncthreads();
}
for(int i = 0; i < n; i++) {
dist[(blockIdx.x * n) + i] = -1;
sigma[(blockIdx.x * n) + i] = 0;
delta[(blockIdx.x * n) + i] = 0;
}
}
}
float* compute_centralities(int *rp, int *ci, int n, float &time_taken) {
const int BLOCK_COUNT = MAX_MEMORY / (4 * 3 * n);
int *sigma, *dist;
float *delta, *d_results;
hipMalloc((void **)&d_results, sizeof(float) * n * 4);
hipMalloc((void **)&sigma, sizeof(int) * n * BLOCK_COUNT);
hipMalloc((void **)&dist, sizeof(int) * n * BLOCK_COUNT);
hipMalloc((void **)&delta, sizeof(float) * n * BLOCK_COUNT);
hipMemset(dist, -1, sizeof(int) * n * BLOCK_COUNT);
hipMemset(sigma, 0, sizeof(int) * n * BLOCK_COUNT);
hipMemset(delta, 0, sizeof(float) * n * BLOCK_COUNT);
hipMemset(d_results, 0, sizeof(float) * 4 * n);
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
cent_kernel<<<BLOCK_COUNT, THREAD_COUNT>>>(d_results, dist, sigma, delta, rp, ci, n);
hipDeviceSynchronize();
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time_taken, start, end);
float *results;
hipHostMalloc((void **)&results, sizeof(float) * n * 4, hipHostMallocDefault);
hipMemcpy(results, d_results, sizeof(float) * n * 4, hipMemcpyDeviceToHost);
hipFree(sigma);
hipFree(dist);
hipFree(delta);
hipFree(d_results);
hipDeviceSynchronize();
return results;
}
int main()
{
hipSetDevice(0);
std::string filename = "../data/wave.mtx";
int *row_ptr, *col_ind;
int num_nodes, num_edges;
read_graph(filename, row_ptr, col_ind, num_nodes, num_edges);
printf("[INFO] Graph is read: %s.\n", filename.c_str());
int *rp;
int *ci;
hipMalloc((void **)&rp, sizeof(int) * (num_nodes + 1));
hipMalloc((void **)&ci, sizeof(int) * (num_edges * 2));
printf("[INFO] CUDA memory parameters are allocated for kernel function.\n");
hipMemcpy(rp, row_ptr, sizeof(int) * (num_nodes + 1), hipMemcpyHostToDevice);
hipMemcpy(ci, col_ind, sizeof(int) * (num_edges * 2), hipMemcpyHostToDevice);
printf("[INFO] CUDA memory parameters are set for kernel function.\n");
float time_taken;
float *results = compute_centralities(rp, ci, num_nodes, time_taken);
printf("[INFO] Kernel function is finished.\n");
printf("Centrality Results:\n");
for (int i = 0; i < num_nodes; i++)
{
printf("%.5f; %.5f; %.5f; %.5f\n ", results[i], results[num_nodes + i], results[2 * num_nodes + i], results[3 * num_nodes + i]);
}
printf("[INFO] Kernel call is ended in: %.5f ms.\n", time_taken);
hipHostFree(results);
hipHostFree(row_ptr);
hipHostFree(col_ind);
hipFree(rp);
hipFree(ci);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <iostream>
#include <string>
#include <vector>
#include <fstream>
#include <sstream>
#include <hip/hip_runtime.h>
#define THREAD_COUNT 1024
// Max device memory : 4 GB
#define MAX_MEMORY ((long long)4e9)
void read_graph(std::string fname, int *&row_ptr, int *&col_ind, int &num_nodes, int &num_edges, bool zero_based = false)
{
std::ifstream input(fname.c_str());
if (input.fail())
throw "No file is found in the current path!";
// read graph
std::string line = "%";
while (line.find("%") != std::string::npos)
{
getline(input, line);
}
std::istringstream ss(line.c_str());
ss >> num_nodes >> num_nodes >> num_edges;
int edge_cnt = 0;
int v1, v2;
std::vector< std::vector<int> > adj_list(num_nodes);
for (int i = 0; i < num_edges; i++)
{
getline(input, line);
std::istringstream inp(line.c_str());
inp >> v1 >> v2;
if (!zero_based)
{
v1--; // make it 0 based
v2--;
}
if (v1 != v2)
{
adj_list[v1].push_back(v2); // add the edge v1->v2
adj_list[v2].push_back(v1); // add the edge v2->v1
edge_cnt++;
}
}
input.close();
num_edges = edge_cnt;
hipHostMalloc((void **)&row_ptr, sizeof(int) * (num_nodes + 1), hipHostMallocDefault);
hipHostMalloc((void **)&col_ind, sizeof(int) * (2 * num_edges), hipHostMallocDefault);
row_ptr[0] = 0;
int index = 0;
for (int v = 0; v < num_nodes; v++)
{
row_ptr[v + 1] = adj_list[v].size(); // assign number of edges going from node v
for (int i = 0; i < (int)adj_list[v].size(); i++)
{
col_ind[index] = adj_list[v][i]; // put all edges in order wrt row_ptr
index++;
}
}
for (int v = 1; v < num_nodes + 1; v++)
{ // cumulative sum
row_ptr[v] += row_ptr[v - 1];
}
}
__global__
void cent_kernel(float *results, int *dist, int *sigma, float *delta, int *rp, int *ci, int n) {
__shared__ int level;
__shared__ int improved;
for(int s = blockIdx.x; s < n; s += gridDim.x) {
if(threadIdx.x == 0) {
results[s] = rp[s + 1] - rp[s]; // degree 1
level = 0;
improved = 1;
dist[blockIdx.x * n + s] = 0;
sigma[blockIdx.x * n + s] = 1;
}
__syncthreads();
// BFS
while(improved == 1) {
if(threadIdx.x == 0) improved = 0;
for(int node = threadIdx.x; node < n; node += blockDim.x) {
for(int edge = rp[node]; edge < rp[node + 1]; edge++) {
int &adj = ci[edge];
if(dist[(blockIdx.x * n) + adj] == level && dist[(blockIdx.x * n) + node] == -1) {
dist[(blockIdx.x * n) + node] = level + 1;
improved = 1;
}
if(dist[(blockIdx.x * n) + adj] == level && dist[(blockIdx.x * n) + node] == level + 1) {
sigma[(blockIdx.x * n) + node] += (float) sigma[(blockIdx.x * n) + adj];
}
}
}
if(threadIdx.x == 0) level++;
__syncthreads();
}
int dist_sum = 0;
int dist2_cnt = 0;
// DISTANCE ADDER
if(threadIdx.x == 0) {
for(int i = 0; i < n; i++) {
if(dist[(blockIdx.x * n) + i] > 0) {
if(dist[(blockIdx.x * n) + i] <= 2) dist2_cnt++;
dist_sum += dist[(blockIdx.x * n) + i];
}
}
results[n + s] = dist2_cnt; // degree 2
results[2 * n + s] = (float) n / dist_sum; // closeness cent.
}
while(level > 0) {
for(int node = threadIdx.x; node < n; node += blockDim.x) {
if(dist[blockIdx.x * n + node] == level){
for(int edge = rp[node]; edge < rp[node + 1]; edge++) {
int adj = ci[edge];
if(dist[(blockIdx.x * n) + adj] + 1 == dist[(blockIdx.x * n) + node]) {
atomicAdd(&delta[(blockIdx.x * n) + adj], (sigma[(blockIdx.x * n) + adj] * 1.0) / sigma[(blockIdx.x * n) + node] * (1 + delta[(blockIdx.x * n) + node]));
}
}
atomicAdd(&results[3 * n + node], delta[(blockIdx.x * n) + node] / 2);
}
}
if(threadIdx.x == 0) level--;
__syncthreads();
}
for(int i = 0; i < n; i++) {
dist[(blockIdx.x * n) + i] = -1;
sigma[(blockIdx.x * n) + i] = 0;
delta[(blockIdx.x * n) + i] = 0;
}
}
}
float* compute_centralities(int *rp, int *ci, int n, float &time_taken) {
const int BLOCK_COUNT = MAX_MEMORY / (4 * 3 * n);
int *sigma, *dist;
float *delta, *d_results;
hipMalloc((void **)&d_results, sizeof(float) * n * 4);
hipMalloc((void **)&sigma, sizeof(int) * n * BLOCK_COUNT);
hipMalloc((void **)&dist, sizeof(int) * n * BLOCK_COUNT);
hipMalloc((void **)&delta, sizeof(float) * n * BLOCK_COUNT);
hipMemset(dist, -1, sizeof(int) * n * BLOCK_COUNT);
hipMemset(sigma, 0, sizeof(int) * n * BLOCK_COUNT);
hipMemset(delta, 0, sizeof(float) * n * BLOCK_COUNT);
hipMemset(d_results, 0, sizeof(float) * 4 * n);
hipEvent_t start, end;
hipEventCreate(&start);
hipEventCreate(&end);
hipEventRecord(start);
cent_kernel<<<BLOCK_COUNT, THREAD_COUNT>>>(d_results, dist, sigma, delta, rp, ci, n);
hipDeviceSynchronize();
hipEventRecord(end);
hipEventSynchronize(end);
hipEventElapsedTime(&time_taken, start, end);
float *results;
hipHostMalloc((void **)&results, sizeof(float) * n * 4, hipHostMallocDefault);
hipMemcpy(results, d_results, sizeof(float) * n * 4, hipMemcpyDeviceToHost);
hipFree(sigma);
hipFree(dist);
hipFree(delta);
hipFree(d_results);
hipDeviceSynchronize();
return results;
}
int main()
{
hipSetDevice(0);
std::string filename = "../data/wave.mtx";
int *row_ptr, *col_ind;
int num_nodes, num_edges;
read_graph(filename, row_ptr, col_ind, num_nodes, num_edges);
printf("[INFO] Graph is read: %s.\n", filename.c_str());
int *rp;
int *ci;
hipMalloc((void **)&rp, sizeof(int) * (num_nodes + 1));
hipMalloc((void **)&ci, sizeof(int) * (num_edges * 2));
printf("[INFO] CUDA memory parameters are allocated for kernel function.\n");
hipMemcpy(rp, row_ptr, sizeof(int) * (num_nodes + 1), hipMemcpyHostToDevice);
hipMemcpy(ci, col_ind, sizeof(int) * (num_edges * 2), hipMemcpyHostToDevice);
printf("[INFO] CUDA memory parameters are set for kernel function.\n");
float time_taken;
float *results = compute_centralities(rp, ci, num_nodes, time_taken);
printf("[INFO] Kernel function is finished.\n");
printf("Centrality Results:\n");
for (int i = 0; i < num_nodes; i++)
{
printf("%.5f; %.5f; %.5f; %.5f\n ", results[i], results[num_nodes + i], results[2 * num_nodes + i], results[3 * num_nodes + i]);
}
printf("[INFO] Kernel call is ended in: %.5f ms.\n", time_taken);
hipHostFree(results);
hipHostFree(row_ptr);
hipHostFree(col_ind);
hipFree(rp);
hipFree(ci);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11cent_kernelPfPiS0_S_S0_S0_i
.globl _Z11cent_kernelPfPiS0_S_S0_S0_i
.p2align 8
.type _Z11cent_kernelPfPiS0_S_S0_S0_i,@function
_Z11cent_kernelPfPiS0_S_S0_S0_i:
s_load_b32 s20, s[0:1], 0x30
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s15, s20
s_cbranch_scc1 .LBB0_47
s_mov_b32 s16, s15
s_clause 0x2
s_load_b256 s[4:11], s[0:1], 0x0
s_load_b128 s[12:15], s[0:1], 0x20
s_load_b32 s21, s[0:1], 0x38
s_add_u32 s18, s0, 56
v_cmp_eq_u32_e64 s2, 0, v0
v_cmp_gt_i32_e64 s3, s20, v0
s_addc_u32 s19, s1, 0
s_lshl_b32 s22, s20, 1
v_cvt_f32_i32_e32 v21, s20
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v22, 1
s_cmp_gt_i32 s20, 0
s_mov_b32 s1, 0
s_cselect_b32 s23, -1, 0
s_mul_i32 s24, s16, s20
s_mul_i32 s25, s20, 3
s_branch .LBB0_3
.LBB0_2:
s_add_i32 s16, s21, s16
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s16, s20
s_cbranch_scc1 .LBB0_47
.LBB0_3:
s_and_saveexec_b32 s26, s2
s_cbranch_execz .LBB0_5
s_ashr_i32 s17, s16, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_lshl_b64 s[28:29], s[16:17], 2
s_waitcnt lgkmcnt(0)
s_add_u32 s30, s12, s28
s_addc_u32 s31, s13, s29
s_add_u32 s28, s4, s28
global_load_b64 v[3:4], v2, s[30:31]
s_addc_u32 s29, s5, s29
s_add_i32 s0, s16, s24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[30:31], s[0:1], 2
s_add_u32 s34, s6, s30
s_addc_u32 s35, s7, s31
s_add_u32 s30, s8, s30
s_addc_u32 s31, s9, s31
s_waitcnt vmcnt(0)
v_sub_nc_u32_e32 v1, v4, v3
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, 1
s_delay_alu instid0(VALU_DEP_2)
v_cvt_f32_i32_e32 v1, v1
ds_store_b64 v2, v[3:4]
s_clause 0x2
global_store_b32 v2, v1, s[28:29]
global_store_b32 v2, v3, s[34:35]
global_store_b32 v2, v4, s[30:31]
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s26
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_ne_u32_e32 vcc_lo, 1, v1
s_cbranch_vccz .LBB0_29
.LBB0_6:
s_and_saveexec_b32 s17, s2
s_cbranch_execz .LBB0_11
v_mov_b32_e32 v1, 0
s_and_not1_b32 vcc_lo, exec_lo, s23
s_mov_b32 s26, 0
s_cbranch_vccnz .LBB0_10
v_mov_b32_e32 v1, 0
s_mov_b32 s0, s24
s_mov_b32 s27, s20
.LBB0_9:
s_lshl_b64 s[28:29], s[0:1], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s28, s6, s28
s_addc_u32 s29, s7, s29
global_load_b32 v3, v2, s[28:29]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v4, -1, v3
v_max_i32_e32 v3, 0, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_u32_e32 vcc_lo, 2, v4
v_add_nc_u32_e32 v1, v3, v1
s_cmp_lg_u32 vcc_lo, 0
s_addc_u32 s26, s26, 0
s_add_i32 s27, s27, -1
s_add_i32 s0, s0, 1
s_cmp_eq_u32 s27, 0
s_cbranch_scc0 .LBB0_9
.LBB0_10:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cvt_f32_i32_e32 v1, v1
s_add_i32 s28, s16, s20
s_ashr_i32 s29, s28, 31
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_lshl_b64 s[28:29], s[28:29], 2
v_div_scale_f32 v3, null, v1, v1, v21
v_div_scale_f32 v6, vcc_lo, v21, v1, v21
s_add_u32 s28, s4, s28
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_rcp_f32_e32 v4, v3
s_addc_u32 s29, s5, s29
s_add_i32 s30, s16, s22
s_ashr_i32 s31, s30, 31
s_waitcnt_depctr 0xfff
v_fma_f32 v5, -v3, v4, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v4, v5, v4
v_mul_f32_e32 v5, v6, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v7, -v3, v5, v6
v_fmac_f32_e32 v5, v7, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v3, -v3, v5, v6
v_div_fmas_f32 v3, v3, v4, v5
v_cvt_f32_i32_e32 v4, s26
s_lshl_b64 s[26:27], s[30:31], 2
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
s_add_u32 s26, s4, s26
v_div_fixup_f32 v1, v3, v1, v21
s_addc_u32 s27, s5, s27
s_clause 0x1
global_store_b32 v2, v4, s[28:29]
global_store_b32 v2, v1, s[26:27]
.LBB0_11:
s_or_b32 exec_lo, exec_lo, s17
s_branch .LBB0_13
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
.LBB0_13:
ds_load_b32 v23, v2
s_waitcnt lgkmcnt(0)
v_cmp_gt_i32_e32 vcc_lo, 1, v23
s_cbranch_vccnz .LBB0_45
s_and_saveexec_b32 s0, s3
s_cbranch_execz .LBB0_26
s_load_b32 s17, s[18:19], 0xc
v_mov_b32_e32 v3, v0
s_mov_b32 s26, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s17, s17, 0xffff
s_branch .LBB0_17
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s27
v_add_nc_u32_e32 v3, s17, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s20, v3
s_or_b32 s26, vcc_lo, s26
s_and_not1_b32 exec_lo, exec_lo, s26
s_cbranch_execz .LBB0_26
.LBB0_17:
v_add_nc_u32_e32 v1, s24, v3
s_mov_b32 s27, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 2, v[1:2]
v_add_co_u32 v7, vcc_lo, s6, v5
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v6, vcc_lo
global_load_b32 v1, v[7:8], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v1, v23
s_cbranch_execz .LBB0_16
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s28, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[9:10], 2, v[3:4]
v_add_co_u32 v9, vcc_lo, s12, v9
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v10, vcc_lo, s13, v10, vcc_lo
global_load_b64 v[11:12], v[9:10], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v11, v12
s_cbranch_execz .LBB0_24
v_add_co_u32 v13, vcc_lo, s8, v5
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v6, vcc_lo
v_add_co_u32 v15, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v16, vcc_lo, s11, v6, vcc_lo
s_mov_b32 s29, 0
s_branch .LBB0_21
.LBB0_20:
s_or_b32 exec_lo, exec_lo, s30
global_load_b32 v1, v[9:10], off offset:4
v_add_nc_u32_e32 v11, 1, v11
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_ge_i32_e32 vcc_lo, v11, v1
s_or_b32 s29, vcc_lo, s29
s_and_not1_b32 exec_lo, exec_lo, s29
s_cbranch_execz .LBB0_24
.LBB0_21:
v_ashrrev_i32_e32 v12, 31, v11
s_mov_b32 s30, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[17:18], 2, v[11:12]
v_add_co_u32 v17, vcc_lo, s14, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_add_co_ci_u32_e32 v18, vcc_lo, s15, v18, vcc_lo
global_load_b32 v1, v[17:18], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, s24, v1
v_lshlrev_b64 v[17:18], 2, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v19, vcc_lo, s6, v17
v_add_co_ci_u32_e32 v20, vcc_lo, s7, v18, vcc_lo
s_clause 0x1
global_load_b32 v1, v[19:20], off
global_load_b32 v4, v[7:8], off
s_waitcnt vmcnt(1)
v_add_nc_u32_e32 v1, 1, v1
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e64 v1, v4
s_cbranch_execz .LBB0_20
v_add_co_u32 v19, vcc_lo, s8, v17
v_add_co_ci_u32_e32 v20, vcc_lo, s9, v18, vcc_lo
v_add_co_u32 v17, vcc_lo, s10, v17
s_clause 0x1
global_load_b32 v1, v[13:14], off
global_load_b32 v4, v[19:20], off
v_add_co_ci_u32_e32 v18, vcc_lo, s11, v18, vcc_lo
s_mov_b32 s31, 0
s_waitcnt vmcnt(1)
v_cvt_f64_i32_e32 v[24:25], v1
s_waitcnt vmcnt(0)
v_cvt_f64_i32_e32 v[26:27], v4
global_load_b32 v1, v[15:16], off
v_div_scale_f64 v[28:29], null, v[24:25], v[24:25], v[26:27]
v_div_scale_f64 v[34:35], vcc_lo, v[26:27], v[24:25], v[26:27]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[19:20], v[28:29]
s_waitcnt_depctr 0xfff
v_fma_f64 v[30:31], -v[28:29], v[19:20], 1.0
v_fma_f64 v[30:31], v[19:20], v[30:31], v[19:20]
global_load_b32 v20, v[17:18], off
v_fma_f64 v[32:33], -v[28:29], v[30:31], 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[30:31], v[30:31], v[32:33], v[30:31]
v_mul_f64 v[32:33], v[34:35], v[30:31]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_fma_f64 v[28:29], -v[28:29], v[32:33], v[34:35]
s_waitcnt vmcnt(1)
v_add_f32_e32 v1, 1.0, v1
v_div_fmas_f64 v[28:29], v[28:29], v[30:31], v[32:33]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_div_fixup_f64 v[24:25], v[28:29], v[24:25], v[26:27]
v_cvt_f64_f32_e32 v[26:27], v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[24:25], v[24:25], v[26:27]
v_cvt_f32_f64_e32 v1, v[24:25]
.LBB0_23:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v19, v20, v1
global_atomic_cmpswap_b32 v4, v[17:18], v[19:20], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v4, v20
v_mov_b32_e32 v20, v4
s_or_b32 s31, vcc_lo, s31
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s31
s_cbranch_execnz .LBB0_23
s_branch .LBB0_20
.LBB0_24:
s_or_b32 exec_lo, exec_lo, s28
v_add_nc_u32_e32 v7, s25, v3
v_add_co_u32 v9, vcc_lo, s10, v5
v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v8, 31, v7
s_mov_b32 s28, 0
v_lshlrev_b64 v[7:8], 2, v[7:8]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s4, v7
v_add_co_ci_u32_e32 v5, vcc_lo, s5, v8, vcc_lo
global_load_b32 v1, v[9:10], off
global_load_b32 v7, v[4:5], off
s_waitcnt vmcnt(1)
v_mul_f32_e32 v1, 0.5, v1
.LBB0_25:
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_add_f32_e32 v6, v7, v1
global_atomic_cmpswap_b32 v6, v[4:5], v[6:7], off glc
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v6, v7
v_mov_b32_e32 v7, v6
s_or_b32 s28, vcc_lo, s28
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s28
s_cbranch_execnz .LBB0_25
s_branch .LBB0_16
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_12
v_add_nc_u32_e32 v1, -1, v23
ds_store_b32 v2, v1
s_branch .LBB0_12
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s0
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
ds_load_b32 v1, v2 offset:4
s_waitcnt lgkmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v1
s_cbranch_vccz .LBB0_6
.LBB0_29:
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_31
ds_store_b32 v2, v2 offset:4
.LBB0_31:
s_or_b32 exec_lo, exec_lo, s0
s_and_saveexec_b32 s17, s3
s_cbranch_execz .LBB0_43
ds_load_b32 v15, v2
s_load_b32 s0, s[18:19], 0xc
s_mov_b32 s27, 0
s_waitcnt lgkmcnt(0)
v_dual_mov_b32 v3, v0 :: v_dual_add_nc_u32 v16, 1, v15
s_and_b32 s26, s0, 0xffff
s_branch .LBB0_34
.LBB0_33:
s_or_b32 exec_lo, exec_lo, s28
v_add_nc_u32_e32 v3, s26, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_cmp_le_i32_e32 vcc_lo, s20, v3
s_or_b32 s27, vcc_lo, s27
s_and_not1_b32 exec_lo, exec_lo, s27
s_cbranch_execz .LBB0_43
.LBB0_34:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v4, 31, v3
s_mov_b32 s28, exec_lo
v_lshlrev_b64 v[4:5], 2, v[3:4]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v4, vcc_lo, s12, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s13, v5, vcc_lo
global_load_b64 v[6:7], v[4:5], off
s_waitcnt vmcnt(0)
v_cmpx_lt_i32_e64 v6, v7
s_cbranch_execz .LBB0_33
v_add_nc_u32_e32 v1, s24, v3
v_ashrrev_i32_e32 v7, 31, v6
s_mov_b32 s29, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[9:10], 2, v[1:2]
v_lshlrev_b64 v[11:12], 2, v[6:7]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v8, vcc_lo, s7, v10, vcc_lo
v_add_co_u32 v9, vcc_lo, s8, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
v_add_co_u32 v11, vcc_lo, s14, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s15, v12, vcc_lo
s_branch .LBB0_37
.LBB0_36:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v1, v[4:5], off offset:4
v_add_nc_u32_e32 v6, 1, v6
v_add_co_u32 v11, s0, v11, 4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e64 v12, s0, 0, v12, s0
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v6, v1
s_or_b32 s29, vcc_lo, s29
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s29
s_cbranch_execz .LBB0_33
.LBB0_37:
global_load_b32 v1, v[11:12], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, s24, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[1:2]
v_add_co_u32 v13, vcc_lo, s6, v13
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v14, vcc_lo, s7, v14, vcc_lo
global_load_b32 v1, v[13:14], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v1, v15
s_cbranch_execz .LBB0_40
global_load_b32 v1, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, -1, v1
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_40
global_store_b32 v[7:8], v16, off
ds_store_b32 v2, v22 offset:4
.LBB0_40:
s_or_b32 exec_lo, exec_lo, s0
global_load_b32 v1, v[11:12], off
s_mov_b32 s0, exec_lo
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, s24, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[13:14], 2, v[1:2]
v_add_co_u32 v17, vcc_lo, s6, v13
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v14, vcc_lo
global_load_b32 v1, v[17:18], off
s_waitcnt vmcnt(0)
v_cmpx_eq_u32_e64 v1, v15
s_cbranch_execz .LBB0_36
global_load_b32 v1, v[7:8], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, v1, v16
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_36
v_add_co_u32 v13, vcc_lo, s8, v13
v_add_co_ci_u32_e32 v14, vcc_lo, s9, v14, vcc_lo
s_clause 0x1
global_load_b32 v1, v[13:14], off
global_load_b32 v13, v[9:10], off
s_waitcnt vmcnt(1)
v_cvt_f32_i32_e32 v1, v1
s_waitcnt vmcnt(0)
v_cvt_f32_i32_e32 v13, v13
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v1, v1, v13
v_cvt_i32_f32_e32 v1, v1
global_store_b32 v[9:10], v1, off
s_branch .LBB0_36
.LBB0_43:
s_or_b32 exec_lo, exec_lo, s17
s_and_saveexec_b32 s0, s2
s_cbranch_execz .LBB0_28
ds_load_b32 v1, v2
s_waitcnt lgkmcnt(0)
v_add_nc_u32_e32 v1, 1, v1
ds_store_b32 v2, v1
s_branch .LBB0_28
.LBB0_45:
s_and_not1_b32 vcc_lo, exec_lo, s23
s_mov_b32 s0, s24
s_mov_b32 s17, s20
s_cbranch_vccnz .LBB0_2
.p2align 6
.LBB0_46:
s_lshl_b64 s[26:27], s[0:1], 2
v_mov_b32_e32 v1, -1
s_add_u32 s28, s6, s26
s_addc_u32 s29, s7, s27
s_add_u32 s30, s8, s26
s_addc_u32 s31, s9, s27
v_mov_b32_e32 v3, 0
s_add_u32 s26, s10, s26
s_addc_u32 s27, s11, s27
s_add_i32 s17, s17, -1
s_add_i32 s0, s0, 1
s_cmp_eq_u32 s17, 0
s_clause 0x2
global_store_b32 v2, v1, s[28:29]
global_store_b32 v2, v3, s[30:31]
global_store_b32 v2, v3, s[26:27]
s_cbranch_scc0 .LBB0_46
s_branch .LBB0_2
.LBB0_47:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11cent_kernelPfPiS0_S_S0_S0_i
.amdhsa_group_segment_fixed_size 8
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 312
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 36
.amdhsa_next_free_sgpr 36
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11cent_kernelPfPiS0_S_S0_S0_i, .Lfunc_end0-_Z11cent_kernelPfPiS0_S_S0_S0_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: by_value
- .offset: 56
.size: 4
.value_kind: hidden_block_count_x
- .offset: 60
.size: 4
.value_kind: hidden_block_count_y
- .offset: 64
.size: 4
.value_kind: hidden_block_count_z
- .offset: 68
.size: 2
.value_kind: hidden_group_size_x
- .offset: 70
.size: 2
.value_kind: hidden_group_size_y
- .offset: 72
.size: 2
.value_kind: hidden_group_size_z
- .offset: 74
.size: 2
.value_kind: hidden_remainder_x
- .offset: 76
.size: 2
.value_kind: hidden_remainder_y
- .offset: 78
.size: 2
.value_kind: hidden_remainder_z
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 112
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 120
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8
.kernarg_segment_align: 8
.kernarg_segment_size: 312
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11cent_kernelPfPiS0_S_S0_S0_i
.private_segment_fixed_size: 0
.sgpr_count: 38
.sgpr_spill_count: 0
.symbol: _Z11cent_kernelPfPiS0_S_S0_S0_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 36
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include<stdio.h>
#include<stdlib.h>
#include <stdint.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <time.h>
#include <iomanip>
#include <iostream>
using namespace std;
struct BITMAPFILEHEADER{
uint8_t type[2];
uint32_t size;
uint16_t reserved1;
uint16_t reserved2;
uint32_t offsetbits;
} __attribute__ ((packed));
struct BITMAPINFOHEADER{
uint32_t size;
uint32_t width;
uint32_t height;
uint16_t planes;
uint16_t bitcount;
uint32_t compression;
uint32_t sizeimage;
long xpelspermeter;
long ypelspermeter;
uint32_t colorsused;
uint32_t colorsimportant;
} __attribute__ ((packed));
struct myRGB{
uint8_t blue;
uint8_t green;
uint8_t red;
};
struct grayStruct{
uint8_t B;
uint8_t G;
uint8_t R;
};
__global__ void kernel(myRGB* input, grayStruct* gray,int w,int h, int chunksize)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalsize = w*h;
if( idx < totalsize)
for( int i = idx*chunksize ; i< idx*chunksize+chunksize && i < totalsize; i++)
{
int graypixel = (int)(0.33* input[i].red + 0.33* input[i].green + 0.33* input[i].blue);
gray[i].R = graypixel;gray[i].G = graypixel;gray[i].B = graypixel;
}
}
int main(int argc, char* argv[])
{
clock_t start = clock();
BITMAPFILEHEADER source_head;
BITMAPINFOHEADER source_info;
FILE *in;
FILE *out;
if(!(in=fopen(argv[1],"rb")))
{
printf("\ncan not open file");
exit(-1);
}
out=fopen("out_cuda.bmp","wb");
fread(&source_head,sizeof(struct BITMAPFILEHEADER),1,in);
fread(&source_info,sizeof(struct BITMAPINFOHEADER),1,in);
int total_pixel = source_info.width * source_info.height;
myRGB* h_pixel;
h_pixel = (myRGB*) malloc (sizeof(myRGB)*total_pixel);
fread(h_pixel,sizeof(myRGB),total_pixel,in);
myRGB* d_pixel;
cudaMalloc((void **)&d_pixel, total_pixel*sizeof(myRGB));
cudaMemcpy(d_pixel, h_pixel,total_pixel*sizeof(myRGB), cudaMemcpyHostToDevice);
grayStruct* d_gray;
cudaMalloc( (void**) &d_gray, total_pixel*sizeof(grayStruct));
cudaMemset(d_gray,255,total_pixel*sizeof(grayStruct));
const int BLOCK_SIZE = atoi(argv[2]);
const int THREAD_SIZE = atoi(argv[3]);
int chunksize= ceil( (double)total_pixel/(BLOCK_SIZE*THREAD_SIZE));
cout<< "Chunk Size: " << chunksize<< endl;
kernel <<<BLOCK_SIZE ,THREAD_SIZE >>> (d_pixel, d_gray, source_info.width, source_info.height, chunksize);
fwrite(&source_head,sizeof(struct BITMAPFILEHEADER),1,out);
fwrite(&source_info,sizeof(struct BITMAPINFOHEADER),1,out);
cudaDeviceSynchronize();
grayStruct* h_gray = (grayStruct*) malloc (total_pixel*sizeof(grayStruct));
cudaMemcpy(h_gray, d_gray, total_pixel*sizeof(grayStruct), cudaMemcpyDeviceToHost);
fwrite(h_gray,sizeof(grayStruct),total_pixel,out);
fclose(in);
fclose(out);
clock_t end = clock();
double t_time = (end - start)/(double)CLOCKS_PER_SEC;
cout << "Time: " << std::setprecision(9) << t_time << endl;
return 0;
} | code for sm_80
Function : _Z6kernelP5myRGBP10grayStructiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a24 */
/* 0x000fe400078e02ff */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fc600078e00ff */
/*00a0*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fc8000bf06270 */
/*00b0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R0, R2.reuse, c[0x0][0x178], RZ ; /* 0x00005e0002007a10 */
/* 0x040fe20007ffe0ff */
/*00e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*0100*/ BSSY B0, 0x380 ; /* 0x0000027000007945 */
/* 0x000fe60003800000 */
/*0110*/ IMNMX R5, R0, R3, !PT ; /* 0x0000000300057217 */
/* 0x000fe40007800200 */
/*0120*/ IADD3 R3, R2, -UR4, RZ ; /* 0x8000000402037c10 */
/* 0x000fc6000fffe0ff */
/*0130*/ IMAD.IADD R4, R2, 0x1, -R5 ; /* 0x0000000102047824 */
/* 0x000fca00078e0a05 */
/*0140*/ IMNMX.U32 R4, R3, R4, !PT ; /* 0x0000000403047217 */
/* 0x000fc80007800000 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R4, -0x4, PT ; /* 0xfffffffc0400780c */
/* 0x000fe20003f04070 */
/*0160*/ IMAD.MOV R3, RZ, RZ, -R4 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0a04 */
/*0170*/ LOP3.LUT P1, R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fda000782c0ff */
/*0180*/ @!P1 BRA 0x370 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.WIDE R4, R2, R7, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0207 */
/*01b0*/ IMAD.WIDE R6, R2, R7, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fe200078e0207 */
/*01c0*/ IADD3 R4, P1, R4, 0x2, RZ ; /* 0x0000000204047810 */
/* 0x000fc80007f3e0ff */
/*01d0*/ IADD3 R6, P2, R6, 0x2, RZ ; /* 0x0000000206067810 */
/* 0x000fe20007f5e0ff */
/*01e0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fc800008e0605 */
/*01f0*/ IMAD.X R15, RZ, RZ, R7, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400010e0607 */
/*0200*/ LDG.E.U8 R14, [R4.64+-0x1] ; /* 0xffffff06040e7981 */
/* 0x0010a8000c1e1100 */
/*0210*/ LDG.E.U8 R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x0000e8000c1e1100 */
/*0220*/ LDG.E.U8 R12, [R4.64+-0x2] ; /* 0xfffffe06040c7981 */
/* 0x000122000c1e1100 */
/*0230*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0240*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc40007ffe0ff */
/*0250*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f25270 */
/*0260*/ IADD3 R4, P2, R4, 0x3, RZ ; /* 0x0000000304047810 */
/* 0x001fca0007f5e0ff */
/*0270*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0280*/ I2F.F64.U16 R10, R14 ; /* 0x0000000e000a7312 */
/* 0x004e300000101800 */
/*0290*/ I2F.F64.U16 R8, R7 ; /* 0x0000000700087312 */
/* 0x008e700000101800 */
/*02a0*/ I2F.F64.U16 R12, R12 ; /* 0x0000000c000c7312 */
/* 0x010ea20000101800 */
/*02b0*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x001e4c0000000000 */
/*02c0*/ DFMA R8, R8, c[0x2][0x0], R10 ; /* 0x0080000008087a2b */
/* 0x002e8c000000000a */
/*02d0*/ DFMA R8, R12, c[0x2][0x0], R8 ; /* 0x008000000c087a2b */
/* 0x004e0c0000000008 */
/*02e0*/ F2I.F64.TRUNC R11, R8 ; /* 0x00000008000b7311 */
/* 0x001064000030d100 */
/*02f0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0006 */
/*0300*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fc600078e000f */
/*0310*/ IADD3 R6, P3, R8, 0x3, RZ ; /* 0x0000000308067810 */
/* 0x000fe40007f7e0ff */
/*0320*/ STG.E.U8 [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0021e6000c101106 */
/*0330*/ IMAD.X R15, RZ, RZ, R9, P3 ; /* 0x000000ffff0f7224 */
/* 0x000fe200018e0609 */
/*0340*/ STG.E.U8 [R8.64+-0x1], R11 ; /* 0xffffff0b08007986 */
/* 0x0001e8000c101106 */
/*0350*/ STG.E.U8 [R8.64+-0x2], R11 ; /* 0xfffffe0b08007986 */
/* 0x0001e2000c101106 */
/*0360*/ @P1 BRA 0x200 ; /* 0xfffffe9000001947 */
/* 0x000fea000383ffff */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0390*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3 ; /* 0x00000003ff0f7424 */
/* 0x000fc800078e00ff */
/*03a0*/ IMAD.WIDE R4, R2, R15, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e020f */
/*03b0*/ LDG.E.U8 R12, [R4.64+0x1] ; /* 0x00000106040c7981 */
/* 0x000ea8000c1e1100 */
/*03c0*/ LDG.E.U8 R3, [R4.64+0x2] ; /* 0x0000020604037981 */
/* 0x000ee8000c1e1100 */
/*03d0*/ LDG.E.U8 R13, [R4.64] ; /* 0x00000006040d7981 */
/* 0x000f22000c1e1100 */
/*03e0*/ I2F.F64.U16 R8, R12 ; /* 0x0000000c00087312 */
/* 0x005e300000101800 */
/*03f0*/ I2F.F64.U16 R6, R3 ; /* 0x0000000300067312 */
/* 0x008e700000101800 */
/*0400*/ I2F.F64.U16 R10, R13 ; /* 0x0000000d000a7312 */
/* 0x010ea20000101800 */
/*0410*/ DMUL R8, R8, c[0x2][0x0] ; /* 0x0080000008087a28 */
/* 0x001e4c0000000000 */
/*0420*/ DFMA R6, R6, c[0x2][0x0], R8 ; /* 0x0080000006067a2b */
/* 0x002e8c0000000008 */
/*0430*/ DFMA R10, R10, c[0x2][0x0], R6 ; /* 0x008000000a0a7a2b */
/* 0x0040640000000006 */
/*0440*/ IMAD.WIDE R6, R2, R15, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x001fd000078e020f */
/*0450*/ F2I.F64.TRUNC R11, R10 ; /* 0x0000000a000b7311 */
/* 0x002e24000030d100 */
/*0460*/ STG.E.U8 [R6.64+0x2], R11 ; /* 0x0000020b06007986 */
/* 0x001fe8000c101106 */
/*0470*/ STG.E.U8 [R6.64+0x1], R11 ; /* 0x0000010b06007986 */
/* 0x000fe8000c101106 */
/*0480*/ STG.E.U8 [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101106 */
/*0490*/ LDG.E.U8 R16, [R4.64+0x4] ; /* 0x0000040604107981 */
/* 0x000ea8000c1e1100 */
/*04a0*/ LDG.E.U8 R3, [R4.64+0x5] ; /* 0x0000050604037981 */
/* 0x000ee8000c1e1100 */
/*04b0*/ LDG.E.U8 R14, [R4.64+0x3] ; /* 0x00000306040e7981 */
/* 0x000f22000c1e1100 */
/*04c0*/ I2F.F64.U16 R12, R16 ; /* 0x00000010000c7312 */
/* 0x004e700000101800 */
/*04d0*/ I2F.F64.U16 R8, R3 ; /* 0x0000000300087312 */
/* 0x008eb00000101800 */
/*04e0*/ I2F.F64.U16 R14, R14 ; /* 0x0000000e000e7312 */
/* 0x010ee20000101800 */
/*04f0*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x002e8c0000000000 */
/*0500*/ DFMA R8, R8, c[0x2][0x0], R12 ; /* 0x0080000008087a2b */
/* 0x004ecc000000000c */
/*0510*/ DFMA R8, R14, c[0x2][0x0], R8 ; /* 0x008000000e087a2b */
/* 0x008e540000000008 */
/*0520*/ F2I.F64.TRUNC R9, R8 ; /* 0x0000000800097311 */
/* 0x002e64000030d100 */
/*0530*/ STG.E.U8 [R6.64+0x5], R9 ; /* 0x0000050906007986 */
/* 0x002fe8000c101106 */
/*0540*/ STG.E.U8 [R6.64+0x4], R9 ; /* 0x0000040906007986 */
/* 0x000fe8000c101106 */
/*0550*/ STG.E.U8 [R6.64+0x3], R9 ; /* 0x0000030906007986 */
/* 0x0003e8000c101106 */
/*0560*/ LDG.E.U8 R17, [R4.64+0x7] ; /* 0x0000070604117981 */
/* 0x000ea8000c1e1100 */
/*0570*/ LDG.E.U8 R16, [R4.64+0x8] ; /* 0x0000080604107981 */
/* 0x000e28000c1e1100 */
/*0580*/ LDG.E.U8 R15, [R4.64+0x6] ; /* 0x00000606040f7981 */
/* 0x000ee2000c1e1100 */
/*0590*/ I2F.F64.U16 R12, R17 ; /* 0x00000011000c7312 */
/* 0x004eb00000101800 */
/*05a0*/ I2F.F64.U16 R10, R16 ; /* 0x00000010000a7312 */
/* 0x001e300000101800 */
/*05b0*/ I2F.F64.U16 R14, R15 ; /* 0x0000000f000e7312 */
/* 0x008ee20000101800 */
/*05c0*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x004e0c0000000000 */
/*05d0*/ DFMA R10, R10, c[0x2][0x0], R12 ; /* 0x008000000a0a7a2b */
/* 0x001ecc000000000c */
/*05e0*/ DFMA R10, R14, c[0x2][0x0], R10 ; /* 0x008000000e0a7a2b */
/* 0x008e14000000000a */
/*05f0*/ F2I.F64.TRUNC R11, R10 ; /* 0x0000000a000b7311 */
/* 0x001e24000030d100 */
/*0600*/ STG.E.U8 [R6.64+0x8], R11 ; /* 0x0000080b06007986 */
/* 0x0011e8000c101106 */
/*0610*/ STG.E.U8 [R6.64+0x7], R11 ; /* 0x0000070b06007986 */
/* 0x0001e8000c101106 */
/*0620*/ STG.E.U8 [R6.64+0x6], R11 ; /* 0x0000060b06007986 */
/* 0x0001e8000c101106 */
/*0630*/ LDG.E.U8 R18, [R4.64+0xa] ; /* 0x00000a0604127981 */
/* 0x000ea8000c1e1100 */
/*0640*/ LDG.E.U8 R3, [R4.64+0xb] ; /* 0x00000b0604037981 */
/* 0x000e68000c1e1100 */
/*0650*/ LDG.E.U8 R14, [R4.64+0x9] ; /* 0x00000906040e7981 */
/* 0x000ee2000c1e1100 */
/*0660*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.GE.AND P0, PT, R2.reuse, R0, PT ; /* 0x000000000200720c */
/* 0x040fe40003f06270 */
/*0680*/ ISETP.LT.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe2000bf21270 */
/*0690*/ I2F.F64.U16 R12, R18 ; /* 0x00000012000c7312 */
/* 0x004eb00000101800 */
/*06a0*/ I2F.F64.U16 R8, R3 ; /* 0x0000000300087312 */
/* 0x002e700000101800 */
/*06b0*/ I2F.F64.U16 R14, R14 ; /* 0x0000000e000e7312 */
/* 0x008ee20000101800 */
/*06c0*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x004e4c0000000000 */
/*06d0*/ DFMA R8, R8, c[0x2][0x0], R12 ; /* 0x0080000008087a2b */
/* 0x002ecc000000000c */
/*06e0*/ DFMA R8, R14, c[0x2][0x0], R8 ; /* 0x008000000e087a2b */
/* 0x008e540000000008 */
/*06f0*/ F2I.F64.TRUNC R9, R8 ; /* 0x0000000800097311 */
/* 0x002e64000030d100 */
/*0700*/ STG.E.U8 [R6.64+0xb], R9 ; /* 0x00000b0906007986 */
/* 0x0021e8000c101106 */
/*0710*/ STG.E.U8 [R6.64+0xa], R9 ; /* 0x00000a0906007986 */
/* 0x0001e8000c101106 */
/*0720*/ STG.E.U8 [R6.64+0x9], R9 ; /* 0x0000090906007986 */
/* 0x0001e2000c101106 */
/*0730*/ @!P0 BRA P1, 0x390 ; /* 0xfffffc5000008947 */
/* 0x000fea000083ffff */
/*0740*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0750*/ BRA 0x750; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include<stdio.h>
#include<stdlib.h>
#include <stdint.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <time.h>
#include <iomanip>
#include <iostream>
using namespace std;
struct BITMAPFILEHEADER{
uint8_t type[2];
uint32_t size;
uint16_t reserved1;
uint16_t reserved2;
uint32_t offsetbits;
} __attribute__ ((packed));
struct BITMAPINFOHEADER{
uint32_t size;
uint32_t width;
uint32_t height;
uint16_t planes;
uint16_t bitcount;
uint32_t compression;
uint32_t sizeimage;
long xpelspermeter;
long ypelspermeter;
uint32_t colorsused;
uint32_t colorsimportant;
} __attribute__ ((packed));
struct myRGB{
uint8_t blue;
uint8_t green;
uint8_t red;
};
struct grayStruct{
uint8_t B;
uint8_t G;
uint8_t R;
};
__global__ void kernel(myRGB* input, grayStruct* gray,int w,int h, int chunksize)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalsize = w*h;
if( idx < totalsize)
for( int i = idx*chunksize ; i< idx*chunksize+chunksize && i < totalsize; i++)
{
int graypixel = (int)(0.33* input[i].red + 0.33* input[i].green + 0.33* input[i].blue);
gray[i].R = graypixel;gray[i].G = graypixel;gray[i].B = graypixel;
}
}
int main(int argc, char* argv[])
{
clock_t start = clock();
BITMAPFILEHEADER source_head;
BITMAPINFOHEADER source_info;
FILE *in;
FILE *out;
if(!(in=fopen(argv[1],"rb")))
{
printf("\ncan not open file");
exit(-1);
}
out=fopen("out_cuda.bmp","wb");
fread(&source_head,sizeof(struct BITMAPFILEHEADER),1,in);
fread(&source_info,sizeof(struct BITMAPINFOHEADER),1,in);
int total_pixel = source_info.width * source_info.height;
myRGB* h_pixel;
h_pixel = (myRGB*) malloc (sizeof(myRGB)*total_pixel);
fread(h_pixel,sizeof(myRGB),total_pixel,in);
myRGB* d_pixel;
cudaMalloc((void **)&d_pixel, total_pixel*sizeof(myRGB));
cudaMemcpy(d_pixel, h_pixel,total_pixel*sizeof(myRGB), cudaMemcpyHostToDevice);
grayStruct* d_gray;
cudaMalloc( (void**) &d_gray, total_pixel*sizeof(grayStruct));
cudaMemset(d_gray,255,total_pixel*sizeof(grayStruct));
const int BLOCK_SIZE = atoi(argv[2]);
const int THREAD_SIZE = atoi(argv[3]);
int chunksize= ceil( (double)total_pixel/(BLOCK_SIZE*THREAD_SIZE));
cout<< "Chunk Size: " << chunksize<< endl;
kernel <<<BLOCK_SIZE ,THREAD_SIZE >>> (d_pixel, d_gray, source_info.width, source_info.height, chunksize);
fwrite(&source_head,sizeof(struct BITMAPFILEHEADER),1,out);
fwrite(&source_info,sizeof(struct BITMAPINFOHEADER),1,out);
cudaDeviceSynchronize();
grayStruct* h_gray = (grayStruct*) malloc (total_pixel*sizeof(grayStruct));
cudaMemcpy(h_gray, d_gray, total_pixel*sizeof(grayStruct), cudaMemcpyDeviceToHost);
fwrite(h_gray,sizeof(grayStruct),total_pixel,out);
fclose(in);
fclose(out);
clock_t end = clock();
double t_time = (end - start)/(double)CLOCKS_PER_SEC;
cout << "Time: " << std::setprecision(9) << t_time << endl;
return 0;
} | .file "tmpxft_00138cc5_00000000-6_grayCUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii
.type _Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii, @function
_Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii:
.LFB3974:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelP5myRGBP10grayStructiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3974:
.size _Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii, .-_Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii
.globl _Z6kernelP5myRGBP10grayStructiii
.type _Z6kernelP5myRGBP10grayStructiii, @function
_Z6kernelP5myRGBP10grayStructiii:
.LFB3975:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3975:
.size _Z6kernelP5myRGBP10grayStructiii, .-_Z6kernelP5myRGBP10grayStructiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "\ncan not open file"
.LC2:
.string "wb"
.LC3:
.string "out_cuda.bmp"
.LC7:
.string "Chunk Size: "
.LC9:
.string "Time: "
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %r15
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, 8(%rsp)
movq 8(%r15), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L17
movq %rax, %rbp
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
leaq 122(%rsp), %rdi
movq %rbp, %r8
movl $1, %ecx
movl $14, %edx
movl $14, %esi
call __fread_chk@PLT
leaq 64(%rsp), %rdi
movq %rbp, %r8
movl $1, %ecx
movl $48, %edx
movl $48, %esi
call __fread_chk@PLT
movl 68(%rsp), %eax
imull 72(%rsp), %eax
movl %eax, 4(%rsp)
movslq %eax, %r13
leaq 0(%r13,%r13,2), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %r8
movq %r13, %rcx
movl $3, %edx
movq %rbx, %rsi
movq %rax, %rdi
call __fread_chk@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $255, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movq 16(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq 24(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
pxor %xmm0, %xmm0
cvtsi2sdl 4(%rsp), %xmm0
imull %r14d, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC10(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L13
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L13:
cvttsd2sil %xmm3, %eax
movl %eax, 4(%rsp)
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 4(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %r15d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %r14d, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
leaq 122(%rsp), %rdi
movq %r12, %rcx
movl $1, %edx
movl $14, %esi
call fwrite@PLT
leaq 64(%rsp), %rdi
movq %r12, %rcx
movl $1, %edx
movl $48, %esi
call fwrite@PLT
call cudaDeviceSynchronize@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, %rcx
movq %r13, %rdx
movl $3, %esi
movq %r14, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
movq %r12, %rdi
call fclose@PLT
call clock@PLT
movq 8(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $9, 8(%rdi,%rax)
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
movl 4(%rsp), %r8d
movl 72(%rsp), %ecx
movl 68(%rsp), %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "_Z6kernelP5myRGBP10grayStructiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3977:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP5myRGBP10grayStructiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3977:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC8:
.long 0
.long 1093567616
.align 8
.LC10:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include<stdio.h>
#include<stdlib.h>
#include <stdint.h>
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <time.h>
#include <iomanip>
#include <iostream>
using namespace std;
struct BITMAPFILEHEADER{
uint8_t type[2];
uint32_t size;
uint16_t reserved1;
uint16_t reserved2;
uint32_t offsetbits;
} __attribute__ ((packed));
struct BITMAPINFOHEADER{
uint32_t size;
uint32_t width;
uint32_t height;
uint16_t planes;
uint16_t bitcount;
uint32_t compression;
uint32_t sizeimage;
long xpelspermeter;
long ypelspermeter;
uint32_t colorsused;
uint32_t colorsimportant;
} __attribute__ ((packed));
struct myRGB{
uint8_t blue;
uint8_t green;
uint8_t red;
};
struct grayStruct{
uint8_t B;
uint8_t G;
uint8_t R;
};
__global__ void kernel(myRGB* input, grayStruct* gray,int w,int h, int chunksize)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalsize = w*h;
if( idx < totalsize)
for( int i = idx*chunksize ; i< idx*chunksize+chunksize && i < totalsize; i++)
{
int graypixel = (int)(0.33* input[i].red + 0.33* input[i].green + 0.33* input[i].blue);
gray[i].R = graypixel;gray[i].G = graypixel;gray[i].B = graypixel;
}
}
int main(int argc, char* argv[])
{
clock_t start = clock();
BITMAPFILEHEADER source_head;
BITMAPINFOHEADER source_info;
FILE *in;
FILE *out;
if(!(in=fopen(argv[1],"rb")))
{
printf("\ncan not open file");
exit(-1);
}
out=fopen("out_cuda.bmp","wb");
fread(&source_head,sizeof(struct BITMAPFILEHEADER),1,in);
fread(&source_info,sizeof(struct BITMAPINFOHEADER),1,in);
int total_pixel = source_info.width * source_info.height;
myRGB* h_pixel;
h_pixel = (myRGB*) malloc (sizeof(myRGB)*total_pixel);
fread(h_pixel,sizeof(myRGB),total_pixel,in);
myRGB* d_pixel;
cudaMalloc((void **)&d_pixel, total_pixel*sizeof(myRGB));
cudaMemcpy(d_pixel, h_pixel,total_pixel*sizeof(myRGB), cudaMemcpyHostToDevice);
grayStruct* d_gray;
cudaMalloc( (void**) &d_gray, total_pixel*sizeof(grayStruct));
cudaMemset(d_gray,255,total_pixel*sizeof(grayStruct));
const int BLOCK_SIZE = atoi(argv[2]);
const int THREAD_SIZE = atoi(argv[3]);
int chunksize= ceil( (double)total_pixel/(BLOCK_SIZE*THREAD_SIZE));
cout<< "Chunk Size: " << chunksize<< endl;
kernel <<<BLOCK_SIZE ,THREAD_SIZE >>> (d_pixel, d_gray, source_info.width, source_info.height, chunksize);
fwrite(&source_head,sizeof(struct BITMAPFILEHEADER),1,out);
fwrite(&source_info,sizeof(struct BITMAPINFOHEADER),1,out);
cudaDeviceSynchronize();
grayStruct* h_gray = (grayStruct*) malloc (total_pixel*sizeof(grayStruct));
cudaMemcpy(h_gray, d_gray, total_pixel*sizeof(grayStruct), cudaMemcpyDeviceToHost);
fwrite(h_gray,sizeof(grayStruct),total_pixel,out);
fclose(in);
fclose(out);
clock_t end = clock();
double t_time = (end - start)/(double)CLOCKS_PER_SEC;
cout << "Time: " << std::setprecision(9) << t_time << endl;
return 0;
} | #include<stdio.h>
#include<stdlib.h>
#include <stdint.h>
#include "hip/hip_runtime.h"
#include <time.h>
#include <iomanip>
#include <iostream>
using namespace std;
struct BITMAPFILEHEADER{
uint8_t type[2];
uint32_t size;
uint16_t reserved1;
uint16_t reserved2;
uint32_t offsetbits;
} __attribute__ ((packed));
struct BITMAPINFOHEADER{
uint32_t size;
uint32_t width;
uint32_t height;
uint16_t planes;
uint16_t bitcount;
uint32_t compression;
uint32_t sizeimage;
long xpelspermeter;
long ypelspermeter;
uint32_t colorsused;
uint32_t colorsimportant;
} __attribute__ ((packed));
struct myRGB{
uint8_t blue;
uint8_t green;
uint8_t red;
};
struct grayStruct{
uint8_t B;
uint8_t G;
uint8_t R;
};
__global__ void kernel(myRGB* input, grayStruct* gray,int w,int h, int chunksize)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalsize = w*h;
if( idx < totalsize)
for( int i = idx*chunksize ; i< idx*chunksize+chunksize && i < totalsize; i++)
{
int graypixel = (int)(0.33* input[i].red + 0.33* input[i].green + 0.33* input[i].blue);
gray[i].R = graypixel;gray[i].G = graypixel;gray[i].B = graypixel;
}
}
int main(int argc, char* argv[])
{
clock_t start = clock();
BITMAPFILEHEADER source_head;
BITMAPINFOHEADER source_info;
FILE *in;
FILE *out;
if(!(in=fopen(argv[1],"rb")))
{
printf("\ncan not open file");
exit(-1);
}
out=fopen("out_cuda.bmp","wb");
fread(&source_head,sizeof(struct BITMAPFILEHEADER),1,in);
fread(&source_info,sizeof(struct BITMAPINFOHEADER),1,in);
int total_pixel = source_info.width * source_info.height;
myRGB* h_pixel;
h_pixel = (myRGB*) malloc (sizeof(myRGB)*total_pixel);
fread(h_pixel,sizeof(myRGB),total_pixel,in);
myRGB* d_pixel;
hipMalloc((void **)&d_pixel, total_pixel*sizeof(myRGB));
hipMemcpy(d_pixel, h_pixel,total_pixel*sizeof(myRGB), hipMemcpyHostToDevice);
grayStruct* d_gray;
hipMalloc( (void**) &d_gray, total_pixel*sizeof(grayStruct));
hipMemset(d_gray,255,total_pixel*sizeof(grayStruct));
const int BLOCK_SIZE = atoi(argv[2]);
const int THREAD_SIZE = atoi(argv[3]);
int chunksize= ceil( (double)total_pixel/(BLOCK_SIZE*THREAD_SIZE));
cout<< "Chunk Size: " << chunksize<< endl;
kernel <<<BLOCK_SIZE ,THREAD_SIZE >>> (d_pixel, d_gray, source_info.width, source_info.height, chunksize);
fwrite(&source_head,sizeof(struct BITMAPFILEHEADER),1,out);
fwrite(&source_info,sizeof(struct BITMAPINFOHEADER),1,out);
hipDeviceSynchronize();
grayStruct* h_gray = (grayStruct*) malloc (total_pixel*sizeof(grayStruct));
hipMemcpy(h_gray, d_gray, total_pixel*sizeof(grayStruct), hipMemcpyDeviceToHost);
fwrite(h_gray,sizeof(grayStruct),total_pixel,out);
fclose(in);
fclose(out);
clock_t end = clock();
double t_time = (end - start)/(double)CLOCKS_PER_SEC;
cout << "Time: " << std::setprecision(9) << t_time << endl;
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include<stdio.h>
#include<stdlib.h>
#include <stdint.h>
#include "hip/hip_runtime.h"
#include <time.h>
#include <iomanip>
#include <iostream>
using namespace std;
struct BITMAPFILEHEADER{
uint8_t type[2];
uint32_t size;
uint16_t reserved1;
uint16_t reserved2;
uint32_t offsetbits;
} __attribute__ ((packed));
struct BITMAPINFOHEADER{
uint32_t size;
uint32_t width;
uint32_t height;
uint16_t planes;
uint16_t bitcount;
uint32_t compression;
uint32_t sizeimage;
long xpelspermeter;
long ypelspermeter;
uint32_t colorsused;
uint32_t colorsimportant;
} __attribute__ ((packed));
struct myRGB{
uint8_t blue;
uint8_t green;
uint8_t red;
};
struct grayStruct{
uint8_t B;
uint8_t G;
uint8_t R;
};
__global__ void kernel(myRGB* input, grayStruct* gray,int w,int h, int chunksize)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalsize = w*h;
if( idx < totalsize)
for( int i = idx*chunksize ; i< idx*chunksize+chunksize && i < totalsize; i++)
{
int graypixel = (int)(0.33* input[i].red + 0.33* input[i].green + 0.33* input[i].blue);
gray[i].R = graypixel;gray[i].G = graypixel;gray[i].B = graypixel;
}
}
int main(int argc, char* argv[])
{
clock_t start = clock();
BITMAPFILEHEADER source_head;
BITMAPINFOHEADER source_info;
FILE *in;
FILE *out;
if(!(in=fopen(argv[1],"rb")))
{
printf("\ncan not open file");
exit(-1);
}
out=fopen("out_cuda.bmp","wb");
fread(&source_head,sizeof(struct BITMAPFILEHEADER),1,in);
fread(&source_info,sizeof(struct BITMAPINFOHEADER),1,in);
int total_pixel = source_info.width * source_info.height;
myRGB* h_pixel;
h_pixel = (myRGB*) malloc (sizeof(myRGB)*total_pixel);
fread(h_pixel,sizeof(myRGB),total_pixel,in);
myRGB* d_pixel;
hipMalloc((void **)&d_pixel, total_pixel*sizeof(myRGB));
hipMemcpy(d_pixel, h_pixel,total_pixel*sizeof(myRGB), hipMemcpyHostToDevice);
grayStruct* d_gray;
hipMalloc( (void**) &d_gray, total_pixel*sizeof(grayStruct));
hipMemset(d_gray,255,total_pixel*sizeof(grayStruct));
const int BLOCK_SIZE = atoi(argv[2]);
const int THREAD_SIZE = atoi(argv[3]);
int chunksize= ceil( (double)total_pixel/(BLOCK_SIZE*THREAD_SIZE));
cout<< "Chunk Size: " << chunksize<< endl;
kernel <<<BLOCK_SIZE ,THREAD_SIZE >>> (d_pixel, d_gray, source_info.width, source_info.height, chunksize);
fwrite(&source_head,sizeof(struct BITMAPFILEHEADER),1,out);
fwrite(&source_info,sizeof(struct BITMAPINFOHEADER),1,out);
hipDeviceSynchronize();
grayStruct* h_gray = (grayStruct*) malloc (total_pixel*sizeof(grayStruct));
hipMemcpy(h_gray, d_gray, total_pixel*sizeof(grayStruct), hipMemcpyDeviceToHost);
fwrite(h_gray,sizeof(grayStruct),total_pixel,out);
fclose(in);
fclose(out);
clock_t end = clock();
double t_time = (end - start)/(double)CLOCKS_PER_SEC;
cout << "Time: " << std::setprecision(9) << t_time << endl;
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelP5myRGBP10grayStructiii
.globl _Z6kernelP5myRGBP10grayStructiii
.p2align 8
.type _Z6kernelP5myRGBP10grayStructiii,@function
_Z6kernelP5myRGBP10grayStructiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_4
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s3, v4
v_min_i32_e32 v5, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[0:1], null, v4, 3, s[0:1]
v_mad_i64_i32 v[2:3], null, v4, 3, s[2:3]
s_mov_b32 s1, 0
s_mov_b32 s3, 0x3fd51eb8
s_mov_b32 s2, 0x51eb851f
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v0, 2
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_clause 0x2
global_load_u8 v6, v[0:1], off offset:-1
global_load_u8 v8, v[0:1], off
global_load_u8 v10, v[0:1], off offset:-2
v_add_nc_u32_e32 v4, 1, v4
v_add_co_u32 v0, vcc_lo, v0, 3
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ge_i32_e32 vcc_lo, v4, v5
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[6:7], v6
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[8:9], v8
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[10:11], v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[6:7], s[2:3]
v_fma_f64 v[6:7], v[8:9], s[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[10:11], s[2:3], v[6:7]
v_cvt_i32_f64_e32 v6, v[6:7]
s_clause 0x2
global_store_b8 v[2:3], v6, off offset:1
global_store_b8 v[2:3], v6, off
global_store_b8 v[2:3], v6, off offset:-1
v_add_co_u32 v2, s0, v2, 3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelP5myRGBP10grayStructiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelP5myRGBP10grayStructiii, .Lfunc_end0-_Z6kernelP5myRGBP10grayStructiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelP5myRGBP10grayStructiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelP5myRGBP10grayStructiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include<stdio.h>
#include<stdlib.h>
#include <stdint.h>
#include "hip/hip_runtime.h"
#include <time.h>
#include <iomanip>
#include <iostream>
using namespace std;
struct BITMAPFILEHEADER{
uint8_t type[2];
uint32_t size;
uint16_t reserved1;
uint16_t reserved2;
uint32_t offsetbits;
} __attribute__ ((packed));
struct BITMAPINFOHEADER{
uint32_t size;
uint32_t width;
uint32_t height;
uint16_t planes;
uint16_t bitcount;
uint32_t compression;
uint32_t sizeimage;
long xpelspermeter;
long ypelspermeter;
uint32_t colorsused;
uint32_t colorsimportant;
} __attribute__ ((packed));
struct myRGB{
uint8_t blue;
uint8_t green;
uint8_t red;
};
struct grayStruct{
uint8_t B;
uint8_t G;
uint8_t R;
};
__global__ void kernel(myRGB* input, grayStruct* gray,int w,int h, int chunksize)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
int totalsize = w*h;
if( idx < totalsize)
for( int i = idx*chunksize ; i< idx*chunksize+chunksize && i < totalsize; i++)
{
int graypixel = (int)(0.33* input[i].red + 0.33* input[i].green + 0.33* input[i].blue);
gray[i].R = graypixel;gray[i].G = graypixel;gray[i].B = graypixel;
}
}
int main(int argc, char* argv[])
{
clock_t start = clock();
BITMAPFILEHEADER source_head;
BITMAPINFOHEADER source_info;
FILE *in;
FILE *out;
if(!(in=fopen(argv[1],"rb")))
{
printf("\ncan not open file");
exit(-1);
}
out=fopen("out_cuda.bmp","wb");
fread(&source_head,sizeof(struct BITMAPFILEHEADER),1,in);
fread(&source_info,sizeof(struct BITMAPINFOHEADER),1,in);
int total_pixel = source_info.width * source_info.height;
myRGB* h_pixel;
h_pixel = (myRGB*) malloc (sizeof(myRGB)*total_pixel);
fread(h_pixel,sizeof(myRGB),total_pixel,in);
myRGB* d_pixel;
hipMalloc((void **)&d_pixel, total_pixel*sizeof(myRGB));
hipMemcpy(d_pixel, h_pixel,total_pixel*sizeof(myRGB), hipMemcpyHostToDevice);
grayStruct* d_gray;
hipMalloc( (void**) &d_gray, total_pixel*sizeof(grayStruct));
hipMemset(d_gray,255,total_pixel*sizeof(grayStruct));
const int BLOCK_SIZE = atoi(argv[2]);
const int THREAD_SIZE = atoi(argv[3]);
int chunksize= ceil( (double)total_pixel/(BLOCK_SIZE*THREAD_SIZE));
cout<< "Chunk Size: " << chunksize<< endl;
kernel <<<BLOCK_SIZE ,THREAD_SIZE >>> (d_pixel, d_gray, source_info.width, source_info.height, chunksize);
fwrite(&source_head,sizeof(struct BITMAPFILEHEADER),1,out);
fwrite(&source_info,sizeof(struct BITMAPINFOHEADER),1,out);
hipDeviceSynchronize();
grayStruct* h_gray = (grayStruct*) malloc (total_pixel*sizeof(grayStruct));
hipMemcpy(h_gray, d_gray, total_pixel*sizeof(grayStruct), hipMemcpyDeviceToHost);
fwrite(h_gray,sizeof(grayStruct),total_pixel,out);
fclose(in);
fclose(out);
clock_t end = clock();
double t_time = (end - start)/(double)CLOCKS_PER_SEC;
cout << "Time: " << std::setprecision(9) << t_time << endl;
return 0;
} | .text
.file "grayCUDA.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelP5myRGBP10grayStructiii # -- Begin function _Z21__device_stub__kernelP5myRGBP10grayStructiii
.p2align 4, 0x90
.type _Z21__device_stub__kernelP5myRGBP10grayStructiii,@function
_Z21__device_stub__kernelP5myRGBP10grayStructiii: # @_Z21__device_stub__kernelP5myRGBP10grayStructiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelP5myRGBP10grayStructiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP5myRGBP10grayStructiii, .Lfunc_end0-_Z21__device_stub__kernelP5myRGBP10grayStructiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
movq 8(%rbp), %rdi
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_12
# %bb.1:
movq %rax, %r14
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, 64(%rsp) # 8-byte Spill
leaq 186(%rsp), %rdi
movl $14, %esi
movl $1, %edx
movq %r14, %rcx
callq fread
leaq 200(%rsp), %rdi
movl $48, %esi
movl $1, %edx
movq %r14, %rcx
callq fread
movl 204(%rsp), %ecx
movl 208(%rsp), %eax
movl %eax, 28(%rsp) # 4-byte Spill
movl %ecx, 32(%rsp) # 4-byte Spill
imull %ecx, %eax
movslq %eax, %r12
leaq (%r12,%r12,2), %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movl $3, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %rcx
callq fread
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movl $255, %esi
movq %r13, %rdx
callq hipMemset
movq 16(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq %r12, 56(%rsp) # 8-byte Spill
cvtsi2sd %r12d, %xmm0
imull %ebx, %eax
cvtsi2sd %eax, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r14
testq %r14, %r14
je .LBB1_13
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_4
# %bb.3:
movzbl 67(%r14), %eax
jmp .LBB1_5
.LBB1_4:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl %ebx, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r15d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 72(%rsp), %r14 # 8-byte Reload
jne .LBB1_7
# %bb.6:
movq 48(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl 32(%rsp), %eax # 4-byte Reload
movl %eax, 44(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
movl %ebp, 36(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6kernelP5myRGBP10grayStructiii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
leaq 186(%rsp), %rdi
movl $14, %esi
movl $1, %edx
movq 64(%rsp), %r15 # 8-byte Reload
movq %r15, %rcx
callq fwrite
leaq 200(%rsp), %rdi
movl $48, %esi
movl $1, %edx
movq %r15, %rcx
callq fwrite
callq hipDeviceSynchronize
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq 16(%rsp), %rsi
movq %rax, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movl $3, %esi
movq %rbx, %rdi
movq 56(%rsp), %rdx # 8-byte Reload
movq %r15, %rcx
callq fwrite
movq %r14, %rdi
callq fclose
movq %r15, %rdi
callq fclose
callq clock
subq 8(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $9, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_13
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i38
cmpb $0, 56(%rbx)
je .LBB1_10
# %bb.9:
movzbl 67(%rbx), %ecx
jmp .LBB1_11
.LBB1_10:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit41
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 304
callq _ZSt16__throw_bad_castv
.LBB1_12:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP5myRGBP10grayStructiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP5myRGBP10grayStructiii,@object # @_Z6kernelP5myRGBP10grayStructiii
.section .rodata,"a",@progbits
.globl _Z6kernelP5myRGBP10grayStructiii
.p2align 3, 0x0
_Z6kernelP5myRGBP10grayStructiii:
.quad _Z21__device_stub__kernelP5myRGBP10grayStructiii
.size _Z6kernelP5myRGBP10grayStructiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\ncan not open file"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "out_cuda.bmp"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "wb"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Chunk Size: "
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time: "
.size .L.str.5, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelP5myRGBP10grayStructiii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP5myRGBP10grayStructiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelP5myRGBP10grayStructiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z6kernelP5myRGBP10grayStructiii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x170] ; /* 0x00005c0000047ab9 */
/* 0x000fe40000000a00 */
/*0030*/ UIMAD UR4, UR5, UR4, URZ ; /* 0x00000004050472a4 */
/* 0x000fe2000f8e023f */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, UR4, PT ; /* 0x0000000400007c0c */
/* 0x000fda000bf06270 */
/*0070*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0080*/ IMAD R2, R0, c[0x0][0x178], RZ ; /* 0x00005e0000027a24 */
/* 0x000fe400078e02ff */
/*0090*/ IMAD.MOV.U32 R0, RZ, RZ, c[0x0][0x178] ; /* 0x00005e00ff007624 */
/* 0x000fc600078e00ff */
/*00a0*/ ISETP.GE.AND P0, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fc8000bf06270 */
/*00b0*/ ISETP.LT.OR P0, PT, R0, 0x1, P0 ; /* 0x000000010000780c */
/* 0x000fda0000701670 */
/*00c0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00d0*/ IADD3 R0, R2.reuse, c[0x0][0x178], RZ ; /* 0x00005e0002007a10 */
/* 0x040fe20007ffe0ff */
/*00e0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ IADD3 R3, R2, 0x1, RZ ; /* 0x0000000102037810 */
/* 0x000fe20007ffe0ff */
/*0100*/ BSSY B0, 0x380 ; /* 0x0000027000007945 */
/* 0x000fe60003800000 */
/*0110*/ IMNMX R5, R0, R3, !PT ; /* 0x0000000300057217 */
/* 0x000fe40007800200 */
/*0120*/ IADD3 R3, R2, -UR4, RZ ; /* 0x8000000402037c10 */
/* 0x000fc6000fffe0ff */
/*0130*/ IMAD.IADD R4, R2, 0x1, -R5 ; /* 0x0000000102047824 */
/* 0x000fca00078e0a05 */
/*0140*/ IMNMX.U32 R4, R3, R4, !PT ; /* 0x0000000403047217 */
/* 0x000fc80007800000 */
/*0150*/ ISETP.GT.U32.AND P0, PT, R4, -0x4, PT ; /* 0xfffffffc0400780c */
/* 0x000fe20003f04070 */
/*0160*/ IMAD.MOV R3, RZ, RZ, -R4 ; /* 0x000000ffff037224 */
/* 0x000fca00078e0a04 */
/*0170*/ LOP3.LUT P1, R3, R3, 0x3, RZ, 0xc0, !PT ; /* 0x0000000303037812 */
/* 0x000fda000782c0ff */
/*0180*/ @!P1 BRA 0x370 ; /* 0x000001e000009947 */
/* 0x000fea0003800000 */
/*0190*/ IMAD.MOV.U32 R7, RZ, RZ, 0x3 ; /* 0x00000003ff077424 */
/* 0x000fc800078e00ff */
/*01a0*/ IMAD.WIDE R4, R2, R7, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fc800078e0207 */
/*01b0*/ IMAD.WIDE R6, R2, R7, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x000fe200078e0207 */
/*01c0*/ IADD3 R4, P1, R4, 0x2, RZ ; /* 0x0000000204047810 */
/* 0x000fc80007f3e0ff */
/*01d0*/ IADD3 R6, P2, R6, 0x2, RZ ; /* 0x0000000206067810 */
/* 0x000fe20007f5e0ff */
/*01e0*/ IMAD.X R5, RZ, RZ, R5, P1 ; /* 0x000000ffff057224 */
/* 0x000fc800008e0605 */
/*01f0*/ IMAD.X R15, RZ, RZ, R7, P2 ; /* 0x000000ffff0f7224 */
/* 0x000fe400010e0607 */
/*0200*/ LDG.E.U8 R14, [R4.64+-0x1] ; /* 0xffffff06040e7981 */
/* 0x0010a8000c1e1100 */
/*0210*/ LDG.E.U8 R7, [R4.64] ; /* 0x0000000604077981 */
/* 0x0000e8000c1e1100 */
/*0220*/ LDG.E.U8 R12, [R4.64+-0x2] ; /* 0xfffffe06040c7981 */
/* 0x000122000c1e1100 */
/*0230*/ IADD3 R3, R3, -0x1, RZ ; /* 0xffffffff03037810 */
/* 0x000fe40007ffe0ff */
/*0240*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc40007ffe0ff */
/*0250*/ ISETP.NE.AND P1, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fe40003f25270 */
/*0260*/ IADD3 R4, P2, R4, 0x3, RZ ; /* 0x0000000304047810 */
/* 0x001fca0007f5e0ff */
/*0270*/ IMAD.X R5, RZ, RZ, R5, P2 ; /* 0x000000ffff057224 */
/* 0x000fe200010e0605 */
/*0280*/ I2F.F64.U16 R10, R14 ; /* 0x0000000e000a7312 */
/* 0x004e300000101800 */
/*0290*/ I2F.F64.U16 R8, R7 ; /* 0x0000000700087312 */
/* 0x008e700000101800 */
/*02a0*/ I2F.F64.U16 R12, R12 ; /* 0x0000000c000c7312 */
/* 0x010ea20000101800 */
/*02b0*/ DMUL R10, R10, c[0x2][0x0] ; /* 0x008000000a0a7a28 */
/* 0x001e4c0000000000 */
/*02c0*/ DFMA R8, R8, c[0x2][0x0], R10 ; /* 0x0080000008087a2b */
/* 0x002e8c000000000a */
/*02d0*/ DFMA R8, R12, c[0x2][0x0], R8 ; /* 0x008000000c087a2b */
/* 0x004e0c0000000008 */
/*02e0*/ F2I.F64.TRUNC R11, R8 ; /* 0x00000008000b7311 */
/* 0x001064000030d100 */
/*02f0*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x001fe400078e0006 */
/*0300*/ IMAD.MOV.U32 R9, RZ, RZ, R15 ; /* 0x000000ffff097224 */
/* 0x000fc600078e000f */
/*0310*/ IADD3 R6, P3, R8, 0x3, RZ ; /* 0x0000000308067810 */
/* 0x000fe40007f7e0ff */
/*0320*/ STG.E.U8 [R8.64], R11 ; /* 0x0000000b08007986 */
/* 0x0021e6000c101106 */
/*0330*/ IMAD.X R15, RZ, RZ, R9, P3 ; /* 0x000000ffff0f7224 */
/* 0x000fe200018e0609 */
/*0340*/ STG.E.U8 [R8.64+-0x1], R11 ; /* 0xffffff0b08007986 */
/* 0x0001e8000c101106 */
/*0350*/ STG.E.U8 [R8.64+-0x2], R11 ; /* 0xfffffe0b08007986 */
/* 0x0001e2000c101106 */
/*0360*/ @P1 BRA 0x200 ; /* 0xfffffe9000001947 */
/* 0x000fea000383ffff */
/*0370*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0380*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0390*/ IMAD.MOV.U32 R15, RZ, RZ, 0x3 ; /* 0x00000003ff0f7424 */
/* 0x000fc800078e00ff */
/*03a0*/ IMAD.WIDE R4, R2, R15, c[0x0][0x160] ; /* 0x0000580002047625 */
/* 0x000fca00078e020f */
/*03b0*/ LDG.E.U8 R12, [R4.64+0x1] ; /* 0x00000106040c7981 */
/* 0x000ea8000c1e1100 */
/*03c0*/ LDG.E.U8 R3, [R4.64+0x2] ; /* 0x0000020604037981 */
/* 0x000ee8000c1e1100 */
/*03d0*/ LDG.E.U8 R13, [R4.64] ; /* 0x00000006040d7981 */
/* 0x000f22000c1e1100 */
/*03e0*/ I2F.F64.U16 R8, R12 ; /* 0x0000000c00087312 */
/* 0x005e300000101800 */
/*03f0*/ I2F.F64.U16 R6, R3 ; /* 0x0000000300067312 */
/* 0x008e700000101800 */
/*0400*/ I2F.F64.U16 R10, R13 ; /* 0x0000000d000a7312 */
/* 0x010ea20000101800 */
/*0410*/ DMUL R8, R8, c[0x2][0x0] ; /* 0x0080000008087a28 */
/* 0x001e4c0000000000 */
/*0420*/ DFMA R6, R6, c[0x2][0x0], R8 ; /* 0x0080000006067a2b */
/* 0x002e8c0000000008 */
/*0430*/ DFMA R10, R10, c[0x2][0x0], R6 ; /* 0x008000000a0a7a2b */
/* 0x0040640000000006 */
/*0440*/ IMAD.WIDE R6, R2, R15, c[0x0][0x168] ; /* 0x00005a0002067625 */
/* 0x001fd000078e020f */
/*0450*/ F2I.F64.TRUNC R11, R10 ; /* 0x0000000a000b7311 */
/* 0x002e24000030d100 */
/*0460*/ STG.E.U8 [R6.64+0x2], R11 ; /* 0x0000020b06007986 */
/* 0x001fe8000c101106 */
/*0470*/ STG.E.U8 [R6.64+0x1], R11 ; /* 0x0000010b06007986 */
/* 0x000fe8000c101106 */
/*0480*/ STG.E.U8 [R6.64], R11 ; /* 0x0000000b06007986 */
/* 0x0001e8000c101106 */
/*0490*/ LDG.E.U8 R16, [R4.64+0x4] ; /* 0x0000040604107981 */
/* 0x000ea8000c1e1100 */
/*04a0*/ LDG.E.U8 R3, [R4.64+0x5] ; /* 0x0000050604037981 */
/* 0x000ee8000c1e1100 */
/*04b0*/ LDG.E.U8 R14, [R4.64+0x3] ; /* 0x00000306040e7981 */
/* 0x000f22000c1e1100 */
/*04c0*/ I2F.F64.U16 R12, R16 ; /* 0x00000010000c7312 */
/* 0x004e700000101800 */
/*04d0*/ I2F.F64.U16 R8, R3 ; /* 0x0000000300087312 */
/* 0x008eb00000101800 */
/*04e0*/ I2F.F64.U16 R14, R14 ; /* 0x0000000e000e7312 */
/* 0x010ee20000101800 */
/*04f0*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x002e8c0000000000 */
/*0500*/ DFMA R8, R8, c[0x2][0x0], R12 ; /* 0x0080000008087a2b */
/* 0x004ecc000000000c */
/*0510*/ DFMA R8, R14, c[0x2][0x0], R8 ; /* 0x008000000e087a2b */
/* 0x008e540000000008 */
/*0520*/ F2I.F64.TRUNC R9, R8 ; /* 0x0000000800097311 */
/* 0x002e64000030d100 */
/*0530*/ STG.E.U8 [R6.64+0x5], R9 ; /* 0x0000050906007986 */
/* 0x002fe8000c101106 */
/*0540*/ STG.E.U8 [R6.64+0x4], R9 ; /* 0x0000040906007986 */
/* 0x000fe8000c101106 */
/*0550*/ STG.E.U8 [R6.64+0x3], R9 ; /* 0x0000030906007986 */
/* 0x0003e8000c101106 */
/*0560*/ LDG.E.U8 R17, [R4.64+0x7] ; /* 0x0000070604117981 */
/* 0x000ea8000c1e1100 */
/*0570*/ LDG.E.U8 R16, [R4.64+0x8] ; /* 0x0000080604107981 */
/* 0x000e28000c1e1100 */
/*0580*/ LDG.E.U8 R15, [R4.64+0x6] ; /* 0x00000606040f7981 */
/* 0x000ee2000c1e1100 */
/*0590*/ I2F.F64.U16 R12, R17 ; /* 0x00000011000c7312 */
/* 0x004eb00000101800 */
/*05a0*/ I2F.F64.U16 R10, R16 ; /* 0x00000010000a7312 */
/* 0x001e300000101800 */
/*05b0*/ I2F.F64.U16 R14, R15 ; /* 0x0000000f000e7312 */
/* 0x008ee20000101800 */
/*05c0*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x004e0c0000000000 */
/*05d0*/ DFMA R10, R10, c[0x2][0x0], R12 ; /* 0x008000000a0a7a2b */
/* 0x001ecc000000000c */
/*05e0*/ DFMA R10, R14, c[0x2][0x0], R10 ; /* 0x008000000e0a7a2b */
/* 0x008e14000000000a */
/*05f0*/ F2I.F64.TRUNC R11, R10 ; /* 0x0000000a000b7311 */
/* 0x001e24000030d100 */
/*0600*/ STG.E.U8 [R6.64+0x8], R11 ; /* 0x0000080b06007986 */
/* 0x0011e8000c101106 */
/*0610*/ STG.E.U8 [R6.64+0x7], R11 ; /* 0x0000070b06007986 */
/* 0x0001e8000c101106 */
/*0620*/ STG.E.U8 [R6.64+0x6], R11 ; /* 0x0000060b06007986 */
/* 0x0001e8000c101106 */
/*0630*/ LDG.E.U8 R18, [R4.64+0xa] ; /* 0x00000a0604127981 */
/* 0x000ea8000c1e1100 */
/*0640*/ LDG.E.U8 R3, [R4.64+0xb] ; /* 0x00000b0604037981 */
/* 0x000e68000c1e1100 */
/*0650*/ LDG.E.U8 R14, [R4.64+0x9] ; /* 0x00000906040e7981 */
/* 0x000ee2000c1e1100 */
/*0660*/ IADD3 R2, R2, 0x4, RZ ; /* 0x0000000402027810 */
/* 0x000fc80007ffe0ff */
/*0670*/ ISETP.GE.AND P0, PT, R2.reuse, R0, PT ; /* 0x000000000200720c */
/* 0x040fe40003f06270 */
/*0680*/ ISETP.LT.AND P1, PT, R2, UR4, PT ; /* 0x0000000402007c0c */
/* 0x000fe2000bf21270 */
/*0690*/ I2F.F64.U16 R12, R18 ; /* 0x00000012000c7312 */
/* 0x004eb00000101800 */
/*06a0*/ I2F.F64.U16 R8, R3 ; /* 0x0000000300087312 */
/* 0x002e700000101800 */
/*06b0*/ I2F.F64.U16 R14, R14 ; /* 0x0000000e000e7312 */
/* 0x008ee20000101800 */
/*06c0*/ DMUL R12, R12, c[0x2][0x0] ; /* 0x008000000c0c7a28 */
/* 0x004e4c0000000000 */
/*06d0*/ DFMA R8, R8, c[0x2][0x0], R12 ; /* 0x0080000008087a2b */
/* 0x002ecc000000000c */
/*06e0*/ DFMA R8, R14, c[0x2][0x0], R8 ; /* 0x008000000e087a2b */
/* 0x008e540000000008 */
/*06f0*/ F2I.F64.TRUNC R9, R8 ; /* 0x0000000800097311 */
/* 0x002e64000030d100 */
/*0700*/ STG.E.U8 [R6.64+0xb], R9 ; /* 0x00000b0906007986 */
/* 0x0021e8000c101106 */
/*0710*/ STG.E.U8 [R6.64+0xa], R9 ; /* 0x00000a0906007986 */
/* 0x0001e8000c101106 */
/*0720*/ STG.E.U8 [R6.64+0x9], R9 ; /* 0x0000090906007986 */
/* 0x0001e2000c101106 */
/*0730*/ @!P0 BRA P1, 0x390 ; /* 0xfffffc5000008947 */
/* 0x000fea000083ffff */
/*0740*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0750*/ BRA 0x750; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z6kernelP5myRGBP10grayStructiii
.globl _Z6kernelP5myRGBP10grayStructiii
.p2align 8
.type _Z6kernelP5myRGBP10grayStructiii,@function
_Z6kernelP5myRGBP10grayStructiii:
s_clause 0x1
s_load_b32 s4, s[0:1], 0x2c
s_load_b64 s[2:3], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s4, s4, 0xffff
s_mul_i32 s2, s3, s2
v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v1
s_cbranch_execz .LBB0_4
s_load_b32 s3, s[0:1], 0x18
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v4, v1, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v0, s3, v4
v_min_i32_e32 v5, s2, v0
s_delay_alu instid0(VALU_DEP_1)
v_cmp_lt_i32_e32 vcc_lo, v4, v5
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_4
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_mad_i64_i32 v[0:1], null, v4, 3, s[0:1]
v_mad_i64_i32 v[2:3], null, v4, 3, s[2:3]
s_mov_b32 s1, 0
s_mov_b32 s3, 0x3fd51eb8
s_mov_b32 s2, 0x51eb851f
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v0, vcc_lo, v0, 2
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v2, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
s_set_inst_prefetch_distance 0x1
.p2align 6
.LBB0_3:
s_clause 0x2
global_load_u8 v6, v[0:1], off offset:-1
global_load_u8 v8, v[0:1], off
global_load_u8 v10, v[0:1], off offset:-2
v_add_nc_u32_e32 v4, 1, v4
v_add_co_u32 v0, vcc_lo, v0, 3
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_3)
v_cmp_ge_i32_e32 vcc_lo, v4, v5
s_or_b32 s1, vcc_lo, s1
s_waitcnt vmcnt(2)
v_cvt_f64_u32_e32 v[6:7], v6
s_waitcnt vmcnt(1)
v_cvt_f64_u32_e32 v[8:9], v8
s_waitcnt vmcnt(0)
v_cvt_f64_u32_e32 v[10:11], v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[6:7], s[2:3]
v_fma_f64 v[6:7], v[8:9], s[2:3], v[6:7]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[6:7], v[10:11], s[2:3], v[6:7]
v_cvt_i32_f64_e32 v6, v[6:7]
s_clause 0x2
global_store_b8 v[2:3], v6, off offset:1
global_store_b8 v[2:3], v6, off
global_store_b8 v[2:3], v6, off offset:-1
v_add_co_u32 v2, s0, v2, 3
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
s_and_not1_b32 exec_lo, exec_lo, s1
s_cbranch_execnz .LBB0_3
.LBB0_4:
s_set_inst_prefetch_distance 0x2
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z6kernelP5myRGBP10grayStructiii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 12
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z6kernelP5myRGBP10grayStructiii, .Lfunc_end0-_Z6kernelP5myRGBP10grayStructiii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z6kernelP5myRGBP10grayStructiii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z6kernelP5myRGBP10grayStructiii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 12
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00138cc5_00000000-6_grayCUDA.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3952:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3952:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii
.type _Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii, @function
_Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii:
.LFB3974:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z6kernelP5myRGBP10grayStructiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3974:
.size _Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii, .-_Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii
.globl _Z6kernelP5myRGBP10grayStructiii
.type _Z6kernelP5myRGBP10grayStructiii, @function
_Z6kernelP5myRGBP10grayStructiii:
.LFB3975:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3975:
.size _Z6kernelP5myRGBP10grayStructiii, .-_Z6kernelP5myRGBP10grayStructiii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "rb"
.LC1:
.string "\ncan not open file"
.LC2:
.string "wb"
.LC3:
.string "out_cuda.bmp"
.LC7:
.string "Chunk Size: "
.LC9:
.string "Time: "
.text
.globl main
.type main, @function
main:
.LFB3949:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $152, %rsp
.cfi_def_cfa_offset 208
movq %rsi, %r15
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
call clock@PLT
movq %rax, 8(%rsp)
movq 8(%r15), %rdi
leaq .LC0(%rip), %rsi
call fopen@PLT
testq %rax, %rax
je .L17
movq %rax, %rbp
leaq .LC2(%rip), %rsi
leaq .LC3(%rip), %rdi
call fopen@PLT
movq %rax, %r12
leaq 122(%rsp), %rdi
movq %rbp, %r8
movl $1, %ecx
movl $14, %edx
movl $14, %esi
call __fread_chk@PLT
leaq 64(%rsp), %rdi
movq %rbp, %r8
movl $1, %ecx
movl $48, %edx
movl $48, %esi
call __fread_chk@PLT
movl 68(%rsp), %eax
imull 72(%rsp), %eax
movl %eax, 4(%rsp)
movslq %eax, %r13
leaq 0(%r13,%r13,2), %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movq %rbp, %r8
movq %r13, %rcx
movl $3, %edx
movq %rbx, %rsi
movq %rax, %rdi
call __fread_chk@PLT
leaq 24(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $255, %esi
movq 32(%rsp), %rdi
call cudaMemset@PLT
movq 16(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movq 24(%r15), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r15
pxor %xmm0, %xmm0
cvtsi2sdl 4(%rsp), %xmm0
imull %r14d, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
divsd %xmm1, %xmm0
movapd %xmm0, %xmm3
movsd .LC10(%rip), %xmm2
movapd %xmm0, %xmm1
andpd %xmm2, %xmm1
movsd .LC4(%rip), %xmm4
ucomisd %xmm1, %xmm4
jbe .L13
cvttsd2siq %xmm0, %rax
pxor %xmm1, %xmm1
cvtsi2sdq %rax, %xmm1
cmpnlesd %xmm1, %xmm3
movsd .LC6(%rip), %xmm4
andpd %xmm4, %xmm3
addsd %xmm1, %xmm3
andnpd %xmm0, %xmm2
orpd %xmm2, %xmm3
.L13:
cvttsd2sil %xmm3, %eax
movl %eax, 4(%rsp)
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl 4(%rsp), %esi
call _ZNSolsEi@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl %r15d, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %r14d, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 52(%rsp), %rdx
movl $1, %ecx
movq 40(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L14:
leaq 122(%rsp), %rdi
movq %r12, %rcx
movl $1, %edx
movl $14, %esi
call fwrite@PLT
leaq 64(%rsp), %rdi
movq %r12, %rcx
movl $1, %edx
movl $48, %esi
call fwrite@PLT
call cudaDeviceSynchronize@PLT
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r14
movl $2, %ecx
movq %rbx, %rdx
movq 32(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %r12, %rcx
movq %r13, %rdx
movl $3, %esi
movq %r14, %rdi
call fwrite@PLT
movq %rbp, %rdi
call fclose@PLT
movq %r12, %rdi
call fclose@PLT
call clock@PLT
movq 8(%rsp), %rcx
subq %rcx, %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC8(%rip), %xmm0
movq %xmm0, %rbx
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq (%rax), %rax
movq -24(%rax), %rax
movq $9, 8(%rdi,%rax)
movq %rbx, %xmm0
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L19
movl $0, %eax
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L18:
movl 4(%rsp), %r8d
movl 72(%rsp), %ecx
movl 68(%rsp), %edx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z46__device_stub__Z6kernelP5myRGBP10grayStructiiiP5myRGBP10grayStructiii
jmp .L14
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3949:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC11:
.string "_Z6kernelP5myRGBP10grayStructiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3977:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _Z6kernelP5myRGBP10grayStructiii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3977:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC4:
.long 0
.long 1127219200
.align 8
.LC6:
.long 0
.long 1072693248
.align 8
.LC8:
.long 0
.long 1093567616
.align 8
.LC10:
.long -1
.long 2147483647
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "grayCUDA.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z21__device_stub__kernelP5myRGBP10grayStructiii # -- Begin function _Z21__device_stub__kernelP5myRGBP10grayStructiii
.p2align 4, 0x90
.type _Z21__device_stub__kernelP5myRGBP10grayStructiii,@function
_Z21__device_stub__kernelP5myRGBP10grayStructiii: # @_Z21__device_stub__kernelP5myRGBP10grayStructiii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z6kernelP5myRGBP10grayStructiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z21__device_stub__kernelP5myRGBP10grayStructiii, .Lfunc_end0-_Z21__device_stub__kernelP5myRGBP10grayStructiii
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbp
callq clock
movq %rax, 8(%rsp) # 8-byte Spill
movq 8(%rbp), %rdi
movl $.L.str, %esi
callq fopen
testq %rax, %rax
je .LBB1_12
# %bb.1:
movq %rax, %r14
movl $.L.str.2, %edi
movl $.L.str.3, %esi
callq fopen
movq %rax, 64(%rsp) # 8-byte Spill
leaq 186(%rsp), %rdi
movl $14, %esi
movl $1, %edx
movq %r14, %rcx
callq fread
leaq 200(%rsp), %rdi
movl $48, %esi
movl $1, %edx
movq %r14, %rcx
callq fread
movl 204(%rsp), %ecx
movl 208(%rsp), %eax
movl %eax, 28(%rsp) # 4-byte Spill
movl %ecx, 32(%rsp) # 4-byte Spill
imull %ecx, %eax
movslq %eax, %r12
leaq (%r12,%r12,2), %r13
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movl $3, %esi
movq %rax, %rdi
movq %r12, %rdx
movq %r14, 72(%rsp) # 8-byte Spill
movq %r14, %rcx
callq fread
leaq 48(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 48(%rsp), %rdi
movq %rbx, %rsi
movq %r13, %rdx
movl $1, %ecx
callq hipMemcpy
leaq 16(%rsp), %rdi
movq %r13, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
movl $255, %esi
movq %r13, %rdx
callq hipMemset
movq 16(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbx
movq 24(%rbp), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r15
movq %r12, 56(%rsp) # 8-byte Spill
cvtsi2sd %r12d, %xmm0
imull %ebx, %eax
cvtsi2sd %eax, %xmm1
divsd %xmm1, %xmm0
callq ceil@PLT
cvttsd2si %xmm0, %ebp
movl $_ZSt4cout, %edi
movl $.L.str.4, %esi
movl $12, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl %ebp, %esi
callq _ZNSolsEi
movq %rax, %r12
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r12,%rax), %r14
testq %r14, %r14
je .LBB1_13
# %bb.2: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r14)
je .LBB1_4
# %bb.3:
movzbl 67(%r14), %eax
jmp .LBB1_5
.LBB1_4:
movq %r14, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%r14), %rax
movq %r14, %rdi
movl $10, %esi
callq *48(%rax)
.LBB1_5: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %al, %esi
movq %r12, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movl %ebx, %edi
movabsq $4294967296, %rax # imm = 0x100000000
orq %rax, %rdi
movl %r15d, %edx
orq %rax, %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
movq 72(%rsp), %r14 # 8-byte Reload
jne .LBB1_7
# %bb.6:
movq 48(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movl 32(%rsp), %eax # 4-byte Reload
movl %eax, 44(%rsp)
movl 28(%rsp), %eax # 4-byte Reload
movl %eax, 40(%rsp)
movl %ebp, 36(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 44(%rsp), %rax
movq %rax, 160(%rsp)
leaq 40(%rsp), %rax
movq %rax, 168(%rsp)
leaq 36(%rsp), %rax
movq %rax, 176(%rsp)
leaq 112(%rsp), %rdi
leaq 96(%rsp), %rsi
leaq 88(%rsp), %rdx
leaq 80(%rsp), %rcx
callq __hipPopCallConfiguration
movq 112(%rsp), %rsi
movl 120(%rsp), %edx
movq 96(%rsp), %rcx
movl 104(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z6kernelP5myRGBP10grayStructiii, %edi
pushq 80(%rsp)
.cfi_adjust_cfa_offset 8
pushq 96(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_7:
leaq 186(%rsp), %rdi
movl $14, %esi
movl $1, %edx
movq 64(%rsp), %r15 # 8-byte Reload
movq %r15, %rcx
callq fwrite
leaq 200(%rsp), %rdi
movl $48, %esi
movl $1, %edx
movq %r15, %rcx
callq fwrite
callq hipDeviceSynchronize
movq %r13, %rdi
callq malloc
movq %rax, %rbx
movq 16(%rsp), %rsi
movq %rax, %rdi
movq %r13, %rdx
movl $2, %ecx
callq hipMemcpy
movl $3, %esi
movq %rbx, %rdi
movq 56(%rsp), %rdx # 8-byte Reload
movq %r15, %rcx
callq fwrite
movq %r14, %rdi
callq fclose
movq %r15, %rdi
callq fclose
callq clock
subq 8(%rsp), %rax # 8-byte Folded Reload
cvtsi2sd %rax, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movsd %xmm0, 8(%rsp) # 8-byte Spill
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq $9, _ZSt4cout+8(%rax)
movl $_ZSt4cout, %edi
movsd 8(%rsp), %xmm0 # 8-byte Reload
# xmm0 = mem[0],zero
callq _ZNSo9_M_insertIdEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB1_13
# %bb.8: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i38
cmpb $0, 56(%rbx)
je .LBB1_10
# %bb.9:
movzbl 67(%rbx), %ecx
jmp .LBB1_11
.LBB1_10:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB1_11: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit41
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %eax, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_13:
.cfi_def_cfa_offset 304
callq _ZSt16__throw_bad_castv
.LBB1_12:
movl $.L.str.1, %edi
xorl %eax, %eax
callq printf
movl $-1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z6kernelP5myRGBP10grayStructiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z6kernelP5myRGBP10grayStructiii,@object # @_Z6kernelP5myRGBP10grayStructiii
.section .rodata,"a",@progbits
.globl _Z6kernelP5myRGBP10grayStructiii
.p2align 3, 0x0
_Z6kernelP5myRGBP10grayStructiii:
.quad _Z21__device_stub__kernelP5myRGBP10grayStructiii
.size _Z6kernelP5myRGBP10grayStructiii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "rb"
.size .L.str, 3
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "\ncan not open file"
.size .L.str.1, 19
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "out_cuda.bmp"
.size .L.str.2, 13
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "wb"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Chunk Size: "
.size .L.str.4, 13
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time: "
.size .L.str.5, 7
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z6kernelP5myRGBP10grayStructiii"
.size .L__unnamed_1, 33
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z21__device_stub__kernelP5myRGBP10grayStructiii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z6kernelP5myRGBP10grayStructiii
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void fact_kernel()
{
int n = threadIdx.x;
if (n != 0)
{
int fact = 1;
for (int i = 1; i <= n; i++)
{
fact *= i;
}
printf("%d!=%d\n", n, fact);
}
}
int main()
{
const int num_threads = 9;
fact_kernel<<<1, num_threads>>>();
cudaDeviceSynchronize();
} | code for sm_80
Function : _Z11fact_kernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fc800078e00ff */
/*0010*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e220000002100 */
/*0020*/ IADD3 R1, R1, -0x8, RZ ; /* 0xfffffff801017810 */
/* 0x000fe40007ffe0ff */
/*0030*/ ISETP.NE.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x001fda0003f05270 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x000fe20003f06270 */
/*0060*/ BSSY B2, 0x700 ; /* 0x0000069000027945 */
/* 0x000fe20003800000 */
/*0070*/ IADD3 R6, P1, R1, c[0x0][0x20], RZ ; /* 0x0000080001067a10 */
/* 0x000fe20007f3e0ff */
/*0080*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fc800078e00ff */
/*0090*/ IMAD.X R7, RZ, RZ, c[0x0][0x24], P1 ; /* 0x00000900ff077624 */
/* 0x000fcc00008e06ff */
/*00a0*/ @!P0 BRA 0x6f0 ; /* 0x0000064000008947 */
/* 0x000fea0003800000 */
/*00b0*/ IADD3 R0, R2.reuse, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x040fe20007ffe0ff */
/*00c0*/ BSSY B1, 0x680 ; /* 0x000005b000017945 */
/* 0x000fe20003800000 */
/*00d0*/ LOP3.LUT R5, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302057812 */
/* 0x000fe200078ec0ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x1 ; /* 0x00000001ff037424 */
/* 0x000fe200078e00ff */
/*00f0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f06070 */
/*0100*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fd800078e00ff */
/*0110*/ @!P0 BRA 0x670 ; /* 0x0000055000008947 */
/* 0x000fea0003800000 */
/*0120*/ IMAD.IADD R9, R5, 0x1, -R2 ; /* 0x0000000105097824 */
/* 0x000fe200078e0a02 */
/*0130*/ BSSY B0, 0x5c0 ; /* 0x0000048000007945 */
/* 0x000fe20003800000 */
/*0140*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fc600078e00ff */
/*0150*/ ISETP.GE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fda0003f06270 */
/*0160*/ @P0 BRA 0x5b0 ; /* 0x0000044000000947 */
/* 0x000fea0003800000 */
/*0170*/ IMAD.MOV R4, RZ, RZ, -R9 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0a09 */
/*0180*/ BSSY B3, 0x410 ; /* 0x0000028000037945 */
/* 0x000fe20003800000 */
/*0190*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fc60003f0f070 */
/*01a0*/ ISETP.GT.AND P1, PT, R4, 0xc, PT ; /* 0x0000000c0400780c */
/* 0x000fda0003f24270 */
/*01b0*/ @!P1 BRA 0x400 ; /* 0x0000024000009947 */
/* 0x000fea0003800000 */
/*01c0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*01d0*/ IADD3 R4, R0.reuse, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x040fe20007ffe0ff */
/*01e0*/ IMAD R3, R0.reuse, R3, RZ ; /* 0x0000000300037224 */
/* 0x040fe200078e02ff */
/*01f0*/ IADD3 R8, R0, 0x2, RZ ; /* 0x0000000200087810 */
/* 0x000fe40007ffe0ff */
/*0200*/ IADD3 R9, R9, 0x10, RZ ; /* 0x0000001009097810 */
/* 0x000fe20007ffe0ff */
/*0210*/ IMAD R3, R4, R3, RZ ; /* 0x0000000304037224 */
/* 0x000fe200078e02ff */
/*0220*/ IADD3 R4, R0.reuse, 0x3, RZ ; /* 0x0000000300047810 */
/* 0x040fe40007ffe0ff */
/*0230*/ ISETP.GE.AND P1, PT, R9, -0xc, PT ; /* 0xfffffff40900780c */
/* 0x000fe20003f26270 */
/*0240*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fe200078e02ff */
/*0250*/ IADD3 R8, R0, 0x4, RZ ; /* 0x0000000400087810 */
/* 0x000fc60007ffe0ff */
/*0260*/ IMAD R3, R3, R4, RZ ; /* 0x0000000403037224 */
/* 0x000fe200078e02ff */
/*0270*/ IADD3 R4, R0, 0x5, RZ ; /* 0x0000000500047810 */
/* 0x000fc60007ffe0ff */
/*0280*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fe200078e02ff */
/*0290*/ IADD3 R8, R0, 0x6, RZ ; /* 0x0000000600087810 */
/* 0x000fc60007ffe0ff */
/*02a0*/ IMAD R3, R4, R3, RZ ; /* 0x0000000304037224 */
/* 0x000fe200078e02ff */
/*02b0*/ IADD3 R4, R0, 0x7, RZ ; /* 0x0000000700047810 */
/* 0x000fc60007ffe0ff */
/*02c0*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fe200078e02ff */
/*02d0*/ IADD3 R8, R0, 0x8, RZ ; /* 0x0000000800087810 */
/* 0x000fc60007ffe0ff */
/*02e0*/ IMAD R3, R3, R4, RZ ; /* 0x0000000403037224 */
/* 0x000fe200078e02ff */
/*02f0*/ IADD3 R4, R0, 0x9, RZ ; /* 0x0000000900047810 */
/* 0x000fc60007ffe0ff */
/*0300*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fe200078e02ff */
/*0310*/ IADD3 R8, R0, 0xa, RZ ; /* 0x0000000a00087810 */
/* 0x000fc60007ffe0ff */
/*0320*/ IMAD R3, R4, R3, RZ ; /* 0x0000000304037224 */
/* 0x000fe200078e02ff */
/*0330*/ IADD3 R4, R0, 0xb, RZ ; /* 0x0000000b00047810 */
/* 0x000fc60007ffe0ff */
/*0340*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fe200078e02ff */
/*0350*/ IADD3 R8, R0, 0xc, RZ ; /* 0x0000000c00087810 */
/* 0x000fc60007ffe0ff */
/*0360*/ IMAD R3, R3, R4, RZ ; /* 0x0000000403037224 */
/* 0x000fe200078e02ff */
/*0370*/ IADD3 R4, R0, 0xd, RZ ; /* 0x0000000d00047810 */
/* 0x000fc60007ffe0ff */
/*0380*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fe200078e02ff */
/*0390*/ IADD3 R8, R0, 0xe, RZ ; /* 0x0000000e00087810 */
/* 0x000fc60007ffe0ff */
/*03a0*/ IMAD R3, R4, R3, RZ ; /* 0x0000000304037224 */
/* 0x000fe200078e02ff */
/*03b0*/ IADD3 R4, R0.reuse, 0xf, RZ ; /* 0x0000000f00047810 */
/* 0x040fe40007ffe0ff */
/*03c0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe20007ffe0ff */
/*03d0*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fc800078e02ff */
/*03e0*/ IMAD R3, R3, R4, RZ ; /* 0x0000000403037224 */
/* 0x000fe200078e02ff */
/*03f0*/ @!P1 BRA 0x1d0 ; /* 0xfffffdd000009947 */
/* 0x000fea000383ffff */
/*0400*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0410*/ IMAD.MOV R4, RZ, RZ, -R9 ; /* 0x000000ffff047224 */
/* 0x000fe200078e0a09 */
/*0420*/ BSSY B3, 0x580 ; /* 0x0000015000037945 */
/* 0x000fe80003800000 */
/*0430*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0440*/ @!P1 BRA 0x570 ; /* 0x0000012000009947 */
/* 0x000fea0003800000 */
/*0450*/ IADD3 R4, R0.reuse, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x040fe20007ffe0ff */
/*0460*/ IMAD R3, R3, R0, RZ ; /* 0x0000000003037224 */
/* 0x000fe200078e02ff */
/*0470*/ IADD3 R8, R0, 0x2, RZ ; /* 0x0000000200087810 */
/* 0x000fe40007ffe0ff */
/*0480*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0490*/ IMAD R3, R4, R3, RZ ; /* 0x0000000304037224 */
/* 0x000fe200078e02ff */
/*04a0*/ IADD3 R4, R0.reuse, 0x3, RZ ; /* 0x0000000300047810 */
/* 0x040fe40007ffe0ff */
/*04b0*/ IADD3 R9, R9, 0x8, RZ ; /* 0x0000000809097810 */
/* 0x000fe20007ffe0ff */
/*04c0*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fe200078e02ff */
/*04d0*/ IADD3 R8, R0, 0x4, RZ ; /* 0x0000000400087810 */
/* 0x000fc60007ffe0ff */
/*04e0*/ IMAD R3, R3, R4, RZ ; /* 0x0000000403037224 */
/* 0x000fe200078e02ff */
/*04f0*/ IADD3 R4, R0, 0x5, RZ ; /* 0x0000000500047810 */
/* 0x000fc60007ffe0ff */
/*0500*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fe200078e02ff */
/*0510*/ IADD3 R8, R0, 0x6, RZ ; /* 0x0000000600087810 */
/* 0x000fc60007ffe0ff */
/*0520*/ IMAD R3, R4, R3, RZ ; /* 0x0000000304037224 */
/* 0x000fe200078e02ff */
/*0530*/ IADD3 R4, R0.reuse, 0x7, RZ ; /* 0x0000000700047810 */
/* 0x040fe40007ffe0ff */
/*0540*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fe20007ffe0ff */
/*0550*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fc800078e02ff */
/*0560*/ IMAD R3, R3, R4, RZ ; /* 0x0000000403037224 */
/* 0x000fe400078e02ff */
/*0570*/ BSYNC B3 ; /* 0x0000000000037941 */
/* 0x000fea0003800000 */
/*0580*/ ISETP.NE.OR P0, PT, R9, RZ, P0 ; /* 0x000000ff0900720c */
/* 0x000fda0000705670 */
/*0590*/ @!P0 BREAK B0 ; /* 0x0000000000008942 */
/* 0x000fe20003800000 */
/*05a0*/ @!P0 BRA 0x670 ; /* 0x000000c000008947 */
/* 0x000fea0003800000 */
/*05b0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*05c0*/ IADD3 R9, R9, 0x4, RZ ; /* 0x0000000409097810 */
/* 0x000fe20007ffe0ff */
/*05d0*/ IMAD R3, R0.reuse, R3, RZ ; /* 0x0000000300037224 */
/* 0x040fe200078e02ff */
/*05e0*/ IADD3 R4, R0.reuse, 0x1, RZ ; /* 0x0000000100047810 */
/* 0x040fe40007ffe0ff */
/*05f0*/ ISETP.NE.AND P0, PT, R9, RZ, PT ; /* 0x000000ff0900720c */
/* 0x000fe40003f05270 */
/*0600*/ IADD3 R8, R0, 0x2, RZ ; /* 0x0000000200087810 */
/* 0x000fe20007ffe0ff */
/*0610*/ IMAD R3, R4, R3, RZ ; /* 0x0000000304037224 */
/* 0x000fe200078e02ff */
/*0620*/ IADD3 R4, R0.reuse, 0x3, RZ ; /* 0x0000000300047810 */
/* 0x040fe40007ffe0ff */
/*0630*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*0640*/ IMAD R3, R3, R8, RZ ; /* 0x0000000803037224 */
/* 0x000fc800078e02ff */
/*0650*/ IMAD R3, R3, R4, RZ ; /* 0x0000000403037224 */
/* 0x000fe400078e02ff */
/*0660*/ @P0 BRA 0x5c0 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0670*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0680*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0690*/ @!P0 BRA 0x6f0 ; /* 0x0000005000008947 */
/* 0x000fea0003800000 */
/*06a0*/ IADD3 R5, R5, -0x1, RZ ; /* 0xffffffff05057810 */
/* 0x000fe20007ffe0ff */
/*06b0*/ IMAD R3, R0.reuse, R3, RZ ; /* 0x0000000300037224 */
/* 0x040fe200078e02ff */
/*06c0*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe40007ffe0ff */
/*06d0*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*06e0*/ @P0 BRA 0x6a0 ; /* 0xffffffb000000947 */
/* 0x000fea000383ffff */
/*06f0*/ BSYNC B2 ; /* 0x0000000000027941 */
/* 0x000fea0003800000 */
/*0700*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0710*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0720*/ STL.64 [R1], R2 ; /* 0x0000000201007387 */
/* 0x0001e20000100a00 */
/*0730*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe400078e00ff */
/*0740*/ LDC.64 R8, c[0x4][R0] ; /* 0x0100000000087b82 */
/* 0x0000620000000a00 */
/*0750*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fce00078e00ff */
/*0760*/ LEPC R2 ; /* 0x000000000002734e */
/* 0x001fe20000000000 */
/*0770*/ MOV R11, 0x7e0 ; /* 0x000007e0000b7802 */
/* 0x000fe40000000f00 */
/*0780*/ MOV R20, 0x760 ; /* 0x0000076000147802 */
/* 0x000fe40000000f00 */
/*0790*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fc40000000f00 */
/*07a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe40000000f00 */
/*07b0*/ IADD3 R20, P0, P1, -R20, R11, R2 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e102 */
/*07c0*/ IADD3.X R21, ~R0, R21, R3, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2503 */
/*07d0*/ CALL.ABS.NOINC R8 ; /* 0x0000000008007343 */
/* 0x002fea0003c00000 */
/*07e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*07f0*/ BRA 0x7f0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0800*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0810*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0820*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0830*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0840*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0850*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0860*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0870*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <stdio.h>
__global__ void fact_kernel()
{
int n = threadIdx.x;
if (n != 0)
{
int fact = 1;
for (int i = 1; i <= n; i++)
{
fact *= i;
}
printf("%d!=%d\n", n, fact);
}
}
int main()
{
const int num_threads = 9;
fact_kernel<<<1, num_threads>>>();
cudaDeviceSynchronize();
} | .file "tmpxft_0004f698_00000000-6_task1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11fact_kernelvv
.type _Z30__device_stub__Z11fact_kernelvv, @function
_Z30__device_stub__Z11fact_kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11fact_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z11fact_kernelvv, .-_Z30__device_stub__Z11fact_kernelvv
.globl _Z11fact_kernelv
.type _Z11fact_kernelv, @function
_Z11fact_kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11fact_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11fact_kernelv, .-_Z11fact_kernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $9, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11fact_kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11fact_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11fact_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <stdio.h>
__global__ void fact_kernel()
{
int n = threadIdx.x;
if (n != 0)
{
int fact = 1;
for (int i = 1; i <= n; i++)
{
fact *= i;
}
printf("%d!=%d\n", n, fact);
}
}
int main()
{
const int num_threads = 9;
fact_kernel<<<1, num_threads>>>();
cudaDeviceSynchronize();
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void fact_kernel()
{
int n = threadIdx.x;
if (n != 0)
{
int fact = 1;
for (int i = 1; i <= n; i++)
{
fact *= i;
}
printf("%d!=%d\n", n, fact);
}
}
int main()
{
const int num_threads = 9;
fact_kernel<<<1, num_threads>>>();
hipDeviceSynchronize();
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void fact_kernel()
{
int n = threadIdx.x;
if (n != 0)
{
int fact = 1;
for (int i = 1; i <= n; i++)
{
fact *= i;
}
printf("%d!=%d\n", n, fact);
}
}
int main()
{
const int num_threads = 9;
fact_kernel<<<1, num_threads>>>();
hipDeviceSynchronize();
} | .text
.file "task1.hip"
.globl _Z26__device_stub__fact_kernelv # -- Begin function _Z26__device_stub__fact_kernelv
.p2align 4, 0x90
.type _Z26__device_stub__fact_kernelv,@function
_Z26__device_stub__fact_kernelv: # @_Z26__device_stub__fact_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11fact_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__fact_kernelv, .Lfunc_end0-_Z26__device_stub__fact_kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 8(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11fact_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11fact_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11fact_kernelv,@object # @_Z11fact_kernelv
.section .rodata,"a",@progbits
.globl _Z11fact_kernelv
.p2align 3, 0x0
_Z11fact_kernelv:
.quad _Z26__device_stub__fact_kernelv
.size _Z11fact_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11fact_kernelv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__fact_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11fact_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0004f698_00000000-6_task1.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z30__device_stub__Z11fact_kernelvv
.type _Z30__device_stub__Z11fact_kernelvv, @function
_Z30__device_stub__Z11fact_kernelvv:
.LFB2082:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z11fact_kernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z30__device_stub__Z11fact_kernelvv, .-_Z30__device_stub__Z11fact_kernelvv
.globl _Z11fact_kernelv
.type _Z11fact_kernelv, @function
_Z11fact_kernelv:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z11fact_kernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11fact_kernelv, .-_Z11fact_kernelv
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
subq $40, %rsp
.cfi_def_cfa_offset 48
movl $9, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L14
.L12:
call cudaDeviceSynchronize@PLT
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call _Z30__device_stub__Z11fact_kernelvv
jmp .L12
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11fact_kernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11fact_kernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "task1.hip"
.globl _Z26__device_stub__fact_kernelv # -- Begin function _Z26__device_stub__fact_kernelv
.p2align 4, 0x90
.type _Z26__device_stub__fact_kernelv,@function
_Z26__device_stub__fact_kernelv: # @_Z26__device_stub__fact_kernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11fact_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z26__device_stub__fact_kernelv, .Lfunc_end0-_Z26__device_stub__fact_kernelv
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 8(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z11fact_kernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
callq hipDeviceSynchronize
xorl %eax, %eax
addq $56, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11fact_kernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11fact_kernelv,@object # @_Z11fact_kernelv
.section .rodata,"a",@progbits
.globl _Z11fact_kernelv
.p2align 3, 0x0
_Z11fact_kernelv:
.quad _Z26__device_stub__fact_kernelv
.size _Z11fact_kernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11fact_kernelv"
.size .L__unnamed_1, 17
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__fact_kernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11fact_kernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
__global__ void hello (void)
{
printf("Hello Wold from GPU!\n");
}
extern "C" int fun_cuda()
{
int c;
int *dev_c;
cudaMalloc((void **)&dev_c, sizeof(int));
add<<<1,1>>>(2, 7, dev_c);
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("2+7=%d\n",c);
cudaFree(dev_c);
hello<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z5hellov
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z3addiiPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff057624 */
/* 0x000fe200078e00ff */
/*0020*/ MOV R2, c[0x0][0x168] ; /* 0x00005a0000027a02 */
/* 0x000fe20000000f00 */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0040*/ MOV R3, c[0x0][0x16c] ; /* 0x00005b0000037a02 */
/* 0x000fe40000000f00 */
/*0050*/ IADD3 R5, R5, c[0x0][0x160], RZ ; /* 0x0000580005057a10 */
/* 0x000fca0007ffe0ff */
/*0060*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*0070*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0080*/ BRA 0x80; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0090*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
__global__ void hello (void)
{
printf("Hello Wold from GPU!\n");
}
extern "C" int fun_cuda()
{
int c;
int *dev_c;
cudaMalloc((void **)&dev_c, sizeof(int));
add<<<1,1>>>(2, 7, dev_c);
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("2+7=%d\n",c);
cudaFree(dev_c);
hello<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | .file "tmpxft_001850df_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addiiPi, .-_Z3addiiPi
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z5hellov, .-_Z5hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "2+7=%d\n"
.text
.globl fun_cuda
.type fun_cuda, @function
fun_cuda:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L20
.L25:
call _Z23__device_stub__Z5hellovv
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size fun_cuda, .-fun_cuda
.section .rodata.str1.1
.LC1:
.string "_Z5hellov"
.LC2:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <cuda_runtime.h>
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
__global__ void hello (void)
{
printf("Hello Wold from GPU!\n");
}
extern "C" int fun_cuda()
{
int c;
int *dev_c;
cudaMalloc((void **)&dev_c, sizeof(int));
add<<<1,1>>>(2, 7, dev_c);
cudaMemcpy(&c, dev_c, sizeof(int), cudaMemcpyDeviceToHost);
printf("2+7=%d\n",c);
cudaFree(dev_c);
hello<<<1, 10>>>();
cudaDeviceReset();
return 0;
} | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
__global__ void hello (void)
{
printf("Hello Wold from GPU!\n");
}
extern "C" int fun_cuda()
{
int c;
int *dev_c;
hipMalloc((void **)&dev_c, sizeof(int));
add<<<1,1>>>(2, 7, dev_c);
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("2+7=%d\n",c);
hipFree(dev_c);
hello<<<1, 10>>>();
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
__global__ void hello (void)
{
printf("Hello Wold from GPU!\n");
}
extern "C" int fun_cuda()
{
int c;
int *dev_c;
hipMalloc((void **)&dev_c, sizeof(int));
add<<<1,1>>>(2, 7, dev_c);
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("2+7=%d\n",c);
hipFree(dev_c);
hello<<<1, 10>>>();
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3addiiPi
.globl _Z3addiiPi
.p2align 8
.type _Z3addiiPi,@function
_Z3addiiPi:
s_load_b128 s[0:3], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_add_i32 s0, s1, s0
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
global_store_b32 v0, v1, s[2:3]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3addiiPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3addiiPi, .Lfunc_end0-_Z3addiiPi
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z5hellov
.globl _Z5hellov
.p2align 8
.type _Z5hellov,@function
_Z5hellov:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB1_5
s_mov_b32 s5, 0
.p2align 6
.LBB1_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB1_3
s_or_b32 exec_lo, exec_lo, s5
.LBB1_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB1_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB1_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB1_12
s_mov_b32 s9, 0
.LBB1_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB1_11
.LBB1_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB1_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB1_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB1_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB1_20
.p2align 6
.LBB1_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB1_19
s_sleep 1
s_cbranch_execnz .LBB1_20
s_branch .LBB1_22
.p2align 6
.LBB1_19:
s_branch .LBB1_22
.LBB1_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB1_17
.LBB1_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_26
s_mov_b32 s0, 0
.LBB1_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB1_25
.LBB1_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB1_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 22
s_branch .LBB1_29
.LBB1_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB1_104
.LBB1_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB1_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB1_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB1_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB1_32
.LBB1_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB1_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB1_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB1_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB1_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB1_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB1_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB1_39
.LBB1_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB1_42
s_branch .LBB1_43
.LBB1_41:
.LBB1_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB1_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB1_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB1_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB1_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB1_46
.LBB1_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB1_49
s_branch .LBB1_50
.LBB1_48:
.LBB1_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB1_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB1_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB1_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB1_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB1_53
.LBB1_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB1_56
s_branch .LBB1_57
.LBB1_55:
.LBB1_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB1_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB1_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB1_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB1_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB1_60
.LBB1_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB1_63
s_branch .LBB1_64
.LBB1_62:
.LBB1_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB1_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB1_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB1_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB1_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB1_67
.LBB1_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB1_70
s_branch .LBB1_71
.LBB1_69:
.LBB1_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB1_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB1_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB1_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB1_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB1_74
.LBB1_75:
s_cbranch_execz .LBB1_77
s_branch .LBB1_78
.LBB1_76:
.LBB1_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB1_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB1_83
s_mov_b32 s11, 0
.p2align 6
.LBB1_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB1_81
s_or_b32 exec_lo, exec_lo, s11
.LBB1_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB1_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB1_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB1_90
s_mov_b32 s15, 0
.LBB1_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB1_89
.LBB1_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB1_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB1_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB1_98
.p2align 6
.LBB1_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB1_97
s_sleep 1
s_cbranch_execnz .LBB1_98
s_branch .LBB1_100
.p2align 6
.LBB1_97:
s_branch .LBB1_100
.LBB1_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB1_95
.LBB1_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_28
s_mov_b32 s0, 0
.LBB1_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB1_103
s_branch .LBB1_28
.LBB1_104:
s_mov_b32 s0, 0
.LBB1_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB1_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB1_111
s_mov_b32 s5, 0
.p2align 6
.LBB1_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB1_109
s_or_b32 exec_lo, exec_lo, s5
.LBB1_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB1_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB1_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB1_118
s_mov_b32 s9, 0
.LBB1_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB1_117
.LBB1_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB1_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB1_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB1_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB1_126
.p2align 6
.LBB1_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB1_125
s_sleep 1
s_cbranch_execnz .LBB1_126
s_branch .LBB1_128
.p2align 6
.LBB1_125:
s_branch .LBB1_128
.LBB1_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB1_123
.LBB1_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB1_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB1_132
s_mov_b32 s0, 0
.LBB1_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB1_131
.LBB1_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z5hellov
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z5hellov, .Lfunc_end1-_Z5hellov
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hello Wold from GPU!\n"
.size .str, 22
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3addiiPi
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z3addiiPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z5hellov
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z5hellov.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <hip/hip_runtime.h>
__global__ void add(int a, int b, int *c) {
*c = a + b;
}
__global__ void hello (void)
{
printf("Hello Wold from GPU!\n");
}
extern "C" int fun_cuda()
{
int c;
int *dev_c;
hipMalloc((void **)&dev_c, sizeof(int));
add<<<1,1>>>(2, 7, dev_c);
hipMemcpy(&c, dev_c, sizeof(int), hipMemcpyDeviceToHost);
printf("2+7=%d\n",c);
hipFree(dev_c);
hello<<<1, 10>>>();
hipDeviceReset();
return 0;
} | .text
.file "cuda.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z20__device_stub__hellov, .Lfunc_end1-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl fun_cuda # -- Begin function fun_cuda
.p2align 4, 0x90
.type fun_cuda,@function
fun_cuda: # @fun_cuda
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq (%rsp), %rax
movl $2, 44(%rsp)
movl $7, 40(%rsp)
movq %rax, 16(%rsp)
leaq 44(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq (%rsp), %rsi
leaq 8(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 8(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
leaq 9(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 80(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5hellov, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceReset
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size fun_cuda, .Lfunc_end2-fun_cuda
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type _Z5hellov,@object # @_Z5hellov
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "2+7=%d\n"
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5hellov"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001850df_00000000-6_cuda.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z24__device_stub__Z3addiiPiiiPi
.type _Z24__device_stub__Z3addiiPiiiPi, @function
_Z24__device_stub__Z3addiiPiiiPi:
.LFB2082:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movl %edi, 12(%rsp)
movl %esi, 8(%rsp)
movq %rdx, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 12(%rsp), %rax
movq %rax, 80(%rsp)
leaq 8(%rsp), %rax
movq %rax, 88(%rsp)
movq %rsp, %rax
movq %rax, 96(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z3addiiPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z24__device_stub__Z3addiiPiiiPi, .-_Z24__device_stub__Z3addiiPiiiPi
.globl _Z3addiiPi
.type _Z3addiiPi, @function
_Z3addiiPi:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z24__device_stub__Z3addiiPiiiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z3addiiPi, .-_Z3addiiPi
.globl _Z23__device_stub__Z5hellovv
.type _Z23__device_stub__Z5hellovv, @function
_Z23__device_stub__Z5hellovv:
.LFB2084:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L15
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L15:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z5hellov(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L11
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z23__device_stub__Z5hellovv, .-_Z23__device_stub__Z5hellovv
.globl _Z5hellov
.type _Z5hellov, @function
_Z5hellov:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z23__device_stub__Z5hellovv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z5hellov, .-_Z5hellov
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "2+7=%d\n"
.text
.globl fun_cuda
.type fun_cuda, @function
fun_cuda:
.LFB2057:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rdi
movl $4, %esi
call cudaMalloc@PLT
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
leaq 4(%rsp), %rdi
movl $2, %ecx
movl $4, %edx
movq 8(%rsp), %rsi
call cudaMemcpy@PLT
movl 4(%rsp), %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movl $10, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L25
.L21:
call cudaDeviceReset@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L26
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movq 8(%rsp), %rdx
movl $7, %esi
movl $2, %edi
call _Z24__device_stub__Z3addiiPiiiPi
jmp .L20
.L25:
call _Z23__device_stub__Z5hellovv
jmp .L21
.L26:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size fun_cuda, .-fun_cuda
.section .rodata.str1.1
.LC1:
.string "_Z5hellov"
.LC2:
.string "_Z3addiiPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2087:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z5hellov(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z3addiiPi(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "cuda.hip"
.globl _Z18__device_stub__addiiPi # -- Begin function _Z18__device_stub__addiiPi
.p2align 4, 0x90
.type _Z18__device_stub__addiiPi,@function
_Z18__device_stub__addiiPi: # @_Z18__device_stub__addiiPi
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movl %edi, 4(%rsp)
movl %esi, (%rsp)
movq %rdx, 56(%rsp)
leaq 4(%rsp), %rax
movq %rax, 64(%rsp)
movq %rsp, %rax
movq %rax, 72(%rsp)
leaq 56(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z18__device_stub__addiiPi, .Lfunc_end0-_Z18__device_stub__addiiPi
.cfi_endproc
# -- End function
.globl _Z20__device_stub__hellov # -- Begin function _Z20__device_stub__hellov
.p2align 4, 0x90
.type _Z20__device_stub__hellov,@function
_Z20__device_stub__hellov: # @_Z20__device_stub__hellov
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z5hellov, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end1:
.size _Z20__device_stub__hellov, .Lfunc_end1-_Z20__device_stub__hellov
.cfi_endproc
# -- End function
.globl fun_cuda # -- Begin function fun_cuda
.p2align 4, 0x90
.type fun_cuda,@function
fun_cuda: # @fun_cuda
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $112, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -16
movabsq $4294967297, %rbx # imm = 0x100000001
movq %rsp, %rdi
movl $4, %esi
callq hipMalloc
movq %rbx, %rdi
movl $1, %esi
movq %rbx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq (%rsp), %rax
movl $2, 44(%rsp)
movl $7, 40(%rsp)
movq %rax, 16(%rsp)
leaq 44(%rsp), %rax
movq %rax, 80(%rsp)
leaq 40(%rsp), %rax
movq %rax, 88(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
leaq 24(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 24(%rsp), %rsi
movl 32(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3addiiPi, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq (%rsp), %rsi
leaq 8(%rsp), %rdi
movl $4, %edx
movl $2, %ecx
callq hipMemcpy
movl 8(%rsp), %esi
movl $.L.str, %edi
xorl %eax, %eax
callq printf
movq (%rsp), %rdi
callq hipFree
leaq 9(%rbx), %rdx
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
leaq 80(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z5hellov, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
callq hipDeviceReset
xorl %eax, %eax
addq $112, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size fun_cuda, .Lfunc_end2-fun_cuda
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3addiiPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z5hellov, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z3addiiPi,@object # @_Z3addiiPi
.section .rodata,"a",@progbits
.globl _Z3addiiPi
.p2align 3, 0x0
_Z3addiiPi:
.quad _Z18__device_stub__addiiPi
.size _Z3addiiPi, 8
.type _Z5hellov,@object # @_Z5hellov
.globl _Z5hellov
.p2align 3, 0x0
_Z5hellov:
.quad _Z20__device_stub__hellov
.size _Z5hellov, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "2+7=%d\n"
.size .L.str, 8
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3addiiPi"
.size .L__unnamed_1, 11
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z5hellov"
.size .L__unnamed_2, 10
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__addiiPi
.addrsig_sym _Z20__device_stub__hellov
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3addiiPi
.addrsig_sym _Z5hellov
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void matrixAdd(float *A, float *B, float *C, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int num = n;
int i = row * num + col;
if (row < num && col < num)
{
C[i] = A[i] + B[i];
}
} | code for sm_80
Function : _Z9matrixAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void matrixAdd(float *A, float *B, float *C, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int num = n;
int i = row * num + col;
if (row < num && col < num)
{
C[i] = A[i] + B[i];
}
} | .file "tmpxft_00117f2f_00000000-6_matrixAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
.globl _Z9matrixAddPfS_S_i
.type _Z9matrixAddPfS_S_i, @function
_Z9matrixAddPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9matrixAddPfS_S_i, .-_Z9matrixAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9matrixAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void matrixAdd(float *A, float *B, float *C, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int num = n;
int i = row * num + col;
if (row < num && col < num)
{
C[i] = A[i] + B[i];
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd(float *A, float *B, float *C, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int num = n;
int i = row * num + col;
if (row < num && col < num)
{
C[i] = A[i] + B[i];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd(float *A, float *B, float *C, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int num = n;
int i = row * num + col;
if (row < num && col < num)
{
C[i] = A[i] + B[i];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPfS_S_i
.globl _Z9matrixAddPfS_S_i
.p2align 8
.type _Z9matrixAddPfS_S_i,@function
_Z9matrixAddPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPfS_S_i, .Lfunc_end0-_Z9matrixAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void matrixAdd(float *A, float *B, float *C, int n)
{
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
int num = n;
int i = row * num + col;
if (row < num && col < num)
{
C[i] = A[i] + B[i];
}
} | .text
.file "matrixAdd.hip"
.globl _Z24__device_stub__matrixAddPfS_S_i # -- Begin function _Z24__device_stub__matrixAddPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPfS_S_i,@function
_Z24__device_stub__matrixAddPfS_S_i: # @_Z24__device_stub__matrixAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixAddPfS_S_i, .Lfunc_end0-_Z24__device_stub__matrixAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPfS_S_i,@object # @_Z9matrixAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixAddPfS_S_i
.p2align 3, 0x0
_Z9matrixAddPfS_S_i:
.quad _Z24__device_stub__matrixAddPfS_S_i
.size _Z9matrixAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9matrixAddPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z9matrixAddPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R3, SR_CTAID.X ; /* 0x0000000000037919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R5, SR_TID.Y ; /* 0x0000000000057919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R3, R3, c[0x0][0x0], R2 ; /* 0x0000000003037a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R3, c[0x0][0x178], PT ; /* 0x00005e0003007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R5 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0205 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R0, R0, c[0x0][0x178], R3 ; /* 0x00005e0000007a24 */
/* 0x000fe200078e0203 */
/*00c0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd00000000a00 */
/*00d0*/ IMAD.WIDE R4, R0, R7, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x000fc800078e0207 */
/*00e0*/ IMAD.WIDE R2, R0.reuse, R7.reuse, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x0c0fe400078e0207 */
/*00f0*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000ea8000c1e1900 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IMAD.WIDE R6, R0, R7, c[0x0][0x170] ; /* 0x00005c0000067625 */
/* 0x000fc800078e0207 */
/*0120*/ FADD R9, R4, R3 ; /* 0x0000000304097221 */
/* 0x004fca0000000000 */
/*0130*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*0140*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0150*/ BRA 0x150; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9matrixAddPfS_S_i
.globl _Z9matrixAddPfS_S_i
.p2align 8
.type _Z9matrixAddPfS_S_i,@function
_Z9matrixAddPfS_S_i:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b32 s2, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s4, s3, 16
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
s_mov_b32 s3, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s2, v2
s_cbranch_execz .LBB0_2
s_load_b128 s[4:7], s[0:1], 0x0
v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
s_load_b64 s[0:1], s[0:1], 0x10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s4, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
v_add_co_u32 v4, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s0, v0
global_load_b32 v2, v[2:3], off
global_load_b32 v3, v[4:5], off
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v2, v3
global_store_b32 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9matrixAddPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 6
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9matrixAddPfS_S_i, .Lfunc_end0-_Z9matrixAddPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9matrixAddPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9matrixAddPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 6
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00117f2f_00000000-6_matrixAdd.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
.type _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i, @function
_Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9matrixAddPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i, .-_Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
.globl _Z9matrixAddPfS_S_i
.type _Z9matrixAddPfS_S_i, @function
_Z9matrixAddPfS_S_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z9matrixAddPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z9matrixAddPfS_S_i, .-_Z9matrixAddPfS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z9matrixAddPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z9matrixAddPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixAdd.hip"
.globl _Z24__device_stub__matrixAddPfS_S_i # -- Begin function _Z24__device_stub__matrixAddPfS_S_i
.p2align 4, 0x90
.type _Z24__device_stub__matrixAddPfS_S_i,@function
_Z24__device_stub__matrixAddPfS_S_i: # @_Z24__device_stub__matrixAddPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9matrixAddPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z24__device_stub__matrixAddPfS_S_i, .Lfunc_end0-_Z24__device_stub__matrixAddPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9matrixAddPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z9matrixAddPfS_S_i,@object # @_Z9matrixAddPfS_S_i
.section .rodata,"a",@progbits
.globl _Z9matrixAddPfS_S_i
.p2align 3, 0x0
_Z9matrixAddPfS_S_i:
.quad _Z24__device_stub__matrixAddPfS_S_i
.size _Z9matrixAddPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9matrixAddPfS_S_i"
.size .L__unnamed_1, 20
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__matrixAddPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9matrixAddPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
/*
status:☹️
sequence:NCHW
*/
struct arg
{
int image_height;
int image_width;
int channel;
int stride;
int filter_height;
int filter_width;
};
__global__ void conv_2d(float *image,float *filter,float *out,arg *args)
{
int x=blockIdx.x*blockDim.x+threadIdx.x;
int y=blockIdx.y*blockDim.y+threadIdx.y;
int out_height=args->image_height-args->filter_height;
int out_width=args->image_width-args->filter_width;
float local=0.0;
for (int i=0;i<args->filter_height;i++)
{
for (int j=0;j<args->filter_width;i++)
local+=filter[i*args->filter_width+j]*image[(i+x)*args->image_width+(j+y)];
}
} | code for sm_80
Function : _Z7conv_2dPfS_S_P3arg
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ LDG.E.CONSTANT R2, [R2.64+0x10] ; /* 0x0000100602027981 */
/* 0x000ea2000c1e9900 */
/*0060*/ UIADD3 UR4, UP0, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc8000ff1e03f */
/*0070*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0080*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f06270 */
/*0090*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fe20008000f00 */
/*00b0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fca000f8e00ff */
/*00c0*/ LDG.E.CONSTANT R2, [R2.64+0x4] ; /* 0x0000040602027981 */
/* 0x000ea4000c1e9900 */
/*00d0*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f04270 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0 ; /* 0xfffffff000007947 */
/* 0x000fea000383ffff */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
/*
status:☹️
sequence:NCHW
*/
struct arg
{
int image_height;
int image_width;
int channel;
int stride;
int filter_height;
int filter_width;
};
__global__ void conv_2d(float *image,float *filter,float *out,arg *args)
{
int x=blockIdx.x*blockDim.x+threadIdx.x;
int y=blockIdx.y*blockDim.y+threadIdx.y;
int out_height=args->image_height-args->filter_height;
int out_width=args->image_width-args->filter_width;
float local=0.0;
for (int i=0;i<args->filter_height;i++)
{
for (int j=0;j<args->filter_width;i++)
local+=filter[i*args->filter_width+j]*image[(i+x)*args->image_width+(j+y)];
}
} | .file "tmpxft_0009317e_00000000-6_CUDA-CNN.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg
.type _Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg, @function
_Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7conv_2dPfS_S_P3arg(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg, .-_Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg
.globl _Z7conv_2dPfS_S_P3arg
.type _Z7conv_2dPfS_S_P3arg, @function
_Z7conv_2dPfS_S_P3arg:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7conv_2dPfS_S_P3arg, .-_Z7conv_2dPfS_S_P3arg
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7conv_2dPfS_S_P3arg"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7conv_2dPfS_S_P3arg(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
/*
status:☹️
sequence:NCHW
*/
struct arg
{
int image_height;
int image_width;
int channel;
int stride;
int filter_height;
int filter_width;
};
__global__ void conv_2d(float *image,float *filter,float *out,arg *args)
{
int x=blockIdx.x*blockDim.x+threadIdx.x;
int y=blockIdx.y*blockDim.y+threadIdx.y;
int out_height=args->image_height-args->filter_height;
int out_width=args->image_width-args->filter_width;
float local=0.0;
for (int i=0;i<args->filter_height;i++)
{
for (int j=0;j<args->filter_width;i++)
local+=filter[i*args->filter_width+j]*image[(i+x)*args->image_width+(j+y)];
}
} | #include <hip/hip_runtime.h>
/*
status:☹️
sequence:NCHW
*/
struct arg
{
int image_height;
int image_width;
int channel;
int stride;
int filter_height;
int filter_width;
};
__global__ void conv_2d(float *image,float *filter,float *out,arg *args)
{
int x=blockIdx.x*blockDim.x+threadIdx.x;
int y=blockIdx.y*blockDim.y+threadIdx.y;
int out_height=args->image_height-args->filter_height;
int out_width=args->image_width-args->filter_width;
float local=0.0;
for (int i=0;i<args->filter_height;i++)
{
for (int j=0;j<args->filter_width;i++)
local+=filter[i*args->filter_width+j]*image[(i+x)*args->image_width+(j+y)];
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
/*
status:☹️
sequence:NCHW
*/
struct arg
{
int image_height;
int image_width;
int channel;
int stride;
int filter_height;
int filter_width;
};
__global__ void conv_2d(float *image,float *filter,float *out,arg *args)
{
int x=blockIdx.x*blockDim.x+threadIdx.x;
int y=blockIdx.y*blockDim.y+threadIdx.y;
int out_height=args->image_height-args->filter_height;
int out_width=args->image_width-args->filter_width;
float local=0.0;
for (int i=0;i<args->filter_height;i++)
{
for (int j=0;j<args->filter_width;i++)
local+=filter[i*args->filter_width+j]*image[(i+x)*args->image_width+(j+y)];
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7conv_2dPfS_S_P3arg
.globl _Z7conv_2dPfS_S_P3arg
.p2align 8
.type _Z7conv_2dPfS_S_P3arg,@function
_Z7conv_2dPfS_S_P3arg:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7conv_2dPfS_S_P3arg
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7conv_2dPfS_S_P3arg, .Lfunc_end0-_Z7conv_2dPfS_S_P3arg
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7conv_2dPfS_S_P3arg
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7conv_2dPfS_S_P3arg.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
/*
status:☹️
sequence:NCHW
*/
struct arg
{
int image_height;
int image_width;
int channel;
int stride;
int filter_height;
int filter_width;
};
__global__ void conv_2d(float *image,float *filter,float *out,arg *args)
{
int x=blockIdx.x*blockDim.x+threadIdx.x;
int y=blockIdx.y*blockDim.y+threadIdx.y;
int out_height=args->image_height-args->filter_height;
int out_width=args->image_width-args->filter_width;
float local=0.0;
for (int i=0;i<args->filter_height;i++)
{
for (int j=0;j<args->filter_width;i++)
local+=filter[i*args->filter_width+j]*image[(i+x)*args->image_width+(j+y)];
}
} | .text
.file "CUDA-CNN.hip"
.globl _Z22__device_stub__conv_2dPfS_S_P3arg # -- Begin function _Z22__device_stub__conv_2dPfS_S_P3arg
.p2align 4, 0x90
.type _Z22__device_stub__conv_2dPfS_S_P3arg,@function
_Z22__device_stub__conv_2dPfS_S_P3arg: # @_Z22__device_stub__conv_2dPfS_S_P3arg
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7conv_2dPfS_S_P3arg, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__conv_2dPfS_S_P3arg, .Lfunc_end0-_Z22__device_stub__conv_2dPfS_S_P3arg
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7conv_2dPfS_S_P3arg, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7conv_2dPfS_S_P3arg,@object # @_Z7conv_2dPfS_S_P3arg
.section .rodata,"a",@progbits
.globl _Z7conv_2dPfS_S_P3arg
.p2align 3, 0x0
_Z7conv_2dPfS_S_P3arg:
.quad _Z22__device_stub__conv_2dPfS_S_P3arg
.size _Z7conv_2dPfS_S_P3arg, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7conv_2dPfS_S_P3arg"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__conv_2dPfS_S_P3arg
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7conv_2dPfS_S_P3arg
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z7conv_2dPfS_S_P3arg
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R2, c[0x0][0x178] ; /* 0x00005e0000027a02 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff037624 */
/* 0x000fe200078e00ff */
/*0030*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe40000000a00 */
/*0040*/ ULDC.64 UR4, c[0x0][0x178] ; /* 0x00005e0000047ab9 */
/* 0x000fe40000000a00 */
/*0050*/ LDG.E.CONSTANT R2, [R2.64+0x10] ; /* 0x0000100602027981 */
/* 0x000ea2000c1e9900 */
/*0060*/ UIADD3 UR4, UP0, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fc8000ff1e03f */
/*0070*/ UIADD3.X UR5, URZ, UR5, URZ, UP0, !UPT ; /* 0x000000053f057290 */
/* 0x000fe200087fe43f */
/*0080*/ ISETP.GE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f06270 */
/*0090*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R2, UR4 ; /* 0x0000000400027c02 */
/* 0x000fe20008000f00 */
/*00b0*/ IMAD.U32 R3, RZ, RZ, UR5 ; /* 0x00000005ff037e24 */
/* 0x000fca000f8e00ff */
/*00c0*/ LDG.E.CONSTANT R2, [R2.64+0x4] ; /* 0x0000040602027981 */
/* 0x000ea4000c1e9900 */
/*00d0*/ ISETP.GT.AND P0, PT, R2, RZ, PT ; /* 0x000000ff0200720c */
/* 0x004fda0003f04270 */
/*00e0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0 ; /* 0xfffffff000007947 */
/* 0x000fea000383ffff */
/*0100*/ BRA 0x100; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z7conv_2dPfS_S_P3arg
.globl _Z7conv_2dPfS_S_P3arg
.p2align 8
.type _Z7conv_2dPfS_S_P3arg,@function
_Z7conv_2dPfS_S_P3arg:
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z7conv_2dPfS_S_P3arg
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 1
.amdhsa_next_free_sgpr 1
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z7conv_2dPfS_S_P3arg, .Lfunc_end0-_Z7conv_2dPfS_S_P3arg
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z7conv_2dPfS_S_P3arg
.private_segment_fixed_size: 0
.sgpr_count: 0
.sgpr_spill_count: 0
.symbol: _Z7conv_2dPfS_S_P3arg.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 0
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0009317e_00000000-6_CUDA-CNN.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg
.type _Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg, @function
_Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z7conv_2dPfS_S_P3arg(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg, .-_Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg
.globl _Z7conv_2dPfS_S_P3arg
.type _Z7conv_2dPfS_S_P3arg, @function
_Z7conv_2dPfS_S_P3arg:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z7conv_2dPfS_S_P3argPfS_S_P3arg
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z7conv_2dPfS_S_P3arg, .-_Z7conv_2dPfS_S_P3arg
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z7conv_2dPfS_S_P3arg"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z7conv_2dPfS_S_P3arg(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "CUDA-CNN.hip"
.globl _Z22__device_stub__conv_2dPfS_S_P3arg # -- Begin function _Z22__device_stub__conv_2dPfS_S_P3arg
.p2align 4, 0x90
.type _Z22__device_stub__conv_2dPfS_S_P3arg,@function
_Z22__device_stub__conv_2dPfS_S_P3arg: # @_Z22__device_stub__conv_2dPfS_S_P3arg
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7conv_2dPfS_S_P3arg, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z22__device_stub__conv_2dPfS_S_P3arg, .Lfunc_end0-_Z22__device_stub__conv_2dPfS_S_P3arg
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7conv_2dPfS_S_P3arg, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7conv_2dPfS_S_P3arg,@object # @_Z7conv_2dPfS_S_P3arg
.section .rodata,"a",@progbits
.globl _Z7conv_2dPfS_S_P3arg
.p2align 3, 0x0
_Z7conv_2dPfS_S_P3arg:
.quad _Z22__device_stub__conv_2dPfS_S_P3arg
.size _Z7conv_2dPfS_S_P3arg, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z7conv_2dPfS_S_P3arg"
.size .L__unnamed_1, 22
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__conv_2dPfS_S_P3arg
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7conv_2dPfS_S_P3arg
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | extern "C"
//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64
#define m 0.001/2000
#define PI 3.14159265359f
__global__ void ker_rho(float *out, const float *x, const int *ind, const float h)
{
//int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z
int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];
for (int i = istart; i < iend; i += Block_Size)
{
int id = i + threadIdx.x;
float xi[3];
if (id < iend)
{
xi[0] = x[3 * id + 0];
xi[1] = x[3 * id + 1];
xi[2] = x[3 * id + 2];
}
float dx[3];
float r2;
float r;
float W;
float rho = 0;
__shared__ float xj[Block_Size * 3];
for (int a = -1; a < 2; a++)
{
for (int b = -1; b < 2; b++)
{
if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
{
continue;
}
int Zstart = max((int)blockIdx.z - 1, 0);
int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);
int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];
for (int j = jstart; j < jend; j += Block_Size)
{
int jd = j + threadIdx.x;
if (jd < jend)
{
xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
}
__syncthreads();
if (id < iend)
{
for (int k = 0; k < Block_Size; k++)
{
if (j + k < jend)
{
dx[0] = xj[3 * k + 0] - xi[0];
dx[1] = xj[3 * k + 1] - xi[1];
dx[2] = xj[3 * k + 2] - xi[2];
r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
if (r2 < 1.0)
{
r = sqrtf(r2+0.001*h*h);
W = (1.0-r);
W*=W;
W*=W;//(1-r)^4
W*=(1+4.0*r)*21.0/(2.0*PI*h*h*h);
//Wendland
//dW = (1.0 - r);
//dW *= dW*dW; //(1-r)^3
//dW *= -5*r;
//dW *= 21.0 / (16.0 * PI * h * h * h * h);
rho += m*W;
}
}
}
}
__syncthreads();
}
//ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
}
}
if (id < iend)
{
out[id] = rho;
}
}
} | .file "tmpxft_000c92d4_00000000-6_ker_rho.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif
.type _Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif, @function
_Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq ker_rho(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif, .-_Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif
.globl ker_rho
.type ker_rho, @function
ker_rho:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size ker_rho, .-ker_rho
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ker_rho"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq ker_rho(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | extern "C"
//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64
#define m 0.001/2000
#define PI 3.14159265359f
__global__ void ker_rho(float *out, const float *x, const int *ind, const float h)
{
//int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z
int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];
for (int i = istart; i < iend; i += Block_Size)
{
int id = i + threadIdx.x;
float xi[3];
if (id < iend)
{
xi[0] = x[3 * id + 0];
xi[1] = x[3 * id + 1];
xi[2] = x[3 * id + 2];
}
float dx[3];
float r2;
float r;
float W;
float rho = 0;
__shared__ float xj[Block_Size * 3];
for (int a = -1; a < 2; a++)
{
for (int b = -1; b < 2; b++)
{
if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
{
continue;
}
int Zstart = max((int)blockIdx.z - 1, 0);
int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);
int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];
for (int j = jstart; j < jend; j += Block_Size)
{
int jd = j + threadIdx.x;
if (jd < jend)
{
xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
}
__syncthreads();
if (id < iend)
{
for (int k = 0; k < Block_Size; k++)
{
if (j + k < jend)
{
dx[0] = xj[3 * k + 0] - xi[0];
dx[1] = xj[3 * k + 1] - xi[1];
dx[2] = xj[3 * k + 2] - xi[2];
r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
if (r2 < 1.0)
{
r = sqrtf(r2+0.001*h*h);
W = (1.0-r);
W*=W;
W*=W;//(1-r)^4
W*=(1+4.0*r)*21.0/(2.0*PI*h*h*h);
//Wendland
//dW = (1.0 - r);
//dW *= dW*dW; //(1-r)^3
//dW *= -5*r;
//dW *= 21.0 / (16.0 * PI * h * h * h * h);
rho += m*W;
}
}
}
}
__syncthreads();
}
//ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
}
}
if (id < iend)
{
out[id] = rho;
}
}
} | #include <hip/hip_runtime.h>
extern "C"
//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64
#define m 0.001/2000
#define PI 3.14159265359f
__global__ void ker_rho(float *out, const float *x, const int *ind, const float h)
{
//int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z
int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];
for (int i = istart; i < iend; i += Block_Size)
{
int id = i + threadIdx.x;
float xi[3];
if (id < iend)
{
xi[0] = x[3 * id + 0];
xi[1] = x[3 * id + 1];
xi[2] = x[3 * id + 2];
}
float dx[3];
float r2;
float r;
float W;
float rho = 0;
__shared__ float xj[Block_Size * 3];
for (int a = -1; a < 2; a++)
{
for (int b = -1; b < 2; b++)
{
if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
{
continue;
}
int Zstart = max((int)blockIdx.z - 1, 0);
int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);
int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];
for (int j = jstart; j < jend; j += Block_Size)
{
int jd = j + threadIdx.x;
if (jd < jend)
{
xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
}
__syncthreads();
if (id < iend)
{
for (int k = 0; k < Block_Size; k++)
{
if (j + k < jend)
{
dx[0] = xj[3 * k + 0] - xi[0];
dx[1] = xj[3 * k + 1] - xi[1];
dx[2] = xj[3 * k + 2] - xi[2];
r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
if (r2 < 1.0)
{
r = sqrtf(r2+0.001*h*h);
W = (1.0-r);
W*=W;
W*=W;//(1-r)^4
W*=(1+4.0*r)*21.0/(2.0*PI*h*h*h);
//Wendland
//dW = (1.0 - r);
//dW *= dW*dW; //(1-r)^3
//dW *= -5*r;
//dW *= 21.0 / (16.0 * PI * h * h * h * h);
rho += m*W;
}
}
}
}
__syncthreads();
}
//ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
}
}
if (id < iend)
{
out[id] = rho;
}
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
extern "C"
//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64
#define m 0.001/2000
#define PI 3.14159265359f
__global__ void ker_rho(float *out, const float *x, const int *ind, const float h)
{
//int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z
int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];
for (int i = istart; i < iend; i += Block_Size)
{
int id = i + threadIdx.x;
float xi[3];
if (id < iend)
{
xi[0] = x[3 * id + 0];
xi[1] = x[3 * id + 1];
xi[2] = x[3 * id + 2];
}
float dx[3];
float r2;
float r;
float W;
float rho = 0;
__shared__ float xj[Block_Size * 3];
for (int a = -1; a < 2; a++)
{
for (int b = -1; b < 2; b++)
{
if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
{
continue;
}
int Zstart = max((int)blockIdx.z - 1, 0);
int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);
int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];
for (int j = jstart; j < jend; j += Block_Size)
{
int jd = j + threadIdx.x;
if (jd < jend)
{
xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
}
__syncthreads();
if (id < iend)
{
for (int k = 0; k < Block_Size; k++)
{
if (j + k < jend)
{
dx[0] = xj[3 * k + 0] - xi[0];
dx[1] = xj[3 * k + 1] - xi[1];
dx[2] = xj[3 * k + 2] - xi[2];
r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
if (r2 < 1.0)
{
r = sqrtf(r2+0.001*h*h);
W = (1.0-r);
W*=W;
W*=W;//(1-r)^4
W*=(1+4.0*r)*21.0/(2.0*PI*h*h*h);
//Wendland
//dW = (1.0 - r);
//dW *= dW*dW; //(1-r)^3
//dW *= -5*r;
//dW *= 21.0 / (16.0 * PI * h * h * h * h);
rho += m*W;
}
}
}
}
__syncthreads();
}
//ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
}
}
if (id < iend)
{
out[id] = rho;
}
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected ker_rho
.globl ker_rho
.p2align 8
.type ker_rho,@function
ker_rho:
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x24
s_load_b64 s[8:9], s[0:1], 0x10
s_add_u32 s10, s0, 32
s_addc_u32 s11, s1, 0
s_lshl_b32 s4, s15, 1
s_mov_b32 s17, 0
s_waitcnt lgkmcnt(0)
s_lshl_b32 s12, s3, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_mul_i32 s20, s12, s2
s_mul_i32 s5, s12, s14
s_mul_i32 s6, s20, s13
s_add_i32 s4, s5, s4
s_add_i32 s16, s4, s6
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[4:5], s[16:17], 2
s_add_u32 s4, s8, s4
s_addc_u32 s5, s9, s5
s_or_b32 s16, s16, 1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[6:7], s[16:17], 2
s_add_u32 s6, s8, s6
s_addc_u32 s7, s9, s7
s_clause 0x1
s_load_b32 s21, s[4:5], 0x0
s_load_b32 s22, s[6:7], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s21, s22
s_cbranch_scc1 .LBB0_25
s_load_b32 s16, s[0:1], 0x18
s_mov_b32 s5, 0x401921fb
s_brev_b32 s4, 6
s_mov_b32 s19, 0x3ea0c6f7
s_mov_b32 s18, 0xa0b5ed8d
v_mov_b32_e32 v14, 0
s_waitcnt lgkmcnt(0)
v_cvt_f64_f32_e32 v[1:2], s16
v_mul_f32_e64 v13, s16, s16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
v_mul_f64 v[3:4], v[1:2], s[4:5]
s_mov_b32 s5, 0x3f50624d
s_mov_b32 s4, 0xd2f1a9fc
v_mul_f64 v[5:6], v[1:2], s[4:5]
s_load_b128 s[4:7], s[0:1], 0x0
s_max_i32 s0, s15, 1
s_add_i32 s15, s15, 1
s_add_i32 s1, s3, -1
s_lshl_b32 s3, s0, 1
s_min_i32 s0, s15, s1
s_add_i32 s3, s3, -2
s_lshl_b32 s15, s0, 1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_f64 v[7:8], v[3:4], v[1:2]
v_mul_f64 v[4:5], v[5:6], v[1:2]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_f64 v[6:7], v[7:8], v[1:2]
v_mul_u32_u24_e32 v1, 3, v0
v_lshlrev_b32_e32 v10, 2, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v11, 4, v10
v_add_nc_u32_e32 v12, 8, v10
s_branch .LBB0_3
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s1
s_add_i32 s21, s21, 64
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_ge_i32 s21, s22
s_cbranch_scc1 .LBB0_25
.LBB0_3:
v_add_nc_u32_e32 v8, s21, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s0, s22, v8
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_5
s_waitcnt vmcnt(0)
v_lshl_add_u32 v1, v8, 1, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v2, 31, v1
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b96 v[1:3], v[1:2], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v15, 0
s_mov_b32 s23, -1
s_branch .LBB0_7
.LBB0_6:
s_add_i32 s23, s23, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s23, 2
s_cbranch_scc1 .LBB0_23
.LBB0_7:
s_add_i32 s24, s23, s13
s_mov_b32 s27, -1
s_cmp_gt_i32 s24, -1
s_mul_i32 s26, s24, s20
s_cselect_b32 s25, -1, 0
s_branch .LBB0_9
.LBB0_8:
s_add_i32 s27, s27, 1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_eq_u32 s27, 2
s_cbranch_scc1 .LBB0_6
.LBB0_9:
s_and_not1_b32 vcc_lo, exec_lo, s25
s_cbranch_vccnz .LBB0_8
s_load_b32 s1, s[10:11], 0x0
s_waitcnt lgkmcnt(0)
s_cmp_ge_i32 s24, s1
s_cbranch_scc1 .LBB0_8
s_add_i32 s1, s27, s14
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
s_cmp_lt_i32 s1, 0
s_cselect_b32 s16, -1, 0
s_cmp_ge_i32 s1, s2
s_cselect_b32 s28, -1, 0
s_or_b32 s16, s16, s28
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s16
s_cbranch_vccnz .LBB0_8
s_mul_i32 s1, s1, s12
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_add_i32 s1, s1, s26
s_add_i32 s16, s3, s1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_lshl_b64 s[28:29], s[16:17], 2
s_add_u32 s28, s8, s28
s_addc_u32 s29, s9, s29
s_add_i32 s1, s1, s15
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_or_b32 s16, s1, 1
s_lshl_b64 s[30:31], s[16:17], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s30, s8, s30
s_addc_u32 s31, s9, s31
s_clause 0x1
global_load_b32 v9, v14, s[28:29]
global_load_b32 v16, v14, s[30:31]
s_waitcnt vmcnt(0)
v_cmp_ge_i32_e32 vcc_lo, v9, v16
s_cbranch_vccz .LBB0_14
s_branch .LBB0_8
.LBB0_13:
s_or_b32 exec_lo, exec_lo, s16
v_add_nc_u32_e32 v9, 64, v9
s_barrier
buffer_gl0_inv
v_cmp_lt_i32_e32 vcc_lo, v9, v16
s_cbranch_vccz .LBB0_8
.LBB0_14:
v_add_nc_u32_e32 v17, v9, v0
s_mov_b32 s1, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v17, v16
s_cbranch_execz .LBB0_16
v_lshl_add_u32 v17, v17, 1, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v18, 31, v17
v_lshlrev_b64 v[17:18], 2, v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v17, vcc_lo, s6, v17
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v18, vcc_lo
global_load_b96 v[17:19], v[17:18], off
s_waitcnt vmcnt(0)
ds_store_b32 v10, v17
ds_store_b32 v11, v18
ds_store_b32 v12, v19
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_waitcnt lgkmcnt(0)
s_waitcnt_vscnt null, 0x0
s_barrier
buffer_gl0_inv
s_and_saveexec_b32 s16, s0
s_cbranch_execz .LBB0_13
s_mov_b32 s28, 0
s_mov_b32 s29, 0
s_branch .LBB0_20
.LBB0_18:
s_or_b32 exec_lo, exec_lo, s30
.LBB0_19:
s_add_i32 s29, s29, 1
s_add_i32 s28, s28, 12
s_cmp_lg_u32 s29, 64
s_cbranch_scc0 .LBB0_13
.LBB0_20:
v_add_nc_u32_e32 v17, s29, v9
s_delay_alu instid0(VALU_DEP_1)
v_cmp_ge_i32_e32 vcc_lo, v17, v16
s_cbranch_vccnz .LBB0_19
v_mov_b32_e32 v19, s28
s_mov_b32 s30, exec_lo
ds_load_2addr_b32 v[17:18], v19 offset1:1
ds_load_b32 v19, v19 offset:8
s_waitcnt lgkmcnt(1)
v_dual_sub_f32 v18, v18, v2 :: v_dual_sub_f32 v17, v17, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v18, v18, v18 :: v_dual_sub_f32 v19, v19, v3
v_fmac_f32_e32 v18, v17, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v18, v19, v19
v_div_scale_f32 v17, null, v13, v13, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f32_e32 v19, v17
s_waitcnt_depctr 0xfff
v_fma_f32 v20, -v17, v19, 1.0
v_fmac_f32_e32 v19, v20, v19
v_div_scale_f32 v20, vcc_lo, v18, v13, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v21, v20, v19
v_fma_f32 v22, -v17, v21, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v21, v22, v19
v_fma_f32 v17, -v17, v21, v20
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f32 v17, v17, v19, v21
v_div_fixup_f32 v17, v17, v13, v18
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_f32_e32 1.0, v17
s_cbranch_execz .LBB0_18
v_cvt_f64_f32_e32 v[17:18], v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[17:18], v[4:5], v[17:18]
v_cvt_f32_f64_e32 v17, v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_f32_e32 v18, 0x4f800000, v17
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v17
v_cndmask_b32_e32 v17, v17, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
v_sqrt_f32_e32 v18, v17
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v19, -1, v18
v_add_nc_u32_e32 v20, 1, v18
v_fma_f32 v21, -v19, v18, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v22, -v20, v18, v17
v_cmp_ge_f32_e64 s1, 0, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v18, v18, v19, s1
v_cmp_lt_f32_e64 s1, 0, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v18, v18, v20, s1
v_mul_f32_e32 v19, 0x37800000, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v18, v18, v19, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v17, 0x260
v_cndmask_b32_e32 v27, v18, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[17:18], v27
v_fma_f64 v[17:18], v[17:18], 4.0, 1.0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[17:18], 0x40350000
v_div_scale_f64 v[19:20], null, v[6:7], v[6:7], v[17:18]
v_div_scale_f64 v[25:26], vcc_lo, v[17:18], v[6:7], v[17:18]
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[21:22], v[19:20]
s_waitcnt_depctr 0xfff
v_fma_f64 v[23:24], -v[19:20], v[21:22], 1.0
v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[23:24], -v[19:20], v[21:22], 1.0
v_fma_f64 v[21:22], v[21:22], v[23:24], v[21:22]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[23:24], v[25:26], v[21:22]
v_fma_f64 v[19:20], -v[19:20], v[23:24], v[25:26]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[19:20], v[19:20], v[21:22], v[23:24]
v_sub_f32_e32 v21, 1.0, v27
v_mul_f32_e32 v21, v21, v21
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v21, v21, v21
v_cvt_f64_f32_e32 v[21:22], v21
v_div_fixup_f64 v[17:18], v[19:20], v[6:7], v[17:18]
v_cvt_f64_f32_e32 v[19:20], v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[17:18], v[17:18], v[21:22]
v_cvt_f32_f64_e32 v17, v[17:18]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cvt_f64_f32_e32 v[17:18], v17
v_fma_f64 v[17:18], v[17:18], s[18:19], v[19:20]
s_delay_alu instid0(VALU_DEP_1)
v_cvt_f32_f64_e32 v15, v[17:18]
s_branch .LBB0_18
.LBB0_23:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_2
v_ashrrev_i32_e32 v9, 31, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], 2, v[8:9]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v8, vcc_lo, s4, v8
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v9, vcc_lo, s5, v9, vcc_lo
global_store_b32 v[8:9], v15, off
s_branch .LBB0_2
.LBB0_25:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel ker_rho
.amdhsa_group_segment_fixed_size 768
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 13
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 1
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 28
.amdhsa_next_free_sgpr 32
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size ker_rho, .Lfunc_end0-ker_rho
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 768
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: ker_rho
.private_segment_fixed_size: 0
.sgpr_count: 34
.sgpr_spill_count: 0
.symbol: ker_rho.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 28
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
extern "C"
//must be same as threads!!!
//Block_Size = blockDim.x
#define Block_Size 64
#define m 0.001/2000
#define PI 3.14159265359f
__global__ void ker_rho(float *out, const float *x, const int *ind, const float h)
{
//int IND = gridDim.z * gridDim.y * blockIdx.x + gridDim.z * blockIdx.y + blockIdx.z
int istart = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 0];
int iend = ind[2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * blockIdx.z + 1];
for (int i = istart; i < iend; i += Block_Size)
{
int id = i + threadIdx.x;
float xi[3];
if (id < iend)
{
xi[0] = x[3 * id + 0];
xi[1] = x[3 * id + 1];
xi[2] = x[3 * id + 2];
}
float dx[3];
float r2;
float r;
float W;
float rho = 0;
__shared__ float xj[Block_Size * 3];
for (int a = -1; a < 2; a++)
{
for (int b = -1; b < 2; b++)
{
if ((int)blockIdx.x + a < 0 || (int)blockIdx.x + a >= (int)gridDim.x || (int)blockIdx.y + b < 0 || (int)blockIdx.y + b >= (int)gridDim.y)
{
continue;
}
int Zstart = max((int)blockIdx.z - 1, 0);
int Zend = min((int)blockIdx.z + 1, (int)gridDim.z - 1);
int jstart = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zstart + 0];
int jend = ind[2 * gridDim.z * gridDim.y * (blockIdx.x+a) + 2 * gridDim.z * (blockIdx.y+b) + 2 * Zend + 1];
for (int j = jstart; j < jend; j += Block_Size)
{
int jd = j + threadIdx.x;
if (jd < jend)
{
xj[3 * threadIdx.x + 0] = x[3 * jd + 0];
xj[3 * threadIdx.x + 1] = x[3 * jd + 1];
xj[3 * threadIdx.x + 2] = x[3 * jd + 2];
}
__syncthreads();
if (id < iend)
{
for (int k = 0; k < Block_Size; k++)
{
if (j + k < jend)
{
dx[0] = xj[3 * k + 0] - xi[0];
dx[1] = xj[3 * k + 1] - xi[1];
dx[2] = xj[3 * k + 2] - xi[2];
r2 = (dx[0] * dx[0] + dx[1] * dx[1] + dx[2] * dx[2]) / (h * h);
if (r2 < 1.0)
{
r = sqrtf(r2+0.001*h*h);
W = (1.0-r);
W*=W;
W*=W;//(1-r)^4
W*=(1+4.0*r)*21.0/(2.0*PI*h*h*h);
//Wendland
//dW = (1.0 - r);
//dW *= dW*dW; //(1-r)^3
//dW *= -5*r;
//dW *= 21.0 / (16.0 * PI * h * h * h * h);
rho += m*W;
}
}
}
}
__syncthreads();
}
//ivol = 2 * gridDim.z * gridDim.y * blockIdx.x + 2 * gridDim.z * blockIdx.y + 2 * Zend;
}
}
if (id < iend)
{
out[id] = rho;
}
}
} | .text
.file "ker_rho.hip"
.globl __device_stub__ker_rho # -- Begin function __device_stub__ker_rho
.p2align 4, 0x90
.type __device_stub__ker_rho,@function
__device_stub__ker_rho: # @__device_stub__ker_rho
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $ker_rho, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__ker_rho, .Lfunc_end0-__device_stub__ker_rho
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ker_rho, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type ker_rho,@object # @ker_rho
.section .rodata,"a",@progbits
.globl ker_rho
.p2align 3, 0x0
ker_rho:
.quad __device_stub__ker_rho
.size ker_rho, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "ker_rho"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__ker_rho
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym ker_rho
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000c92d4_00000000-6_ker_rho.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif
.type _Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif, @function
_Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif:
.LFB2051:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movss %xmm0, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq ker_rho(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif, .-_Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif
.globl ker_rho
.type ker_rho, @function
ker_rho:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z33__device_stub__Z7ker_rhoPfPKfPKifPfPKfPKif
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size ker_rho, .-ker_rho
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "ker_rho"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq ker_rho(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "ker_rho.hip"
.globl __device_stub__ker_rho # -- Begin function __device_stub__ker_rho
.p2align 4, 0x90
.type __device_stub__ker_rho,@function
__device_stub__ker_rho: # @__device_stub__ker_rho
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movss %xmm0, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $ker_rho, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size __device_stub__ker_rho, .Lfunc_end0-__device_stub__ker_rho
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $ker_rho, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type ker_rho,@object # @ker_rho
.section .rodata,"a",@progbits
.globl ker_rho
.p2align 3, 0x0
ker_rho:
.quad __device_stub__ker_rho
.size ker_rho, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "ker_rho"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __device_stub__ker_rho
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym ker_rho
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <bits/stdc++.h>
#include <cuda.h>
using namespace std;
#define N ((int)1e3)
#define CEIL(a, b) ((a-1)/b +1)
__global__ void multiply(float *d_a, float *d_b, float *d_c) {
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if(x >= N || y >= N)
return;
float cij=0.0;
for(int k=0; k<N; k++)
cij += d_a[x*N + k] * d_b[k*N + y];
d_c[x*N + y] = cij;
}
template <class T>
void testSolution(T *h_a, T *h_b, T *h_c, float precision=0.0) {
int errors = 0;
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
float exp = 0.0, act;
for(int k=0; k<N; k++)
exp += h_a[i*N + k] * h_b[k*N + j];
act = h_c[i*N + j];
if(abs(act-exp) / (max(exp, precision)) > precision) {
errors++;
if(errors <= 10)
printf("Test failed at index : (%d, %d) [Expected: %10.2f | Got: %10.2f]\n",
i, j, exp, act);
}
}
if(errors)
printf("\n%d Tests failed!\n\n", errors);
else
printf("All tests passed !\n\n");
}
int main() {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
// Allocate host memory
h_a = new float[N*N];
h_b = new float[N*N];
h_c = new float[N*N];
printf("\nSize of matrices : %d x %d\n\n", N, N);
srand(time(0));
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
h_a[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
h_b[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
}
// Allocate memory on device
cudaMalloc((void**)&d_a, N*N*sizeof(float));
cudaMalloc((void**)&d_b, N*N*sizeof(float));
cudaMalloc((void**)&d_c, N*N*sizeof(float));
//Copy data into device memory
cudaMemcpy(d_a, h_a, N*N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, N*N*sizeof(float), cudaMemcpyHostToDevice);
// Kernel call
dim3 grid(CEIL(N, 32), CEIL(N, 32), 1);
dim3 block(32, 32, 1);
multiply <<<grid, block>>> (d_a, d_b, d_c);
cudaThreadSynchronize();
// Copy data back to host
cudaMemcpy(h_c, d_c, N*N*sizeof(float), cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
testSolution(h_a, h_b, h_c, 1e-3); //Tolerates 0.1% relative error
// Free host memory
delete[] h_a, h_b, h_c;
} | code for sm_80
Function : _Z8multiplyPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x3e7, PT ; /* 0x000003e70000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R2 ; /* 0x0000000007077a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R7, 0x3e7, P0 ; /* 0x000003e70700780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R7, R7, 0x3e8, RZ ; /* 0x000003e807077824 */
/* 0x000fe200078e02ff */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*00d0*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe20000000f00 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00f0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fc80000000a00 */
/*0100*/ IMAD.WIDE R2, R7, R6, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0206 */
/*0110*/ IADD3 R2, P0, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R3, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff037210 */
/* 0x000fc800007fe4ff */
/*0130*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0140*/ LDG.E R8, [R2.64+-0x10] ; /* 0xfffff00402087981 */
/* 0x000ea2000c1e1900 */
/*0150*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fc60008000f00 */
/*0160*/ LDG.E R22, [R2.64+-0xc] ; /* 0xfffff40402167981 */
/* 0x000ee4000c1e1900 */
/*0170*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x000fe400078e0204 */
/*0180*/ LDG.E R20, [R2.64+-0x8] ; /* 0xfffff80402147981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R25, [R4.64+0xfa0] ; /* 0x000fa00404197981 */
/* 0x000ee8000c1e1900 */
/*01b0*/ LDG.E R23, [R4.64+0x1f40] ; /* 0x001f400404177981 */
/* 0x000f28000c1e1900 */
/*01c0*/ LDG.E R21, [R2.64+-0x4] ; /* 0xfffffc0402157981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R18, [R4.64+0x2ee0] ; /* 0x002ee00404127981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R19, [R4.64+0x3e80] ; /* 0x003e800404137981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R17, [R4.64+0x4e20] ; /* 0x004e200404117981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R15, [R4.64+0x5dc0] ; /* 0x005dc004040f7981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c04020a7981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R13, [R4.64+0x6d60] ; /* 0x006d6004040d7981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R27, [R2.64+0x8c] ; /* 0x00008c04021b7981 */
/* 0x000162000c1e1900 */
/*0270*/ FFMA R24, R11, R8, R24 ; /* 0x000000080b187223 */
/* 0x004fc60000000018 */
/*0280*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100402087981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R11, [R4.64+0x7d00] ; /* 0x007d0004040b7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x008fc60000000018 */
/*02b0*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140402167981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ FFMA R24, R23, R20, R24 ; /* 0x0000001417187223 */
/* 0x010fc60000000018 */
/*02d0*/ LDG.E R25, [R4.64+0x8ca0] ; /* 0x008ca00404197981 */
/* 0x000ee8000c1e1900 */
/*02e0*/ LDG.E R20, [R2.64+0x18] ; /* 0x0000180402147981 */
/* 0x000f22000c1e1900 */
/*02f0*/ FFMA R24, R18, R21, R24 ; /* 0x0000001512187223 */
/* 0x020fc60000000018 */
/*0300*/ LDG.E R23, [R4.64+0x9c40] ; /* 0x009c400404177981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R18, [R2.64+0x1c] ; /* 0x00001c0402127981 */
/* 0x000f62000c1e1900 */
/*0320*/ FFMA R24, R19, R16, R24 ; /* 0x0000001013187223 */
/* 0x000fc60000000018 */
/*0330*/ LDG.E R21, [R4.64+0xabe0] ; /* 0x00abe00404157981 */
/* 0x000f68000c1e1900 */
/*0340*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000f62000c1e1900 */
/*0350*/ FFMA R24, R17, R14, R24 ; /* 0x0000000e11187223 */
/* 0x000fc60000000018 */
/*0360*/ LDG.E R19, [R4.64+0xbb80] ; /* 0x00bb800404137981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000f62000c1e1900 */
/*0380*/ FFMA R24, R15, R12, R24 ; /* 0x0000000c0f187223 */
/* 0x000fc60000000018 */
/*0390*/ LDG.E R17, [R4.64+0xcb20] ; /* 0x00cb200404117981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R12, [R2.64+0x28] ; /* 0x00002804020c7981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R15, [R4.64+0xdac0] ; /* 0x00dac004040f7981 */
/* 0x000f62000c1e1900 */
/*03c0*/ FFMA R24, R13, R10, R24 ; /* 0x0000000a0d187223 */
/* 0x000fc60000000018 */
/*03d0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */
/* 0x000f68000c1e1900 */
/*03e0*/ LDG.E R13, [R4.64+0xea60] ; /* 0x00ea6004040d7981 */
/* 0x000f62000c1e1900 */
/*03f0*/ FFMA R24, R11, R8, R24 ; /* 0x000000080b187223 */
/* 0x004fc60000000018 */
/*0400*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300402087981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R11, [R4.64+0xfa00] ; /* 0x00fa0004040b7981 */
/* 0x000ea2000c1e1900 */
/*0420*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x008fc60000000018 */
/*0430*/ LDG.E R22, [R2.64+0x34] ; /* 0x0000340402167981 */
/* 0x000ee8000c1e1900 */
/*0440*/ LDG.E R25, [R4.64+0x109a0] ; /* 0x0109a00404197981 */
/* 0x000ee2000c1e1900 */
/*0450*/ FFMA R24, R23, R20, R24 ; /* 0x0000001417187223 */
/* 0x010fc60000000018 */
/*0460*/ LDG.E R20, [R2.64+0x38] ; /* 0x0000380402147981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R23, [R4.64+0x11940] ; /* 0x0119400404177981 */
/* 0x000f22000c1e1900 */
/*0480*/ FFMA R24, R21, R18, R24 ; /* 0x0000001215187223 */
/* 0x020fc60000000018 */
/*0490*/ LDG.E R18, [R2.64+0x3c] ; /* 0x00003c0402127981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R21, [R4.64+0x128e0] ; /* 0x0128e00404157981 */
/* 0x000f62000c1e1900 */
/*04b0*/ FFMA R24, R19, R16, R24 ; /* 0x0000001013187223 */
/* 0x000fc60000000018 */
/*04c0*/ LDG.E R19, [R2.64+0x40] ; /* 0x0000400402137981 */
/* 0x000f68000c1e1900 */
/*04d0*/ LDG.E R16, [R4.64+0x13880] ; /* 0x0138800404107981 */
/* 0x000f62000c1e1900 */
/*04e0*/ FFMA R24, R17, R14, R24 ; /* 0x0000000e11187223 */
/* 0x000fc60000000018 */
/*04f0*/ LDG.E R17, [R2.64+0x44] ; /* 0x0000440402117981 */
/* 0x000f68000c1e1900 */
/*0500*/ LDG.E R14, [R4.64+0x14820] ; /* 0x01482004040e7981 */
/* 0x000f62000c1e1900 */
/*0510*/ FFMA R24, R15, R12, R24 ; /* 0x0000000c0f187223 */
/* 0x000fc60000000018 */
/*0520*/ LDG.E R15, [R2.64+0x48] ; /* 0x00004804020f7981 */
/* 0x000f68000c1e1900 */
/*0530*/ LDG.E R12, [R4.64+0x157c0] ; /* 0x0157c004040c7981 */
/* 0x000f62000c1e1900 */
/*0540*/ FFMA R24, R13, R10, R24 ; /* 0x0000000a0d187223 */
/* 0x000fc60000000018 */
/*0550*/ LDG.E R13, [R2.64+0x4c] ; /* 0x00004c04020d7981 */
/* 0x000f68000c1e1900 */
/*0560*/ LDG.E R10, [R4.64+0x16760] ; /* 0x01676004040a7981 */
/* 0x000f62000c1e1900 */
/*0570*/ FFMA R24, R11, R8, R24 ; /* 0x000000080b187223 */
/* 0x004fc60000000018 */
/*0580*/ LDG.E R11, [R2.64+0x50] ; /* 0x00005004020b7981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R8, [R4.64+0x17700] ; /* 0x0177000404087981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x008fc60000000018 */
/*05b0*/ LDG.E R22, [R2.64+0x54] ; /* 0x0000540402167981 */
/* 0x000ee8000c1e1900 */
/*05c0*/ LDG.E R25, [R4.64+0x186a0] ; /* 0x0186a00404197981 */
/* 0x000ee2000c1e1900 */
/*05d0*/ FFMA R24, R23, R20, R24 ; /* 0x0000001417187223 */
/* 0x010fc60000000018 */
/*05e0*/ LDG.E R23, [R2.64+0x58] ; /* 0x0000580402177981 */
/* 0x000f28000c1e1900 */
/*05f0*/ LDG.E R20, [R4.64+0x19640] ; /* 0x0196400404147981 */
/* 0x000f22000c1e1900 */
/*0600*/ FFMA R24, R21, R18, R24 ; /* 0x0000001215187223 */
/* 0x020fc60000000018 */
/*0610*/ LDG.E R21, [R2.64+0x5c] ; /* 0x00005c0402157981 */
/* 0x000f68000c1e1900 */
/*0620*/ LDG.E R18, [R4.64+0x1a5e0] ; /* 0x01a5e00404127981 */
/* 0x000f62000c1e1900 */
/*0630*/ FFMA R24, R16, R19, R24 ; /* 0x0000001310187223 */
/* 0x000fc60000000018 */
/*0640*/ LDG.E R19, [R2.64+0x60] ; /* 0x0000600402137981 */
/* 0x000f68000c1e1900 */
/*0650*/ LDG.E R16, [R4.64+0x1b580] ; /* 0x01b5800404107981 */
/* 0x000f62000c1e1900 */
/*0660*/ FFMA R24, R14, R17, R24 ; /* 0x000000110e187223 */
/* 0x000fc60000000018 */
/*0670*/ LDG.E R17, [R2.64+0x64] ; /* 0x0000640402117981 */
/* 0x000f68000c1e1900 */
/*0680*/ LDG.E R14, [R4.64+0x1c520] ; /* 0x01c52004040e7981 */
/* 0x000f62000c1e1900 */
/*0690*/ FFMA R24, R12, R15, R24 ; /* 0x0000000f0c187223 */
/* 0x000fc60000000018 */
/*06a0*/ LDG.E R15, [R2.64+0x68] ; /* 0x00006804020f7981 */
/* 0x000f68000c1e1900 */
/*06b0*/ LDG.E R12, [R4.64+0x1d4c0] ; /* 0x01d4c004040c7981 */
/* 0x000f62000c1e1900 */
/*06c0*/ FFMA R24, R10, R13, R24 ; /* 0x0000000d0a187223 */
/* 0x000fc60000000018 */
/*06d0*/ LDG.E R13, [R2.64+0x6c] ; /* 0x00006c04020d7981 */
/* 0x000f68000c1e1900 */
/*06e0*/ LDG.E R10, [R4.64+0x1e460] ; /* 0x01e46004040a7981 */
/* 0x000f62000c1e1900 */
/*06f0*/ FFMA R24, R8, R11, R24 ; /* 0x0000000b08187223 */
/* 0x004fc60000000018 */
/*0700*/ LDG.E R8, [R2.64+0x70] ; /* 0x0000700402087981 */
/* 0x0000a8000c1e1900 */
/*0710*/ LDG.E R11, [R4.64+0x1f400] ; /* 0x01f40004040b7981 */
/* 0x000ea2000c1e1900 */
/*0720*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x008fc60000000018 */
/*0730*/ LDG.E R25, [R2.64+0x74] ; /* 0x0000740402197981 */
/* 0x0000e8000c1e1900 */
/*0740*/ LDG.E R22, [R4.64+0x203a0] ; /* 0x0203a00404167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ FFMA R24, R20, R23, R24 ; /* 0x0000001714187223 */
/* 0x010fc60000000018 */
/*0760*/ LDG.E R23, [R2.64+0x78] ; /* 0x0000780402177981 */
/* 0x000128000c1e1900 */
/*0770*/ LDG.E R20, [R4.64+0x21340] ; /* 0x0213400404147981 */
/* 0x000f22000c1e1900 */
/*0780*/ FFMA R24, R18, R21, R24 ; /* 0x0000001512187223 */
/* 0x020fc60000000018 */
/*0790*/ LDG.E R21, [R2.64+0x7c] ; /* 0x00007c0402157981 */
/* 0x000168000c1e1900 */
/*07a0*/ LDG.E R18, [R4.64+0x222e0] ; /* 0x0222e00404127981 */
/* 0x000f62000c1e1900 */
/*07b0*/ FFMA R24, R16, R19, R24 ; /* 0x0000001310187223 */
/* 0x000fc60000000018 */
/*07c0*/ LDG.E R19, [R2.64+0x80] ; /* 0x0000800402137981 */
/* 0x000168000c1e1900 */
/*07d0*/ LDG.E R16, [R4.64+0x23280] ; /* 0x0232800404107981 */
/* 0x000f62000c1e1900 */
/*07e0*/ FFMA R24, R14, R17, R24 ; /* 0x000000110e187223 */
/* 0x000fc60000000018 */
/*07f0*/ LDG.E R17, [R2.64+0x84] ; /* 0x0000840402117981 */
/* 0x000168000c1e1900 */
/*0800*/ LDG.E R14, [R4.64+0x24220] ; /* 0x02422004040e7981 */
/* 0x000f62000c1e1900 */
/*0810*/ FFMA R26, R12, R15, R24 ; /* 0x0000000f0c1a7223 */
/* 0x000fc60000000018 */
/*0820*/ LDG.E R12, [R2.64+0x88] ; /* 0x00008804020c7981 */
/* 0x000168000c1e1900 */
/*0830*/ LDG.E R15, [R4.64+0x251c0] ; /* 0x0251c004040f7981 */
/* 0x000f68000c1e1900 */
/*0840*/ LDG.E R24, [R4.64+0x26160] ; /* 0x0261600404187981 */
/* 0x000f62000c1e1900 */
/*0850*/ FFMA R10, R10, R13, R26 ; /* 0x0000000d0a0a7223 */
/* 0x000fe2000000001a */
/*0860*/ IADD3 R9, R9, 0x28, RZ ; /* 0x0000002809097810 */
/* 0x000fc80007ffe0ff */
/*0870*/ ISETP.NE.AND P0, PT, R9, 0x3e8, PT ; /* 0x000003e80900780c */
/* 0x000fe20003f05270 */
/*0880*/ UIADD3 UR6, UP0, UR6, 0x27100, URZ ; /* 0x0002710006067890 */
/* 0x000fe2000ff1e03f */
/*0890*/ IADD3 R2, P1, R2, 0xa0, RZ ; /* 0x000000a002027810 */
/* 0x001fc60007f3e0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*08c0*/ FFMA R8, R11, R8, R10 ; /* 0x000000080b087223 */
/* 0x004fc8000000000a */
/*08d0*/ FFMA R8, R22, R25, R8 ; /* 0x0000001916087223 */
/* 0x008fc80000000008 */
/*08e0*/ FFMA R8, R20, R23, R8 ; /* 0x0000001714087223 */
/* 0x010fc80000000008 */
/*08f0*/ FFMA R8, R18, R21, R8 ; /* 0x0000001512087223 */
/* 0x020fc80000000008 */
/*0900*/ FFMA R8, R16, R19, R8 ; /* 0x0000001310087223 */
/* 0x000fc80000000008 */
/*0910*/ FFMA R8, R14, R17, R8 ; /* 0x000000110e087223 */
/* 0x000fc80000000008 */
/*0920*/ FFMA R8, R15, R12, R8 ; /* 0x0000000c0f087223 */
/* 0x000fc80000000008 */
/*0930*/ FFMA R24, R24, R27, R8 ; /* 0x0000001b18187223 */
/* 0x000fe20000000008 */
/*0940*/ @P0 BRA 0x130 ; /* 0xfffff7e000000947 */
/* 0x000fea000383ffff */
/*0950*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x000fca0007ffe0ff */
/*0960*/ IMAD.WIDE R6, R7, R6, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fca00078e0206 */
/*0970*/ STG.E [R6.64], R24 ; /* 0x0000001806007986 */
/* 0x000fe2000c101904 */
/*0980*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0990*/ BRA 0x990; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <bits/stdc++.h>
#include <cuda.h>
using namespace std;
#define N ((int)1e3)
#define CEIL(a, b) ((a-1)/b +1)
__global__ void multiply(float *d_a, float *d_b, float *d_c) {
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if(x >= N || y >= N)
return;
float cij=0.0;
for(int k=0; k<N; k++)
cij += d_a[x*N + k] * d_b[k*N + y];
d_c[x*N + y] = cij;
}
template <class T>
void testSolution(T *h_a, T *h_b, T *h_c, float precision=0.0) {
int errors = 0;
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
float exp = 0.0, act;
for(int k=0; k<N; k++)
exp += h_a[i*N + k] * h_b[k*N + j];
act = h_c[i*N + j];
if(abs(act-exp) / (max(exp, precision)) > precision) {
errors++;
if(errors <= 10)
printf("Test failed at index : (%d, %d) [Expected: %10.2f | Got: %10.2f]\n",
i, j, exp, act);
}
}
if(errors)
printf("\n%d Tests failed!\n\n", errors);
else
printf("All tests passed !\n\n");
}
int main() {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
// Allocate host memory
h_a = new float[N*N];
h_b = new float[N*N];
h_c = new float[N*N];
printf("\nSize of matrices : %d x %d\n\n", N, N);
srand(time(0));
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
h_a[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
h_b[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
}
// Allocate memory on device
cudaMalloc((void**)&d_a, N*N*sizeof(float));
cudaMalloc((void**)&d_b, N*N*sizeof(float));
cudaMalloc((void**)&d_c, N*N*sizeof(float));
//Copy data into device memory
cudaMemcpy(d_a, h_a, N*N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, N*N*sizeof(float), cudaMemcpyHostToDevice);
// Kernel call
dim3 grid(CEIL(N, 32), CEIL(N, 32), 1);
dim3 block(32, 32, 1);
multiply <<<grid, block>>> (d_a, d_b, d_c);
cudaThreadSynchronize();
// Copy data back to host
cudaMemcpy(h_c, d_c, N*N*sizeof(float), cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
testSolution(h_a, h_b, h_c, 1e-3); //Tolerates 0.1% relative error
// Free host memory
delete[] h_a, h_b, h_c;
} | .file "tmpxft_00189ddf_00000000-6_matrixMultiplication.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10863:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8multiplyPfS_S_PfS_S_
.type _Z31__device_stub__Z8multiplyPfS_S_PfS_S_, @function
_Z31__device_stub__Z8multiplyPfS_S_PfS_S_:
.LFB10885:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10885:
.size _Z31__device_stub__Z8multiplyPfS_S_PfS_S_, .-_Z31__device_stub__Z8multiplyPfS_S_PfS_S_
.globl _Z8multiplyPfS_S_
.type _Z8multiplyPfS_S_, @function
_Z8multiplyPfS_S_:
.LFB10886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8multiplyPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10886:
.size _Z8multiplyPfS_S_, .-_Z8multiplyPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8multiplyPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10888:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10888:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z12testSolutionIfEvPT_S1_S1_f.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Test failed at index : (%d, %d) [Expected: %10.2f | Got: %10.2f]\n"
.section .rodata._Z12testSolutionIfEvPT_S1_S1_f.str1.1,"aMS",@progbits,1
.LC4:
.string "\n%d Tests failed!\n\n"
.LC5:
.string "All tests passed !\n\n"
.section .text._Z12testSolutionIfEvPT_S1_S1_f,"axG",@progbits,_Z12testSolutionIfEvPT_S1_S1_f,comdat
.weak _Z12testSolutionIfEvPT_S1_S1_f
.type _Z12testSolutionIfEvPT_S1_S1_f, @function
_Z12testSolutionIfEvPT_S1_S1_f:
.LFB11567:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 8(%rsp)
movl $0, %r15d
movl $0, 12(%rsp)
movl $0, %r14d
jmp .L14
.L16:
addl $1, %ebp
addq $4, %r12
addq $4, %rbx
cmpl $1000, %ebp
je .L18
.L20:
leaq 0(%r13,%r15), %rdx
leaq -4000000(%rbx), %rax
movl $0x00000000, (%rsp)
.L15:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss (%rsp), %xmm0
movss %xmm0, (%rsp)
addq $4, %rdx
addq $4000, %rax
cmpq %rbx, %rax
jne .L15
movss (%r12), %xmm3
movss %xmm3, 4(%rsp)
movaps %xmm0, %xmm1
movss 8(%rsp), %xmm0
call fmaxf@PLT
movaps %xmm0, %xmm1
movss 4(%rsp), %xmm3
subss (%rsp), %xmm3
movaps %xmm3, %xmm0
andps .LC2(%rip), %xmm0
divss %xmm1, %xmm0
comiss 8(%rsp), %xmm0
jbe .L16
addl $1, %r14d
cmpl $10, %r14d
jg .L16
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 4(%rsp), %xmm1
movl %ebp, %ecx
movl 12(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L16
.L18:
addl $1, 12(%rsp)
movl 12(%rsp), %eax
addq $4000, %r15
cmpl $1000, %eax
je .L19
.L14:
movq 24(%rsp), %rax
leaq (%rax,%r15), %r12
movq 16(%rsp), %rax
leaq 4000000(%rax), %rbx
movl $0, %ebp
jmp .L20
.L19:
testl %r14d, %r14d
je .L21
movl %r14d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L13:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.cfi_endproc
.LFE11567:
.size _Z12testSolutionIfEvPT_S1_S1_f, .-_Z12testSolutionIfEvPT_S1_S1_f
.section .rodata.str1.1
.LC6:
.string "\nSize of matrices : %d x %d\n\n"
.text
.globl main
.type main, @function
main:
.LFB10860:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r14
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r15
movl $4000000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $1000, %ecx
movl $1000, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r14, %rbp
movq %r15, %r12
leaq 4000000(%r14), %r13
.L27:
movl $0, %ebx
.L28:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm2, %xmm2
cvtsi2sdl %eax, %xmm2
movsd %xmm2, (%rsp)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd (%rsp), %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm3, %xmm3
cvtsi2sdl %eax, %xmm3
movsd %xmm3, (%rsp)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd (%rsp), %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rbx)
addq $4, %rbx
cmpq $4000, %rbx
jne .L28
addq $4000, %rbp
addq $4000, %r12
cmpq %r13, %rbp
jne .L27
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $4000000, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movss .LC7(%rip), %xmm0
movq %rbx, %rdx
movq %r15, %rsi
movq %r14, %rdi
call _Z12testSolutionIfEvPT_S1_S1_f
movq %r14, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z8multiplyPfS_S_PfS_S_
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10860:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <bits/stdc++.h>
#include <cuda.h>
using namespace std;
#define N ((int)1e3)
#define CEIL(a, b) ((a-1)/b +1)
__global__ void multiply(float *d_a, float *d_b, float *d_c) {
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if(x >= N || y >= N)
return;
float cij=0.0;
for(int k=0; k<N; k++)
cij += d_a[x*N + k] * d_b[k*N + y];
d_c[x*N + y] = cij;
}
template <class T>
void testSolution(T *h_a, T *h_b, T *h_c, float precision=0.0) {
int errors = 0;
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
float exp = 0.0, act;
for(int k=0; k<N; k++)
exp += h_a[i*N + k] * h_b[k*N + j];
act = h_c[i*N + j];
if(abs(act-exp) / (max(exp, precision)) > precision) {
errors++;
if(errors <= 10)
printf("Test failed at index : (%d, %d) [Expected: %10.2f | Got: %10.2f]\n",
i, j, exp, act);
}
}
if(errors)
printf("\n%d Tests failed!\n\n", errors);
else
printf("All tests passed !\n\n");
}
int main() {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
// Allocate host memory
h_a = new float[N*N];
h_b = new float[N*N];
h_c = new float[N*N];
printf("\nSize of matrices : %d x %d\n\n", N, N);
srand(time(0));
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
h_a[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
h_b[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
}
// Allocate memory on device
cudaMalloc((void**)&d_a, N*N*sizeof(float));
cudaMalloc((void**)&d_b, N*N*sizeof(float));
cudaMalloc((void**)&d_c, N*N*sizeof(float));
//Copy data into device memory
cudaMemcpy(d_a, h_a, N*N*sizeof(float), cudaMemcpyHostToDevice);
cudaMemcpy(d_b, h_b, N*N*sizeof(float), cudaMemcpyHostToDevice);
// Kernel call
dim3 grid(CEIL(N, 32), CEIL(N, 32), 1);
dim3 block(32, 32, 1);
multiply <<<grid, block>>> (d_a, d_b, d_c);
cudaThreadSynchronize();
// Copy data back to host
cudaMemcpy(h_c, d_c, N*N*sizeof(float), cudaMemcpyDeviceToHost);
// Free device memory
cudaFree(d_a);
cudaFree(d_b);
cudaFree(d_c);
testSolution(h_a, h_b, h_c, 1e-3); //Tolerates 0.1% relative error
// Free host memory
delete[] h_a, h_b, h_c;
} | #include <bits/stdc++.h>
#include <hip/hip_runtime.h>
using namespace std;
#define N ((int)1e3)
#define CEIL(a, b) ((a-1)/b +1)
__global__ void multiply(float *d_a, float *d_b, float *d_c) {
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if(x >= N || y >= N)
return;
float cij=0.0;
for(int k=0; k<N; k++)
cij += d_a[x*N + k] * d_b[k*N + y];
d_c[x*N + y] = cij;
}
template <class T>
void testSolution(T *h_a, T *h_b, T *h_c, float precision=0.0) {
int errors = 0;
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
float exp = 0.0, act;
for(int k=0; k<N; k++)
exp += h_a[i*N + k] * h_b[k*N + j];
act = h_c[i*N + j];
if(abs(act-exp) / (max(exp, precision)) > precision) {
errors++;
if(errors <= 10)
printf("Test failed at index : (%d, %d) [Expected: %10.2f | Got: %10.2f]\n",
i, j, exp, act);
}
}
if(errors)
printf("\n%d Tests failed!\n\n", errors);
else
printf("All tests passed !\n\n");
}
int main() {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
// Allocate host memory
h_a = new float[N*N];
h_b = new float[N*N];
h_c = new float[N*N];
printf("\nSize of matrices : %d x %d\n\n", N, N);
srand(time(0));
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
h_a[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
h_b[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
}
// Allocate memory on device
hipMalloc((void**)&d_a, N*N*sizeof(float));
hipMalloc((void**)&d_b, N*N*sizeof(float));
hipMalloc((void**)&d_c, N*N*sizeof(float));
//Copy data into device memory
hipMemcpy(d_a, h_a, N*N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, N*N*sizeof(float), hipMemcpyHostToDevice);
// Kernel call
dim3 grid(CEIL(N, 32), CEIL(N, 32), 1);
dim3 block(32, 32, 1);
multiply <<<grid, block>>> (d_a, d_b, d_c);
hipDeviceSynchronize();
// Copy data back to host
hipMemcpy(h_c, d_c, N*N*sizeof(float), hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
testSolution(h_a, h_b, h_c, 1e-3); //Tolerates 0.1% relative error
// Free host memory
delete[] h_a, h_b, h_c;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <bits/stdc++.h>
#include <hip/hip_runtime.h>
using namespace std;
#define N ((int)1e3)
#define CEIL(a, b) ((a-1)/b +1)
__global__ void multiply(float *d_a, float *d_b, float *d_c) {
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if(x >= N || y >= N)
return;
float cij=0.0;
for(int k=0; k<N; k++)
cij += d_a[x*N + k] * d_b[k*N + y];
d_c[x*N + y] = cij;
}
template <class T>
void testSolution(T *h_a, T *h_b, T *h_c, float precision=0.0) {
int errors = 0;
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
float exp = 0.0, act;
for(int k=0; k<N; k++)
exp += h_a[i*N + k] * h_b[k*N + j];
act = h_c[i*N + j];
if(abs(act-exp) / (max(exp, precision)) > precision) {
errors++;
if(errors <= 10)
printf("Test failed at index : (%d, %d) [Expected: %10.2f | Got: %10.2f]\n",
i, j, exp, act);
}
}
if(errors)
printf("\n%d Tests failed!\n\n", errors);
else
printf("All tests passed !\n\n");
}
int main() {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
// Allocate host memory
h_a = new float[N*N];
h_b = new float[N*N];
h_c = new float[N*N];
printf("\nSize of matrices : %d x %d\n\n", N, N);
srand(time(0));
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
h_a[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
h_b[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
}
// Allocate memory on device
hipMalloc((void**)&d_a, N*N*sizeof(float));
hipMalloc((void**)&d_b, N*N*sizeof(float));
hipMalloc((void**)&d_c, N*N*sizeof(float));
//Copy data into device memory
hipMemcpy(d_a, h_a, N*N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, N*N*sizeof(float), hipMemcpyHostToDevice);
// Kernel call
dim3 grid(CEIL(N, 32), CEIL(N, 32), 1);
dim3 block(32, 32, 1);
multiply <<<grid, block>>> (d_a, d_b, d_c);
hipDeviceSynchronize();
// Copy data back to host
hipMemcpy(h_c, d_c, N*N*sizeof(float), hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
testSolution(h_a, h_b, h_c, 1e-3); //Tolerates 0.1% relative error
// Free host memory
delete[] h_a, h_b, h_c;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPfS_S_
.globl _Z8multiplyPfS_S_
.p2align 8
.type _Z8multiplyPfS_S_,@function
_Z8multiplyPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x3e8, v2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, 0x3e8
v_mov_b32_e32 v4, 0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v2, v1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v7, vcc_lo, v5, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_nc_u32_e32 v2, 0x3e8, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0xfa0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v7, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v3, v7
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, 0x3e8, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPfS_S_, .Lfunc_end0-_Z8multiplyPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <bits/stdc++.h>
#include <hip/hip_runtime.h>
using namespace std;
#define N ((int)1e3)
#define CEIL(a, b) ((a-1)/b +1)
__global__ void multiply(float *d_a, float *d_b, float *d_c) {
int x = blockIdx.x*blockDim.x + threadIdx.x;
int y = blockIdx.y*blockDim.y + threadIdx.y;
if(x >= N || y >= N)
return;
float cij=0.0;
for(int k=0; k<N; k++)
cij += d_a[x*N + k] * d_b[k*N + y];
d_c[x*N + y] = cij;
}
template <class T>
void testSolution(T *h_a, T *h_b, T *h_c, float precision=0.0) {
int errors = 0;
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
float exp = 0.0, act;
for(int k=0; k<N; k++)
exp += h_a[i*N + k] * h_b[k*N + j];
act = h_c[i*N + j];
if(abs(act-exp) / (max(exp, precision)) > precision) {
errors++;
if(errors <= 10)
printf("Test failed at index : (%d, %d) [Expected: %10.2f | Got: %10.2f]\n",
i, j, exp, act);
}
}
if(errors)
printf("\n%d Tests failed!\n\n", errors);
else
printf("All tests passed !\n\n");
}
int main() {
float *h_a, *h_b, *h_c;
float *d_a, *d_b, *d_c;
// Allocate host memory
h_a = new float[N*N];
h_b = new float[N*N];
h_c = new float[N*N];
printf("\nSize of matrices : %d x %d\n\n", N, N);
srand(time(0));
for(int i=0; i<N; i++)
for(int j=0; j<N; j++) {
h_a[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
h_b[i*N + j] = (rand()%N) *1.0/ (rand()%N +1);
}
// Allocate memory on device
hipMalloc((void**)&d_a, N*N*sizeof(float));
hipMalloc((void**)&d_b, N*N*sizeof(float));
hipMalloc((void**)&d_c, N*N*sizeof(float));
//Copy data into device memory
hipMemcpy(d_a, h_a, N*N*sizeof(float), hipMemcpyHostToDevice);
hipMemcpy(d_b, h_b, N*N*sizeof(float), hipMemcpyHostToDevice);
// Kernel call
dim3 grid(CEIL(N, 32), CEIL(N, 32), 1);
dim3 block(32, 32, 1);
multiply <<<grid, block>>> (d_a, d_b, d_c);
hipDeviceSynchronize();
// Copy data back to host
hipMemcpy(h_c, d_c, N*N*sizeof(float), hipMemcpyDeviceToHost);
// Free device memory
hipFree(d_a);
hipFree(d_b);
hipFree(d_c);
testSolution(h_a, h_b, h_c, 1e-3); //Tolerates 0.1% relative error
// Free host memory
delete[] h_a, h_b, h_c;
} | .text
.file "matrixMultiplication.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__multiplyPfS_S_ # -- Begin function _Z23__device_stub__multiplyPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPfS_S_,@function
_Z23__device_stub__multiplyPfS_S_: # @_Z23__device_stub__multiplyPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPfS_S_, .Lfunc_end0-_Z23__device_stub__multiplyPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3a83126f # float 0.00100000005
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %r14
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, 32(%rsp) # 8-byte Spill
xorl %r12d, %r12d
movl $.L.str, %edi
movl $1000, %esi # imm = 0x3E8
movl $1000, %edx # imm = 0x3E8
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %rbx, %r13
movq %r14, %rbp
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, (%r13,%r15,4)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, (%rbp,%r15,4)
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $4000, %rbp # imm = 0xFA0
addq $4000, %r13 # imm = 0xFA0
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq 24(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8multiplyPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 32(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq _Z12testSolutionIfEvPT_S1_S1_f
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12testSolutionIfEvPT_S1_S1_f
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .text._Z12testSolutionIfEvPT_S1_S1_f,"axG",@progbits,_Z12testSolutionIfEvPT_S1_S1_f,comdat
.weak _Z12testSolutionIfEvPT_S1_S1_f
.p2align 4, 0x90
.type _Z12testSolutionIfEvPT_S1_S1_f,@function
_Z12testSolutionIfEvPT_S1_S1_f: # @_Z12testSolutionIfEvPT_S1_S1_f
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movaps %xmm0, %xmm4
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %r15
xorl %r12d, %r12d
movaps .LCPI2_0(%rip), %xmm5 # xmm5 = [NaN,NaN,NaN,NaN]
xorl %esi, %esi
movss %xmm0, 4(%rsp) # 4-byte Spill
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_1 Depth=1
incq %r12
addq $4000, %r15 # imm = 0xFA0
cmpq $1000, %r12 # imm = 0x3E8
je .LBB2_10
.LBB2_1: # %.preheader32
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_3 Depth 3
imulq $4000, %r12, %rbp # imm = 0xFA0
addq 16(%rsp), %rbp # 8-byte Folded Reload
movq 8(%rsp), %r14 # 8-byte Reload
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_2 Depth=2
movl %ebx, %esi
.LBB2_8: # in Loop: Header=BB2_2 Depth=2
incq %r13
addq $4, %r14
cmpq $1000, %r13 # imm = 0x3E8
je .LBB2_9
.LBB2_2: # %.preheader
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_3 Depth 3
xorps %xmm0, %xmm0
movq %r14, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r15,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rax), %xmm1
addss %xmm1, %xmm0
incq %rcx
addq $4000, %rax # imm = 0xFA0
cmpq $1000, %rcx # imm = 0x3E8
jne .LBB2_3
# %bb.4: # in Loop: Header=BB2_2 Depth=2
movss (%rbp,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm1, %xmm2
subss %xmm0, %xmm2
andps %xmm5, %xmm2
movaps %xmm4, %xmm3
maxss %xmm0, %xmm3
divss %xmm3, %xmm2
ucomiss %xmm4, %xmm2
jbe .LBB2_8
# %bb.5: # in Loop: Header=BB2_2 Depth=2
leal 1(%rsi), %ebx
cmpl $9, %esi
jg .LBB2_7
# %bb.6: # in Loop: Header=BB2_2 Depth=2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %r12d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
movaps .LCPI2_0(%rip), %xmm5 # xmm5 = [NaN,NaN,NaN,NaN]
movss 4(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
jmp .LBB2_7
.LBB2_10:
testl %esi, %esi
je .LBB2_12
# %bb.11:
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB2_12:
.cfi_def_cfa_offset 80
movl $.Lstr, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z12testSolutionIfEvPT_S1_S1_f, .Lfunc_end2-_Z12testSolutionIfEvPT_S1_S1_f
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPfS_S_,@object # @_Z8multiplyPfS_S_
.section .rodata,"a",@progbits
.globl _Z8multiplyPfS_S_
.p2align 3, 0x0
_Z8multiplyPfS_S_:
.quad _Z23__device_stub__multiplyPfS_S_
.size _Z8multiplyPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nSize of matrices : %d x %d\n\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Test failed at index : (%d, %d) [Expected: %10.2f | Got: %10.2f]\n"
.size .L.str.1, 66
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%d Tests failed!\n\n"
.size .L.str.2, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPfS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "All tests passed !\n"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z8multiplyPfS_S_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R7, SR_CTAID.X ; /* 0x0000000000077919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GT.AND P0, PT, R0, 0x3e7, PT ; /* 0x000003e70000780c */
/* 0x000fe20003f04270 */
/*0070*/ IMAD R7, R7, c[0x0][0x0], R2 ; /* 0x0000000007077a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GT.OR P0, PT, R7, 0x3e7, P0 ; /* 0x000003e70700780c */
/* 0x000fda0000704670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ HFMA2.MMA R6, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff067435 */
/* 0x000fe200000001ff */
/*00b0*/ IMAD R7, R7, 0x3e8, RZ ; /* 0x000003e807077824 */
/* 0x000fe200078e02ff */
/*00c0*/ HFMA2.MMA R24, -RZ, RZ, 0, 0 ; /* 0x00000000ff187435 */
/* 0x000fe200000001ff */
/*00d0*/ MOV R9, RZ ; /* 0x000000ff00097202 */
/* 0x000fe20000000f00 */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*00f0*/ ULDC.64 UR6, c[0x0][0x168] ; /* 0x00005a0000067ab9 */
/* 0x000fc80000000a00 */
/*0100*/ IMAD.WIDE R2, R7, R6, c[0x0][0x160] ; /* 0x0000580007027625 */
/* 0x000fca00078e0206 */
/*0110*/ IADD3 R2, P0, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc80007f1e0ff */
/*0120*/ IADD3.X R3, RZ, R3, RZ, P0, !PT ; /* 0x00000003ff037210 */
/* 0x000fc800007fe4ff */
/*0130*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0140*/ LDG.E R8, [R2.64+-0x10] ; /* 0xfffff00402087981 */
/* 0x000ea2000c1e1900 */
/*0150*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fc60008000f00 */
/*0160*/ LDG.E R22, [R2.64+-0xc] ; /* 0xfffff40402167981 */
/* 0x000ee4000c1e1900 */
/*0170*/ IMAD.WIDE R4, R0, 0x4, R4 ; /* 0x0000000400047825 */
/* 0x000fe400078e0204 */
/*0180*/ LDG.E R20, [R2.64+-0x8] ; /* 0xfffff80402147981 */
/* 0x000f28000c1e1900 */
/*0190*/ LDG.E R11, [R4.64] ; /* 0x00000004040b7981 */
/* 0x000ea8000c1e1900 */
/*01a0*/ LDG.E R25, [R4.64+0xfa0] ; /* 0x000fa00404197981 */
/* 0x000ee8000c1e1900 */
/*01b0*/ LDG.E R23, [R4.64+0x1f40] ; /* 0x001f400404177981 */
/* 0x000f28000c1e1900 */
/*01c0*/ LDG.E R21, [R2.64+-0x4] ; /* 0xfffffc0402157981 */
/* 0x000f68000c1e1900 */
/*01d0*/ LDG.E R18, [R4.64+0x2ee0] ; /* 0x002ee00404127981 */
/* 0x000f68000c1e1900 */
/*01e0*/ LDG.E R16, [R2.64] ; /* 0x0000000402107981 */
/* 0x000f68000c1e1900 */
/*01f0*/ LDG.E R19, [R4.64+0x3e80] ; /* 0x003e800404137981 */
/* 0x000f68000c1e1900 */
/*0200*/ LDG.E R14, [R2.64+0x4] ; /* 0x00000404020e7981 */
/* 0x000f68000c1e1900 */
/*0210*/ LDG.E R17, [R4.64+0x4e20] ; /* 0x004e200404117981 */
/* 0x000f68000c1e1900 */
/*0220*/ LDG.E R12, [R2.64+0x8] ; /* 0x00000804020c7981 */
/* 0x000f68000c1e1900 */
/*0230*/ LDG.E R15, [R4.64+0x5dc0] ; /* 0x005dc004040f7981 */
/* 0x000f68000c1e1900 */
/*0240*/ LDG.E R10, [R2.64+0xc] ; /* 0x00000c04020a7981 */
/* 0x000f68000c1e1900 */
/*0250*/ LDG.E R13, [R4.64+0x6d60] ; /* 0x006d6004040d7981 */
/* 0x000f68000c1e1900 */
/*0260*/ LDG.E R27, [R2.64+0x8c] ; /* 0x00008c04021b7981 */
/* 0x000162000c1e1900 */
/*0270*/ FFMA R24, R11, R8, R24 ; /* 0x000000080b187223 */
/* 0x004fc60000000018 */
/*0280*/ LDG.E R8, [R2.64+0x10] ; /* 0x0000100402087981 */
/* 0x000ea8000c1e1900 */
/*0290*/ LDG.E R11, [R4.64+0x7d00] ; /* 0x007d0004040b7981 */
/* 0x000ea2000c1e1900 */
/*02a0*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x008fc60000000018 */
/*02b0*/ LDG.E R22, [R2.64+0x14] ; /* 0x0000140402167981 */
/* 0x000ee2000c1e1900 */
/*02c0*/ FFMA R24, R23, R20, R24 ; /* 0x0000001417187223 */
/* 0x010fc60000000018 */
/*02d0*/ LDG.E R25, [R4.64+0x8ca0] ; /* 0x008ca00404197981 */
/* 0x000ee8000c1e1900 */
/*02e0*/ LDG.E R20, [R2.64+0x18] ; /* 0x0000180402147981 */
/* 0x000f22000c1e1900 */
/*02f0*/ FFMA R24, R18, R21, R24 ; /* 0x0000001512187223 */
/* 0x020fc60000000018 */
/*0300*/ LDG.E R23, [R4.64+0x9c40] ; /* 0x009c400404177981 */
/* 0x000f28000c1e1900 */
/*0310*/ LDG.E R18, [R2.64+0x1c] ; /* 0x00001c0402127981 */
/* 0x000f62000c1e1900 */
/*0320*/ FFMA R24, R19, R16, R24 ; /* 0x0000001013187223 */
/* 0x000fc60000000018 */
/*0330*/ LDG.E R21, [R4.64+0xabe0] ; /* 0x00abe00404157981 */
/* 0x000f68000c1e1900 */
/*0340*/ LDG.E R16, [R2.64+0x20] ; /* 0x0000200402107981 */
/* 0x000f62000c1e1900 */
/*0350*/ FFMA R24, R17, R14, R24 ; /* 0x0000000e11187223 */
/* 0x000fc60000000018 */
/*0360*/ LDG.E R19, [R4.64+0xbb80] ; /* 0x00bb800404137981 */
/* 0x000f68000c1e1900 */
/*0370*/ LDG.E R14, [R2.64+0x24] ; /* 0x00002404020e7981 */
/* 0x000f62000c1e1900 */
/*0380*/ FFMA R24, R15, R12, R24 ; /* 0x0000000c0f187223 */
/* 0x000fc60000000018 */
/*0390*/ LDG.E R17, [R4.64+0xcb20] ; /* 0x00cb200404117981 */
/* 0x000f68000c1e1900 */
/*03a0*/ LDG.E R12, [R2.64+0x28] ; /* 0x00002804020c7981 */
/* 0x000f68000c1e1900 */
/*03b0*/ LDG.E R15, [R4.64+0xdac0] ; /* 0x00dac004040f7981 */
/* 0x000f62000c1e1900 */
/*03c0*/ FFMA R24, R13, R10, R24 ; /* 0x0000000a0d187223 */
/* 0x000fc60000000018 */
/*03d0*/ LDG.E R10, [R2.64+0x2c] ; /* 0x00002c04020a7981 */
/* 0x000f68000c1e1900 */
/*03e0*/ LDG.E R13, [R4.64+0xea60] ; /* 0x00ea6004040d7981 */
/* 0x000f62000c1e1900 */
/*03f0*/ FFMA R24, R11, R8, R24 ; /* 0x000000080b187223 */
/* 0x004fc60000000018 */
/*0400*/ LDG.E R8, [R2.64+0x30] ; /* 0x0000300402087981 */
/* 0x000ea8000c1e1900 */
/*0410*/ LDG.E R11, [R4.64+0xfa00] ; /* 0x00fa0004040b7981 */
/* 0x000ea2000c1e1900 */
/*0420*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x008fc60000000018 */
/*0430*/ LDG.E R22, [R2.64+0x34] ; /* 0x0000340402167981 */
/* 0x000ee8000c1e1900 */
/*0440*/ LDG.E R25, [R4.64+0x109a0] ; /* 0x0109a00404197981 */
/* 0x000ee2000c1e1900 */
/*0450*/ FFMA R24, R23, R20, R24 ; /* 0x0000001417187223 */
/* 0x010fc60000000018 */
/*0460*/ LDG.E R20, [R2.64+0x38] ; /* 0x0000380402147981 */
/* 0x000f28000c1e1900 */
/*0470*/ LDG.E R23, [R4.64+0x11940] ; /* 0x0119400404177981 */
/* 0x000f22000c1e1900 */
/*0480*/ FFMA R24, R21, R18, R24 ; /* 0x0000001215187223 */
/* 0x020fc60000000018 */
/*0490*/ LDG.E R18, [R2.64+0x3c] ; /* 0x00003c0402127981 */
/* 0x000f68000c1e1900 */
/*04a0*/ LDG.E R21, [R4.64+0x128e0] ; /* 0x0128e00404157981 */
/* 0x000f62000c1e1900 */
/*04b0*/ FFMA R24, R19, R16, R24 ; /* 0x0000001013187223 */
/* 0x000fc60000000018 */
/*04c0*/ LDG.E R19, [R2.64+0x40] ; /* 0x0000400402137981 */
/* 0x000f68000c1e1900 */
/*04d0*/ LDG.E R16, [R4.64+0x13880] ; /* 0x0138800404107981 */
/* 0x000f62000c1e1900 */
/*04e0*/ FFMA R24, R17, R14, R24 ; /* 0x0000000e11187223 */
/* 0x000fc60000000018 */
/*04f0*/ LDG.E R17, [R2.64+0x44] ; /* 0x0000440402117981 */
/* 0x000f68000c1e1900 */
/*0500*/ LDG.E R14, [R4.64+0x14820] ; /* 0x01482004040e7981 */
/* 0x000f62000c1e1900 */
/*0510*/ FFMA R24, R15, R12, R24 ; /* 0x0000000c0f187223 */
/* 0x000fc60000000018 */
/*0520*/ LDG.E R15, [R2.64+0x48] ; /* 0x00004804020f7981 */
/* 0x000f68000c1e1900 */
/*0530*/ LDG.E R12, [R4.64+0x157c0] ; /* 0x0157c004040c7981 */
/* 0x000f62000c1e1900 */
/*0540*/ FFMA R24, R13, R10, R24 ; /* 0x0000000a0d187223 */
/* 0x000fc60000000018 */
/*0550*/ LDG.E R13, [R2.64+0x4c] ; /* 0x00004c04020d7981 */
/* 0x000f68000c1e1900 */
/*0560*/ LDG.E R10, [R4.64+0x16760] ; /* 0x01676004040a7981 */
/* 0x000f62000c1e1900 */
/*0570*/ FFMA R24, R11, R8, R24 ; /* 0x000000080b187223 */
/* 0x004fc60000000018 */
/*0580*/ LDG.E R11, [R2.64+0x50] ; /* 0x00005004020b7981 */
/* 0x000ea8000c1e1900 */
/*0590*/ LDG.E R8, [R4.64+0x17700] ; /* 0x0177000404087981 */
/* 0x000ea2000c1e1900 */
/*05a0*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x008fc60000000018 */
/*05b0*/ LDG.E R22, [R2.64+0x54] ; /* 0x0000540402167981 */
/* 0x000ee8000c1e1900 */
/*05c0*/ LDG.E R25, [R4.64+0x186a0] ; /* 0x0186a00404197981 */
/* 0x000ee2000c1e1900 */
/*05d0*/ FFMA R24, R23, R20, R24 ; /* 0x0000001417187223 */
/* 0x010fc60000000018 */
/*05e0*/ LDG.E R23, [R2.64+0x58] ; /* 0x0000580402177981 */
/* 0x000f28000c1e1900 */
/*05f0*/ LDG.E R20, [R4.64+0x19640] ; /* 0x0196400404147981 */
/* 0x000f22000c1e1900 */
/*0600*/ FFMA R24, R21, R18, R24 ; /* 0x0000001215187223 */
/* 0x020fc60000000018 */
/*0610*/ LDG.E R21, [R2.64+0x5c] ; /* 0x00005c0402157981 */
/* 0x000f68000c1e1900 */
/*0620*/ LDG.E R18, [R4.64+0x1a5e0] ; /* 0x01a5e00404127981 */
/* 0x000f62000c1e1900 */
/*0630*/ FFMA R24, R16, R19, R24 ; /* 0x0000001310187223 */
/* 0x000fc60000000018 */
/*0640*/ LDG.E R19, [R2.64+0x60] ; /* 0x0000600402137981 */
/* 0x000f68000c1e1900 */
/*0650*/ LDG.E R16, [R4.64+0x1b580] ; /* 0x01b5800404107981 */
/* 0x000f62000c1e1900 */
/*0660*/ FFMA R24, R14, R17, R24 ; /* 0x000000110e187223 */
/* 0x000fc60000000018 */
/*0670*/ LDG.E R17, [R2.64+0x64] ; /* 0x0000640402117981 */
/* 0x000f68000c1e1900 */
/*0680*/ LDG.E R14, [R4.64+0x1c520] ; /* 0x01c52004040e7981 */
/* 0x000f62000c1e1900 */
/*0690*/ FFMA R24, R12, R15, R24 ; /* 0x0000000f0c187223 */
/* 0x000fc60000000018 */
/*06a0*/ LDG.E R15, [R2.64+0x68] ; /* 0x00006804020f7981 */
/* 0x000f68000c1e1900 */
/*06b0*/ LDG.E R12, [R4.64+0x1d4c0] ; /* 0x01d4c004040c7981 */
/* 0x000f62000c1e1900 */
/*06c0*/ FFMA R24, R10, R13, R24 ; /* 0x0000000d0a187223 */
/* 0x000fc60000000018 */
/*06d0*/ LDG.E R13, [R2.64+0x6c] ; /* 0x00006c04020d7981 */
/* 0x000f68000c1e1900 */
/*06e0*/ LDG.E R10, [R4.64+0x1e460] ; /* 0x01e46004040a7981 */
/* 0x000f62000c1e1900 */
/*06f0*/ FFMA R24, R8, R11, R24 ; /* 0x0000000b08187223 */
/* 0x004fc60000000018 */
/*0700*/ LDG.E R8, [R2.64+0x70] ; /* 0x0000700402087981 */
/* 0x0000a8000c1e1900 */
/*0710*/ LDG.E R11, [R4.64+0x1f400] ; /* 0x01f40004040b7981 */
/* 0x000ea2000c1e1900 */
/*0720*/ FFMA R24, R25, R22, R24 ; /* 0x0000001619187223 */
/* 0x008fc60000000018 */
/*0730*/ LDG.E R25, [R2.64+0x74] ; /* 0x0000740402197981 */
/* 0x0000e8000c1e1900 */
/*0740*/ LDG.E R22, [R4.64+0x203a0] ; /* 0x0203a00404167981 */
/* 0x000ee2000c1e1900 */
/*0750*/ FFMA R24, R20, R23, R24 ; /* 0x0000001714187223 */
/* 0x010fc60000000018 */
/*0760*/ LDG.E R23, [R2.64+0x78] ; /* 0x0000780402177981 */
/* 0x000128000c1e1900 */
/*0770*/ LDG.E R20, [R4.64+0x21340] ; /* 0x0213400404147981 */
/* 0x000f22000c1e1900 */
/*0780*/ FFMA R24, R18, R21, R24 ; /* 0x0000001512187223 */
/* 0x020fc60000000018 */
/*0790*/ LDG.E R21, [R2.64+0x7c] ; /* 0x00007c0402157981 */
/* 0x000168000c1e1900 */
/*07a0*/ LDG.E R18, [R4.64+0x222e0] ; /* 0x0222e00404127981 */
/* 0x000f62000c1e1900 */
/*07b0*/ FFMA R24, R16, R19, R24 ; /* 0x0000001310187223 */
/* 0x000fc60000000018 */
/*07c0*/ LDG.E R19, [R2.64+0x80] ; /* 0x0000800402137981 */
/* 0x000168000c1e1900 */
/*07d0*/ LDG.E R16, [R4.64+0x23280] ; /* 0x0232800404107981 */
/* 0x000f62000c1e1900 */
/*07e0*/ FFMA R24, R14, R17, R24 ; /* 0x000000110e187223 */
/* 0x000fc60000000018 */
/*07f0*/ LDG.E R17, [R2.64+0x84] ; /* 0x0000840402117981 */
/* 0x000168000c1e1900 */
/*0800*/ LDG.E R14, [R4.64+0x24220] ; /* 0x02422004040e7981 */
/* 0x000f62000c1e1900 */
/*0810*/ FFMA R26, R12, R15, R24 ; /* 0x0000000f0c1a7223 */
/* 0x000fc60000000018 */
/*0820*/ LDG.E R12, [R2.64+0x88] ; /* 0x00008804020c7981 */
/* 0x000168000c1e1900 */
/*0830*/ LDG.E R15, [R4.64+0x251c0] ; /* 0x0251c004040f7981 */
/* 0x000f68000c1e1900 */
/*0840*/ LDG.E R24, [R4.64+0x26160] ; /* 0x0261600404187981 */
/* 0x000f62000c1e1900 */
/*0850*/ FFMA R10, R10, R13, R26 ; /* 0x0000000d0a0a7223 */
/* 0x000fe2000000001a */
/*0860*/ IADD3 R9, R9, 0x28, RZ ; /* 0x0000002809097810 */
/* 0x000fc80007ffe0ff */
/*0870*/ ISETP.NE.AND P0, PT, R9, 0x3e8, PT ; /* 0x000003e80900780c */
/* 0x000fe20003f05270 */
/*0880*/ UIADD3 UR6, UP0, UR6, 0x27100, URZ ; /* 0x0002710006067890 */
/* 0x000fe2000ff1e03f */
/*0890*/ IADD3 R2, P1, R2, 0xa0, RZ ; /* 0x000000a002027810 */
/* 0x001fc60007f3e0ff */
/*08a0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*08b0*/ IADD3.X R3, RZ, R3, RZ, P1, !PT ; /* 0x00000003ff037210 */
/* 0x000fe20000ffe4ff */
/*08c0*/ FFMA R8, R11, R8, R10 ; /* 0x000000080b087223 */
/* 0x004fc8000000000a */
/*08d0*/ FFMA R8, R22, R25, R8 ; /* 0x0000001916087223 */
/* 0x008fc80000000008 */
/*08e0*/ FFMA R8, R20, R23, R8 ; /* 0x0000001714087223 */
/* 0x010fc80000000008 */
/*08f0*/ FFMA R8, R18, R21, R8 ; /* 0x0000001512087223 */
/* 0x020fc80000000008 */
/*0900*/ FFMA R8, R16, R19, R8 ; /* 0x0000001310087223 */
/* 0x000fc80000000008 */
/*0910*/ FFMA R8, R14, R17, R8 ; /* 0x000000110e087223 */
/* 0x000fc80000000008 */
/*0920*/ FFMA R8, R15, R12, R8 ; /* 0x0000000c0f087223 */
/* 0x000fc80000000008 */
/*0930*/ FFMA R24, R24, R27, R8 ; /* 0x0000001b18187223 */
/* 0x000fe20000000008 */
/*0940*/ @P0 BRA 0x130 ; /* 0xfffff7e000000947 */
/* 0x000fea000383ffff */
/*0950*/ IADD3 R7, R0, R7, RZ ; /* 0x0000000700077210 */
/* 0x000fca0007ffe0ff */
/*0960*/ IMAD.WIDE R6, R7, R6, c[0x0][0x170] ; /* 0x00005c0007067625 */
/* 0x000fca00078e0206 */
/*0970*/ STG.E [R6.64], R24 ; /* 0x0000001806007986 */
/* 0x000fe2000c101904 */
/*0980*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0990*/ BRA 0x990; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0a70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z8multiplyPfS_S_
.globl _Z8multiplyPfS_S_
.p2align 8
.type _Z8multiplyPfS_S_,@function
_Z8multiplyPfS_S_:
s_load_b32 s2, s[0:1], 0x24
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e32 0x3e8, v2
s_cbranch_execz .LBB0_4
s_load_b128 s[4:7], s[0:1], 0x0
v_mul_lo_u32 v2, v0, 0x3e8
v_mov_b32_e32 v4, 0
s_mov_b64 s[2:3], 0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v5, vcc_lo, s4, v2
v_add_co_ci_u32_e32 v6, vcc_lo, s5, v3, vcc_lo
v_mov_b32_e32 v2, v1
.p2align 6
.LBB0_2:
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
v_ashrrev_i32_e32 v3, 31, v2
v_add_co_u32 v7, vcc_lo, v5, s2
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v6, vcc_lo
v_lshlrev_b64 v[9:10], 2, v[2:3]
v_add_nc_u32_e32 v2, 0x3e8, v2
s_add_u32 s2, s2, 4
s_addc_u32 s3, s3, 0
s_cmpk_eq_i32 s2, 0xfa0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_u32 v9, vcc_lo, s6, v9
v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
global_load_b32 v3, v[7:8], off
global_load_b32 v7, v[9:10], off
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v4, v3, v7
s_cbranch_scc0 .LBB0_2
s_load_b64 s[0:1], s[0:1], 0x10
v_mad_u64_u32 v[2:3], null, v0, 0x3e8, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[0:1], 2, v[2:3]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v4, off
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z8multiplyPfS_S_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 11
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z8multiplyPfS_S_, .Lfunc_end0-_Z8multiplyPfS_S_
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z8multiplyPfS_S_
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z8multiplyPfS_S_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 11
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00189ddf_00000000-6_matrixMultiplication.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10863:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10863:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z31__device_stub__Z8multiplyPfS_S_PfS_S_
.type _Z31__device_stub__Z8multiplyPfS_S_PfS_S_, @function
_Z31__device_stub__Z8multiplyPfS_S_PfS_S_:
.LFB10885:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z8multiplyPfS_S_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10885:
.size _Z31__device_stub__Z8multiplyPfS_S_PfS_S_, .-_Z31__device_stub__Z8multiplyPfS_S_PfS_S_
.globl _Z8multiplyPfS_S_
.type _Z8multiplyPfS_S_, @function
_Z8multiplyPfS_S_:
.LFB10886:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z31__device_stub__Z8multiplyPfS_S_PfS_S_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10886:
.size _Z8multiplyPfS_S_, .-_Z8multiplyPfS_S_
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z8multiplyPfS_S_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10888:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z8multiplyPfS_S_(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE10888:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._Z12testSolutionIfEvPT_S1_S1_f.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Test failed at index : (%d, %d) [Expected: %10.2f | Got: %10.2f]\n"
.section .rodata._Z12testSolutionIfEvPT_S1_S1_f.str1.1,"aMS",@progbits,1
.LC4:
.string "\n%d Tests failed!\n\n"
.LC5:
.string "All tests passed !\n\n"
.section .text._Z12testSolutionIfEvPT_S1_S1_f,"axG",@progbits,_Z12testSolutionIfEvPT_S1_S1_f,comdat
.weak _Z12testSolutionIfEvPT_S1_S1_f
.type _Z12testSolutionIfEvPT_S1_S1_f, @function
_Z12testSolutionIfEvPT_S1_S1_f:
.LFB11567:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, %r13
movq %rsi, 16(%rsp)
movq %rdx, 24(%rsp)
movss %xmm0, 8(%rsp)
movl $0, %r15d
movl $0, 12(%rsp)
movl $0, %r14d
jmp .L14
.L16:
addl $1, %ebp
addq $4, %r12
addq $4, %rbx
cmpl $1000, %ebp
je .L18
.L20:
leaq 0(%r13,%r15), %rdx
leaq -4000000(%rbx), %rax
movl $0x00000000, (%rsp)
.L15:
movss (%rdx), %xmm0
mulss (%rax), %xmm0
addss (%rsp), %xmm0
movss %xmm0, (%rsp)
addq $4, %rdx
addq $4000, %rax
cmpq %rbx, %rax
jne .L15
movss (%r12), %xmm3
movss %xmm3, 4(%rsp)
movaps %xmm0, %xmm1
movss 8(%rsp), %xmm0
call fmaxf@PLT
movaps %xmm0, %xmm1
movss 4(%rsp), %xmm3
subss (%rsp), %xmm3
movaps %xmm3, %xmm0
andps .LC2(%rip), %xmm0
divss %xmm1, %xmm0
comiss 8(%rsp), %xmm0
jbe .L16
addl $1, %r14d
cmpl $10, %r14d
jg .L16
pxor %xmm0, %xmm0
cvtss2sd (%rsp), %xmm0
pxor %xmm1, %xmm1
cvtss2sd 4(%rsp), %xmm1
movl %ebp, %ecx
movl 12(%rsp), %edx
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
jmp .L16
.L18:
addl $1, 12(%rsp)
movl 12(%rsp), %eax
addq $4000, %r15
cmpl $1000, %eax
je .L19
.L14:
movq 24(%rsp), %rax
leaq (%rax,%r15), %r12
movq 16(%rsp), %rax
leaq 4000000(%rax), %rbx
movl $0, %ebp
jmp .L20
.L19:
testl %r14d, %r14d
je .L21
movl %r14d, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L13:
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L13
.cfi_endproc
.LFE11567:
.size _Z12testSolutionIfEvPT_S1_S1_f, .-_Z12testSolutionIfEvPT_S1_S1_f
.section .rodata.str1.1
.LC6:
.string "\nSize of matrices : %d x %d\n\n"
.text
.globl main
.type main, @function
main:
.LFB10860:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r14
movl $4000000, %edi
call _Znam@PLT
movq %rax, %r15
movl $4000000, %edi
call _Znam@PLT
movq %rax, 8(%rsp)
movl $1000, %ecx
movl $1000, %edx
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movq %r14, %rbp
movq %r15, %r12
leaq 4000000(%r14), %r13
.L27:
movl $0, %ebx
.L28:
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm2, %xmm2
cvtsi2sdl %eax, %xmm2
movsd %xmm2, (%rsp)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd (%rsp), %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, 0(%rbp,%rbx)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm3, %xmm3
cvtsi2sdl %eax, %xmm3
movsd %xmm3, (%rsp)
call rand@PLT
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
imull $1000, %edx, %edx
subl %edx, %eax
addl $1, %eax
pxor %xmm1, %xmm1
cvtsi2sdl %eax, %xmm1
movsd (%rsp), %xmm0
divsd %xmm1, %xmm0
cvtsd2ss %xmm0, %xmm0
movss %xmm0, (%r12,%rbx)
addq $4, %rbx
cmpq $4000, %rbx
jne .L28
addq $4000, %rbp
addq $4000, %r12
cmpq %r13, %rbp
jne .L27
leaq 24(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 32(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
leaq 40(%rsp), %rdi
movl $4000000, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r14, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $4000000, %edx
movq %r15, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 48(%rsp)
movl $32, 52(%rsp)
movl $32, 60(%rsp)
movl $32, 64(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 60(%rsp), %rdx
movl $1, %ecx
movq 48(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
call cudaThreadSynchronize@PLT
movl $2, %ecx
movl $4000000, %edx
movq 40(%rsp), %rsi
movq 8(%rsp), %rbx
movq %rbx, %rdi
call cudaMemcpy@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movss .LC7(%rip), %xmm0
movq %rbx, %rdx
movq %r15, %rsi
movq %r14, %rdi
call _Z12testSolutionIfEvPT_S1_S1_f
movq %r14, %rdi
call _ZdaPv@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L35
movl $0, %eax
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z31__device_stub__Z8multiplyPfS_S_PfS_S_
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE10860:
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC2:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC7:
.long 981668463
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMultiplication.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z23__device_stub__multiplyPfS_S_ # -- Begin function _Z23__device_stub__multiplyPfS_S_
.p2align 4, 0x90
.type _Z23__device_stub__multiplyPfS_S_,@function
_Z23__device_stub__multiplyPfS_S_: # @_Z23__device_stub__multiplyPfS_S_
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z8multiplyPfS_S_, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z23__device_stub__multiplyPfS_S_, .Lfunc_end0-_Z23__device_stub__multiplyPfS_S_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI1_0:
.long 0x3a83126f # float 0.00100000005
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %rbx
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, %r14
movl $4000000, %edi # imm = 0x3D0900
callq _Znam
movq %rax, 32(%rsp) # 8-byte Spill
xorl %r12d, %r12d
movl $.L.str, %edi
movl $1000, %esi # imm = 0x3E8
movl $1000, %edx # imm = 0x3E8
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movq %rbx, %r13
movq %r14, %rbp
.p2align 4, 0x90
.LBB1_1: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_2 Depth 2
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB1_2: # Parent Loop BB1_1 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, (%r13,%r15,4)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd %xmm0, (%rsp) # 8-byte Spill
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
negl %ecx
addl %ecx, %eax
incl %eax
xorps %xmm0, %xmm0
cvtsi2sd %eax, %xmm0
movsd (%rsp), %xmm1 # 8-byte Reload
# xmm1 = mem[0],zero
divsd %xmm0, %xmm1
xorps %xmm0, %xmm0
cvtsd2ss %xmm1, %xmm0
movss %xmm0, (%rbp,%r15,4)
incq %r15
cmpq $1000, %r15 # imm = 0x3E8
jne .LBB1_2
# %bb.3: # in Loop: Header=BB1_1 Depth=1
incq %r12
addq $4000, %rbp # imm = 0xFA0
addq $4000, %r13 # imm = 0xFA0
cmpq $1000, %r12 # imm = 0x3E8
jne .LBB1_1
# %bb.4:
leaq 24(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 16(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
leaq 8(%rsp), %rdi
movl $4000000, %esi # imm = 0x3D0900
callq hipMalloc
movq 24(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $4000000, %edx # imm = 0x3D0900
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $137438953504, %rdi # imm = 0x2000000020
movl $1, %esi
movq %rdi, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z8multiplyPfS_S_, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
callq hipDeviceSynchronize
movq 8(%rsp), %rsi
movl $4000000, %edx # imm = 0x3D0900
movq 32(%rsp), %r15 # 8-byte Reload
movq %r15, %rdi
movl $2, %ecx
callq hipMemcpy
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movss .LCPI1_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq _Z12testSolutionIfEvPT_S1_S1_f
movq %rbx, %rdi
callq _ZdaPv
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z12testSolutionIfEvPT_S1_S1_f
.LCPI2_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .text._Z12testSolutionIfEvPT_S1_S1_f,"axG",@progbits,_Z12testSolutionIfEvPT_S1_S1_f,comdat
.weak _Z12testSolutionIfEvPT_S1_S1_f
.p2align 4, 0x90
.type _Z12testSolutionIfEvPT_S1_S1_f,@function
_Z12testSolutionIfEvPT_S1_S1_f: # @_Z12testSolutionIfEvPT_S1_S1_f
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movaps %xmm0, %xmm4
movq %rdx, 16(%rsp) # 8-byte Spill
movq %rsi, 8(%rsp) # 8-byte Spill
movq %rdi, %r15
xorl %r12d, %r12d
movaps .LCPI2_0(%rip), %xmm5 # xmm5 = [NaN,NaN,NaN,NaN]
xorl %esi, %esi
movss %xmm0, 4(%rsp) # 4-byte Spill
jmp .LBB2_1
.p2align 4, 0x90
.LBB2_9: # in Loop: Header=BB2_1 Depth=1
incq %r12
addq $4000, %r15 # imm = 0xFA0
cmpq $1000, %r12 # imm = 0x3E8
je .LBB2_10
.LBB2_1: # %.preheader32
# =>This Loop Header: Depth=1
# Child Loop BB2_2 Depth 2
# Child Loop BB2_3 Depth 3
imulq $4000, %r12, %rbp # imm = 0xFA0
addq 16(%rsp), %rbp # 8-byte Folded Reload
movq 8(%rsp), %r14 # 8-byte Reload
xorl %r13d, %r13d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_7: # in Loop: Header=BB2_2 Depth=2
movl %ebx, %esi
.LBB2_8: # in Loop: Header=BB2_2 Depth=2
incq %r13
addq $4, %r14
cmpq $1000, %r13 # imm = 0x3E8
je .LBB2_9
.LBB2_2: # %.preheader
# Parent Loop BB2_1 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB2_3 Depth 3
xorps %xmm0, %xmm0
movq %r14, %rax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB2_3: # Parent Loop BB2_1 Depth=1
# Parent Loop BB2_2 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r15,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rax), %xmm1
addss %xmm1, %xmm0
incq %rcx
addq $4000, %rax # imm = 0xFA0
cmpq $1000, %rcx # imm = 0x3E8
jne .LBB2_3
# %bb.4: # in Loop: Header=BB2_2 Depth=2
movss (%rbp,%r13,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movaps %xmm1, %xmm2
subss %xmm0, %xmm2
andps %xmm5, %xmm2
movaps %xmm4, %xmm3
maxss %xmm0, %xmm3
divss %xmm3, %xmm2
ucomiss %xmm4, %xmm2
jbe .LBB2_8
# %bb.5: # in Loop: Header=BB2_2 Depth=2
leal 1(%rsi), %ebx
cmpl $9, %esi
jg .LBB2_7
# %bb.6: # in Loop: Header=BB2_2 Depth=2
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl $.L.str.1, %edi
movl %r12d, %esi
movl %r13d, %edx
movb $2, %al
callq printf
movaps .LCPI2_0(%rip), %xmm5 # xmm5 = [NaN,NaN,NaN,NaN]
movss 4(%rsp), %xmm4 # 4-byte Reload
# xmm4 = mem[0],zero,zero,zero
jmp .LBB2_7
.LBB2_10:
testl %esi, %esi
je .LBB2_12
# %bb.11:
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB2_12:
.cfi_def_cfa_offset 80
movl $.Lstr, %edi
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp puts@PLT # TAILCALL
.Lfunc_end2:
.size _Z12testSolutionIfEvPT_S1_S1_f, .Lfunc_end2-_Z12testSolutionIfEvPT_S1_S1_f
.cfi_endproc
# -- End function
.text
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z8multiplyPfS_S_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z8multiplyPfS_S_,@object # @_Z8multiplyPfS_S_
.section .rodata,"a",@progbits
.globl _Z8multiplyPfS_S_
.p2align 3, 0x0
_Z8multiplyPfS_S_:
.quad _Z23__device_stub__multiplyPfS_S_
.size _Z8multiplyPfS_S_, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "\nSize of matrices : %d x %d\n\n"
.size .L.str, 30
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "Test failed at index : (%d, %d) [Expected: %10.2f | Got: %10.2f]\n"
.size .L.str.1, 66
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "\n%d Tests failed!\n\n"
.size .L.str.2, 20
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z8multiplyPfS_S_"
.size .L__unnamed_1, 18
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "All tests passed !\n"
.size .Lstr, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z23__device_stub__multiplyPfS_S_
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z8multiplyPfS_S_
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
cudaError_t addWithCuda(int* c, const int* a, const int* b, unsigned int size);
int getSPcores(cudaDeviceProp devProp)
{
int cores = 0;
int mp = devProp.multiProcessorCount;
switch (devProp.major) {
case 2: // Fermi
if (devProp.minor == 1) cores = mp * 48;
else cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if ((devProp.minor == 1) || (devProp.minor == 2)) cores = mp * 128;
else if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 7: // Volta and Turing
if ((devProp.minor == 0) || (devProp.minor == 5)) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 8: // Ampere
if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
default:
printf("Unknown device type\n");
break;
}
printf("Hay %i nucleos\n", cores);
return cores;
}
__global__ void addKernel(int* a, int* b)
{
int i = threadIdx.x;
a[i] += b[i];
}
__global__ void invertirArray(int* dest, int* org, unsigned int n) {
for (int i = n - 1; i >= 0; i--) {
dest[(n - 1) - i] = org[i];
}
}
int main()
{
int deviceID = 0, ncores, nvec;
int* hst_matriz = NULL;
int* dev_matriz = NULL;
int* dev_matriz_inver = NULL;
int deviceCount;
cudaGetDeviceCount(&deviceCount);
cudaDeviceProp props;
cudaGetDeviceProperties(&props, deviceID);
ncores = getSPcores(props);
printf("Numero de valores del vector(max %i): ", ncores);
scanf("%i", &nvec);
hst_matriz = (int*)malloc(nvec * sizeof(int));
cudaMallocManaged((void**)&dev_matriz, nvec * sizeof(int));
cudaMallocManaged((void**)&dev_matriz_inver, nvec * sizeof(int));
// Generacion del array
srand(time(NULL));
for (int i = 0; i < nvec; i++) {
hst_matriz[i] = rand() % 10;
}
int* arr = (int*)malloc(nvec * sizeof(int));
cudaMemcpy((void**)dev_matriz, hst_matriz, nvec * sizeof(int), cudaMemcpyHostToDevice);
invertirArray <<<1,1>>> (dev_matriz_inver, dev_matriz, nvec);
addKernel <<<1,nvec>>> (dev_matriz, dev_matriz_inver);
cudaMemcpy((void**)hst_matriz,dev_matriz,nvec*sizeof(int),cudaMemcpyDeviceToHost);
printf("Resultado final:");
for (int i = 0; i < nvec;i++) {
printf("[%i]",hst_matriz[i]);
}
} | code for sm_80
Function : _Z13invertirArrayPiS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fca00078e00ff */
/*0020*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fc80007ffe0ff */
/*0030*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f06270 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe2000780c0ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, R0 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0000 */
/*0080*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0e7624 */
/* 0x000fd200078e00ff */
/*0090*/ @!P0 BRA 0x1a0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0e7624 */
/* 0x000fca00078e00ff */
/*00d0*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fc800078e00ff */
/*00f0*/ IMAD.WIDE R2, R14, R3, c[0x0][0x168] ; /* 0x00005a000e027625 */
/* 0x000fcc00078e0203 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0130*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0140*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*0150*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0160*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0170*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041f2000c101904 */
/*0180*/ @P0 BRA 0xd0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0190*/ IADD3 R3, R14, -0x1, RZ ; /* 0xffffffff0e037810 */
/* 0x001fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f06070 */
/*01b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R0, R3.reuse, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe20003f24270 */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; /* 0x00000002ff007424 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R2, -R3, c[0x0][0x170], RZ ; /* 0x00005c0003027a10 */
/* 0x000fc80007ffe1ff */
/*0210*/ IADD3 R0, -R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a10 */
/* 0x000fce0007ffe100 */
/*0220*/ @!P1 BRA 0x730 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x002fc800078e00ff */
/*0250*/ IMAD.WIDE R8, R3, R5, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fca00078e0205 */
/*0260*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IADD3 R6, -R14, c[0x0][0x170], RZ ; /* 0x00005c000e067a10 */
/* 0x000fca0007ffe1ff */
/*0280*/ IMAD.WIDE.U32 R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0005 */
/*0290*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0041e8000c101904 */
/*02a0*/ LDG.E R19, [R8.64+-0x4] ; /* 0xfffffc0408137981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ IMAD.WIDE.U32 R10, R2.reuse, R5, c[0x0][0x160] ; /* 0x00005800020a7625 */
/* 0x040fe200078e0005 */
/*02c0*/ IADD3 R12, R2, 0x1, RZ ; /* 0x00000001020c7810 */
/* 0x000fc80007ffe0ff */
/*02d0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0043e8000c101904 */
/*02e0*/ LDG.E R21, [R8.64+-0x8] ; /* 0xfffff80408157981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe200078e0005 */
/*0300*/ IADD3 R4, R3, -0x4, RZ ; /* 0xfffffffc03047810 */
/* 0x000fc80007ffe0ff */
/*0310*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0045e8000c101904 */
/*0320*/ LDG.E R23, [R8.64+-0xc] ; /* 0xfffff40408177981 */
/* 0x000ee2000c1e1900 */
/*0330*/ IMAD.WIDE.U32 R14, R0, R5, c[0x0][0x160] ; /* 0x00005800000e7625 */
/* 0x000fc800078e0005 */
/*0340*/ IMAD.WIDE R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x001fe200078e0205 */
/*0350*/ IADD3 R4, R3, -0x3, RZ ; /* 0xfffffffd03047810 */
/* 0x000fe20007ffe0ff */
/*0360*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0081e8000c101904 */
/*0370*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee2000c1e1900 */
/*0380*/ IADD3 R4, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fca0007ffe1ff */
/*0390*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x002fe200078e0005 */
/*03a0*/ IADD3 R12, R2, 0x4, RZ ; /* 0x00000004020c7810 */
/* 0x004fc80007ffe0ff */
/*03b0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0083e8000c101904 */
/*03c0*/ LDG.E R19, [R6.64+-0x4] ; /* 0xfffffc0406137981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe200078e0005 */
/*03e0*/ IADD3 R14, R2, 0x5, RZ ; /* 0x00000005020e7810 */
/* 0x001fc80007ffe0ff */
/*03f0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0041e8000c101904 */
/*0400*/ LDG.E R21, [R6.64+-0x8] ; /* 0xfffff80406157981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE.U32 R14, R14, R5.reuse, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x080fe200078e0005 */
/*0420*/ IADD3 R4, R0, 0x4, RZ ; /* 0x0000000400047810 */
/* 0x000fe40007ffe0ff */
/*0430*/ IADD3 R8, R3, -0x8, RZ ; /* 0xfffffff803087810 */
/* 0x000fe40007ffe0ff */
/*0440*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0045e8000c101904 */
/*0450*/ LDG.E R23, [R6.64+-0xc] ; /* 0xfffff40406177981 */
/* 0x000ee2000c1e1900 */
/*0460*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x002fc800078e0005 */
/*0470*/ IMAD.WIDE R8, R8, R5, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0205 */
/*0480*/ IADD3 R4, R3, -0x7, RZ ; /* 0xfffffff903047810 */
/* 0x000fe20007ffe0ff */
/*0490*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0083e8000c101904 */
/*04a0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee2000c1e1900 */
/*04b0*/ IADD3 R4, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fca0007ffe1ff */
/*04c0*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x001fe200078e0005 */
/*04d0*/ IADD3 R14, R2, 0x8, RZ ; /* 0x00000008020e7810 */
/* 0x004fc80007ffe0ff */
/*04e0*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0081e8000c101904 */
/*04f0*/ LDG.E R19, [R8.64+-0x4] ; /* 0xfffffc0408137981 */
/* 0x000ea2000c1e1900 */
/*0500*/ IMAD.WIDE.U32 R14, R14, R5, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e0005 */
/*0510*/ IADD3 R10, R2, 0x9, RZ ; /* 0x00000009020a7810 */
/* 0x002fc80007ffe0ff */
/*0520*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0043e8000c101904 */
/*0530*/ LDG.E R21, [R8.64+-0x8] ; /* 0xfffff80408157981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IMAD.WIDE.U32 R10, R10, R5.reuse, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x080fe200078e0005 */
/*0550*/ IADD3 R4, R0, 0x8, RZ ; /* 0x0000000800047810 */
/* 0x000fe40007ffe0ff */
/*0560*/ IADD3 R6, R3, -0xc, RZ ; /* 0xfffffff403067810 */
/* 0x000fe40007ffe0ff */
/*0570*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0045e8000c101904 */
/*0580*/ LDG.E R23, [R8.64+-0xc] ; /* 0xfffff40408177981 */
/* 0x000ee2000c1e1900 */
/*0590*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x001fc800078e0005 */
/*05a0*/ IMAD.WIDE R6, R6, R5, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0205 */
/*05b0*/ IADD3 R4, R3, -0xb, RZ ; /* 0xfffffff503047810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x008fe8000c101904 */
/*05d0*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee2000c1e1900 */
/*05e0*/ IADD3 R4, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fca0007ffe1ff */
/*05f0*/ IMAD.WIDE.U32 R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x002fe200078e0005 */
/*0600*/ IADD3 R8, R2, 0xc, RZ ; /* 0x0000000c02087810 */
/* 0x000fc80007ffe0ff */
/*0610*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0081e8000c101904 */
/*0620*/ LDG.E R19, [R6.64+-0x4] ; /* 0xfffffc0406137981 */
/* 0x000ee2000c1e1900 */
/*0630*/ IMAD.WIDE.U32 R8, R8, R5, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0005 */
/*0640*/ IADD3 R10, R2, 0xd, RZ ; /* 0x0000000d020a7810 */
/* 0x004fc80007ffe0ff */
/*0650*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0083e8000c101904 */
/*0660*/ LDG.E R21, [R6.64+-0x8] ; /* 0xfffff80406157981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IMAD.WIDE.U32 R10, R10, R5, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe200078e0005 */
/*0680*/ IADD3 R14, R3.reuse, -0xf, RZ ; /* 0xfffffff1030e7810 */
/* 0x041fe40007ffe0ff */
/*0690*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ IADD3 R4, R0, 0xc, RZ ; /* 0x0000000c00047810 */
/* 0x000fc40007ffe0ff */
/*06b0*/ ISETP.GT.AND P1, PT, R3, 0xb, PT ; /* 0x0000000b0300780c */
/* 0x000fe20003f24270 */
/*06c0*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0043e8000c101904 */
/*06d0*/ LDG.E R13, [R6.64+-0xc] ; /* 0xfffff404060d7981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0005 */
/*06f0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*0710*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0043e4000c101904 */
/*0720*/ @P1 BRA 0x240 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0730*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x002fc80007ffe0ff */
/*0740*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0750*/ @!P1 BRA 0x9e0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0770*/ IMAD.WIDE R8, R3, R5, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fca00078e0205 */
/*0780*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea2000c1e1900 */
/*0790*/ IADD3 R6, -R14, c[0x0][0x170], RZ ; /* 0x00005c000e067a10 */
/* 0x000fca0007ffe1ff */
/*07a0*/ IMAD.WIDE.U32 R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0005 */
/*07b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0041e8000c101904 */
/*07c0*/ LDG.E R19, [R8.64+-0x4] ; /* 0xfffffc0408137981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ IMAD.WIDE.U32 R10, R2.reuse, R5, c[0x0][0x160] ; /* 0x00005800020a7625 */
/* 0x040fe200078e0005 */
/*07e0*/ IADD3 R12, R2, 0x1, RZ ; /* 0x00000001020c7810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0043e8000c101904 */
/*0800*/ LDG.E R21, [R8.64+-0x8] ; /* 0xfffff80408157981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe200078e0005 */
/*0820*/ IADD3 R4, R3, -0x4, RZ ; /* 0xfffffffc03047810 */
/* 0x000fc80007ffe0ff */
/*0830*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0045e8000c101904 */
/*0840*/ LDG.E R23, [R8.64+-0xc] ; /* 0xfffff40408177981 */
/* 0x000ee2000c1e1900 */
/*0850*/ IMAD.WIDE.U32 R14, R0, R5, c[0x0][0x160] ; /* 0x00005800000e7625 */
/* 0x000fc800078e0005 */
/*0860*/ IMAD.WIDE R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x001fe200078e0205 */
/*0870*/ IADD3 R4, R3, -0x3, RZ ; /* 0xfffffffd03047810 */
/* 0x000fe20007ffe0ff */
/*0880*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0081e8000c101904 */
/*0890*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee2000c1e1900 */
/*08a0*/ IADD3 R4, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fca0007ffe1ff */
/*08b0*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x002fe200078e0005 */
/*08c0*/ IADD3 R8, R2, 0x4, RZ ; /* 0x0000000402087810 */
/* 0x000fc80007ffe0ff */
/*08d0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0083e8000c101904 */
/*08e0*/ LDG.E R19, [R6.64+-0x4] ; /* 0xfffffc0406137981 */
/* 0x000ee2000c1e1900 */
/*08f0*/ IMAD.WIDE.U32 R8, R8, R5, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0005 */
/*0900*/ IADD3 R12, R2, 0x5, RZ ; /* 0x00000005020c7810 */
/* 0x004fc80007ffe0ff */
/*0910*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0083e8000c101904 */
/*0920*/ LDG.E R21, [R6.64+-0x8] ; /* 0xfffff80406157981 */
/* 0x000ea2000c1e1900 */
/*0930*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe200078e0005 */
/*0940*/ IADD3 R4, R0, 0x4, RZ ; /* 0x0000000400047810 */
/* 0x000fc80007ffe0ff */
/*0950*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0043e8000c101904 */
/*0960*/ LDG.E R15, [R6.64+-0xc] ; /* 0xfffff404060f7981 */
/* 0x001ea2000c1e1900 */
/*0970*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0005 */
/*0980*/ IADD3 R14, R3, -0x7, RZ ; /* 0xfffffff9030e7810 */
/* 0x000fe40007ffe0ff */
/*0990*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*09a0*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc40007ffe0ff */
/*09b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0043e8000c101904 */
/*09e0*/ ISETP.GT.OR P0, PT, R3, -0x1, P0 ; /* 0xffffffff0300780c */
/* 0x000fda0000704670 */
/*09f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a00*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x002fc800078e00ff */
/*0a10*/ IMAD.WIDE R4, R3, R11, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fca00078e020b */
/*0a20*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R6, -R14, c[0x0][0x170], RZ ; /* 0x00005c000e067a10 */
/* 0x000fca0007ffe1ff */
/*0a40*/ IMAD.WIDE.U32 R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e000b */
/*0a50*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x004fe8000c101904 */
/*0a60*/ LDG.E R15, [R4.64+-0x4] ; /* 0xfffffc04040f7981 */
/* 0x000ea2000c1e1900 */
/*0a70*/ IMAD.WIDE.U32 R8, R2.reuse, R11, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x040fe200078e000b */
/*0a80*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x004fe8000c101904 */
/*0aa0*/ LDG.E R17, [R4.64+-0x8] ; /* 0xfffff80404117981 */
/* 0x000ea2000c1e1900 */
/*0ab0*/ IMAD.WIDE.U32 R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e000b */
/*0ac0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x004fe8000c101904 */
/*0ad0*/ LDG.E R19, [R4.64+-0xc] ; /* 0xfffff40404137981 */
/* 0x000ea2000c1e1900 */
/*0ae0*/ IMAD.WIDE.U32 R10, R0, R11, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x000fca00078e000b */
/*0af0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x004fe2000c101904 */
/*0b00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b10*/ BRA 0xb10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R7, R2, R7, RZ ; /* 0x0000000702077210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
cudaError_t addWithCuda(int* c, const int* a, const int* b, unsigned int size);
int getSPcores(cudaDeviceProp devProp)
{
int cores = 0;
int mp = devProp.multiProcessorCount;
switch (devProp.major) {
case 2: // Fermi
if (devProp.minor == 1) cores = mp * 48;
else cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if ((devProp.minor == 1) || (devProp.minor == 2)) cores = mp * 128;
else if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 7: // Volta and Turing
if ((devProp.minor == 0) || (devProp.minor == 5)) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 8: // Ampere
if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
default:
printf("Unknown device type\n");
break;
}
printf("Hay %i nucleos\n", cores);
return cores;
}
__global__ void addKernel(int* a, int* b)
{
int i = threadIdx.x;
a[i] += b[i];
}
__global__ void invertirArray(int* dest, int* org, unsigned int n) {
for (int i = n - 1; i >= 0; i--) {
dest[(n - 1) - i] = org[i];
}
}
int main()
{
int deviceID = 0, ncores, nvec;
int* hst_matriz = NULL;
int* dev_matriz = NULL;
int* dev_matriz_inver = NULL;
int deviceCount;
cudaGetDeviceCount(&deviceCount);
cudaDeviceProp props;
cudaGetDeviceProperties(&props, deviceID);
ncores = getSPcores(props);
printf("Numero de valores del vector(max %i): ", ncores);
scanf("%i", &nvec);
hst_matriz = (int*)malloc(nvec * sizeof(int));
cudaMallocManaged((void**)&dev_matriz, nvec * sizeof(int));
cudaMallocManaged((void**)&dev_matriz_inver, nvec * sizeof(int));
// Generacion del array
srand(time(NULL));
for (int i = 0; i < nvec; i++) {
hst_matriz[i] = rand() % 10;
}
int* arr = (int*)malloc(nvec * sizeof(int));
cudaMemcpy((void**)dev_matriz, hst_matriz, nvec * sizeof(int), cudaMemcpyHostToDevice);
invertirArray <<<1,1>>> (dev_matriz_inver, dev_matriz, nvec);
addKernel <<<1,nvec>>> (dev_matriz, dev_matriz_inver);
cudaMemcpy((void**)hst_matriz,dev_matriz,nvec*sizeof(int),cudaMemcpyDeviceToHost);
printf("Resultado final:");
for (int i = 0; i < nvec;i++) {
printf("[%i]",hst_matriz[i]);
}
} | .file "tmpxft_0006220a_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Unknown device type\n"
.LC1:
.string "Hay %i nucleos\n"
.text
.globl _Z10getSPcores14cudaDeviceProp
.type _Z10getSPcores14cudaDeviceProp, @function
_Z10getSPcores14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl 380(%rsp), %esi
movl 404(%rsp), %ecx
cmpl $8, 376(%rsp)
ja .L4
movl 376(%rsp), %eax
leaq .L6(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L6:
.long .L4-.L6
.long .L4-.L6
.long .L11-.L6
.long .L10-.L6
.long .L4-.L6
.long .L9-.L6
.long .L8-.L6
.long .L7-.L6
.long .L5-.L6
.text
.L11:
movl %ecx, %ebx
sall $5, %ebx
cmpl $1, %esi
jne .L13
leal (%rcx,%rcx,2), %ebx
sall $4, %ebx
jmp .L13
.L10:
leal (%rcx,%rcx,2), %ebx
sall $6, %ebx
.L13:
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
sall $7, %ecx
movl %ecx, %ebx
jmp .L13
.L8:
leal -1(%rsi), %eax
cmpl $1, %eax
jbe .L21
testl %esi, %esi
jne .L15
sall $6, %ecx
movl %ecx, %ebx
jmp .L13
.L21:
sall $7, %ecx
movl %ecx, %ebx
jmp .L13
.L15:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L13
.L7:
cmpl $5, %esi
je .L19
testl %esi, %esi
jne .L16
.L19:
sall $6, %ecx
movl %ecx, %ebx
jmp .L13
.L16:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L13
.L5:
testl %esi, %esi
jne .L18
sall $6, %ecx
movl %ecx, %ebx
jmp .L13
.L18:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L13
.L4:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L13
.cfi_endproc
.LFE2057:
.size _Z10getSPcores14cudaDeviceProp, .-_Z10getSPcores14cudaDeviceProp
.globl _Z30__device_stub__Z9addKernelPiS_PiS_
.type _Z30__device_stub__Z9addKernelPiS_PiS_, @function
_Z30__device_stub__Z9addKernelPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z9addKernelPiS_PiS_, .-_Z30__device_stub__Z9addKernelPiS_PiS_
.globl _Z9addKernelPiS_
.type _Z9addKernelPiS_, @function
_Z9addKernelPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9addKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9addKernelPiS_, .-_Z9addKernelPiS_
.globl _Z36__device_stub__Z13invertirArrayPiS_jPiS_j
.type _Z36__device_stub__Z13invertirArrayPiS_jPiS_j, @function
_Z36__device_stub__Z13invertirArrayPiS_jPiS_j:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13invertirArrayPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z13invertirArrayPiS_jPiS_j, .-_Z36__device_stub__Z13invertirArrayPiS_jPiS_j
.globl _Z13invertirArrayPiS_j
.type _Z13invertirArrayPiS_j, @function
_Z13invertirArrayPiS_j:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13invertirArrayPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13invertirArrayPiS_j, .-_Z13invertirArrayPiS_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Numero de valores del vector(max %i): "
.section .rodata.str1.1
.LC3:
.string "%i"
.LC4:
.string "Resultado final:"
.LC5:
.string "[%i]"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1088, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq 48(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2160
movl $129, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep movsq
call _Z10getSPcores14cudaDeviceProp
movl %eax, %edx
addq $1040, %rsp
.cfi_def_cfa_offset 1120
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq (%rsp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movslq (%rsp), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl (%rsp), %edx
testl %edx, %edx
jle .L39
movl $0, %ebx
.L40:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx,4)
movl (%rsp), %edx
addq $1, %rbx
cmpl %ebx, %edx
jg .L40
.L39:
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L41:
movl (%rsp), %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L42:
movslq (%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, (%rsp)
jle .L43
movl $0, %ebx
leaq .LC5(%rip), %r12
.L44:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, (%rsp)
jg .L44
.L43:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $1088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movl (%rsp), %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z13invertirArrayPiS_jPiS_j
jmp .L41
.L50:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9addKernelPiS_PiS_
jmp .L42
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z13invertirArrayPiS_j"
.LC7:
.string "_Z9addKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13invertirArrayPiS_j(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda_runtime.h>
#include "device_launch_parameters.h"
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
cudaError_t addWithCuda(int* c, const int* a, const int* b, unsigned int size);
int getSPcores(cudaDeviceProp devProp)
{
int cores = 0;
int mp = devProp.multiProcessorCount;
switch (devProp.major) {
case 2: // Fermi
if (devProp.minor == 1) cores = mp * 48;
else cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if ((devProp.minor == 1) || (devProp.minor == 2)) cores = mp * 128;
else if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 7: // Volta and Turing
if ((devProp.minor == 0) || (devProp.minor == 5)) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 8: // Ampere
if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
default:
printf("Unknown device type\n");
break;
}
printf("Hay %i nucleos\n", cores);
return cores;
}
__global__ void addKernel(int* a, int* b)
{
int i = threadIdx.x;
a[i] += b[i];
}
__global__ void invertirArray(int* dest, int* org, unsigned int n) {
for (int i = n - 1; i >= 0; i--) {
dest[(n - 1) - i] = org[i];
}
}
int main()
{
int deviceID = 0, ncores, nvec;
int* hst_matriz = NULL;
int* dev_matriz = NULL;
int* dev_matriz_inver = NULL;
int deviceCount;
cudaGetDeviceCount(&deviceCount);
cudaDeviceProp props;
cudaGetDeviceProperties(&props, deviceID);
ncores = getSPcores(props);
printf("Numero de valores del vector(max %i): ", ncores);
scanf("%i", &nvec);
hst_matriz = (int*)malloc(nvec * sizeof(int));
cudaMallocManaged((void**)&dev_matriz, nvec * sizeof(int));
cudaMallocManaged((void**)&dev_matriz_inver, nvec * sizeof(int));
// Generacion del array
srand(time(NULL));
for (int i = 0; i < nvec; i++) {
hst_matriz[i] = rand() % 10;
}
int* arr = (int*)malloc(nvec * sizeof(int));
cudaMemcpy((void**)dev_matriz, hst_matriz, nvec * sizeof(int), cudaMemcpyHostToDevice);
invertirArray <<<1,1>>> (dev_matriz_inver, dev_matriz, nvec);
addKernel <<<1,nvec>>> (dev_matriz, dev_matriz_inver);
cudaMemcpy((void**)hst_matriz,dev_matriz,nvec*sizeof(int),cudaMemcpyDeviceToHost);
printf("Resultado final:");
for (int i = 0; i < nvec;i++) {
printf("[%i]",hst_matriz[i]);
}
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
hipError_t addWithCuda(int* c, const int* a, const int* b, unsigned int size);
int getSPcores(hipDeviceProp_t devProp)
{
int cores = 0;
int mp = devProp.multiProcessorCount;
switch (devProp.major) {
case 2: // Fermi
if (devProp.minor == 1) cores = mp * 48;
else cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if ((devProp.minor == 1) || (devProp.minor == 2)) cores = mp * 128;
else if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 7: // Volta and Turing
if ((devProp.minor == 0) || (devProp.minor == 5)) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 8: // Ampere
if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
default:
printf("Unknown device type\n");
break;
}
printf("Hay %i nucleos\n", cores);
return cores;
}
__global__ void addKernel(int* a, int* b)
{
int i = threadIdx.x;
a[i] += b[i];
}
__global__ void invertirArray(int* dest, int* org, unsigned int n) {
for (int i = n - 1; i >= 0; i--) {
dest[(n - 1) - i] = org[i];
}
}
int main()
{
int deviceID = 0, ncores, nvec;
int* hst_matriz = NULL;
int* dev_matriz = NULL;
int* dev_matriz_inver = NULL;
int deviceCount;
hipGetDeviceCount(&deviceCount);
hipDeviceProp_t props;
hipGetDeviceProperties(&props, deviceID);
ncores = getSPcores(props);
printf("Numero de valores del vector(max %i): ", ncores);
scanf("%i", &nvec);
hst_matriz = (int*)malloc(nvec * sizeof(int));
hipMallocManaged((void**)&dev_matriz, nvec * sizeof(int));
hipMallocManaged((void**)&dev_matriz_inver, nvec * sizeof(int));
// Generacion del array
srand(time(NULL));
for (int i = 0; i < nvec; i++) {
hst_matriz[i] = rand() % 10;
}
int* arr = (int*)malloc(nvec * sizeof(int));
hipMemcpy((void**)dev_matriz, hst_matriz, nvec * sizeof(int), hipMemcpyHostToDevice);
invertirArray <<<1,1>>> (dev_matriz_inver, dev_matriz, nvec);
addKernel <<<1,nvec>>> (dev_matriz, dev_matriz_inver);
hipMemcpy((void**)hst_matriz,dev_matriz,nvec*sizeof(int),hipMemcpyDeviceToHost);
printf("Resultado final:");
for (int i = 0; i < nvec;i++) {
printf("[%i]",hst_matriz[i]);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
hipError_t addWithCuda(int* c, const int* a, const int* b, unsigned int size);
int getSPcores(hipDeviceProp_t devProp)
{
int cores = 0;
int mp = devProp.multiProcessorCount;
switch (devProp.major) {
case 2: // Fermi
if (devProp.minor == 1) cores = mp * 48;
else cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if ((devProp.minor == 1) || (devProp.minor == 2)) cores = mp * 128;
else if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 7: // Volta and Turing
if ((devProp.minor == 0) || (devProp.minor == 5)) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 8: // Ampere
if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
default:
printf("Unknown device type\n");
break;
}
printf("Hay %i nucleos\n", cores);
return cores;
}
__global__ void addKernel(int* a, int* b)
{
int i = threadIdx.x;
a[i] += b[i];
}
__global__ void invertirArray(int* dest, int* org, unsigned int n) {
for (int i = n - 1; i >= 0; i--) {
dest[(n - 1) - i] = org[i];
}
}
int main()
{
int deviceID = 0, ncores, nvec;
int* hst_matriz = NULL;
int* dev_matriz = NULL;
int* dev_matriz_inver = NULL;
int deviceCount;
hipGetDeviceCount(&deviceCount);
hipDeviceProp_t props;
hipGetDeviceProperties(&props, deviceID);
ncores = getSPcores(props);
printf("Numero de valores del vector(max %i): ", ncores);
scanf("%i", &nvec);
hst_matriz = (int*)malloc(nvec * sizeof(int));
hipMallocManaged((void**)&dev_matriz, nvec * sizeof(int));
hipMallocManaged((void**)&dev_matriz_inver, nvec * sizeof(int));
// Generacion del array
srand(time(NULL));
for (int i = 0; i < nvec; i++) {
hst_matriz[i] = rand() % 10;
}
int* arr = (int*)malloc(nvec * sizeof(int));
hipMemcpy((void**)dev_matriz, hst_matriz, nvec * sizeof(int), hipMemcpyHostToDevice);
invertirArray <<<1,1>>> (dev_matriz_inver, dev_matriz, nvec);
addKernel <<<1,nvec>>> (dev_matriz, dev_matriz_inver);
hipMemcpy((void**)hst_matriz,dev_matriz,nvec*sizeof(int),hipMemcpyDeviceToHost);
printf("Resultado final:");
for (int i = 0; i < nvec;i++) {
printf("[%i]",hst_matriz[i]);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiS_
.globl _Z9addKernelPiS_
.p2align 8
.type _Z9addKernelPiS_,@function
_Z9addKernelPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiS_, .Lfunc_end0-_Z9addKernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13invertirArrayPiS_j
.globl _Z13invertirArrayPiS_j
.p2align 8
.type _Z13invertirArrayPiS_j,@function
_Z13invertirArrayPiS_j:
s_load_b32 s6, s[0:1], 0x10
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s4, 0
s_cbranch_scc1 .LBB1_3
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b64 s[4:5], s[4:5], 2
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
.LBB1_2:
global_load_b32 v1, v0, s[2:3]
s_add_i32 s6, s6, -1
s_add_u32 s2, s2, -4
s_addc_u32 s3, s3, -1
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lt_i32 s6, 1
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13invertirArrayPiS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13invertirArrayPiS_j, .Lfunc_end1-_Z13invertirArrayPiS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13invertirArrayPiS_j
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z13invertirArrayPiS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
hipError_t addWithCuda(int* c, const int* a, const int* b, unsigned int size);
int getSPcores(hipDeviceProp_t devProp)
{
int cores = 0;
int mp = devProp.multiProcessorCount;
switch (devProp.major) {
case 2: // Fermi
if (devProp.minor == 1) cores = mp * 48;
else cores = mp * 32;
break;
case 3: // Kepler
cores = mp * 192;
break;
case 5: // Maxwell
cores = mp * 128;
break;
case 6: // Pascal
if ((devProp.minor == 1) || (devProp.minor == 2)) cores = mp * 128;
else if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 7: // Volta and Turing
if ((devProp.minor == 0) || (devProp.minor == 5)) cores = mp * 64;
else printf("Unknown device type\n");
break;
case 8: // Ampere
if (devProp.minor == 0) cores = mp * 64;
else printf("Unknown device type\n");
break;
default:
printf("Unknown device type\n");
break;
}
printf("Hay %i nucleos\n", cores);
return cores;
}
__global__ void addKernel(int* a, int* b)
{
int i = threadIdx.x;
a[i] += b[i];
}
__global__ void invertirArray(int* dest, int* org, unsigned int n) {
for (int i = n - 1; i >= 0; i--) {
dest[(n - 1) - i] = org[i];
}
}
int main()
{
int deviceID = 0, ncores, nvec;
int* hst_matriz = NULL;
int* dev_matriz = NULL;
int* dev_matriz_inver = NULL;
int deviceCount;
hipGetDeviceCount(&deviceCount);
hipDeviceProp_t props;
hipGetDeviceProperties(&props, deviceID);
ncores = getSPcores(props);
printf("Numero de valores del vector(max %i): ", ncores);
scanf("%i", &nvec);
hst_matriz = (int*)malloc(nvec * sizeof(int));
hipMallocManaged((void**)&dev_matriz, nvec * sizeof(int));
hipMallocManaged((void**)&dev_matriz_inver, nvec * sizeof(int));
// Generacion del array
srand(time(NULL));
for (int i = 0; i < nvec; i++) {
hst_matriz[i] = rand() % 10;
}
int* arr = (int*)malloc(nvec * sizeof(int));
hipMemcpy((void**)dev_matriz, hst_matriz, nvec * sizeof(int), hipMemcpyHostToDevice);
invertirArray <<<1,1>>> (dev_matriz_inver, dev_matriz, nvec);
addKernel <<<1,nvec>>> (dev_matriz, dev_matriz_inver);
hipMemcpy((void**)hst_matriz,dev_matriz,nvec*sizeof(int),hipMemcpyDeviceToHost);
printf("Resultado final:");
for (int i = 0; i < nvec;i++) {
printf("[%i]",hst_matriz[i]);
}
} | .text
.file "kernel.hip"
.globl _Z10getSPcores20hipDeviceProp_tR0600 # -- Begin function _Z10getSPcores20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z10getSPcores20hipDeviceProp_tR0600,@function
_Z10getSPcores20hipDeviceProp_tR0600: # @_Z10getSPcores20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl 376(%rsp), %eax
addl $-2, %eax
cmpl $6, %eax
ja .LBB0_15
# %bb.1:
leaq 16(%rsp), %rcx
movl 404(%rsp), %ebx
jmpq *.LJTI0_0(,%rax,8)
.LBB0_2:
cmpl $1, 364(%rcx)
jne .LBB0_13
# %bb.3:
shll $4, %ebx
leal (%rbx,%rbx,2), %ebx
jmp .LBB0_16
.LBB0_5:
cmpl $0, 364(%rcx)
jne .LBB0_15
jmp .LBB0_17
.LBB0_7:
shll $6, %ebx
leal (%rbx,%rbx,2), %ebx
jmp .LBB0_16
.LBB0_8:
movl 364(%rcx), %eax
leal -1(%rax), %ecx
cmpl $1, %ecx
ja .LBB0_14
.LBB0_4:
shll $7, %ebx
jmp .LBB0_16
.LBB0_10:
movl 364(%rcx), %eax
cmpl $5, %eax
je .LBB0_17
# %bb.11:
testl %eax, %eax
jne .LBB0_15
.LBB0_17:
shll $6, %ebx
jmp .LBB0_16
.LBB0_13:
shll $5, %ebx
jmp .LBB0_16
.LBB0_14:
testl %eax, %eax
je .LBB0_17
.LBB0_15:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %ebx, %ebx
.LBB0_16:
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10getSPcores20hipDeviceProp_tR0600, .Lfunc_end0-_Z10getSPcores20hipDeviceProp_tR0600
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI0_0:
.quad .LBB0_2
.quad .LBB0_7
.quad .LBB0_15
.quad .LBB0_4
.quad .LBB0_8
.quad .LBB0_10
.quad .LBB0_5
# -- End function
.text
.globl _Z24__device_stub__addKernelPiS_ # -- Begin function _Z24__device_stub__addKernelPiS_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiS_,@function
_Z24__device_stub__addKernelPiS_: # @_Z24__device_stub__addKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__addKernelPiS_, .Lfunc_end1-_Z24__device_stub__addKernelPiS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__invertirArrayPiS_j # -- Begin function _Z28__device_stub__invertirArrayPiS_j
.p2align 4, 0x90
.type _Z28__device_stub__invertirArrayPiS_j,@function
_Z28__device_stub__invertirArrayPiS_j: # @_Z28__device_stub__invertirArrayPiS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13invertirArrayPiS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z28__device_stub__invertirArrayPiS_j, .Lfunc_end2-_Z28__device_stub__invertirArrayPiS_j
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 1632
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 132(%rsp), %rdi
callq hipGetDeviceCount
leaq 136(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
subq $1472, %rsp # imm = 0x5C0
.cfi_adjust_cfa_offset 1472
movl $184, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep
callq _Z10getSPcores20hipDeviceProp_tR0600
addq $1472, %rsp # imm = 0x5C0
.cfi_adjust_cfa_offset -1472
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
movslq 4(%rsp), %rax
cmpq %rax, %r14
jl .LBB3_2
.LBB3_3: # %._crit_edge
movabsq $4294967297, %r14 # imm = 0x100000001
movslq %eax, %rdx
shlq $2, %rdx
movq 8(%rsp), %rdi
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl 4(%rsp), %edx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl %edx, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 92(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13invertirArrayPiS_j, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
movl 4(%rsp), %eax
leaq (%r14,%rax), %rdx
decq %rdx
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7:
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB3_10
# %bb.8: # %.lr.ph39.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_9: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r14
movslq 4(%rsp), %rax
cmpq %rax, %r14
jl .LBB3_9
.LBB3_10: # %._crit_edge40
xorl %eax, %eax
addq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13invertirArrayPiS_j, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Hay %i nucleos\n"
.size .L.str.1, 16
.type _Z9addKernelPiS_,@object # @_Z9addKernelPiS_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiS_
.p2align 3, 0x0
_Z9addKernelPiS_:
.quad _Z24__device_stub__addKernelPiS_
.size _Z9addKernelPiS_, 8
.type _Z13invertirArrayPiS_j,@object # @_Z13invertirArrayPiS_j
.globl _Z13invertirArrayPiS_j
.p2align 3, 0x0
_Z13invertirArrayPiS_j:
.quad _Z28__device_stub__invertirArrayPiS_j
.size _Z13invertirArrayPiS_j, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Numero de valores del vector(max %i): "
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%i"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Resultado final:"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "[%i]"
.size .L.str.5, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiS_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13invertirArrayPiS_j"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.3,@object # @str.3
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.3:
.asciz "Unknown device type"
.size .Lstr.3, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiS_
.addrsig_sym _Z28__device_stub__invertirArrayPiS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiS_
.addrsig_sym _Z13invertirArrayPiS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13invertirArrayPiS_j
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fca00078e00ff */
/*0020*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fc80007ffe0ff */
/*0030*/ ISETP.GE.AND P0, PT, R0, RZ, PT ; /* 0x000000ff0000720c */
/* 0x000fda0003f06270 */
/*0040*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0050*/ LOP3.LUT P0, R2, R2, 0x3, RZ, 0xc0, !PT ; /* 0x0000000302027812 */
/* 0x000fe2000780c0ff */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0070*/ IMAD.MOV.U32 R3, RZ, RZ, R0 ; /* 0x000000ffff037224 */
/* 0x000fe400078e0000 */
/*0080*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0e7624 */
/* 0x000fd200078e00ff */
/*0090*/ @!P0 BRA 0x1a0 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R6, RZ, RZ, R2 ; /* 0x000000ffff067224 */
/* 0x000fe200078e0002 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ IMAD.MOV.U32 R14, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff0e7624 */
/* 0x000fca00078e00ff */
/*00d0*/ IADD3 R14, R14, -0x1, RZ ; /* 0xffffffff0e0e7810 */
/* 0x000fe20007ffe0ff */
/*00e0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x001fc800078e00ff */
/*00f0*/ IMAD.WIDE R2, R14, R3, c[0x0][0x168] ; /* 0x00005a000e027625 */
/* 0x000fcc00078e0203 */
/*0100*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1900 */
/*0110*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe20007ffe0ff */
/*0120*/ IMAD.U32 R4, RZ, RZ, UR6 ; /* 0x00000006ff047e24 */
/* 0x000fe2000f8e00ff */
/*0130*/ UIADD3 UR6, UP0, UR6, 0x4, URZ ; /* 0x0000000406067890 */
/* 0x000fe2000ff1e03f */
/*0140*/ IMAD.U32 R5, RZ, RZ, UR7 ; /* 0x00000007ff057e24 */
/* 0x000fe2000f8e00ff */
/*0150*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe40003f05270 */
/*0160*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe400087fe43f */
/*0170*/ STG.E [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x0041f2000c101904 */
/*0180*/ @P0 BRA 0xd0 ; /* 0xffffff4000000947 */
/* 0x000fea000383ffff */
/*0190*/ IADD3 R3, R14, -0x1, RZ ; /* 0xffffffff0e037810 */
/* 0x001fe40007ffe0ff */
/*01a0*/ ISETP.GE.U32.AND P0, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fda0003f06070 */
/*01b0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*01c0*/ IADD3 R0, R3.reuse, 0x1, RZ ; /* 0x0000000103007810 */
/* 0x040fe40007ffe0ff */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0f070 */
/*01e0*/ ISETP.GT.AND P1, PT, R0, 0xc, PT ; /* 0x0000000c0000780c */
/* 0x000fe20003f24270 */
/*01f0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x2 ; /* 0x00000002ff007424 */
/* 0x000fe200078e00ff */
/*0200*/ IADD3 R2, -R3, c[0x0][0x170], RZ ; /* 0x00005c0003027a10 */
/* 0x000fc80007ffe1ff */
/*0210*/ IADD3 R0, -R3, c[0x0][0x170], R0 ; /* 0x00005c0003007a10 */
/* 0x000fce0007ffe100 */
/*0220*/ @!P1 BRA 0x730 ; /* 0x0000050000009947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x002fc800078e00ff */
/*0250*/ IMAD.WIDE R8, R3, R5, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fca00078e0205 */
/*0260*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea2000c1e1900 */
/*0270*/ IADD3 R6, -R14, c[0x0][0x170], RZ ; /* 0x00005c000e067a10 */
/* 0x000fca0007ffe1ff */
/*0280*/ IMAD.WIDE.U32 R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0005 */
/*0290*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0041e8000c101904 */
/*02a0*/ LDG.E R19, [R8.64+-0x4] ; /* 0xfffffc0408137981 */
/* 0x000ea2000c1e1900 */
/*02b0*/ IMAD.WIDE.U32 R10, R2.reuse, R5, c[0x0][0x160] ; /* 0x00005800020a7625 */
/* 0x040fe200078e0005 */
/*02c0*/ IADD3 R12, R2, 0x1, RZ ; /* 0x00000001020c7810 */
/* 0x000fc80007ffe0ff */
/*02d0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0043e8000c101904 */
/*02e0*/ LDG.E R21, [R8.64+-0x8] ; /* 0xfffff80408157981 */
/* 0x000ea2000c1e1900 */
/*02f0*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe200078e0005 */
/*0300*/ IADD3 R4, R3, -0x4, RZ ; /* 0xfffffffc03047810 */
/* 0x000fc80007ffe0ff */
/*0310*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0045e8000c101904 */
/*0320*/ LDG.E R23, [R8.64+-0xc] ; /* 0xfffff40408177981 */
/* 0x000ee2000c1e1900 */
/*0330*/ IMAD.WIDE.U32 R14, R0, R5, c[0x0][0x160] ; /* 0x00005800000e7625 */
/* 0x000fc800078e0005 */
/*0340*/ IMAD.WIDE R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x001fe200078e0205 */
/*0350*/ IADD3 R4, R3, -0x3, RZ ; /* 0xfffffffd03047810 */
/* 0x000fe20007ffe0ff */
/*0360*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0081e8000c101904 */
/*0370*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee2000c1e1900 */
/*0380*/ IADD3 R4, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fca0007ffe1ff */
/*0390*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x002fe200078e0005 */
/*03a0*/ IADD3 R12, R2, 0x4, RZ ; /* 0x00000004020c7810 */
/* 0x004fc80007ffe0ff */
/*03b0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0083e8000c101904 */
/*03c0*/ LDG.E R19, [R6.64+-0x4] ; /* 0xfffffc0406137981 */
/* 0x000ea2000c1e1900 */
/*03d0*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe200078e0005 */
/*03e0*/ IADD3 R14, R2, 0x5, RZ ; /* 0x00000005020e7810 */
/* 0x001fc80007ffe0ff */
/*03f0*/ STG.E [R12.64], R19 ; /* 0x000000130c007986 */
/* 0x0041e8000c101904 */
/*0400*/ LDG.E R21, [R6.64+-0x8] ; /* 0xfffff80406157981 */
/* 0x000ea2000c1e1900 */
/*0410*/ IMAD.WIDE.U32 R14, R14, R5.reuse, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x080fe200078e0005 */
/*0420*/ IADD3 R4, R0, 0x4, RZ ; /* 0x0000000400047810 */
/* 0x000fe40007ffe0ff */
/*0430*/ IADD3 R8, R3, -0x8, RZ ; /* 0xfffffff803087810 */
/* 0x000fe40007ffe0ff */
/*0440*/ STG.E [R14.64], R21 ; /* 0x000000150e007986 */
/* 0x0045e8000c101904 */
/*0450*/ LDG.E R23, [R6.64+-0xc] ; /* 0xfffff40406177981 */
/* 0x000ee2000c1e1900 */
/*0460*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x002fc800078e0005 */
/*0470*/ IMAD.WIDE R8, R8, R5, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0205 */
/*0480*/ IADD3 R4, R3, -0x7, RZ ; /* 0xfffffff903047810 */
/* 0x000fe20007ffe0ff */
/*0490*/ STG.E [R10.64], R23 ; /* 0x000000170a007986 */
/* 0x0083e8000c101904 */
/*04a0*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ee2000c1e1900 */
/*04b0*/ IADD3 R4, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fca0007ffe1ff */
/*04c0*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x001fe200078e0005 */
/*04d0*/ IADD3 R14, R2, 0x8, RZ ; /* 0x00000008020e7810 */
/* 0x004fc80007ffe0ff */
/*04e0*/ STG.E [R12.64], R17 ; /* 0x000000110c007986 */
/* 0x0081e8000c101904 */
/*04f0*/ LDG.E R19, [R8.64+-0x4] ; /* 0xfffffc0408137981 */
/* 0x000ea2000c1e1900 */
/*0500*/ IMAD.WIDE.U32 R14, R14, R5, c[0x0][0x160] ; /* 0x000058000e0e7625 */
/* 0x000fe200078e0005 */
/*0510*/ IADD3 R10, R2, 0x9, RZ ; /* 0x00000009020a7810 */
/* 0x002fc80007ffe0ff */
/*0520*/ STG.E [R14.64], R19 ; /* 0x000000130e007986 */
/* 0x0043e8000c101904 */
/*0530*/ LDG.E R21, [R8.64+-0x8] ; /* 0xfffff80408157981 */
/* 0x000ea2000c1e1900 */
/*0540*/ IMAD.WIDE.U32 R10, R10, R5.reuse, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x080fe200078e0005 */
/*0550*/ IADD3 R4, R0, 0x8, RZ ; /* 0x0000000800047810 */
/* 0x000fe40007ffe0ff */
/*0560*/ IADD3 R6, R3, -0xc, RZ ; /* 0xfffffff403067810 */
/* 0x000fe40007ffe0ff */
/*0570*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0045e8000c101904 */
/*0580*/ LDG.E R23, [R8.64+-0xc] ; /* 0xfffff40408177981 */
/* 0x000ee2000c1e1900 */
/*0590*/ IMAD.WIDE.U32 R12, R4, R5, c[0x0][0x160] ; /* 0x00005800040c7625 */
/* 0x001fc800078e0005 */
/*05a0*/ IMAD.WIDE R6, R6, R5, c[0x0][0x168] ; /* 0x00005a0006067625 */
/* 0x000fe200078e0205 */
/*05b0*/ IADD3 R4, R3, -0xb, RZ ; /* 0xfffffff503047810 */
/* 0x000fe20007ffe0ff */
/*05c0*/ STG.E [R12.64], R23 ; /* 0x000000170c007986 */
/* 0x008fe8000c101904 */
/*05d0*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee2000c1e1900 */
/*05e0*/ IADD3 R4, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fca0007ffe1ff */
/*05f0*/ IMAD.WIDE.U32 R14, R4, R5, c[0x0][0x160] ; /* 0x00005800040e7625 */
/* 0x002fe200078e0005 */
/*0600*/ IADD3 R8, R2, 0xc, RZ ; /* 0x0000000c02087810 */
/* 0x000fc80007ffe0ff */
/*0610*/ STG.E [R14.64], R17 ; /* 0x000000110e007986 */
/* 0x0081e8000c101904 */
/*0620*/ LDG.E R19, [R6.64+-0x4] ; /* 0xfffffc0406137981 */
/* 0x000ee2000c1e1900 */
/*0630*/ IMAD.WIDE.U32 R8, R8, R5, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0005 */
/*0640*/ IADD3 R10, R2, 0xd, RZ ; /* 0x0000000d020a7810 */
/* 0x004fc80007ffe0ff */
/*0650*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0083e8000c101904 */
/*0660*/ LDG.E R21, [R6.64+-0x8] ; /* 0xfffff80406157981 */
/* 0x000ea2000c1e1900 */
/*0670*/ IMAD.WIDE.U32 R10, R10, R5, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fe200078e0005 */
/*0680*/ IADD3 R14, R3.reuse, -0xf, RZ ; /* 0xfffffff1030e7810 */
/* 0x041fe40007ffe0ff */
/*0690*/ IADD3 R3, R3, -0x10, RZ ; /* 0xfffffff003037810 */
/* 0x000fe40007ffe0ff */
/*06a0*/ IADD3 R4, R0, 0xc, RZ ; /* 0x0000000c00047810 */
/* 0x000fc40007ffe0ff */
/*06b0*/ ISETP.GT.AND P1, PT, R3, 0xb, PT ; /* 0x0000000b0300780c */
/* 0x000fe20003f24270 */
/*06c0*/ STG.E [R10.64], R21 ; /* 0x000000150a007986 */
/* 0x0043e8000c101904 */
/*06d0*/ LDG.E R13, [R6.64+-0xc] ; /* 0xfffff404060d7981 */
/* 0x000ea2000c1e1900 */
/*06e0*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0005 */
/*06f0*/ IADD3 R0, R0, 0x10, RZ ; /* 0x0000001000007810 */
/* 0x000fe40007ffe0ff */
/*0700*/ IADD3 R2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fe40007ffe0ff */
/*0710*/ STG.E [R4.64], R13 ; /* 0x0000000d04007986 */
/* 0x0043e4000c101904 */
/*0720*/ @P1 BRA 0x240 ; /* 0xfffffb1000001947 */
/* 0x000fea000383ffff */
/*0730*/ IADD3 R4, R3, 0x1, RZ ; /* 0x0000000103047810 */
/* 0x002fc80007ffe0ff */
/*0740*/ ISETP.GT.AND P1, PT, R4, 0x4, PT ; /* 0x000000040400780c */
/* 0x000fda0003f24270 */
/*0750*/ @!P1 BRA 0x9e0 ; /* 0x0000028000009947 */
/* 0x000fea0003800000 */
/*0760*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fc800078e00ff */
/*0770*/ IMAD.WIDE R8, R3, R5, c[0x0][0x168] ; /* 0x00005a0003087625 */
/* 0x000fca00078e0205 */
/*0780*/ LDG.E R17, [R8.64] ; /* 0x0000000408117981 */
/* 0x000ea2000c1e1900 */
/*0790*/ IADD3 R6, -R14, c[0x0][0x170], RZ ; /* 0x00005c000e067a10 */
/* 0x000fca0007ffe1ff */
/*07a0*/ IMAD.WIDE.U32 R6, R6, R5, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e0005 */
/*07b0*/ STG.E [R6.64], R17 ; /* 0x0000001106007986 */
/* 0x0041e8000c101904 */
/*07c0*/ LDG.E R19, [R8.64+-0x4] ; /* 0xfffffc0408137981 */
/* 0x000ea2000c1e1900 */
/*07d0*/ IMAD.WIDE.U32 R10, R2.reuse, R5, c[0x0][0x160] ; /* 0x00005800020a7625 */
/* 0x040fe200078e0005 */
/*07e0*/ IADD3 R12, R2, 0x1, RZ ; /* 0x00000001020c7810 */
/* 0x000fc80007ffe0ff */
/*07f0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x0043e8000c101904 */
/*0800*/ LDG.E R21, [R8.64+-0x8] ; /* 0xfffff80408157981 */
/* 0x000ea2000c1e1900 */
/*0810*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe200078e0005 */
/*0820*/ IADD3 R4, R3, -0x4, RZ ; /* 0xfffffffc03047810 */
/* 0x000fc80007ffe0ff */
/*0830*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0045e8000c101904 */
/*0840*/ LDG.E R23, [R8.64+-0xc] ; /* 0xfffff40408177981 */
/* 0x000ee2000c1e1900 */
/*0850*/ IMAD.WIDE.U32 R14, R0, R5, c[0x0][0x160] ; /* 0x00005800000e7625 */
/* 0x000fc800078e0005 */
/*0860*/ IMAD.WIDE R6, R4, R5, c[0x0][0x168] ; /* 0x00005a0004067625 */
/* 0x001fe200078e0205 */
/*0870*/ IADD3 R4, R3, -0x3, RZ ; /* 0xfffffffd03047810 */
/* 0x000fe20007ffe0ff */
/*0880*/ STG.E [R14.64], R23 ; /* 0x000000170e007986 */
/* 0x0081e8000c101904 */
/*0890*/ LDG.E R17, [R6.64] ; /* 0x0000000406117981 */
/* 0x000ee2000c1e1900 */
/*08a0*/ IADD3 R4, -R4, c[0x0][0x170], RZ ; /* 0x00005c0004047a10 */
/* 0x000fca0007ffe1ff */
/*08b0*/ IMAD.WIDE.U32 R10, R4, R5, c[0x0][0x160] ; /* 0x00005800040a7625 */
/* 0x002fe200078e0005 */
/*08c0*/ IADD3 R8, R2, 0x4, RZ ; /* 0x0000000402087810 */
/* 0x000fc80007ffe0ff */
/*08d0*/ STG.E [R10.64], R17 ; /* 0x000000110a007986 */
/* 0x0083e8000c101904 */
/*08e0*/ LDG.E R19, [R6.64+-0x4] ; /* 0xfffffc0406137981 */
/* 0x000ee2000c1e1900 */
/*08f0*/ IMAD.WIDE.U32 R8, R8, R5, c[0x0][0x160] ; /* 0x0000580008087625 */
/* 0x000fe200078e0005 */
/*0900*/ IADD3 R12, R2, 0x5, RZ ; /* 0x00000005020c7810 */
/* 0x004fc80007ffe0ff */
/*0910*/ STG.E [R8.64], R19 ; /* 0x0000001308007986 */
/* 0x0083e8000c101904 */
/*0920*/ LDG.E R21, [R6.64+-0x8] ; /* 0xfffff80406157981 */
/* 0x000ea2000c1e1900 */
/*0930*/ IMAD.WIDE.U32 R12, R12, R5, c[0x0][0x160] ; /* 0x000058000c0c7625 */
/* 0x000fe200078e0005 */
/*0940*/ IADD3 R4, R0, 0x4, RZ ; /* 0x0000000400047810 */
/* 0x000fc80007ffe0ff */
/*0950*/ STG.E [R12.64], R21 ; /* 0x000000150c007986 */
/* 0x0043e8000c101904 */
/*0960*/ LDG.E R15, [R6.64+-0xc] ; /* 0xfffff404060f7981 */
/* 0x001ea2000c1e1900 */
/*0970*/ IMAD.WIDE.U32 R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe200078e0005 */
/*0980*/ IADD3 R14, R3, -0x7, RZ ; /* 0xfffffff9030e7810 */
/* 0x000fe40007ffe0ff */
/*0990*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*09a0*/ IADD3 R0, R0, 0x8, RZ ; /* 0x0000000800007810 */
/* 0x000fc40007ffe0ff */
/*09b0*/ IADD3 R2, R2, 0x8, RZ ; /* 0x0000000802027810 */
/* 0x000fe40007ffe0ff */
/*09c0*/ IADD3 R3, R3, -0x8, RZ ; /* 0xfffffff803037810 */
/* 0x000fe20007ffe0ff */
/*09d0*/ STG.E [R4.64], R15 ; /* 0x0000000f04007986 */
/* 0x0043e8000c101904 */
/*09e0*/ ISETP.GT.OR P0, PT, R3, -0x1, P0 ; /* 0xffffffff0300780c */
/* 0x000fda0000704670 */
/*09f0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0a00*/ IMAD.MOV.U32 R11, RZ, RZ, 0x4 ; /* 0x00000004ff0b7424 */
/* 0x002fc800078e00ff */
/*0a10*/ IMAD.WIDE R4, R3, R11, c[0x0][0x168] ; /* 0x00005a0003047625 */
/* 0x000fca00078e020b */
/*0a20*/ LDG.E R13, [R4.64] ; /* 0x00000004040d7981 */
/* 0x000ea2000c1e1900 */
/*0a30*/ IADD3 R6, -R14, c[0x0][0x170], RZ ; /* 0x00005c000e067a10 */
/* 0x000fca0007ffe1ff */
/*0a40*/ IMAD.WIDE.U32 R6, R6, R11, c[0x0][0x160] ; /* 0x0000580006067625 */
/* 0x000fca00078e000b */
/*0a50*/ STG.E [R6.64], R13 ; /* 0x0000000d06007986 */
/* 0x004fe8000c101904 */
/*0a60*/ LDG.E R15, [R4.64+-0x4] ; /* 0xfffffc04040f7981 */
/* 0x000ea2000c1e1900 */
/*0a70*/ IMAD.WIDE.U32 R8, R2.reuse, R11, c[0x0][0x160] ; /* 0x0000580002087625 */
/* 0x040fe200078e000b */
/*0a80*/ IADD3 R2, R2, 0x1, RZ ; /* 0x0000000102027810 */
/* 0x000fc80007ffe0ff */
/*0a90*/ STG.E [R8.64], R15 ; /* 0x0000000f08007986 */
/* 0x004fe8000c101904 */
/*0aa0*/ LDG.E R17, [R4.64+-0x8] ; /* 0xfffff80404117981 */
/* 0x000ea2000c1e1900 */
/*0ab0*/ IMAD.WIDE.U32 R2, R2, R11, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e000b */
/*0ac0*/ STG.E [R2.64], R17 ; /* 0x0000001102007986 */
/* 0x004fe8000c101904 */
/*0ad0*/ LDG.E R19, [R4.64+-0xc] ; /* 0xfffff40404137981 */
/* 0x000ea2000c1e1900 */
/*0ae0*/ IMAD.WIDE.U32 R10, R0, R11, c[0x0][0x160] ; /* 0x00005800000a7625 */
/* 0x000fca00078e000b */
/*0af0*/ STG.E [R10.64], R19 ; /* 0x000000130a007986 */
/* 0x004fe2000c101904 */
/*0b00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0b10*/ BRA 0xb10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0b20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0b90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ba0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bc0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bd0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0be0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0bf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9addKernelPiS_
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R4, SR_TID.X ; /* 0x0000000000047919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R4, R5, c[0x0][0x168] ; /* 0x00005a0004027625 */
/* 0x001fc800078e0205 */
/*0050*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fe400078e0205 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R7, [R4.64] ; /* 0x0000000404077981 */
/* 0x000ea4000c1e1900 */
/*0080*/ IADD3 R7, R2, R7, RZ ; /* 0x0000000702077210 */
/* 0x004fca0007ffe0ff */
/*0090*/ STG.E [R4.64], R7 ; /* 0x0000000704007986 */
/* 0x000fe2000c101904 */
/*00a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00b0*/ BRA 0xb0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9addKernelPiS_
.globl _Z9addKernelPiS_
.p2align 8
.type _Z9addKernelPiS_,@function
_Z9addKernelPiS_:
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[2:3]
global_load_b32 v2, v0, s[0:1]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9addKernelPiS_
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 16
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 4
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9addKernelPiS_, .Lfunc_end0-_Z9addKernelPiS_
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z13invertirArrayPiS_j
.globl _Z13invertirArrayPiS_j
.p2align 8
.type _Z13invertirArrayPiS_j,@function
_Z13invertirArrayPiS_j:
s_load_b32 s6, s[0:1], 0x10
s_mov_b32 s5, 0
s_waitcnt lgkmcnt(0)
s_add_i32 s4, s6, -1
s_delay_alu instid0(SALU_CYCLE_1)
s_cmp_lt_i32 s4, 0
s_cbranch_scc1 .LBB1_3
s_load_b128 s[0:3], s[0:1], 0x0
s_lshl_b64 s[4:5], s[4:5], 2
v_mov_b32_e32 v0, 0
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s2, s4
s_addc_u32 s3, s3, s5
.LBB1_2:
global_load_b32 v1, v0, s[2:3]
s_add_i32 s6, s6, -1
s_add_u32 s2, s2, -4
s_addc_u32 s3, s3, -1
s_waitcnt vmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_add_u32 s0, s0, 4
s_addc_u32 s1, s1, 0
s_cmp_lt_i32 s6, 1
s_cbranch_scc0 .LBB1_2
.LBB1_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13invertirArrayPiS_j
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 7
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z13invertirArrayPiS_j, .Lfunc_end1-_Z13invertirArrayPiS_j
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 16
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9addKernelPiS_
.private_segment_fixed_size: 0
.sgpr_count: 4
.sgpr_spill_count: 0
.symbol: _Z9addKernelPiS_.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13invertirArrayPiS_j
.private_segment_fixed_size: 0
.sgpr_count: 7
.sgpr_spill_count: 0
.symbol: _Z13invertirArrayPiS_j.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0006220a_00000000-6_kernel.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Unknown device type\n"
.LC1:
.string "Hay %i nucleos\n"
.text
.globl _Z10getSPcores14cudaDeviceProp
.type _Z10getSPcores14cudaDeviceProp, @function
_Z10getSPcores14cudaDeviceProp:
.LFB2057:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
movl 380(%rsp), %esi
movl 404(%rsp), %ecx
cmpl $8, 376(%rsp)
ja .L4
movl 376(%rsp), %eax
leaq .L6(%rip), %rdx
movslq (%rdx,%rax,4), %rax
addq %rdx, %rax
notrack jmp *%rax
.section .rodata
.align 4
.align 4
.L6:
.long .L4-.L6
.long .L4-.L6
.long .L11-.L6
.long .L10-.L6
.long .L4-.L6
.long .L9-.L6
.long .L8-.L6
.long .L7-.L6
.long .L5-.L6
.text
.L11:
movl %ecx, %ebx
sall $5, %ebx
cmpl $1, %esi
jne .L13
leal (%rcx,%rcx,2), %ebx
sall $4, %ebx
jmp .L13
.L10:
leal (%rcx,%rcx,2), %ebx
sall $6, %ebx
.L13:
movl %ebx, %edx
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %ebx, %eax
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
sall $7, %ecx
movl %ecx, %ebx
jmp .L13
.L8:
leal -1(%rsi), %eax
cmpl $1, %eax
jbe .L21
testl %esi, %esi
jne .L15
sall $6, %ecx
movl %ecx, %ebx
jmp .L13
.L21:
sall $7, %ecx
movl %ecx, %ebx
jmp .L13
.L15:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L13
.L7:
cmpl $5, %esi
je .L19
testl %esi, %esi
jne .L16
.L19:
sall $6, %ecx
movl %ecx, %ebx
jmp .L13
.L16:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L13
.L5:
testl %esi, %esi
jne .L18
sall $6, %ecx
movl %ecx, %ebx
jmp .L13
.L18:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L13
.L4:
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebx
jmp .L13
.cfi_endproc
.LFE2057:
.size _Z10getSPcores14cudaDeviceProp, .-_Z10getSPcores14cudaDeviceProp
.globl _Z30__device_stub__Z9addKernelPiS_PiS_
.type _Z30__device_stub__Z9addKernelPiS_PiS_, @function
_Z30__device_stub__Z9addKernelPiS_PiS_:
.LFB2083:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L26
.L22:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L27
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L26:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z9addKernelPiS_(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L22
.L27:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z30__device_stub__Z9addKernelPiS_PiS_, .-_Z30__device_stub__Z9addKernelPiS_PiS_
.globl _Z9addKernelPiS_
.type _Z9addKernelPiS_, @function
_Z9addKernelPiS_:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z30__device_stub__Z9addKernelPiS_PiS_
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z9addKernelPiS_, .-_Z9addKernelPiS_
.globl _Z36__device_stub__Z13invertirArrayPiS_jPiS_j
.type _Z36__device_stub__Z13invertirArrayPiS_jPiS_j, @function
_Z36__device_stub__Z13invertirArrayPiS_jPiS_j:
.LFB2085:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L34
.L30:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L35
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L34:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13invertirArrayPiS_j(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L30
.L35:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2085:
.size _Z36__device_stub__Z13invertirArrayPiS_jPiS_j, .-_Z36__device_stub__Z13invertirArrayPiS_jPiS_j
.globl _Z13invertirArrayPiS_j
.type _Z13invertirArrayPiS_j, @function
_Z13invertirArrayPiS_j:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z13invertirArrayPiS_jPiS_j
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _Z13invertirArrayPiS_j, .-_Z13invertirArrayPiS_j
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Numero de valores del vector(max %i): "
.section .rodata.str1.1
.LC3:
.string "%i"
.LC4:
.string "Resultado final:"
.LC5:
.string "[%i]"
.text
.globl main
.type main, @function
main:
.LFB2058:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $1088, %rsp
.cfi_def_cfa_offset 1120
movq %fs:40, %rax
movq %rax, 1080(%rsp)
xorl %eax, %eax
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 4(%rsp), %rdi
call cudaGetDeviceCount@PLT
leaq 48(%rsp), %rbx
movl $0, %esi
movq %rbx, %rdi
call cudaGetDeviceProperties_v2@PLT
subq $1040, %rsp
.cfi_def_cfa_offset 2160
movl $129, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep movsq
call _Z10getSPcores14cudaDeviceProp
movl %eax, %edx
addq $1040, %rsp
.cfi_def_cfa_offset 1120
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rsi
leaq .LC3(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movslq (%rsp), %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %rbp
leaq 8(%rsp), %rdi
movl $1, %edx
movq %rbx, %rsi
call cudaMallocManaged@PLT
movslq (%rsp), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
call cudaMallocManaged@PLT
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl (%rsp), %edx
testl %edx, %edx
jle .L39
movl $0, %ebx
.L40:
call rand@PLT
movslq %eax, %rdx
imulq $1717986919, %rdx, %rdx
sarq $34, %rdx
movl %eax, %ecx
sarl $31, %ecx
subl %ecx, %edx
leal (%rdx,%rdx,4), %edx
addl %edx, %edx
subl %edx, %eax
movl %eax, 0(%rbp,%rbx,4)
movl (%rsp), %edx
addq $1, %rbx
cmpl %ebx, %edx
jg .L40
.L39:
movslq %edx, %rdx
salq $2, %rdx
movl $1, %ecx
movq %rbp, %rsi
movq 8(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L49
.L41:
movl (%rsp), %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 36(%rsp), %rdx
movl $1, %ecx
movq 24(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L50
.L42:
movslq (%rsp), %rdx
salq $2, %rdx
movl $2, %ecx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
cmpl $0, (%rsp)
jle .L43
movl $0, %ebx
leaq .LC5(%rip), %r12
.L44:
movl 0(%rbp,%rbx,4), %edx
movq %r12, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $1, %rbx
cmpl %ebx, (%rsp)
jg .L44
.L43:
movq 1080(%rsp), %rax
subq %fs:40, %rax
jne .L51
movl $0, %eax
addq $1088, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L49:
.cfi_restore_state
movl (%rsp), %edx
movq 8(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z13invertirArrayPiS_jPiS_j
jmp .L41
.L50:
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z30__device_stub__Z9addKernelPiS_PiS_
jmp .L42
.L51:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size main, .-main
.section .rodata.str1.1
.LC6:
.string "_Z13invertirArrayPiS_j"
.LC7:
.string "_Z9addKernelPiS_"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2088:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _Z13invertirArrayPiS_j(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _Z9addKernelPiS_(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "kernel.hip"
.globl _Z10getSPcores20hipDeviceProp_tR0600 # -- Begin function _Z10getSPcores20hipDeviceProp_tR0600
.p2align 4, 0x90
.type _Z10getSPcores20hipDeviceProp_tR0600,@function
_Z10getSPcores20hipDeviceProp_tR0600: # @_Z10getSPcores20hipDeviceProp_tR0600
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
movl 376(%rsp), %eax
addl $-2, %eax
cmpl $6, %eax
ja .LBB0_15
# %bb.1:
leaq 16(%rsp), %rcx
movl 404(%rsp), %ebx
jmpq *.LJTI0_0(,%rax,8)
.LBB0_2:
cmpl $1, 364(%rcx)
jne .LBB0_13
# %bb.3:
shll $4, %ebx
leal (%rbx,%rbx,2), %ebx
jmp .LBB0_16
.LBB0_5:
cmpl $0, 364(%rcx)
jne .LBB0_15
jmp .LBB0_17
.LBB0_7:
shll $6, %ebx
leal (%rbx,%rbx,2), %ebx
jmp .LBB0_16
.LBB0_8:
movl 364(%rcx), %eax
leal -1(%rax), %ecx
cmpl $1, %ecx
ja .LBB0_14
.LBB0_4:
shll $7, %ebx
jmp .LBB0_16
.LBB0_10:
movl 364(%rcx), %eax
cmpl $5, %eax
je .LBB0_17
# %bb.11:
testl %eax, %eax
jne .LBB0_15
.LBB0_17:
shll $6, %ebx
jmp .LBB0_16
.LBB0_13:
shll $5, %ebx
jmp .LBB0_16
.LBB0_14:
testl %eax, %eax
je .LBB0_17
.LBB0_15:
movl $.Lstr.3, %edi
callq puts@PLT
xorl %ebx, %ebx
.LBB0_16:
movl $.L.str.1, %edi
movl %ebx, %esi
xorl %eax, %eax
callq printf
movl %ebx, %eax
popq %rbx
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z10getSPcores20hipDeviceProp_tR0600, .Lfunc_end0-_Z10getSPcores20hipDeviceProp_tR0600
.cfi_endproc
.section .rodata,"a",@progbits
.p2align 3, 0x0
.LJTI0_0:
.quad .LBB0_2
.quad .LBB0_7
.quad .LBB0_15
.quad .LBB0_4
.quad .LBB0_8
.quad .LBB0_10
.quad .LBB0_5
# -- End function
.text
.globl _Z24__device_stub__addKernelPiS_ # -- Begin function _Z24__device_stub__addKernelPiS_
.p2align 4, 0x90
.type _Z24__device_stub__addKernelPiS_,@function
_Z24__device_stub__addKernelPiS_: # @_Z24__device_stub__addKernelPiS_
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z9addKernelPiS_, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z24__device_stub__addKernelPiS_, .Lfunc_end1-_Z24__device_stub__addKernelPiS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__invertirArrayPiS_j # -- Begin function _Z28__device_stub__invertirArrayPiS_j
.p2align 4, 0x90
.type _Z28__device_stub__invertirArrayPiS_j,@function
_Z28__device_stub__invertirArrayPiS_j: # @_Z28__device_stub__invertirArrayPiS_j
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13invertirArrayPiS_j, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end2:
.size _Z28__device_stub__invertirArrayPiS_j, .Lfunc_end2-_Z28__device_stub__invertirArrayPiS_j
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 1632
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movq $0, 8(%rsp)
movq $0, 16(%rsp)
leaq 132(%rsp), %rdi
callq hipGetDeviceCount
leaq 136(%rsp), %rbx
movq %rbx, %rdi
xorl %esi, %esi
callq hipGetDevicePropertiesR0600
subq $1472, %rsp # imm = 0x5C0
.cfi_adjust_cfa_offset 1472
movl $184, %ecx
movq %rsp, %rdi
movq %rbx, %rsi
rep
callq _Z10getSPcores20hipDeviceProp_tR0600
addq $1472, %rsp # imm = 0x5C0
.cfi_adjust_cfa_offset -1472
movl $.L.str.2, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
leaq 4(%rsp), %rsi
movl $.L.str.3, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 4(%rsp), %r14
shlq $2, %r14
movq %r14, %rdi
callq malloc
movq %rax, %rbx
leaq 8(%rsp), %rdi
movq %r14, %rsi
movl $1, %edx
callq hipMallocManaged
movslq 4(%rsp), %rsi
shlq $2, %rsi
leaq 16(%rsp), %rdi
movl $1, %edx
callq hipMallocManaged
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl 4(%rsp), %eax
testl %eax, %eax
jle .LBB3_3
# %bb.1: # %.lr.ph.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
callq rand
cltq
imulq $1717986919, %rax, %rcx # imm = 0x66666667
movq %rcx, %rdx
shrq $63, %rdx
sarq $34, %rcx
addl %edx, %ecx
addl %ecx, %ecx
leal (%rcx,%rcx,4), %ecx
subl %ecx, %eax
movl %eax, (%rbx,%r14,4)
incq %r14
movslq 4(%rsp), %rax
cmpq %rax, %r14
jl .LBB3_2
.LBB3_3: # %._crit_edge
movabsq $4294967297, %r14 # imm = 0x100000001
movslq %eax, %rdx
shlq $2, %rdx
movq 8(%rsp), %rdi
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_5
# %bb.4:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movl 4(%rsp), %edx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
movl %edx, 92(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 92(%rsp), %rax
movq %rax, 112(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13invertirArrayPiS_j, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_5:
movl 4(%rsp), %eax
leaq (%r14,%rax), %rdx
decq %rdx
movq %r14, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_7
# %bb.6:
movq 8(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 80(%rsp)
movq %rcx, 72(%rsp)
leaq 80(%rsp), %rax
movq %rax, 96(%rsp)
leaq 72(%rsp), %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z9addKernelPiS_, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_7:
movq 8(%rsp), %rsi
movslq 4(%rsp), %rdx
shlq $2, %rdx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.L.str.4, %edi
xorl %eax, %eax
callq printf
cmpl $0, 4(%rsp)
jle .LBB3_10
# %bb.8: # %.lr.ph39.preheader
xorl %r14d, %r14d
.p2align 4, 0x90
.LBB3_9: # %.lr.ph39
# =>This Inner Loop Header: Depth=1
movl (%rbx,%r14,4), %esi
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
incq %r14
movslq 4(%rsp), %rax
cmpq %rax, %r14
jl .LBB3_9
.LBB3_10: # %._crit_edge40
xorl %eax, %eax
addq $1608, %rsp # imm = 0x648
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9addKernelPiS_, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13invertirArrayPiS_j, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Hay %i nucleos\n"
.size .L.str.1, 16
.type _Z9addKernelPiS_,@object # @_Z9addKernelPiS_
.section .rodata,"a",@progbits
.globl _Z9addKernelPiS_
.p2align 3, 0x0
_Z9addKernelPiS_:
.quad _Z24__device_stub__addKernelPiS_
.size _Z9addKernelPiS_, 8
.type _Z13invertirArrayPiS_j,@object # @_Z13invertirArrayPiS_j
.globl _Z13invertirArrayPiS_j
.p2align 3, 0x0
_Z13invertirArrayPiS_j:
.quad _Z28__device_stub__invertirArrayPiS_j
.size _Z13invertirArrayPiS_j, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Numero de valores del vector(max %i): "
.size .L.str.2, 39
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "%i"
.size .L.str.3, 3
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Resultado final:"
.size .L.str.4, 17
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "[%i]"
.size .L.str.5, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z9addKernelPiS_"
.size .L__unnamed_1, 17
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z13invertirArrayPiS_j"
.size .L__unnamed_2, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr.3,@object # @str.3
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr.3:
.asciz "Unknown device type"
.size .Lstr.3, 20
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__addKernelPiS_
.addrsig_sym _Z28__device_stub__invertirArrayPiS_j
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z9addKernelPiS_
.addrsig_sym _Z13invertirArrayPiS_j
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* One Way Hash with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements a simple hash from a space of size 2n --> n
*
* The following code makes use of the kernel call hash(char *f, char *h, int n)
* to perform a parallel hash of elements f --> h with corresponding indices 2i --> i
*
* The result is a mapping of the data within f to the data within h
* The output is verified before the program terminates to see that every
* element at index 2i of f is indeed at index i in h
*
* We can see that there is a significant speedup in comparison to the time it takes
* to perform the hash in the serial code.
*
* The output of the performance is displayed in seconds.
* The performance results are to be compared with the performance of hash.c
*
*/
// System includes
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
// We also indicate EVEN_NUM as the vector size since this hash requires even length arrays
#define THREADS_PER_BLOCK 1024
#define EVEN_NUM 123374234
__global__ void hash(char *f, char *h, int n) {
int i = blockIdx.x*blockDim.x+threadIdx.x;
if( i < n ){
h[i] = f[2*i];
}
}
int main(void) {
int two_n = EVEN_NUM, i, r=50;
char *f, *h, *d_f,*d_h;
cudaError_t error;
if ( two_n % 2 ){
printf("NO NO NO!!! Even numbers only please.\n");
exit(EXIT_FAILURE);
}
//printf("Malloc space on CPU (f,h)");
f = (char *)calloc(sizeof(char), two_n);
if( f == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for f.",two_n);
exit(EXIT_FAILURE);
}
h = (char *)calloc(sizeof(char), two_n/2);
if( h == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for h.",two_n/2);
exit(EXIT_FAILURE);
}
/* Identify our streams */
//printf("Malloc space on GPU (d_f,d_h)\n");
error = cudaMalloc((void **)&d_f, sizeof(char) * two_n);
if( error != cudaSuccess ){
fprintf(stderr,"Failed to cudaMalloc %d bytes for d_f.",two_n);
exit(EXIT_FAILURE);
}
error = cudaMalloc((void **)&d_h, sizeof(char) * two_n/2);
if( error != cudaSuccess ){
fprintf(stderr,"Failed to cudaMalloc %d bytes for d_h.",two_n/2);
exit(EXIT_FAILURE);
}
//populate data into array
//printf("Generate vectored data (Size=%d bytes)\n",two_n);
for (i = 0; i < two_n; i++) {
f[i] = (char) ((i % 94) + 33);
}
//send data over the bus
//printf("Send data to GPU\n");
error = cudaMemcpy( d_f, f, two_n, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_f,f) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/*************************** Setup for testing ************************************/
//printf("Run kernel code \n");
cudaDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
cudaEvent_t start;
error = cudaEventCreate(&start);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
cudaEvent_t stop;
error = cudaEventCreate(&stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = cudaEventRecord(start, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
printf("Running...\n");
//run kernel
for( i = 0; i < r; i++){
hash<<<(two_n/2+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_f,d_h,two_n/2);
}
// Record the stop event
error = cudaEventRecord(stop, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = cudaEventSynchronize(stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = cudaEventElapsedTime(&msecTotal, start, stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
/*******************************************************************************************
****************************** for testing purposes ***************************************/
//send data over the bus
error = cudaMemcpy( h, d_h, sizeof(char)*two_n/2, cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
printf("cudaMemcpy (h,d_h) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
//printf("Done.\n");
//validate for correctness
for (i = 0; i < two_n/2; i++) {
if (h[i] != f[2*i]) {
//printf("index %d FAILED!\n", i);
exit(EXIT_FAILURE);
}
}
// Compute and print the performance
float msecPerhash = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerhash/1000.0 );
free(f); free(h);
cudaFree(d_f); cudaFree(d_h);
cudaDeviceReset();
return 0;
} | code for sm_80
Function : _Z4hashPcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.SHL.U32 R3, R0, 0x2, RZ ; /* 0x0000000200037824 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fcc00000f0eff */
/*00a0*/ LDG.E.U8 R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f0eff */
/*00d0*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101104 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* One Way Hash with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements a simple hash from a space of size 2n --> n
*
* The following code makes use of the kernel call hash(char *f, char *h, int n)
* to perform a parallel hash of elements f --> h with corresponding indices 2i --> i
*
* The result is a mapping of the data within f to the data within h
* The output is verified before the program terminates to see that every
* element at index 2i of f is indeed at index i in h
*
* We can see that there is a significant speedup in comparison to the time it takes
* to perform the hash in the serial code.
*
* The output of the performance is displayed in seconds.
* The performance results are to be compared with the performance of hash.c
*
*/
// System includes
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
// We also indicate EVEN_NUM as the vector size since this hash requires even length arrays
#define THREADS_PER_BLOCK 1024
#define EVEN_NUM 123374234
__global__ void hash(char *f, char *h, int n) {
int i = blockIdx.x*blockDim.x+threadIdx.x;
if( i < n ){
h[i] = f[2*i];
}
}
int main(void) {
int two_n = EVEN_NUM, i, r=50;
char *f, *h, *d_f,*d_h;
cudaError_t error;
if ( two_n % 2 ){
printf("NO NO NO!!! Even numbers only please.\n");
exit(EXIT_FAILURE);
}
//printf("Malloc space on CPU (f,h)");
f = (char *)calloc(sizeof(char), two_n);
if( f == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for f.",two_n);
exit(EXIT_FAILURE);
}
h = (char *)calloc(sizeof(char), two_n/2);
if( h == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for h.",two_n/2);
exit(EXIT_FAILURE);
}
/* Identify our streams */
//printf("Malloc space on GPU (d_f,d_h)\n");
error = cudaMalloc((void **)&d_f, sizeof(char) * two_n);
if( error != cudaSuccess ){
fprintf(stderr,"Failed to cudaMalloc %d bytes for d_f.",two_n);
exit(EXIT_FAILURE);
}
error = cudaMalloc((void **)&d_h, sizeof(char) * two_n/2);
if( error != cudaSuccess ){
fprintf(stderr,"Failed to cudaMalloc %d bytes for d_h.",two_n/2);
exit(EXIT_FAILURE);
}
//populate data into array
//printf("Generate vectored data (Size=%d bytes)\n",two_n);
for (i = 0; i < two_n; i++) {
f[i] = (char) ((i % 94) + 33);
}
//send data over the bus
//printf("Send data to GPU\n");
error = cudaMemcpy( d_f, f, two_n, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_f,f) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/*************************** Setup for testing ************************************/
//printf("Run kernel code \n");
cudaDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
cudaEvent_t start;
error = cudaEventCreate(&start);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
cudaEvent_t stop;
error = cudaEventCreate(&stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = cudaEventRecord(start, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
printf("Running...\n");
//run kernel
for( i = 0; i < r; i++){
hash<<<(two_n/2+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_f,d_h,two_n/2);
}
// Record the stop event
error = cudaEventRecord(stop, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = cudaEventSynchronize(stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = cudaEventElapsedTime(&msecTotal, start, stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
/*******************************************************************************************
****************************** for testing purposes ***************************************/
//send data over the bus
error = cudaMemcpy( h, d_h, sizeof(char)*two_n/2, cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
printf("cudaMemcpy (h,d_h) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
//printf("Done.\n");
//validate for correctness
for (i = 0; i < two_n/2; i++) {
if (h[i] != f[2*i]) {
//printf("index %d FAILED!\n", i);
exit(EXIT_FAILURE);
}
}
// Compute and print the performance
float msecPerhash = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerhash/1000.0 );
free(f); free(h);
cudaFree(d_f); cudaFree(d_h);
cudaDeviceReset();
return 0;
} | .file "tmpxft_0006584e_00000000-6_hash.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z26__device_stub__Z4hashPcS_iPcS_i
.type _Z26__device_stub__Z4hashPcS_iPcS_i, @function
_Z26__device_stub__Z4hashPcS_iPcS_i:
.LFB2082:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z4hashPcS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z26__device_stub__Z4hashPcS_iPcS_i, .-_Z26__device_stub__Z4hashPcS_iPcS_i
.globl _Z4hashPcS_i
.type _Z4hashPcS_i, @function
_Z4hashPcS_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z26__device_stub__Z4hashPcS_iPcS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z4hashPcS_i, .-_Z4hashPcS_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocate %d bytes for f."
.align 8
.LC1:
.string "Failed to allocate %d bytes for h."
.align 8
.LC2:
.string "Failed to cudaMalloc %d bytes for d_f."
.align 8
.LC3:
.string "Failed to cudaMalloc %d bytes for d_h."
.align 8
.LC4:
.string "cudaMemcpy (d_f,f) returned error code %d, line(%d)\n"
.align 8
.LC5:
.string "Failed to create start event (error code %s)!\n"
.align 8
.LC6:
.string "Failed to create stop event (error code %s)!\n"
.align 8
.LC7:
.string "Failed to record start event (error code %s)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC8:
.string "Running...\n"
.section .rodata.str1.8
.align 8
.LC9:
.string "Failed to record stop event (error code %s)!\n"
.align 8
.LC10:
.string "Failed to synchronize on the stop event (error code %s)!\n"
.align 8
.LC12:
.string "Failed to get time elapsed between events (error code %s)!\n"
.align 8
.LC13:
.string "cudaMemcpy (h,d_h) returned error code %d, line(%d)\n"
.section .rodata.str1.1
.LC15:
.string "Performance= %.06f sec\n"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $123374234, %esi
movl $1, %edi
call calloc@PLT
testq %rax, %rax
je .L34
movq %rax, %rbx
movl $61687117, %esi
movl $1, %edi
call calloc@PLT
movq %rax, %rbp
testq %rax, %rax
je .L35
movq %rsp, %rdi
movl $123374234, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L36
leaq 8(%rsp), %rdi
movl $61687117, %esi
call cudaMalloc@PLT
testl %eax, %eax
jne .L37
movl $0, %edx
.L15:
movslq %edx, %rax
imulq $-1370734243, %rax, %rax
shrq $32, %rax
addl %edx, %eax
sarl $6, %eax
movl %edx, %ecx
sarl $31, %ecx
subl %ecx, %eax
imull $94, %eax, %eax
movl %edx, %ecx
subl %eax, %ecx
leal 33(%rcx), %eax
movb %al, (%rbx,%rdx)
addq $1, %rdx
cmpq $123374234, %rdx
jne .L15
movl $1, %ecx
movq %rbx, %rsi
movq (%rsp), %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L38
call cudaDeviceSynchronize@PLT
leaq 16(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L39
leaq 24(%rsp), %rdi
call cudaEventCreate@PLT
testl %eax, %eax
jne .L40
movl $0, %esi
movq 16(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L41
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $50, %r12d
jmp .L21
.L34:
movl $123374234, %ecx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L35:
movl $61687117, %ecx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L36:
movl $123374234, %ecx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L37:
movl $61687117, %ecx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
movl $98, %ecx
movl %eax, %edx
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC5(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L20:
subl $1, %r12d
je .L42
.L21:
movl $1024, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $60242, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L20
movl $61687117, %edx
movq 8(%rsp), %rsi
movq (%rsp), %rdi
call _Z26__device_stub__Z4hashPcS_iPcS_i
jmp .L20
.L42:
movl $0, %esi
movq 24(%rsp), %rdi
call cudaEventRecord@PLT
testl %eax, %eax
jne .L43
movq 24(%rsp), %rdi
call cudaEventSynchronize@PLT
testl %eax, %eax
jne .L44
movl $0x00000000, 44(%rsp)
leaq 44(%rsp), %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call cudaEventElapsedTime@PLT
testl %eax, %eax
jne .L45
movl $2, %ecx
movl $61687117, %edx
movq 8(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
testl %eax, %eax
jne .L46
movl $0, %eax
.L25:
movzbl (%rbx,%rax,2), %esi
cmpb %sil, 0(%rbp,%rax)
jne .L47
addq $1, %rax
cmpq $61687117, %rax
jne .L25
pxor %xmm0, %xmm0
cvtss2sd 44(%rsp), %xmm0
divsd .LC14(%rip), %xmm0
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbx, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
call cudaDeviceReset@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L48
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L43:
.cfi_restore_state
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC9(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC10(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L45:
movl %eax, %edi
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC12(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movl $177, %ecx
movl %eax, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movl $1, %edi
call exit@PLT
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC16:
.string "_Z4hashPcS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z4hashPcS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC14:
.long 0
.long 1083129856
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* One Way Hash with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements a simple hash from a space of size 2n --> n
*
* The following code makes use of the kernel call hash(char *f, char *h, int n)
* to perform a parallel hash of elements f --> h with corresponding indices 2i --> i
*
* The result is a mapping of the data within f to the data within h
* The output is verified before the program terminates to see that every
* element at index 2i of f is indeed at index i in h
*
* We can see that there is a significant speedup in comparison to the time it takes
* to perform the hash in the serial code.
*
* The output of the performance is displayed in seconds.
* The performance results are to be compared with the performance of hash.c
*
*/
// System includes
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
// We also indicate EVEN_NUM as the vector size since this hash requires even length arrays
#define THREADS_PER_BLOCK 1024
#define EVEN_NUM 123374234
__global__ void hash(char *f, char *h, int n) {
int i = blockIdx.x*blockDim.x+threadIdx.x;
if( i < n ){
h[i] = f[2*i];
}
}
int main(void) {
int two_n = EVEN_NUM, i, r=50;
char *f, *h, *d_f,*d_h;
cudaError_t error;
if ( two_n % 2 ){
printf("NO NO NO!!! Even numbers only please.\n");
exit(EXIT_FAILURE);
}
//printf("Malloc space on CPU (f,h)");
f = (char *)calloc(sizeof(char), two_n);
if( f == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for f.",two_n);
exit(EXIT_FAILURE);
}
h = (char *)calloc(sizeof(char), two_n/2);
if( h == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for h.",two_n/2);
exit(EXIT_FAILURE);
}
/* Identify our streams */
//printf("Malloc space on GPU (d_f,d_h)\n");
error = cudaMalloc((void **)&d_f, sizeof(char) * two_n);
if( error != cudaSuccess ){
fprintf(stderr,"Failed to cudaMalloc %d bytes for d_f.",two_n);
exit(EXIT_FAILURE);
}
error = cudaMalloc((void **)&d_h, sizeof(char) * two_n/2);
if( error != cudaSuccess ){
fprintf(stderr,"Failed to cudaMalloc %d bytes for d_h.",two_n/2);
exit(EXIT_FAILURE);
}
//populate data into array
//printf("Generate vectored data (Size=%d bytes)\n",two_n);
for (i = 0; i < two_n; i++) {
f[i] = (char) ((i % 94) + 33);
}
//send data over the bus
//printf("Send data to GPU\n");
error = cudaMemcpy( d_f, f, two_n, cudaMemcpyHostToDevice);
if (error != cudaSuccess)
{
printf("cudaMemcpy (d_f,f) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/*************************** Setup for testing ************************************/
//printf("Run kernel code \n");
cudaDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
cudaEvent_t start;
error = cudaEventCreate(&start);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
cudaEvent_t stop;
error = cudaEventCreate(&stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = cudaEventRecord(start, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
printf("Running...\n");
//run kernel
for( i = 0; i < r; i++){
hash<<<(two_n/2+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_f,d_h,two_n/2);
}
// Record the stop event
error = cudaEventRecord(stop, NULL);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = cudaEventSynchronize(stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = cudaEventElapsedTime(&msecTotal, start, stop);
if (error != cudaSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", cudaGetErrorString(error));
exit(EXIT_FAILURE);
}
/*******************************************************************************************
****************************** for testing purposes ***************************************/
//send data over the bus
error = cudaMemcpy( h, d_h, sizeof(char)*two_n/2, cudaMemcpyDeviceToHost);
if (error != cudaSuccess)
{
printf("cudaMemcpy (h,d_h) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
//printf("Done.\n");
//validate for correctness
for (i = 0; i < two_n/2; i++) {
if (h[i] != f[2*i]) {
//printf("index %d FAILED!\n", i);
exit(EXIT_FAILURE);
}
}
// Compute and print the performance
float msecPerhash = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerhash/1000.0 );
free(f); free(h);
cudaFree(d_f); cudaFree(d_h);
cudaDeviceReset();
return 0;
} | /**
* One Way Hash with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements a simple hash from a space of size 2n --> n
*
* The following code makes use of the kernel call hash(char *f, char *h, int n)
* to perform a parallel hash of elements f --> h with corresponding indices 2i --> i
*
* The result is a mapping of the data within f to the data within h
* The output is verified before the program terminates to see that every
* element at index 2i of f is indeed at index i in h
*
* We can see that there is a significant speedup in comparison to the time it takes
* to perform the hash in the serial code.
*
* The output of the performance is displayed in seconds.
* The performance results are to be compared with the performance of hash.c
*
*/
// System includes
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
// We also indicate EVEN_NUM as the vector size since this hash requires even length arrays
#define THREADS_PER_BLOCK 1024
#define EVEN_NUM 123374234
__global__ void hash(char *f, char *h, int n) {
int i = blockIdx.x*blockDim.x+threadIdx.x;
if( i < n ){
h[i] = f[2*i];
}
}
int main(void) {
int two_n = EVEN_NUM, i, r=50;
char *f, *h, *d_f,*d_h;
hipError_t error;
if ( two_n % 2 ){
printf("NO NO NO!!! Even numbers only please.\n");
exit(EXIT_FAILURE);
}
//printf("Malloc space on CPU (f,h)");
f = (char *)calloc(sizeof(char), two_n);
if( f == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for f.",two_n);
exit(EXIT_FAILURE);
}
h = (char *)calloc(sizeof(char), two_n/2);
if( h == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for h.",two_n/2);
exit(EXIT_FAILURE);
}
/* Identify our streams */
//printf("Malloc space on GPU (d_f,d_h)\n");
error = hipMalloc((void **)&d_f, sizeof(char) * two_n);
if( error != hipSuccess ){
fprintf(stderr,"Failed to hipMalloc %d bytes for d_f.",two_n);
exit(EXIT_FAILURE);
}
error = hipMalloc((void **)&d_h, sizeof(char) * two_n/2);
if( error != hipSuccess ){
fprintf(stderr,"Failed to hipMalloc %d bytes for d_h.",two_n/2);
exit(EXIT_FAILURE);
}
//populate data into array
//printf("Generate vectored data (Size=%d bytes)\n",two_n);
for (i = 0; i < two_n; i++) {
f[i] = (char) ((i % 94) + 33);
}
//send data over the bus
//printf("Send data to GPU\n");
error = hipMemcpy( d_f, f, two_n, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_f,f) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/*************************** Setup for testing ************************************/
//printf("Run kernel code \n");
hipDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
hipEvent_t start;
error = hipEventCreate(&start);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
hipEvent_t stop;
error = hipEventCreate(&stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = hipEventRecord(start, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
printf("Running...\n");
//run kernel
for( i = 0; i < r; i++){
hash<<<(two_n/2+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_f,d_h,two_n/2);
}
// Record the stop event
error = hipEventRecord(stop, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = hipEventSynchronize(stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = hipEventElapsedTime(&msecTotal, start, stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
/*******************************************************************************************
****************************** for testing purposes ***************************************/
//send data over the bus
error = hipMemcpy( h, d_h, sizeof(char)*two_n/2, hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
printf("hipMemcpy (h,d_h) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
//printf("Done.\n");
//validate for correctness
for (i = 0; i < two_n/2; i++) {
if (h[i] != f[2*i]) {
//printf("index %d FAILED!\n", i);
exit(EXIT_FAILURE);
}
}
// Compute and print the performance
float msecPerhash = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerhash/1000.0 );
free(f); free(h);
hipFree(d_f); hipFree(d_h);
hipDeviceReset();
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* One Way Hash with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements a simple hash from a space of size 2n --> n
*
* The following code makes use of the kernel call hash(char *f, char *h, int n)
* to perform a parallel hash of elements f --> h with corresponding indices 2i --> i
*
* The result is a mapping of the data within f to the data within h
* The output is verified before the program terminates to see that every
* element at index 2i of f is indeed at index i in h
*
* We can see that there is a significant speedup in comparison to the time it takes
* to perform the hash in the serial code.
*
* The output of the performance is displayed in seconds.
* The performance results are to be compared with the performance of hash.c
*
*/
// System includes
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
// We also indicate EVEN_NUM as the vector size since this hash requires even length arrays
#define THREADS_PER_BLOCK 1024
#define EVEN_NUM 123374234
__global__ void hash(char *f, char *h, int n) {
int i = blockIdx.x*blockDim.x+threadIdx.x;
if( i < n ){
h[i] = f[2*i];
}
}
int main(void) {
int two_n = EVEN_NUM, i, r=50;
char *f, *h, *d_f,*d_h;
hipError_t error;
if ( two_n % 2 ){
printf("NO NO NO!!! Even numbers only please.\n");
exit(EXIT_FAILURE);
}
//printf("Malloc space on CPU (f,h)");
f = (char *)calloc(sizeof(char), two_n);
if( f == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for f.",two_n);
exit(EXIT_FAILURE);
}
h = (char *)calloc(sizeof(char), two_n/2);
if( h == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for h.",two_n/2);
exit(EXIT_FAILURE);
}
/* Identify our streams */
//printf("Malloc space on GPU (d_f,d_h)\n");
error = hipMalloc((void **)&d_f, sizeof(char) * two_n);
if( error != hipSuccess ){
fprintf(stderr,"Failed to hipMalloc %d bytes for d_f.",two_n);
exit(EXIT_FAILURE);
}
error = hipMalloc((void **)&d_h, sizeof(char) * two_n/2);
if( error != hipSuccess ){
fprintf(stderr,"Failed to hipMalloc %d bytes for d_h.",two_n/2);
exit(EXIT_FAILURE);
}
//populate data into array
//printf("Generate vectored data (Size=%d bytes)\n",two_n);
for (i = 0; i < two_n; i++) {
f[i] = (char) ((i % 94) + 33);
}
//send data over the bus
//printf("Send data to GPU\n");
error = hipMemcpy( d_f, f, two_n, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_f,f) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/*************************** Setup for testing ************************************/
//printf("Run kernel code \n");
hipDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
hipEvent_t start;
error = hipEventCreate(&start);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
hipEvent_t stop;
error = hipEventCreate(&stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = hipEventRecord(start, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
printf("Running...\n");
//run kernel
for( i = 0; i < r; i++){
hash<<<(two_n/2+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_f,d_h,two_n/2);
}
// Record the stop event
error = hipEventRecord(stop, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = hipEventSynchronize(stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = hipEventElapsedTime(&msecTotal, start, stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
/*******************************************************************************************
****************************** for testing purposes ***************************************/
//send data over the bus
error = hipMemcpy( h, d_h, sizeof(char)*two_n/2, hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
printf("hipMemcpy (h,d_h) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
//printf("Done.\n");
//validate for correctness
for (i = 0; i < two_n/2; i++) {
if (h[i] != f[2*i]) {
//printf("index %d FAILED!\n", i);
exit(EXIT_FAILURE);
}
}
// Compute and print the performance
float msecPerhash = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerhash/1000.0 );
free(f); free(h);
hipFree(d_f); hipFree(d_h);
hipDeviceReset();
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4hashPcS_i
.globl _Z4hashPcS_i
.p2align 8
.type _Z4hashPcS_i,@function
_Z4hashPcS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v1
global_load_u8 v2, v[2:3], off
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4hashPcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4hashPcS_i, .Lfunc_end0-_Z4hashPcS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4hashPcS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4hashPcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* One Way Hash with CUDA (Fall 2016):
*
* Members:
* Emanuelle Crespi, Tolga Keskinoglu
*
* This test implements a simple hash from a space of size 2n --> n
*
* The following code makes use of the kernel call hash(char *f, char *h, int n)
* to perform a parallel hash of elements f --> h with corresponding indices 2i --> i
*
* The result is a mapping of the data within f to the data within h
* The output is verified before the program terminates to see that every
* element at index 2i of f is indeed at index i in h
*
* We can see that there is a significant speedup in comparison to the time it takes
* to perform the hash in the serial code.
*
* The output of the performance is displayed in seconds.
* The performance results are to be compared with the performance of hash.c
*
*/
// System includes
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <math.h>
#include <time.h>
// Jetson TK1 has device capability 1.x allowing 1024 threads/block
// We also indicate EVEN_NUM as the vector size since this hash requires even length arrays
#define THREADS_PER_BLOCK 1024
#define EVEN_NUM 123374234
__global__ void hash(char *f, char *h, int n) {
int i = blockIdx.x*blockDim.x+threadIdx.x;
if( i < n ){
h[i] = f[2*i];
}
}
int main(void) {
int two_n = EVEN_NUM, i, r=50;
char *f, *h, *d_f,*d_h;
hipError_t error;
if ( two_n % 2 ){
printf("NO NO NO!!! Even numbers only please.\n");
exit(EXIT_FAILURE);
}
//printf("Malloc space on CPU (f,h)");
f = (char *)calloc(sizeof(char), two_n);
if( f == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for f.",two_n);
exit(EXIT_FAILURE);
}
h = (char *)calloc(sizeof(char), two_n/2);
if( h == NULL ){
fprintf(stderr,"Failed to allocate %d bytes for h.",two_n/2);
exit(EXIT_FAILURE);
}
/* Identify our streams */
//printf("Malloc space on GPU (d_f,d_h)\n");
error = hipMalloc((void **)&d_f, sizeof(char) * two_n);
if( error != hipSuccess ){
fprintf(stderr,"Failed to hipMalloc %d bytes for d_f.",two_n);
exit(EXIT_FAILURE);
}
error = hipMalloc((void **)&d_h, sizeof(char) * two_n/2);
if( error != hipSuccess ){
fprintf(stderr,"Failed to hipMalloc %d bytes for d_h.",two_n/2);
exit(EXIT_FAILURE);
}
//populate data into array
//printf("Generate vectored data (Size=%d bytes)\n",two_n);
for (i = 0; i < two_n; i++) {
f[i] = (char) ((i % 94) + 33);
}
//send data over the bus
//printf("Send data to GPU\n");
error = hipMemcpy( d_f, f, two_n, hipMemcpyHostToDevice);
if (error != hipSuccess)
{
printf("hipMemcpy (d_f,f) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
/*************************** Setup for testing ************************************/
//printf("Run kernel code \n");
hipDeviceSynchronize();
// Allocate CUDA events that we'll use for timing
hipEvent_t start;
error = hipEventCreate(&start);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
hipEvent_t stop;
error = hipEventCreate(&stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to create stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Record the start event
error = hipEventRecord(start, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record start event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
printf("Running...\n");
//run kernel
for( i = 0; i < r; i++){
hash<<<(two_n/2+THREADS_PER_BLOCK-1)/THREADS_PER_BLOCK,THREADS_PER_BLOCK>>>(d_f,d_h,two_n/2);
}
// Record the stop event
error = hipEventRecord(stop, NULL);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to record stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
// Wait for the stop event to complete
error = hipEventSynchronize(stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to synchronize on the stop event (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
float msecTotal = 0.0f;
error = hipEventElapsedTime(&msecTotal, start, stop);
if (error != hipSuccess)
{
fprintf(stderr, "Failed to get time elapsed between events (error code %s)!\n", hipGetErrorString(error));
exit(EXIT_FAILURE);
}
/*******************************************************************************************
****************************** for testing purposes ***************************************/
//send data over the bus
error = hipMemcpy( h, d_h, sizeof(char)*two_n/2, hipMemcpyDeviceToHost);
if (error != hipSuccess)
{
printf("hipMemcpy (h,d_h) returned error code %d, line(%d)\n", error, __LINE__);
exit(EXIT_FAILURE);
}
//printf("Done.\n");
//validate for correctness
for (i = 0; i < two_n/2; i++) {
if (h[i] != f[2*i]) {
//printf("index %d FAILED!\n", i);
exit(EXIT_FAILURE);
}
}
// Compute and print the performance
float msecPerhash = msecTotal / 1;
printf( "Performance= %.06f sec\n", msecPerhash/1000.0 );
free(f); free(h);
hipFree(d_f); hipFree(d_h);
hipDeviceReset();
return 0;
} | .text
.file "hash.hip"
.globl _Z19__device_stub__hashPcS_i # -- Begin function _Z19__device_stub__hashPcS_i
.p2align 4, 0x90
.type _Z19__device_stub__hashPcS_i,@function
_Z19__device_stub__hashPcS_i: # @_Z19__device_stub__hashPcS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z4hashPcS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z19__device_stub__hashPcS_i, .Lfunc_end0-_Z19__device_stub__hashPcS_i
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function main
.LCPI1_0:
.quad 0x408f400000000000 # double 1000
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $136, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $1, %edi
movl $123374234, %esi # imm = 0x75A8A9A
callq calloc
testq %rax, %rax
je .LBB1_23
# %bb.1:
movq %rax, %rbx
movl $1, %edi
movl $61687117, %esi # imm = 0x3AD454D
callq calloc
testq %rax, %rax
je .LBB1_24
# %bb.2:
movq %rax, %r14
leaq 24(%rsp), %rdi
movl $123374234, %esi # imm = 0x75A8A9A
callq hipMalloc
testl %eax, %eax
jne .LBB1_25
# %bb.3:
leaq 16(%rsp), %rdi
movl $61687117, %esi # imm = 0x3AD454D
callq hipMalloc
testl %eax, %eax
jne .LBB1_27
# %bb.4: # %.preheader79.preheader
movb $33, %al
xorl %ecx, %ecx
movl $2924233053, %edx # imm = 0xAE4C415D
xorl %esi, %esi
.p2align 4, 0x90
.LBB1_5: # %.preheader79
# =>This Inner Loop Header: Depth=1
movl %ecx, %edi
imulq %rdx, %rdi
shrq $38, %rdi
imull $94, %edi, %edi
movl %eax, %r8d
subb %dil, %r8b
movb %r8b, (%rbx,%rsi)
incq %rsi
incb %al
incl %ecx
cmpq $123374234, %rsi # imm = 0x75A8A9A
jne .LBB1_5
# %bb.6:
movq 24(%rsp), %rdi
movl $123374234, %edx # imm = 0x75A8A9A
movq %rbx, %rsi
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_30
# %bb.7:
callq hipDeviceSynchronize
leaq 40(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_31
# %bb.8:
leaq 8(%rsp), %rdi
callq hipEventCreate
testl %eax, %eax
jne .LBB1_32
# %bb.9:
movq 40(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_33
# %bb.10:
movabsq $4294968320, %r15 # imm = 0x100000400
movl $.Lstr, %edi
callq puts@PLT
movl $50, %ebp
leaq 59218(%r15), %r12
leaq 48(%rsp), %r13
jmp .LBB1_12
.p2align 4, 0x90
.LBB1_11: # in Loop: Header=BB1_12 Depth=1
decl %ebp
je .LBB1_14
.LBB1_12: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_11
# %bb.13: # in Loop: Header=BB1_12 Depth=1
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq %rax, 128(%rsp)
movq %rcx, 120(%rsp)
movl $61687117, 36(%rsp) # imm = 0x3AD454D
leaq 128(%rsp), %rax
movq %rax, 48(%rsp)
leaq 120(%rsp), %rax
movq %rax, 56(%rsp)
leaq 36(%rsp), %rax
movq %rax, 64(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
movl $_Z4hashPcS_i, %edi
movq %r13, %r9
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
jmp .LBB1_11
.LBB1_14:
movq 8(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
testl %eax, %eax
jne .LBB1_34
# %bb.15:
movq 8(%rsp), %rdi
callq hipEventSynchronize
testl %eax, %eax
jne .LBB1_35
# %bb.16:
movl $0, 48(%rsp)
movq 40(%rsp), %rsi
movq 8(%rsp), %rdx
leaq 48(%rsp), %rdi
callq hipEventElapsedTime
testl %eax, %eax
jne .LBB1_36
# %bb.17:
movq 16(%rsp), %rsi
movl $61687117, %edx # imm = 0x3AD454D
movq %r14, %rdi
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_38
# %bb.18: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_19: # %.preheader
# =>This Inner Loop Header: Depth=1
movzbl (%r14,%rax), %ecx
cmpb (%rbx,%rax,2), %cl
jne .LBB1_22
# %bb.20: # in Loop: Header=BB1_19 Depth=1
incq %rax
cmpq $61687117, %rax # imm = 0x3AD454D
jne .LBB1_19
# %bb.21:
movss 48(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
divsd .LCPI1_0(%rip), %xmm0
movl $.L.str.14, %edi
movb $1, %al
callq printf
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
callq hipDeviceReset
xorl %eax, %eax
addq $136, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_22:
.cfi_def_cfa_offset 192
movl $1, %edi
callq exit
.LBB1_23:
movq stderr(%rip), %rdi
movl $.L.str.1, %esi
jmp .LBB1_26
.LBB1_24:
movq stderr(%rip), %rdi
movl $.L.str.2, %esi
jmp .LBB1_28
.LBB1_25:
movq stderr(%rip), %rdi
movl $.L.str.3, %esi
.LBB1_26:
movl $123374234, %edx # imm = 0x75A8A9A
jmp .LBB1_29
.LBB1_27:
movq stderr(%rip), %rdi
movl $.L.str.4, %esi
.LBB1_28:
movl $61687117, %edx # imm = 0x3AD454D
.LBB1_29:
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_30:
movl $.L.str.5, %edi
movl %eax, %esi
movl $100, %edx
jmp .LBB1_39
.LBB1_31:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB1_37
.LBB1_32:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.7, %esi
jmp .LBB1_37
.LBB1_33:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB1_37
.LBB1_34:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.10, %esi
jmp .LBB1_37
.LBB1_35:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.11, %esi
jmp .LBB1_37
.LBB1_36:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.12, %esi
.LBB1_37:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_38:
movl $.L.str.13, %edi
movl %eax, %esi
movl $179, %edx
.LBB1_39:
xorl %eax, %eax
callq printf
movl $1, %edi
callq exit
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z4hashPcS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z4hashPcS_i,@object # @_Z4hashPcS_i
.section .rodata,"a",@progbits
.globl _Z4hashPcS_i
.p2align 3, 0x0
_Z4hashPcS_i:
.quad _Z19__device_stub__hashPcS_i
.size _Z4hashPcS_i, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "Failed to allocate %d bytes for f."
.size .L.str.1, 35
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Failed to allocate %d bytes for h."
.size .L.str.2, 35
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to hipMalloc %d bytes for d_f."
.size .L.str.3, 38
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to hipMalloc %d bytes for d_h."
.size .L.str.4, 38
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "hipMemcpy (d_f,f) returned error code %d, line(%d)\n"
.size .L.str.5, 52
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to create start event (error code %s)!\n"
.size .L.str.6, 47
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Failed to create stop event (error code %s)!\n"
.size .L.str.7, 46
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to record start event (error code %s)!\n"
.size .L.str.8, 47
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Failed to record stop event (error code %s)!\n"
.size .L.str.10, 46
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "Failed to synchronize on the stop event (error code %s)!\n"
.size .L.str.11, 58
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "Failed to get time elapsed between events (error code %s)!\n"
.size .L.str.12, 60
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "hipMemcpy (h,d_h) returned error code %d, line(%d)\n"
.size .L.str.13, 52
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "Performance= %.06f sec\n"
.size .L.str.14, 24
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z4hashPcS_i"
.size .L__unnamed_1, 13
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Running..."
.size .Lstr, 11
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z19__device_stub__hashPcS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z4hashPcS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z4hashPcS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.SHL.U32 R3, R0, 0x2, RZ ; /* 0x0000000200037824 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc80000000a00 */
/*0080*/ IADD3 R2, P0, R3, c[0x0][0x160], RZ ; /* 0x0000580003027a10 */
/* 0x000fc80007f1e0ff */
/*0090*/ LEA.HI.X.SX32 R3, R3, c[0x0][0x164], 0x1, P0 ; /* 0x0000590003037a11 */
/* 0x000fcc00000f0eff */
/*00a0*/ LDG.E.U8 R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea2000c1e1100 */
/*00b0*/ IADD3 R4, P0, R0, c[0x0][0x168], RZ ; /* 0x00005a0000047a10 */
/* 0x000fc80007f1e0ff */
/*00c0*/ LEA.HI.X.SX32 R5, R0, c[0x0][0x16c], 0x1, P0 ; /* 0x00005b0000057a11 */
/* 0x000fca00000f0eff */
/*00d0*/ STG.E.U8 [R4.64], R3 ; /* 0x0000000304007986 */
/* 0x004fe2000c101104 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z4hashPcS_i
.globl _Z4hashPcS_i
.p2align 8
.type _Z4hashPcS_i,@function
_Z4hashPcS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_load_b128 s[0:3], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 1, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v3, 31, v0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v1
global_load_u8 v2, v[2:3], off
v_ashrrev_i32_e32 v3, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v3, vcc_lo
s_waitcnt vmcnt(0)
global_store_b8 v[0:1], v2, off
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z4hashPcS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z4hashPcS_i, .Lfunc_end0-_Z4hashPcS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z4hashPcS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z4hashPcS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
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