system stringclasses 7
values | input stringlengths 10 94.5k | output stringlengths 14 55.5k |
|---|---|---|
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00062399_00000000-6_randTest.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2275:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2275:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z6G_randP17curandStateXORWOWi
.type _Z6G_randP17curandStateXORWOWi, @function
_Z6G_randP17curandStateXORWOWi:
.LFB2271:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2271:
.size _Z6G_randP17curandStateXORWOWi, .-_Z6G_randP17curandStateXORWOWi
.globl _Z45__device_stub__Z7G_srandP17curandStateXORWOWmP17curandStateXORWOWm
.type _Z45__device_stub__Z7G_srandP17curandStateXORWOWmP17curandStateXORWOWm, @function
_Z45__device_stub__Z7G_srandP17curandStateXORWOWmP17curandStateXORWOWm:
.LFB2297:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z7G_srandP17curandStateXORWOWm(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2297:
.size _Z45__device_stub__Z7G_srandP17curandStateXORWOWmP17curandStateXORWOWm, .-_Z45__device_stub__Z7G_srandP17curandStateXORWOWmP17curandStateXORWOWm
.globl _Z7G_srandP17curandStateXORWOWm
.type _Z7G_srandP17curandStateXORWOWm, @function
_Z7G_srandP17curandStateXORWOWm:
.LFB2298:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z7G_srandP17curandStateXORWOWmP17curandStateXORWOWm
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2298:
.size _Z7G_srandP17curandStateXORWOWm, .-_Z7G_srandP17curandStateXORWOWm
.globl _Z50__device_stub__Z10G_testRandPdP17curandStateXORWOWPdP17curandStateXORWOW
.type _Z50__device_stub__Z10G_testRandPdP17curandStateXORWOWPdP17curandStateXORWOW, @function
_Z50__device_stub__Z10G_testRandPdP17curandStateXORWOWPdP17curandStateXORWOW:
.LFB2299:
.cfi_startproc
endbr64
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 8(%rsp)
movq %rsi, (%rsp)
movq %fs:40, %rax
movq %rax, 104(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movq %rsp, %rax
movq %rax, 88(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L17
.L13:
movq 104(%rsp), %rax
subq %fs:40, %rax
jne .L18
addq $120, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 136
pushq 24(%rsp)
.cfi_def_cfa_offset 144
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z10G_testRandPdP17curandStateXORWOW(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 128
jmp .L13
.L18:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2299:
.size _Z50__device_stub__Z10G_testRandPdP17curandStateXORWOWPdP17curandStateXORWOW, .-_Z50__device_stub__Z10G_testRandPdP17curandStateXORWOWPdP17curandStateXORWOW
.globl _Z10G_testRandPdP17curandStateXORWOW
.type _Z10G_testRandPdP17curandStateXORWOW, @function
_Z10G_testRandPdP17curandStateXORWOW:
.LFB2300:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z10G_testRandPdP17curandStateXORWOWPdP17curandStateXORWOW
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2300:
.size _Z10G_testRandPdP17curandStateXORWOW, .-_Z10G_testRandPdP17curandStateXORWOW
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result: ----------------\n"
.LC1:
.string "%lf\t"
.LC2:
.string "\n"
.text
.globl main
.type main, @function
main:
.LFB2272:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $192, %esi
call cudaMalloc@PLT
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L30
.L22:
leaq 8(%rsp), %rdi
movl $128, %esi
call cudaMalloc@PLT
movl $128, %edi
call malloc@PLT
movq %rax, %r14
movl $4, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $4, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
movl $1, %ecx
movq 16(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L31
.L23:
movl $2, %ecx
movl $128, %edx
movq 8(%rsp), %rsi
movq %r14, %rdi
call cudaMemcpy@PLT
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 32(%r14), %rbp
movl $0, %r13d
leaq .LC1(%rip), %r12
leaq .LC2(%rip), %r15
.L24:
leaq -32(%rbp), %rbx
.L25:
movsd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $8, %rbx
cmpq %rbp, %rbx
jne .L25
movq %r15, %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $4, %r13d
addq $32, %rbp
cmpl $16, %r13d
jne .L24
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq %r14, %rdi
call free@PLT
movq 40(%rsp), %rax
subq %fs:40, %rax
jne .L32
movl $0, %eax
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L30:
.cfi_restore_state
movl $0, %edi
call time@PLT
movl %eax, %esi
movq (%rsp), %rdi
call _Z45__device_stub__Z7G_srandP17curandStateXORWOWmP17curandStateXORWOWm
jmp .L22
.L31:
movq (%rsp), %rsi
movq 8(%rsp), %rdi
call _Z50__device_stub__Z10G_testRandPdP17curandStateXORWOWPdP17curandStateXORWOW
jmp .L23
.L32:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2272:
.size main, .-main
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "_Z10G_testRandPdP17curandStateXORWOW"
.align 8
.LC4:
.string "_Z7G_srandP17curandStateXORWOWm"
.section .rodata.str1.1
.LC5:
.string "precalc_xorwow_matrix"
.LC6:
.string "precalc_xorwow_offset_matrix"
.LC7:
.string "mrg32k3aM1"
.LC8:
.string "mrg32k3aM2"
.LC9:
.string "mrg32k3aM1SubSeq"
.LC10:
.string "mrg32k3aM2SubSeq"
.LC11:
.string "mrg32k3aM1Seq"
.LC12:
.string "mrg32k3aM2Seq"
.LC13:
.string "__cr_lgamma_table"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2302:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z10G_testRandPdP17curandStateXORWOW(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC4(%rip), %rdx
movq %rdx, %rcx
leaq _Z7G_srandP17curandStateXORWOWm(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC5(%rip), %rdx
movq %rdx, %rcx
leaq _ZL21precalc_xorwow_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $102400, %r9d
movl $0, %r8d
leaq .LC6(%rip), %rdx
movq %rdx, %rcx
leaq _ZL28precalc_xorwow_offset_matrix(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC7(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM1(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL10mrg32k3aM2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM1SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2016, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL16mrg32k3aM2SubSeq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC11(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM1Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
movl $2304, %r9d
movl $0, %r8d
leaq .LC12(%rip), %rdx
movq %rdx, %rcx
leaq _ZL13mrg32k3aM2Seq(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $72, %r9d
movl $0, %r8d
leaq .LC13(%rip), %rdx
movq %rdx, %rcx
leaq _ZL17__cr_lgamma_table(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2302:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL17__cr_lgamma_table
.comm _ZL17__cr_lgamma_table,72,32
.local _ZL13mrg32k3aM2Seq
.comm _ZL13mrg32k3aM2Seq,2304,32
.local _ZL13mrg32k3aM1Seq
.comm _ZL13mrg32k3aM1Seq,2304,32
.local _ZL16mrg32k3aM2SubSeq
.comm _ZL16mrg32k3aM2SubSeq,2016,32
.local _ZL16mrg32k3aM1SubSeq
.comm _ZL16mrg32k3aM1SubSeq,2016,32
.local _ZL10mrg32k3aM2
.comm _ZL10mrg32k3aM2,2304,32
.local _ZL10mrg32k3aM1
.comm _ZL10mrg32k3aM1,2304,32
.local _ZL28precalc_xorwow_offset_matrix
.comm _ZL28precalc_xorwow_offset_matrix,102400,32
.local _ZL21precalc_xorwow_matrix
.comm _ZL21precalc_xorwow_matrix,102400,32
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "randTest.hip"
.globl _Z22__device_stub__G_srandP12hiprandStatem # -- Begin function _Z22__device_stub__G_srandP12hiprandStatem
.p2align 4, 0x90
.type _Z22__device_stub__G_srandP12hiprandStatem,@function
_Z22__device_stub__G_srandP12hiprandStatem: # @_Z22__device_stub__G_srandP12hiprandStatem
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z7G_srandP12hiprandStatem, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end0:
.size _Z22__device_stub__G_srandP12hiprandStatem, .Lfunc_end0-_Z22__device_stub__G_srandP12hiprandStatem
.cfi_endproc
# -- End function
.globl _Z25__device_stub__G_testRandPdP12hiprandState # -- Begin function _Z25__device_stub__G_testRandPdP12hiprandState
.p2align 4, 0x90
.type _Z25__device_stub__G_testRandPdP12hiprandState,@function
_Z25__device_stub__G_testRandPdP12hiprandState: # @_Z25__device_stub__G_testRandPdP12hiprandState
.cfi_startproc
# %bb.0:
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 56(%rsp)
movq %rsi, 48(%rsp)
leaq 56(%rsp), %rax
movq %rax, 64(%rsp)
leaq 48(%rsp), %rax
movq %rax, 72(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 64(%rsp), %r9
movl $_Z10G_testRandPdP12hiprandState, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $104, %rsp
.cfi_adjust_cfa_offset -104
retq
.Lfunc_end1:
.size _Z25__device_stub__G_testRandPdP12hiprandState, .Lfunc_end1-_Z25__device_stub__G_testRandPdP12hiprandState
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
subq $104, %rsp
.cfi_def_cfa_offset 144
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movabsq $4294967300, %r14 # imm = 0x100000004
leaq 8(%rsp), %rdi
movl $192, %esi
callq hipMalloc
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_2
# %bb.1:
movq 8(%rsp), %rbx
xorl %edi, %edi
callq time
movl %eax, %eax
movq %rbx, 72(%rsp)
movq %rax, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z7G_srandP12hiprandStatem, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_2:
movq %rsp, %rdi
movl $128, %esi
callq hipMalloc
movl $128, %edi
callq malloc
movq %rax, %rbx
movq %r14, %rdi
movl $1, %esi
movq %r14, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_4
# %bb.3:
movq (%rsp), %rax
movq 8(%rsp), %rcx
movq %rax, 72(%rsp)
movq %rcx, 64(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z10G_testRandPdP12hiprandState, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_4:
movq (%rsp), %rsi
movl $128, %edx
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movl $.Lstr, %edi
callq puts@PLT
xorl %r14d, %r14d
movq %rbx, %r15
.p2align 4, 0x90
.LBB2_5: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_6 Depth 2
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB2_6: # Parent Loop BB2_5 Depth=1
# => This Inner Loop Header: Depth=2
movsd (%r15,%r12,8), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.1, %edi
movb $1, %al
callq printf
incq %r12
cmpq $4, %r12
jne .LBB2_6
# %bb.7: # in Loop: Header=BB2_5 Depth=1
movl $10, %edi
callq putchar@PLT
incq %r14
addq $32, %r15
cmpq $4, %r14
jne .LBB2_5
# %bb.8:
movq 8(%rsp), %rdi
callq hipFree
movq (%rsp), %rdi
callq hipFree
movq %rbx, %rdi
callq free
xorl %eax, %eax
addq $104, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z7G_srandP12hiprandStatem, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z10G_testRandPdP12hiprandState, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z7G_srandP12hiprandStatem,@object # @_Z7G_srandP12hiprandStatem
.section .rodata,"a",@progbits
.globl _Z7G_srandP12hiprandStatem
.p2align 3, 0x0
_Z7G_srandP12hiprandStatem:
.quad _Z22__device_stub__G_srandP12hiprandStatem
.size _Z7G_srandP12hiprandStatem, 8
.type _Z10G_testRandPdP12hiprandState,@object # @_Z10G_testRandPdP12hiprandState
.globl _Z10G_testRandPdP12hiprandState
.p2align 3, 0x0
_Z10G_testRandPdP12hiprandState:
.quad _Z25__device_stub__G_testRandPdP12hiprandState
.size _Z10G_testRandPdP12hiprandState, 8
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "%lf\t"
.size .L.str.1, 5
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z7G_srandP12hiprandStatem"
.size .L__unnamed_1, 27
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z10G_testRandPdP12hiprandState"
.size .L__unnamed_2, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Result: ----------------"
.size .Lstr, 25
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z22__device_stub__G_srandP12hiprandStatem
.addrsig_sym _Z25__device_stub__G_testRandPdP12hiprandState
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z7G_srandP12hiprandStatem
.addrsig_sym _Z10G_testRandPdP12hiprandState
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
#define max(a, b) a > b ? a : b
#define min(a, b) a < b ? a : b
struct Edge{
long long int x;
};
///*
//*/
__global__ void leaf_pointer_jumping(int* parent, int* vertex_state, int n){
int bid = blockIdx.x;
int id = bid*blockDim.x + threadIdx.x;
int parent_id, grandparent_id;
if(id < n)
if(vertex_state[id] == 1){
parent_id = parent[id];
grandparent_id = parent[parent_id];
parent[id] = grandparent_id;
}
return;
} | code for sm_80
Function : _Z20leaf_pointer_jumpingPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*00d0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*00e0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*00f0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0100*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x004fcc00078e0205 */
/*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0120*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
#define max(a, b) a > b ? a : b
#define min(a, b) a < b ? a : b
struct Edge{
long long int x;
};
///*
//*/
__global__ void leaf_pointer_jumping(int* parent, int* vertex_state, int n){
int bid = blockIdx.x;
int id = bid*blockDim.x + threadIdx.x;
int parent_id, grandparent_id;
if(id < n)
if(vertex_state[id] == 1){
parent_id = parent[id];
grandparent_id = parent[parent_id];
parent[id] = grandparent_id;
}
return;
} | .file "tmpxft_000fc866_00000000-6_leaf_pointer_jumping.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i
.type _Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i, @function
_Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20leaf_pointer_jumpingPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i, .-_Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i
.globl _Z20leaf_pointer_jumpingPiS_i
.type _Z20leaf_pointer_jumpingPiS_i, @function
_Z20leaf_pointer_jumpingPiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20leaf_pointer_jumpingPiS_i, .-_Z20leaf_pointer_jumpingPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20leaf_pointer_jumpingPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20leaf_pointer_jumpingPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
#define max(a, b) a > b ? a : b
#define min(a, b) a < b ? a : b
struct Edge{
long long int x;
};
///*
//*/
__global__ void leaf_pointer_jumping(int* parent, int* vertex_state, int n){
int bid = blockIdx.x;
int id = bid*blockDim.x + threadIdx.x;
int parent_id, grandparent_id;
if(id < n)
if(vertex_state[id] == 1){
parent_id = parent[id];
grandparent_id = parent[parent_id];
parent[id] = grandparent_id;
}
return;
} | #include <hip/hip_runtime.h>
#include "includes.h"
#define max(a, b) a > b ? a : b
#define min(a, b) a < b ? a : b
struct Edge{
long long int x;
};
///*
//*/
__global__ void leaf_pointer_jumping(int* parent, int* vertex_state, int n){
int bid = blockIdx.x;
int id = bid*blockDim.x + threadIdx.x;
int parent_id, grandparent_id;
if(id < n)
if(vertex_state[id] == 1){
parent_id = parent[id];
grandparent_id = parent[parent_id];
parent[id] = grandparent_id;
}
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define max(a, b) a > b ? a : b
#define min(a, b) a < b ? a : b
struct Edge{
long long int x;
};
///*
//*/
__global__ void leaf_pointer_jumping(int* parent, int* vertex_state, int n){
int bid = blockIdx.x;
int id = bid*blockDim.x + threadIdx.x;
int parent_id, grandparent_id;
if(id < n)
if(vertex_state[id] == 1){
parent_id = parent[id];
grandparent_id = parent[parent_id];
parent[id] = grandparent_id;
}
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20leaf_pointer_jumpingPiS_i
.globl _Z20leaf_pointer_jumpingPiS_i
.p2align 8
.type _Z20leaf_pointer_jumpingPiS_i,@function
_Z20leaf_pointer_jumpingPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20leaf_pointer_jumpingPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20leaf_pointer_jumpingPiS_i, .Lfunc_end0-_Z20leaf_pointer_jumpingPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20leaf_pointer_jumpingPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20leaf_pointer_jumpingPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
#define max(a, b) a > b ? a : b
#define min(a, b) a < b ? a : b
struct Edge{
long long int x;
};
///*
//*/
__global__ void leaf_pointer_jumping(int* parent, int* vertex_state, int n){
int bid = blockIdx.x;
int id = bid*blockDim.x + threadIdx.x;
int parent_id, grandparent_id;
if(id < n)
if(vertex_state[id] == 1){
parent_id = parent[id];
grandparent_id = parent[parent_id];
parent[id] = grandparent_id;
}
return;
} | .text
.file "leaf_pointer_jumping.hip"
.globl _Z35__device_stub__leaf_pointer_jumpingPiS_i # -- Begin function _Z35__device_stub__leaf_pointer_jumpingPiS_i
.p2align 4, 0x90
.type _Z35__device_stub__leaf_pointer_jumpingPiS_i,@function
_Z35__device_stub__leaf_pointer_jumpingPiS_i: # @_Z35__device_stub__leaf_pointer_jumpingPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20leaf_pointer_jumpingPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__leaf_pointer_jumpingPiS_i, .Lfunc_end0-_Z35__device_stub__leaf_pointer_jumpingPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20leaf_pointer_jumpingPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20leaf_pointer_jumpingPiS_i,@object # @_Z20leaf_pointer_jumpingPiS_i
.section .rodata,"a",@progbits
.globl _Z20leaf_pointer_jumpingPiS_i
.p2align 3, 0x0
_Z20leaf_pointer_jumpingPiS_i:
.quad _Z35__device_stub__leaf_pointer_jumpingPiS_i
.size _Z20leaf_pointer_jumpingPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20leaf_pointer_jumpingPiS_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__leaf_pointer_jumpingPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20leaf_pointer_jumpingPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z20leaf_pointer_jumpingPiS_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0020*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0030*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0040*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x170], PT ; /* 0x00005c0000007a0c */
/* 0x000fda0003f06270 */
/*0050*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0060*/ IMAD.MOV.U32 R5, RZ, RZ, 0x4 ; /* 0x00000004ff057424 */
/* 0x000fe200078e00ff */
/*0070*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0080*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0090*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea4000c1e1900 */
/*00a0*/ ISETP.NE.AND P0, PT, R2, 0x1, PT ; /* 0x000000010200780c */
/* 0x004fda0003f05270 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fe40000011400 */
/*00d0*/ LEA R2, P0, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000027a11 */
/* 0x000fc800078010ff */
/*00e0*/ LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P0 ; /* 0x0000590000037a11 */
/* 0x000fca00000f1403 */
/*00f0*/ LDG.E R4, [R2.64] ; /* 0x0000000402047981 */
/* 0x000ea4000c1e1900 */
/*0100*/ IMAD.WIDE R4, R4, R5, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x004fcc00078e0205 */
/*0110*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea8000c1e1900 */
/*0120*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x004fe2000c101904 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ BRA 0x140; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0180*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0190*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z20leaf_pointer_jumpingPiS_i
.globl _Z20leaf_pointer_jumpingPiS_i
.p2align 8
.type _Z20leaf_pointer_jumpingPiS_i,@function
_Z20leaf_pointer_jumpingPiS_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x24
s_load_b32 s3, s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_3
s_load_b64 s[2:3], s[0:1], 0x8
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_cmp_eq_u32_e32 vcc_lo, 1, v2
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_3
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_ashrrev_i32_e32 v3, 31, v2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[2:3], 2, v[2:3]
v_add_co_u32 v2, vcc_lo, s0, v2
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z20leaf_pointer_jumpingPiS_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 280
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 4
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z20leaf_pointer_jumpingPiS_i, .Lfunc_end0-_Z20leaf_pointer_jumpingPiS_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 24
.size: 4
.value_kind: hidden_block_count_x
- .offset: 28
.size: 4
.value_kind: hidden_block_count_y
- .offset: 32
.size: 4
.value_kind: hidden_block_count_z
- .offset: 36
.size: 2
.value_kind: hidden_group_size_x
- .offset: 38
.size: 2
.value_kind: hidden_group_size_y
- .offset: 40
.size: 2
.value_kind: hidden_group_size_z
- .offset: 42
.size: 2
.value_kind: hidden_remainder_x
- .offset: 44
.size: 2
.value_kind: hidden_remainder_y
- .offset: 46
.size: 2
.value_kind: hidden_remainder_z
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 88
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 280
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z20leaf_pointer_jumpingPiS_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z20leaf_pointer_jumpingPiS_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 4
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000fc866_00000000-6_leaf_pointer_jumping.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i
.type _Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i, @function
_Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z20leaf_pointer_jumpingPiS_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i, .-_Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i
.globl _Z20leaf_pointer_jumpingPiS_i
.type _Z20leaf_pointer_jumpingPiS_i, @function
_Z20leaf_pointer_jumpingPiS_i:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z43__device_stub__Z20leaf_pointer_jumpingPiS_iPiS_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z20leaf_pointer_jumpingPiS_i, .-_Z20leaf_pointer_jumpingPiS_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z20leaf_pointer_jumpingPiS_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z20leaf_pointer_jumpingPiS_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "leaf_pointer_jumping.hip"
.globl _Z35__device_stub__leaf_pointer_jumpingPiS_i # -- Begin function _Z35__device_stub__leaf_pointer_jumpingPiS_i
.p2align 4, 0x90
.type _Z35__device_stub__leaf_pointer_jumpingPiS_i,@function
_Z35__device_stub__leaf_pointer_jumpingPiS_i: # @_Z35__device_stub__leaf_pointer_jumpingPiS_i
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z20leaf_pointer_jumpingPiS_i, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z35__device_stub__leaf_pointer_jumpingPiS_i, .Lfunc_end0-_Z35__device_stub__leaf_pointer_jumpingPiS_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z20leaf_pointer_jumpingPiS_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z20leaf_pointer_jumpingPiS_i,@object # @_Z20leaf_pointer_jumpingPiS_i
.section .rodata,"a",@progbits
.globl _Z20leaf_pointer_jumpingPiS_i
.p2align 3, 0x0
_Z20leaf_pointer_jumpingPiS_i:
.quad _Z35__device_stub__leaf_pointer_jumpingPiS_i
.size _Z20leaf_pointer_jumpingPiS_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z20leaf_pointer_jumpingPiS_i"
.size .L__unnamed_1, 30
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z35__device_stub__leaf_pointer_jumpingPiS_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z20leaf_pointer_jumpingPiS_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* @file : constant_eg1.cu
* @brief : Examples of using constant memory for CUDA, with smart pointers
* @details : constant memory for CUDA examples
*
* @author : Ernest Yeung <ernestyalumni@gmail.com>
* @date : 20170103
* @ref : http://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#device-memory-specifiers
*
* https://www.paypal.com/cgi-bin/webscr?cmd=_donations&business=ernestsaveschristmas%2bpaypal%40gmail%2ecom&lc=US&item_name=ernestyalumni¤cy_code=USD&bn=PP%2dDonationsBF%3abtn_donateCC_LG%2egif%3aNonHosted
*
* which won't go through a 3rd. party such as indiegogo, kickstarter, patreon.
* Otherwise, I receive emails and messages on how all my (free) material on
* physics, math, and engineering have helped students with their studies,
* and I know what it's like to not have money as a student, but love physics
* (or math, sciences, etc.), so I am committed to keeping all my material
* open-source and free, whether or not
* sufficiently crowdfunded, under the open-source MIT license:
* feel free to copy, edit, paste, make your own versions, share, use as you wish.
* Just don't be an asshole and not give credit where credit is due.
* Peace out, never give up! -EY
*
* */
/*
* COMPILATION TIP
* nvcc constant_eg.cu -o constant_eg
*
* */
#include <iostream>
#include <memory> // std::unique_ptr
#include <array> // std::array
#include <math.h> // std::exp
/*
// custom deleter as lambda function for float arrays (RR=real numbers=floats)
auto del_RRarr_lambda=[&](float* ptr) { cudaFree(ptr); };
// custom deleter as lambda function for int arrays (ZZ=integers=ints)
auto del_ZZarr_lambda=[&](int* ptr) { cudaFree(ptr); };
/* error: expected a type specifier // constant_eg1.cu(39): error: variable "del_RRarr_lambda" is not a type name
* obtained when trying to initialize in type declaration in struct */
/*
struct S1_unique_lambda {
// (data) members
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr(nullptr, del_RRarr_lambda);
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr(nullptr, del_ZZarr_lambda);
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr;
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr;
// std::unique_ptr<float[]> dev_X_uptr; // error:
/* error: no operator "=" matches these operands
operand types are: std::unique_ptr<float [], std::default_delete<float []>> = std::unique_ptr<float [], lambda [](float *)->void>
*/
/*
std::unique_ptr<int[]> dev_S_uptr;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
// constructor
S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny);
// move constructor
S1_unique_lambda(S1_unique_lambda &&);
// operator overload assignment =
S1_unique_lambda &operator=(S1_unique_lambda &&);
};
// constructor
S1_unique_lambda::S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr_new(nullptr,del_RRarr_lambda);
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],decltype(del_ZZarr_lambda)> dev_S_uptr_new(nullptr,del_ZZarr_lambda);
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_lambda::S1_unique_lambda(S1_unique_lambda&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_lambda & S1_unique_lambda::operator=(S1_unique_lambda && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
// custom deleter as struct for float arrays (RR=real numbers=floats)
struct del_RRarr_struct {
void operator()(float* ptr) { cudaFree(ptr); }
};
// custom deleter as struct for int arrays (ZZ=integers=ints)
struct del_ZZarr_struct {
void operator()(int* ptr) { cudaFree(ptr); }
};
struct S1_unique_struct {
// (data) members , no dynamic initialization, but then no suitable constructor
// std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr; //(nullptr, del_RRarr_struct());
// std::unique_ptr<int[], del_ZZarr_struct> dev_S_uptr; // (nullptr, del_ZZarr_struct());
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
/* no dynamic initialization
// default constructor, needed by __constant__
S1_unique_struct();
// constructor
S1_unique_struct(size_t Lx, size_t Ly,unsigned long long Nx, unsigned long long Ny);
// move constructor
S1_unique_struct(S1_unique_struct &&);
// operator overload assignment =
S1_unique_struct &operator=(S1_unique_struct &&);
*/
};
/* no dynamic initialization
// default constructor
S1_unique_struct::S1_unique_struct() {
/* std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
/*
* error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
*/
// constructor
/*
S1_unique_struct::S1_unique_struct(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_struct::S1_unique_struct(S1_unique_struct&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_struct & S1_unique_struct::operator=(S1_unique_struct && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
__constant__ S1_unique_struct constS1_uniq_struct;
/*
* struct with a constructor (but very trivial, or what CUDA doc calls "empty"
* */
struct S2 {
float E;
float M;
float T;
// default constructor
// S2();
// constructors
// S2(float, float, float);
// S2(float); // only given T
};
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
/*
S2::S2() : E {0.f}, M {0.f}, T {0.f} {};
S2::S2(float E, float M, float T) : E{E}, M{M}, T{T} {};
S2::S2(float T) : E{0.f}, M{0.f}, T{T} {};
*/
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
//S2::S2() { E = 0.f; M=0.f; T=0.f; } ;
__constant__ S2 constS2 ;
struct S3 {
// (data) members , no dynamic initialization, but then no suitable constructor
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
float J;
// getting function
float get_by_DeltaE(int DeltaE) {
return transProb[DeltaE+8]; }
};
__constant__ S3 constS3;
int main(int argc, char* argv[]) {
// std::cout << " sizeof S1_unique_lambda : " << sizeof(S1_unique_lambda) << std::endl;
std::cout << " sizeof S1_unique_struct : " << sizeof(S1_unique_struct) << std::endl;
/* "boilerplate" test values */
// on host
std::array<float,17> h_transProb;
for (int i=0; i<17; i++) {
h_transProb[i] = std::exp( (float) i) ;
}
S1_unique_struct s1_uniq_struct { h_transProb, 256,128,64,32 };
cudaMemcpyToSymbol(constS1_uniq_struct, &s1_uniq_struct, sizeof(S1_unique_struct));
// this works as well
// cudaMemcpyToSymbol(constS1_uniq_struct, &s1_uniq_struct, sizeof(s1_uniq_struct));
/* sanity check */
S1_unique_struct h_s1_uniq_struct;
cudaMemcpyFromSymbol(&h_s1_uniq_struct, constS1_uniq_struct, sizeof(S1_unique_struct));
std::cout << " Lx : " << h_s1_uniq_struct.Lx << " Ly : " << h_s1_uniq_struct.Ly <<
" Nx : " << h_s1_uniq_struct.Nx << " Ny : " << h_s1_uniq_struct.Ny << std::endl;
for (int i =0; i<17; i++) {
std::cout << h_s1_uniq_struct.transProb[i] << " ";
}
std::cout << std::endl << std::endl;
/* "boilerplate" test values */
// on host
S2 hS2 { 1.f };
cudaMemcpyToSymbol(constS2, &hS2, sizeof(S2));
/* ********** testing struct S3 ********** */
S3 hS3 { h_transProb, 256,128,64,32, 1.0f } ;
cudaMemcpyToSymbol(constS3, &hS3, sizeof(S3));
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* @file : constant_eg1.cu
* @brief : Examples of using constant memory for CUDA, with smart pointers
* @details : constant memory for CUDA examples
*
* @author : Ernest Yeung <ernestyalumni@gmail.com>
* @date : 20170103
* @ref : http://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#device-memory-specifiers
*
* https://www.paypal.com/cgi-bin/webscr?cmd=_donations&business=ernestsaveschristmas%2bpaypal%40gmail%2ecom&lc=US&item_name=ernestyalumni¤cy_code=USD&bn=PP%2dDonationsBF%3abtn_donateCC_LG%2egif%3aNonHosted
*
* which won't go through a 3rd. party such as indiegogo, kickstarter, patreon.
* Otherwise, I receive emails and messages on how all my (free) material on
* physics, math, and engineering have helped students with their studies,
* and I know what it's like to not have money as a student, but love physics
* (or math, sciences, etc.), so I am committed to keeping all my material
* open-source and free, whether or not
* sufficiently crowdfunded, under the open-source MIT license:
* feel free to copy, edit, paste, make your own versions, share, use as you wish.
* Just don't be an asshole and not give credit where credit is due.
* Peace out, never give up! -EY
*
* */
/*
* COMPILATION TIP
* nvcc constant_eg.cu -o constant_eg
*
* */
#include <iostream>
#include <memory> // std::unique_ptr
#include <array> // std::array
#include <math.h> // std::exp
/*
// custom deleter as lambda function for float arrays (RR=real numbers=floats)
auto del_RRarr_lambda=[&](float* ptr) { cudaFree(ptr); };
// custom deleter as lambda function for int arrays (ZZ=integers=ints)
auto del_ZZarr_lambda=[&](int* ptr) { cudaFree(ptr); };
/* error: expected a type specifier // constant_eg1.cu(39): error: variable "del_RRarr_lambda" is not a type name
* obtained when trying to initialize in type declaration in struct */
/*
struct S1_unique_lambda {
// (data) members
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr(nullptr, del_RRarr_lambda);
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr(nullptr, del_ZZarr_lambda);
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr;
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr;
// std::unique_ptr<float[]> dev_X_uptr; // error:
/* error: no operator "=" matches these operands
operand types are: std::unique_ptr<float [], std::default_delete<float []>> = std::unique_ptr<float [], lambda [](float *)->void>
*/
/*
std::unique_ptr<int[]> dev_S_uptr;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
// constructor
S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny);
// move constructor
S1_unique_lambda(S1_unique_lambda &&);
// operator overload assignment =
S1_unique_lambda &operator=(S1_unique_lambda &&);
};
// constructor
S1_unique_lambda::S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr_new(nullptr,del_RRarr_lambda);
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],decltype(del_ZZarr_lambda)> dev_S_uptr_new(nullptr,del_ZZarr_lambda);
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_lambda::S1_unique_lambda(S1_unique_lambda&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_lambda & S1_unique_lambda::operator=(S1_unique_lambda && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
// custom deleter as struct for float arrays (RR=real numbers=floats)
struct del_RRarr_struct {
void operator()(float* ptr) { cudaFree(ptr); }
};
// custom deleter as struct for int arrays (ZZ=integers=ints)
struct del_ZZarr_struct {
void operator()(int* ptr) { cudaFree(ptr); }
};
struct S1_unique_struct {
// (data) members , no dynamic initialization, but then no suitable constructor
// std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr; //(nullptr, del_RRarr_struct());
// std::unique_ptr<int[], del_ZZarr_struct> dev_S_uptr; // (nullptr, del_ZZarr_struct());
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
/* no dynamic initialization
// default constructor, needed by __constant__
S1_unique_struct();
// constructor
S1_unique_struct(size_t Lx, size_t Ly,unsigned long long Nx, unsigned long long Ny);
// move constructor
S1_unique_struct(S1_unique_struct &&);
// operator overload assignment =
S1_unique_struct &operator=(S1_unique_struct &&);
*/
};
/* no dynamic initialization
// default constructor
S1_unique_struct::S1_unique_struct() {
/* std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
/*
* error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
*/
// constructor
/*
S1_unique_struct::S1_unique_struct(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_struct::S1_unique_struct(S1_unique_struct&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_struct & S1_unique_struct::operator=(S1_unique_struct && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
__constant__ S1_unique_struct constS1_uniq_struct;
/*
* struct with a constructor (but very trivial, or what CUDA doc calls "empty"
* */
struct S2 {
float E;
float M;
float T;
// default constructor
// S2();
// constructors
// S2(float, float, float);
// S2(float); // only given T
};
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
/*
S2::S2() : E {0.f}, M {0.f}, T {0.f} {};
S2::S2(float E, float M, float T) : E{E}, M{M}, T{T} {};
S2::S2(float T) : E{0.f}, M{0.f}, T{T} {};
*/
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
//S2::S2() { E = 0.f; M=0.f; T=0.f; } ;
__constant__ S2 constS2 ;
struct S3 {
// (data) members , no dynamic initialization, but then no suitable constructor
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
float J;
// getting function
float get_by_DeltaE(int DeltaE) {
return transProb[DeltaE+8]; }
};
__constant__ S3 constS3;
int main(int argc, char* argv[]) {
// std::cout << " sizeof S1_unique_lambda : " << sizeof(S1_unique_lambda) << std::endl;
std::cout << " sizeof S1_unique_struct : " << sizeof(S1_unique_struct) << std::endl;
/* "boilerplate" test values */
// on host
std::array<float,17> h_transProb;
for (int i=0; i<17; i++) {
h_transProb[i] = std::exp( (float) i) ;
}
S1_unique_struct s1_uniq_struct { h_transProb, 256,128,64,32 };
cudaMemcpyToSymbol(constS1_uniq_struct, &s1_uniq_struct, sizeof(S1_unique_struct));
// this works as well
// cudaMemcpyToSymbol(constS1_uniq_struct, &s1_uniq_struct, sizeof(s1_uniq_struct));
/* sanity check */
S1_unique_struct h_s1_uniq_struct;
cudaMemcpyFromSymbol(&h_s1_uniq_struct, constS1_uniq_struct, sizeof(S1_unique_struct));
std::cout << " Lx : " << h_s1_uniq_struct.Lx << " Ly : " << h_s1_uniq_struct.Ly <<
" Nx : " << h_s1_uniq_struct.Nx << " Ny : " << h_s1_uniq_struct.Ny << std::endl;
for (int i =0; i<17; i++) {
std::cout << h_s1_uniq_struct.transProb[i] << " ";
}
std::cout << std::endl << std::endl;
/* "boilerplate" test values */
// on host
S2 hS2 { 1.f };
cudaMemcpyToSymbol(constS2, &hS2, sizeof(S2));
/* ********** testing struct S3 ********** */
S3 hS3 { h_transProb, 256,128,64,32, 1.0f } ;
cudaMemcpyToSymbol(constS3, &hS3, sizeof(S3));
} | .file "tmpxft_00188199_00000000-6_constant_eg1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4359:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4359:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " sizeof S1_unique_struct : "
.LC1:
.string " Lx : "
.LC2:
.string " Ly : "
.LC3:
.string " Nx : "
.LC4:
.string " Ny : "
.LC5:
.string " "
.text
.globl main
.type main, @function
main:
.LFB4356:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $456, %rsp
.cfi_def_cfa_offset 496
movq %fs:40, %rax
movq %rax, 440(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $104, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
.L4:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
call expf@PLT
movss %xmm0, 16(%rsp,%rbx,4)
addq $1, %rbx
cmpq $17, %rbx
jne .L4
movl $0, 164(%rsp)
movq $256, 168(%rsp)
movq $128, 176(%rsp)
movq $64, 184(%rsp)
movq $32, 192(%rsp)
movdqa 16(%rsp), %xmm1
movaps %xmm1, 96(%rsp)
movdqa 32(%rsp), %xmm2
movaps %xmm2, 112(%rsp)
movdqa 48(%rsp), %xmm3
movaps %xmm3, 128(%rsp)
movdqa 64(%rsp), %xmm4
movaps %xmm4, 144(%rsp)
movl 80(%rsp), %eax
movl %eax, 160(%rsp)
leaq 96(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $104, %edx
leaq _ZL19constS1_uniq_struct(%rip), %rbp
movq %rbp, %rdi
call cudaMemcpyToSymbol@PLT
leaq 208(%rsp), %rbx
movl $2, %r8d
movl $0, %ecx
movl $104, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMemcpyFromSymbol@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 280(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 288(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 296(%rsp), %rsi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 304(%rsp), %rsi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 276(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC5(%rip), %rbp
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L5
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq $0, 8(%rsp)
movl .LC6(%rip), %ebx
movl %ebx, 4(%rsp)
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $12, %edx
leaq _ZL7constS2(%rip), %rdi
call cudaMemcpyToSymbol@PLT
pxor %xmm0, %xmm0
movups %xmm0, 388(%rsp)
movups %xmm0, 416(%rsp)
movq $256, 392(%rsp)
movq $128, 400(%rsp)
movq $64, 408(%rsp)
movq $32, 416(%rsp)
movl %ebx, 424(%rsp)
movdqa 16(%rsp), %xmm5
movaps %xmm5, 320(%rsp)
movdqa 32(%rsp), %xmm6
movaps %xmm6, 336(%rsp)
movdqa 48(%rsp), %xmm7
movaps %xmm7, 352(%rsp)
movdqa 64(%rsp), %xmm1
movaps %xmm1, 368(%rsp)
movl 80(%rsp), %eax
movl %eax, 384(%rsp)
leaq 320(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $112, %edx
leaq _ZL7constS3(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq 440(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $456, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4356:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "constS1_uniq_struct"
.LC9:
.string "constS2"
.LC10:
.string "constS3"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4382:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $104, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL19constS1_uniq_struct(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $12, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7constS2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $112, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7constS3(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4382:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7constS3
.comm _ZL7constS3,112,32
.local _ZL7constS2
.comm _ZL7constS2,12,8
.local _ZL19constS1_uniq_struct
.comm _ZL19constS1_uniq_struct,104,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* @file : constant_eg1.cu
* @brief : Examples of using constant memory for CUDA, with smart pointers
* @details : constant memory for CUDA examples
*
* @author : Ernest Yeung <ernestyalumni@gmail.com>
* @date : 20170103
* @ref : http://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#device-memory-specifiers
*
* https://www.paypal.com/cgi-bin/webscr?cmd=_donations&business=ernestsaveschristmas%2bpaypal%40gmail%2ecom&lc=US&item_name=ernestyalumni¤cy_code=USD&bn=PP%2dDonationsBF%3abtn_donateCC_LG%2egif%3aNonHosted
*
* which won't go through a 3rd. party such as indiegogo, kickstarter, patreon.
* Otherwise, I receive emails and messages on how all my (free) material on
* physics, math, and engineering have helped students with their studies,
* and I know what it's like to not have money as a student, but love physics
* (or math, sciences, etc.), so I am committed to keeping all my material
* open-source and free, whether or not
* sufficiently crowdfunded, under the open-source MIT license:
* feel free to copy, edit, paste, make your own versions, share, use as you wish.
* Just don't be an asshole and not give credit where credit is due.
* Peace out, never give up! -EY
*
* */
/*
* COMPILATION TIP
* nvcc constant_eg.cu -o constant_eg
*
* */
#include <iostream>
#include <memory> // std::unique_ptr
#include <array> // std::array
#include <math.h> // std::exp
/*
// custom deleter as lambda function for float arrays (RR=real numbers=floats)
auto del_RRarr_lambda=[&](float* ptr) { cudaFree(ptr); };
// custom deleter as lambda function for int arrays (ZZ=integers=ints)
auto del_ZZarr_lambda=[&](int* ptr) { cudaFree(ptr); };
/* error: expected a type specifier // constant_eg1.cu(39): error: variable "del_RRarr_lambda" is not a type name
* obtained when trying to initialize in type declaration in struct */
/*
struct S1_unique_lambda {
// (data) members
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr(nullptr, del_RRarr_lambda);
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr(nullptr, del_ZZarr_lambda);
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr;
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr;
// std::unique_ptr<float[]> dev_X_uptr; // error:
/* error: no operator "=" matches these operands
operand types are: std::unique_ptr<float [], std::default_delete<float []>> = std::unique_ptr<float [], lambda [](float *)->void>
*/
/*
std::unique_ptr<int[]> dev_S_uptr;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
// constructor
S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny);
// move constructor
S1_unique_lambda(S1_unique_lambda &&);
// operator overload assignment =
S1_unique_lambda &operator=(S1_unique_lambda &&);
};
// constructor
S1_unique_lambda::S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr_new(nullptr,del_RRarr_lambda);
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],decltype(del_ZZarr_lambda)> dev_S_uptr_new(nullptr,del_ZZarr_lambda);
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_lambda::S1_unique_lambda(S1_unique_lambda&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_lambda & S1_unique_lambda::operator=(S1_unique_lambda && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
// custom deleter as struct for float arrays (RR=real numbers=floats)
struct del_RRarr_struct {
void operator()(float* ptr) { cudaFree(ptr); }
};
// custom deleter as struct for int arrays (ZZ=integers=ints)
struct del_ZZarr_struct {
void operator()(int* ptr) { cudaFree(ptr); }
};
struct S1_unique_struct {
// (data) members , no dynamic initialization, but then no suitable constructor
// std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr; //(nullptr, del_RRarr_struct());
// std::unique_ptr<int[], del_ZZarr_struct> dev_S_uptr; // (nullptr, del_ZZarr_struct());
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
/* no dynamic initialization
// default constructor, needed by __constant__
S1_unique_struct();
// constructor
S1_unique_struct(size_t Lx, size_t Ly,unsigned long long Nx, unsigned long long Ny);
// move constructor
S1_unique_struct(S1_unique_struct &&);
// operator overload assignment =
S1_unique_struct &operator=(S1_unique_struct &&);
*/
};
/* no dynamic initialization
// default constructor
S1_unique_struct::S1_unique_struct() {
/* std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
/*
* error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
*/
// constructor
/*
S1_unique_struct::S1_unique_struct(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_struct::S1_unique_struct(S1_unique_struct&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_struct & S1_unique_struct::operator=(S1_unique_struct && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
__constant__ S1_unique_struct constS1_uniq_struct;
/*
* struct with a constructor (but very trivial, or what CUDA doc calls "empty"
* */
struct S2 {
float E;
float M;
float T;
// default constructor
// S2();
// constructors
// S2(float, float, float);
// S2(float); // only given T
};
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
/*
S2::S2() : E {0.f}, M {0.f}, T {0.f} {};
S2::S2(float E, float M, float T) : E{E}, M{M}, T{T} {};
S2::S2(float T) : E{0.f}, M{0.f}, T{T} {};
*/
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
//S2::S2() { E = 0.f; M=0.f; T=0.f; } ;
__constant__ S2 constS2 ;
struct S3 {
// (data) members , no dynamic initialization, but then no suitable constructor
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
float J;
// getting function
float get_by_DeltaE(int DeltaE) {
return transProb[DeltaE+8]; }
};
__constant__ S3 constS3;
int main(int argc, char* argv[]) {
// std::cout << " sizeof S1_unique_lambda : " << sizeof(S1_unique_lambda) << std::endl;
std::cout << " sizeof S1_unique_struct : " << sizeof(S1_unique_struct) << std::endl;
/* "boilerplate" test values */
// on host
std::array<float,17> h_transProb;
for (int i=0; i<17; i++) {
h_transProb[i] = std::exp( (float) i) ;
}
S1_unique_struct s1_uniq_struct { h_transProb, 256,128,64,32 };
cudaMemcpyToSymbol(constS1_uniq_struct, &s1_uniq_struct, sizeof(S1_unique_struct));
// this works as well
// cudaMemcpyToSymbol(constS1_uniq_struct, &s1_uniq_struct, sizeof(s1_uniq_struct));
/* sanity check */
S1_unique_struct h_s1_uniq_struct;
cudaMemcpyFromSymbol(&h_s1_uniq_struct, constS1_uniq_struct, sizeof(S1_unique_struct));
std::cout << " Lx : " << h_s1_uniq_struct.Lx << " Ly : " << h_s1_uniq_struct.Ly <<
" Nx : " << h_s1_uniq_struct.Nx << " Ny : " << h_s1_uniq_struct.Ny << std::endl;
for (int i =0; i<17; i++) {
std::cout << h_s1_uniq_struct.transProb[i] << " ";
}
std::cout << std::endl << std::endl;
/* "boilerplate" test values */
// on host
S2 hS2 { 1.f };
cudaMemcpyToSymbol(constS2, &hS2, sizeof(S2));
/* ********** testing struct S3 ********** */
S3 hS3 { h_transProb, 256,128,64,32, 1.0f } ;
cudaMemcpyToSymbol(constS3, &hS3, sizeof(S3));
} | /**
* @file : constant_eg1.cu
* @brief : Examples of using constant memory for CUDA, with smart pointers
* @details : constant memory for CUDA examples
*
* @author : Ernest Yeung <ernestyalumni@gmail.com>
* @date : 20170103
* @ref : http://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#device-memory-specifiers
*
* https://www.paypal.com/cgi-bin/webscr?cmd=_donations&business=ernestsaveschristmas%2bpaypal%40gmail%2ecom&lc=US&item_name=ernestyalumni¤cy_code=USD&bn=PP%2dDonationsBF%3abtn_donateCC_LG%2egif%3aNonHosted
*
* which won't go through a 3rd. party such as indiegogo, kickstarter, patreon.
* Otherwise, I receive emails and messages on how all my (free) material on
* physics, math, and engineering have helped students with their studies,
* and I know what it's like to not have money as a student, but love physics
* (or math, sciences, etc.), so I am committed to keeping all my material
* open-source and free, whether or not
* sufficiently crowdfunded, under the open-source MIT license:
* feel free to copy, edit, paste, make your own versions, share, use as you wish.
* Just don't be an asshole and not give credit where credit is due.
* Peace out, never give up! -EY
*
* */
/*
* COMPILATION TIP
* nvcc constant_eg.cu -o constant_eg
*
* */
#include <hip/hip_runtime.h>
#include <iostream>
#include <memory> // std::unique_ptr
#include <array> // std::array
#include <math.h> // std::exp
/*
// custom deleter as lambda function for float arrays (RR=real numbers=floats)
auto del_RRarr_lambda=[&](float* ptr) { cudaFree(ptr); };
// custom deleter as lambda function for int arrays (ZZ=integers=ints)
auto del_ZZarr_lambda=[&](int* ptr) { cudaFree(ptr); };
/* error: expected a type specifier // constant_eg1.cu(39): error: variable "del_RRarr_lambda" is not a type name
* obtained when trying to initialize in type declaration in struct */
/*
struct S1_unique_lambda {
// (data) members
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr(nullptr, del_RRarr_lambda);
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr(nullptr, del_ZZarr_lambda);
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr;
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr;
// std::unique_ptr<float[]> dev_X_uptr; // error:
/* error: no operator "=" matches these operands
operand types are: std::unique_ptr<float [], std::default_delete<float []>> = std::unique_ptr<float [], lambda [](float *)->void>
*/
/*
std::unique_ptr<int[]> dev_S_uptr;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
// constructor
S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny);
// move constructor
S1_unique_lambda(S1_unique_lambda &&);
// operator overload assignment =
S1_unique_lambda &operator=(S1_unique_lambda &&);
};
// constructor
S1_unique_lambda::S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr_new(nullptr,del_RRarr_lambda);
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],decltype(del_ZZarr_lambda)> dev_S_uptr_new(nullptr,del_ZZarr_lambda);
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_lambda::S1_unique_lambda(S1_unique_lambda&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_lambda & S1_unique_lambda::operator=(S1_unique_lambda && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
// custom deleter as struct for float arrays (RR=real numbers=floats)
struct del_RRarr_struct {
void operator()(float* ptr) { hipFree(ptr); }
};
// custom deleter as struct for int arrays (ZZ=integers=ints)
struct del_ZZarr_struct {
void operator()(int* ptr) { hipFree(ptr); }
};
struct S1_unique_struct {
// (data) members , no dynamic initialization, but then no suitable constructor
// std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr; //(nullptr, del_RRarr_struct());
// std::unique_ptr<int[], del_ZZarr_struct> dev_S_uptr; // (nullptr, del_ZZarr_struct());
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
/* no dynamic initialization
// default constructor, needed by __constant__
S1_unique_struct();
// constructor
S1_unique_struct(size_t Lx, size_t Ly,unsigned long long Nx, unsigned long long Ny);
// move constructor
S1_unique_struct(S1_unique_struct &&);
// operator overload assignment =
S1_unique_struct &operator=(S1_unique_struct &&);
*/
};
/* no dynamic initialization
// default constructor
S1_unique_struct::S1_unique_struct() {
/* std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
/*
* error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
*/
// constructor
/*
S1_unique_struct::S1_unique_struct(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_struct::S1_unique_struct(S1_unique_struct&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_struct & S1_unique_struct::operator=(S1_unique_struct && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
__constant__ S1_unique_struct constS1_uniq_struct;
/*
* struct with a constructor (but very trivial, or what CUDA doc calls "empty"
* */
struct S2 {
float E;
float M;
float T;
// default constructor
// S2();
// constructors
// S2(float, float, float);
// S2(float); // only given T
};
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
/*
S2::S2() : E {0.f}, M {0.f}, T {0.f} {};
S2::S2(float E, float M, float T) : E{E}, M{M}, T{T} {};
S2::S2(float T) : E{0.f}, M{0.f}, T{T} {};
*/
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
//S2::S2() { E = 0.f; M=0.f; T=0.f; } ;
__constant__ S2 constS2 ;
struct S3 {
// (data) members , no dynamic initialization, but then no suitable constructor
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
float J;
// getting function
float get_by_DeltaE(int DeltaE) {
return transProb[DeltaE+8]; }
};
__constant__ S3 constS3;
int main(int argc, char* argv[]) {
// std::cout << " sizeof S1_unique_lambda : " << sizeof(S1_unique_lambda) << std::endl;
std::cout << " sizeof S1_unique_struct : " << sizeof(S1_unique_struct) << std::endl;
/* "boilerplate" test values */
// on host
std::array<float,17> h_transProb;
for (int i=0; i<17; i++) {
h_transProb[i] = std::exp( (float) i) ;
}
S1_unique_struct s1_uniq_struct { h_transProb, 256,128,64,32 };
hipMemcpyToSymbol(HIP_SYMBOL(constS1_uniq_struct), &s1_uniq_struct, sizeof(S1_unique_struct));
// this works as well
// cudaMemcpyToSymbol(constS1_uniq_struct, &s1_uniq_struct, sizeof(s1_uniq_struct));
/* sanity check */
S1_unique_struct h_s1_uniq_struct;
hipMemcpyFromSymbol(&h_s1_uniq_struct, HIP_SYMBOL(constS1_uniq_struct), sizeof(S1_unique_struct));
std::cout << " Lx : " << h_s1_uniq_struct.Lx << " Ly : " << h_s1_uniq_struct.Ly <<
" Nx : " << h_s1_uniq_struct.Nx << " Ny : " << h_s1_uniq_struct.Ny << std::endl;
for (int i =0; i<17; i++) {
std::cout << h_s1_uniq_struct.transProb[i] << " ";
}
std::cout << std::endl << std::endl;
/* "boilerplate" test values */
// on host
S2 hS2 { 1.f };
hipMemcpyToSymbol(HIP_SYMBOL(constS2), &hS2, sizeof(S2));
/* ********** testing struct S3 ********** */
S3 hS3 { h_transProb, 256,128,64,32, 1.0f } ;
hipMemcpyToSymbol(HIP_SYMBOL(constS3), &hS3, sizeof(S3));
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* @file : constant_eg1.cu
* @brief : Examples of using constant memory for CUDA, with smart pointers
* @details : constant memory for CUDA examples
*
* @author : Ernest Yeung <ernestyalumni@gmail.com>
* @date : 20170103
* @ref : http://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#device-memory-specifiers
*
* https://www.paypal.com/cgi-bin/webscr?cmd=_donations&business=ernestsaveschristmas%2bpaypal%40gmail%2ecom&lc=US&item_name=ernestyalumni¤cy_code=USD&bn=PP%2dDonationsBF%3abtn_donateCC_LG%2egif%3aNonHosted
*
* which won't go through a 3rd. party such as indiegogo, kickstarter, patreon.
* Otherwise, I receive emails and messages on how all my (free) material on
* physics, math, and engineering have helped students with their studies,
* and I know what it's like to not have money as a student, but love physics
* (or math, sciences, etc.), so I am committed to keeping all my material
* open-source and free, whether or not
* sufficiently crowdfunded, under the open-source MIT license:
* feel free to copy, edit, paste, make your own versions, share, use as you wish.
* Just don't be an asshole and not give credit where credit is due.
* Peace out, never give up! -EY
*
* */
/*
* COMPILATION TIP
* nvcc constant_eg.cu -o constant_eg
*
* */
#include <hip/hip_runtime.h>
#include <iostream>
#include <memory> // std::unique_ptr
#include <array> // std::array
#include <math.h> // std::exp
/*
// custom deleter as lambda function for float arrays (RR=real numbers=floats)
auto del_RRarr_lambda=[&](float* ptr) { cudaFree(ptr); };
// custom deleter as lambda function for int arrays (ZZ=integers=ints)
auto del_ZZarr_lambda=[&](int* ptr) { cudaFree(ptr); };
/* error: expected a type specifier // constant_eg1.cu(39): error: variable "del_RRarr_lambda" is not a type name
* obtained when trying to initialize in type declaration in struct */
/*
struct S1_unique_lambda {
// (data) members
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr(nullptr, del_RRarr_lambda);
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr(nullptr, del_ZZarr_lambda);
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr;
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr;
// std::unique_ptr<float[]> dev_X_uptr; // error:
/* error: no operator "=" matches these operands
operand types are: std::unique_ptr<float [], std::default_delete<float []>> = std::unique_ptr<float [], lambda [](float *)->void>
*/
/*
std::unique_ptr<int[]> dev_S_uptr;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
// constructor
S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny);
// move constructor
S1_unique_lambda(S1_unique_lambda &&);
// operator overload assignment =
S1_unique_lambda &operator=(S1_unique_lambda &&);
};
// constructor
S1_unique_lambda::S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr_new(nullptr,del_RRarr_lambda);
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],decltype(del_ZZarr_lambda)> dev_S_uptr_new(nullptr,del_ZZarr_lambda);
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_lambda::S1_unique_lambda(S1_unique_lambda&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_lambda & S1_unique_lambda::operator=(S1_unique_lambda && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
// custom deleter as struct for float arrays (RR=real numbers=floats)
struct del_RRarr_struct {
void operator()(float* ptr) { hipFree(ptr); }
};
// custom deleter as struct for int arrays (ZZ=integers=ints)
struct del_ZZarr_struct {
void operator()(int* ptr) { hipFree(ptr); }
};
struct S1_unique_struct {
// (data) members , no dynamic initialization, but then no suitable constructor
// std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr; //(nullptr, del_RRarr_struct());
// std::unique_ptr<int[], del_ZZarr_struct> dev_S_uptr; // (nullptr, del_ZZarr_struct());
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
/* no dynamic initialization
// default constructor, needed by __constant__
S1_unique_struct();
// constructor
S1_unique_struct(size_t Lx, size_t Ly,unsigned long long Nx, unsigned long long Ny);
// move constructor
S1_unique_struct(S1_unique_struct &&);
// operator overload assignment =
S1_unique_struct &operator=(S1_unique_struct &&);
*/
};
/* no dynamic initialization
// default constructor
S1_unique_struct::S1_unique_struct() {
/* std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
/*
* error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
*/
// constructor
/*
S1_unique_struct::S1_unique_struct(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_struct::S1_unique_struct(S1_unique_struct&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_struct & S1_unique_struct::operator=(S1_unique_struct && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
__constant__ S1_unique_struct constS1_uniq_struct;
/*
* struct with a constructor (but very trivial, or what CUDA doc calls "empty"
* */
struct S2 {
float E;
float M;
float T;
// default constructor
// S2();
// constructors
// S2(float, float, float);
// S2(float); // only given T
};
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
/*
S2::S2() : E {0.f}, M {0.f}, T {0.f} {};
S2::S2(float E, float M, float T) : E{E}, M{M}, T{T} {};
S2::S2(float T) : E{0.f}, M{0.f}, T{T} {};
*/
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
//S2::S2() { E = 0.f; M=0.f; T=0.f; } ;
__constant__ S2 constS2 ;
struct S3 {
// (data) members , no dynamic initialization, but then no suitable constructor
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
float J;
// getting function
float get_by_DeltaE(int DeltaE) {
return transProb[DeltaE+8]; }
};
__constant__ S3 constS3;
int main(int argc, char* argv[]) {
// std::cout << " sizeof S1_unique_lambda : " << sizeof(S1_unique_lambda) << std::endl;
std::cout << " sizeof S1_unique_struct : " << sizeof(S1_unique_struct) << std::endl;
/* "boilerplate" test values */
// on host
std::array<float,17> h_transProb;
for (int i=0; i<17; i++) {
h_transProb[i] = std::exp( (float) i) ;
}
S1_unique_struct s1_uniq_struct { h_transProb, 256,128,64,32 };
hipMemcpyToSymbol(HIP_SYMBOL(constS1_uniq_struct), &s1_uniq_struct, sizeof(S1_unique_struct));
// this works as well
// cudaMemcpyToSymbol(constS1_uniq_struct, &s1_uniq_struct, sizeof(s1_uniq_struct));
/* sanity check */
S1_unique_struct h_s1_uniq_struct;
hipMemcpyFromSymbol(&h_s1_uniq_struct, HIP_SYMBOL(constS1_uniq_struct), sizeof(S1_unique_struct));
std::cout << " Lx : " << h_s1_uniq_struct.Lx << " Ly : " << h_s1_uniq_struct.Ly <<
" Nx : " << h_s1_uniq_struct.Nx << " Ny : " << h_s1_uniq_struct.Ny << std::endl;
for (int i =0; i<17; i++) {
std::cout << h_s1_uniq_struct.transProb[i] << " ";
}
std::cout << std::endl << std::endl;
/* "boilerplate" test values */
// on host
S2 hS2 { 1.f };
hipMemcpyToSymbol(HIP_SYMBOL(constS2), &hS2, sizeof(S2));
/* ********** testing struct S3 ********** */
S3 hS3 { h_transProb, 256,128,64,32, 1.0f } ;
hipMemcpyToSymbol(HIP_SYMBOL(constS3), &hS3, sizeof(S3));
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected constS1_uniq_struct
.type constS1_uniq_struct,@object
.section .bss,"aw",@nobits
.globl constS1_uniq_struct
.p2align 3, 0x0
constS1_uniq_struct:
.zero 104
.size constS1_uniq_struct, 104
.protected constS2
.type constS2,@object
.globl constS2
.p2align 2, 0x0
constS2:
.zero 12
.size constS2, 12
.protected constS3
.type constS3,@object
.globl constS3
.p2align 3, 0x0
constS3:
.zero 112
.size constS3, 112
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym constS1_uniq_struct
.addrsig_sym constS2
.addrsig_sym constS3
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* @file : constant_eg1.cu
* @brief : Examples of using constant memory for CUDA, with smart pointers
* @details : constant memory for CUDA examples
*
* @author : Ernest Yeung <ernestyalumni@gmail.com>
* @date : 20170103
* @ref : http://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#device-memory-specifiers
*
* https://www.paypal.com/cgi-bin/webscr?cmd=_donations&business=ernestsaveschristmas%2bpaypal%40gmail%2ecom&lc=US&item_name=ernestyalumni¤cy_code=USD&bn=PP%2dDonationsBF%3abtn_donateCC_LG%2egif%3aNonHosted
*
* which won't go through a 3rd. party such as indiegogo, kickstarter, patreon.
* Otherwise, I receive emails and messages on how all my (free) material on
* physics, math, and engineering have helped students with their studies,
* and I know what it's like to not have money as a student, but love physics
* (or math, sciences, etc.), so I am committed to keeping all my material
* open-source and free, whether or not
* sufficiently crowdfunded, under the open-source MIT license:
* feel free to copy, edit, paste, make your own versions, share, use as you wish.
* Just don't be an asshole and not give credit where credit is due.
* Peace out, never give up! -EY
*
* */
/*
* COMPILATION TIP
* nvcc constant_eg.cu -o constant_eg
*
* */
#include <hip/hip_runtime.h>
#include <iostream>
#include <memory> // std::unique_ptr
#include <array> // std::array
#include <math.h> // std::exp
/*
// custom deleter as lambda function for float arrays (RR=real numbers=floats)
auto del_RRarr_lambda=[&](float* ptr) { cudaFree(ptr); };
// custom deleter as lambda function for int arrays (ZZ=integers=ints)
auto del_ZZarr_lambda=[&](int* ptr) { cudaFree(ptr); };
/* error: expected a type specifier // constant_eg1.cu(39): error: variable "del_RRarr_lambda" is not a type name
* obtained when trying to initialize in type declaration in struct */
/*
struct S1_unique_lambda {
// (data) members
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr(nullptr, del_RRarr_lambda);
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr(nullptr, del_ZZarr_lambda);
// std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr;
// std::unique_ptr<int[], decltype(del_ZZarr_lambda)> dev_S_uptr;
// std::unique_ptr<float[]> dev_X_uptr; // error:
/* error: no operator "=" matches these operands
operand types are: std::unique_ptr<float [], std::default_delete<float []>> = std::unique_ptr<float [], lambda [](float *)->void>
*/
/*
std::unique_ptr<int[]> dev_S_uptr;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
// constructor
S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny);
// move constructor
S1_unique_lambda(S1_unique_lambda &&);
// operator overload assignment =
S1_unique_lambda &operator=(S1_unique_lambda &&);
};
// constructor
S1_unique_lambda::S1_unique_lambda(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],decltype(del_RRarr_lambda)> dev_X_uptr_new(nullptr,del_RRarr_lambda);
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],decltype(del_ZZarr_lambda)> dev_S_uptr_new(nullptr,del_ZZarr_lambda);
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_lambda::S1_unique_lambda(S1_unique_lambda&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_lambda & S1_unique_lambda::operator=(S1_unique_lambda && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
// custom deleter as struct for float arrays (RR=real numbers=floats)
struct del_RRarr_struct {
void operator()(float* ptr) { hipFree(ptr); }
};
// custom deleter as struct for int arrays (ZZ=integers=ints)
struct del_ZZarr_struct {
void operator()(int* ptr) { hipFree(ptr); }
};
struct S1_unique_struct {
// (data) members , no dynamic initialization, but then no suitable constructor
// std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr; //(nullptr, del_RRarr_struct());
// std::unique_ptr<int[], del_ZZarr_struct> dev_S_uptr; // (nullptr, del_ZZarr_struct());
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
/* no dynamic initialization
// default constructor, needed by __constant__
S1_unique_struct();
// constructor
S1_unique_struct(size_t Lx, size_t Ly,unsigned long long Nx, unsigned long long Ny);
// move constructor
S1_unique_struct(S1_unique_struct &&);
// operator overload assignment =
S1_unique_struct &operator=(S1_unique_struct &&);
*/
};
/* no dynamic initialization
// default constructor
S1_unique_struct::S1_unique_struct() {
/* std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
/*
* error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
*/
// constructor
/*
S1_unique_struct::S1_unique_struct(size_t Lx,size_t Ly,unsigned long long Nx,unsigned long long Ny) :
Lx {Lx}, Ly {Ly}, Nx {Nx}, Ny{Ny}
{
std::unique_ptr<float[],del_RRarr_struct> dev_X_uptr_new(nullptr,del_RRarr_struct());
dev_X_uptr = std::move(dev_X_uptr_new);
std::unique_ptr<int[],del_ZZarr_struct> dev_S_uptr_new(nullptr,del_ZZarr_struct());
dev_S_uptr = std::move(dev_S_uptr_new);
};
// move constructor
S1_unique_struct::S1_unique_struct(S1_unique_struct&& old_struct) :
Lx { old_struct.Lx }, Ly { old_struct.Ly}, Nx { old_struct.Nx }, Ny { old_struct.Ny },
dev_X_uptr{std::move(old_struct.dev_X_uptr) }, dev_S_uptr{std::move(old_struct.dev_S_uptr) } {};
// operator overload assignment =
S1_unique_struct & S1_unique_struct::operator=(S1_unique_struct && old_struct) {
Lx = old_struct.Lx;
Ly = old_struct.Ly;
Nx = old_struct.Nx;
Ny = old_struct.Ny;
// unique_ptrs moved
dev_X_uptr = std::move( old_struct.dev_X_uptr) ;
dev_S_uptr = std::move( old_struct.dev_S_uptr);
return *this;
};
*/
__constant__ S1_unique_struct constS1_uniq_struct;
/*
* struct with a constructor (but very trivial, or what CUDA doc calls "empty"
* */
struct S2 {
float E;
float M;
float T;
// default constructor
// S2();
// constructors
// S2(float, float, float);
// S2(float); // only given T
};
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
/*
S2::S2() : E {0.f}, M {0.f}, T {0.f} {};
S2::S2(float E, float M, float T) : E{E}, M{M}, T{T} {};
S2::S2(float T) : E{0.f}, M{0.f}, T{T} {};
*/
// error: dynamic initialization is not supported for __device__, __constant__ and __shared__ variables.
//S2::S2() { E = 0.f; M=0.f; T=0.f; } ;
__constant__ S2 constS2 ;
struct S3 {
// (data) members , no dynamic initialization, but then no suitable constructor
std::array<float, 17> transProb;
size_t Lx; // 8 bytes
size_t Ly; // 8 bytes
unsigned long long Nx; // 8 bytes
unsigned long long Ny; // 8 bytes
float J;
// getting function
float get_by_DeltaE(int DeltaE) {
return transProb[DeltaE+8]; }
};
__constant__ S3 constS3;
int main(int argc, char* argv[]) {
// std::cout << " sizeof S1_unique_lambda : " << sizeof(S1_unique_lambda) << std::endl;
std::cout << " sizeof S1_unique_struct : " << sizeof(S1_unique_struct) << std::endl;
/* "boilerplate" test values */
// on host
std::array<float,17> h_transProb;
for (int i=0; i<17; i++) {
h_transProb[i] = std::exp( (float) i) ;
}
S1_unique_struct s1_uniq_struct { h_transProb, 256,128,64,32 };
hipMemcpyToSymbol(HIP_SYMBOL(constS1_uniq_struct), &s1_uniq_struct, sizeof(S1_unique_struct));
// this works as well
// cudaMemcpyToSymbol(constS1_uniq_struct, &s1_uniq_struct, sizeof(s1_uniq_struct));
/* sanity check */
S1_unique_struct h_s1_uniq_struct;
hipMemcpyFromSymbol(&h_s1_uniq_struct, HIP_SYMBOL(constS1_uniq_struct), sizeof(S1_unique_struct));
std::cout << " Lx : " << h_s1_uniq_struct.Lx << " Ly : " << h_s1_uniq_struct.Ly <<
" Nx : " << h_s1_uniq_struct.Nx << " Ny : " << h_s1_uniq_struct.Ny << std::endl;
for (int i =0; i<17; i++) {
std::cout << h_s1_uniq_struct.transProb[i] << " ";
}
std::cout << std::endl << std::endl;
/* "boilerplate" test values */
// on host
S2 hS2 { 1.f };
hipMemcpyToSymbol(HIP_SYMBOL(constS2), &hS2, sizeof(S2));
/* ********** testing struct S3 ********** */
S3 hS3 { h_transProb, 256,128,64,32, 1.0f } ;
hipMemcpyToSymbol(HIP_SYMBOL(constS3), &hS3, sizeof(S3));
} | .text
.file "constant_eg1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $408, %rsp # imm = 0x198
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $104, %esi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
callq expf
movss %xmm0, 12(%rsp,%rbx,4)
incq %rbx
cmpq $17, %rbx
jne .LBB0_5
# %bb.6:
movl 76(%rsp), %eax
movl %eax, 256(%rsp)
movups 12(%rsp), %xmm0
movups 28(%rsp), %xmm1
movups 44(%rsp), %xmm2
movups 60(%rsp), %xmm3
movaps %xmm3, 240(%rsp)
movaps %xmm2, 224(%rsp)
movaps %xmm1, 208(%rsp)
movaps %xmm0, 192(%rsp)
movq $256, 264(%rsp) # imm = 0x100
movq $128, 272(%rsp)
movq $64, 280(%rsp)
movq $32, 288(%rsp)
leaq 192(%rsp), %rsi
movl $constS1_uniq_struct, %edi
movl $104, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 304(%rsp), %rdi
movl $constS1_uniq_struct, %esi
movl $104, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 376(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.2, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 384(%rsp), %rsi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 392(%rsp), %rsi
movq %rbx, %rdi
callq _ZNSo9_M_insertIyEERSoT_
movq %rax, %rbx
movl $.L.str.4, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 400(%rsp), %rsi
movq %rbx, %rdi
callq _ZNSo9_M_insertIyEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10
cmpb $0, 56(%rbx)
je .LBB0_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB0_10
.LBB0_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_11: # =>This Inner Loop Header: Depth=1
movss 304(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $17, %rbx
jne .LBB0_11
# %bb.12:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%rbx)
je .LBB0_15
# %bb.14:
movzbl 67(%rbx), %eax
jmp .LBB0_16
.LBB0_15:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%rbx)
je .LBB0_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB0_20
.LBB0_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq $1065353216, (%rsp) # imm = 0x3F800000
movl $0, 8(%rsp)
movq %rsp, %rsi
movl $constS2, %edi
movl $12, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl 76(%rsp), %eax
movl %eax, 144(%rsp)
movups 12(%rsp), %xmm0
movups 28(%rsp), %xmm1
movups 44(%rsp), %xmm2
movups 60(%rsp), %xmm3
movaps %xmm3, 128(%rsp)
movaps %xmm2, 112(%rsp)
movaps %xmm1, 96(%rsp)
movaps %xmm0, 80(%rsp)
movq $256, 152(%rsp) # imm = 0x100
movq $128, 160(%rsp)
movq $64, 168(%rsp)
movq $32, 176(%rsp)
movl $1065353216, 184(%rsp) # imm = 0x3F800000
leaq 80(%rsp), %rsi
movl $constS3, %edi
movl $112, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
xorl %eax, %eax
addq $408, %rsp # imm = 0x198
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_21:
.cfi_def_cfa_offset 432
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
movl $constS1_uniq_struct, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $104, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $constS2, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $12, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $constS3, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $112, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type constS1_uniq_struct,@object # @constS1_uniq_struct
.local constS1_uniq_struct
.comm constS1_uniq_struct,104,8
.type constS2,@object # @constS2
.local constS2
.comm constS2,12,4
.type constS3,@object # @constS3
.local constS3
.comm constS3,112,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " sizeof S1_unique_struct : "
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Lx : "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Ly : "
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Nx : "
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Ny : "
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " "
.size .L.str.5, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "constS1_uniq_struct"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "constS2"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "constS3"
.size .L__unnamed_3, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym constS1_uniq_struct
.addrsig_sym constS2
.addrsig_sym constS3
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.protected constS1_uniq_struct
.type constS1_uniq_struct,@object
.section .bss,"aw",@nobits
.globl constS1_uniq_struct
.p2align 3, 0x0
constS1_uniq_struct:
.zero 104
.size constS1_uniq_struct, 104
.protected constS2
.type constS2,@object
.globl constS2
.p2align 2, 0x0
constS2:
.zero 12
.size constS2, 12
.protected constS3
.type constS3,@object
.globl constS3
.p2align 3, 0x0
constS3:
.zero 112
.size constS3, 112
.type __hip_cuid_,@object
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym constS1_uniq_struct
.addrsig_sym constS2
.addrsig_sym constS3
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00188199_00000000-6_constant_eg1.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4359:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4359:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string " sizeof S1_unique_struct : "
.LC1:
.string " Lx : "
.LC2:
.string " Ly : "
.LC3:
.string " Nx : "
.LC4:
.string " Ny : "
.LC5:
.string " "
.text
.globl main
.type main, @function
main:
.LFB4356:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $456, %rsp
.cfi_def_cfa_offset 496
movq %fs:40, %rax
movq %rax, 440(%rsp)
xorl %eax, %eax
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movl $104, %esi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movl $0, %ebx
.L4:
pxor %xmm0, %xmm0
cvtsi2ssl %ebx, %xmm0
call expf@PLT
movss %xmm0, 16(%rsp,%rbx,4)
addq $1, %rbx
cmpq $17, %rbx
jne .L4
movl $0, 164(%rsp)
movq $256, 168(%rsp)
movq $128, 176(%rsp)
movq $64, 184(%rsp)
movq $32, 192(%rsp)
movdqa 16(%rsp), %xmm1
movaps %xmm1, 96(%rsp)
movdqa 32(%rsp), %xmm2
movaps %xmm2, 112(%rsp)
movdqa 48(%rsp), %xmm3
movaps %xmm3, 128(%rsp)
movdqa 64(%rsp), %xmm4
movaps %xmm4, 144(%rsp)
movl 80(%rsp), %eax
movl %eax, 160(%rsp)
leaq 96(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $104, %edx
leaq _ZL19constS1_uniq_struct(%rip), %rbp
movq %rbp, %rdi
call cudaMemcpyToSymbol@PLT
leaq 208(%rsp), %rbx
movl $2, %r8d
movl $0, %ecx
movl $104, %edx
movq %rbp, %rsi
movq %rbx, %rdi
call cudaMemcpyFromSymbol@PLT
leaq .LC1(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 280(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC2(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 288(%rsp), %rsi
call _ZNSo9_M_insertImEERSoT_@PLT
movq %rax, %rdi
leaq .LC3(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 296(%rsp), %rsi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
leaq .LC4(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 304(%rsp), %rsi
call _ZNSo9_M_insertIyEERSoT_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq 276(%rsp), %r13
leaq _ZSt4cout(%rip), %r12
leaq .LC5(%rip), %rbp
.L5:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rdi
call _ZNSo9_M_insertIdEERSoT_@PLT
movq %rax, %rdi
movl $1, %edx
movq %rbp, %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
addq $4, %rbx
cmpq %r13, %rbx
jne .L5
leaq _ZSt4cout(%rip), %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
movq $0, 8(%rsp)
movl .LC6(%rip), %ebx
movl %ebx, 4(%rsp)
leaq 4(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $12, %edx
leaq _ZL7constS2(%rip), %rdi
call cudaMemcpyToSymbol@PLT
pxor %xmm0, %xmm0
movups %xmm0, 388(%rsp)
movups %xmm0, 416(%rsp)
movq $256, 392(%rsp)
movq $128, 400(%rsp)
movq $64, 408(%rsp)
movq $32, 416(%rsp)
movl %ebx, 424(%rsp)
movdqa 16(%rsp), %xmm5
movaps %xmm5, 320(%rsp)
movdqa 32(%rsp), %xmm6
movaps %xmm6, 336(%rsp)
movdqa 48(%rsp), %xmm7
movaps %xmm7, 352(%rsp)
movdqa 64(%rsp), %xmm1
movaps %xmm1, 368(%rsp)
movl 80(%rsp), %eax
movl %eax, 384(%rsp)
leaq 320(%rsp), %rsi
movl $1, %r8d
movl $0, %ecx
movl $112, %edx
leaq _ZL7constS3(%rip), %rdi
call cudaMemcpyToSymbol@PLT
movq 440(%rsp), %rax
subq %fs:40, %rax
jne .L10
movl $0, %eax
addq $456, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L10:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4356:
.size main, .-main
.section .rodata.str1.1
.LC8:
.string "constS1_uniq_struct"
.LC9:
.string "constS2"
.LC10:
.string "constS3"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4382:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $104, %r9d
movl $0, %r8d
leaq .LC8(%rip), %rdx
movq %rdx, %rcx
leaq _ZL19constS1_uniq_struct(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $12, %r9d
movl $0, %r8d
leaq .LC9(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7constS2(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $1
.cfi_def_cfa_offset 32
movl $112, %r9d
movl $0, %r8d
leaq .LC10(%rip), %rdx
movq %rdx, %rcx
leaq _ZL7constS3(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterVar@PLT
addq $16, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4382:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZL7constS3
.comm _ZL7constS3,112,32
.local _ZL7constS2
.comm _ZL7constS2,12,8
.local _ZL19constS1_uniq_struct
.comm _ZL19constS1_uniq_struct,104,32
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC6:
.long 1065353216
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "constant_eg1.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $408, %rsp # imm = 0x198
.cfi_def_cfa_offset 432
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $27, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movl $_ZSt4cout, %edi
movl $104, %esi
callq _ZNSo9_M_insertImEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.1: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%rbx)
je .LBB0_3
# %bb.2:
movzbl 67(%rbx), %ecx
jmp .LBB0_4
.LBB0_3:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_4: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %ebx, %xmm0
callq expf
movss %xmm0, 12(%rsp,%rbx,4)
incq %rbx
cmpq $17, %rbx
jne .LBB0_5
# %bb.6:
movl 76(%rsp), %eax
movl %eax, 256(%rsp)
movups 12(%rsp), %xmm0
movups 28(%rsp), %xmm1
movups 44(%rsp), %xmm2
movups 60(%rsp), %xmm3
movaps %xmm3, 240(%rsp)
movaps %xmm2, 224(%rsp)
movaps %xmm1, 208(%rsp)
movaps %xmm0, 192(%rsp)
movq $256, 264(%rsp) # imm = 0x100
movq $128, 272(%rsp)
movq $64, 280(%rsp)
movq $32, 288(%rsp)
leaq 192(%rsp), %rsi
movl $constS1_uniq_struct, %edi
movl $104, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
leaq 304(%rsp), %rdi
movl $constS1_uniq_struct, %esi
movl $104, %edx
xorl %ecx, %ecx
movl $2, %r8d
callq hipMemcpyFromSymbol
movl $_ZSt4cout, %edi
movl $.L.str.1, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 376(%rsp), %rsi
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.2, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 384(%rsp), %rsi
movq %rbx, %rdi
callq _ZNSo9_M_insertImEERSoT_
movq %rax, %rbx
movl $.L.str.3, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 392(%rsp), %rsi
movq %rbx, %rdi
callq _ZNSo9_M_insertIyEERSoT_
movq %rax, %rbx
movl $.L.str.4, %esi
movl $6, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq 400(%rsp), %rsi
movq %rbx, %rdi
callq _ZNSo9_M_insertIyEERSoT_
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.7: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i10
cmpb $0, 56(%rbx)
je .LBB0_9
# %bb.8:
movzbl 67(%rbx), %ecx
jmp .LBB0_10
.LBB0_9:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_10: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit13
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
xorl %ebx, %ebx
.p2align 4, 0x90
.LBB0_11: # =>This Inner Loop Header: Depth=1
movss 304(%rsp,%rbx,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $_ZSt4cout, %edi
callq _ZNSo9_M_insertIdEERSoT_
movl $.L.str.5, %esi
movl $1, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
incq %rbx
cmpq $17, %rbx
jne .LBB0_11
# %bb.12:
movq _ZSt4cout(%rip), %rax
movq -24(%rax), %rax
movq _ZSt4cout+240(%rax), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.13: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i15
cmpb $0, 56(%rbx)
je .LBB0_15
# %bb.14:
movzbl 67(%rbx), %eax
jmp .LBB0_16
.LBB0_15:
movq %rbx, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
.LBB0_16: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit18
movsbl %al, %esi
movl $_ZSt4cout, %edi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq (%rax), %rcx
movq -24(%rcx), %rcx
movq 240(%rax,%rcx), %rbx
testq %rbx, %rbx
je .LBB0_21
# %bb.17: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i20
cmpb $0, 56(%rbx)
je .LBB0_19
# %bb.18:
movzbl 67(%rbx), %ecx
jmp .LBB0_20
.LBB0_19:
movq %rbx, %rdi
movq %rax, %r14
callq _ZNKSt5ctypeIcE13_M_widen_initEv
movq (%rbx), %rax
movq %rbx, %rdi
movl $10, %esi
callq *48(%rax)
movl %eax, %ecx
movq %r14, %rax
.LBB0_20: # %_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_.exit23
movsbl %cl, %esi
movq %rax, %rdi
callq _ZNSo3putEc
movq %rax, %rdi
callq _ZNSo5flushEv
movq $1065353216, (%rsp) # imm = 0x3F800000
movl $0, 8(%rsp)
movq %rsp, %rsi
movl $constS2, %edi
movl $12, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
movl 76(%rsp), %eax
movl %eax, 144(%rsp)
movups 12(%rsp), %xmm0
movups 28(%rsp), %xmm1
movups 44(%rsp), %xmm2
movups 60(%rsp), %xmm3
movaps %xmm3, 128(%rsp)
movaps %xmm2, 112(%rsp)
movaps %xmm1, 96(%rsp)
movaps %xmm0, 80(%rsp)
movq $256, 152(%rsp) # imm = 0x100
movq $128, 160(%rsp)
movq $64, 168(%rsp)
movq $32, 176(%rsp)
movl $1065353216, 184(%rsp) # imm = 0x3F800000
leaq 80(%rsp), %rsi
movl $constS3, %edi
movl $112, %edx
xorl %ecx, %ecx
movl $1, %r8d
callq hipMemcpyToSymbol
xorl %eax, %eax
addq $408, %rsp # imm = 0x198
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
retq
.LBB0_21:
.cfi_def_cfa_offset 432
callq _ZSt16__throw_bad_castv
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rbx
movl $constS1_uniq_struct, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $104, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $constS2, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movl $12, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $constS3, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movl $112, %r9d
movq %rbx, %rdi
xorl %r8d, %r8d
pushq $0
.cfi_adjust_cfa_offset 8
pushq $1
.cfi_adjust_cfa_offset 8
callq __hipRegisterVar
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl $__hip_module_dtor, %edi
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type constS1_uniq_struct,@object # @constS1_uniq_struct
.local constS1_uniq_struct
.comm constS1_uniq_struct,104,8
.type constS2,@object # @constS2
.local constS2
.comm constS2,12,4
.type constS3,@object # @constS3
.local constS3
.comm constS3,112,8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz " sizeof S1_unique_struct : "
.size .L.str, 28
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " Lx : "
.size .L.str.1, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz " Ly : "
.size .L.str.2, 7
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz " Nx : "
.size .L.str.3, 7
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz " Ny : "
.size .L.str.4, 7
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz " "
.size .L.str.5, 2
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "constS1_uniq_struct"
.size .L__unnamed_1, 20
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "constS2"
.size .L__unnamed_2, 8
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "constS3"
.size .L__unnamed_3, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym constS1_uniq_struct
.addrsig_sym constS2
.addrsig_sym constS3
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__device__ double efficientLocalMean_dev (const long x,const long y,const long k, double * input_img, int rowsize, int colsize) {
long k2 = k/2;
long dimx = rowsize;
long dimy = colsize;
//wanting average over area: (y-k2,x-k2) ... (y+k2-1, x+k2-1)
long starty = y-k2;
long startx = x-k2;
long stopy = y+k2-1;
long stopx = x+k2-1;
if (starty < 0) starty = 0;
if (startx < 0) startx = 0;
if (stopx > dimx-1) stopx = dimx-1;
if (stopy > dimy-1) stopy = dimy-1;
double unten, links, oben, obenlinks;
if (startx-1 < 0) links = 0;
else links = *(input_img+(stopy * dimx + startx-1));
if (starty-1 < 0) oben = 0;
else oben = *(input_img+((stopy-1) * dimx + startx));
if ((starty-1 < 0) || (startx-1 <0)) obenlinks = 0;
else obenlinks = *(input_img+((stopy-1) * dimx + startx-1));
unten = *(input_img+(stopy * dimx + startx));
long counter = (stopy-starty+1)*(stopx-startx+1);
return (unten-links-oben+obenlinks)/counter;
}
__global__ void process_coarseness_ak_pix(double * output_ak,double * input_img,int colsize, int rowsize,long lenOf_ak)
{
int index;
int y = threadIdx.x + blockIdx.x * blockDim.x;
int x = threadIdx.y + blockIdx.y * blockDim.y;
if(y < (colsize) && x < (rowsize))
{
index = y * rowsize + x ;
output_ak[index] = efficientLocalMean_dev(x,y,lenOf_ak,input_img,rowsize,colsize);
}
} | code for sm_80
Function : _Z25process_coarseness_ak_pixPdS_iil
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R9, R9, c[0x0][0x0], R2 ; /* 0x0000000009097a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x170], P0 ; /* 0x00005c0009007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff147624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ SHF.R.S32.HI R18, RZ, 0x1f, R0 ; /* 0x0000001fff127819 */
/* 0x000fe20000011400 */
/*00d0*/ UIADD3 UR8, UP0, UR6, -0x1, URZ ; /* 0xffffffff06087890 */
/* 0x000fe2000ff1e03f */
/*00e0*/ SHF.R.S32.HI R2, RZ, 0x1f, R9 ; /* 0x0000001fff027819 */
/* 0x000fe20000011409 */
/*00f0*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR7 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011407 */
/*0100*/ LEA.HI R20, P0, R20, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e0014147a11 */
/* 0x000fe200078108ff */
/*0110*/ ULEA.HI.X.SX32 UR5, UR6, 0xffffffff, 0x1, UP0 ; /* 0xffffffff06057891 */
/* 0x000fc600080f0e3f */
/*0120*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IMAD.X R21, RZ, RZ, c[0x0][0x17c], P0 ; /* 0x00005f00ff157624 */
/* 0x000fca00000e06ff */
/*0140*/ SHF.R.S64 R20, R20, 0x1, R21.reuse ; /* 0x0000000114147819 */
/* 0x100fe40000001015 */
/*0150*/ SHF.R.S32.HI R21, RZ, 0x1, R21 ; /* 0x00000001ff157819 */
/* 0x000fe40000011415 */
/*0160*/ IADD3 R4, P2, R0, -R20, RZ ; /* 0x8000001400047210 */
/* 0x000fe40007f5e0ff */
/*0170*/ IADD3 R19, P1, P3, R9, -0x1, R20 ; /* 0xffffffff09137810 */
/* 0x000fc60007b3e014 */
/*0180*/ IMAD.X R3, R18, 0x1, ~R21.reuse, P2 ; /* 0x0000000112037824 */
/* 0x100fe200010e0e15 */
/*0190*/ ISETP.LT.U32.AND P0, PT, R19, UR8, PT ; /* 0x0000000813007c0c */
/* 0x000fe4000bf01070 */
/*01a0*/ IADD3.X R8, R2, -0x1, R21, P1, P3 ; /* 0xffffffff02087810 */
/* 0x000fe40000fe6415 */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f24070 */
/*01c0*/ ISETP.LT.AND.EX P2, PT, R8, UR5, PT, P0 ; /* 0x0000000508007c0c */
/* 0x000fe4000bf41300 */
/*01d0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P1 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04310 */
/*01e0*/ IADD3 R22, P1, R9, -R20, RZ ; /* 0x8000001409167210 */
/* 0x000fc40007f3e0ff */
/*01f0*/ SEL R19, R19, UR8, P2 ; /* 0x0000000813137c07 */
/* 0x000fe40009000000 */
/*0200*/ SEL R8, R8, UR5, P2 ; /* 0x0000000508087c07 */
/* 0x000fe20009000000 */
/*0210*/ IMAD.X R23, R2, 0x1, ~R21, P1 ; /* 0x0000000102177824 */
/* 0x000fe200008e0e15 */
/*0220*/ SEL R4, R4, RZ, P0 ; /* 0x000000ff04047207 */
/* 0x000fe40000000000 */
/*0230*/ SEL R5, R3, RZ, P0 ; /* 0x000000ff03057207 */
/* 0x000fe20000000000 */
/*0240*/ IMAD R2, R8, c[0x0][0x174], RZ ; /* 0x00005d0008027a24 */
/* 0x000fe200078e02ff */
/*0250*/ IADD3 R7, P0, R19.reuse, -0x1, RZ ; /* 0xffffffff13077810 */
/* 0x040fe40007f1e0ff */
/*0260*/ ISETP.GT.U32.AND P1, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f24070 */
/*0270*/ IMAD R13, R19.reuse, UR4, R2 ; /* 0x00000004130d7c24 */
/* 0x040fe2000f8e0202 */
/*0280*/ IADD3.X R6, R8, -0x1, RZ, P0, !PT ; /* 0xffffffff08067810 */
/* 0x000fe200007fe4ff */
/*0290*/ IMAD.WIDE.U32 R2, R19, c[0x0][0x174], R4 ; /* 0x00005d0013027a25 */
/* 0x000fe200078e0004 */
/*02a0*/ ISETP.GT.AND.EX P1, PT, R23, RZ, PT, P1 ; /* 0x000000ff1700720c */
/* 0x000fc40003f24310 */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06070 */
/*02c0*/ IMAD R6, R6, c[0x0][0x174], RZ ; /* 0x00005d0006067a24 */
/* 0x000fe200078e02ff */
/*02d0*/ SEL R22, R22, RZ, P1 ; /* 0x000000ff16167207 */
/* 0x000fe20000800000 */
/*02e0*/ IMAD.IADD R3, R3, 0x1, R13 ; /* 0x0000000103037824 */
/* 0x000fe200078e020d */
/*02f0*/ ISETP.GE.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fe20003f06300 */
/*0300*/ IMAD.WIDE.U32 R10, R7, c[0x0][0x174], R4 ; /* 0x00005d00070a7a25 */
/* 0x000fe200078e0004 */
/*0310*/ SEL R23, R23, RZ, P1 ; /* 0x000000ff17177207 */
/* 0x000fe40000800000 */
/*0320*/ LEA R16, P2, R2, c[0x0][0x168], 0x3 ; /* 0x00005a0002107a11 */
/* 0x000fe200078418ff */
/*0330*/ IMAD R7, R7, UR4, R6 ; /* 0x0000000407077c24 */
/* 0x000fe2000f8e0206 */
/*0340*/ ISETP.GE.U32.AND P1, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fc40003f26070 */
/*0350*/ LEA.HI.X R17, R2, c[0x0][0x16c], R3, 0x3, P2 ; /* 0x00005b0002117a11 */
/* 0x000fe200010f1c03 */
/*0360*/ IMAD.IADD R7, R11, 0x1, R7 ; /* 0x000000010b077824 */
/* 0x000fe200078e0207 */
/*0370*/ ISETP.GE.AND.EX P1, PT, R23.reuse, RZ, PT, P1 ; /* 0x000000ff1700720c */
/* 0x040fe20003f26310 */
/*0380*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0390*/ LEA R6, P3, R10, c[0x0][0x168], 0x3 ; /* 0x00005a000a067a11 */
/* 0x000fe400078618ff */
/*03a0*/ ISETP.LT.U32.AND P2, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fe20003f41070 */
/*03b0*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*03c0*/ LEA.HI.X R7, R10, c[0x0][0x16c], R7, 0x3, P3 ; /* 0x00005b000a077a11 */
/* 0x000fe200018f1c07 */
/*03d0*/ @P0 LDG.E.64 R2, [R16.64+-0x8] ; /* 0xfffff80610020981 */
/* 0x0000a2000c1e1b00 */
/*03e0*/ ISETP.LT.OR.EX P2, PT, R23, RZ, !P0, P2 ; /* 0x000000ff1700720c */
/* 0x000fc60004741720 */
/*03f0*/ LDG.E.64 R10, [R16.64] ; /* 0x00000006100a7981 */
/* 0x0000a2000c1e1b00 */
/*0400*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fc6000001ff00 */
/*0410*/ @P1 LDG.E.64 R12, [R6.64] ; /* 0x00000006060c1981 */
/* 0x0002ec000c1e1b00 */
/*0420*/ @!P2 LDG.E.64 R14, [R6.64+-0x8] ; /* 0xfffff806060ea981 */
/* 0x000322000c1e1b00 */
/*0430*/ IADD3 R20, P0, R0, R20, RZ ; /* 0x0000001400147210 */
/* 0x000fca0007f1e0ff */
/*0440*/ IMAD.X R18, R18, 0x1, R21, P0 ; /* 0x0000000112127824 */
/* 0x000fe200000e0615 */
/*0450*/ ISETP.LT.U32.AND P0, PT, R20, c[0x0][0x174], PT ; /* 0x00005d0014007a0c */
/* 0x000fc80003f01070 */
/*0460*/ ISETP.LT.AND.EX P0, PT, R18, UR4, PT, P0 ; /* 0x0000000412007c0c */
/* 0x000fe4000bf01300 */
/*0470*/ IADD3 R19, P1, P2, R19, 0x1, -R22 ; /* 0x0000000113137810 */
/* 0x000fe40007a3e816 */
/*0480*/ SEL R21, R20, c[0x0][0x174], P0 ; /* 0x00005d0014157a07 */
/* 0x000fe40000000000 */
/*0490*/ IADD3.X R23, R8, RZ, ~R23, P1, P2 ; /* 0x000000ff08177210 */
/* 0x000fe40000fe4c17 */
/*04a0*/ IADD3 R4, P3, R21, -R4, RZ ; /* 0x8000000415047210 */
/* 0x000fe40007f7e0ff */
/*04b0*/ SEL R17, R18, UR4, P0 ; /* 0x0000000412117c07 */
/* 0x001fc60008000000 */
/*04c0*/ IMAD R6, R23, R4, RZ ; /* 0x0000000417067224 */
/* 0x002fe400078e02ff */
/*04d0*/ IMAD.X R5, R17, 0x1, ~R5, P3 ; /* 0x0000000111057824 */
/* 0x000fc800018e0e05 */
/*04e0*/ IMAD R7, R5, R19, R6 ; /* 0x0000001305077224 */
/* 0x000fe400078e0206 */
/*04f0*/ IMAD.WIDE.U32 R4, R19, R4, RZ ; /* 0x0000000413047225 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.IADD R7, R5, 0x1, R7 ; /* 0x0000000105077824 */
/* 0x000fe400078e0207 */
/*0510*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fcc00078e0004 */
/*0520*/ I2F.F64.S64 R6, R6 ; /* 0x0000000600067312 */
/* 0x000e220000301c00 */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fce00078e00ff */
/*0540*/ MUFU.RCP64H R5, R7 ; /* 0x0000000700057308 */
/* 0x001e240000001800 */
/*0550*/ DFMA R16, -R6, R4, 1 ; /* 0x3ff000000610742b */
/* 0x001e0c0000000104 */
/*0560*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0570*/ DFMA R16, R4, R16, R4 ; /* 0x000000100410722b */
/* 0x001e0c0000000004 */
/*0580*/ DFMA R4, -R6, R16, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c0000000110 */
/*0590*/ DFMA R4, R16, R4, R16 ; /* 0x000000041004722b */
/* 0x001fe20000000010 */
/*05a0*/ BSSY B0, 0x6b0 ; /* 0x0000010000007945 */
/* 0x000fe60003800000 */
/*05b0*/ DADD R2, R10, -R2 ; /* 0x000000000a027229 */
/* 0x004ecc0000000802 */
/*05c0*/ DADD R2, R2, -R12 ; /* 0x0000000002027229 */
/* 0x008f0c000000080c */
/*05d0*/ DADD R14, R2, R14 ; /* 0x00000000020e7229 */
/* 0x010e0c000000000e */
/*05e0*/ DMUL R2, R14, R4 ; /* 0x000000040e027228 */
/* 0x001e0c0000000000 */
/*05f0*/ DFMA R10, -R6, R2, R14 ; /* 0x00000002060a722b */
/* 0x001e0c000000010e */
/*0600*/ DFMA R2, R4, R10, R2 ; /* 0x0000000a0402722b */
/* 0x001e220000000002 */
/*0610*/ FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x000fd20003f2e200 */
/*0620*/ FFMA R4, RZ, R7, R3 ; /* 0x00000007ff047223 */
/* 0x001fca0000000003 */
/*0630*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fe20003f04200 */
/*0640*/ IMAD R10, R9, c[0x0][0x174], R0 ; /* 0x00005d00090a7a24 */
/* 0x000fd800078e0200 */
/*0650*/ @P0 BRA P1, 0x6a0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0660*/ MOV R0, 0x680 ; /* 0x0000068000007802 */
/* 0x000fe40000000f00 */
/*0670*/ CALL.REL.NOINC 0x6f0 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*0690*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*06a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc800078e00ff */
/*06c0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e020b */
/*06d0*/ STG.E.64 [R10.64], R2 ; /* 0x000000020a007986 */
/* 0x000fe2000c101b06 */
/*06e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06f0*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0700*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000f */
/*0710*/ LOP3.LUT R2, R7.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x040fe200078ec0ff */
/*0720*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*0730*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fe200078ec0ff */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000e */
/*0750*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*0760*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0770*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0780*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0790*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe200078ec0ff */
/*07a0*/ BSSY B1, 0xca0 ; /* 0x000004f000017945 */
/* 0x000fe40003800000 */
/*07b0*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*07c0*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*07d0*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fc600078e000b */
/*07e0*/ SEL R9, R12.reuse, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x040fe20004800000 */
/*07f0*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0800*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0810*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0820*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fe400078ef805 */
/*0830*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*0840*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0850*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*0860*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fc40005800000 */
/*0870*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0880*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe200078ef805 */
/*0890*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*08a0*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fc600078efcff */
/*08b0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e080000000012 */
/*08c0*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000e480000000814 */
/*08d0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e0c000000000e */
/*08e0*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x002fe200078ec0ff */
/*08f0*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0900*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fc60007ffe0ff */
/*0910*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0920*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc80003f04070 */
/*0930*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fe20000704470 */
/*0940*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*0950*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*0960*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0970*/ @P0 BRA 0xb40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0980*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*0990*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*09a0*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*09b0*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*09c0*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*09d0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*09e0*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0a00*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0a10*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*0a20*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*0a30*/ @P0 BRA 0xc90 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0a40*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*0a50*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*0a60*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*0a70*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0a80*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*0a90*/ @!P0 BRA 0xc90 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*0ab0*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0ad0*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0ae0*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fc600078e3cff */
/*0af0*/ IADD3 R2, -R11, -0x43300000, RZ ; /* 0xbcd000000b027810 */
/* 0x004fc80007ffe1ff */
/*0b00*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0b10*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*0b20*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0b30*/ BRA 0xc90 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0b40*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*0b50*/ @P0 BRA 0xc70 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0b60*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0b70*/ @P0 BRA 0xc40 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0b80*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0ba0*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0bb0*/ @!P0 BRA 0xc90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0bd0*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0be0*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0bf0*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0c00*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0c10*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0c20*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*0c30*/ BRA 0xc90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0c50*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0c60*/ BRA 0xc90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c70*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*0c80*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*0c90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ca0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0cb0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0cc0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff33002007950 */
/* 0x000fea0003c3ffff */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__device__ double efficientLocalMean_dev (const long x,const long y,const long k, double * input_img, int rowsize, int colsize) {
long k2 = k/2;
long dimx = rowsize;
long dimy = colsize;
//wanting average over area: (y-k2,x-k2) ... (y+k2-1, x+k2-1)
long starty = y-k2;
long startx = x-k2;
long stopy = y+k2-1;
long stopx = x+k2-1;
if (starty < 0) starty = 0;
if (startx < 0) startx = 0;
if (stopx > dimx-1) stopx = dimx-1;
if (stopy > dimy-1) stopy = dimy-1;
double unten, links, oben, obenlinks;
if (startx-1 < 0) links = 0;
else links = *(input_img+(stopy * dimx + startx-1));
if (starty-1 < 0) oben = 0;
else oben = *(input_img+((stopy-1) * dimx + startx));
if ((starty-1 < 0) || (startx-1 <0)) obenlinks = 0;
else obenlinks = *(input_img+((stopy-1) * dimx + startx-1));
unten = *(input_img+(stopy * dimx + startx));
long counter = (stopy-starty+1)*(stopx-startx+1);
return (unten-links-oben+obenlinks)/counter;
}
__global__ void process_coarseness_ak_pix(double * output_ak,double * input_img,int colsize, int rowsize,long lenOf_ak)
{
int index;
int y = threadIdx.x + blockIdx.x * blockDim.x;
int x = threadIdx.y + blockIdx.y * blockDim.y;
if(y < (colsize) && x < (rowsize))
{
index = y * rowsize + x ;
output_ak[index] = efficientLocalMean_dev(x,y,lenOf_ak,input_img,rowsize,colsize);
}
} | .file "tmpxft_00069d83_00000000-6_process_coarseness_ak_pix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22efficientLocalMean_devlllPdii
.type _Z22efficientLocalMean_devlllPdii, @function
_Z22efficientLocalMean_devlllPdii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z22efficientLocalMean_devlllPdii, .-_Z22efficientLocalMean_devlllPdii
.globl _Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil
.type _Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil, @function
_Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25process_coarseness_ak_pixPdS_iil(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil, .-_Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil
.globl _Z25process_coarseness_ak_pixPdS_iil
.type _Z25process_coarseness_ak_pixPdS_iil, @function
_Z25process_coarseness_ak_pixPdS_iil:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z25process_coarseness_ak_pixPdS_iil, .-_Z25process_coarseness_ak_pixPdS_iil
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25process_coarseness_ak_pixPdS_iil"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25process_coarseness_ak_pixPdS_iil(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__device__ double efficientLocalMean_dev (const long x,const long y,const long k, double * input_img, int rowsize, int colsize) {
long k2 = k/2;
long dimx = rowsize;
long dimy = colsize;
//wanting average over area: (y-k2,x-k2) ... (y+k2-1, x+k2-1)
long starty = y-k2;
long startx = x-k2;
long stopy = y+k2-1;
long stopx = x+k2-1;
if (starty < 0) starty = 0;
if (startx < 0) startx = 0;
if (stopx > dimx-1) stopx = dimx-1;
if (stopy > dimy-1) stopy = dimy-1;
double unten, links, oben, obenlinks;
if (startx-1 < 0) links = 0;
else links = *(input_img+(stopy * dimx + startx-1));
if (starty-1 < 0) oben = 0;
else oben = *(input_img+((stopy-1) * dimx + startx));
if ((starty-1 < 0) || (startx-1 <0)) obenlinks = 0;
else obenlinks = *(input_img+((stopy-1) * dimx + startx-1));
unten = *(input_img+(stopy * dimx + startx));
long counter = (stopy-starty+1)*(stopx-startx+1);
return (unten-links-oben+obenlinks)/counter;
}
__global__ void process_coarseness_ak_pix(double * output_ak,double * input_img,int colsize, int rowsize,long lenOf_ak)
{
int index;
int y = threadIdx.x + blockIdx.x * blockDim.x;
int x = threadIdx.y + blockIdx.y * blockDim.y;
if(y < (colsize) && x < (rowsize))
{
index = y * rowsize + x ;
output_ak[index] = efficientLocalMean_dev(x,y,lenOf_ak,input_img,rowsize,colsize);
}
} | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double efficientLocalMean_dev (const long x,const long y,const long k, double * input_img, int rowsize, int colsize) {
long k2 = k/2;
long dimx = rowsize;
long dimy = colsize;
//wanting average over area: (y-k2,x-k2) ... (y+k2-1, x+k2-1)
long starty = y-k2;
long startx = x-k2;
long stopy = y+k2-1;
long stopx = x+k2-1;
if (starty < 0) starty = 0;
if (startx < 0) startx = 0;
if (stopx > dimx-1) stopx = dimx-1;
if (stopy > dimy-1) stopy = dimy-1;
double unten, links, oben, obenlinks;
if (startx-1 < 0) links = 0;
else links = *(input_img+(stopy * dimx + startx-1));
if (starty-1 < 0) oben = 0;
else oben = *(input_img+((stopy-1) * dimx + startx));
if ((starty-1 < 0) || (startx-1 <0)) obenlinks = 0;
else obenlinks = *(input_img+((stopy-1) * dimx + startx-1));
unten = *(input_img+(stopy * dimx + startx));
long counter = (stopy-starty+1)*(stopx-startx+1);
return (unten-links-oben+obenlinks)/counter;
}
__global__ void process_coarseness_ak_pix(double * output_ak,double * input_img,int colsize, int rowsize,long lenOf_ak)
{
int index;
int y = threadIdx.x + blockIdx.x * blockDim.x;
int x = threadIdx.y + blockIdx.y * blockDim.y;
if(y < (colsize) && x < (rowsize))
{
index = y * rowsize + x ;
output_ak[index] = efficientLocalMean_dev(x,y,lenOf_ak,input_img,rowsize,colsize);
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double efficientLocalMean_dev (const long x,const long y,const long k, double * input_img, int rowsize, int colsize) {
long k2 = k/2;
long dimx = rowsize;
long dimy = colsize;
//wanting average over area: (y-k2,x-k2) ... (y+k2-1, x+k2-1)
long starty = y-k2;
long startx = x-k2;
long stopy = y+k2-1;
long stopx = x+k2-1;
if (starty < 0) starty = 0;
if (startx < 0) startx = 0;
if (stopx > dimx-1) stopx = dimx-1;
if (stopy > dimy-1) stopy = dimy-1;
double unten, links, oben, obenlinks;
if (startx-1 < 0) links = 0;
else links = *(input_img+(stopy * dimx + startx-1));
if (starty-1 < 0) oben = 0;
else oben = *(input_img+((stopy-1) * dimx + startx));
if ((starty-1 < 0) || (startx-1 <0)) obenlinks = 0;
else obenlinks = *(input_img+((stopy-1) * dimx + startx-1));
unten = *(input_img+(stopy * dimx + startx));
long counter = (stopy-starty+1)*(stopx-startx+1);
return (unten-links-oben+obenlinks)/counter;
}
__global__ void process_coarseness_ak_pix(double * output_ak,double * input_img,int colsize, int rowsize,long lenOf_ak)
{
int index;
int y = threadIdx.x + blockIdx.x * blockDim.x;
int x = threadIdx.y + blockIdx.y * blockDim.y;
if(y < (colsize) && x < (rowsize))
{
index = y * rowsize + x ;
output_ak[index] = efficientLocalMean_dev(x,y,lenOf_ak,input_img,rowsize,colsize);
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25process_coarseness_ak_pixPdS_iil
.globl _Z25process_coarseness_ak_pixPdS_iil
.p2align 8
.type _Z25process_coarseness_ak_pixPdS_iil,@function
_Z25process_coarseness_ak_pixPdS_iil:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[10:11], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s4, s11
v_cmp_gt_i32_e32 vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x8
v_ashrrev_i32_e32 v10, 31, v0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s3, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s2, s5
s_addc_u32 s3, s3, 0
s_ashr_i32 s11, s10, 31
s_ashr_i64 s[6:7], s[2:3], 1
s_ashr_i32 s5, s4, 31
v_add_co_u32 v3, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v10, vcc_lo
v_sub_co_u32 v7, vcc_lo, v1, s6
v_subrev_co_ci_u32_e32 v8, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_gt_i64_e32 vcc_lo, s[10:11], v[3:4]
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_cmp_lt_i64_e64 s2, 0, v[7:8]
v_cndmask_b32_e32 v13, s11, v4, vcc_lo
v_cndmask_b32_e32 v14, s10, v3, vcc_lo
v_cmp_gt_i64_e32 vcc_lo, 1, v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, 0, v8, s2
v_cndmask_b32_e64 v3, 0, v7, s2
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
v_add_co_u32 v15, s3, v14, -1
v_add_co_ci_u32_e64 v16, s3, -1, v13, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v16, s4
v_mul_lo_u32 v11, v15, s5
v_mad_u64_u32 v[7:8], null, v15, s4, 0
v_add3_u32 v8, v8, v11, v9
v_lshlrev_b64 v[11:12], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v7, s2, s8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v8, s2, s9, v8, s2
v_add_co_u32 v7, s2, v7, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s2, v8, v12, s2
global_load_b64 v[7:8], v[7:8], off offset:-8
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
v_sub_co_u32 v9, s2, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e64 v10, s2, s7, v10, s2
s_mov_b32 s10, exec_lo
v_cmp_gt_i64_e64 s2, 1, v[9:10]
v_cmpx_lt_i64_e32 0, v[9:10]
s_cbranch_execz .LBB0_5
v_add_co_u32 v11, s3, v14, -2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v5, s3, -1, v13, s3
v_mul_lo_u32 v17, v11, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v12, v5, s4
v_mad_u64_u32 v[5:6], null, v11, s4, 0
v_add3_u32 v6, v6, v17, v12
v_lshlrev_b64 v[11:12], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_co_u32 v5, s3, s8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v6, s3, s9, v6, s3
v_add_co_u32 v5, s3, v5, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s3, v6, v12, s3
global_load_b64 v[5:6], v[5:6], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
s_or_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s2, -1
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_7
v_add_co_u32 v17, vcc_lo, v14, -2
v_add_co_ci_u32_e32 v11, vcc_lo, -1, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v19, v17, s5
v_mul_lo_u32 v18, v11, s4
v_mad_u64_u32 v[11:12], null, v17, s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v12, v12, v19, v18
v_lshlrev_b64 v[17:18], 3, v[3:4]
v_lshlrev_b64 v[11:12], 3, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, v11, v17
v_add_co_ci_u32_e32 v12, vcc_lo, v12, v18, vcc_lo
global_load_b64 v[11:12], v[11:12], off offset:-8
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
v_mul_lo_u32 v18, v16, s4
v_mul_lo_u32 v19, v15, s5
v_mad_u64_u32 v[16:17], null, v15, s4, 0
v_cmp_lt_i64_e64 s2, 0, v[9:10]
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, 0, v9, s2
v_add3_u32 v17, v17, v19, v18
v_cndmask_b32_e64 v10, 0, v10, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[15:16], 3, v[16:17]
v_lshlrev_b64 v[17:18], 3, v[3:4]
v_add_co_u32 v15, vcc_lo, s8, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, v15, v17
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v16, vcc_lo, v16, v18, vcc_lo
v_add_co_u32 v17, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v2, vcc_lo
global_load_b64 v[15:16], v[15:16], off
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[17:18]
v_cndmask_b32_e32 v17, s4, v17, vcc_lo
v_cndmask_b32_e32 v18, s5, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v17, vcc_lo, v17, v3
v_sub_co_ci_u32_e32 v3, vcc_lo, v18, v4, vcc_lo
v_sub_co_u32 v9, vcc_lo, v14, v9
v_sub_co_ci_u32_e32 v4, vcc_lo, v13, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v10, v3, v9
v_mul_lo_u32 v13, v17, v4
v_mad_u64_u32 v[3:4], null, v17, v9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v4, v13, v10
v_cvt_f64_i32_e32 v[9:10], v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_u32_e32 v[3:4], v3
v_ldexp_f64 v[9:10], v[9:10], 32
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[9:10], v[3:4]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[15:16], -v[7:8]
v_add_f64 v[5:6], v[7:8], -v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[11:12], v[5:6]
v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_div_scale_f64 v[11:12], vcc_lo, v[5:6], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[11:12], v[9:10]
v_fma_f64 v[7:8], -v[7:8], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[13:14]
v_div_fixup_f64 v[3:4], v[7:8], v[3:4], v[5:6]
v_mad_u64_u32 v[5:6], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25process_coarseness_ak_pixPdS_iil
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25process_coarseness_ak_pixPdS_iil, .Lfunc_end0-_Z25process_coarseness_ak_pixPdS_iil
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25process_coarseness_ak_pixPdS_iil
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25process_coarseness_ak_pixPdS_iil.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__device__ double efficientLocalMean_dev (const long x,const long y,const long k, double * input_img, int rowsize, int colsize) {
long k2 = k/2;
long dimx = rowsize;
long dimy = colsize;
//wanting average over area: (y-k2,x-k2) ... (y+k2-1, x+k2-1)
long starty = y-k2;
long startx = x-k2;
long stopy = y+k2-1;
long stopx = x+k2-1;
if (starty < 0) starty = 0;
if (startx < 0) startx = 0;
if (stopx > dimx-1) stopx = dimx-1;
if (stopy > dimy-1) stopy = dimy-1;
double unten, links, oben, obenlinks;
if (startx-1 < 0) links = 0;
else links = *(input_img+(stopy * dimx + startx-1));
if (starty-1 < 0) oben = 0;
else oben = *(input_img+((stopy-1) * dimx + startx));
if ((starty-1 < 0) || (startx-1 <0)) obenlinks = 0;
else obenlinks = *(input_img+((stopy-1) * dimx + startx-1));
unten = *(input_img+(stopy * dimx + startx));
long counter = (stopy-starty+1)*(stopx-startx+1);
return (unten-links-oben+obenlinks)/counter;
}
__global__ void process_coarseness_ak_pix(double * output_ak,double * input_img,int colsize, int rowsize,long lenOf_ak)
{
int index;
int y = threadIdx.x + blockIdx.x * blockDim.x;
int x = threadIdx.y + blockIdx.y * blockDim.y;
if(y < (colsize) && x < (rowsize))
{
index = y * rowsize + x ;
output_ak[index] = efficientLocalMean_dev(x,y,lenOf_ak,input_img,rowsize,colsize);
}
} | .text
.file "process_coarseness_ak_pix.hip"
.globl _Z40__device_stub__process_coarseness_ak_pixPdS_iil # -- Begin function _Z40__device_stub__process_coarseness_ak_pixPdS_iil
.p2align 4, 0x90
.type _Z40__device_stub__process_coarseness_ak_pixPdS_iil,@function
_Z40__device_stub__process_coarseness_ak_pixPdS_iil: # @_Z40__device_stub__process_coarseness_ak_pixPdS_iil
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25process_coarseness_ak_pixPdS_iil, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__process_coarseness_ak_pixPdS_iil, .Lfunc_end0-_Z40__device_stub__process_coarseness_ak_pixPdS_iil
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25process_coarseness_ak_pixPdS_iil, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25process_coarseness_ak_pixPdS_iil,@object # @_Z25process_coarseness_ak_pixPdS_iil
.section .rodata,"a",@progbits
.globl _Z25process_coarseness_ak_pixPdS_iil
.p2align 3, 0x0
_Z25process_coarseness_ak_pixPdS_iil:
.quad _Z40__device_stub__process_coarseness_ak_pixPdS_iil
.size _Z25process_coarseness_ak_pixPdS_iil, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25process_coarseness_ak_pixPdS_iil"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__process_coarseness_ak_pixPdS_iil
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25process_coarseness_ak_pixPdS_iil
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z25process_coarseness_ak_pixPdS_iil
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002600 */
/*0020*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e280000002200 */
/*0030*/ S2R R9, SR_CTAID.X ; /* 0x0000000000097919 */
/* 0x000e680000002500 */
/*0040*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x001fca00078e0203 */
/*0060*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x174], PT ; /* 0x00005d0000007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R9, R9, c[0x0][0x0], R2 ; /* 0x0000000009097a24 */
/* 0x002fca00078e0202 */
/*0080*/ ISETP.GE.OR P0, PT, R9, c[0x0][0x170], P0 ; /* 0x00005c0009007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ IMAD.MOV.U32 R20, RZ, RZ, c[0x0][0x17c] ; /* 0x00005f00ff147624 */
/* 0x000fe200078e00ff */
/*00b0*/ ULDC.64 UR6, c[0x0][0x170] ; /* 0x00005c0000067ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ SHF.R.S32.HI R18, RZ, 0x1f, R0 ; /* 0x0000001fff127819 */
/* 0x000fe20000011400 */
/*00d0*/ UIADD3 UR8, UP0, UR6, -0x1, URZ ; /* 0xffffffff06087890 */
/* 0x000fe2000ff1e03f */
/*00e0*/ SHF.R.S32.HI R2, RZ, 0x1f, R9 ; /* 0x0000001fff027819 */
/* 0x000fe20000011409 */
/*00f0*/ USHF.R.S32.HI UR4, URZ, 0x1f, UR7 ; /* 0x0000001f3f047899 */
/* 0x000fe20008011407 */
/*0100*/ LEA.HI R20, P0, R20, c[0x0][0x178], RZ, 0x1 ; /* 0x00005e0014147a11 */
/* 0x000fe200078108ff */
/*0110*/ ULEA.HI.X.SX32 UR5, UR6, 0xffffffff, 0x1, UP0 ; /* 0xffffffff06057891 */
/* 0x000fc600080f0e3f */
/*0120*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*0130*/ IMAD.X R21, RZ, RZ, c[0x0][0x17c], P0 ; /* 0x00005f00ff157624 */
/* 0x000fca00000e06ff */
/*0140*/ SHF.R.S64 R20, R20, 0x1, R21.reuse ; /* 0x0000000114147819 */
/* 0x100fe40000001015 */
/*0150*/ SHF.R.S32.HI R21, RZ, 0x1, R21 ; /* 0x00000001ff157819 */
/* 0x000fe40000011415 */
/*0160*/ IADD3 R4, P2, R0, -R20, RZ ; /* 0x8000001400047210 */
/* 0x000fe40007f5e0ff */
/*0170*/ IADD3 R19, P1, P3, R9, -0x1, R20 ; /* 0xffffffff09137810 */
/* 0x000fc60007b3e014 */
/*0180*/ IMAD.X R3, R18, 0x1, ~R21.reuse, P2 ; /* 0x0000000112037824 */
/* 0x100fe200010e0e15 */
/*0190*/ ISETP.LT.U32.AND P0, PT, R19, UR8, PT ; /* 0x0000000813007c0c */
/* 0x000fe4000bf01070 */
/*01a0*/ IADD3.X R8, R2, -0x1, R21, P1, P3 ; /* 0xffffffff02087810 */
/* 0x000fe40000fe6415 */
/*01b0*/ ISETP.GT.U32.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720c */
/* 0x000fe40003f24070 */
/*01c0*/ ISETP.LT.AND.EX P2, PT, R8, UR5, PT, P0 ; /* 0x0000000508007c0c */
/* 0x000fe4000bf41300 */
/*01d0*/ ISETP.GT.AND.EX P0, PT, R3, RZ, PT, P1 ; /* 0x000000ff0300720c */
/* 0x000fe40003f04310 */
/*01e0*/ IADD3 R22, P1, R9, -R20, RZ ; /* 0x8000001409167210 */
/* 0x000fc40007f3e0ff */
/*01f0*/ SEL R19, R19, UR8, P2 ; /* 0x0000000813137c07 */
/* 0x000fe40009000000 */
/*0200*/ SEL R8, R8, UR5, P2 ; /* 0x0000000508087c07 */
/* 0x000fe20009000000 */
/*0210*/ IMAD.X R23, R2, 0x1, ~R21, P1 ; /* 0x0000000102177824 */
/* 0x000fe200008e0e15 */
/*0220*/ SEL R4, R4, RZ, P0 ; /* 0x000000ff04047207 */
/* 0x000fe40000000000 */
/*0230*/ SEL R5, R3, RZ, P0 ; /* 0x000000ff03057207 */
/* 0x000fe20000000000 */
/*0240*/ IMAD R2, R8, c[0x0][0x174], RZ ; /* 0x00005d0008027a24 */
/* 0x000fe200078e02ff */
/*0250*/ IADD3 R7, P0, R19.reuse, -0x1, RZ ; /* 0xffffffff13077810 */
/* 0x040fe40007f1e0ff */
/*0260*/ ISETP.GT.U32.AND P1, PT, R22, RZ, PT ; /* 0x000000ff1600720c */
/* 0x000fe20003f24070 */
/*0270*/ IMAD R13, R19.reuse, UR4, R2 ; /* 0x00000004130d7c24 */
/* 0x040fe2000f8e0202 */
/*0280*/ IADD3.X R6, R8, -0x1, RZ, P0, !PT ; /* 0xffffffff08067810 */
/* 0x000fe200007fe4ff */
/*0290*/ IMAD.WIDE.U32 R2, R19, c[0x0][0x174], R4 ; /* 0x00005d0013027a25 */
/* 0x000fe200078e0004 */
/*02a0*/ ISETP.GT.AND.EX P1, PT, R23, RZ, PT, P1 ; /* 0x000000ff1700720c */
/* 0x000fc40003f24310 */
/*02b0*/ ISETP.GE.U32.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f06070 */
/*02c0*/ IMAD R6, R6, c[0x0][0x174], RZ ; /* 0x00005d0006067a24 */
/* 0x000fe200078e02ff */
/*02d0*/ SEL R22, R22, RZ, P1 ; /* 0x000000ff16167207 */
/* 0x000fe20000800000 */
/*02e0*/ IMAD.IADD R3, R3, 0x1, R13 ; /* 0x0000000103037824 */
/* 0x000fe200078e020d */
/*02f0*/ ISETP.GE.AND.EX P0, PT, R5, RZ, PT, P0 ; /* 0x000000ff0500720c */
/* 0x000fe20003f06300 */
/*0300*/ IMAD.WIDE.U32 R10, R7, c[0x0][0x174], R4 ; /* 0x00005d00070a7a25 */
/* 0x000fe200078e0004 */
/*0310*/ SEL R23, R23, RZ, P1 ; /* 0x000000ff17177207 */
/* 0x000fe40000800000 */
/*0320*/ LEA R16, P2, R2, c[0x0][0x168], 0x3 ; /* 0x00005a0002107a11 */
/* 0x000fe200078418ff */
/*0330*/ IMAD R7, R7, UR4, R6 ; /* 0x0000000407077c24 */
/* 0x000fe2000f8e0206 */
/*0340*/ ISETP.GE.U32.AND P1, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fc40003f26070 */
/*0350*/ LEA.HI.X R17, R2, c[0x0][0x16c], R3, 0x3, P2 ; /* 0x00005b0002117a11 */
/* 0x000fe200010f1c03 */
/*0360*/ IMAD.IADD R7, R11, 0x1, R7 ; /* 0x000000010b077824 */
/* 0x000fe200078e0207 */
/*0370*/ ISETP.GE.AND.EX P1, PT, R23.reuse, RZ, PT, P1 ; /* 0x000000ff1700720c */
/* 0x040fe20003f26310 */
/*0380*/ CS2R R2, SRZ ; /* 0x0000000000027805 */
/* 0x000fe2000001ff00 */
/*0390*/ LEA R6, P3, R10, c[0x0][0x168], 0x3 ; /* 0x00005a000a067a11 */
/* 0x000fe400078618ff */
/*03a0*/ ISETP.LT.U32.AND P2, PT, R22, 0x1, PT ; /* 0x000000011600780c */
/* 0x000fe20003f41070 */
/*03b0*/ CS2R R12, SRZ ; /* 0x00000000000c7805 */
/* 0x000fe2000001ff00 */
/*03c0*/ LEA.HI.X R7, R10, c[0x0][0x16c], R7, 0x3, P3 ; /* 0x00005b000a077a11 */
/* 0x000fe200018f1c07 */
/*03d0*/ @P0 LDG.E.64 R2, [R16.64+-0x8] ; /* 0xfffff80610020981 */
/* 0x0000a2000c1e1b00 */
/*03e0*/ ISETP.LT.OR.EX P2, PT, R23, RZ, !P0, P2 ; /* 0x000000ff1700720c */
/* 0x000fc60004741720 */
/*03f0*/ LDG.E.64 R10, [R16.64] ; /* 0x00000006100a7981 */
/* 0x0000a2000c1e1b00 */
/*0400*/ CS2R R14, SRZ ; /* 0x00000000000e7805 */
/* 0x000fc6000001ff00 */
/*0410*/ @P1 LDG.E.64 R12, [R6.64] ; /* 0x00000006060c1981 */
/* 0x0002ec000c1e1b00 */
/*0420*/ @!P2 LDG.E.64 R14, [R6.64+-0x8] ; /* 0xfffff806060ea981 */
/* 0x000322000c1e1b00 */
/*0430*/ IADD3 R20, P0, R0, R20, RZ ; /* 0x0000001400147210 */
/* 0x000fca0007f1e0ff */
/*0440*/ IMAD.X R18, R18, 0x1, R21, P0 ; /* 0x0000000112127824 */
/* 0x000fe200000e0615 */
/*0450*/ ISETP.LT.U32.AND P0, PT, R20, c[0x0][0x174], PT ; /* 0x00005d0014007a0c */
/* 0x000fc80003f01070 */
/*0460*/ ISETP.LT.AND.EX P0, PT, R18, UR4, PT, P0 ; /* 0x0000000412007c0c */
/* 0x000fe4000bf01300 */
/*0470*/ IADD3 R19, P1, P2, R19, 0x1, -R22 ; /* 0x0000000113137810 */
/* 0x000fe40007a3e816 */
/*0480*/ SEL R21, R20, c[0x0][0x174], P0 ; /* 0x00005d0014157a07 */
/* 0x000fe40000000000 */
/*0490*/ IADD3.X R23, R8, RZ, ~R23, P1, P2 ; /* 0x000000ff08177210 */
/* 0x000fe40000fe4c17 */
/*04a0*/ IADD3 R4, P3, R21, -R4, RZ ; /* 0x8000000415047210 */
/* 0x000fe40007f7e0ff */
/*04b0*/ SEL R17, R18, UR4, P0 ; /* 0x0000000412117c07 */
/* 0x001fc60008000000 */
/*04c0*/ IMAD R6, R23, R4, RZ ; /* 0x0000000417067224 */
/* 0x002fe400078e02ff */
/*04d0*/ IMAD.X R5, R17, 0x1, ~R5, P3 ; /* 0x0000000111057824 */
/* 0x000fc800018e0e05 */
/*04e0*/ IMAD R7, R5, R19, R6 ; /* 0x0000001305077224 */
/* 0x000fe400078e0206 */
/*04f0*/ IMAD.WIDE.U32 R4, R19, R4, RZ ; /* 0x0000000413047225 */
/* 0x000fc800078e00ff */
/*0500*/ IMAD.IADD R7, R5, 0x1, R7 ; /* 0x0000000105077824 */
/* 0x000fe400078e0207 */
/*0510*/ IMAD.MOV.U32 R6, RZ, RZ, R4 ; /* 0x000000ffff067224 */
/* 0x000fcc00078e0004 */
/*0520*/ I2F.F64.S64 R6, R6 ; /* 0x0000000600067312 */
/* 0x000e220000301c00 */
/*0530*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fce00078e00ff */
/*0540*/ MUFU.RCP64H R5, R7 ; /* 0x0000000700057308 */
/* 0x001e240000001800 */
/*0550*/ DFMA R16, -R6, R4, 1 ; /* 0x3ff000000610742b */
/* 0x001e0c0000000104 */
/*0560*/ DFMA R16, R16, R16, R16 ; /* 0x000000101010722b */
/* 0x001e0c0000000010 */
/*0570*/ DFMA R16, R4, R16, R4 ; /* 0x000000100410722b */
/* 0x001e0c0000000004 */
/*0580*/ DFMA R4, -R6, R16, 1 ; /* 0x3ff000000604742b */
/* 0x001e0c0000000110 */
/*0590*/ DFMA R4, R16, R4, R16 ; /* 0x000000041004722b */
/* 0x001fe20000000010 */
/*05a0*/ BSSY B0, 0x6b0 ; /* 0x0000010000007945 */
/* 0x000fe60003800000 */
/*05b0*/ DADD R2, R10, -R2 ; /* 0x000000000a027229 */
/* 0x004ecc0000000802 */
/*05c0*/ DADD R2, R2, -R12 ; /* 0x0000000002027229 */
/* 0x008f0c000000080c */
/*05d0*/ DADD R14, R2, R14 ; /* 0x00000000020e7229 */
/* 0x010e0c000000000e */
/*05e0*/ DMUL R2, R14, R4 ; /* 0x000000040e027228 */
/* 0x001e0c0000000000 */
/*05f0*/ DFMA R10, -R6, R2, R14 ; /* 0x00000002060a722b */
/* 0x001e0c000000010e */
/*0600*/ DFMA R2, R4, R10, R2 ; /* 0x0000000a0402722b */
/* 0x001e220000000002 */
/*0610*/ FSETP.GEU.AND P1, PT, |R15|, 6.5827683646048100446e-37, PT ; /* 0x036000000f00780b */
/* 0x000fd20003f2e200 */
/*0620*/ FFMA R4, RZ, R7, R3 ; /* 0x00000007ff047223 */
/* 0x001fca0000000003 */
/*0630*/ FSETP.GT.AND P0, PT, |R4|, 1.469367938527859385e-39, PT ; /* 0x001000000400780b */
/* 0x000fe20003f04200 */
/*0640*/ IMAD R10, R9, c[0x0][0x174], R0 ; /* 0x00005d00090a7a24 */
/* 0x000fd800078e0200 */
/*0650*/ @P0 BRA P1, 0x6a0 ; /* 0x0000004000000947 */
/* 0x000fea0000800000 */
/*0660*/ MOV R0, 0x680 ; /* 0x0000068000007802 */
/* 0x000fe40000000f00 */
/*0670*/ CALL.REL.NOINC 0x6f0 ; /* 0x0000007000007944 */
/* 0x000fea0003c00000 */
/*0680*/ IMAD.MOV.U32 R2, RZ, RZ, R12 ; /* 0x000000ffff027224 */
/* 0x000fe400078e000c */
/*0690*/ IMAD.MOV.U32 R3, RZ, RZ, R13 ; /* 0x000000ffff037224 */
/* 0x000fe400078e000d */
/*06a0*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*06b0*/ IMAD.MOV.U32 R11, RZ, RZ, 0x8 ; /* 0x00000008ff0b7424 */
/* 0x000fc800078e00ff */
/*06c0*/ IMAD.WIDE R10, R10, R11, c[0x0][0x160] ; /* 0x000058000a0a7625 */
/* 0x000fca00078e020b */
/*06d0*/ STG.E.64 [R10.64], R2 ; /* 0x000000020a007986 */
/* 0x000fe2000c101b06 */
/*06e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06f0*/ FSETP.GEU.AND P0, PT, |R7|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000700780b */
/* 0x040fe20003f0e200 */
/*0700*/ IMAD.MOV.U32 R5, RZ, RZ, R15 ; /* 0x000000ffff057224 */
/* 0x000fe200078e000f */
/*0710*/ LOP3.LUT R2, R7.reuse, 0x800fffff, RZ, 0xc0, !PT ; /* 0x800fffff07027812 */
/* 0x040fe200078ec0ff */
/*0720*/ IMAD.MOV.U32 R12, RZ, RZ, 0x1ca00000 ; /* 0x1ca00000ff0c7424 */
/* 0x000fe200078e00ff */
/*0730*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fe200078ec0ff */
/*0740*/ IMAD.MOV.U32 R4, RZ, RZ, R14 ; /* 0x000000ffff047224 */
/* 0x000fe200078e000e */
/*0750*/ FSETP.GEU.AND P2, PT, |R5|.reuse, 1.469367938527859385e-39, PT ; /* 0x001000000500780b */
/* 0x040fe20003f4e200 */
/*0760*/ IMAD.MOV.U32 R14, RZ, RZ, 0x1 ; /* 0x00000001ff0e7424 */
/* 0x000fe200078e00ff */
/*0770*/ LOP3.LUT R3, R2, 0x3ff00000, RZ, 0xfc, !PT ; /* 0x3ff0000002037812 */
/* 0x000fe200078efcff */
/*0780*/ IMAD.MOV.U32 R2, RZ, RZ, R6 ; /* 0x000000ffff027224 */
/* 0x000fe200078e0006 */
/*0790*/ LOP3.LUT R11, R5, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff00000050b7812 */
/* 0x000fe200078ec0ff */
/*07a0*/ BSSY B1, 0xca0 ; /* 0x000004f000017945 */
/* 0x000fe40003800000 */
/*07b0*/ @!P0 DMUL R2, R6, 8.98846567431157953865e+307 ; /* 0x7fe0000006028828 */
/* 0x000e220000000000 */
/*07c0*/ ISETP.GE.U32.AND P1, PT, R11, R16, PT ; /* 0x000000100b00720c */
/* 0x000fe20003f26070 */
/*07d0*/ IMAD.MOV.U32 R17, RZ, RZ, R11 ; /* 0x000000ffff117224 */
/* 0x000fc600078e000b */
/*07e0*/ SEL R9, R12.reuse, 0x63400000, !P1 ; /* 0x634000000c097807 */
/* 0x040fe20004800000 */
/*07f0*/ MUFU.RCP64H R15, R3 ; /* 0x00000003000f7308 */
/* 0x001e220000001800 */
/*0800*/ @!P2 LOP3.LUT R8, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000708a812 */
/* 0x000fe200078ec0ff */
/*0810*/ @!P2 IMAD.MOV.U32 R20, RZ, RZ, RZ ; /* 0x000000ffff14a224 */
/* 0x000fe200078e00ff */
/*0820*/ LOP3.LUT R9, R9, 0x800fffff, R5, 0xf8, !PT ; /* 0x800fffff09097812 */
/* 0x000fe400078ef805 */
/*0830*/ @!P2 ISETP.GE.U32.AND P3, PT, R11, R8, PT ; /* 0x000000080b00a20c */
/* 0x000fe20003f66070 */
/*0840*/ IMAD.MOV.U32 R8, RZ, RZ, R4 ; /* 0x000000ffff087224 */
/* 0x000fe200078e0004 */
/*0850*/ @!P0 LOP3.LUT R16, R3, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000003108812 */
/* 0x000fe400078ec0ff */
/*0860*/ @!P2 SEL R13, R12, 0x63400000, !P3 ; /* 0x634000000c0da807 */
/* 0x000fc40005800000 */
/*0870*/ IADD3 R22, R16, -0x1, RZ ; /* 0xffffffff10167810 */
/* 0x000fe40007ffe0ff */
/*0880*/ @!P2 LOP3.LUT R13, R13, 0x80000000, R5, 0xf8, !PT ; /* 0x800000000d0da812 */
/* 0x000fe200078ef805 */
/*0890*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*08a0*/ @!P2 LOP3.LUT R21, R13, 0x100000, RZ, 0xfc, !PT ; /* 0x001000000d15a812 */
/* 0x000fc600078efcff */
/*08b0*/ DFMA R18, R18, R18, R18 ; /* 0x000000121212722b */
/* 0x001e080000000012 */
/*08c0*/ @!P2 DFMA R8, R8, 2, -R20 ; /* 0x400000000808a82b */
/* 0x000e480000000814 */
/*08d0*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e0c000000000e */
/*08e0*/ @!P2 LOP3.LUT R17, R9, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff000000911a812 */
/* 0x002fe200078ec0ff */
/*08f0*/ DFMA R18, R14, -R2, 1 ; /* 0x3ff000000e12742b */
/* 0x001e060000000802 */
/*0900*/ IADD3 R13, R17, -0x1, RZ ; /* 0xffffffff110d7810 */
/* 0x000fc60007ffe0ff */
/*0910*/ DFMA R14, R14, R18, R14 ; /* 0x000000120e0e722b */
/* 0x001e22000000000e */
/*0920*/ ISETP.GT.U32.AND P0, PT, R13, 0x7feffffe, PT ; /* 0x7feffffe0d00780c */
/* 0x000fc80003f04070 */
/*0930*/ ISETP.GT.U32.OR P0, PT, R22, 0x7feffffe, P0 ; /* 0x7feffffe1600780c */
/* 0x000fe20000704470 */
/*0940*/ DMUL R18, R14, R8 ; /* 0x000000080e127228 */
/* 0x001e0c0000000000 */
/*0950*/ DFMA R20, R18, -R2, R8 ; /* 0x800000021214722b */
/* 0x001e0c0000000008 */
/*0960*/ DFMA R14, R14, R20, R18 ; /* 0x000000140e0e722b */
/* 0x0010620000000012 */
/*0970*/ @P0 BRA 0xb40 ; /* 0x000001c000000947 */
/* 0x000fea0003800000 */
/*0980*/ LOP3.LUT R16, R7, 0x7ff00000, RZ, 0xc0, !PT ; /* 0x7ff0000007107812 */
/* 0x000fc800078ec0ff */
/*0990*/ ISETP.GE.U32.AND P0, PT, R11.reuse, R16, PT ; /* 0x000000100b00720c */
/* 0x040fe20003f06070 */
/*09a0*/ IMAD.IADD R4, R11, 0x1, -R16 ; /* 0x000000010b047824 */
/* 0x000fc600078e0a10 */
/*09b0*/ SEL R11, R12, 0x63400000, !P0 ; /* 0x634000000c0b7807 */
/* 0x000fe40004000000 */
/*09c0*/ IMNMX R4, R4, -0x46a00000, !PT ; /* 0xb960000004047817 */
/* 0x000fc80007800200 */
/*09d0*/ IMNMX R4, R4, 0x46a00000, PT ; /* 0x46a0000004047817 */
/* 0x000fca0003800200 */
/*09e0*/ IMAD.IADD R11, R4, 0x1, -R11 ; /* 0x00000001040b7824 */
/* 0x000fe400078e0a0b */
/*09f0*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fc600078e00ff */
/*0a00*/ IADD3 R5, R11, 0x7fe00000, RZ ; /* 0x7fe000000b057810 */
/* 0x000fcc0007ffe0ff */
/*0a10*/ DMUL R12, R14, R4 ; /* 0x000000040e0c7228 */
/* 0x002e540000000000 */
/*0a20*/ FSETP.GTU.AND P0, PT, |R13|, 1.469367938527859385e-39, PT ; /* 0x001000000d00780b */
/* 0x002fda0003f0c200 */
/*0a30*/ @P0 BRA 0xc90 ; /* 0x0000025000000947 */
/* 0x000fea0003800000 */
/*0a40*/ DFMA R2, R14, -R2, R8 ; /* 0x800000020e02722b */
/* 0x000e620000000008 */
/*0a50*/ IMAD.MOV.U32 R4, RZ, RZ, RZ ; /* 0x000000ffff047224 */
/* 0x000fd200078e00ff */
/*0a60*/ FSETP.NEU.AND P0, PT, R3.reuse, RZ, PT ; /* 0x000000ff0300720b */
/* 0x042fe40003f0d000 */
/*0a70*/ LOP3.LUT R7, R3, 0x80000000, R7, 0x48, !PT ; /* 0x8000000003077812 */
/* 0x000fc800078e4807 */
/*0a80*/ LOP3.LUT R5, R7, R5, RZ, 0xfc, !PT ; /* 0x0000000507057212 */
/* 0x000fce00078efcff */
/*0a90*/ @!P0 BRA 0xc90 ; /* 0x000001f000008947 */
/* 0x000fea0003800000 */
/*0aa0*/ IMAD.MOV R3, RZ, RZ, -R11 ; /* 0x000000ffff037224 */
/* 0x000fe200078e0a0b */
/*0ab0*/ DMUL.RP R4, R14, R4 ; /* 0x000000040e047228 */
/* 0x000e620000008000 */
/*0ac0*/ IMAD.MOV.U32 R2, RZ, RZ, RZ ; /* 0x000000ffff027224 */
/* 0x000fcc00078e00ff */
/*0ad0*/ DFMA R2, R12, -R2, R14 ; /* 0x800000020c02722b */
/* 0x000e86000000000e */
/*0ae0*/ LOP3.LUT R7, R5, R7, RZ, 0x3c, !PT ; /* 0x0000000705077212 */
/* 0x002fc600078e3cff */
/*0af0*/ IADD3 R2, -R11, -0x43300000, RZ ; /* 0xbcd000000b027810 */
/* 0x004fc80007ffe1ff */
/*0b00*/ FSETP.NEU.AND P0, PT, |R3|, R2, PT ; /* 0x000000020300720b */
/* 0x000fc80003f0d200 */
/*0b10*/ FSEL R12, R4, R12, !P0 ; /* 0x0000000c040c7208 */
/* 0x000fe40004000000 */
/*0b20*/ FSEL R13, R7, R13, !P0 ; /* 0x0000000d070d7208 */
/* 0x000fe20004000000 */
/*0b30*/ BRA 0xc90 ; /* 0x0000015000007947 */
/* 0x000fea0003800000 */
/*0b40*/ DSETP.NAN.AND P0, PT, R4, R4, PT ; /* 0x000000040400722a */
/* 0x000e9c0003f08000 */
/*0b50*/ @P0 BRA 0xc70 ; /* 0x0000011000000947 */
/* 0x004fea0003800000 */
/*0b60*/ DSETP.NAN.AND P0, PT, R6, R6, PT ; /* 0x000000060600722a */
/* 0x000e9c0003f08000 */
/*0b70*/ @P0 BRA 0xc40 ; /* 0x000000c000000947 */
/* 0x004fea0003800000 */
/*0b80*/ ISETP.NE.AND P0, PT, R17, R16, PT ; /* 0x000000101100720c */
/* 0x000fe20003f05270 */
/*0b90*/ IMAD.MOV.U32 R12, RZ, RZ, 0x0 ; /* 0x00000000ff0c7424 */
/* 0x000fe400078e00ff */
/*0ba0*/ IMAD.MOV.U32 R13, RZ, RZ, -0x80000 ; /* 0xfff80000ff0d7424 */
/* 0x000fd400078e00ff */
/*0bb0*/ @!P0 BRA 0xc90 ; /* 0x000000d000008947 */
/* 0x000fea0003800000 */
/*0bc0*/ ISETP.NE.AND P0, PT, R17, 0x7ff00000, PT ; /* 0x7ff000001100780c */
/* 0x000fe40003f05270 */
/*0bd0*/ LOP3.LUT R13, R5, 0x80000000, R7, 0x48, !PT ; /* 0x80000000050d7812 */
/* 0x000fe400078e4807 */
/*0be0*/ ISETP.EQ.OR P0, PT, R16, RZ, !P0 ; /* 0x000000ff1000720c */
/* 0x000fda0004702670 */
/*0bf0*/ @P0 LOP3.LUT R2, R13, 0x7ff00000, RZ, 0xfc, !PT ; /* 0x7ff000000d020812 */
/* 0x000fe200078efcff */
/*0c00*/ @!P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c8224 */
/* 0x000fe400078e00ff */
/*0c10*/ @P0 IMAD.MOV.U32 R12, RZ, RZ, RZ ; /* 0x000000ffff0c0224 */
/* 0x000fe400078e00ff */
/*0c20*/ @P0 IMAD.MOV.U32 R13, RZ, RZ, R2 ; /* 0x000000ffff0d0224 */
/* 0x000fe200078e0002 */
/*0c30*/ BRA 0xc90 ; /* 0x0000005000007947 */
/* 0x000fea0003800000 */
/*0c40*/ LOP3.LUT R13, R7, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000070d7812 */
/* 0x000fe200078efcff */
/*0c50*/ IMAD.MOV.U32 R12, RZ, RZ, R6 ; /* 0x000000ffff0c7224 */
/* 0x000fe200078e0006 */
/*0c60*/ BRA 0xc90 ; /* 0x0000002000007947 */
/* 0x000fea0003800000 */
/*0c70*/ LOP3.LUT R13, R5, 0x80000, RZ, 0xfc, !PT ; /* 0x00080000050d7812 */
/* 0x000fe200078efcff */
/*0c80*/ IMAD.MOV.U32 R12, RZ, RZ, R4 ; /* 0x000000ffff0c7224 */
/* 0x000fe400078e0004 */
/*0c90*/ BSYNC B1 ; /* 0x0000000000017941 */
/* 0x000fea0003800000 */
/*0ca0*/ IMAD.MOV.U32 R2, RZ, RZ, R0 ; /* 0x000000ffff027224 */
/* 0x000fe400078e0000 */
/*0cb0*/ IMAD.MOV.U32 R3, RZ, RZ, 0x0 ; /* 0x00000000ff037424 */
/* 0x000fc800078e00ff */
/*0cc0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff33002007950 */
/* 0x000fea0003c3ffff */
/*0cd0*/ BRA 0xcd0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0ce0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0cf0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0d70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z25process_coarseness_ak_pixPdS_iil
.globl _Z25process_coarseness_ak_pixPdS_iil
.p2align 8
.type _Z25process_coarseness_ak_pixPdS_iil,@function
_Z25process_coarseness_ak_pixPdS_iil:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b64 s[10:11], s[0:1], 0x10
v_and_b32_e32 v2, 0x3ff, v0
v_bfe_u32 v3, v0, 10, 10
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s2, 0xffff
s_lshr_b32 s2, s2, 16
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[0:1], null, s14, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s15, s2, v[3:4]
s_mov_b32 s4, s11
v_cmp_gt_i32_e32 vcc_lo, s10, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s4, v1
s_and_b32 s2, vcc_lo, s2
s_delay_alu instid0(SALU_CYCLE_1)
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_8
s_clause 0x1
s_load_b64 s[2:3], s[0:1], 0x18
s_load_b64 s[8:9], s[0:1], 0x8
v_ashrrev_i32_e32 v10, 31, v0
v_ashrrev_i32_e32 v2, 31, v1
s_waitcnt lgkmcnt(0)
s_lshr_b32 s5, s3, 31
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s2, s2, s5
s_addc_u32 s3, s3, 0
s_ashr_i32 s11, s10, 31
s_ashr_i64 s[6:7], s[2:3], 1
s_ashr_i32 s5, s4, 31
v_add_co_u32 v3, vcc_lo, s6, v0
v_add_co_ci_u32_e32 v4, vcc_lo, s7, v10, vcc_lo
v_sub_co_u32 v7, vcc_lo, v1, s6
v_subrev_co_ci_u32_e32 v8, vcc_lo, s7, v2, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_cmp_gt_i64_e32 vcc_lo, s[10:11], v[3:4]
v_mov_b32_e32 v5, 0
v_mov_b32_e32 v6, 0
v_cmp_lt_i64_e64 s2, 0, v[7:8]
v_cndmask_b32_e32 v13, s11, v4, vcc_lo
v_cndmask_b32_e32 v14, s10, v3, vcc_lo
v_cmp_gt_i64_e32 vcc_lo, 1, v[7:8]
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v4, 0, v8, s2
v_cndmask_b32_e64 v3, 0, v7, s2
v_dual_mov_b32 v8, v6 :: v_dual_mov_b32 v7, v5
v_add_co_u32 v15, s3, v14, -1
v_add_co_ci_u32_e64 v16, s3, -1, v13, s3
s_and_saveexec_b32 s3, s2
s_cbranch_execz .LBB0_3
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mul_lo_u32 v9, v16, s4
v_mul_lo_u32 v11, v15, s5
v_mad_u64_u32 v[7:8], null, v15, s4, 0
v_add3_u32 v8, v8, v11, v9
v_lshlrev_b64 v[11:12], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[7:8], 3, v[7:8]
v_add_co_u32 v7, s2, s8, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v8, s2, s9, v8, s2
v_add_co_u32 v7, s2, v7, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v8, s2, v8, v12, s2
global_load_b64 v[7:8], v[7:8], off offset:-8
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
v_sub_co_u32 v9, s2, v0, s6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_subrev_co_ci_u32_e64 v10, s2, s7, v10, s2
s_mov_b32 s10, exec_lo
v_cmp_gt_i64_e64 s2, 1, v[9:10]
v_cmpx_lt_i64_e32 0, v[9:10]
s_cbranch_execz .LBB0_5
v_add_co_u32 v11, s3, v14, -2
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v5, s3, -1, v13, s3
v_mul_lo_u32 v17, v11, s5
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mul_lo_u32 v12, v5, s4
v_mad_u64_u32 v[5:6], null, v11, s4, 0
v_add3_u32 v6, v6, v17, v12
v_lshlrev_b64 v[11:12], 3, v[3:4]
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[5:6], 3, v[5:6]
v_add_co_u32 v5, s3, s8, v5
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e64 v6, s3, s9, v6, s3
v_add_co_u32 v5, s3, v5, v11
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e64 v6, s3, v6, v12, s3
global_load_b64 v[5:6], v[5:6], off
.LBB0_5:
s_or_b32 exec_lo, exec_lo, s10
v_mov_b32_e32 v11, 0
v_mov_b32_e32 v12, 0
s_or_b32 s2, s2, vcc_lo
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_xor_b32 s3, s2, -1
s_and_saveexec_b32 s2, s3
s_cbranch_execz .LBB0_7
v_add_co_u32 v17, vcc_lo, v14, -2
v_add_co_ci_u32_e32 v11, vcc_lo, -1, v13, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v19, v17, s5
v_mul_lo_u32 v18, v11, s4
v_mad_u64_u32 v[11:12], null, v17, s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add3_u32 v12, v12, v19, v18
v_lshlrev_b64 v[17:18], 3, v[3:4]
v_lshlrev_b64 v[11:12], 3, v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, s8, v11
v_add_co_ci_u32_e32 v12, vcc_lo, s9, v12, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v11, vcc_lo, v11, v17
v_add_co_ci_u32_e32 v12, vcc_lo, v12, v18, vcc_lo
global_load_b64 v[11:12], v[11:12], off offset:-8
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s2
v_mul_lo_u32 v18, v16, s4
v_mul_lo_u32 v19, v15, s5
v_mad_u64_u32 v[16:17], null, v15, s4, 0
v_cmp_lt_i64_e64 s2, 0, v[9:10]
s_load_b64 s[0:1], s[0:1], 0x0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v9, 0, v9, s2
v_add3_u32 v17, v17, v19, v18
v_cndmask_b32_e64 v10, 0, v10, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[15:16], 3, v[16:17]
v_lshlrev_b64 v[17:18], 3, v[3:4]
v_add_co_u32 v15, vcc_lo, s8, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_ci_u32_e32 v16, vcc_lo, s9, v16, vcc_lo
v_add_co_u32 v15, vcc_lo, v15, v17
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v16, vcc_lo, v16, v18, vcc_lo
v_add_co_u32 v17, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v18, vcc_lo, s7, v2, vcc_lo
global_load_b64 v[15:16], v[15:16], off
v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[17:18]
v_cndmask_b32_e32 v17, s4, v17, vcc_lo
v_cndmask_b32_e32 v18, s5, v18, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_co_u32 v17, vcc_lo, v17, v3
v_sub_co_ci_u32_e32 v3, vcc_lo, v18, v4, vcc_lo
v_sub_co_u32 v9, vcc_lo, v14, v9
v_sub_co_ci_u32_e32 v4, vcc_lo, v13, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v10, v3, v9
v_mul_lo_u32 v13, v17, v4
v_mad_u64_u32 v[3:4], null, v17, v9, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add3_u32 v4, v4, v13, v10
v_cvt_f64_i32_e32 v[9:10], v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cvt_f64_u32_e32 v[3:4], v3
v_ldexp_f64 v[9:10], v[9:10], 32
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_f64 v[3:4], v[9:10], v[3:4]
s_waitcnt vmcnt(0)
v_add_f64 v[7:8], v[15:16], -v[7:8]
v_add_f64 v[5:6], v[7:8], -v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f64 v[5:6], v[11:12], v[5:6]
v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_rcp_f64_e32 v[9:10], v[7:8]
s_waitcnt_depctr 0xfff
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
v_div_scale_f64 v[11:12], vcc_lo, v[5:6], v[3:4], v[5:6]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[13:14], v[11:12], v[9:10]
v_fma_f64 v[7:8], -v[7:8], v[13:14], v[11:12]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[13:14]
v_div_fixup_f64 v[3:4], v[7:8], v[3:4], v[5:6]
v_mad_u64_u32 v[5:6], null, v0, s4, v[1:2]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v6, 31, v5
v_lshlrev_b64 v[0:1], 3, v[5:6]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b64 v[0:1], v[3:4], off
.LBB0_8:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z25process_coarseness_ak_pixPdS_iil
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 20
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z25process_coarseness_ak_pixPdS_iil, .Lfunc_end0-_Z25process_coarseness_ak_pixPdS_iil
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
- .offset: 20
.size: 4
.value_kind: by_value
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z25process_coarseness_ak_pixPdS_iil
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z25process_coarseness_ak_pixPdS_iil.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 20
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00069d83_00000000-6_process_coarseness_ak_pix.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2030:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z22efficientLocalMean_devlllPdii
.type _Z22efficientLocalMean_devlllPdii, @function
_Z22efficientLocalMean_devlllPdii:
.LFB2027:
.cfi_startproc
endbr64
pushq %rax
.cfi_def_cfa_offset 16
popq %rax
.cfi_def_cfa_offset 8
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $1, 12(%rsp)
movl 12(%rsp), %edi
call exit@PLT
.cfi_endproc
.LFE2027:
.size _Z22efficientLocalMean_devlllPdii, .-_Z22efficientLocalMean_devlllPdii
.globl _Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil
.type _Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil, @function
_Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil:
.LFB2052:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L9
.L5:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L10
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L9:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z25process_coarseness_ak_pixPdS_iil(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L5
.L10:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2052:
.size _Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil, .-_Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil
.globl _Z25process_coarseness_ak_pixPdS_iil
.type _Z25process_coarseness_ak_pixPdS_iil, @function
_Z25process_coarseness_ak_pixPdS_iil:
.LFB2053:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z50__device_stub__Z25process_coarseness_ak_pixPdS_iilPdS_iil
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2053:
.size _Z25process_coarseness_ak_pixPdS_iil, .-_Z25process_coarseness_ak_pixPdS_iil
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z25process_coarseness_ak_pixPdS_iil"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z25process_coarseness_ak_pixPdS_iil(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2055:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "process_coarseness_ak_pix.hip"
.globl _Z40__device_stub__process_coarseness_ak_pixPdS_iil # -- Begin function _Z40__device_stub__process_coarseness_ak_pixPdS_iil
.p2align 4, 0x90
.type _Z40__device_stub__process_coarseness_ak_pixPdS_iil,@function
_Z40__device_stub__process_coarseness_ak_pixPdS_iil: # @_Z40__device_stub__process_coarseness_ak_pixPdS_iil
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 4(%rsp)
movl %ecx, (%rsp)
movq %r8, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 4(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsp, %rax
movq %rax, 104(%rsp)
leaq 56(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z25process_coarseness_ak_pixPdS_iil, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z40__device_stub__process_coarseness_ak_pixPdS_iil, .Lfunc_end0-_Z40__device_stub__process_coarseness_ak_pixPdS_iil
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z25process_coarseness_ak_pixPdS_iil, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z25process_coarseness_ak_pixPdS_iil,@object # @_Z25process_coarseness_ak_pixPdS_iil
.section .rodata,"a",@progbits
.globl _Z25process_coarseness_ak_pixPdS_iil
.p2align 3, 0x0
_Z25process_coarseness_ak_pixPdS_iil:
.quad _Z40__device_stub__process_coarseness_ak_pixPdS_iil
.size _Z25process_coarseness_ak_pixPdS_iil, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z25process_coarseness_ak_pixPdS_iil"
.size .L__unnamed_1, 37
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z40__device_stub__process_coarseness_ak_pixPdS_iil
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z25process_coarseness_ak_pixPdS_iil
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void roi_logits_to_attrs_gpu_kernel(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
const float anchor_diag = sqrtf(powf(anchor_w, 2) + powf(anchor_l, 2));
int input_id = threadIdx.x + blockIdx.x * blockDim.x;
if (input_id < input_npoint) {
output_attrs[input_id * 7 + 0] = expf(input_logits[input_id * channels + 0]) * anchor_w;
output_attrs[input_id * 7 + 1] = expf(input_logits[input_id * channels + 1]) * anchor_l;
output_attrs[input_id * 7 + 2] = expf(input_logits[input_id * channels + 2]) * anchor_h;
output_attrs[input_id * 7 + 3] = input_logits[input_id * channels + 3] * anchor_diag + base_coors[input_id * 3 + 0];
output_attrs[input_id * 7 + 4] = input_logits[input_id * channels + 4] * anchor_diag + base_coors[input_id * 3 + 1];
output_attrs[input_id * 7 + 5] = input_logits[input_id * channels + 5] * anchor_h + base_coors[input_id * 3 + 2];
output_attrs[input_id * 7 + 6] = input_logits[input_id * channels + 6] * 3.1415927;
}
}
void roi_logits_to_attrs_gpu_launcher(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
if (input_npoint == 0)
return;
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, roi_logits_to_attrs_gpu_kernel, 0, input_npoint);
// Round up according to array size
gridSize = (input_npoint + blockSize - 1) / blockSize;
roi_logits_to_attrs_gpu_kernel<<<gridSize, blockSize>>>(input_npoint, channels,
anchor_w, anchor_l, anchor_h,
base_coors,
input_logits,
output_attrs);
} | code for sm_80
Function : _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ MOV R0, c[0x0][0x168] ; /* 0x00005a0000007a02 */
/* 0x000fc80000000f00 */
/*0020*/ FSETP.GEU.AND P0, PT, |R0|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000000780b */
/* 0x040fe20003f0e200 */
/*0030*/ FMUL R2, |R0|.reuse, 16777216 ; /* 0x4b80000000027820 */
/* 0x040fe20000400200 */
/*0040*/ FSETP.NEU.AND P2, PT, R0, 1, PT ; /* 0x3f8000000000780b */
/* 0x000fc80003f4d000 */
/*0050*/ FSEL R2, R2, |c[0x0][0x168]|, !P0 ; /* 0x40005a0002027a08 */
/* 0x000fc80004000000 */
/*0060*/ IADD3 R3, R2, -0x3f3504f3, RZ ; /* 0xc0cafb0d02037810 */
/* 0x000fc80007ffe0ff */
/*0070*/ LOP3.LUT R5, R3, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000003057812 */
/* 0x000fe400078ec0ff */
/*0080*/ FSEL R3, RZ, -24, P0 ; /* 0xc1c00000ff037808 */
/* 0x000fe40000000000 */
/*0090*/ IADD3 R2, R2, -R5, RZ ; /* 0x8000000502027210 */
/* 0x000fe20007ffe0ff */
/*00a0*/ I2F R4, R5 ; /* 0x0000000500047306 */
/* 0x000e280000201400 */
/*00b0*/ FADD R7, R2.reuse, 1 ; /* 0x3f80000002077421 */
/* 0x040fe40000000000 */
/*00c0*/ FADD R6, R2, -1 ; /* 0xbf80000002067421 */
/* 0x000fc80000000000 */
/*00d0*/ MUFU.RCP R7, R7 ; /* 0x0000000700077308 */
/* 0x000e620000001000 */
/*00e0*/ FADD R2, R6, R6 ; /* 0x0000000606027221 */
/* 0x000fe40000000000 */
/*00f0*/ FFMA R3, R4, 1.1920928955078125e-07, R3 ; /* 0x3400000004037823 */
/* 0x001fe40000000003 */
/*0100*/ FMUL R9, R7, R2 ; /* 0x0000000207097220 */
/* 0x002fe20000400000 */
/*0110*/ HFMA2.MMA R2, -RZ, RZ, 0.771484375, 0.21533203125 ; /* 0x3a2c32e4ff027435 */
/* 0x000fc600000001ff */
/*0120*/ FADD R4, R6, -R9 ; /* 0x8000000906047221 */
/* 0x000fe40000000000 */
/*0130*/ FMUL R11, R9.reuse, R9 ; /* 0x00000009090b7220 */
/* 0x040fe40000400000 */
/*0140*/ FFMA R10, R9, 1.4426950216293334961, R3 ; /* 0x3fb8aa3b090a7823 */
/* 0x000fe40000000003 */
/*0150*/ FADD R4, R4, R4 ; /* 0x0000000404047221 */
/* 0x000fe40000000000 */
/*0160*/ FFMA R8, R11, R2, 0.0032181653659790754318 ; /* 0x3b52e7db0b087423 */
/* 0x000fe40000000002 */
/*0170*/ FADD R12, R3, -R10 ; /* 0x8000000a030c7221 */
/* 0x000fc40000000000 */
/*0180*/ FFMA R4, R6, -R9, R4 ; /* 0x8000000906047223 */
/* 0x000fe40000000004 */
/*0190*/ FFMA R8, R11, R8, 0.018033718690276145935 ; /* 0x3c93bb730b087423 */
/* 0x000fe40000000008 */
/*01a0*/ FFMA R3, R9, 1.4426950216293334961, R12 ; /* 0x3fb8aa3b09037823 */
/* 0x000fe4000000000c */
/*01b0*/ FMUL R4, R7, R4 ; /* 0x0000000407047220 */
/* 0x000fe40000400000 */
/*01c0*/ FFMA R8, R11, R8, 0.12022458761930465698 ; /* 0x3df6384f0b087423 */
/* 0x000fe40000000008 */
/*01d0*/ FFMA R6, R4, 1.4426950216293334961, R3 ; /* 0x3fb8aa3b04067823 */
/* 0x000fc40000000003 */
/*01e0*/ FMUL R8, R11, R8 ; /* 0x000000080b087220 */
/* 0x000fe40000400000 */
/*01f0*/ FFMA R3, R9, 1.9251366722983220825e-08, R6 ; /* 0x32a55e3409037823 */
/* 0x000fe40000000006 */
/*0200*/ FMUL R5, R8, 3 ; /* 0x4040000008057820 */
/* 0x000fc80000400000 */
/*0210*/ FFMA R3, R4, R5, R3 ; /* 0x0000000504037223 */
/* 0x000fc80000000003 */
/*0220*/ FFMA R3, R9, R8, R3 ; /* 0x0000000809037223 */
/* 0x000fc80000000003 */
/*0230*/ FADD R5, R10, R3 ; /* 0x000000030a057221 */
/* 0x000fc80000000000 */
/*0240*/ FMUL R4, R5.reuse, 2 ; /* 0x4000000005047820 */
/* 0x040fe40000400000 */
/*0250*/ FADD R10, -R10, R5 ; /* 0x000000050a0a7221 */
/* 0x000fe40000000100 */
/*0260*/ FRND R7, R4 ; /* 0x0000000400077307 */
/* 0x000e220000201000 */
/*0270*/ FFMA R5, R5, 2, -R4 ; /* 0x4000000005057823 */
/* 0x000fe20000000804 */
/*0280*/ FSETP.GEU.AND P1, PT, R4, RZ, PT ; /* 0x000000ff0400720b */
/* 0x000fe20003f2e000 */
/*0290*/ FADD R10, R3, -R10 ; /* 0x8000000a030a7221 */
/* 0x000fe20000000000 */
/*02a0*/ MOV R3, 0x391fcb8e ; /* 0x391fcb8e00037802 */
/* 0x000fc60000000f00 */
/*02b0*/ FFMA R5, R10, 2, R5 ; /* 0x400000000a057823 */
/* 0x000fe20000000005 */
/*02c0*/ F2I.NTZ R8, R4 ; /* 0x0000000400087305 */
/* 0x0002a20000203100 */
/*02d0*/ FADD R6, R4, -R7 ; /* 0x8000000704067221 */
/* 0x001fe20000000000 */
/*02e0*/ FSETP.GT.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fc60003f04000 */
/*02f0*/ FADD R6, R5, R6 ; /* 0x0000000605067221 */
/* 0x000fe20000000000 */
/*0300*/ SEL R7, RZ, 0x83000000, P0 ; /* 0x83000000ff077807 */
/* 0x000fe40000000000 */
/*0310*/ FSETP.GT.AND P0, PT, |R4|, 152, PT ; /* 0x431800000400780b */
/* 0x000fe20003f04200 */
/*0320*/ FFMA R5, R6, R3, 0.0013391353422775864601 ; /* 0x3aaf85ed06057423 */
/* 0x000fe20000000003 */
/*0330*/ IADD3 R10, R7, 0x7f000000, RZ ; /* 0x7f000000070a7810 */
/* 0x000fe20007ffe0ff */
/*0340*/ HFMA2.MMA R4, -RZ, RZ, 1.875, 0 ; /* 0x3f800000ff047435 */
/* 0x002fe200000001ff */
/*0350*/ LEA R8, R8, -R7, 0x17 ; /* 0x8000000708087211 */
/* 0x004fe200078eb8ff */
/*0360*/ FFMA R5, R6, R5, 0.0096188392490148544312 ; /* 0x3c1d985606057423 */
/* 0x000fc80000000005 */
/*0370*/ FFMA R5, R6, R5, 0.055503588169813156128 ; /* 0x3d6357bb06057423 */
/* 0x000fc80000000005 */
/*0380*/ FFMA R5, R6, R5, 0.24022644758224487305 ; /* 0x3e75fdec06057423 */
/* 0x000fc80000000005 */
/*0390*/ FFMA R5, R6, R5, 0.69314718246459960938 ; /* 0x3f31721806057423 */
/* 0x000fc80000000005 */
/*03a0*/ FFMA R5, R6, R5, 1 ; /* 0x3f80000006057423 */
/* 0x000fc80000000005 */
/*03b0*/ FMUL R5, R5, R10 ; /* 0x0000000a05057220 */
/* 0x000fc80000400000 */
/*03c0*/ FMUL R8, R5, R8 ; /* 0x0000000805087220 */
/* 0x000fe20000400000 */
/*03d0*/ MOV R5, 0x3f800000 ; /* 0x3f80000000057802 */
/* 0x000fe40000000f00 */
/*03e0*/ @P0 FSEL R8, RZ, +INF , !P1 ; /* 0x7f800000ff080808 */
/* 0x000fe20004800000 */
/*03f0*/ @!P2 BRA 0x4e0 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0400*/ FSETP.GTU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f0c200 */
/*0410*/ @P0 BRA 0x4d0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0420*/ FSETP.NEU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f0d200 */
/*0430*/ FSETP.EQ.OR P0, PT, RZ, c[0x0][0x168], !P0 ; /* 0x00005a00ff007a0b */
/* 0x000fda0004702400 */
/*0440*/ @P0 BRA 0x4a0 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*0450*/ FSETP.LEU.AND P0, PT, RZ, c[0x0][0x168], PT ; /* 0x00005a00ff007a0b */
/* 0x000fe40003f0b000 */
/*0460*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fd60000000f00 */
/*0470*/ @P0 BRA 0x4e0 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0480*/ MOV R5, R8 ; /* 0x0000000800057202 */
/* 0x000fe20000000f00 */
/*0490*/ BRA 0x4e0 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*04a0*/ FADD R0, R0, c[0x0][0x168] ; /* 0x00005a0000007621 */
/* 0x000fca0000000000 */
/*04b0*/ LOP3.LUT R5, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00057812 */
/* 0x000fe200078ec0ff */
/*04c0*/ BRA 0x4e0 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*04d0*/ FADD R5, R0, 2 ; /* 0x4000000000057421 */
/* 0x000fe40000000000 */
/*04e0*/ MOV R0, c[0x0][0x16c] ; /* 0x00005b0000007a02 */
/* 0x000fc80000000f00 */
/*04f0*/ FSETP.GEU.AND P0, PT, |R0|.reuse, 1.175494350822287508e-38, PT ; /* 0x008000000000780b */
/* 0x040fe20003f0e200 */
/*0500*/ FMUL R6, |R0|.reuse, 16777216 ; /* 0x4b80000000067820 */
/* 0x040fe20000400200 */
/*0510*/ FSETP.NEU.AND P2, PT, R0, 1, PT ; /* 0x3f8000000000780b */
/* 0x000fc80003f4d000 */
/*0520*/ FSEL R6, R6, |c[0x0][0x16c]|, !P0 ; /* 0x40005b0006067a08 */
/* 0x000fc80004000000 */
/*0530*/ IADD3 R7, R6, -0x3f3504f3, RZ ; /* 0xc0cafb0d06077810 */
/* 0x000fc80007ffe0ff */
/*0540*/ LOP3.LUT R7, R7, 0xff800000, RZ, 0xc0, !PT ; /* 0xff80000007077812 */
/* 0x000fc800078ec0ff */
/*0550*/ IADD3 R6, R6, -R7, RZ ; /* 0x8000000706067210 */
/* 0x000fe40007ffe0ff */
/*0560*/ I2F R7, R7 ; /* 0x0000000700077306 */
/* 0x000e260000201400 */
/*0570*/ FADD R9, R6.reuse, 1 ; /* 0x3f80000006097421 */
/* 0x040fe40000000000 */
/*0580*/ FADD R8, R6, -1 ; /* 0xbf80000006087421 */
/* 0x000fe20000000000 */
/*0590*/ FSEL R6, RZ, -24, P0 ; /* 0xc1c00000ff067808 */
/* 0x000fc60000000000 */
/*05a0*/ MUFU.RCP R9, R9 ; /* 0x0000000900097308 */
/* 0x000e620000001000 */
/*05b0*/ FADD R10, R8, R8 ; /* 0x00000008080a7221 */
/* 0x000fe40000000000 */
/*05c0*/ FFMA R6, R7, 1.1920928955078125e-07, R6 ; /* 0x3400000007067823 */
/* 0x001fe40000000006 */
/*05d0*/ FMUL R11, R9, R10 ; /* 0x0000000a090b7220 */
/* 0x002fc80000400000 */
/*05e0*/ FADD R10, R8, -R11 ; /* 0x8000000b080a7221 */
/* 0x000fe40000000000 */
/*05f0*/ FMUL R13, R11.reuse, R11 ; /* 0x0000000b0b0d7220 */
/* 0x040fe40000400000 */
/*0600*/ FFMA R15, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b0f7823 */
/* 0x000fe40000000006 */
/*0610*/ FADD R10, R10, R10 ; /* 0x0000000a0a0a7221 */
/* 0x000fe40000000000 */
/*0620*/ FFMA R2, R13, R2, 0.0032181653659790754318 ; /* 0x3b52e7db0d027423 */
/* 0x000fe40000000002 */
/*0630*/ FADD R6, R6, -R15 ; /* 0x8000000f06067221 */
/* 0x000fc40000000000 */
/*0640*/ FFMA R10, R8, -R11, R10 ; /* 0x8000000b080a7223 */
/* 0x000fe4000000000a */
/*0650*/ FFMA R2, R13, R2, 0.018033718690276145935 ; /* 0x3c93bb730d027423 */
/* 0x000fe40000000002 */
/*0660*/ FFMA R7, R11, 1.4426950216293334961, R6 ; /* 0x3fb8aa3b0b077823 */
/* 0x000fe40000000006 */
/*0670*/ FMUL R10, R9, R10 ; /* 0x0000000a090a7220 */
/* 0x000fe40000400000 */
/*0680*/ FFMA R2, R13, R2, 0.12022458761930465698 ; /* 0x3df6384f0d027423 */
/* 0x000fe40000000002 */
/*0690*/ FFMA R6, R10, 1.4426950216293334961, R7 ; /* 0x3fb8aa3b0a067823 */
/* 0x000fc40000000007 */
/*06a0*/ FMUL R2, R13, R2 ; /* 0x000000020d027220 */
/* 0x000fe40000400000 */
/*06b0*/ FFMA R7, R11, 1.9251366722983220825e-08, R6 ; /* 0x32a55e340b077823 */
/* 0x000fe40000000006 */
/*06c0*/ FMUL R6, R2, 3 ; /* 0x4040000002067820 */
/* 0x000fc80000400000 */
/*06d0*/ FFMA R6, R10, R6, R7 ; /* 0x000000060a067223 */
/* 0x000fc80000000007 */
/*06e0*/ FFMA R6, R11, R2, R6 ; /* 0x000000020b067223 */
/* 0x000fc80000000006 */
/*06f0*/ FADD R2, R15, R6 ; /* 0x000000060f027221 */
/* 0x000fc80000000000 */
/*0700*/ FMUL R7, R2.reuse, 2 ; /* 0x4000000002077820 */
/* 0x040fe40000400000 */
/*0710*/ FADD R15, -R15, R2 ; /* 0x000000020f0f7221 */
/* 0x000fe40000000100 */
/*0720*/ FRND R8, R7 ; /* 0x0000000700087307 */
/* 0x000e220000201000 */
/*0730*/ FFMA R2, R2, 2, -R7 ; /* 0x4000000002027823 */
/* 0x000fe20000000807 */
/*0740*/ FSETP.GEU.AND P1, PT, R7, RZ, PT ; /* 0x000000ff0700720b */
/* 0x000fe20003f2e000 */
/*0750*/ FADD R15, R6, -R15 ; /* 0x8000000f060f7221 */
/* 0x000fc80000000000 */
/*0760*/ FFMA R2, R15, 2, R2 ; /* 0x400000000f027823 */
/* 0x000fe20000000002 */
/*0770*/ F2I.NTZ R6, R7 ; /* 0x0000000700067305 */
/* 0x000e620000203100 */
/*0780*/ FADD R9, R7, -R8 ; /* 0x8000000807097221 */
/* 0x001fe20000000000 */
/*0790*/ FSETP.GT.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720b */
/* 0x000fc60003f04000 */
/*07a0*/ FADD R2, R2, R9 ; /* 0x0000000902027221 */
/* 0x000fe20000000000 */
/*07b0*/ SEL R9, RZ, 0x83000000, P0 ; /* 0x83000000ff097807 */
/* 0x000fe40000000000 */
/*07c0*/ FSETP.GT.AND P0, PT, |R7|, 152, PT ; /* 0x431800000700780b */
/* 0x000fe20003f04200 */
/*07d0*/ FFMA R3, R2, R3, 0.0013391353422775864601 ; /* 0x3aaf85ed02037423 */
/* 0x000fe20000000003 */
/*07e0*/ IADD3 R8, R9, 0x7f000000, RZ ; /* 0x7f00000009087810 */
/* 0x000fe40007ffe0ff */
/*07f0*/ LEA R6, R6, -R9, 0x17 ; /* 0x8000000906067211 */
/* 0x002fe200078eb8ff */
/*0800*/ FFMA R3, R2, R3, 0.0096188392490148544312 ; /* 0x3c1d985602037423 */
/* 0x000fc80000000003 */
/*0810*/ FFMA R3, R2, R3, 0.055503588169813156128 ; /* 0x3d6357bb02037423 */
/* 0x000fc80000000003 */
/*0820*/ FFMA R3, R2, R3, 0.24022644758224487305 ; /* 0x3e75fdec02037423 */
/* 0x000fc80000000003 */
/*0830*/ FFMA R3, R2, R3, 0.69314718246459960938 ; /* 0x3f31721802037423 */
/* 0x000fc80000000003 */
/*0840*/ FFMA R3, R2, R3, 1 ; /* 0x3f80000002037423 */
/* 0x000fc80000000003 */
/*0850*/ FMUL R3, R3, R8 ; /* 0x0000000803037220 */
/* 0x000fc80000400000 */
/*0860*/ FMUL R3, R3, R6 ; /* 0x0000000603037220 */
/* 0x000fe20000400000 */
/*0870*/ @P0 FSEL R3, RZ, +INF , !P1 ; /* 0x7f800000ff030808 */
/* 0x000fe20004800000 */
/*0880*/ @!P2 BRA 0x970 ; /* 0x000000e00000a947 */
/* 0x000fea0003800000 */
/*0890*/ FSETP.GTU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fda0003f0c200 */
/*08a0*/ @P0 BRA 0x960 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*08b0*/ FSETP.NEU.AND P0, PT, |R0|, +INF , PT ; /* 0x7f8000000000780b */
/* 0x000fc80003f0d200 */
/*08c0*/ FSETP.EQ.OR P0, PT, RZ, c[0x0][0x16c], !P0 ; /* 0x00005b00ff007a0b */
/* 0x000fda0004702400 */
/*08d0*/ @P0 BRA 0x930 ; /* 0x0000005000000947 */
/* 0x000fea0003800000 */
/*08e0*/ FSETP.LEU.AND P0, PT, RZ, c[0x0][0x16c], PT ; /* 0x00005b00ff007a0b */
/* 0x000fe40003f0b000 */
/*08f0*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fd60000000f00 */
/*0900*/ @P0 BRA 0x970 ; /* 0x0000006000000947 */
/* 0x000fea0003800000 */
/*0910*/ MOV R4, R3 ; /* 0x0000000300047202 */
/* 0x000fe20000000f00 */
/*0920*/ BRA 0x970 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0930*/ FADD R0, R0, c[0x0][0x16c] ; /* 0x00005b0000007621 */
/* 0x000fca0000000000 */
/*0940*/ LOP3.LUT R4, R0, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff00047812 */
/* 0x000fe200078ec0ff */
/*0950*/ BRA 0x970 ; /* 0x0000001000007947 */
/* 0x000fea0003800000 */
/*0960*/ FADD R4, R0, 2 ; /* 0x4000000000047421 */
/* 0x000fe40000000000 */
/*0970*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e280000002500 */
/*0980*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0990*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*09a0*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x160], PT ; /* 0x0000580000007a0c */
/* 0x000fda0003f06270 */
/*09b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*09c0*/ FADD R3, R5, R4 ; /* 0x0000000405037221 */
/* 0x000fe20000000000 */
/*09d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*09e0*/ MUFU.RSQ R2, R3 ; /* 0x0000000300027308 */
/* 0x0000620000001400 */
/*09f0*/ IADD3 R4, R3, -0xd000000, RZ ; /* 0xf300000003047810 */
/* 0x000fc80007ffe0ff */
/*0a00*/ ISETP.GT.U32.AND P0, PT, R4, 0x727fffff, PT ; /* 0x727fffff0400780c */
/* 0x000fda0003f04070 */
/*0a10*/ @!P0 BRA 0xa50 ; /* 0x0000003000008947 */
/* 0x000fea0003800000 */
/*0a20*/ MOV R7, 0xa40 ; /* 0x00000a4000077802 */
/* 0x003fe40000000f00 */
/*0a30*/ CALL.REL.NOINC 0xe70 ; /* 0x0000043000007944 */
/* 0x000fea0003c00000 */
/*0a40*/ BRA 0xa90 ; /* 0x0000004000007947 */
/* 0x000fea0003800000 */
/*0a50*/ FMUL.FTZ R6, R3, R2 ; /* 0x0000000203067220 */
/* 0x003fe40000410000 */
/*0a60*/ FMUL.FTZ R2, R2, 0.5 ; /* 0x3f00000002027820 */
/* 0x000fe40000410000 */
/*0a70*/ FFMA R3, -R6, R6, R3 ; /* 0x0000000606037223 */
/* 0x000fc80000000103 */
/*0a80*/ FFMA R6, R3, R2, R6 ; /* 0x0000000203067223 */
/* 0x000fe40000000006 */
/*0a90*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0aa0*/ IMAD R2, R0, c[0x0][0x164], RZ ; /* 0x0000590000027a24 */
/* 0x000fd200078e02ff */
/*0ab0*/ IMAD.WIDE R2, R2, R7, c[0x0][0x180] ; /* 0x0000600002027625 */
/* 0x000fca00078e0207 */
/*0ac0*/ LDG.E R5, [R2.64] ; /* 0x0000000402057981 */
/* 0x000ea2000c1e1900 */
/*0ad0*/ HFMA2.MMA R9, -RZ, RZ, 3.7421875, 0 ; /* 0x437c0000ff097435 */
/* 0x000fe200000001ff */
/*0ae0*/ MOV R8, 0x3bbb989d ; /* 0x3bbb989d00087802 */
/* 0x000fe40000000f00 */
/*0af0*/ LEA R12, R0, -R0, 0x3 ; /* 0x80000000000c7211 */
/* 0x000fc600078e18ff */
/*0b00*/ FFMA.SAT R4, R5, R8, 0.5 ; /* 0x3f00000005047423 */
/* 0x004fc80000002008 */
/*0b10*/ FFMA.RM R4, R4, R9, 12582913 ; /* 0x4b40000104047423 */
/* 0x000fc80000004009 */
/*0b20*/ FADD R10, R4.reuse, -12583039 ; /* 0xcb40007f040a7421 */
/* 0x040fe20000000000 */
/*0b30*/ SHF.L.U32 R4, R4, 0x17, RZ ; /* 0x0000001704047819 */
/* 0x000fc600000006ff */
/*0b40*/ FFMA R10, R5, 1.4426950216293334961, -R10 ; /* 0x3fb8aa3b050a7823 */
/* 0x000fc8000000080a */
/*0b50*/ FFMA R10, R5, 1.925963033500011079e-08, R10 ; /* 0x32a57060050a7823 */
/* 0x000fc8000000000a */
/*0b60*/ MUFU.EX2 R5, R10 ; /* 0x0000000a00057308 */
/* 0x000e240000000800 */
/*0b70*/ FMUL R11, R4, R5 ; /* 0x00000005040b7220 */
/* 0x001fe40000400000 */
/*0b80*/ IMAD.WIDE R4, R12, R7, c[0x0][0x188] ; /* 0x000062000c047625 */
/* 0x000fc800078e0207 */
/*0b90*/ FMUL R11, R11, c[0x0][0x168] ; /* 0x00005a000b0b7a20 */
/* 0x000fca0000400000 */
/*0ba0*/ STG.E [R4.64], R11 ; /* 0x0000000b04007986 */
/* 0x0001e8000c101904 */
/*0bb0*/ LDG.E R13, [R2.64+0x4] ; /* 0x00000404020d7981 */
/* 0x000ea4000c1e1900 */
/*0bc0*/ FFMA.SAT R12, R13, R8, 0.5 ; /* 0x3f0000000d0c7423 */
/* 0x004fc80000002008 */
/*0bd0*/ FFMA.RM R12, R12, R9, 12582913 ; /* 0x4b4000010c0c7423 */
/* 0x000fc80000004009 */
/*0be0*/ FADD R14, R12.reuse, -12583039 ; /* 0xcb40007f0c0e7421 */
/* 0x040fe20000000000 */
/*0bf0*/ SHF.L.U32 R12, R12, 0x17, RZ ; /* 0x000000170c0c7819 */
/* 0x000fc600000006ff */
/*0c00*/ FFMA R14, R13, 1.4426950216293334961, -R14 ; /* 0x3fb8aa3b0d0e7823 */
/* 0x000fc8000000080e */
/*0c10*/ FFMA R14, R13, 1.925963033500011079e-08, R14 ; /* 0x32a570600d0e7823 */
/* 0x000fc8000000000e */
/*0c20*/ MUFU.EX2 R13, R14 ; /* 0x0000000e000d7308 */
/* 0x000e640000000800 */
/*0c30*/ FMUL R12, R12, R13 ; /* 0x0000000d0c0c7220 */
/* 0x002fc80000400000 */
/*0c40*/ FMUL R13, R12, c[0x0][0x16c] ; /* 0x00005b000c0d7a20 */
/* 0x000fca0000400000 */
/*0c50*/ STG.E [R4.64+0x4], R13 ; /* 0x0000040d04007986 */
/* 0x0003e8000c101904 */
/*0c60*/ LDG.E R11, [R2.64+0x8] ; /* 0x00000804020b7981 */
/* 0x001ea2000c1e1900 */
/*0c70*/ LEA R0, R0, R0, 0x1 ; /* 0x0000000000007211 */
/* 0x000fe200078e08ff */
/*0c80*/ FFMA.SAT R8, R11, R8, 0.5 ; /* 0x3f0000000b087423 */
/* 0x004fc80000002008 */
/*0c90*/ FFMA.RM R8, R8, R9, 12582913 ; /* 0x4b40000108087423 */
/* 0x000fc80000004009 */
/*0ca0*/ FADD R10, R8.reuse, -12583039 ; /* 0xcb40007f080a7421 */
/* 0x040fe20000000000 */
/*0cb0*/ SHF.L.U32 R8, R8, 0x17, RZ ; /* 0x0000001708087819 */
/* 0x000fc600000006ff */
/*0cc0*/ FFMA R10, R11, 1.4426950216293334961, -R10 ; /* 0x3fb8aa3b0b0a7823 */
/* 0x000fc8000000080a */
/*0cd0*/ FFMA R10, R11, 1.925963033500011079e-08, R10 ; /* 0x32a570600b0a7823 */
/* 0x000fc8000000000a */
/*0ce0*/ MUFU.EX2 R9, R10 ; /* 0x0000000a00097308 */
/* 0x000e240000000800 */
/*0cf0*/ FMUL R8, R8, R9 ; /* 0x0000000908087220 */
/* 0x001fc80000400000 */
/*0d00*/ FMUL R13, R8, c[0x0][0x170] ; /* 0x00005c00080d7a20 */
/* 0x002fe40000400000 */
/*0d10*/ IMAD.WIDE R8, R0, R7, c[0x0][0x178] ; /* 0x00005e0000087625 */
/* 0x000fc600078e0207 */
/*0d20*/ STG.E [R4.64+0x8], R13 ; /* 0x0000080d04007986 */
/* 0x000fe8000c101904 */
/*0d30*/ LDG.E R8, [R8.64] ; /* 0x0000000408087981 */
/* 0x000ea8000c1e1900 */
/*0d40*/ LDG.E R11, [R2.64+0xc] ; /* 0x00000c04020b7981 */
/* 0x000ea2000c1e1900 */
/*0d50*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fe20007ffe0ff */
/*0d60*/ FFMA R15, R11, R6, R8 ; /* 0x000000060b0f7223 */
/* 0x004fc80000000008 */
/*0d70*/ IMAD.WIDE R10, R0, R7, c[0x0][0x178] ; /* 0x00005e00000a7625 */
/* 0x000fe200078e0207 */
/*0d80*/ STG.E [R4.64+0xc], R15 ; /* 0x00000c0f04007986 */
/* 0x000fe8000c101904 */
/*0d90*/ LDG.E R7, [R2.64+0x10] ; /* 0x0000100402077981 */
/* 0x000ea8000c1e1900 */
/*0da0*/ LDG.E R0, [R10.64] ; /* 0x000000040a007981 */
/* 0x000ea4000c1e1900 */
/*0db0*/ FFMA R17, R7, R6, R0 ; /* 0x0000000607117223 */
/* 0x004fca0000000000 */
/*0dc0*/ STG.E [R4.64+0x10], R17 ; /* 0x0000101104007986 */
/* 0x000fe8000c101904 */
/*0dd0*/ LDG.E R7, [R10.64+0x4] ; /* 0x000004040a077981 */
/* 0x000ea8000c1e1900 */
/*0de0*/ LDG.E R0, [R2.64+0x14] ; /* 0x0000140402007981 */
/* 0x000ea4000c1e1900 */
/*0df0*/ FFMA R9, R0, c[0x0][0x170], R7 ; /* 0x00005c0000097a23 */
/* 0x004fca0000000007 */
/*0e00*/ STG.E [R4.64+0x14], R9 ; /* 0x0000140904007986 */
/* 0x000fe8000c101904 */
/*0e10*/ LDG.E R0, [R2.64+0x18] ; /* 0x0000180402007981 */
/* 0x000ea4000c1e1900 */
/*0e20*/ F2F.F64.F32 R6, R0 ; /* 0x0000000000067310 */
/* 0x004e240000201800 */
/*0e30*/ DMUL R6, R6, c[0x2][0x0] ; /* 0x0080000006067a28 */
/* 0x001e140000000000 */
/*0e40*/ F2F.F32.F64 R7, R6 ; /* 0x0000000600077310 */
/* 0x001e240000301000 */
/*0e50*/ STG.E [R4.64+0x18], R7 ; /* 0x0000180704007986 */
/* 0x001fe2000c101904 */
/*0e60*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e70*/ LOP3.LUT P0, RZ, R3, 0x7fffffff, RZ, 0xc0, !PT ; /* 0x7fffffff03ff7812 */
/* 0x000fda000780c0ff */
/*0e80*/ @!P0 BRA 0xfb0 ; /* 0x0000012000008947 */
/* 0x000fea0003800000 */
/*0e90*/ FSETP.GEU.FTZ.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720b */
/* 0x000fe40003f1e000 */
/*0ea0*/ MOV R2, R3 ; /* 0x0000000300027202 */
/* 0x000fd60000000f00 */
/*0eb0*/ @!P0 MOV R3, 0x7fffffff ; /* 0x7fffffff00038802 */
/* 0x000fe20000000f00 */
/*0ec0*/ @!P0 BRA 0xfb0 ; /* 0x000000e000008947 */
/* 0x000fea0003800000 */
/*0ed0*/ FSETP.GTU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1c200 */
/*0ee0*/ @P0 FADD.FTZ R3, R2, 1 ; /* 0x3f80000002030421 */
/* 0x000fe20000010000 */
/*0ef0*/ @P0 BRA 0xfb0 ; /* 0x000000b000000947 */
/* 0x000fea0003800000 */
/*0f00*/ FSETP.NEU.FTZ.AND P0, PT, |R2|, +INF , PT ; /* 0x7f8000000200780b */
/* 0x000fda0003f1d200 */
/*0f10*/ @!P0 MOV R3, R2 ; /* 0x0000000200038202 */
/* 0x000fe20000000f00 */
/*0f20*/ @!P0 BRA 0xfb0 ; /* 0x0000008000008947 */
/* 0x000fea0003800000 */
/*0f30*/ FFMA R2, R2, 1.84467440737095516160e+19, RZ ; /* 0x5f80000002027823 */
/* 0x000fc800000000ff */
/*0f40*/ MUFU.RSQ R3, R2 ; /* 0x0000000200037308 */
/* 0x000e240000001400 */
/*0f50*/ FMUL.FTZ R5, R2, R3 ; /* 0x0000000302057220 */
/* 0x001fe40000410000 */
/*0f60*/ FMUL.FTZ R3, R3, 0.5 ; /* 0x3f00000003037820 */
/* 0x000fe40000410000 */
/*0f70*/ FADD.FTZ R4, -R5, -RZ ; /* 0x800000ff05047221 */
/* 0x000fc80000010100 */
/*0f80*/ FFMA R4, R5, R4, R2 ; /* 0x0000000405047223 */
/* 0x000fc80000000002 */
/*0f90*/ FFMA R3, R4, R3, R5 ; /* 0x0000000304037223 */
/* 0x000fc80000000005 */
/*0fa0*/ FMUL.FTZ R3, R3, 2.3283064365386962891e-10 ; /* 0x2f80000003037820 */
/* 0x000fca0000410000 */
/*0fb0*/ MOV R6, R3 ; /* 0x0000000300067202 */
/* 0x000fe20000000f00 */
/*0fc0*/ HFMA2.MMA R3, -RZ, RZ, 0, 0 ; /* 0x00000000ff037435 */
/* 0x000fe200000001ff */
/*0fd0*/ MOV R2, R7 ; /* 0x0000000700027202 */
/* 0x000fca0000000f00 */
/*0fe0*/ RET.REL.NODEC R2 0x0 ; /* 0xfffff01002007950 */
/* 0x000fea0003c3ffff */
/*0ff0*/ BRA 0xff0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*1000*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1010*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1020*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1030*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1040*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1050*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1060*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*1070*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void roi_logits_to_attrs_gpu_kernel(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
const float anchor_diag = sqrtf(powf(anchor_w, 2) + powf(anchor_l, 2));
int input_id = threadIdx.x + blockIdx.x * blockDim.x;
if (input_id < input_npoint) {
output_attrs[input_id * 7 + 0] = expf(input_logits[input_id * channels + 0]) * anchor_w;
output_attrs[input_id * 7 + 1] = expf(input_logits[input_id * channels + 1]) * anchor_l;
output_attrs[input_id * 7 + 2] = expf(input_logits[input_id * channels + 2]) * anchor_h;
output_attrs[input_id * 7 + 3] = input_logits[input_id * channels + 3] * anchor_diag + base_coors[input_id * 3 + 0];
output_attrs[input_id * 7 + 4] = input_logits[input_id * channels + 4] * anchor_diag + base_coors[input_id * 3 + 1];
output_attrs[input_id * 7 + 5] = input_logits[input_id * channels + 5] * anchor_h + base_coors[input_id * 3 + 2];
output_attrs[input_id * 7 + 6] = input_logits[input_id * channels + 6] * 3.1415927;
}
}
void roi_logits_to_attrs_gpu_launcher(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
if (input_npoint == 0)
return;
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, roi_logits_to_attrs_gpu_kernel, 0, input_npoint);
// Round up according to array size
gridSize = (input_npoint + blockSize - 1) / blockSize;
roi_logits_to_attrs_gpu_kernel<<<gridSize, blockSize>>>(input_npoint, channels,
anchor_w, anchor_l, anchor_h,
base_coors,
input_logits,
output_attrs);
} | .file "tmpxft_0012a196_00000000-6_roi_logits_to_attrs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf
.type _Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf, @function
_Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf, .-_Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf
.globl _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.type _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, @function
_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, .-_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.globl _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf
.type _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf, @function
_Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $280, %rsp
.cfi_def_cfa_offset 336
movss %xmm0, 12(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 20(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
testl %edi, %edi
jne .L24
.L11:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl %edi, %ebx
movl %esi, %r15d
movq %rdx, %rbp
movq %rcx, %r12
movq %r8, %r13
leaq 72(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L26
.L13:
movl %r14d, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
leal -1(%r14,%rbx), %eax
cltd
idivl %r14d
movl %eax, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L11
movq %r13, %r8
movq %r12, %rcx
movq %rbp, %rdx
movss 20(%rsp), %xmm2
movss 16(%rsp), %xmm1
movss 12(%rsp), %xmm0
movl %r15d, %esi
movl %ebx, %edi
call _Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf
jmp .L11
.L26:
leaq 76(%rsp), %rdi
movl 72(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L13
leaq 80(%rsp), %rdi
movl 72(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L13
leaq 84(%rsp), %rdi
movl 72(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L13
leaq 88(%rsp), %rdi
movl 72(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L13
leaq 112(%rsp), %rdi
leaq _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L13
movl 76(%rsp), %edi
movl 80(%rsp), %ecx
movl 136(%rsp), %eax
movl 84(%rsp), %edx
cmpl %edx, %eax
cmovg %edx, %eax
cmpl %ebx, %eax
cmovg %ebx, %eax
movl %eax, %esi
leal -1(%rcx,%rax), %eax
cltd
idivl %ecx
imull %ecx, %eax
testl %eax, %eax
jle .L18
movl $0, 24(%rsp)
movl $0, %edx
movl %r14d, 60(%rsp)
movl %edi, %r14d
movl %ebx, 28(%rsp)
movl %eax, %ebx
movl %r15d, 56(%rsp)
movl %ecx, %r15d
movq %rbp, 32(%rsp)
movq %r12, 40(%rsp)
movl %edx, %r12d
movq %r13, 48(%rsp)
movl %esi, %r13d
jmp .L15
.L14:
cmpl %r12d, %r14d
je .L20
subl %r15d, %ebx
testl %ebx, %ebx
jle .L27
.L15:
cmpl %ebx, %r13d
movl %ebx, %ebp
cmovle %r13d, %ebp
leaq 100(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebp, %edx
leaq _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L22
movl %ebp, %eax
imull 100(%rsp), %eax
cmpl %eax, %r12d
jge .L14
movl %eax, %r12d
movl %ebp, 24(%rsp)
jmp .L14
.L27:
movl 28(%rsp), %ebx
movl 56(%rsp), %r15d
movq 32(%rsp), %rbp
movq 40(%rsp), %r12
movq 48(%rsp), %r13
movl 24(%rsp), %r14d
jmp .L13
.L18:
movl $0, %r14d
jmp .L13
.L20:
movl 28(%rsp), %ebx
movl 56(%rsp), %r15d
movq 32(%rsp), %rbp
movq 40(%rsp), %r12
movq 48(%rsp), %r13
movl 24(%rsp), %r14d
jmp .L13
.L22:
movl 60(%rsp), %r14d
movl 28(%rsp), %ebx
movl 56(%rsp), %r15d
movq 32(%rsp), %rbp
movq 40(%rsp), %r12
movq 48(%rsp), %r13
jmp .L13
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf, .-_Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void roi_logits_to_attrs_gpu_kernel(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
const float anchor_diag = sqrtf(powf(anchor_w, 2) + powf(anchor_l, 2));
int input_id = threadIdx.x + blockIdx.x * blockDim.x;
if (input_id < input_npoint) {
output_attrs[input_id * 7 + 0] = expf(input_logits[input_id * channels + 0]) * anchor_w;
output_attrs[input_id * 7 + 1] = expf(input_logits[input_id * channels + 1]) * anchor_l;
output_attrs[input_id * 7 + 2] = expf(input_logits[input_id * channels + 2]) * anchor_h;
output_attrs[input_id * 7 + 3] = input_logits[input_id * channels + 3] * anchor_diag + base_coors[input_id * 3 + 0];
output_attrs[input_id * 7 + 4] = input_logits[input_id * channels + 4] * anchor_diag + base_coors[input_id * 3 + 1];
output_attrs[input_id * 7 + 5] = input_logits[input_id * channels + 5] * anchor_h + base_coors[input_id * 3 + 2];
output_attrs[input_id * 7 + 6] = input_logits[input_id * channels + 6] * 3.1415927;
}
}
void roi_logits_to_attrs_gpu_launcher(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
if (input_npoint == 0)
return;
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, roi_logits_to_attrs_gpu_kernel, 0, input_npoint);
// Round up according to array size
gridSize = (input_npoint + blockSize - 1) / blockSize;
roi_logits_to_attrs_gpu_kernel<<<gridSize, blockSize>>>(input_npoint, channels,
anchor_w, anchor_l, anchor_h,
base_coors,
input_logits,
output_attrs);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void roi_logits_to_attrs_gpu_kernel(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
const float anchor_diag = sqrtf(powf(anchor_w, 2) + powf(anchor_l, 2));
int input_id = threadIdx.x + blockIdx.x * blockDim.x;
if (input_id < input_npoint) {
output_attrs[input_id * 7 + 0] = expf(input_logits[input_id * channels + 0]) * anchor_w;
output_attrs[input_id * 7 + 1] = expf(input_logits[input_id * channels + 1]) * anchor_l;
output_attrs[input_id * 7 + 2] = expf(input_logits[input_id * channels + 2]) * anchor_h;
output_attrs[input_id * 7 + 3] = input_logits[input_id * channels + 3] * anchor_diag + base_coors[input_id * 3 + 0];
output_attrs[input_id * 7 + 4] = input_logits[input_id * channels + 4] * anchor_diag + base_coors[input_id * 3 + 1];
output_attrs[input_id * 7 + 5] = input_logits[input_id * channels + 5] * anchor_h + base_coors[input_id * 3 + 2];
output_attrs[input_id * 7 + 6] = input_logits[input_id * channels + 6] * 3.1415927;
}
}
void roi_logits_to_attrs_gpu_launcher(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
if (input_npoint == 0)
return;
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, roi_logits_to_attrs_gpu_kernel, 0, input_npoint);
// Round up according to array size
gridSize = (input_npoint + blockSize - 1) / blockSize;
roi_logits_to_attrs_gpu_kernel<<<gridSize, blockSize>>>(input_npoint, channels,
anchor_w, anchor_l, anchor_h,
base_coors,
input_logits,
output_attrs);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void roi_logits_to_attrs_gpu_kernel(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
const float anchor_diag = sqrtf(powf(anchor_w, 2) + powf(anchor_l, 2));
int input_id = threadIdx.x + blockIdx.x * blockDim.x;
if (input_id < input_npoint) {
output_attrs[input_id * 7 + 0] = expf(input_logits[input_id * channels + 0]) * anchor_w;
output_attrs[input_id * 7 + 1] = expf(input_logits[input_id * channels + 1]) * anchor_l;
output_attrs[input_id * 7 + 2] = expf(input_logits[input_id * channels + 2]) * anchor_h;
output_attrs[input_id * 7 + 3] = input_logits[input_id * channels + 3] * anchor_diag + base_coors[input_id * 3 + 0];
output_attrs[input_id * 7 + 4] = input_logits[input_id * channels + 4] * anchor_diag + base_coors[input_id * 3 + 1];
output_attrs[input_id * 7 + 5] = input_logits[input_id * channels + 5] * anchor_h + base_coors[input_id * 3 + 2];
output_attrs[input_id * 7 + 6] = input_logits[input_id * channels + 6] * 3.1415927;
}
}
void roi_logits_to_attrs_gpu_launcher(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
if (input_npoint == 0)
return;
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, roi_logits_to_attrs_gpu_kernel, 0, input_npoint);
// Round up according to array size
gridSize = (input_npoint + blockSize - 1) / blockSize;
roi_logits_to_attrs_gpu_kernel<<<gridSize, blockSize>>>(input_npoint, channels,
anchor_w, anchor_l, anchor_h,
base_coors,
input_logits,
output_attrs);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.globl _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.p2align 8
.type _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf,@function
_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x3c
s_load_b32 s3, s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e64 s3, v1
s_cbranch_execz .LBB0_2
s_clause 0x2
s_load_b128 s[4:7], s[0:1], 0x4
s_load_b128 s[8:11], s[0:1], 0x18
s_load_b64 s[0:1], s[0:1], 0x28
s_waitcnt lgkmcnt(0)
v_mul_lo_u32 v2, v1, s4
v_frexp_exp_i32_f32_e32 v22, s6
v_cmp_class_f32_e64 s4, s6, 0x204
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v3, 31, v2
v_lshlrev_b64 v[2:3], 2, v[2:3]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, s10, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
global_load_b32 v0, v[2:3], off
s_waitcnt vmcnt(0)
v_mul_f32_e32 v4, 0x3fb8aa3b, v0
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_fma_f32 v5, v0, 0x3fb8aa3b, -v4
v_rndne_f32_e32 v6, v4
v_dual_fmac_f32 v5, 0x32a5705f, v0 :: v_dual_sub_f32 v4, v4, v6
v_cvt_i32_f32_e32 v6, v6
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v4, v4, v5
v_exp_f32_e32 v5, v4
v_mul_lo_u32 v4, v1, 7
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v5, v6
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e32 v0, 0x7f800000, v6, vcc_lo
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
v_mul_f32_e32 v0, s5, v0
s_mov_b32 s1, 0x3e76c4e1
global_store_b32 v[4:5], v0, off
global_load_b32 v0, v[2:3], off offset:4
s_waitcnt vmcnt(0)
v_mul_f32_e32 v6, 0x3fb8aa3b, v0
v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_fma_f32 v7, v0, 0x3fb8aa3b, -v6
v_rndne_f32_e32 v8, v6
v_fmac_f32_e32 v7, 0x32a5705f, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v6, v6, v8
v_add_f32_e32 v6, v6, v7
v_cvt_i32_f32_e32 v7, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_exp_f32_e32 v6, v6
s_waitcnt_depctr 0xfff
v_ldexp_f32 v6, v6, v7
v_frexp_mant_f32_e64 v7, |s6|
v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v9, 0, 1, s0
v_ldexp_f32 v7, v7, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v9, 1.0, v7
v_add_f32_e32 v13, -1.0, v7
v_rcp_f32_e32 v11, v9
v_add_f32_e32 v18, -1.0, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_f32_e32 v7, v7, v18
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v15, v13, v11
v_mul_f32_e32 v19, v9, v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_fma_f32 v9, v15, v9, -v19
v_cndmask_b32_e32 v6, 0, v6, vcc_lo
v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v0
v_fmac_f32_e32 v9, v15, v7
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v7, v19, v9 :: v_dual_cndmask_b32 v0, 0x7f800000, v6
v_sub_f32_e32 v19, v7, v19
v_sub_f32_e32 v18, v13, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v0, s6, v0 :: v_dual_sub_f32 v9, v19, v9
v_sub_f32_e32 v13, v13, v18
global_store_b32 v[4:5], v0, off offset:4
global_load_b32 v6, v[2:3], off offset:8
v_frexp_mant_f32_e64 v0, |s5|
v_frexp_exp_i32_f32_e32 v19, s5
v_sub_f32_e32 v7, v13, v7
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v0
v_add_f32_e32 v7, v9, v7
v_cndmask_b32_e64 v8, 0, 1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v7, v18, v7
v_ldexp_f32 v0, v0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_mul_f32 v7, v11, v7 :: v_dual_add_f32 v8, 1.0, v0
v_add_f32_e32 v12, -1.0, v0
v_rcp_f32_e32 v10, v8
v_add_f32_e32 v16, -1.0, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v0, v16
s_waitcnt_depctr 0xfff
v_mul_f32_e32 v14, v12, v10
v_mul_f32_e32 v17, v8, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fma_f32 v8, v14, v8, -v17
v_fmac_f32_e32 v8, v14, v0
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v0, v17, v8 :: v_dual_mul_f32 v13, 0x3fb8aa3b, v6
v_sub_f32_e32 v16, v12, v0
v_sub_f32_e32 v17, v0, v17
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v12, v12, v16
v_sub_f32_e32 v8, v17, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v0, v12, v0
v_add_f32_e32 v0, v8, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_f32_e32 v0, v16, v0
v_rndne_f32_e32 v16, v13
v_mul_f32_e32 v8, v10, v0
v_lshl_add_u32 v0, v1, 1, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v9, v14, v8
v_sub_f32_e32 v1, v9, v14
v_mul_f32_e32 v11, v9, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_sub_f32_e32 v8, v8, v1
v_dual_add_f32 v10, v15, v7 :: v_dual_add_f32 v1, v8, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v12, v10, v15
v_mul_f32_e32 v14, v10, v10
v_fma_f32 v15, v9, v9, -v11
v_sub_f32_e32 v7, v7, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
v_fma_f32 v17, v10, v10, -v14
v_fma_f32 v12, v6, 0x3fb8aa3b, -v13
v_sub_f32_e32 v13, v13, v16
v_dual_fmac_f32 v15, v9, v1 :: v_dual_add_f32 v18, v7, v7
v_cvt_i32_f32_e32 v16, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_fmac_f32_e32 v12, 0x32a5705f, v6
v_ashrrev_i32_e32 v1, 31, v0
v_fmac_f32_e32 v17, v10, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[0:1], 2, v[0:1]
v_add_f32_e32 v18, v14, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmaak_f32 v21, s1, v18, 0x3e91f4c4 :: v_dual_add_f32 v12, v13, v12
v_dual_add_f32 v13, v11, v15 :: v_dual_sub_f32 v14, v18, v14
v_fmaak_f32 v21, v18, v21, 0x3ecccdef
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_exp_f32_e32 v12, v12
v_dual_fmaak_f32 v20, s1, v13, 0x3e91f4c4 :: v_dual_sub_f32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_sub_f32_e32 v14, v17, v14
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v6
v_dual_fmaak_f32 v20, v13, v20, 0x3ecccdef :: v_dual_sub_f32 v11, v15, v11
s_waitcnt_depctr 0xfff
v_ldexp_f32 v12, v12, v16
v_dual_mul_f32 v15, v13, v20 :: v_dual_mul_f32 v16, v18, v21
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v12, 0, v12, s1
v_fma_f32 v17, v13, v20, -v15
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_fma_f32 v23, v18, v21, -v16
v_cmp_nlt_f32_e64 s1, 0x42b17218, v6
v_fmac_f32_e32 v17, v11, v20
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v23, v14, v21
v_cndmask_b32_e64 v6, 0x7f800000, v12, s1
v_add_co_u32 v0, s1, s8, v0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_add_f32 v21, v15, v17 :: v_dual_add_f32 v24, v16, v23
v_add_co_ci_u32_e64 v1, s1, s9, v1, s1
v_sub_f32_e32 v15, v21, v15
v_add_f32_e32 v27, 0x3f2aaaaa, v21
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v29, 0x3f2aaaaa, v24
v_sub_f32_e32 v15, v17, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_mul_f32 v12, v9, v13 :: v_dual_add_f32 v17, 0xbf2aaaaa, v27
v_dual_mul_f32 v20, v10, v18 :: v_dual_add_f32 v15, 0x31739010, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fma_f32 v26, v13, v9, -v12
v_dual_sub_f32 v17, v21, v17 :: v_dual_sub_f32 v16, v24, v16
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v28, v18, v10, -v20
v_dual_fmac_f32 v26, v13, v8 :: v_dual_add_f32 v15, v15, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_dual_mul_f32 v6, s7, v6 :: v_dual_sub_f32 v13, v23, v16
v_ldexp_f32 v8, v8, 1
v_fmac_f32_e32 v26, v11, v9
v_add_f32_e32 v16, 0xbf2aaaaa, v29
s_delay_alu instid0(VALU_DEP_4)
v_dual_fmac_f32 v28, v18, v7 :: v_dual_add_f32 v11, 0x31739010, v13
v_ldexp_f32 v9, v9, 1
global_store_b32 v[4:5], v6, off offset:8
v_dual_sub_f32 v13, v24, v16 :: v_dual_fmac_f32 v28, v14, v10
v_subrev_co_ci_u32_e32 v16, vcc_lo, 0, v19, vcc_lo
v_subrev_co_ci_u32_e64 v17, vcc_lo, 0, v22, s0
s_delay_alu instid0(VALU_DEP_3)
v_add_f32_e32 v11, v11, v13
v_ldexp_f32 v10, v10, 1
global_load_b32 v6, v[2:3], off offset:12
global_load_b32 v25, v[0:1], off
v_ldexp_f32 v7, v7, 1
v_cmp_eq_f32_e64 s0, s5, 1.0
v_add_f32_e32 v18, v29, v11
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v14, v27, v15 :: v_dual_sub_f32 v23, v29, v18
v_sub_f32_e32 v21, v27, v14
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v11, v11, v23
v_add_f32_e32 v15, v15, v21
v_add_f32_e32 v19, v20, v28
v_add_f32_e32 v13, v12, v26
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v22, v13, v14
v_fma_f32 v21, v13, v14, -v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v24, v19, v18 :: v_dual_fmac_f32 v21, v13, v15
v_fma_f32 v23, v19, v18, -v24
v_sub_f32_e32 v12, v13, v12
v_cvt_f32_i32_e32 v13, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_fmac_f32 v23, v19, v11 :: v_dual_sub_f32 v12, v26, v12
v_sub_f32_e32 v20, v19, v20
v_cvt_f32_i32_e32 v11, v17
v_fmac_f32_e32 v21, v12, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v15, v28, v20 :: v_dual_mul_f32 v12, 0x3f317218, v13
v_dual_mul_f32 v14, 0x3f317218, v11 :: v_dual_fmac_f32 v23, v15, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v15, v22, v21
v_fma_f32 v16, v13, 0x3f317218, -v12
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_add_f32 v17, v24, v23 :: v_dual_sub_f32 v18, v15, v22
v_dual_add_f32 v19, v9, v15 :: v_dual_add_f32 v22, v10, v17
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v20, v17, v24 :: v_dual_sub_f32 v9, v19, v9
v_dual_sub_f32 v18, v21, v18 :: v_dual_sub_f32 v9, v15, v9
v_fma_f32 v15, v11, 0x3f317218, -v14
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v20, v23, v20 :: v_dual_fmac_f32 v15, 0xb102e308, v11
v_dual_sub_f32 v10, v22, v10 :: v_dual_add_f32 v7, v7, v20
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v8, v8, v18
v_dual_fmac_f32 v16, 0xb102e308, v13 :: v_dual_add_f32 v11, v14, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v10, v17, v10
v_add_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v9, v12, v16 :: v_dual_sub_f32 v14, v11, v14
v_add_f32_e32 v7, v7, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v14, v15, v14 :: v_dual_add_f32 v13, v22, v7
v_add_f32_e32 v18, v11, v13
v_dual_add_f32 v10, v19, v8 :: v_dual_sub_f32 v21, v13, v22
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v12, v9, v12 :: v_dual_sub_f32 v7, v7, v21
v_sub_f32_e32 v12, v16, v12
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_sub_f32_e32 v16, v10, v19
v_sub_f32_e32 v19, v18, v11
v_dual_add_f32 v17, v9, v10 :: v_dual_sub_f32 v8, v8, v16
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v13, v13, v19
v_sub_f32_e32 v20, v17, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v15, v17, v20 :: v_dual_sub_f32 v16, v18, v19
v_sub_f32_e32 v9, v9, v15
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_sub_f32_e32 v11, v11, v16
v_sub_f32_e32 v10, v10, v20
v_add_f32_e32 v15, v12, v8
v_add_f32_e32 v11, v13, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v10, v9
v_dual_add_f32 v10, v14, v7 :: v_dual_sub_f32 v13, v15, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_dual_add_f32 v9, v15, v9 :: v_dual_sub_f32 v16, v10, v14
v_dual_add_f32 v11, v10, v11 :: v_dual_sub_f32 v8, v8, v13
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_sub_f32 v15, v15, v13 :: v_dual_sub_f32 v10, v10, v16
v_dual_add_f32 v19, v17, v9 :: v_dual_sub_f32 v12, v12, v15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_f32_e32 v13, v18, v11
v_dual_sub_f32 v10, v14, v10 :: v_dual_sub_f32 v15, v19, v17
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v8, v8, v12
v_dual_sub_f32 v7, v7, v16 :: v_dual_sub_f32 v14, v13, v18
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
v_sub_f32_e32 v9, v9, v15
v_add_f32_e32 v7, v7, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_sub_f32_e32 v10, v11, v14
v_add_f32_e32 v8, v8, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_f32_e32 v9, v19, v8
v_add_f32_e32 v7, v7, v10
v_cndmask_b32_e64 v10, 2.0, 1.0, s0
v_cmp_eq_f32_e64 s0, s6, 1.0
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v14, v9, v19
v_add_f32_e32 v11, v13, v7
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_trunc_f32_e32 v20, v10
v_cndmask_b32_e64 v12, 2.0, 1.0, s0
v_mul_f32_e32 v21, 0.5, v10
v_sub_f32_e32 v8, v8, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_dual_mul_f32 v16, v12, v11 :: v_dual_sub_f32 v13, v11, v13
v_mul_f32_e32 v26, 0.5, v12
v_trunc_f32_e32 v23, v12
v_fma_f32 v11, v12, v11, -v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_sub_f32_e32 v7, v7, v13
v_trunc_f32_e32 v29, v26
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
v_cmp_eq_f32_e64 s0, v23, v12
v_fmac_f32_e32 v11, v12, v7
v_mul_f32_e32 v15, v10, v9
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
v_cmp_neq_f32_e64 s2, v29, v26
v_fma_f32 v9, v10, v9, -v15
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_dual_fmac_f32 v9, v10, v8 :: v_dual_add_f32 v8, v16, v11
v_cmp_class_f32_e64 vcc_lo, v15, 0x204
v_add_f32_e32 v7, v15, v9
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e32 v13, v7, v15, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v16, 0x204
v_cndmask_b32_e32 v14, v8, v16, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v13
v_sub_f32_e32 v8, v8, v16
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
v_cndmask_b32_e64 v17, 0, 0x37000000, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v14
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_sub_f32_e32 v8, v11, v8
v_cndmask_b32_e64 v18, 0, 0x37000000, vcc_lo
v_cmp_eq_f32_e32 vcc_lo, v20, v10
v_sub_f32_e32 v22, v14, v18
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mul_f32 v10, 0x3fb8aa3b, v22 :: v_dual_sub_f32 v7, v7, v15
v_fma_f32 v12, v22, 0x3fb8aa3b, -v10
v_sub_f32_e32 v19, v13, v17
v_rndne_f32_e32 v23, v10
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_fmac_f32_e32 v12, 0x32a5705f, v22
v_mul_f32_e32 v24, 0x3fb8aa3b, v19
s_delay_alu instid0(VALU_DEP_3)
v_sub_f32_e32 v10, v10, v23
v_trunc_f32_e32 v20, v21
v_sub_f32_e32 v7, v9, v7
v_cvt_i32_f32_e32 v11, v23
v_fma_f32 v27, v19, 0x3fb8aa3b, -v24
v_rndne_f32_e32 v28, v24
v_cmp_neq_f32_e64 s1, v20, v21
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_dual_add_f32 v10, v10, v12 :: v_dual_fmac_f32 v27, 0x32a5705f, v19
v_sub_f32_e32 v24, v24, v28
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
s_and_b32 s3, vcc_lo, s1
v_cmp_neq_f32_e64 s1, 0x7f800000, |v13|
v_exp_f32_e32 v10, v10
v_cvt_i32_f32_e32 v9, v28
v_add_f32_e32 v20, v24, v27
v_cndmask_b32_e64 v15, 0, s5, s3
v_cndmask_b32_e64 v7, 0, v7, s1
v_cmp_neq_f32_e64 s1, 0x7f800000, |v14|
s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
v_exp_f32_e32 v12, v20
v_cndmask_b32_e64 v8, 0, v8, s1
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v19
s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_ldexp_f32 v10, v10, v11
v_dual_add_f32 v7, v17, v7 :: v_dual_add_f32 v8, v18, v8
s_waitcnt_depctr 0xfff
v_ldexp_f32 v9, v12, v9
v_cndmask_b32_e64 v12, 1.0, s5, s3
v_cmp_eq_f32_e64 s3, s6, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e64 v9, 0, v9, s1
v_cmp_ngt_f32_e64 s1, 0xc2ce8ed0, v22
v_cndmask_b32_e64 v10, 0, v10, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v19
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_cndmask_b32_e64 v9, 0x7f800000, v9, s1
v_cmp_nlt_f32_e64 s1, 0x42b17218, v22
v_fma_f32 v7, v9, v7, v9
s_delay_alu instid0(VALU_DEP_2)
v_cndmask_b32_e64 v10, 0x7f800000, v10, s1
s_and_b32 s1, s0, s2
v_cmp_eq_f32_e64 s2, s5, 0
v_cndmask_b32_e64 v11, 0, s6, s1
v_cndmask_b32_e64 v13, 1.0, s6, s1
v_cmp_eq_f32_e64 s1, 0x7f800000, v9
v_fma_f32 v8, v10, v8, v10
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v7, v7, v9, s1
v_cmp_eq_f32_e64 s1, 0x7f800000, v10
v_cndmask_b32_e64 v9, 0x7f800000, 0, s2
v_bfi_b32 v7, 0x7fffffff, v7, v12
s_delay_alu instid0(VALU_DEP_3)
v_cndmask_b32_e64 v8, v8, v10, s1
v_cndmask_b32_e64 v10, 0x7f800000, 0, s3
v_cmp_class_f32_e64 s1, s5, 0x204
v_bfi_b32 v9, 0x7fffffff, v9, v15
v_cndmask_b32_e32 v12, 0x7fc00000, v7, vcc_lo
v_bfi_b32 v8, 0x7fffffff, v8, v13
v_cmp_lt_f32_e64 vcc_lo, s5, 0
v_bfi_b32 v10, 0x7fffffff, v10, v11
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
v_cndmask_b32_e64 v13, 0x7fc00000, v8, s0
v_cndmask_b32_e32 v7, v7, v12, vcc_lo
v_cmp_lt_f32_e64 vcc_lo, s6, 0
v_cndmask_b32_e32 v8, v8, v13, vcc_lo
s_or_b32 vcc_lo, s2, s1
s_mov_b32 s1, 0x400921fb
v_cndmask_b32_e32 v7, v7, v9, vcc_lo
s_or_b32 vcc_lo, s3, s4
v_cndmask_b32_e32 v8, v8, v10, vcc_lo
v_cmp_o_f32_e64 vcc_lo, s5, s5
s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
v_cmp_o_f32_e64 vcc_lo, s6, s6
v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_f32_e32 v7, v7, v8
v_mul_f32_e32 v8, 0x4f800000, v7
v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v7, v8, vcc_lo
v_sqrt_f32_e32 v8, v7
s_waitcnt_depctr 0xfff
v_add_nc_u32_e32 v9, -1, v8
v_add_nc_u32_e32 v10, 1, v8
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_fma_f32 v11, -v9, v8, v7
v_fma_f32 v12, -v10, v8, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_ge_f32_e64 s0, 0, v11
v_cndmask_b32_e64 v8, v8, v9, s0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_lt_f32_e64 s0, 0, v12
v_cndmask_b32_e64 v8, v8, v10, s0
s_mov_b32 s0, 0x5a7ed197
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f32_e32 v9, 0x37800000, v8
v_cndmask_b32_e32 v8, v8, v9, vcc_lo
v_cmp_class_f32_e64 vcc_lo, v7, 0x260
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cndmask_b32_e32 v7, v8, v7, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v25, v7, v6
global_store_b32 v[4:5], v25, off offset:12
global_load_b32 v6, v[2:3], off offset:16
global_load_b32 v8, v[0:1], off offset:4
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v8, v7, v6
global_store_b32 v[4:5], v8, off offset:16
global_load_b32 v6, v[2:3], off offset:20
global_load_b32 v0, v[0:1], off offset:8
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v0, s7, v6
global_store_b32 v[4:5], v0, off offset:20
global_load_b32 v0, v[2:3], off offset:24
s_waitcnt vmcnt(0)
v_cvt_f64_f32_e32 v[0:1], v0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mul_f64 v[0:1], v[0:1], s[0:1]
v_cvt_f32_f64_e32 v0, v[0:1]
global_store_b32 v[4:5], v0, off offset:24
.LBB0_2:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 304
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 30
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, .Lfunc_end0-_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: by_value
- .offset: 4
.size: 4
.value_kind: by_value
- .offset: 8
.size: 4
.value_kind: by_value
- .offset: 12
.size: 4
.value_kind: by_value
- .offset: 16
.size: 4
.value_kind: by_value
- .address_space: global
.offset: 24
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 32
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 40
.size: 8
.value_kind: global_buffer
- .offset: 48
.size: 4
.value_kind: hidden_block_count_x
- .offset: 52
.size: 4
.value_kind: hidden_block_count_y
- .offset: 56
.size: 4
.value_kind: hidden_block_count_z
- .offset: 60
.size: 2
.value_kind: hidden_group_size_x
- .offset: 62
.size: 2
.value_kind: hidden_group_size_y
- .offset: 64
.size: 2
.value_kind: hidden_group_size_z
- .offset: 66
.size: 2
.value_kind: hidden_remainder_x
- .offset: 68
.size: 2
.value_kind: hidden_remainder_y
- .offset: 70
.size: 2
.value_kind: hidden_remainder_z
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 104
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 112
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 304
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 30
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void roi_logits_to_attrs_gpu_kernel(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
const float anchor_diag = sqrtf(powf(anchor_w, 2) + powf(anchor_l, 2));
int input_id = threadIdx.x + blockIdx.x * blockDim.x;
if (input_id < input_npoint) {
output_attrs[input_id * 7 + 0] = expf(input_logits[input_id * channels + 0]) * anchor_w;
output_attrs[input_id * 7 + 1] = expf(input_logits[input_id * channels + 1]) * anchor_l;
output_attrs[input_id * 7 + 2] = expf(input_logits[input_id * channels + 2]) * anchor_h;
output_attrs[input_id * 7 + 3] = input_logits[input_id * channels + 3] * anchor_diag + base_coors[input_id * 3 + 0];
output_attrs[input_id * 7 + 4] = input_logits[input_id * channels + 4] * anchor_diag + base_coors[input_id * 3 + 1];
output_attrs[input_id * 7 + 5] = input_logits[input_id * channels + 5] * anchor_h + base_coors[input_id * 3 + 2];
output_attrs[input_id * 7 + 6] = input_logits[input_id * channels + 6] * 3.1415927;
}
}
void roi_logits_to_attrs_gpu_launcher(int input_npoint, int channels,
float anchor_w, float anchor_l, float anchor_h,
const float* base_coors,
const float* input_logits,
float* output_attrs) {
if (input_npoint == 0)
return;
int blockSize; // The launch configurator returned block size
int minGridSize; // The minimum grid size needed to achieve the maximum occupancy for a full device launch
int gridSize; // The actual grid size needed, based on input size
hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, roi_logits_to_attrs_gpu_kernel, 0, input_npoint);
// Round up according to array size
gridSize = (input_npoint + blockSize - 1) / blockSize;
roi_logits_to_attrs_gpu_kernel<<<gridSize, blockSize>>>(input_npoint, channels,
anchor_w, anchor_l, anchor_h,
base_coors,
input_logits,
output_attrs);
} | .text
.file "roi_logits_to_attrs.hip"
.globl _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf # -- Begin function _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.p2align 4, 0x90
.type _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf,@function
_Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf: # @_Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, .Lfunc_end0-_Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.cfi_endproc
# -- End function
.globl _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf # -- Begin function _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf
.p2align 4, 0x90
.type _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf,@function
_Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf: # @_Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB1_4
# %bb.1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movl %esi, %ebp
movl %edi, %r12d
movss %xmm0, 12(%rsp) # 4-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm2, 20(%rsp) # 4-byte Spill
leaq 124(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, %edx
xorl %ecx, %ecx
movl %r12d, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl 24(%rsp), %ecx
leal (%r12,%rcx), %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rax,%rdx), %rdi
orq %rdx, %rcx
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
movl %r12d, 44(%rsp)
movl %ebp, 40(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 36(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 32(%rsp)
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 28(%rsp)
movq %r15, 112(%rsp)
movq %r14, 104(%rsp)
movq %rbx, 96(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_4:
retq
.Lfunc_end1:
.size _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf, .Lfunc_end1-_Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf,@object # @_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.p2align 3, 0x0
_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf:
.quad _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.size _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012a196_00000000-6_roi_logits_to_attrs.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf
.type _Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf, @function
_Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf:
.LFB2082:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edi, 44(%rsp)
movl %esi, 40(%rsp)
movss %xmm0, 36(%rsp)
movss %xmm1, 32(%rsp)
movss %xmm2, 28(%rsp)
movq %rdx, 16(%rsp)
movq %rcx, 8(%rsp)
movq %r8, (%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 44(%rsp), %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 36(%rsp), %rax
movq %rax, 128(%rsp)
leaq 32(%rsp), %rax
movq %rax, 136(%rsp)
leaq 28(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 8(%rsp), %rax
movq %rax, 160(%rsp)
movq %rsp, %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf, .-_Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf
.globl _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.type _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, @function
_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, .-_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.globl _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf
.type _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf, @function
_Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $280, %rsp
.cfi_def_cfa_offset 336
movss %xmm0, 12(%rsp)
movss %xmm1, 16(%rsp)
movss %xmm2, 20(%rsp)
movq %fs:40, %rax
movq %rax, 264(%rsp)
xorl %eax, %eax
testl %edi, %edi
jne .L24
.L11:
movq 264(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $280, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
movl %edi, %ebx
movl %esi, %r15d
movq %rdx, %rbp
movq %rcx, %r12
movq %r8, %r13
leaq 72(%rsp), %rdi
call cudaGetDevice@PLT
testl %eax, %eax
je .L26
.L13:
movl %r14d, 100(%rsp)
movl $1, 104(%rsp)
movl $1, 108(%rsp)
leal -1(%r14,%rbx), %eax
cltd
idivl %r14d
movl %eax, 88(%rsp)
movl $1, 92(%rsp)
movl $1, 96(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 100(%rsp), %rdx
movl $1, %ecx
movq 88(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
jne .L11
movq %r13, %r8
movq %r12, %rcx
movq %rbp, %rdx
movss 20(%rsp), %xmm2
movss 16(%rsp), %xmm1
movss 12(%rsp), %xmm0
movl %r15d, %esi
movl %ebx, %edi
call _Z61__device_stub__Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_PfiifffPKfS0_Pf
jmp .L11
.L26:
leaq 76(%rsp), %rdi
movl 72(%rsp), %edx
movl $39, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L13
leaq 80(%rsp), %rdi
movl 72(%rsp), %edx
movl $10, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L13
leaq 84(%rsp), %rdi
movl 72(%rsp), %edx
movl $1, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L13
leaq 88(%rsp), %rdi
movl 72(%rsp), %edx
movl $16, %esi
call cudaDeviceGetAttribute@PLT
testl %eax, %eax
jne .L13
leaq 112(%rsp), %rdi
leaq _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf(%rip), %rsi
call cudaFuncGetAttributes@PLT
testl %eax, %eax
jne .L13
movl 76(%rsp), %edi
movl 80(%rsp), %ecx
movl 136(%rsp), %eax
movl 84(%rsp), %edx
cmpl %edx, %eax
cmovg %edx, %eax
cmpl %ebx, %eax
cmovg %ebx, %eax
movl %eax, %esi
leal -1(%rcx,%rax), %eax
cltd
idivl %ecx
imull %ecx, %eax
testl %eax, %eax
jle .L18
movl $0, 24(%rsp)
movl $0, %edx
movl %r14d, 60(%rsp)
movl %edi, %r14d
movl %ebx, 28(%rsp)
movl %eax, %ebx
movl %r15d, 56(%rsp)
movl %ecx, %r15d
movq %rbp, 32(%rsp)
movq %r12, 40(%rsp)
movl %edx, %r12d
movq %r13, 48(%rsp)
movl %esi, %r13d
jmp .L15
.L14:
cmpl %r12d, %r14d
je .L20
subl %r15d, %ebx
testl %ebx, %ebx
jle .L27
.L15:
cmpl %ebx, %r13d
movl %ebx, %ebp
cmovle %r13d, %ebp
leaq 100(%rsp), %rdi
movl $0, %r8d
movl $0, %ecx
movl %ebp, %edx
leaq _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf(%rip), %rsi
call cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
testl %eax, %eax
jne .L22
movl %ebp, %eax
imull 100(%rsp), %eax
cmpl %eax, %r12d
jge .L14
movl %eax, %r12d
movl %ebp, 24(%rsp)
jmp .L14
.L27:
movl 28(%rsp), %ebx
movl 56(%rsp), %r15d
movq 32(%rsp), %rbp
movq 40(%rsp), %r12
movq 48(%rsp), %r13
movl 24(%rsp), %r14d
jmp .L13
.L18:
movl $0, %r14d
jmp .L13
.L20:
movl 28(%rsp), %ebx
movl 56(%rsp), %r15d
movq 32(%rsp), %rbp
movq 40(%rsp), %r12
movq 48(%rsp), %r13
movl 24(%rsp), %r14d
jmp .L13
.L22:
movl 60(%rsp), %r14d
movl 28(%rsp), %ebx
movl 56(%rsp), %r15d
movq 32(%rsp), %rbp
movq 40(%rsp), %r12
movq 48(%rsp), %r13
jmp .L13
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf, .-_Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "roi_logits_to_attrs.hip"
.globl _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf # -- Begin function _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.p2align 4, 0x90
.type _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf,@function
_Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf: # @_Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.cfi_startproc
# %bb.0:
subq $168, %rsp
.cfi_def_cfa_offset 176
movl %edi, 20(%rsp)
movl %esi, 16(%rsp)
movss %xmm0, 12(%rsp)
movss %xmm1, 8(%rsp)
movss %xmm2, 4(%rsp)
movq %rdx, 88(%rsp)
movq %rcx, 80(%rsp)
movq %r8, 72(%rsp)
leaq 20(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
leaq 88(%rsp), %rax
movq %rax, 136(%rsp)
leaq 80(%rsp), %rax
movq %rax, 144(%rsp)
leaq 72(%rsp), %rax
movq %rax, 152(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $184, %rsp
.cfi_adjust_cfa_offset -184
retq
.Lfunc_end0:
.size _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, .Lfunc_end0-_Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.cfi_endproc
# -- End function
.globl _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf # -- Begin function _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf
.p2align 4, 0x90
.type _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf,@function
_Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf: # @_Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf
.cfi_startproc
# %bb.0:
testl %edi, %edi
je .LBB1_4
# %bb.1:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $192, %rsp
.cfi_def_cfa_offset 240
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbx
movq %rcx, %r14
movq %rdx, %r15
movl %esi, %ebp
movl %edi, %r12d
movss %xmm0, 12(%rsp) # 4-byte Spill
movss %xmm1, 16(%rsp) # 4-byte Spill
movss %xmm2, 20(%rsp) # 4-byte Spill
leaq 124(%rsp), %rdi
leaq 24(%rsp), %rsi
movl $_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, %edx
xorl %ecx, %ecx
movl %r12d, %r8d
callq hipOccupancyMaxPotentialBlockSize
movl 24(%rsp), %ecx
leal (%r12,%rcx), %eax
decl %eax
cltd
idivl %ecx
# kill: def $eax killed $eax def $rax
movabsq $4294967296, %rdx # imm = 0x100000000
leaq (%rax,%rdx), %rdi
orq %rdx, %rcx
movl $1, %esi
movq %rcx, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_3
# %bb.2:
movl %r12d, 44(%rsp)
movl %ebp, 40(%rsp)
movss 12(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 36(%rsp)
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 32(%rsp)
movss 20(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
movss %xmm0, 28(%rsp)
movq %r15, 112(%rsp)
movq %r14, 104(%rsp)
movq %rbx, 96(%rsp)
leaq 44(%rsp), %rax
movq %rax, 128(%rsp)
leaq 40(%rsp), %rax
movq %rax, 136(%rsp)
leaq 36(%rsp), %rax
movq %rax, 144(%rsp)
leaq 32(%rsp), %rax
movq %rax, 152(%rsp)
leaq 28(%rsp), %rax
movq %rax, 160(%rsp)
leaq 112(%rsp), %rax
movq %rax, 168(%rsp)
leaq 104(%rsp), %rax
movq %rax, 176(%rsp)
leaq 96(%rsp), %rax
movq %rax, 184(%rsp)
leaq 80(%rsp), %rdi
leaq 64(%rsp), %rsi
leaq 56(%rsp), %rdx
leaq 48(%rsp), %rcx
callq __hipPopCallConfiguration
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
movq 64(%rsp), %rcx
movl 72(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, %edi
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
pushq 64(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_3:
addq $192, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.cfi_restore %rbp
.LBB1_4:
retq
.Lfunc_end1:
.size _Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf, .Lfunc_end1-_Z32roi_logits_to_attrs_gpu_launcheriifffPKfS0_Pf
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf,@object # @_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.section .rodata,"a",@progbits
.globl _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.p2align 3, 0x0
_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf:
.quad _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.size _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf"
.size .L__unnamed_1, 48
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z45__device_stub__roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z30roi_logits_to_attrs_gpu_kerneliifffPKfS0_Pf
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <iostream>
#include <stdio.h>
using namespace std;
int main(int argc, char *argv[]) {
std::string salt = "";
std::string password = "";
if (argc < 3) {
std::cout << "!!! ERROR !!! Please enter salt and password strings as arguments !!!\n";
return EXIT_FAILURE;
}
salt = argv[1];
password = argv[2];
if (salt.length() != 8) {
std::cout << "!!! ERROR !!! Salt must be eight characters long !!!\n";
return EXIT_FAILURE;
}
salt = "$6$" + salt + "$";
string testHash = crypt((char*) password.c_str(), (char*) salt.c_str());
testHash = testHash.substr(0,76) + "$";
cout << "User entered information...\n";
cout << "Salt: " << salt << endl;
cout << "Password: " << password << endl;
cout << "Calculated hash...\n";
cout << testHash << endl;
return EXIT_SUCCESS;
} | code for sm_80 |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <iostream>
#include <stdio.h>
using namespace std;
int main(int argc, char *argv[]) {
std::string salt = "";
std::string password = "";
if (argc < 3) {
std::cout << "!!! ERROR !!! Please enter salt and password strings as arguments !!!\n";
return EXIT_FAILURE;
}
salt = argv[1];
password = argv[2];
if (salt.length() != 8) {
std::cout << "!!! ERROR !!! Salt must be eight characters long !!!\n";
return EXIT_FAILURE;
}
salt = "$6$" + salt + "$";
string testHash = crypt((char*) password.c_str(), (char*) salt.c_str());
testHash = testHash.substr(0,76) + "$";
cout << "User entered information...\n";
cout << "Salt: " << salt << endl;
cout << "Password: " << password << endl;
cout << "Calculated hash...\n";
cout << testHash << endl;
return EXIT_SUCCESS;
} | .file "tmpxft_0015ae12_00000000-6_CreateHash.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3688:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3688:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3711:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3711:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .rodata._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "basic_string: construction from null is not valid"
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC5IS3_EEPKcRKS3_,comdat
.align 2
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, @function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_:
.LFB4012:
.cfi_startproc
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $24, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
leaq 16(%rdi), %r12
movq %r12, (%rdi)
testq %rsi, %rsi
je .L14
movq %rdi, %rbx
movq %rsi, %r13
movq %rsi, %rdi
call strlen@PLT
movq %rax, %rbp
movq %rax, (%rsp)
cmpq $15, %rax
ja .L15
cmpq $1, %rax
jne .L10
movzbl 0(%r13), %eax
movb %al, 16(%rbx)
.L11:
movq (%rsp), %rax
movq %rax, 8(%rbx)
movq (%rbx), %rdx
movb $0, (%rdx,%rax)
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L16
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L17
leaq .LC0(%rip), %rdi
call _ZSt19__throw_logic_errorPKc@PLT
.L17:
call __stack_chk_fail@PLT
.L15:
movq %rsp, %rsi
movl $0, %edx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm@PLT
movq %rax, %r12
movq %rax, (%rbx)
movq (%rsp), %rax
movq %rax, 16(%rbx)
.L9:
movq %rbp, %rdx
movq %r13, %rsi
movq %r12, %rdi
call memcpy@PLT
jmp .L11
.L10:
testq %rax, %rax
je .L11
jmp .L9
.L16:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE4012:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_, .-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.set _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_
.section .rodata.str1.1,"aMS",@progbits,1
.LC1:
.string ""
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "!!! ERROR !!! Please enter salt and password strings as arguments !!!\n"
.align 8
.LC3:
.string "!!! ERROR !!! Salt must be eight characters long !!!\n"
.section .rodata.str1.1
.LC4:
.string "basic_string::append"
.LC5:
.string "$6$"
.LC6:
.string "$"
.LC7:
.string "User entered information...\n"
.LC8:
.string "Salt: "
.LC9:
.string "Password: "
.LC10:
.string "Calculated hash...\n"
.text
.globl main
.type main, @function
main:
.LFB3682:
.cfi_startproc
.cfi_personality 0x9b,DW.ref.__gxx_personality_v0
.cfi_lsda 0x1b,.LLSDA3682
endbr64
pushq %r13
.cfi_def_cfa_offset 16
.cfi_offset 13, -16
pushq %r12
.cfi_def_cfa_offset 24
.cfi_offset 12, -24
pushq %rbp
.cfi_def_cfa_offset 32
.cfi_offset 6, -32
pushq %rbx
.cfi_def_cfa_offset 40
.cfi_offset 3, -40
subq $200, %rsp
.cfi_def_cfa_offset 240
movl %edi, %ebp
movq %rsi, %rbx
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
leaq 15(%rsp), %r13
leaq 16(%rsp), %rdi
movq %r13, %rdx
leaq .LC1(%rip), %r12
movq %r12, %rsi
.LEHB0:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE0:
leaq 48(%rsp), %rdi
movq %r13, %rdx
movq %r12, %rsi
.LEHB1:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE1:
cmpl $2, %ebp
jle .L48
movq 8(%rbx), %rsi
leaq 16(%rsp), %rdi
.LEHB2:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKc@PLT
jmp .L49
.L48:
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
jmp .L50
.L49:
movq 16(%rbx), %rsi
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6assignEPKc@PLT
cmpq $8, 24(%rsp)
je .L21
leaq .LC3(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
.LEHE2:
jmp .L51
.L21:
movq 16(%rsp), %rbx
leaq 112(%rsp), %rdi
leaq 128(%rsp), %rax
movq %rax, 112(%rsp)
movq $0, 120(%rsp)
movb $0, 128(%rsp)
movl $11, %esi
.LEHB3:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm@PLT
movabsq $4611686018427387903, %rax
subq 120(%rsp), %rax
cmpq $2, %rax
jbe .L52
leaq 112(%rsp), %rdi
movl $3, %edx
leaq .LC5(%rip), %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L53
.L52:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L54
leaq .LC4(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.L42:
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L28:
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L32:
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
je .L33
call __stack_chk_fail@PLT
.L54:
call __stack_chk_fail@PLT
.L53:
movabsq $4611686018427387903, %rax
subq 120(%rsp), %rax
cmpq $7, %rax
jbe .L55
leaq 112(%rsp), %rdi
movl $8, %edx
movq %rbx, %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_appendEPKcm@PLT
jmp .L56
.L55:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L57
leaq .LC4(%rip), %rdi
call _ZSt20__throw_length_errorPKc@PLT
.LEHE3:
.L57:
call __stack_chk_fail@PLT
.L56:
leaq 112(%rsp), %rdi
leaq .LC6(%rip), %rsi
.LEHB4:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKc@PLT
.LEHE4:
movq %rax, %rsi
leaq 144(%rsp), %rbx
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EOS4_@PLT
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_@PLT
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 16(%rsp), %rsi
movq 48(%rsp), %rdi
call crypt@PLT
movq %rax, %rsi
leaq 15(%rsp), %rdx
leaq 80(%rsp), %rdi
.LEHB5:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1IS3_EEPKcRKS3_
.LEHE5:
leaq 112(%rsp), %rdi
leaq 80(%rsp), %rsi
movl $76, %ecx
movl $0, %edx
.LEHB6:
call _ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6substrEmm@PLT
.LEHE6:
leaq 112(%rsp), %rdi
leaq .LC6(%rip), %rsi
.LEHB7:
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKc@PLT
.LEHE7:
movq %rax, %rsi
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC1EOS4_@PLT
leaq 80(%rsp), %rdi
movq %rbx, %rsi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_@PLT
movq %rbx, %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq .LC7(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
.LEHB8:
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
leaq .LC8(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC9(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
leaq .LC10(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
movq %rax, %rdi
call _ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
.LEHE8:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movl $0, %ebx
jmp .L20
.L50:
movl $1, %ebx
.L20:
leaq 48(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
leaq 16(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L58
movl %ebx, %eax
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %rbp
.cfi_def_cfa_offset 24
popq %r12
.cfi_def_cfa_offset 16
popq %r13
.cfi_def_cfa_offset 8
ret
.L51:
.cfi_restore_state
movl $1, %ebx
jmp .L20
.L39:
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L28
.L40:
endbr64
movq %rax, %rbx
leaq 112(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
.L31:
leaq 80(%rsp), %rdi
call _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@PLT
jmp .L28
.L41:
endbr64
movq %rax, %rbx
jmp .L31
.L38:
endbr64
movq %rax, %rbx
jmp .L28
.L37:
endbr64
movq %rax, %rbx
jmp .L32
.L33:
movq %rbx, %rdi
.LEHB9:
call _Unwind_Resume@PLT
.LEHE9:
.L58:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3682:
.globl __gxx_personality_v0
.section .gcc_except_table,"a",@progbits
.LLSDA3682:
.byte 0xff
.byte 0xff
.byte 0x1
.uleb128 .LLSDACSE3682-.LLSDACSB3682
.LLSDACSB3682:
.uleb128 .LEHB0-.LFB3682
.uleb128 .LEHE0-.LEHB0
.uleb128 0
.uleb128 0
.uleb128 .LEHB1-.LFB3682
.uleb128 .LEHE1-.LEHB1
.uleb128 .L37-.LFB3682
.uleb128 0
.uleb128 .LEHB2-.LFB3682
.uleb128 .LEHE2-.LEHB2
.uleb128 .L38-.LFB3682
.uleb128 0
.uleb128 .LEHB3-.LFB3682
.uleb128 .LEHE3-.LEHB3
.uleb128 .L42-.LFB3682
.uleb128 0
.uleb128 .LEHB4-.LFB3682
.uleb128 .LEHE4-.LEHB4
.uleb128 .L39-.LFB3682
.uleb128 0
.uleb128 .LEHB5-.LFB3682
.uleb128 .LEHE5-.LEHB5
.uleb128 .L38-.LFB3682
.uleb128 0
.uleb128 .LEHB6-.LFB3682
.uleb128 .LEHE6-.LEHB6
.uleb128 .L41-.LFB3682
.uleb128 0
.uleb128 .LEHB7-.LFB3682
.uleb128 .LEHE7-.LEHB7
.uleb128 .L40-.LFB3682
.uleb128 0
.uleb128 .LEHB8-.LFB3682
.uleb128 .LEHE8-.LEHB8
.uleb128 .L41-.LFB3682
.uleb128 0
.uleb128 .LEHB9-.LFB3682
.uleb128 .LEHE9-.LEHB9
.uleb128 0
.uleb128 0
.LLSDACSE3682:
.text
.size main, .-main
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.hidden DW.ref.__gxx_personality_v0
.weak DW.ref.__gxx_personality_v0
.section .data.rel.local.DW.ref.__gxx_personality_v0,"awG",@progbits,DW.ref.__gxx_personality_v0,comdat
.align 8
.type DW.ref.__gxx_personality_v0, @object
.size DW.ref.__gxx_personality_v0, 8
DW.ref.__gxx_personality_v0:
.quad __gxx_personality_v0
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <iostream>
#include <stdio.h>
using namespace std;
int main(int argc, char *argv[]) {
std::string salt = "";
std::string password = "";
if (argc < 3) {
std::cout << "!!! ERROR !!! Please enter salt and password strings as arguments !!!\n";
return EXIT_FAILURE;
}
salt = argv[1];
password = argv[2];
if (salt.length() != 8) {
std::cout << "!!! ERROR !!! Salt must be eight characters long !!!\n";
return EXIT_FAILURE;
}
salt = "$6$" + salt + "$";
string testHash = crypt((char*) password.c_str(), (char*) salt.c_str());
testHash = testHash.substr(0,76) + "$";
cout << "User entered information...\n";
cout << "Salt: " << salt << endl;
cout << "Password: " << password << endl;
cout << "Calculated hash...\n";
cout << testHash << endl;
return EXIT_SUCCESS;
} | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <iostream>
#include <stdio.h>
using namespace std;
int main(int argc, char *argv[]) {
std::string salt = "";
std::string password = "";
if (argc < 3) {
std::cout << "!!! ERROR !!! Please enter salt and password strings as arguments !!!\n";
return EXIT_FAILURE;
}
salt = argv[1];
password = argv[2];
if (salt.length() != 8) {
std::cout << "!!! ERROR !!! Salt must be eight characters long !!!\n";
return EXIT_FAILURE;
}
salt = "$6$" + salt + "$";
string testHash = crypt((char*) password.c_str(), (char*) salt.c_str());
testHash = testHash.substr(0,76) + "$";
cout << "User entered information...\n";
cout << "Salt: " << salt << endl;
cout << "Password: " << password << endl;
cout << "Calculated hash...\n";
cout << testHash << endl;
return EXIT_SUCCESS;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <iostream>
#include <stdio.h>
using namespace std;
int main(int argc, char *argv[]) {
std::string salt = "";
std::string password = "";
if (argc < 3) {
std::cout << "!!! ERROR !!! Please enter salt and password strings as arguments !!!\n";
return EXIT_FAILURE;
}
salt = argv[1];
password = argv[2];
if (salt.length() != 8) {
std::cout << "!!! ERROR !!! Salt must be eight characters long !!!\n";
return EXIT_FAILURE;
}
salt = "$6$" + salt + "$";
string testHash = crypt((char*) password.c_str(), (char*) salt.c_str());
testHash = testHash.substr(0,76) + "$";
cout << "User entered information...\n";
cout << "Salt: " << salt << endl;
cout << "Password: " << password << endl;
cout << "Calculated hash...\n";
cout << testHash << endl;
return EXIT_SUCCESS;
} | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include <iostream>
#include <stdio.h>
using namespace std;
int main(int argc, char *argv[]) {
std::string salt = "";
std::string password = "";
if (argc < 3) {
std::cout << "!!! ERROR !!! Please enter salt and password strings as arguments !!!\n";
return EXIT_FAILURE;
}
salt = argv[1];
password = argv[2];
if (salt.length() != 8) {
std::cout << "!!! ERROR !!! Salt must be eight characters long !!!\n";
return EXIT_FAILURE;
}
salt = "$6$" + salt + "$";
string testHash = crypt((char*) password.c_str(), (char*) salt.c_str());
testHash = testHash.substr(0,76) + "$";
cout << "User entered information...\n";
cout << "Salt: " << salt << endl;
cout << "Password: " << password << endl;
cout << "Calculated hash...\n";
cout << testHash << endl;
return EXIT_SUCCESS;
} | .text
.file "CreateHash.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.Lfunc_begin0:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception0
# %bb.0: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
leaq 120(%rsp), %rbp
movq %rbp, 104(%rsp)
movq $0, 112(%rsp)
movb $0, 120(%rsp)
leaq 152(%rsp), %r12
movq %r12, 136(%rsp)
movq $0, 144(%rsp)
movb $0, 152(%rsp)
cmpl $3, %edi
jge .LBB0_2
# %bb.1:
movl $70, %edx
movl $.L.str.1, %esi
jmp .LBB0_12
.LBB0_2:
movq %rsi, %rbx
movq 8(%rsi), %r14
movq 112(%rsp), %r15
movq %r14, %rdi
callq strlen
.Ltmp0:
leaq 104(%rsp), %rdi
xorl %esi, %esi
movq %r15, %rdx
movq %r14, %rcx
movq %rax, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.Ltmp1:
# %bb.3: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEPKc.exit
movq 16(%rbx), %rbx
movq 144(%rsp), %r14
movq %rbx, %rdi
callq strlen
.Ltmp2:
leaq 136(%rsp), %rdi
xorl %esi, %esi
movq %r14, %rdx
movq %rbx, %rcx
movq %rax, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.Ltmp3:
# %bb.4: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEPKc.exit35
movq 112(%rsp), %r8
cmpq $8, %r8
jne .LBB0_11
# %bb.5:
movq 104(%rsp), %rcx
.Ltmp4:
leaq 40(%rsp), %rdi
leaq 72(%rsp), %r9
movl $.L.str.3, %esi
movl $3, %edx
callq _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.Ltmp5:
# %bb.6: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_RKS8_.exit
movabsq $9223372036854775807, %r13 # imm = 0x7FFFFFFFFFFFFFFF
movq 48(%rsp), %rsi
cmpq %r13, %rsi
je .LBB0_111
# %bb.7: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
leaq 1(%rsi), %rbx
movq 40(%rsp), %rax
leaq 56(%rsp), %r14
movl $15, %ecx
cmpq %r14, %rax
je .LBB0_9
# %bb.8: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
movq 56(%rsp), %rcx
.LBB0_9: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i
cmpq %rcx, %rbx
jbe .LBB0_13
# %bb.10:
.Ltmp7:
leaq 40(%rsp), %rdi
movl $.L.str.4, %ecx
movl $1, %r8d
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp8:
jmp .LBB0_14
.LBB0_11:
movl $53, %edx
movl $.L.str.2, %esi
.LBB0_12: # %.invoke
movl $1, %ebx
.Ltmp70:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp71:
jmp .LBB0_102
.LBB0_13:
movb $36, (%rax,%rsi)
.LBB0_14: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKc.exit.i
movq %rbx, 48(%rsp)
movq 40(%rsp), %rax
movb $0, (%rax,%rbx)
leaq 24(%rsp), %rbx
movq %rbx, 8(%rsp)
movq 40(%rsp), %rax
cmpq %r14, %rax
je .LBB0_16
# %bb.15: # %.critedge.i.i
movq %rax, 8(%rsp)
movq 56(%rsp), %rax
movq %rax, 24(%rsp)
jmp .LBB0_17
.LBB0_16: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i
movq 48(%rsp), %rdx
incq %rdx
movq %rbx, %rdi
movq %r14, %rsi
callq memcpy@PLT
.LBB0_17: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEOS8_PKS5_.exit
movq 48(%rsp), %rdx
movq %rdx, 16(%rsp)
movq %r14, 40(%rsp)
movq $0, 48(%rsp)
movb $0, 56(%rsp)
movq 104(%rsp), %rdi
movq 8(%rsp), %rsi
cmpq %rbx, %rsi
je .LBB0_21
# %bb.18: # %.critedge.i
movq 120(%rsp), %rax
movq %rsi, 104(%rsp)
movq %rdx, 112(%rsp)
movq 24(%rsp), %rcx
movq %rcx, 120(%rsp)
cmpq %rbp, %rdi
je .LBB0_24
# %bb.19: # %.critedge.i
testq %rdi, %rdi
je .LBB0_24
# %bb.20:
movq %rdi, 8(%rsp)
movq %rax, 24(%rsp)
jmp .LBB0_27
.LBB0_21: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit23.i
testq %rdx, %rdx
je .LBB0_26
# %bb.22: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit23.i
cmpq $1, %rdx
jne .LBB0_25
# %bb.23:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB0_26
.LBB0_24:
movq %rbx, 8(%rsp)
jmp .LBB0_27
.LBB0_25:
callq memcpy@PLT
.LBB0_26: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit.i
movq 16(%rsp), %rax
movq %rax, 112(%rsp)
movq 104(%rsp), %rcx
movb $0, (%rcx,%rax)
.LBB0_27: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_.exit
movq $0, 16(%rsp)
movq 8(%rsp), %rax
movb $0, (%rax)
movq 8(%rsp), %rdi
cmpq %rbx, %rdi
je .LBB0_29
# %bb.28: # %.critedge.i.i41
callq _ZdlPv
.LBB0_29: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq 40(%rsp), %rdi
cmpq %r14, %rdi
je .LBB0_31
# %bb.30: # %.critedge.i.i43
callq _ZdlPv
.LBB0_31: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit45
movq 136(%rsp), %rdi
movq 104(%rsp), %rsi
callq crypt
movq %rbx, 8(%rsp)
testq %rax, %rax
je .LBB0_113
# %bb.32:
movq %rax, %r15
movq %rax, %rdi
callq strlen
movq %rax, %r12
cmpq $16, %rax
jb .LBB0_37
# %bb.33:
testq %r12, %r12
js .LBB0_117
# %bb.34:
movq %r12, %rdi
incq %rdi
js .LBB0_107
# %bb.35: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit.i.i46
.Ltmp9:
callq _Znwm
.Ltmp10:
# %bb.36: # %.noexc52
movq %rax, 8(%rsp)
movq %r12, 24(%rsp)
.LBB0_37:
testq %r12, %r12
je .LBB0_41
# %bb.38:
movq 8(%rsp), %rdi
cmpq $1, %r12
jne .LBB0_40
# %bb.39:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB0_41
.LBB0_40:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB0_41: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2IS3_EEPKcRKS3_.exit53
movq %r13, %rbx
movq %r12, 16(%rsp)
movq 8(%rsp), %rax
movb $0, (%rax,%r12)
leaq 88(%rsp), %r15
movq %r15, 72(%rsp)
movq 8(%rsp), %r13
movq 16(%rsp), %rax
cmpq $76, %rax
movl $76, %r12d
cmovbq %rax, %r12
cmpq $16, %rax
jb .LBB0_44
# %bb.42:
leaq 1(%r12), %rdi
.Ltmp11:
callq _Znwm
.Ltmp12:
# %bb.43: # %.noexc124
movq %rax, 72(%rsp)
movq %r12, 88(%rsp)
.LBB0_44:
testq %r12, %r12
je .LBB0_48
# %bb.45:
movq 72(%rsp), %rdi
cmpq $1, %r12
jne .LBB0_47
# %bb.46:
movzbl (%r13), %eax
movb %al, (%rdi)
jmp .LBB0_48
.LBB0_47:
movq %r13, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB0_48: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEC2ERKS4_mm.exit
movq %r12, 80(%rsp)
movq 72(%rsp), %rax
movb $0, (%rax,%r12)
movq 80(%rsp), %rsi
cmpq %rbx, %rsi
je .LBB0_115
# %bb.49: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i55
leaq 1(%rsi), %r12
movq 72(%rsp), %rax
movl $15, %ecx
cmpq %r15, %rax
leaq 24(%rsp), %rbx
je .LBB0_51
# %bb.50: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i55
movq 88(%rsp), %rcx
.LBB0_51: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i.i55
cmpq %rcx, %r12
jbe .LBB0_53
# %bb.52:
.Ltmp14:
leaq 72(%rsp), %rdi
movl $.L.str.4, %ecx
movl $1, %r8d
xorl %edx, %edx
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp15:
jmp .LBB0_54
.LBB0_53:
movb $36, (%rax,%rsi)
.LBB0_54: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKc.exit.i60
movq %r12, 80(%rsp)
movq 72(%rsp), %rax
movb $0, (%rax,%r12)
movq %r14, 40(%rsp)
movq 72(%rsp), %rax
cmpq %r15, %rax
je .LBB0_56
# %bb.55: # %.critedge.i.i61
movq %rax, 40(%rsp)
movq 88(%rsp), %rax
movq %rax, 56(%rsp)
jmp .LBB0_57
.LBB0_56: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit.i.i62
movq 80(%rsp), %rdx
incq %rdx
movq %r14, %rdi
movq %r15, %rsi
callq memcpy@PLT
.LBB0_57: # %_ZStplIcSt11char_traitsIcESaIcEENSt7__cxx1112basic_stringIT_T0_T1_EEOS8_PKS5_.exit65
leaq 152(%rsp), %r12
movq 80(%rsp), %rdx
movq %rdx, 48(%rsp)
movq %r15, 72(%rsp)
movq $0, 80(%rsp)
movb $0, 88(%rsp)
movq 8(%rsp), %rdi
movq 40(%rsp), %rsi
cmpq %r14, %rsi
je .LBB0_61
# %bb.58: # %.critedge.i67
movq 24(%rsp), %rax
movq %rsi, 8(%rsp)
movq %rdx, 16(%rsp)
movq 56(%rsp), %rcx
movq %rcx, 24(%rsp)
cmpq %rbx, %rdi
je .LBB0_64
# %bb.59: # %.critedge.i67
testq %rdi, %rdi
je .LBB0_64
# %bb.60:
movq %rdi, 40(%rsp)
movq %rax, 56(%rsp)
jmp .LBB0_67
.LBB0_61: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit23.i70
testq %rdx, %rdx
je .LBB0_66
# %bb.62: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_is_localEv.exit23.i70
cmpq $1, %rdx
jne .LBB0_65
# %bb.63:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB0_66
.LBB0_64:
movq %r14, 40(%rsp)
jmp .LBB0_67
.LBB0_65:
callq memcpy@PLT
.LBB0_66: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit.i71
movq 48(%rsp), %rax
movq %rax, 16(%rsp)
movq 8(%rsp), %rcx
movb $0, (%rcx,%rax)
.LBB0_67: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEaSEOS4_.exit72
movq $0, 48(%rsp)
movq 40(%rsp), %rax
movb $0, (%rax)
movq 40(%rsp), %rdi
cmpq %r14, %rdi
je .LBB0_69
# %bb.68: # %.critedge.i.i73
callq _ZdlPv
.LBB0_69: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit75
movq 72(%rsp), %rdi
cmpq %r15, %rdi
je .LBB0_71
# %bb.70: # %.critedge.i.i76
callq _ZdlPv
.LBB0_71: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit78
.Ltmp16:
movl $_ZSt4cout, %edi
movl $.L.str.5, %esi
movl $28, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp17:
# %bb.72: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit80
.Ltmp18:
movl $_ZSt4cout, %edi
movl $.L.str.6, %esi
movl $6, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp19:
# %bb.73: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit82
movq 104(%rsp), %rsi
movq 112(%rsp), %rdx
.Ltmp20:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp21:
# %bb.74: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_109
# %bb.75: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i
cmpb $0, 56(%r15)
je .LBB0_77
# %bb.76:
movzbl 67(%r15), %eax
jmp .LBB0_79
.LBB0_77:
.Ltmp22:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp23:
# %bb.78: # %.noexc127
movq (%r15), %rax
.Ltmp24:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp25:
.LBB0_79: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i
.Ltmp26:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp27:
# %bb.80: # %.noexc129
.Ltmp28:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp29:
# %bb.81: # %_ZNSolsEPFRSoS_E.exit
.Ltmp30:
movl $_ZSt4cout, %edi
movl $.L.str.7, %esi
movl $10, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp31:
# %bb.82: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit86
movq 136(%rsp), %rsi
movq 144(%rsp), %rdx
.Ltmp32:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp33:
# %bb.83: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit88
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_109
# %bb.84: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i132
cmpb $0, 56(%r15)
je .LBB0_86
# %bb.85:
movzbl 67(%r15), %eax
jmp .LBB0_88
.LBB0_86:
.Ltmp34:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp35:
# %bb.87: # %.noexc137
movq (%r15), %rax
.Ltmp36:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp37:
.LBB0_88: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i134
.Ltmp38:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp39:
# %bb.89: # %.noexc139
.Ltmp40:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp41:
# %bb.90: # %_ZNSolsEPFRSoS_E.exit90
.Ltmp42:
movl $_ZSt4cout, %edi
movl $.L.str.8, %esi
movl $19, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp43:
# %bb.91: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit92
movq 8(%rsp), %rsi
movq 16(%rsp), %rdx
.Ltmp44:
movl $_ZSt4cout, %edi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.Ltmp45:
# %bb.92: # %_ZStlsIcSt11char_traitsIcESaIcEERSt13basic_ostreamIT_T0_ES7_RKNSt7__cxx1112basic_stringIS4_S5_T1_EE.exit94
movq %rax, %r14
movq (%rax), %rax
movq -24(%rax), %rax
movq 240(%r14,%rax), %r15
testq %r15, %r15
je .LBB0_109
# %bb.93: # %_ZSt13__check_facetISt5ctypeIcEERKT_PS3_.exit.i.i143
cmpb $0, 56(%r15)
je .LBB0_95
# %bb.94:
movzbl 67(%r15), %eax
jmp .LBB0_97
.LBB0_95:
.Ltmp46:
movq %r15, %rdi
callq _ZNKSt5ctypeIcE13_M_widen_initEv
.Ltmp47:
# %bb.96: # %.noexc148
movq (%r15), %rax
.Ltmp48:
movq %r15, %rdi
movl $10, %esi
callq *48(%rax)
.Ltmp49:
.LBB0_97: # %_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc.exit.i145
.Ltmp50:
movsbl %al, %esi
movq %r14, %rdi
callq _ZNSo3putEc
.Ltmp51:
# %bb.98: # %.noexc150
.Ltmp52:
movq %rax, %rdi
callq _ZNSo5flushEv
.Ltmp53:
# %bb.99: # %_ZNSolsEPFRSoS_E.exit96
movq 8(%rsp), %rdi
cmpq %rbx, %rdi
je .LBB0_101
# %bb.100: # %.critedge.i.i97
callq _ZdlPv
.LBB0_101: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit99
xorl %ebx, %ebx
.LBB0_102: # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
movq 136(%rsp), %rdi
cmpq %r12, %rdi
je .LBB0_104
# %bb.103: # %.critedge.i.i109
callq _ZdlPv
.LBB0_104: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit111
movq 104(%rsp), %rdi
cmpq %rbp, %rdi
je .LBB0_106
# %bb.105: # %.critedge.i.i112
callq _ZdlPv
.LBB0_106: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit114
movl %ebx, %eax
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB0_107: # %.noexc11.i47
.cfi_def_cfa_offset 224
.Ltmp60:
callq _ZSt17__throw_bad_allocv
.Ltmp61:
# %bb.108: # %.noexc51
.LBB0_109: # %.invoke155
.Ltmp54:
callq _ZSt16__throw_bad_castv
.Ltmp55:
# %bb.110: # %.cont
.LBB0_111:
.Ltmp67:
movl $.L.str.12, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp68:
# %bb.112: # %.noexc39
.LBB0_113:
.Ltmp64:
movl $.L.str.9, %edi
callq _ZSt19__throw_logic_errorPKc
.Ltmp65:
# %bb.114: # %.noexc49
.LBB0_115:
.Ltmp57:
movl $.L.str.12, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp58:
# %bb.116: # %.noexc63
.LBB0_117: # %.noexc.i48
.Ltmp62:
movl $.L.str.10, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp63:
# %bb.118: # %.noexc50
.LBB0_119:
.Ltmp13:
jmp .LBB0_127
.LBB0_120:
.Ltmp6:
jmp .LBB0_131
.LBB0_121:
.Ltmp59:
movq %rax, %r14
movq 72(%rsp), %rdi
cmpq %r15, %rdi
je .LBB0_128
# %bb.122: # %.critedge.i.i103
callq _ZdlPv
jmp .LBB0_128
.LBB0_123:
.Ltmp69:
movq %rax, %r14
movq 40(%rsp), %rdi
leaq 56(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_132
jmp .LBB0_124
.LBB0_125:
.Ltmp72:
jmp .LBB0_131
.LBB0_126:
.Ltmp56:
.LBB0_127:
movq %rax, %r14
.LBB0_128:
movq 8(%rsp), %rdi
leaq 24(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_132
.LBB0_124: # %.critedge.i.i100
callq _ZdlPv
jmp .LBB0_132
.LBB0_130:
.Ltmp66:
.LBB0_131:
movq %rax, %r14
.LBB0_132:
movq 136(%rsp), %rdi
leaq 152(%rsp), %rax
cmpq %rax, %rdi
je .LBB0_134
# %bb.133: # %.critedge.i.i115
callq _ZdlPv
.LBB0_134: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit117
movq 104(%rsp), %rdi
cmpq %rbp, %rdi
je .LBB0_136
# %bb.135: # %.critedge.i.i118
callq _ZdlPv
.LBB0_136: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit120
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
.section .gcc_except_table,"a",@progbits
.p2align 2, 0x0
GCC_except_table0:
.Lexception0:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end0-.Lcst_begin0
.Lcst_begin0:
.uleb128 .Ltmp0-.Lfunc_begin0 # >> Call Site 1 <<
.uleb128 .Ltmp3-.Ltmp0 # Call between .Ltmp0 and .Ltmp3
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp4-.Lfunc_begin0 # >> Call Site 2 <<
.uleb128 .Ltmp5-.Ltmp4 # Call between .Ltmp4 and .Ltmp5
.uleb128 .Ltmp6-.Lfunc_begin0 # jumps to .Ltmp6
.byte 0 # On action: cleanup
.uleb128 .Ltmp7-.Lfunc_begin0 # >> Call Site 3 <<
.uleb128 .Ltmp8-.Ltmp7 # Call between .Ltmp7 and .Ltmp8
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp70-.Lfunc_begin0 # >> Call Site 4 <<
.uleb128 .Ltmp71-.Ltmp70 # Call between .Ltmp70 and .Ltmp71
.uleb128 .Ltmp72-.Lfunc_begin0 # jumps to .Ltmp72
.byte 0 # On action: cleanup
.uleb128 .Ltmp71-.Lfunc_begin0 # >> Call Site 5 <<
.uleb128 .Ltmp9-.Ltmp71 # Call between .Ltmp71 and .Ltmp9
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp9-.Lfunc_begin0 # >> Call Site 6 <<
.uleb128 .Ltmp10-.Ltmp9 # Call between .Ltmp9 and .Ltmp10
.uleb128 .Ltmp66-.Lfunc_begin0 # jumps to .Ltmp66
.byte 0 # On action: cleanup
.uleb128 .Ltmp10-.Lfunc_begin0 # >> Call Site 7 <<
.uleb128 .Ltmp11-.Ltmp10 # Call between .Ltmp10 and .Ltmp11
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp11-.Lfunc_begin0 # >> Call Site 8 <<
.uleb128 .Ltmp12-.Ltmp11 # Call between .Ltmp11 and .Ltmp12
.uleb128 .Ltmp13-.Lfunc_begin0 # jumps to .Ltmp13
.byte 0 # On action: cleanup
.uleb128 .Ltmp12-.Lfunc_begin0 # >> Call Site 9 <<
.uleb128 .Ltmp14-.Ltmp12 # Call between .Ltmp12 and .Ltmp14
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp14-.Lfunc_begin0 # >> Call Site 10 <<
.uleb128 .Ltmp15-.Ltmp14 # Call between .Ltmp14 and .Ltmp15
.uleb128 .Ltmp59-.Lfunc_begin0 # jumps to .Ltmp59
.byte 0 # On action: cleanup
.uleb128 .Ltmp15-.Lfunc_begin0 # >> Call Site 11 <<
.uleb128 .Ltmp16-.Ltmp15 # Call between .Ltmp15 and .Ltmp16
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp16-.Lfunc_begin0 # >> Call Site 12 <<
.uleb128 .Ltmp53-.Ltmp16 # Call between .Ltmp16 and .Ltmp53
.uleb128 .Ltmp56-.Lfunc_begin0 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp60-.Lfunc_begin0 # >> Call Site 13 <<
.uleb128 .Ltmp61-.Ltmp60 # Call between .Ltmp60 and .Ltmp61
.uleb128 .Ltmp66-.Lfunc_begin0 # jumps to .Ltmp66
.byte 0 # On action: cleanup
.uleb128 .Ltmp54-.Lfunc_begin0 # >> Call Site 14 <<
.uleb128 .Ltmp55-.Ltmp54 # Call between .Ltmp54 and .Ltmp55
.uleb128 .Ltmp56-.Lfunc_begin0 # jumps to .Ltmp56
.byte 0 # On action: cleanup
.uleb128 .Ltmp67-.Lfunc_begin0 # >> Call Site 15 <<
.uleb128 .Ltmp68-.Ltmp67 # Call between .Ltmp67 and .Ltmp68
.uleb128 .Ltmp69-.Lfunc_begin0 # jumps to .Ltmp69
.byte 0 # On action: cleanup
.uleb128 .Ltmp64-.Lfunc_begin0 # >> Call Site 16 <<
.uleb128 .Ltmp65-.Ltmp64 # Call between .Ltmp64 and .Ltmp65
.uleb128 .Ltmp66-.Lfunc_begin0 # jumps to .Ltmp66
.byte 0 # On action: cleanup
.uleb128 .Ltmp57-.Lfunc_begin0 # >> Call Site 17 <<
.uleb128 .Ltmp58-.Ltmp57 # Call between .Ltmp57 and .Ltmp58
.uleb128 .Ltmp59-.Lfunc_begin0 # jumps to .Ltmp59
.byte 0 # On action: cleanup
.uleb128 .Ltmp62-.Lfunc_begin0 # >> Call Site 18 <<
.uleb128 .Ltmp63-.Ltmp62 # Call between .Ltmp62 and .Ltmp63
.uleb128 .Ltmp66-.Lfunc_begin0 # jumps to .Ltmp66
.byte 0 # On action: cleanup
.uleb128 .Ltmp63-.Lfunc_begin0 # >> Call Site 19 <<
.uleb128 .Lfunc_end0-.Ltmp63 # Call between .Ltmp63 and .Lfunc_end0
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end0:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movq 8(%rdi), %rax
movq %rdx, %rdi
subq %rax, %rdi
movabsq $9223372036854775807, %r9 # imm = 0x7FFFFFFFFFFFFFFF
addq %rdi, %r9
cmpq %r8, %r9
jb .LBB1_19
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
movq %r8, %r15
subq %rdx, %r15
addq %rax, %r15
movq (%rbx), %rdi
leaq 16(%rbx), %r10
movl $15, %r9d
cmpq %r10, %rdi
je .LBB1_3
# %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
movq 16(%rbx), %r9
.LBB1_3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit
cmpq %r9, %r15
jbe .LBB1_4
# %bb.17:
movq %rbx, %rdi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
jmp .LBB1_18
.LBB1_4:
leaq (%rdi,%rsi), %r14
addq %rdx, %rsi
movq %rax, %r9
subq %rsi, %r9
cmpq %rcx, %rdi
ja .LBB1_6
# %bb.5:
addq %rax, %rdi
cmpq %rcx, %rdi
jae .LBB1_16
.LBB1_6:
cmpq %rdx, %r8
je .LBB1_12
# %bb.7:
cmpq %rsi, %rax
je .LBB1_12
# %bb.8:
testq %r9, %r9
je .LBB1_12
# %bb.9:
leaq (%r14,%r8), %rdi
addq %r14, %rdx
cmpq $1, %r9
jne .LBB1_11
# %bb.10:
movzbl (%rdx), %eax
movb %al, (%rdi)
.LBB1_12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit
testq %r8, %r8
je .LBB1_18
.LBB1_13: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_moveEPcPKcm.exit
cmpq $1, %r8
jne .LBB1_15
# %bb.14:
movzbl (%rcx), %eax
movb %al, (%r14)
jmp .LBB1_18
.LBB1_15:
movq %r14, %rdi
movq %rcx, %rsi
movq %r8, %rdx
callq memcpy@PLT
.LBB1_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movq %rbx, %rax
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB1_11:
.cfi_def_cfa_offset 48
movq %rdx, %rsi
movq %r9, %rdx
movq %r8, %r12
movq %rcx, %r13
callq memmove@PLT
movq %r13, %rcx
movq %r12, %r8
testq %r8, %r8
jne .LBB1_13
jmp .LBB1_18
.LBB1_16:
movq %rbx, %rdi
movq %r14, %rsi
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_replace_coldEPcmPKcmm
jmp .LBB1_18
.LBB1_19:
movl $.L.str.11, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end1:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm, .Lfunc_end1-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEmmPKcm
.cfi_endproc
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %rbp
movq %rcx, 32(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %rbx
movq (%rdi), %r14
movq 8(%rdi), %r12
movq %r8, (%rsp) # 8-byte Spill
movq %rdx, 16(%rsp) # 8-byte Spill
subq %rdx, %rbp
leaq 16(%rdi), %rcx
movl $15, %eax
cmpq %rcx, %r14
je .LBB2_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB2_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
addq %r12, %rbp
js .LBB2_26
# %bb.3:
cmpq %rax, %rbp
jbe .LBB2_6
# %bb.4:
addq %rax, %rax
cmpq %rax, %rbp
jae .LBB2_6
# %bb.5:
movabsq $9223372036854775807, %rbp # imm = 0x7FFFFFFFFFFFFFFF
cmpq %rbp, %rax
cmovbq %rax, %rbp
.LBB2_6:
movq %rbp, %rdi
incq %rdi
js .LBB2_27
# %bb.7: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
movq %rcx, 24(%rsp) # 8-byte Spill
callq _Znwm
movq %rax, %r13
testq %r15, %r15
je .LBB2_11
# %bb.8: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
cmpq $1, %r15
jne .LBB2_10
# %bb.9:
movzbl (%r14), %eax
movb %al, (%r13)
jmp .LBB2_11
.LBB2_10:
movq %r13, %rdi
movq %r14, %rsi
movq %r15, %rdx
callq memcpy@PLT
.LBB2_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
movq %r14, 8(%rsp) # 8-byte Spill
movq 16(%rsp), %rax # 8-byte Reload
leaq (%rax,%r15), %r14
movq 32(%rsp), %rsi # 8-byte Reload
testq %rsi, %rsi
movq (%rsp), %rdx # 8-byte Reload
je .LBB2_18
# %bb.12: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
testq %rdx, %rdx
je .LBB2_18
# %bb.13:
je .LBB2_18
# %bb.14:
leaq (%r15,%r13), %rdi
cmpq $1, %rdx
jne .LBB2_16
# %bb.15:
movzbl (%rsi), %eax
movb %al, (%rdi)
jmp .LBB2_17
.LBB2_16:
callq memcpy@PLT
.LBB2_17: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
movq (%rsp), %rdx # 8-byte Reload
.LBB2_18: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit26
cmpq %r14, %r12
je .LBB2_23
# %bb.19:
subq %r14, %r12
je .LBB2_23
# %bb.20:
movq %r13, %rdi
addq %r15, %rdi
addq %rdx, %rdi
addq 8(%rsp), %r15 # 8-byte Folded Reload
addq 16(%rsp), %r15 # 8-byte Folded Reload
cmpq $1, %r12
jne .LBB2_22
# %bb.21:
movzbl (%r15), %eax
movb %al, (%rdi)
jmp .LBB2_23
.LBB2_22:
movq %r15, %rsi
movq %r12, %rdx
callq memcpy@PLT
.LBB2_23: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit27
movq 8(%rsp), %rdi # 8-byte Reload
cmpq 24(%rsp), %rdi # 8-byte Folded Reload
je .LBB2_25
# %bb.24: # %.critedge.i
callq _ZdlPv
.LBB2_25: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r13, (%rbx)
movq %rbp, 16(%rbx)
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB2_27:
.cfi_def_cfa_offset 96
callq _ZSt17__throw_bad_allocv
.LBB2_26:
movl $.L.str.10, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end2:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm, .Lfunc_end2-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.cfi_endproc
# -- End function
.section .text._ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,"axG",@progbits,_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,comdat
.weak _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE # -- Begin function _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.p2align 4, 0x90
.type _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,@function
_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE: # @_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.Lfunc_begin1:
.cfi_startproc
.cfi_personality 3, __gxx_personality_v0
.cfi_lsda 3, .Lexception1
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r14
movq %rcx, 8(%rsp) # 8-byte Spill
movq %rdx, %r12
movq %rsi, 16(%rsp) # 8-byte Spill
movq %rdi, %rbx
leaq 16(%rdi), %rbp
movq %rbp, (%rdi)
movq $0, 8(%rdi)
movb $0, 16(%rdi)
leaq (%r8,%rdx), %rsi
.Ltmp73:
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.Ltmp74:
# %bb.1:
movabsq $9223372036854775807, %r15 # imm = 0x7FFFFFFFFFFFFFFF
movq 8(%rbx), %rsi
movq %r15, %rax
subq %rsi, %rax
cmpq %r12, %rax
jb .LBB3_11
# %bb.2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
leaq (%rsi,%r12), %r13
movq (%rbx), %rdi
movl $15, %eax
cmpq %rbp, %rdi
je .LBB3_4
# %bb.3: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
movq (%rbp), %rax
.LBB3_4: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i
cmpq %rax, %r13
jbe .LBB3_5
# %bb.9:
.Ltmp75:
movq %rbx, %rdi
xorl %edx, %edx
movq 16(%rsp), %rcx # 8-byte Reload
movq %r12, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp76:
jmp .LBB3_10
.LBB3_5:
testq %r12, %r12
je .LBB3_10
# %bb.6:
addq %rsi, %rdi
cmpq $1, %r12
jne .LBB3_8
# %bb.7:
movq 16(%rsp), %rax # 8-byte Reload
movzbl (%rax), %eax
movb %al, (%rdi)
jmp .LBB3_10
.LBB3_8:
movq 16(%rsp), %rsi # 8-byte Reload
movq %r12, %rdx
callq memcpy@PLT
.LBB3_10: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.exit
movq %r13, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r13)
movq 8(%rbx), %rsi
subq %rsi, %r15
cmpq %r14, %r15
jb .LBB3_11
# %bb.13: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
leaq (%rsi,%r14), %r15
movq (%rbx), %rdi
movl $15, %eax
cmpq %rbp, %rdi
je .LBB3_15
# %bb.14: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
movq (%rbp), %rax
.LBB3_15: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE15_M_check_lengthEmmPKc.exit.i10
cmpq %rax, %r15
jbe .LBB3_16
# %bb.20:
.Ltmp77:
movq %rbx, %rdi
xorl %edx, %edx
movq 8(%rsp), %rcx # 8-byte Reload
movq %r14, %r8
callq _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_mutateEmmPKcm
.Ltmp78:
jmp .LBB3_21
.LBB3_16:
testq %r14, %r14
je .LBB3_21
# %bb.17:
addq %rsi, %rdi
cmpq $1, %r14
jne .LBB3_19
# %bb.18:
movq 8(%rsp), %rax # 8-byte Reload
movzbl (%rax), %eax
movb %al, (%rdi)
jmp .LBB3_21
.LBB3_19:
movq 8(%rsp), %rsi # 8-byte Reload
movq %r14, %rdx
callq memcpy@PLT
.LBB3_21: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE6appendEPKcm.exit17
movq %r15, 8(%rbx)
movq (%rbx), %rax
movb $0, (%rax,%r15)
movq %rbx, %rax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB3_11: # %.invoke
.cfi_def_cfa_offset 80
.Ltmp79:
movl $.L.str.12, %edi
callq _ZSt20__throw_length_errorPKc
.Ltmp80:
# %bb.12: # %.cont
.LBB3_22:
.Ltmp81:
movq %rax, %r14
movq (%rbx), %rdi
cmpq %rbp, %rdi
je .LBB3_24
# %bb.23: # %.critedge.i.i
callq _ZdlPv
.LBB3_24: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEED2Ev.exit
movq %r14, %rdi
callq _Unwind_Resume@PLT
.Lfunc_end3:
.size _ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE, .Lfunc_end3-_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE
.cfi_endproc
.section .gcc_except_table._ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,"aG",@progbits,_ZSt12__str_concatINSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEEET_PKNS6_10value_typeENS6_9size_typeES9_SA_RKNS6_14allocator_typeE,comdat
.p2align 2, 0x0
GCC_except_table3:
.Lexception1:
.byte 255 # @LPStart Encoding = omit
.byte 255 # @TType Encoding = omit
.byte 1 # Call site Encoding = uleb128
.uleb128 .Lcst_end1-.Lcst_begin1
.Lcst_begin1:
.uleb128 .Ltmp73-.Lfunc_begin1 # >> Call Site 1 <<
.uleb128 .Ltmp76-.Ltmp73 # Call between .Ltmp73 and .Ltmp76
.uleb128 .Ltmp81-.Lfunc_begin1 # jumps to .Ltmp81
.byte 0 # On action: cleanup
.uleb128 .Ltmp76-.Lfunc_begin1 # >> Call Site 2 <<
.uleb128 .Ltmp77-.Ltmp76 # Call between .Ltmp76 and .Ltmp77
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp77-.Lfunc_begin1 # >> Call Site 3 <<
.uleb128 .Ltmp78-.Ltmp77 # Call between .Ltmp77 and .Ltmp78
.uleb128 .Ltmp81-.Lfunc_begin1 # jumps to .Ltmp81
.byte 0 # On action: cleanup
.uleb128 .Ltmp78-.Lfunc_begin1 # >> Call Site 4 <<
.uleb128 .Ltmp79-.Ltmp78 # Call between .Ltmp78 and .Ltmp79
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.uleb128 .Ltmp79-.Lfunc_begin1 # >> Call Site 5 <<
.uleb128 .Ltmp80-.Ltmp79 # Call between .Ltmp79 and .Ltmp80
.uleb128 .Ltmp81-.Lfunc_begin1 # jumps to .Ltmp81
.byte 0 # On action: cleanup
.uleb128 .Ltmp80-.Lfunc_begin1 # >> Call Site 6 <<
.uleb128 .Lfunc_end3-.Ltmp80 # Call between .Ltmp80 and .Lfunc_end3
.byte 0 # has no landing pad
.byte 0 # On action: cleanup
.Lcst_end1:
.p2align 2, 0x0
# -- End function
.section .text._ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,"axG",@progbits,_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,comdat
.weak _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm # -- Begin function _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.p2align 4, 0x90
.type _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm,@function
_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm: # @_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.cfi_startproc
# %bb.0: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movq %rdi, %rbx
movq (%rdi), %r14
leaq 16(%rdi), %r12
movl $15, %eax
cmpq %r12, %r14
je .LBB4_2
# %bb.1: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
movq 16(%rbx), %rax
.LBB4_2: # %_ZNKSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE8capacityEv.exit
cmpq %rsi, %rax
jae .LBB4_12
# %bb.3:
testq %rsi, %rsi
js .LBB4_13
# %bb.4:
addq %rax, %rax
movabsq $9223372036854775807, %r13 # imm = 0x7FFFFFFFFFFFFFFF
cmpq %r13, %rax
cmovbq %rax, %r13
cmpq %rsi, %rax
cmovbeq %rsi, %r13
movq %r13, %rdi
incq %rdi
js .LBB4_14
# %bb.5: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
callq _Znwm
movq %rax, %r15
movq 8(%rbx), %rdx
cmpq $-1, %rdx
je .LBB4_9
# %bb.6: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE9_M_createERmm.exit
testq %rdx, %rdx
jne .LBB4_8
# %bb.7:
movzbl (%r14), %eax
movb %al, (%r15)
.LBB4_9: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7_S_copyEPcPKcm.exit
cmpq %r12, %r14
je .LBB4_11
.LBB4_10: # %.critedge.i
movq %r14, %rdi
callq _ZdlPv
.LBB4_11: # %_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv.exit
movq %r15, (%rbx)
movq %r13, 16(%rbx)
.LBB4_12:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.LBB4_8:
.cfi_def_cfa_offset 48
incq %rdx
movq %r15, %rdi
movq %r14, %rsi
callq memcpy@PLT
cmpq %r12, %r14
jne .LBB4_10
jmp .LBB4_11
.LBB4_14:
callq _ZSt17__throw_bad_allocv
.LBB4_13:
movl $.L.str.10, %edi
callq _ZSt20__throw_length_errorPKc
.Lfunc_end4:
.size _ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm, .Lfunc_end4-_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE7reserveEm
.cfi_endproc
# -- End function
.type .L.str.1,@object # @.str.1
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.1:
.asciz "!!! ERROR !!! Please enter salt and password strings as arguments !!!\n"
.size .L.str.1, 71
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "!!! ERROR !!! Salt must be eight characters long !!!\n"
.size .L.str.2, 54
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "$6$"
.size .L.str.3, 4
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "$"
.size .L.str.4, 2
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "User entered information...\n"
.size .L.str.5, 29
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Salt: "
.size .L.str.6, 7
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Password: "
.size .L.str.7, 11
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Calculated hash...\n"
.size .L.str.8, 20
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "basic_string: construction from null is not valid"
.size .L.str.9, 50
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "basic_string::_M_create"
.size .L.str.10, 24
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "basic_string::_M_replace"
.size .L.str.11, 25
.type .L.str.12,@object # @.str.12
.L.str.12:
.asciz "basic_string::append"
.size .L.str.12, 21
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __gxx_personality_v0
.addrsig_sym _Unwind_Resume
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80 | .text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.amdgpu_metadata
---
amdhsa.kernels: []
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <assert.h>
#include <iostream>
#include <chrono>
// CUDA runtime
#include <cuda_runtime.h>
#include <curand.h>
template <int BLOCK_SIZE> __global__ void MatrixMulCUDA(float *C, float *A, float *B, int wA, int wB) {
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = wA * BLOCK_SIZE * by;
int aEnd = aBegin + wA - 1;
int aStep = BLOCK_SIZE;
int bBegin = BLOCK_SIZE * bx;
int bStep = BLOCK_SIZE * wB;
float Csub = 0;
for (int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = A[a + wA * ty + tx];
Bs[ty][tx] = B[b + wB * ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
#pragma unroll
for (int k = 0; k < BLOCK_SIZE; ++k) {
Csub += As[ty][k] * Bs[k][tx];
}
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = wB * BLOCK_SIZE * by + BLOCK_SIZE * bx;
C[c + wB * ty + tx] = Csub;
}
void GPU_fill_rand(float *A, int nr_rows_A, int nr_cols_A) {
// Create a pseudo-random number generator
curandGenerator_t prng;
curandCreateGenerator(&prng, CURAND_RNG_PSEUDO_DEFAULT);
// Set the seed for the random number generator using the system clock
curandSetPseudoRandomGeneratorSeed(prng, (unsigned long long) clock());
// Fill the array with random numbers on the device
curandGenerateUniform(prng, A, nr_rows_A * nr_cols_A);
}
int MatrixMultiply(int argc, char **argv,
int block_size, const dim3 &dimsA,
const dim3 &dimsB) {
// Allocate host memory for matrices A and B
unsigned int size_A = dimsA.x * dimsA.y;
unsigned int mem_size_A = sizeof(float) * size_A;
float *h_A = reinterpret_cast<float *>(malloc(mem_size_A));
unsigned int size_B = dimsB.x * dimsB.y;
unsigned int mem_size_B = sizeof(float) * size_B;
float *h_B = reinterpret_cast<float *>(malloc(mem_size_B));
// Allocate device memory
float *d_A, *d_B, *d_C;
// Allocate host matrix C
dim3 dimsC(dimsB.x, dimsA.y, 1);
unsigned int mem_size_C = dimsC.x * dimsC.y * sizeof(float);
float *h_C = reinterpret_cast<float *>(malloc(mem_size_C));
float *h_C_test = reinterpret_cast<float *>(malloc(mem_size_C));
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
h_C_test[i]=0;
}
if (h_C == NULL) {
fprintf(stderr, "Failed to allocate host matrix C!\n");
exit(EXIT_FAILURE);
}
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
// Record the start event
cudaEventRecord(start, NULL);
cudaMalloc(&d_A, mem_size_A);
cudaMalloc(&d_B, mem_size_B);
cudaMalloc(&d_C, mem_size_C);
GPU_fill_rand(d_A, dimsA.x, dimsA.y);
GPU_fill_rand(d_B, dimsB.x, dimsB.y);
// Only for tests purposes
cudaMemcpy(h_A,d_A, mem_size_A,cudaMemcpyDeviceToHost);
cudaMemcpy(h_B,d_B, mem_size_A,cudaMemcpyDeviceToHost);
// Setup execution parameters
dim3 threads(block_size, block_size);
dim3 grid(dimsB.x / threads.x, dimsA.y / threads.y);
// Create and start timer
printf("Computing result using CUDA Kernel...\n");
cudaDeviceSynchronize();
MatrixMulCUDA<32> <<< grid, threads >>>(d_C, d_A, d_B,
dimsA.x, dimsB.x);
// Record the stop event
cudaEventRecord(stop, NULL);
// Wait for the stop event to complete
cudaEventSynchronize(stop);
printf("done\n");
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal, start, stop);
// Compute and print the performance
float msecPerMatrixMul = msecTotal;
printf(
"Time spent executing by the GPU = %.3f msec," \
" WorkgroupSize= %u threads/block\n",
msecPerMatrixMul,
threads.x * threads.y);
// Copy result from device to host
cudaMemcpy(h_C, d_C, mem_size_C, cudaMemcpyDeviceToHost);
bool correct = true;
unsigned int cpu_start = clock();
for(int i = 0; i < dimsA.x; ++i)
for(int j = 0; j < dimsA.y; ++j)
for(int k = 0; k < dimsA.x; ++k)
{
h_C_test[j + i * dimsA.x] += h_A[i * dimsA.x + k] * h_B[k* dimsA.x +j];
}
unsigned int cpu_end = clock();
double cpuTime = (double)(cpu_end - cpu_start);
printf("Time spent executing by the CPU: %.3f msec\n", cpuTime);
printf("Checking computed result for correctness: ");
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6; // machine zero
const float valB = 0.01f;
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
double abs_err = fabs(h_C[i] - h_C_test[i]);
double dot_length = dimsA.x;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err / abs_val / dot_length;
if (rel_err > eps) {
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n",
i, h_C[i], dimsA.x * valB, eps);
correct = false;
break;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Clean up memory
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
if (correct) {
return EXIT_SUCCESS;
} else {
return EXIT_FAILURE;
}
}
int main(int argc, char **argv) {
printf("[Matrix Multiply Using CUDA] - Starting...\n");
int block_size = 32;
dim3 dimsA(10 * block_size, 10 * block_size, 1);
dim3 dimsB(10 * block_size, 10 * block_size, 1);
printf("MatrixA(%d,%d), MatrixB(%d,%d)\n", dimsA.x, dimsA.y,
dimsB.x, dimsB.y);
int matrix_result = MatrixMultiply(argc, argv, block_size, dimsA, dimsB);
exit(matrix_result);
} | code for sm_80
Function : _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0030*/ HFMA2.MMA R18, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff127435 */
/* 0x000fe200000001ff */
/*0040*/ MOV R16, c[0x0][0x17c] ; /* 0x00005f0000107a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ SHF.L.U32 R16, R16, 0x5, RZ ; /* 0x0000000510107819 */
/* 0x000fe200000006ff */
/*0080*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0090*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000ea40000002600 */
/*00a0*/ @!P0 MOV R23, RZ ; /* 0x000000ff00178202 */
/* 0x000fc40000000f00 */
/*00b0*/ LEA R2, R5, R0, 0x5 ; /* 0x0000000005027211 */
/* 0x001fca00078e28ff */
/*00c0*/ IMAD R3, R7, c[0x0][0x17c], R2 ; /* 0x00005f0007037a24 */
/* 0x002fc800078e0202 */
/*00d0*/ IMAD R3, R16, R6, R3 ; /* 0x0000000610037224 */
/* 0x004fc800078e0203 */
/*00e0*/ IMAD.WIDE R18, R3, R18, c[0x0][0x160] ; /* 0x0000580003127625 */
/* 0x000fe200078e0212 */
/*00f0*/ @!P0 BRA 0x740 ; /* 0x0000064000008947 */
/* 0x000fea0003800000 */
/*0100*/ LEA R3, R6.reuse, R7, 0x5 ; /* 0x0000000706037211 */
/* 0x040fe200078e28ff */
/*0110*/ IMAD R4, R7.reuse, c[0x0][0x17c], R0.reuse ; /* 0x00005f0007047a24 */
/* 0x140fe200078e0200 */
/*0120*/ MOV R21, 0x4 ; /* 0x0000000400157802 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD R6, R6, c[0x0][0x178], RZ ; /* 0x00005e0006067a24 */
/* 0x000fe200078e02ff */
/*0140*/ SHF.L.U32 R7, R7, 0x7, RZ ; /* 0x0000000707077819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fe200078e0200 */
/*0160*/ LEA R20, R5, R4, 0x5 ; /* 0x0000000405147211 */
/* 0x000fe400078e28ff */
/*0170*/ SHF.L.U32 R6, R6, 0x5, RZ ; /* 0x0000000506067819 */
/* 0x000fe200000006ff */
/*0180*/ IMAD.WIDE R2, R3, R21, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0215 */
/*0190*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fc40000000f00 */
/*01a0*/ LEA R4, R0, R7, 0x2 ; /* 0x0000000700047211 */
/* 0x000fe200078e10ff */
/*01b0*/ IMAD.WIDE R20, R20, R21, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x000fe200078e0215 */
/*01c0*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fe40000000f00 */
/*01d0*/ IADD3 R3, R6, c[0x0][0x178], RZ ; /* 0x00005e0006037a10 */
/* 0x000fe40007ffe0ff */
/*01e0*/ MOV R25, R5 ; /* 0x0000000500197202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E R29, [R20.64] ; /* 0x00000004141d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R24, R2 ; /* 0x0000000200187202 */
/* 0x000fca0000000f00 */
/*0210*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IADD3 R6, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R2, P1, R2, 0x80, RZ ; /* 0x0000008002027810 */
/* 0x000fe20007f3e0ff */
/*0240*/ IMAD.WIDE R20, R16, 0x4, R20 ; /* 0x0000000410147825 */
/* 0x001fe200078e0214 */
/*0250*/ ISETP.GE.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe40003f06270 */
/*0260*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0270*/ STS [R4+0x1000], R29 ; /* 0x0010001d04007388 */
/* 0x004fe80000000800 */
/*0280*/ STS [R4], R25 ; /* 0x0000001904007388 */
/* 0x008fe80000000800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ LDS R26, [R0.X4+0x1000] ; /* 0x00100000001a7984 */
/* 0x000fe80000004800 */
/*02b0*/ LDS.128 R12, [R7] ; /* 0x00000000070c7984 */
/* 0x000e280000000c00 */
/*02c0*/ LDS R28, [R0.X4+0x1080] ; /* 0x00108000001c7984 */
/* 0x000e680000004800 */
/*02d0*/ LDS R27, [R0.X4+0x1100] ; /* 0x00110000001b7984 */
/* 0x000ea80000004800 */
/*02e0*/ LDS R22, [R0.X4+0x1180] ; /* 0x0011800000167984 */
/* 0x000ee80000004800 */
/*02f0*/ LDS R17, [R0.X4+0x1200] ; /* 0x0012000000117984 */
/* 0x000fe80000004800 */
/*0300*/ LDS.128 R8, [R7+0x10] ; /* 0x0000100007087984 */
/* 0x000f280000000c00 */
/*0310*/ LDS R24, [R0.X4+0x1280] ; /* 0x0012800000187984 */
/* 0x000f680000004800 */
/*0320*/ LDS R25, [R0.X4+0x1300] ; /* 0x0013000000197984 */
/* 0x000f620000004800 */
/*0330*/ FFMA R12, R26, R12, R23 ; /* 0x0000000c1a0c7223 */
/* 0x001fc60000000017 */
/*0340*/ LDS R26, [R0.X4+0x1380] ; /* 0x00138000001a7984 */
/* 0x000e220000004800 */
/*0350*/ FFMA R12, R28, R13, R12 ; /* 0x0000000d1c0c7223 */
/* 0x002fc6000000000c */
/*0360*/ LDS R23, [R0.X4+0x1400] ; /* 0x0014000000177984 */
/* 0x000fe20000004800 */
/*0370*/ FFMA R12, R27, R14, R12 ; /* 0x0000000e1b0c7223 */
/* 0x004fc6000000000c */
/*0380*/ LDS R28, [R0.X4+0x1580] ; /* 0x00158000001c7984 */
/* 0x000fe20000004800 */
/*0390*/ FFMA R22, R22, R15, R12 ; /* 0x0000000f16167223 */
/* 0x008fc6000000000c */
/*03a0*/ LDS.128 R12, [R7+0x20] ; /* 0x00002000070c7984 */
/* 0x000e620000000c00 */
/*03b0*/ FFMA R8, R17, R8, R22 ; /* 0x0000000811087223 */
/* 0x010fc60000000016 */
/*03c0*/ LDS R22, [R0.X4+0x1480] ; /* 0x0014800000167984 */
/* 0x000ea20000004800 */
/*03d0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x020fc60000000008 */
/*03e0*/ LDS R17, [R0.X4+0x1500] ; /* 0x0015000000117984 */
/* 0x000ee20000004800 */
/*03f0*/ FFMA R8, R25, R10, R8 ; /* 0x0000000a19087223 */
/* 0x000fc60000000008 */
/*0400*/ LDS R25, [R0.X4+0x1600] ; /* 0x0016000000197984 */
/* 0x000fe80000004800 */
/*0410*/ LDS R24, [R0.X4+0x1780] ; /* 0x0017800000187984 */
/* 0x000fe20000004800 */
/*0420*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x001fc60000000008 */
/*0430*/ LDS.128 R8, [R7+0x30] ; /* 0x0000300007087984 */
/* 0x000e220000000c00 */
/*0440*/ FFMA R12, R23, R12, R26 ; /* 0x0000000c170c7223 */
/* 0x002fc6000000001a */
/*0450*/ LDS R26, [R0.X4+0x1680] ; /* 0x00168000001a7984 */
/* 0x000e680000004800 */
/*0460*/ LDS R23, [R0.X4+0x1700] ; /* 0x0017000000177984 */
/* 0x000f220000004800 */
/*0470*/ FFMA R12, R22, R13, R12 ; /* 0x0000000d160c7223 */
/* 0x004fc6000000000c */
/*0480*/ LDS R22, [R0.X4+0x1880] ; /* 0x0018800000167984 */
/* 0x000fe20000004800 */
/*0490*/ FFMA R12, R17, R14, R12 ; /* 0x0000000e110c7223 */
/* 0x008fc6000000000c */
/*04a0*/ LDS R17, [R0.X4+0x1800] ; /* 0x0018000000117984 */
/* 0x000fe20000004800 */
/*04b0*/ FFMA R28, R28, R15, R12 ; /* 0x0000000f1c1c7223 */
/* 0x000fc6000000000c */
/*04c0*/ LDS.128 R12, [R7+0x40] ; /* 0x00004000070c7984 */
/* 0x000ea20000000c00 */
/*04d0*/ FFMA R8, R25, R8, R28 ; /* 0x0000000819087223 */
/* 0x001fc6000000001c */
/*04e0*/ LDS R25, [R0.X4+0x1900] ; /* 0x0019000000197984 */
/* 0x000e280000004800 */
/*04f0*/ LDS R28, [R0.X4+0x1b80] ; /* 0x001b8000001c7984 */
/* 0x000fe20000004800 */
/*0500*/ FFMA R8, R26, R9, R8 ; /* 0x000000091a087223 */
/* 0x002fc60000000008 */
/*0510*/ LDS R26, [R0.X4+0x1980] ; /* 0x00198000001a7984 */
/* 0x000e620000004800 */
/*0520*/ FFMA R8, R23, R10, R8 ; /* 0x0000000a17087223 */
/* 0x010fc60000000008 */
/*0530*/ LDS R23, [R0.X4+0x1a00] ; /* 0x001a000000177984 */
/* 0x000fe20000004800 */
/*0540*/ FFMA R24, R24, R11, R8 ; /* 0x0000000b18187223 */
/* 0x000fc60000000008 */
/*0550*/ LDS.128 R8, [R7+0x50] ; /* 0x0000500007087984 */
/* 0x000ee20000000c00 */
/*0560*/ FFMA R12, R17, R12, R24 ; /* 0x0000000c110c7223 */
/* 0x004fc60000000018 */
/*0570*/ LDS R24, [R0.X4+0x1a80] ; /* 0x001a800000187984 */
/* 0x000ea20000004800 */
/*0580*/ FFMA R12, R22, R13, R12 ; /* 0x0000000d160c7223 */
/* 0x000fc6000000000c */
/*0590*/ LDS R17, [R0.X4+0x1b00] ; /* 0x001b000000117984 */
/* 0x000f280000004800 */
/*05a0*/ LDS R22, [R0.X4+0x1c80] ; /* 0x001c800000167984 */
/* 0x000fe20000004800 */
/*05b0*/ FFMA R12, R25, R14, R12 ; /* 0x0000000e190c7223 */
/* 0x001fc6000000000c */
/*05c0*/ LDS R25, [R0.X4+0x1c00] ; /* 0x001c000000197984 */
/* 0x000fe20000004800 */
/*05d0*/ FFMA R26, R26, R15, R12 ; /* 0x0000000f1a1a7223 */
/* 0x002fc6000000000c */
/*05e0*/ LDS.128 R12, [R7+0x60] ; /* 0x00006000070c7984 */
/* 0x000e220000000c00 */
/*05f0*/ FFMA R8, R23, R8, R26 ; /* 0x0000000817087223 */
/* 0x008fc6000000001a */
/*0600*/ LDS R23, [R0.X4+0x1d00] ; /* 0x001d000000177984 */
/* 0x000e620000004800 */
/*0610*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x004fc60000000008 */
/*0620*/ LDS R24, [R0.X4+0x1d80] ; /* 0x001d800000187984 */
/* 0x000ea20000004800 */
/*0630*/ FFMA R8, R17, R10, R8 ; /* 0x0000000a11087223 */
/* 0x010fc60000000008 */
/*0640*/ LDS R17, [R0.X4+0x1e00] ; /* 0x001e000000117984 */
/* 0x000fe20000004800 */
/*0650*/ FFMA R28, R28, R11, R8 ; /* 0x0000000b1c1c7223 */
/* 0x000fc60000000008 */
/*0660*/ LDS.128 R8, [R7+0x70] ; /* 0x0000700007087984 */
/* 0x000ee20000000c00 */
/*0670*/ FFMA R28, R25, R12, R28 ; /* 0x0000000c191c7223 */
/* 0x001fc6000000001c */
/*0680*/ LDS R12, [R0.X4+0x1e80] ; /* 0x001e8000000c7984 */
/* 0x000e220000004800 */
/*0690*/ FFMA R13, R22, R13, R28 ; /* 0x0000000d160d7223 */
/* 0x000fc6000000001c */
/*06a0*/ LDS R25, [R0.X4+0x1f00] ; /* 0x001f000000197984 */
/* 0x000f220000004800 */
/*06b0*/ FFMA R13, R23, R14, R13 ; /* 0x0000000e170d7223 */
/* 0x002fc6000000000d */
/*06c0*/ LDS R22, [R0.X4+0x1f80] ; /* 0x001f800000167984 */
/* 0x000e620000004800 */
/*06d0*/ FFMA R13, R24, R15, R13 ; /* 0x0000000f180d7223 */
/* 0x004fc8000000000d */
/*06e0*/ FFMA R8, R17, R8, R13 ; /* 0x0000000811087223 */
/* 0x008fc8000000000d */
/*06f0*/ FFMA R8, R12, R9, R8 ; /* 0x000000090c087223 */
/* 0x001fc80000000008 */
/*0700*/ FFMA R8, R25, R10, R8 ; /* 0x0000000a19087223 */
/* 0x010fc80000000008 */
/*0710*/ FFMA R23, R22, R11, R8 ; /* 0x0000000b16177223 */
/* 0x002fe20000000008 */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ @!P0 BRA 0x1e0 ; /* 0xfffffaa000008947 */
/* 0x000fea000383ffff */
/*0740*/ STG.E [R18.64], R23 ; /* 0x0000001712007986 */
/* 0x000fe2000c101904 */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <assert.h>
#include <iostream>
#include <chrono>
// CUDA runtime
#include <cuda_runtime.h>
#include <curand.h>
template <int BLOCK_SIZE> __global__ void MatrixMulCUDA(float *C, float *A, float *B, int wA, int wB) {
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = wA * BLOCK_SIZE * by;
int aEnd = aBegin + wA - 1;
int aStep = BLOCK_SIZE;
int bBegin = BLOCK_SIZE * bx;
int bStep = BLOCK_SIZE * wB;
float Csub = 0;
for (int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = A[a + wA * ty + tx];
Bs[ty][tx] = B[b + wB * ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
#pragma unroll
for (int k = 0; k < BLOCK_SIZE; ++k) {
Csub += As[ty][k] * Bs[k][tx];
}
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = wB * BLOCK_SIZE * by + BLOCK_SIZE * bx;
C[c + wB * ty + tx] = Csub;
}
void GPU_fill_rand(float *A, int nr_rows_A, int nr_cols_A) {
// Create a pseudo-random number generator
curandGenerator_t prng;
curandCreateGenerator(&prng, CURAND_RNG_PSEUDO_DEFAULT);
// Set the seed for the random number generator using the system clock
curandSetPseudoRandomGeneratorSeed(prng, (unsigned long long) clock());
// Fill the array with random numbers on the device
curandGenerateUniform(prng, A, nr_rows_A * nr_cols_A);
}
int MatrixMultiply(int argc, char **argv,
int block_size, const dim3 &dimsA,
const dim3 &dimsB) {
// Allocate host memory for matrices A and B
unsigned int size_A = dimsA.x * dimsA.y;
unsigned int mem_size_A = sizeof(float) * size_A;
float *h_A = reinterpret_cast<float *>(malloc(mem_size_A));
unsigned int size_B = dimsB.x * dimsB.y;
unsigned int mem_size_B = sizeof(float) * size_B;
float *h_B = reinterpret_cast<float *>(malloc(mem_size_B));
// Allocate device memory
float *d_A, *d_B, *d_C;
// Allocate host matrix C
dim3 dimsC(dimsB.x, dimsA.y, 1);
unsigned int mem_size_C = dimsC.x * dimsC.y * sizeof(float);
float *h_C = reinterpret_cast<float *>(malloc(mem_size_C));
float *h_C_test = reinterpret_cast<float *>(malloc(mem_size_C));
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
h_C_test[i]=0;
}
if (h_C == NULL) {
fprintf(stderr, "Failed to allocate host matrix C!\n");
exit(EXIT_FAILURE);
}
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
// Record the start event
cudaEventRecord(start, NULL);
cudaMalloc(&d_A, mem_size_A);
cudaMalloc(&d_B, mem_size_B);
cudaMalloc(&d_C, mem_size_C);
GPU_fill_rand(d_A, dimsA.x, dimsA.y);
GPU_fill_rand(d_B, dimsB.x, dimsB.y);
// Only for tests purposes
cudaMemcpy(h_A,d_A, mem_size_A,cudaMemcpyDeviceToHost);
cudaMemcpy(h_B,d_B, mem_size_A,cudaMemcpyDeviceToHost);
// Setup execution parameters
dim3 threads(block_size, block_size);
dim3 grid(dimsB.x / threads.x, dimsA.y / threads.y);
// Create and start timer
printf("Computing result using CUDA Kernel...\n");
cudaDeviceSynchronize();
MatrixMulCUDA<32> <<< grid, threads >>>(d_C, d_A, d_B,
dimsA.x, dimsB.x);
// Record the stop event
cudaEventRecord(stop, NULL);
// Wait for the stop event to complete
cudaEventSynchronize(stop);
printf("done\n");
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal, start, stop);
// Compute and print the performance
float msecPerMatrixMul = msecTotal;
printf(
"Time spent executing by the GPU = %.3f msec," \
" WorkgroupSize= %u threads/block\n",
msecPerMatrixMul,
threads.x * threads.y);
// Copy result from device to host
cudaMemcpy(h_C, d_C, mem_size_C, cudaMemcpyDeviceToHost);
bool correct = true;
unsigned int cpu_start = clock();
for(int i = 0; i < dimsA.x; ++i)
for(int j = 0; j < dimsA.y; ++j)
for(int k = 0; k < dimsA.x; ++k)
{
h_C_test[j + i * dimsA.x] += h_A[i * dimsA.x + k] * h_B[k* dimsA.x +j];
}
unsigned int cpu_end = clock();
double cpuTime = (double)(cpu_end - cpu_start);
printf("Time spent executing by the CPU: %.3f msec\n", cpuTime);
printf("Checking computed result for correctness: ");
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6; // machine zero
const float valB = 0.01f;
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
double abs_err = fabs(h_C[i] - h_C_test[i]);
double dot_length = dimsA.x;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err / abs_val / dot_length;
if (rel_err > eps) {
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n",
i, h_C[i], dimsA.x * valB, eps);
correct = false;
break;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Clean up memory
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
if (correct) {
return EXIT_SUCCESS;
} else {
return EXIT_FAILURE;
}
}
int main(int argc, char **argv) {
printf("[Matrix Multiply Using CUDA] - Starting...\n");
int block_size = 32;
dim3 dimsA(10 * block_size, 10 * block_size, 1);
dim3 dimsB(10 * block_size, 10 * block_size, 1);
printf("MatrixA(%d,%d), MatrixB(%d,%d)\n", dimsA.x, dimsA.y,
dimsB.x, dimsB.y);
int matrix_result = MatrixMultiply(argc, argv, block_size, dimsA, dimsB);
exit(matrix_result);
} | .file "tmpxft_000ab6c2_00000000-6_matrixMul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii, @function
_ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii:
.LFB3797:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii, .-_ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii
.section .text._Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,"axG",@progbits,_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,comdat
.weak _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.type _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, @function
_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii:
.LFB4129:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4129:
.size _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, .-_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13GPU_fill_randPfii
.type _Z13GPU_fill_randPfii, @function
_Z13GPU_fill_randPfii:
.LFB3770:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %ebx
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $100, %esi
call curandCreateGenerator@PLT
call clock@PLT
movq %rax, %rsi
movq (%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
imull %r12d, %ebx
movslq %ebx, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call curandGenerateUniform@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.size _Z13GPU_fill_randPfii, .-_Z13GPU_fill_randPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result = PASS"
.LC1:
.string "Result = FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Failed to allocate host matrix C!\n"
.align 8
.LC4:
.string "Computing result using CUDA Kernel...\n"
.section .rodata.str1.1
.LC5:
.string "done\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Time spent executing by the GPU = %.3f msec, WorkgroupSize= %u threads/block\n"
.align 8
.LC7:
.string "Time spent executing by the CPU: %.3f msec\n"
.align 8
.LC8:
.string "Checking computed result for correctness: "
.align 8
.LC12:
.string "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n"
.section .rodata.str1.1
.LC13:
.string "%s\n"
.text
.globl _Z14MatrixMultiplyiPPciRK4dim3S3_
.type _Z14MatrixMultiplyiPPciRK4dim3S3_, @function
_Z14MatrixMultiplyiPPciRK4dim3S3_:
.LFB3771:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edx, 16(%rsp)
movq %rcx, %r13
movq %r8, %r14
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl 4(%rcx), %r12d
movl %r12d, %eax
imull (%rcx), %eax
leal 0(,%rax,4), %eax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbp
movl (%r14), %r15d
movl %r15d, %eax
imull 4(%r14), %eax
leal 0(,%rax,4), %eax
movq %rax, 40(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r12d, %edi
imull %r15d, %edi
movl %edi, 28(%rsp)
leal 0(,%rdi,4), %r12d
movq %r12, 32(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
movq %r12, %rdi
call malloc@PLT
movq %rax, %r12
movl 28(%rsp), %edi
testl %edi, %edi
jle .L16
movl %edi, %edx
leaq (%rax,%rdx,4), %rdx
.L17:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L17
.L16:
testq %r15, %r15
je .L45
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
leaq 56(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq 40(%rsp), %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq 32(%rsp), %rsi
call cudaMalloc@PLT
movl 4(%r13), %edx
movl 0(%r13), %esi
movq 56(%rsp), %rdi
call _Z13GPU_fill_randPfii
movl 4(%r14), %edx
movl (%r14), %esi
movq 64(%rsp), %rdi
call _Z13GPU_fill_randPfii
movl $2, %ecx
movq 8(%rsp), %rdx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 64(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %ecx
movl $1, 104(%rsp)
movl 4(%r13), %eax
movl $0, %edx
divl %ecx
movl %eax, %esi
movl (%r14), %eax
movl $0, %edx
divl %ecx
movl %eax, 108(%rsp)
movl %esi, 112(%rsp)
movl $1, 116(%rsp)
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl 16(%rsp), %eax
movl %eax, 96(%rsp)
movl %eax, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L19:
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0x00000000, 52(%rsp)
leaq 52(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 16(%rsp), %edx
imull %edx, %edx
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq 32(%rsp), %rdx
movq 72(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r14
movl 0(%r13), %edi
testl %edi, %edi
je .L20
movl 4(%r13), %r11d
movl %edi, %r8d
movl $0, %r10d
movl $0, %edx
movq %rax, 16(%rsp)
jmp .L21
.L45:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movl 0(%r13), %ecx
movl (%r14), %r8d
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 72(%rsp), %rdi
call _ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii
jmp .L19
.L24:
movl %r9d, %ecx
leal (%r10,%r9), %eax
leaq (%r12,%rax,4), %r14
movss (%r14), %xmm1
movl %r10d, %eax
.L22:
movl %eax, %esi
movl %ecx, %edx
movss 0(%rbp,%rsi,4), %xmm0
mulss (%rbx,%rdx,4), %xmm0
addss %xmm0, %xmm1
addl $1, %eax
addl %edi, %ecx
cmpl %r8d, %eax
jne .L22
movss %xmm1, (%r14)
addl $1, %r9d
cmpl %r9d, %r11d
jne .L24
movl 8(%rsp), %edx
.L23:
addl $1, %edx
addl %edi, %r10d
addl %edi, %r8d
cmpl %edi, %edx
je .L43
.L21:
testl %r11d, %r11d
je .L23
movl $0, %r9d
movl %edx, 8(%rsp)
jmp .L24
.L43:
movq 16(%rsp), %r14
.L20:
call clock@PLT
subl %r14d, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %edi
testl %edi, %edi
jle .L36
movl 0(%r13), %ecx
movl %ecx, %eax
pxor %xmm5, %xmm5
cvtsi2sdq %rax, %xmm5
movl %edi, %edx
movl $0, %eax
movss .LC9(%rip), %xmm3
movsd .LC10(%rip), %xmm4
.L34:
movss (%r15,%rax,4), %xmm0
movaps %xmm0, %xmm1
subss (%r12,%rax,4), %xmm1
andps %xmm3, %xmm1
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
cvtss2sd %xmm2, %xmm2
divsd %xmm2, %xmm1
divsd %xmm5, %xmm1
comisd %xmm4, %xmm1
ja .L47
addq $1, %rax
cmpq %rax, %rdx
jne .L34
movl $1, %r12d
leaq .LC0(%rip), %rdx
jmp .L27
.L47:
movl %ecx, %ecx
pxor %xmm1, %xmm1
cvtsi2ssq %rcx, %xmm1
mulss .LC11(%rip), %xmm1
cvtss2sd %xmm0, %xmm0
movsd .LC10(%rip), %xmm2
cvtss2sd %xmm1, %xmm1
movl %eax, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC1(%rip), %rdx
.L27:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %r12d, %eax
xorl $1, %eax
movzbl %al, %eax
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L48
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $1, %r12d
leaq .LC0(%rip), %rdx
jmp .L27
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3771:
.size _Z14MatrixMultiplyiPPciRK4dim3S3_, .-_Z14MatrixMultiplyiPPciRK4dim3S3_
.section .rodata.str1.8
.align 8
.LC14:
.string "[Matrix Multiply Using CUDA] - Starting...\n"
.align 8
.LC15:
.string "MatrixA(%d,%d), MatrixB(%d,%d)\n"
.text
.globl main
.type main, @function
main:
.LFB3772:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC14(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $320, (%rsp)
movl $320, 4(%rsp)
movl $1, 8(%rsp)
movl $320, 12(%rsp)
movl $320, 16(%rsp)
movl $1, 20(%rsp)
movl $320, %r9d
movl $320, %r8d
movl $320, %ecx
movl $320, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rcx
leaq 12(%rsp), %r8
movl $32, %edx
movq %rbp, %rsi
movl %ebx, %edi
call _Z14MatrixMultiplyiPPciRK4dim3S3_
movl %eax, %edi
call exit@PLT
.cfi_endproc
.LFE3772:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC16:
.string "_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1008981770
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <assert.h>
#include <iostream>
#include <chrono>
// CUDA runtime
#include <cuda_runtime.h>
#include <curand.h>
template <int BLOCK_SIZE> __global__ void MatrixMulCUDA(float *C, float *A, float *B, int wA, int wB) {
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = wA * BLOCK_SIZE * by;
int aEnd = aBegin + wA - 1;
int aStep = BLOCK_SIZE;
int bBegin = BLOCK_SIZE * bx;
int bStep = BLOCK_SIZE * wB;
float Csub = 0;
for (int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = A[a + wA * ty + tx];
Bs[ty][tx] = B[b + wB * ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
#pragma unroll
for (int k = 0; k < BLOCK_SIZE; ++k) {
Csub += As[ty][k] * Bs[k][tx];
}
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = wB * BLOCK_SIZE * by + BLOCK_SIZE * bx;
C[c + wB * ty + tx] = Csub;
}
void GPU_fill_rand(float *A, int nr_rows_A, int nr_cols_A) {
// Create a pseudo-random number generator
curandGenerator_t prng;
curandCreateGenerator(&prng, CURAND_RNG_PSEUDO_DEFAULT);
// Set the seed for the random number generator using the system clock
curandSetPseudoRandomGeneratorSeed(prng, (unsigned long long) clock());
// Fill the array with random numbers on the device
curandGenerateUniform(prng, A, nr_rows_A * nr_cols_A);
}
int MatrixMultiply(int argc, char **argv,
int block_size, const dim3 &dimsA,
const dim3 &dimsB) {
// Allocate host memory for matrices A and B
unsigned int size_A = dimsA.x * dimsA.y;
unsigned int mem_size_A = sizeof(float) * size_A;
float *h_A = reinterpret_cast<float *>(malloc(mem_size_A));
unsigned int size_B = dimsB.x * dimsB.y;
unsigned int mem_size_B = sizeof(float) * size_B;
float *h_B = reinterpret_cast<float *>(malloc(mem_size_B));
// Allocate device memory
float *d_A, *d_B, *d_C;
// Allocate host matrix C
dim3 dimsC(dimsB.x, dimsA.y, 1);
unsigned int mem_size_C = dimsC.x * dimsC.y * sizeof(float);
float *h_C = reinterpret_cast<float *>(malloc(mem_size_C));
float *h_C_test = reinterpret_cast<float *>(malloc(mem_size_C));
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
h_C_test[i]=0;
}
if (h_C == NULL) {
fprintf(stderr, "Failed to allocate host matrix C!\n");
exit(EXIT_FAILURE);
}
cudaEvent_t start;
cudaEventCreate(&start);
cudaEvent_t stop;
cudaEventCreate(&stop);
// Record the start event
cudaEventRecord(start, NULL);
cudaMalloc(&d_A, mem_size_A);
cudaMalloc(&d_B, mem_size_B);
cudaMalloc(&d_C, mem_size_C);
GPU_fill_rand(d_A, dimsA.x, dimsA.y);
GPU_fill_rand(d_B, dimsB.x, dimsB.y);
// Only for tests purposes
cudaMemcpy(h_A,d_A, mem_size_A,cudaMemcpyDeviceToHost);
cudaMemcpy(h_B,d_B, mem_size_A,cudaMemcpyDeviceToHost);
// Setup execution parameters
dim3 threads(block_size, block_size);
dim3 grid(dimsB.x / threads.x, dimsA.y / threads.y);
// Create and start timer
printf("Computing result using CUDA Kernel...\n");
cudaDeviceSynchronize();
MatrixMulCUDA<32> <<< grid, threads >>>(d_C, d_A, d_B,
dimsA.x, dimsB.x);
// Record the stop event
cudaEventRecord(stop, NULL);
// Wait for the stop event to complete
cudaEventSynchronize(stop);
printf("done\n");
float msecTotal = 0.0f;
cudaEventElapsedTime(&msecTotal, start, stop);
// Compute and print the performance
float msecPerMatrixMul = msecTotal;
printf(
"Time spent executing by the GPU = %.3f msec," \
" WorkgroupSize= %u threads/block\n",
msecPerMatrixMul,
threads.x * threads.y);
// Copy result from device to host
cudaMemcpy(h_C, d_C, mem_size_C, cudaMemcpyDeviceToHost);
bool correct = true;
unsigned int cpu_start = clock();
for(int i = 0; i < dimsA.x; ++i)
for(int j = 0; j < dimsA.y; ++j)
for(int k = 0; k < dimsA.x; ++k)
{
h_C_test[j + i * dimsA.x] += h_A[i * dimsA.x + k] * h_B[k* dimsA.x +j];
}
unsigned int cpu_end = clock();
double cpuTime = (double)(cpu_end - cpu_start);
printf("Time spent executing by the CPU: %.3f msec\n", cpuTime);
printf("Checking computed result for correctness: ");
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6; // machine zero
const float valB = 0.01f;
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
double abs_err = fabs(h_C[i] - h_C_test[i]);
double dot_length = dimsA.x;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err / abs_val / dot_length;
if (rel_err > eps) {
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n",
i, h_C[i], dimsA.x * valB, eps);
correct = false;
break;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Clean up memory
free(h_A);
free(h_B);
free(h_C);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
if (correct) {
return EXIT_SUCCESS;
} else {
return EXIT_FAILURE;
}
}
int main(int argc, char **argv) {
printf("[Matrix Multiply Using CUDA] - Starting...\n");
int block_size = 32;
dim3 dimsA(10 * block_size, 10 * block_size, 1);
dim3 dimsB(10 * block_size, 10 * block_size, 1);
printf("MatrixA(%d,%d), MatrixB(%d,%d)\n", dimsA.x, dimsA.y,
dimsB.x, dimsB.y);
int matrix_result = MatrixMultiply(argc, argv, block_size, dimsA, dimsB);
exit(matrix_result);
} | #include <stdio.h>
#include <assert.h>
#include <iostream>
#include <chrono>
// CUDA runtime
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
template <int BLOCK_SIZE> __global__ void MatrixMulCUDA(float *C, float *A, float *B, int wA, int wB) {
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = wA * BLOCK_SIZE * by;
int aEnd = aBegin + wA - 1;
int aStep = BLOCK_SIZE;
int bBegin = BLOCK_SIZE * bx;
int bStep = BLOCK_SIZE * wB;
float Csub = 0;
for (int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = A[a + wA * ty + tx];
Bs[ty][tx] = B[b + wB * ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
#pragma unroll
for (int k = 0; k < BLOCK_SIZE; ++k) {
Csub += As[ty][k] * Bs[k][tx];
}
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = wB * BLOCK_SIZE * by + BLOCK_SIZE * bx;
C[c + wB * ty + tx] = Csub;
}
void GPU_fill_rand(float *A, int nr_rows_A, int nr_cols_A) {
// Create a pseudo-random number generator
hiprandGenerator_t prng;
hiprandCreateGenerator(&prng, HIPRAND_RNG_PSEUDO_DEFAULT);
// Set the seed for the random number generator using the system clock
hiprandSetPseudoRandomGeneratorSeed(prng, (unsigned long long) clock());
// Fill the array with random numbers on the device
hiprandGenerateUniform(prng, A, nr_rows_A * nr_cols_A);
}
int MatrixMultiply(int argc, char **argv,
int block_size, const dim3 &dimsA,
const dim3 &dimsB) {
// Allocate host memory for matrices A and B
unsigned int size_A = dimsA.x * dimsA.y;
unsigned int mem_size_A = sizeof(float) * size_A;
float *h_A = reinterpret_cast<float *>(malloc(mem_size_A));
unsigned int size_B = dimsB.x * dimsB.y;
unsigned int mem_size_B = sizeof(float) * size_B;
float *h_B = reinterpret_cast<float *>(malloc(mem_size_B));
// Allocate device memory
float *d_A, *d_B, *d_C;
// Allocate host matrix C
dim3 dimsC(dimsB.x, dimsA.y, 1);
unsigned int mem_size_C = dimsC.x * dimsC.y * sizeof(float);
float *h_C = reinterpret_cast<float *>(malloc(mem_size_C));
float *h_C_test = reinterpret_cast<float *>(malloc(mem_size_C));
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
h_C_test[i]=0;
}
if (h_C == NULL) {
fprintf(stderr, "Failed to allocate host matrix C!\n");
exit(EXIT_FAILURE);
}
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
// Record the start event
hipEventRecord(start, NULL);
hipMalloc(&d_A, mem_size_A);
hipMalloc(&d_B, mem_size_B);
hipMalloc(&d_C, mem_size_C);
GPU_fill_rand(d_A, dimsA.x, dimsA.y);
GPU_fill_rand(d_B, dimsB.x, dimsB.y);
// Only for tests purposes
hipMemcpy(h_A,d_A, mem_size_A,hipMemcpyDeviceToHost);
hipMemcpy(h_B,d_B, mem_size_A,hipMemcpyDeviceToHost);
// Setup execution parameters
dim3 threads(block_size, block_size);
dim3 grid(dimsB.x / threads.x, dimsA.y / threads.y);
// Create and start timer
printf("Computing result using CUDA Kernel...\n");
hipDeviceSynchronize();
MatrixMulCUDA<32> <<< grid, threads >>>(d_C, d_A, d_B,
dimsA.x, dimsB.x);
// Record the stop event
hipEventRecord(stop, NULL);
// Wait for the stop event to complete
hipEventSynchronize(stop);
printf("done\n");
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal, start, stop);
// Compute and print the performance
float msecPerMatrixMul = msecTotal;
printf(
"Time spent executing by the GPU = %.3f msec," \
" WorkgroupSize= %u threads/block\n",
msecPerMatrixMul,
threads.x * threads.y);
// Copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C, hipMemcpyDeviceToHost);
bool correct = true;
unsigned int cpu_start = clock();
for(int i = 0; i < dimsA.x; ++i)
for(int j = 0; j < dimsA.y; ++j)
for(int k = 0; k < dimsA.x; ++k)
{
h_C_test[j + i * dimsA.x] += h_A[i * dimsA.x + k] * h_B[k* dimsA.x +j];
}
unsigned int cpu_end = clock();
double cpuTime = (double)(cpu_end - cpu_start);
printf("Time spent executing by the CPU: %.3f msec\n", cpuTime);
printf("Checking computed result for correctness: ");
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6; // machine zero
const float valB = 0.01f;
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
double abs_err = fabs(h_C[i] - h_C_test[i]);
double dot_length = dimsA.x;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err / abs_val / dot_length;
if (rel_err > eps) {
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n",
i, h_C[i], dimsA.x * valB, eps);
correct = false;
break;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Clean up memory
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
if (correct) {
return EXIT_SUCCESS;
} else {
return EXIT_FAILURE;
}
}
int main(int argc, char **argv) {
printf("[Matrix Multiply Using CUDA] - Starting...\n");
int block_size = 32;
dim3 dimsA(10 * block_size, 10 * block_size, 1);
dim3 dimsB(10 * block_size, 10 * block_size, 1);
printf("MatrixA(%d,%d), MatrixB(%d,%d)\n", dimsA.x, dimsA.y,
dimsB.x, dimsB.y);
int matrix_result = MatrixMultiply(argc, argv, block_size, dimsA, dimsB);
exit(matrix_result);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <assert.h>
#include <iostream>
#include <chrono>
// CUDA runtime
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
template <int BLOCK_SIZE> __global__ void MatrixMulCUDA(float *C, float *A, float *B, int wA, int wB) {
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = wA * BLOCK_SIZE * by;
int aEnd = aBegin + wA - 1;
int aStep = BLOCK_SIZE;
int bBegin = BLOCK_SIZE * bx;
int bStep = BLOCK_SIZE * wB;
float Csub = 0;
for (int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = A[a + wA * ty + tx];
Bs[ty][tx] = B[b + wB * ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
#pragma unroll
for (int k = 0; k < BLOCK_SIZE; ++k) {
Csub += As[ty][k] * Bs[k][tx];
}
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = wB * BLOCK_SIZE * by + BLOCK_SIZE * bx;
C[c + wB * ty + tx] = Csub;
}
void GPU_fill_rand(float *A, int nr_rows_A, int nr_cols_A) {
// Create a pseudo-random number generator
hiprandGenerator_t prng;
hiprandCreateGenerator(&prng, HIPRAND_RNG_PSEUDO_DEFAULT);
// Set the seed for the random number generator using the system clock
hiprandSetPseudoRandomGeneratorSeed(prng, (unsigned long long) clock());
// Fill the array with random numbers on the device
hiprandGenerateUniform(prng, A, nr_rows_A * nr_cols_A);
}
int MatrixMultiply(int argc, char **argv,
int block_size, const dim3 &dimsA,
const dim3 &dimsB) {
// Allocate host memory for matrices A and B
unsigned int size_A = dimsA.x * dimsA.y;
unsigned int mem_size_A = sizeof(float) * size_A;
float *h_A = reinterpret_cast<float *>(malloc(mem_size_A));
unsigned int size_B = dimsB.x * dimsB.y;
unsigned int mem_size_B = sizeof(float) * size_B;
float *h_B = reinterpret_cast<float *>(malloc(mem_size_B));
// Allocate device memory
float *d_A, *d_B, *d_C;
// Allocate host matrix C
dim3 dimsC(dimsB.x, dimsA.y, 1);
unsigned int mem_size_C = dimsC.x * dimsC.y * sizeof(float);
float *h_C = reinterpret_cast<float *>(malloc(mem_size_C));
float *h_C_test = reinterpret_cast<float *>(malloc(mem_size_C));
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
h_C_test[i]=0;
}
if (h_C == NULL) {
fprintf(stderr, "Failed to allocate host matrix C!\n");
exit(EXIT_FAILURE);
}
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
// Record the start event
hipEventRecord(start, NULL);
hipMalloc(&d_A, mem_size_A);
hipMalloc(&d_B, mem_size_B);
hipMalloc(&d_C, mem_size_C);
GPU_fill_rand(d_A, dimsA.x, dimsA.y);
GPU_fill_rand(d_B, dimsB.x, dimsB.y);
// Only for tests purposes
hipMemcpy(h_A,d_A, mem_size_A,hipMemcpyDeviceToHost);
hipMemcpy(h_B,d_B, mem_size_A,hipMemcpyDeviceToHost);
// Setup execution parameters
dim3 threads(block_size, block_size);
dim3 grid(dimsB.x / threads.x, dimsA.y / threads.y);
// Create and start timer
printf("Computing result using CUDA Kernel...\n");
hipDeviceSynchronize();
MatrixMulCUDA<32> <<< grid, threads >>>(d_C, d_A, d_B,
dimsA.x, dimsB.x);
// Record the stop event
hipEventRecord(stop, NULL);
// Wait for the stop event to complete
hipEventSynchronize(stop);
printf("done\n");
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal, start, stop);
// Compute and print the performance
float msecPerMatrixMul = msecTotal;
printf(
"Time spent executing by the GPU = %.3f msec," \
" WorkgroupSize= %u threads/block\n",
msecPerMatrixMul,
threads.x * threads.y);
// Copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C, hipMemcpyDeviceToHost);
bool correct = true;
unsigned int cpu_start = clock();
for(int i = 0; i < dimsA.x; ++i)
for(int j = 0; j < dimsA.y; ++j)
for(int k = 0; k < dimsA.x; ++k)
{
h_C_test[j + i * dimsA.x] += h_A[i * dimsA.x + k] * h_B[k* dimsA.x +j];
}
unsigned int cpu_end = clock();
double cpuTime = (double)(cpu_end - cpu_start);
printf("Time spent executing by the CPU: %.3f msec\n", cpuTime);
printf("Checking computed result for correctness: ");
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6; // machine zero
const float valB = 0.01f;
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
double abs_err = fabs(h_C[i] - h_C_test[i]);
double dot_length = dimsA.x;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err / abs_val / dot_length;
if (rel_err > eps) {
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n",
i, h_C[i], dimsA.x * valB, eps);
correct = false;
break;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Clean up memory
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
if (correct) {
return EXIT_SUCCESS;
} else {
return EXIT_FAILURE;
}
}
int main(int argc, char **argv) {
printf("[Matrix Multiply Using CUDA] - Starting...\n");
int block_size = 32;
dim3 dimsA(10 * block_size, 10 * block_size, 1);
dim3 dimsB(10 * block_size, 10 * block_size, 1);
printf("MatrixA(%d,%d), MatrixB(%d,%d)\n", dimsA.x, dimsA.y,
dimsB.x, dimsB.y);
int matrix_result = MatrixMultiply(argc, argv, block_size, dimsA, dimsB);
exit(matrix_result);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,"axG",@progbits,_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,comdat
.protected _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.globl _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.p2align 8
.type _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,@function
_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii:
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s8, s14, 5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v5, v1, s3
s_lshl_b32 s3, s3, 5
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b32_e32 v3, 2, v0
v_lshl_add_u32 v4, s15, 5, v1
v_dual_mov_b32 v59, 0 :: v_dual_lshlrev_b32 v6, 7, v1
s_mul_i32 s9, s2, s15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_or_b32_e32 v8, 0x1000, v3
v_mad_u64_u32 v[1:2], null, s2, v4, v[0:1]
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v7, v6, v3
v_or_b32_e32 v9, 4, v6
v_add_nc_u32_e32 v10, 0x1080, v3
v_or_b32_e32 v11, 8, v6
v_add_nc_u32_e32 v12, 0x1100, v3
v_add_nc_u32_e32 v13, v8, v6
v_or_b32_e32 v14, 12, v6
v_add_nc_u32_e32 v15, 0x1180, v3
v_or_b32_e32 v16, 16, v6
v_add_nc_u32_e32 v17, 0x1200, v3
v_or_b32_e32 v18, 20, v6
v_add_nc_u32_e32 v19, 0x1280, v3
v_or_b32_e32 v20, 24, v6
v_add_nc_u32_e32 v21, 0x1300, v3
v_or_b32_e32 v22, 28, v6
v_add_nc_u32_e32 v23, 0x1380, v3
v_or_b32_e32 v24, 32, v6
v_add_nc_u32_e32 v25, 0x1400, v3
v_or_b32_e32 v26, 36, v6
v_add_nc_u32_e32 v27, 0x1480, v3
v_or_b32_e32 v28, 40, v6
v_add_nc_u32_e32 v29, 0x1500, v3
v_or_b32_e32 v30, 44, v6
v_add_nc_u32_e32 v31, 0x1580, v3
v_or_b32_e32 v32, 48, v6
v_add_nc_u32_e32 v33, 0x1600, v3
v_or_b32_e32 v34, 52, v6
v_add_nc_u32_e32 v35, 0x1680, v3
v_or_b32_e32 v36, 56, v6
v_add_nc_u32_e32 v37, 0x1700, v3
v_or_b32_e32 v38, 60, v6
v_add_nc_u32_e32 v39, 0x1780, v3
v_or_b32_e32 v40, 64, v6
v_add_nc_u32_e32 v41, 0x1800, v3
v_or_b32_e32 v42, 0x44, v6
v_add_nc_u32_e32 v43, 0x1880, v3
v_or_b32_e32 v44, 0x48, v6
v_add_nc_u32_e32 v45, 0x1900, v3
v_or_b32_e32 v46, 0x4c, v6
v_add_nc_u32_e32 v47, 0x1980, v3
v_or_b32_e32 v48, 0x50, v6
v_add_nc_u32_e32 v49, 0x1a00, v3
v_or_b32_e32 v50, 0x54, v6
v_add_nc_u32_e32 v51, 0x1a80, v3
v_or_b32_e32 v52, 0x58, v6
v_add_nc_u32_e32 v53, 0x1b00, v3
v_or_b32_e32 v54, 0x5c, v6
v_add_nc_u32_e32 v55, 0x1b80, v3
v_or_b32_e32 v56, 0x60, v6
v_add_nc_u32_e32 v57, 0x1c00, v3
v_or_b32_e32 v58, 0x64, v6
v_add_nc_u32_e32 v60, 0x1c80, v3
v_or_b32_e32 v61, 0x68, v6
v_add_nc_u32_e32 v62, 0x1d00, v3
v_or_b32_e32 v63, 0x6c, v6
v_add_nc_u32_e32 v64, 0x1d80, v3
v_or_b32_e32 v65, 0x70, v6
v_add_nc_u32_e32 v66, 0x1e00, v3
v_or_b32_e32 v67, 0x74, v6
v_add_nc_u32_e32 v68, 0x1e80, v3
v_or_b32_e32 v69, 0x78, v6
v_add_nc_u32_e32 v70, 0x1f00, v3
v_or_b32_e32 v71, 0x7c, v6
v_add_nc_u32_e32 v72, 0x1f80, v3
v_add3_u32 v3, v0, v5, s8
s_lshl_b32 s9, s9, 5
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s9, s2
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s9, s9, 32
s_cmp_ge_i32 s9, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[73:74], 2, v[1:2]
v_lshlrev_b64 v[75:76], 2, v[3:4]
v_add_nc_u32_e32 v3, s3, v3
v_add_nc_u32_e32 v1, 32, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v73, vcc_lo, s4, v73
v_add_co_ci_u32_e32 v74, vcc_lo, s5, v74, vcc_lo
v_add_co_u32 v75, vcc_lo, s6, v75
v_add_co_ci_u32_e32 v76, vcc_lo, s7, v76, vcc_lo
global_load_b32 v2, v[73:74], off
global_load_b32 v4, v[75:76], off
s_waitcnt vmcnt(1)
ds_store_b32 v7, v2
s_waitcnt vmcnt(0)
ds_store_b32 v13, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v6
ds_load_b32 v4, v8
ds_load_b32 v73, v9
ds_load_b32 v74, v10
ds_load_b32 v75, v11
ds_load_b32 v76, v12
ds_load_b32 v77, v14
ds_load_b32 v78, v15
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v16
ds_load_b32 v4, v17
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v18
ds_load_b32 v74, v19
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v20
ds_load_b32 v76, v21
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v22
ds_load_b32 v78, v23
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v24
ds_load_b32 v4, v25
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v26
ds_load_b32 v74, v27
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v28
ds_load_b32 v76, v29
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v30
ds_load_b32 v78, v31
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v32
ds_load_b32 v4, v33
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v34
ds_load_b32 v74, v35
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v36
ds_load_b32 v76, v37
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v38
ds_load_b32 v78, v39
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v40
ds_load_b32 v4, v41
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v42
ds_load_b32 v74, v43
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v44
ds_load_b32 v76, v45
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v46
ds_load_b32 v78, v47
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v48
ds_load_b32 v4, v49
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v50
ds_load_b32 v74, v51
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v52
ds_load_b32 v76, v53
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v54
ds_load_b32 v78, v55
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v56
ds_load_b32 v4, v57
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v58
ds_load_b32 v74, v60
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v61
ds_load_b32 v76, v62
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v63
ds_load_b32 v78, v64
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v65
ds_load_b32 v4, v66
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v67
ds_load_b32 v74, v68
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v69
ds_load_b32 v76, v70
ds_load_b32 v79, v71
ds_load_b32 v80, v72
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v59, v77, v78
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v59, v2, v4
v_fmac_f32_e32 v59, v73, v74
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v59, v75, v76
v_fmac_f32_e32 v59, v79, v80
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v59, 0
.LBB0_4:
v_add_nc_u32_e32 v0, s8, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s3, s3, s15
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, v0, v5, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v59, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 81
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,"axG",@progbits,_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,comdat
.Lfunc_end0:
.size _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, .Lfunc_end0-_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 81
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <assert.h>
#include <iostream>
#include <chrono>
// CUDA runtime
#include <hip/hip_runtime.h>
#include <hiprand/hiprand.h>
template <int BLOCK_SIZE> __global__ void MatrixMulCUDA(float *C, float *A, float *B, int wA, int wB) {
// Block index
int bx = blockIdx.x;
int by = blockIdx.y;
// Thread index
int tx = threadIdx.x;
int ty = threadIdx.y;
int aBegin = wA * BLOCK_SIZE * by;
int aEnd = aBegin + wA - 1;
int aStep = BLOCK_SIZE;
int bBegin = BLOCK_SIZE * bx;
int bStep = BLOCK_SIZE * wB;
float Csub = 0;
for (int a = aBegin, b = bBegin;
a <= aEnd;
a += aStep, b += bStep) {
__shared__ float As[BLOCK_SIZE][BLOCK_SIZE];
__shared__ float Bs[BLOCK_SIZE][BLOCK_SIZE];
As[ty][tx] = A[a + wA * ty + tx];
Bs[ty][tx] = B[b + wB * ty + tx];
// Synchronize to make sure the matrices are loaded
__syncthreads();
#pragma unroll
for (int k = 0; k < BLOCK_SIZE; ++k) {
Csub += As[ty][k] * Bs[k][tx];
}
__syncthreads();
}
// Write the block sub-matrix to device memory;
// each thread writes one element
int c = wB * BLOCK_SIZE * by + BLOCK_SIZE * bx;
C[c + wB * ty + tx] = Csub;
}
void GPU_fill_rand(float *A, int nr_rows_A, int nr_cols_A) {
// Create a pseudo-random number generator
hiprandGenerator_t prng;
hiprandCreateGenerator(&prng, HIPRAND_RNG_PSEUDO_DEFAULT);
// Set the seed for the random number generator using the system clock
hiprandSetPseudoRandomGeneratorSeed(prng, (unsigned long long) clock());
// Fill the array with random numbers on the device
hiprandGenerateUniform(prng, A, nr_rows_A * nr_cols_A);
}
int MatrixMultiply(int argc, char **argv,
int block_size, const dim3 &dimsA,
const dim3 &dimsB) {
// Allocate host memory for matrices A and B
unsigned int size_A = dimsA.x * dimsA.y;
unsigned int mem_size_A = sizeof(float) * size_A;
float *h_A = reinterpret_cast<float *>(malloc(mem_size_A));
unsigned int size_B = dimsB.x * dimsB.y;
unsigned int mem_size_B = sizeof(float) * size_B;
float *h_B = reinterpret_cast<float *>(malloc(mem_size_B));
// Allocate device memory
float *d_A, *d_B, *d_C;
// Allocate host matrix C
dim3 dimsC(dimsB.x, dimsA.y, 1);
unsigned int mem_size_C = dimsC.x * dimsC.y * sizeof(float);
float *h_C = reinterpret_cast<float *>(malloc(mem_size_C));
float *h_C_test = reinterpret_cast<float *>(malloc(mem_size_C));
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
h_C_test[i]=0;
}
if (h_C == NULL) {
fprintf(stderr, "Failed to allocate host matrix C!\n");
exit(EXIT_FAILURE);
}
hipEvent_t start;
hipEventCreate(&start);
hipEvent_t stop;
hipEventCreate(&stop);
// Record the start event
hipEventRecord(start, NULL);
hipMalloc(&d_A, mem_size_A);
hipMalloc(&d_B, mem_size_B);
hipMalloc(&d_C, mem_size_C);
GPU_fill_rand(d_A, dimsA.x, dimsA.y);
GPU_fill_rand(d_B, dimsB.x, dimsB.y);
// Only for tests purposes
hipMemcpy(h_A,d_A, mem_size_A,hipMemcpyDeviceToHost);
hipMemcpy(h_B,d_B, mem_size_A,hipMemcpyDeviceToHost);
// Setup execution parameters
dim3 threads(block_size, block_size);
dim3 grid(dimsB.x / threads.x, dimsA.y / threads.y);
// Create and start timer
printf("Computing result using CUDA Kernel...\n");
hipDeviceSynchronize();
MatrixMulCUDA<32> <<< grid, threads >>>(d_C, d_A, d_B,
dimsA.x, dimsB.x);
// Record the stop event
hipEventRecord(stop, NULL);
// Wait for the stop event to complete
hipEventSynchronize(stop);
printf("done\n");
float msecTotal = 0.0f;
hipEventElapsedTime(&msecTotal, start, stop);
// Compute and print the performance
float msecPerMatrixMul = msecTotal;
printf(
"Time spent executing by the GPU = %.3f msec," \
" WorkgroupSize= %u threads/block\n",
msecPerMatrixMul,
threads.x * threads.y);
// Copy result from device to host
hipMemcpy(h_C, d_C, mem_size_C, hipMemcpyDeviceToHost);
bool correct = true;
unsigned int cpu_start = clock();
for(int i = 0; i < dimsA.x; ++i)
for(int j = 0; j < dimsA.y; ++j)
for(int k = 0; k < dimsA.x; ++k)
{
h_C_test[j + i * dimsA.x] += h_A[i * dimsA.x + k] * h_B[k* dimsA.x +j];
}
unsigned int cpu_end = clock();
double cpuTime = (double)(cpu_end - cpu_start);
printf("Time spent executing by the CPU: %.3f msec\n", cpuTime);
printf("Checking computed result for correctness: ");
// test relative error by the formula
// |<x, y>_cpu - <x,y>_gpu|/<|x|, |y|> < eps
double eps = 1.e-6; // machine zero
const float valB = 0.01f;
for (int i = 0; i < static_cast<int>(dimsC.x * dimsC.y); i++) {
double abs_err = fabs(h_C[i] - h_C_test[i]);
double dot_length = dimsA.x;
double abs_val = fabs(h_C[i]);
double rel_err = abs_err / abs_val / dot_length;
if (rel_err > eps) {
printf("Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n",
i, h_C[i], dimsA.x * valB, eps);
correct = false;
break;
}
}
printf("%s\n", correct ? "Result = PASS" : "Result = FAIL");
// Clean up memory
free(h_A);
free(h_B);
free(h_C);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
if (correct) {
return EXIT_SUCCESS;
} else {
return EXIT_FAILURE;
}
}
int main(int argc, char **argv) {
printf("[Matrix Multiply Using CUDA] - Starting...\n");
int block_size = 32;
dim3 dimsA(10 * block_size, 10 * block_size, 1);
dim3 dimsB(10 * block_size, 10 * block_size, 1);
printf("MatrixA(%d,%d), MatrixB(%d,%d)\n", dimsA.x, dimsA.y,
dimsB.x, dimsB.y);
int matrix_result = MatrixMultiply(argc, argv, block_size, dimsA, dimsB);
exit(matrix_result);
} | .text
.file "matrixMul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z13GPU_fill_randPfii # -- Begin function _Z13GPU_fill_randPfii
.p2align 4, 0x90
.type _Z13GPU_fill_randPfii,@function
_Z13GPU_fill_randPfii: # @_Z13GPU_fill_randPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movq %rsp, %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
movq (%rsp), %r15
callq clock
movq %r15, %rdi
movq %rax, %rsi
callq hiprandSetPseudoRandomGeneratorSeed
movq (%rsp), %rdi
imull %ebx, %ebp
movslq %ebp, %rdx
movq %r14, %rsi
callq hiprandGenerateUniform
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13GPU_fill_randPfii, .Lfunc_end0-_Z13GPU_fill_randPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z14MatrixMultiplyiPPciRK4dim3S3_
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.LCPI1_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_3:
.long 0x3c23d70a # float 0.00999999977
.text
.globl _Z14MatrixMultiplyiPPciRK4dim3S3_
.p2align 4, 0x90
.type _Z14MatrixMultiplyiPPciRK4dim3S3_,@function
_Z14MatrixMultiplyiPPciRK4dim3S3_: # @_Z14MatrixMultiplyiPPciRK4dim3S3_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r15
movl %edx, 68(%rsp) # 4-byte Spill
movl 4(%rcx), %ebp
movq %rcx, 8(%rsp) # 8-byte Spill
movl (%rcx), %edi
imull %ebp, %edi
shll $2, %edi
movq %rdi, 16(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movl (%r15), %r14d
movq %r15, 128(%rsp) # 8-byte Spill
movl 4(%r15), %r12d
imull %r14d, %r12d
shll $2, %r12d
movq %r12, %rdi
callq malloc
movq %rax, %r15
imull %ebp, %r14d
leal (,%r14,4), %ebp
movq %rbp, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq malloc
movq %rax, %r13
movl %r14d, %eax
movq %r14, 168(%rsp) # 8-byte Spill
testl %r14d, %r14d
movq %rax, 144(%rsp) # 8-byte Spill
jle .LBB1_2
# %bb.1: # %.lr.ph.preheader
leaq (,%rax,4), %rdx
movq %r13, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB1_2: # %._crit_edge
cmpq $0, 24(%rsp) # 8-byte Folded Reload
je .LBB1_21
# %bb.3:
leaq 136(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 136(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 40(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 40(%rsp), %r14
movq 8(%rsp), %rcx # 8-byte Reload
movslq (%rcx), %rax
movslq 4(%rcx), %r12
imulq %rax, %r12
leaq 80(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
movq %rbp, 160(%rsp) # 8-byte Spill
movq 80(%rsp), %rbp
callq clock
movq %rbp, %rdi
movq %rax, %rsi
callq hiprandSetPseudoRandomGeneratorSeed
movq 80(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
callq hiprandGenerateUniform
movq 32(%rsp), %rax
movq %rax, 152(%rsp) # 8-byte Spill
movq 128(%rsp), %r14 # 8-byte Reload
movslq (%r14), %rax
movslq 4(%r14), %rbp
imulq %rax, %rbp
leaq 80(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
movq 80(%rsp), %r12
callq clock
movq %r12, %rdi
movq %rax, %rsi
callq hiprandSetPseudoRandomGeneratorSeed
movq 80(%rsp), %rdi
movq 152(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
callq hiprandGenerateUniform
movq 40(%rsp), %rsi
movq %rbx, %rdi
movq 16(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl 68(%rsp), %ecx # 4-byte Reload
movl %ecx, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
movl (%r14), %eax
xorl %edx, %edx
divl %ecx
movl %eax, %ebp
movq 8(%rsp), %rax # 8-byte Reload
movl 4(%rax), %eax
movl %ecx, %r14d
xorl %edx, %edx
divl %ecx
# kill: def $eax killed $eax def $rax
shlq $32, %rax
orq %rax, %rbp
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceSynchronize
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 56(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 8(%rsp), %rsi # 8-byte Reload
movl (%rsi), %esi
movq 128(%rsp), %rdi # 8-byte Reload
movl (%rdi), %edi
movq %rax, 240(%rsp)
movq %rcx, 232(%rsp)
movq %rdx, 224(%rsp)
movl %esi, 76(%rsp)
movl %edi, 72(%rsp)
leaq 240(%rsp), %rax
movq %rax, 80(%rsp)
leaq 232(%rsp), %rax
movq %rax, 88(%rsp)
leaq 224(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 48(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
movl $0, 80(%rsp)
movq 136(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
imull %r14d, %r14d
movb $1, %bpl
movl $.L.str.3, %edi
movl %r14d, %esi
movb $1, %al
callq printf
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq 160(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
movq 8(%rsp), %rax # 8-byte Reload
movl (%rax), %eax
testq %rax, %rax
je .LBB1_13
# %bb.6: # %.preheader116.lr.ph
movq 8(%rsp), %rcx # 8-byte Reload
movl 4(%rcx), %ecx
xorl %edx, %edx
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_12: # %._crit_edge120
# in Loop: Header=BB1_7 Depth=1
incl %edx
addl %eax, %r12d
cmpl %eax, %edx
je .LBB1_13
.LBB1_7: # %.preheader116
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
# Child Loop BB1_10 Depth 3
testq %rcx, %rcx
je .LBB1_12
# %bb.8: # %.preheader.lr.ph
# in Loop: Header=BB1_7 Depth=1
movl %eax, %esi
imull %edx, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_9: # %.preheader
# Parent Loop BB1_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_10 Depth 3
leal (%rsi,%rdi), %r8d
movss (%r13,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, %r9
movl %r12d, %r10d
movl %edi, %r11d
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_7 Depth=1
# Parent Loop BB1_9 Depth=2
# => This Inner Loop Header: Depth=3
movl %r10d, %r14d
movss (%rbx,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %r11d, %r14d
mulss (%r15,%r14,4), %xmm1
addss %xmm1, %xmm0
addl %eax, %r11d
incl %r10d
decq %r9
jne .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=2
movss %xmm0, (%r13,%r8,4)
incq %rdi
cmpq %rcx, %rdi
jne .LBB1_9
jmp .LBB1_12
.LBB1_13: # %._crit_edge122
callq clock
subl 16(%rsp), %eax # 4-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
cmpl $0, 168(%rsp) # 4-byte Folded Reload
jle .LBB1_20
# %bb.14: # %.lr.ph126.preheader
movq 144(%rsp), %rcx # 8-byte Reload
decq %rcx
movb $1, %bpl
xorl %r12d, %r12d
movaps .LCPI1_0(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movaps .LCPI1_1(%rip), %xmm4 # xmm4 = [NaN,NaN]
movsd .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero
movq 8(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB1_15: # %.lr.ph126
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax # 8-byte Reload
movss (%rax,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
subss (%r13,%r12,4), %xmm1
cvtss2sd %xmm0, %xmm0
andps %xmm3, %xmm1
xorps %xmm6, %xmm6
cvtss2sd %xmm1, %xmm6
movl (%r14), %eax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movaps %xmm0, %xmm5
andps %xmm4, %xmm5
divsd %xmm5, %xmm6
divsd %xmm1, %xmm6
ucomisd %xmm2, %xmm6
jbe .LBB1_17
# %bb.16: # in Loop: Header=BB1_15 Depth=1
movl %eax, %eax
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
mulss .LCPI1_3(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.6, %edi
movl %r12d, %esi
movb $3, %al
movq %rcx, %rbp
movsd %xmm6, 16(%rsp) # 8-byte Spill
callq printf
movsd 16(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
movsd .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero
movaps .LCPI1_1(%rip), %xmm4 # xmm4 = [NaN,NaN]
movaps .LCPI1_0(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movq %rbp, %rcx
xorl %ebp, %ebp
.LBB1_17: # in Loop: Header=BB1_15 Depth=1
ucomisd %xmm2, %xmm6
ja .LBB1_19
# %bb.18: # in Loop: Header=BB1_15 Depth=1
leaq 1(%r12), %rax
cmpq %r12, %rcx
movq %rax, %r12
jne .LBB1_15
.LBB1_19: # %._crit_edge127.loopexit
andb $1, %bpl
.LBB1_20: # %._crit_edge127
testb %bpl, %bpl
movl $.L.str.9, %eax
movl $.L.str.8, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
xorb $1, %bpl
movzbl %bpl, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 304
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $34, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14MatrixMultiplyiPPciRK4dim3S3_, .Lfunc_end1-_Z14MatrixMultiplyiPPciRK4dim3S3_
.cfi_endproc
# -- End function
.section .text._Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii,"axG",@progbits,_Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii,comdat
.weak _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii # -- Begin function _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii
.p2align 4, 0x90
.type _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii,@function
_Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii: # @_Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii, .Lfunc_end2-_Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii
.cfi_endproc
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $.Lstr.2, %edi
callq puts@PLT
movabsq $1374389535040, %rax # imm = 0x14000000140
movq %rax, 12(%rsp)
movl $1, 20(%rsp)
movq %rax, (%rsp)
movl $1, 8(%rsp)
movl $.L.str.11, %edi
movl $320, %esi # imm = 0x140
movl $320, %edx # imm = 0x140
movl $320, %ecx # imm = 0x140
movl $320, %r8d # imm = 0x140
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rcx
movq %rsp, %r8
movl $32, %edx
callq _Z14MatrixMultiplyiPPciRK4dim3S3_
movl %eax, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate host matrix C!\n"
.size .L.str, 35
.type _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,@object # @_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.section .rodata._Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,"aG",@progbits,_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,comdat
.weak _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.p2align 3, 0x0
_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii:
.quad _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii
.size _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Time spent executing by the GPU = %.3f msec, WorkgroupSize= %u threads/block\n"
.size .L.str.3, 78
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time spent executing by the CPU: %.3f msec\n"
.size .L.str.4, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Checking computed result for correctness: "
.size .L.str.5, 43
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n"
.size .L.str.6, 55
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Result = PASS"
.size .L.str.8, 14
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result = FAIL"
.size .L.str.9, 14
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "MatrixA(%d,%d), MatrixB(%d,%d)\n"
.size .L.str.11, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Computing result using CUDA Kernel..."
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "done"
.size .Lstr.1, 5
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "[Matrix Multiply Using CUDA] - Starting..."
.size .Lstr.2, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_TID.X ; /* 0x0000000000007919 */
/* 0x000e220000002100 */
/*0020*/ ISETP.LT.AND P0, PT, RZ, c[0x0][0x178], PT ; /* 0x00005e00ff007a0c */
/* 0x000fe20003f01270 */
/*0030*/ HFMA2.MMA R18, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff127435 */
/* 0x000fe200000001ff */
/*0040*/ MOV R16, c[0x0][0x17c] ; /* 0x00005f0000107a02 */
/* 0x000fe20000000f00 */
/*0050*/ S2R R5, SR_CTAID.X ; /* 0x0000000000057919 */
/* 0x000e220000002500 */
/*0060*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe40000000a00 */
/*0070*/ SHF.L.U32 R16, R16, 0x5, RZ ; /* 0x0000000510107819 */
/* 0x000fe200000006ff */
/*0080*/ S2R R7, SR_TID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002200 */
/*0090*/ S2R R6, SR_CTAID.Y ; /* 0x0000000000067919 */
/* 0x000ea40000002600 */
/*00a0*/ @!P0 MOV R23, RZ ; /* 0x000000ff00178202 */
/* 0x000fc40000000f00 */
/*00b0*/ LEA R2, R5, R0, 0x5 ; /* 0x0000000005027211 */
/* 0x001fca00078e28ff */
/*00c0*/ IMAD R3, R7, c[0x0][0x17c], R2 ; /* 0x00005f0007037a24 */
/* 0x002fc800078e0202 */
/*00d0*/ IMAD R3, R16, R6, R3 ; /* 0x0000000610037224 */
/* 0x004fc800078e0203 */
/*00e0*/ IMAD.WIDE R18, R3, R18, c[0x0][0x160] ; /* 0x0000580003127625 */
/* 0x000fe200078e0212 */
/*00f0*/ @!P0 BRA 0x740 ; /* 0x0000064000008947 */
/* 0x000fea0003800000 */
/*0100*/ LEA R3, R6.reuse, R7, 0x5 ; /* 0x0000000706037211 */
/* 0x040fe200078e28ff */
/*0110*/ IMAD R4, R7.reuse, c[0x0][0x17c], R0.reuse ; /* 0x00005f0007047a24 */
/* 0x140fe200078e0200 */
/*0120*/ MOV R21, 0x4 ; /* 0x0000000400157802 */
/* 0x000fe20000000f00 */
/*0130*/ IMAD R6, R6, c[0x0][0x178], RZ ; /* 0x00005e0006067a24 */
/* 0x000fe200078e02ff */
/*0140*/ SHF.L.U32 R7, R7, 0x7, RZ ; /* 0x0000000707077819 */
/* 0x000fe200000006ff */
/*0150*/ IMAD R3, R3, c[0x0][0x178], R0 ; /* 0x00005e0003037a24 */
/* 0x000fe200078e0200 */
/*0160*/ LEA R20, R5, R4, 0x5 ; /* 0x0000000405147211 */
/* 0x000fe400078e28ff */
/*0170*/ SHF.L.U32 R6, R6, 0x5, RZ ; /* 0x0000000506067819 */
/* 0x000fe200000006ff */
/*0180*/ IMAD.WIDE R2, R3, R21, c[0x0][0x168] ; /* 0x00005a0003027625 */
/* 0x000fe200078e0215 */
/*0190*/ MOV R23, RZ ; /* 0x000000ff00177202 */
/* 0x000fc40000000f00 */
/*01a0*/ LEA R4, R0, R7, 0x2 ; /* 0x0000000700047211 */
/* 0x000fe200078e10ff */
/*01b0*/ IMAD.WIDE R20, R20, R21, c[0x0][0x170] ; /* 0x00005c0014147625 */
/* 0x000fe200078e0215 */
/*01c0*/ MOV R5, R3 ; /* 0x0000000300057202 */
/* 0x000fe40000000f00 */
/*01d0*/ IADD3 R3, R6, c[0x0][0x178], RZ ; /* 0x00005e0006037a10 */
/* 0x000fe40007ffe0ff */
/*01e0*/ MOV R25, R5 ; /* 0x0000000500197202 */
/* 0x000fe20000000f00 */
/*01f0*/ LDG.E R29, [R20.64] ; /* 0x00000004141d7981 */
/* 0x0000a2000c1e1900 */
/*0200*/ MOV R24, R2 ; /* 0x0000000200187202 */
/* 0x000fca0000000f00 */
/*0210*/ LDG.E R25, [R24.64] ; /* 0x0000000418197981 */
/* 0x000ee2000c1e1900 */
/*0220*/ IADD3 R6, R6, 0x20, RZ ; /* 0x0000002006067810 */
/* 0x000fe40007ffe0ff */
/*0230*/ IADD3 R2, P1, R2, 0x80, RZ ; /* 0x0000008002027810 */
/* 0x000fe20007f3e0ff */
/*0240*/ IMAD.WIDE R20, R16, 0x4, R20 ; /* 0x0000000410147825 */
/* 0x001fe200078e0214 */
/*0250*/ ISETP.GE.AND P0, PT, R6, R3, PT ; /* 0x000000030600720c */
/* 0x000fe40003f06270 */
/*0260*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x000fe20000ffe4ff */
/*0270*/ STS [R4+0x1000], R29 ; /* 0x0010001d04007388 */
/* 0x004fe80000000800 */
/*0280*/ STS [R4], R25 ; /* 0x0000001904007388 */
/* 0x008fe80000000800 */
/*0290*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*02a0*/ LDS R26, [R0.X4+0x1000] ; /* 0x00100000001a7984 */
/* 0x000fe80000004800 */
/*02b0*/ LDS.128 R12, [R7] ; /* 0x00000000070c7984 */
/* 0x000e280000000c00 */
/*02c0*/ LDS R28, [R0.X4+0x1080] ; /* 0x00108000001c7984 */
/* 0x000e680000004800 */
/*02d0*/ LDS R27, [R0.X4+0x1100] ; /* 0x00110000001b7984 */
/* 0x000ea80000004800 */
/*02e0*/ LDS R22, [R0.X4+0x1180] ; /* 0x0011800000167984 */
/* 0x000ee80000004800 */
/*02f0*/ LDS R17, [R0.X4+0x1200] ; /* 0x0012000000117984 */
/* 0x000fe80000004800 */
/*0300*/ LDS.128 R8, [R7+0x10] ; /* 0x0000100007087984 */
/* 0x000f280000000c00 */
/*0310*/ LDS R24, [R0.X4+0x1280] ; /* 0x0012800000187984 */
/* 0x000f680000004800 */
/*0320*/ LDS R25, [R0.X4+0x1300] ; /* 0x0013000000197984 */
/* 0x000f620000004800 */
/*0330*/ FFMA R12, R26, R12, R23 ; /* 0x0000000c1a0c7223 */
/* 0x001fc60000000017 */
/*0340*/ LDS R26, [R0.X4+0x1380] ; /* 0x00138000001a7984 */
/* 0x000e220000004800 */
/*0350*/ FFMA R12, R28, R13, R12 ; /* 0x0000000d1c0c7223 */
/* 0x002fc6000000000c */
/*0360*/ LDS R23, [R0.X4+0x1400] ; /* 0x0014000000177984 */
/* 0x000fe20000004800 */
/*0370*/ FFMA R12, R27, R14, R12 ; /* 0x0000000e1b0c7223 */
/* 0x004fc6000000000c */
/*0380*/ LDS R28, [R0.X4+0x1580] ; /* 0x00158000001c7984 */
/* 0x000fe20000004800 */
/*0390*/ FFMA R22, R22, R15, R12 ; /* 0x0000000f16167223 */
/* 0x008fc6000000000c */
/*03a0*/ LDS.128 R12, [R7+0x20] ; /* 0x00002000070c7984 */
/* 0x000e620000000c00 */
/*03b0*/ FFMA R8, R17, R8, R22 ; /* 0x0000000811087223 */
/* 0x010fc60000000016 */
/*03c0*/ LDS R22, [R0.X4+0x1480] ; /* 0x0014800000167984 */
/* 0x000ea20000004800 */
/*03d0*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x020fc60000000008 */
/*03e0*/ LDS R17, [R0.X4+0x1500] ; /* 0x0015000000117984 */
/* 0x000ee20000004800 */
/*03f0*/ FFMA R8, R25, R10, R8 ; /* 0x0000000a19087223 */
/* 0x000fc60000000008 */
/*0400*/ LDS R25, [R0.X4+0x1600] ; /* 0x0016000000197984 */
/* 0x000fe80000004800 */
/*0410*/ LDS R24, [R0.X4+0x1780] ; /* 0x0017800000187984 */
/* 0x000fe20000004800 */
/*0420*/ FFMA R26, R26, R11, R8 ; /* 0x0000000b1a1a7223 */
/* 0x001fc60000000008 */
/*0430*/ LDS.128 R8, [R7+0x30] ; /* 0x0000300007087984 */
/* 0x000e220000000c00 */
/*0440*/ FFMA R12, R23, R12, R26 ; /* 0x0000000c170c7223 */
/* 0x002fc6000000001a */
/*0450*/ LDS R26, [R0.X4+0x1680] ; /* 0x00168000001a7984 */
/* 0x000e680000004800 */
/*0460*/ LDS R23, [R0.X4+0x1700] ; /* 0x0017000000177984 */
/* 0x000f220000004800 */
/*0470*/ FFMA R12, R22, R13, R12 ; /* 0x0000000d160c7223 */
/* 0x004fc6000000000c */
/*0480*/ LDS R22, [R0.X4+0x1880] ; /* 0x0018800000167984 */
/* 0x000fe20000004800 */
/*0490*/ FFMA R12, R17, R14, R12 ; /* 0x0000000e110c7223 */
/* 0x008fc6000000000c */
/*04a0*/ LDS R17, [R0.X4+0x1800] ; /* 0x0018000000117984 */
/* 0x000fe20000004800 */
/*04b0*/ FFMA R28, R28, R15, R12 ; /* 0x0000000f1c1c7223 */
/* 0x000fc6000000000c */
/*04c0*/ LDS.128 R12, [R7+0x40] ; /* 0x00004000070c7984 */
/* 0x000ea20000000c00 */
/*04d0*/ FFMA R8, R25, R8, R28 ; /* 0x0000000819087223 */
/* 0x001fc6000000001c */
/*04e0*/ LDS R25, [R0.X4+0x1900] ; /* 0x0019000000197984 */
/* 0x000e280000004800 */
/*04f0*/ LDS R28, [R0.X4+0x1b80] ; /* 0x001b8000001c7984 */
/* 0x000fe20000004800 */
/*0500*/ FFMA R8, R26, R9, R8 ; /* 0x000000091a087223 */
/* 0x002fc60000000008 */
/*0510*/ LDS R26, [R0.X4+0x1980] ; /* 0x00198000001a7984 */
/* 0x000e620000004800 */
/*0520*/ FFMA R8, R23, R10, R8 ; /* 0x0000000a17087223 */
/* 0x010fc60000000008 */
/*0530*/ LDS R23, [R0.X4+0x1a00] ; /* 0x001a000000177984 */
/* 0x000fe20000004800 */
/*0540*/ FFMA R24, R24, R11, R8 ; /* 0x0000000b18187223 */
/* 0x000fc60000000008 */
/*0550*/ LDS.128 R8, [R7+0x50] ; /* 0x0000500007087984 */
/* 0x000ee20000000c00 */
/*0560*/ FFMA R12, R17, R12, R24 ; /* 0x0000000c110c7223 */
/* 0x004fc60000000018 */
/*0570*/ LDS R24, [R0.X4+0x1a80] ; /* 0x001a800000187984 */
/* 0x000ea20000004800 */
/*0580*/ FFMA R12, R22, R13, R12 ; /* 0x0000000d160c7223 */
/* 0x000fc6000000000c */
/*0590*/ LDS R17, [R0.X4+0x1b00] ; /* 0x001b000000117984 */
/* 0x000f280000004800 */
/*05a0*/ LDS R22, [R0.X4+0x1c80] ; /* 0x001c800000167984 */
/* 0x000fe20000004800 */
/*05b0*/ FFMA R12, R25, R14, R12 ; /* 0x0000000e190c7223 */
/* 0x001fc6000000000c */
/*05c0*/ LDS R25, [R0.X4+0x1c00] ; /* 0x001c000000197984 */
/* 0x000fe20000004800 */
/*05d0*/ FFMA R26, R26, R15, R12 ; /* 0x0000000f1a1a7223 */
/* 0x002fc6000000000c */
/*05e0*/ LDS.128 R12, [R7+0x60] ; /* 0x00006000070c7984 */
/* 0x000e220000000c00 */
/*05f0*/ FFMA R8, R23, R8, R26 ; /* 0x0000000817087223 */
/* 0x008fc6000000001a */
/*0600*/ LDS R23, [R0.X4+0x1d00] ; /* 0x001d000000177984 */
/* 0x000e620000004800 */
/*0610*/ FFMA R8, R24, R9, R8 ; /* 0x0000000918087223 */
/* 0x004fc60000000008 */
/*0620*/ LDS R24, [R0.X4+0x1d80] ; /* 0x001d800000187984 */
/* 0x000ea20000004800 */
/*0630*/ FFMA R8, R17, R10, R8 ; /* 0x0000000a11087223 */
/* 0x010fc60000000008 */
/*0640*/ LDS R17, [R0.X4+0x1e00] ; /* 0x001e000000117984 */
/* 0x000fe20000004800 */
/*0650*/ FFMA R28, R28, R11, R8 ; /* 0x0000000b1c1c7223 */
/* 0x000fc60000000008 */
/*0660*/ LDS.128 R8, [R7+0x70] ; /* 0x0000700007087984 */
/* 0x000ee20000000c00 */
/*0670*/ FFMA R28, R25, R12, R28 ; /* 0x0000000c191c7223 */
/* 0x001fc6000000001c */
/*0680*/ LDS R12, [R0.X4+0x1e80] ; /* 0x001e8000000c7984 */
/* 0x000e220000004800 */
/*0690*/ FFMA R13, R22, R13, R28 ; /* 0x0000000d160d7223 */
/* 0x000fc6000000001c */
/*06a0*/ LDS R25, [R0.X4+0x1f00] ; /* 0x001f000000197984 */
/* 0x000f220000004800 */
/*06b0*/ FFMA R13, R23, R14, R13 ; /* 0x0000000e170d7223 */
/* 0x002fc6000000000d */
/*06c0*/ LDS R22, [R0.X4+0x1f80] ; /* 0x001f800000167984 */
/* 0x000e620000004800 */
/*06d0*/ FFMA R13, R24, R15, R13 ; /* 0x0000000f180d7223 */
/* 0x004fc8000000000d */
/*06e0*/ FFMA R8, R17, R8, R13 ; /* 0x0000000811087223 */
/* 0x008fc8000000000d */
/*06f0*/ FFMA R8, R12, R9, R8 ; /* 0x000000090c087223 */
/* 0x001fc80000000008 */
/*0700*/ FFMA R8, R25, R10, R8 ; /* 0x0000000a19087223 */
/* 0x010fc80000000008 */
/*0710*/ FFMA R23, R22, R11, R8 ; /* 0x0000000b16177223 */
/* 0x002fe20000000008 */
/*0720*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0730*/ @!P0 BRA 0x1e0 ; /* 0xfffffaa000008947 */
/* 0x000fea000383ffff */
/*0740*/ STG.E [R18.64], R23 ; /* 0x0000001712007986 */
/* 0x000fe2000c101904 */
/*0750*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0760*/ BRA 0x760; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0780*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0790*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*07f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.section .text._Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,"axG",@progbits,_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,comdat
.protected _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.globl _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.p2align 8
.type _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,@function
_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii:
s_load_b64 s[2:3], s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v0, 0x3ff, v0
s_lshl_b32 s8, s14, 5
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2)
v_mul_lo_u32 v5, v1, s3
s_lshl_b32 s3, s3, 5
s_cmp_lt_i32 s2, 1
s_cbranch_scc1 .LBB0_3
s_load_b128 s[4:7], s[0:1], 0x8
v_lshlrev_b32_e32 v3, 2, v0
v_lshl_add_u32 v4, s15, 5, v1
v_dual_mov_b32 v59, 0 :: v_dual_lshlrev_b32 v6, 7, v1
s_mul_i32 s9, s2, s15
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
v_or_b32_e32 v8, 0x1000, v3
v_mad_u64_u32 v[1:2], null, s2, v4, v[0:1]
s_delay_alu instid0(VALU_DEP_3)
v_add_nc_u32_e32 v7, v6, v3
v_or_b32_e32 v9, 4, v6
v_add_nc_u32_e32 v10, 0x1080, v3
v_or_b32_e32 v11, 8, v6
v_add_nc_u32_e32 v12, 0x1100, v3
v_add_nc_u32_e32 v13, v8, v6
v_or_b32_e32 v14, 12, v6
v_add_nc_u32_e32 v15, 0x1180, v3
v_or_b32_e32 v16, 16, v6
v_add_nc_u32_e32 v17, 0x1200, v3
v_or_b32_e32 v18, 20, v6
v_add_nc_u32_e32 v19, 0x1280, v3
v_or_b32_e32 v20, 24, v6
v_add_nc_u32_e32 v21, 0x1300, v3
v_or_b32_e32 v22, 28, v6
v_add_nc_u32_e32 v23, 0x1380, v3
v_or_b32_e32 v24, 32, v6
v_add_nc_u32_e32 v25, 0x1400, v3
v_or_b32_e32 v26, 36, v6
v_add_nc_u32_e32 v27, 0x1480, v3
v_or_b32_e32 v28, 40, v6
v_add_nc_u32_e32 v29, 0x1500, v3
v_or_b32_e32 v30, 44, v6
v_add_nc_u32_e32 v31, 0x1580, v3
v_or_b32_e32 v32, 48, v6
v_add_nc_u32_e32 v33, 0x1600, v3
v_or_b32_e32 v34, 52, v6
v_add_nc_u32_e32 v35, 0x1680, v3
v_or_b32_e32 v36, 56, v6
v_add_nc_u32_e32 v37, 0x1700, v3
v_or_b32_e32 v38, 60, v6
v_add_nc_u32_e32 v39, 0x1780, v3
v_or_b32_e32 v40, 64, v6
v_add_nc_u32_e32 v41, 0x1800, v3
v_or_b32_e32 v42, 0x44, v6
v_add_nc_u32_e32 v43, 0x1880, v3
v_or_b32_e32 v44, 0x48, v6
v_add_nc_u32_e32 v45, 0x1900, v3
v_or_b32_e32 v46, 0x4c, v6
v_add_nc_u32_e32 v47, 0x1980, v3
v_or_b32_e32 v48, 0x50, v6
v_add_nc_u32_e32 v49, 0x1a00, v3
v_or_b32_e32 v50, 0x54, v6
v_add_nc_u32_e32 v51, 0x1a80, v3
v_or_b32_e32 v52, 0x58, v6
v_add_nc_u32_e32 v53, 0x1b00, v3
v_or_b32_e32 v54, 0x5c, v6
v_add_nc_u32_e32 v55, 0x1b80, v3
v_or_b32_e32 v56, 0x60, v6
v_add_nc_u32_e32 v57, 0x1c00, v3
v_or_b32_e32 v58, 0x64, v6
v_add_nc_u32_e32 v60, 0x1c80, v3
v_or_b32_e32 v61, 0x68, v6
v_add_nc_u32_e32 v62, 0x1d00, v3
v_or_b32_e32 v63, 0x6c, v6
v_add_nc_u32_e32 v64, 0x1d80, v3
v_or_b32_e32 v65, 0x70, v6
v_add_nc_u32_e32 v66, 0x1e00, v3
v_or_b32_e32 v67, 0x74, v6
v_add_nc_u32_e32 v68, 0x1e80, v3
v_or_b32_e32 v69, 0x78, v6
v_add_nc_u32_e32 v70, 0x1f00, v3
v_or_b32_e32 v71, 0x7c, v6
v_add_nc_u32_e32 v72, 0x1f80, v3
v_add3_u32 v3, v0, v5, s8
s_lshl_b32 s9, s9, 5
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s2, s9, s2
.LBB0_2:
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v4, 31, v3
s_add_i32 s9, s9, 32
s_cmp_ge_i32 s9, s2
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[73:74], 2, v[1:2]
v_lshlrev_b64 v[75:76], 2, v[3:4]
v_add_nc_u32_e32 v3, s3, v3
v_add_nc_u32_e32 v1, 32, v1
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_4)
v_add_co_u32 v73, vcc_lo, s4, v73
v_add_co_ci_u32_e32 v74, vcc_lo, s5, v74, vcc_lo
v_add_co_u32 v75, vcc_lo, s6, v75
v_add_co_ci_u32_e32 v76, vcc_lo, s7, v76, vcc_lo
global_load_b32 v2, v[73:74], off
global_load_b32 v4, v[75:76], off
s_waitcnt vmcnt(1)
ds_store_b32 v7, v2
s_waitcnt vmcnt(0)
ds_store_b32 v13, v4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
ds_load_b32 v2, v6
ds_load_b32 v4, v8
ds_load_b32 v73, v9
ds_load_b32 v74, v10
ds_load_b32 v75, v11
ds_load_b32 v76, v12
ds_load_b32 v77, v14
ds_load_b32 v78, v15
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v16
ds_load_b32 v4, v17
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v18
ds_load_b32 v74, v19
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v20
ds_load_b32 v76, v21
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v22
ds_load_b32 v78, v23
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v24
ds_load_b32 v4, v25
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v26
ds_load_b32 v74, v27
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v28
ds_load_b32 v76, v29
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v30
ds_load_b32 v78, v31
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v32
ds_load_b32 v4, v33
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v34
ds_load_b32 v74, v35
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v36
ds_load_b32 v76, v37
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v38
ds_load_b32 v78, v39
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v40
ds_load_b32 v4, v41
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v42
ds_load_b32 v74, v43
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v44
ds_load_b32 v76, v45
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v46
ds_load_b32 v78, v47
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v48
ds_load_b32 v4, v49
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v50
ds_load_b32 v74, v51
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v52
ds_load_b32 v76, v53
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v54
ds_load_b32 v78, v55
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v56
ds_load_b32 v4, v57
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v58
ds_load_b32 v74, v60
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v61
ds_load_b32 v76, v62
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v77, v78
ds_load_b32 v77, v63
ds_load_b32 v78, v64
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v2, v4
ds_load_b32 v2, v65
ds_load_b32 v4, v66
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v73, v74
ds_load_b32 v73, v67
ds_load_b32 v74, v68
s_waitcnt lgkmcnt(6)
v_fmac_f32_e32 v59, v75, v76
ds_load_b32 v75, v69
ds_load_b32 v76, v70
ds_load_b32 v79, v71
ds_load_b32 v80, v72
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_fmac_f32_e32 v59, v77, v78
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v59, v2, v4
v_fmac_f32_e32 v59, v73, v74
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_fmac_f32_e32 v59, v75, v76
v_fmac_f32_e32 v59, v79, v80
s_cbranch_scc0 .LBB0_2
s_branch .LBB0_4
.LBB0_3:
v_mov_b32_e32 v59, 0
.LBB0_4:
v_add_nc_u32_e32 v0, s8, v0
s_load_b64 s[0:1], s[0:1], 0x0
s_mul_i32 s3, s3, s15
s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
v_add3_u32 v0, v0, v5, s3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_ashrrev_i32_e32 v1, 31, v0
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, s0, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_store_b32 v[0:1], v59, off
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 32
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 81
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.section .text._Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,"axG",@progbits,_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,comdat
.Lfunc_end0:
.size _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, .Lfunc_end0-_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 32
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 81
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_000ab6c2_00000000-6_matrixMul.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii, @function
_ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii:
.LFB3797:
.cfi_startproc
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movq %rsp, %rax
movq %rax, 128(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L5
.L1:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L6
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L5:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L1
.L6:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3797:
.size _ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii, .-_ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii
.section .text._Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,"axG",@progbits,_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,comdat
.weak _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.type _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, @function
_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii:
.LFB4129:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE4129:
.size _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, .-_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.text
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3775:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3775:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z13GPU_fill_randPfii
.type _Z13GPU_fill_randPfii, @function
_Z13GPU_fill_randPfii:
.LFB3770:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $16, %rsp
.cfi_def_cfa_offset 48
movq %rdi, %rbp
movl %esi, %ebx
movl %edx, %r12d
movq %fs:40, %rax
movq %rax, 8(%rsp)
xorl %eax, %eax
movq %rsp, %rdi
movl $100, %esi
call curandCreateGenerator@PLT
call clock@PLT
movq %rax, %rsi
movq (%rsp), %rdi
call curandSetPseudoRandomGeneratorSeed@PLT
imull %r12d, %ebx
movslq %ebx, %rdx
movq %rbp, %rsi
movq (%rsp), %rdi
call curandGenerateUniform@PLT
movq 8(%rsp), %rax
subq %fs:40, %rax
jne .L14
addq $16, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L14:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3770:
.size _Z13GPU_fill_randPfii, .-_Z13GPU_fill_randPfii
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Result = PASS"
.LC1:
.string "Result = FAIL"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC3:
.string "Failed to allocate host matrix C!\n"
.align 8
.LC4:
.string "Computing result using CUDA Kernel...\n"
.section .rodata.str1.1
.LC5:
.string "done\n"
.section .rodata.str1.8
.align 8
.LC6:
.string "Time spent executing by the GPU = %.3f msec, WorkgroupSize= %u threads/block\n"
.align 8
.LC7:
.string "Time spent executing by the CPU: %.3f msec\n"
.align 8
.LC8:
.string "Checking computed result for correctness: "
.align 8
.LC12:
.string "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n"
.section .rodata.str1.1
.LC13:
.string "%s\n"
.text
.globl _Z14MatrixMultiplyiPPciRK4dim3S3_
.type _Z14MatrixMultiplyiPPciRK4dim3S3_, @function
_Z14MatrixMultiplyiPPciRK4dim3S3_:
.LFB3771:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $136, %rsp
.cfi_def_cfa_offset 192
movl %edx, 16(%rsp)
movq %rcx, %r13
movq %r8, %r14
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
movl 4(%rcx), %r12d
movl %r12d, %eax
imull (%rcx), %eax
leal 0(,%rax,4), %eax
movq %rax, 8(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbp
movl (%r14), %r15d
movl %r15d, %eax
imull 4(%r14), %eax
leal 0(,%rax,4), %eax
movq %rax, 40(%rsp)
movq %rax, %rdi
call malloc@PLT
movq %rax, %rbx
movl %r12d, %edi
imull %r15d, %edi
movl %edi, 28(%rsp)
leal 0(,%rdi,4), %r12d
movq %r12, 32(%rsp)
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
movq %r12, %rdi
call malloc@PLT
movq %rax, %r12
movl 28(%rsp), %edi
testl %edi, %edi
jle .L16
movl %edi, %edx
leaq (%rax,%rdx,4), %rdx
.L17:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L17
.L16:
testq %r15, %r15
je .L45
leaq 80(%rsp), %rdi
call cudaEventCreate@PLT
leaq 88(%rsp), %rdi
call cudaEventCreate@PLT
movl $0, %esi
movq 80(%rsp), %rdi
call cudaEventRecord@PLT
leaq 56(%rsp), %rdi
movq 8(%rsp), %rsi
call cudaMalloc@PLT
leaq 64(%rsp), %rdi
movq 40(%rsp), %rsi
call cudaMalloc@PLT
leaq 72(%rsp), %rdi
movq 32(%rsp), %rsi
call cudaMalloc@PLT
movl 4(%r13), %edx
movl 0(%r13), %esi
movq 56(%rsp), %rdi
call _Z13GPU_fill_randPfii
movl 4(%r14), %edx
movl (%r14), %esi
movq 64(%rsp), %rdi
call _Z13GPU_fill_randPfii
movl $2, %ecx
movq 8(%rsp), %rdx
movq 56(%rsp), %rsi
movq %rbp, %rdi
call cudaMemcpy@PLT
movl $2, %ecx
movq 8(%rsp), %rdx
movq 64(%rsp), %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl 16(%rsp), %ecx
movl $1, 104(%rsp)
movl 4(%r13), %eax
movl $0, %edx
divl %ecx
movl %eax, %esi
movl (%r14), %eax
movl $0, %edx
divl %ecx
movl %eax, 108(%rsp)
movl %esi, 112(%rsp)
movl $1, 116(%rsp)
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
call cudaDeviceSynchronize@PLT
movl 16(%rsp), %eax
movl %eax, 96(%rsp)
movl %eax, 100(%rsp)
movl 104(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 96(%rsp), %rdx
movq 108(%rsp), %rdi
movl 116(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L46
.L19:
movl $0, %esi
movq 88(%rsp), %rdi
call cudaEventRecord@PLT
movq 88(%rsp), %rdi
call cudaEventSynchronize@PLT
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0x00000000, 52(%rsp)
leaq 52(%rsp), %rdi
movq 88(%rsp), %rdx
movq 80(%rsp), %rsi
call cudaEventElapsedTime@PLT
movl 16(%rsp), %edx
imull %edx, %edx
pxor %xmm0, %xmm0
cvtss2sd 52(%rsp), %xmm0
leaq .LC6(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movl $2, %ecx
movq 32(%rsp), %rdx
movq 72(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
call clock@PLT
movq %rax, %r14
movl 0(%r13), %edi
testl %edi, %edi
je .L20
movl 4(%r13), %r11d
movl %edi, %r8d
movl $0, %r10d
movl $0, %edx
movq %rax, 16(%rsp)
jmp .L21
.L45:
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
movl 0(%r13), %ecx
movl (%r14), %r8d
movq 64(%rsp), %rdx
movq 56(%rsp), %rsi
movq 72(%rsp), %rdi
call _ZL49__device_stub__Z13MatrixMulCUDAILi32EEvPfS0_S0_iiPfS_S_ii
jmp .L19
.L24:
movl %r9d, %ecx
leal (%r10,%r9), %eax
leaq (%r12,%rax,4), %r14
movss (%r14), %xmm1
movl %r10d, %eax
.L22:
movl %eax, %esi
movl %ecx, %edx
movss 0(%rbp,%rsi,4), %xmm0
mulss (%rbx,%rdx,4), %xmm0
addss %xmm0, %xmm1
addl $1, %eax
addl %edi, %ecx
cmpl %r8d, %eax
jne .L22
movss %xmm1, (%r14)
addl $1, %r9d
cmpl %r9d, %r11d
jne .L24
movl 8(%rsp), %edx
.L23:
addl $1, %edx
addl %edi, %r10d
addl %edi, %r8d
cmpl %edi, %edx
je .L43
.L21:
testl %r11d, %r11d
je .L23
movl $0, %r9d
movl %edx, 8(%rsp)
jmp .L24
.L43:
movq 16(%rsp), %r14
.L20:
call clock@PLT
subl %r14d, %eax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl 28(%rsp), %edi
testl %edi, %edi
jle .L36
movl 0(%r13), %ecx
movl %ecx, %eax
pxor %xmm5, %xmm5
cvtsi2sdq %rax, %xmm5
movl %edi, %edx
movl $0, %eax
movss .LC9(%rip), %xmm3
movsd .LC10(%rip), %xmm4
.L34:
movss (%r15,%rax,4), %xmm0
movaps %xmm0, %xmm1
subss (%r12,%rax,4), %xmm1
andps %xmm3, %xmm1
cvtss2sd %xmm1, %xmm1
movaps %xmm0, %xmm2
andps %xmm3, %xmm2
cvtss2sd %xmm2, %xmm2
divsd %xmm2, %xmm1
divsd %xmm5, %xmm1
comisd %xmm4, %xmm1
ja .L47
addq $1, %rax
cmpq %rax, %rdx
jne .L34
movl $1, %r12d
leaq .LC0(%rip), %rdx
jmp .L27
.L47:
movl %ecx, %ecx
pxor %xmm1, %xmm1
cvtsi2ssq %rcx, %xmm1
mulss .LC11(%rip), %xmm1
cvtss2sd %xmm0, %xmm0
movsd .LC10(%rip), %xmm2
cvtss2sd %xmm1, %xmm1
movl %eax, %edx
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $3, %eax
call __printf_chk@PLT
movl $0, %r12d
leaq .LC1(%rip), %rdx
.L27:
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq %r15, %rdi
call free@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 64(%rsp), %rdi
call cudaFree@PLT
movq 72(%rsp), %rdi
call cudaFree@PLT
movl %r12d, %eax
xorl $1, %eax
movzbl %al, %eax
movq 120(%rsp), %rdx
subq %fs:40, %rdx
jne .L48
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L36:
.cfi_restore_state
movl $1, %r12d
leaq .LC0(%rip), %rdx
jmp .L27
.L48:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3771:
.size _Z14MatrixMultiplyiPPciRK4dim3S3_, .-_Z14MatrixMultiplyiPPciRK4dim3S3_
.section .rodata.str1.8
.align 8
.LC14:
.string "[Matrix Multiply Using CUDA] - Starting...\n"
.align 8
.LC15:
.string "MatrixA(%d,%d), MatrixB(%d,%d)\n"
.text
.globl main
.type main, @function
main:
.LFB3772:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $40, %rsp
.cfi_def_cfa_offset 64
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC14(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl $320, (%rsp)
movl $320, 4(%rsp)
movl $1, 8(%rsp)
movl $320, 12(%rsp)
movl $320, 16(%rsp)
movl $1, 20(%rsp)
movl $320, %r9d
movl $320, %r8d
movl $320, %ecx
movl $320, %edx
leaq .LC15(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq %rsp, %rcx
leaq 12(%rsp), %r8
movl $32, %edx
movq %rbp, %rsi
movl %ebx, %edi
call _Z14MatrixMultiplyiPPciRK4dim3S3_
movl %eax, %edi
call exit@PLT
.cfi_endproc
.LFE3772:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC16:
.string "_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3800:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC16(%rip), %rdx
movq %rdx, %rcx
leaq _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3800:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long -1598689907
.long 1051772663
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC11:
.long 1008981770
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrixMul.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z13GPU_fill_randPfii # -- Begin function _Z13GPU_fill_randPfii
.p2align 4, 0x90
.type _Z13GPU_fill_randPfii,@function
_Z13GPU_fill_randPfii: # @_Z13GPU_fill_randPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %edx, %ebx
movl %esi, %ebp
movq %rdi, %r14
movq %rsp, %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
movq (%rsp), %r15
callq clock
movq %r15, %rdi
movq %rax, %rsi
callq hiprandSetPseudoRandomGeneratorSeed
movq (%rsp), %rdi
imull %ebx, %ebp
movslq %ebp, %rdx
movq %r14, %rsi
callq hiprandGenerateUniform
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z13GPU_fill_randPfii, .Lfunc_end0-_Z13GPU_fill_randPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z14MatrixMultiplyiPPciRK4dim3S3_
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.LCPI1_1:
.quad 0x7fffffffffffffff # double NaN
.quad 0x7fffffffffffffff # double NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_2:
.quad 0x3eb0c6f7a0b5ed8d # double 9.9999999999999995E-7
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0
.LCPI1_3:
.long 0x3c23d70a # float 0.00999999977
.text
.globl _Z14MatrixMultiplyiPPciRK4dim3S3_
.p2align 4, 0x90
.type _Z14MatrixMultiplyiPPciRK4dim3S3_,@function
_Z14MatrixMultiplyiPPciRK4dim3S3_: # @_Z14MatrixMultiplyiPPciRK4dim3S3_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $248, %rsp
.cfi_def_cfa_offset 304
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r8, %r15
movl %edx, 68(%rsp) # 4-byte Spill
movl 4(%rcx), %ebp
movq %rcx, 8(%rsp) # 8-byte Spill
movl (%rcx), %edi
imull %ebp, %edi
shll $2, %edi
movq %rdi, 16(%rsp) # 8-byte Spill
callq malloc
movq %rax, %rbx
movl (%r15), %r14d
movq %r15, 128(%rsp) # 8-byte Spill
movl 4(%r15), %r12d
imull %r14d, %r12d
shll $2, %r12d
movq %r12, %rdi
callq malloc
movq %rax, %r15
imull %ebp, %r14d
leal (,%r14,4), %ebp
movq %rbp, %rdi
callq malloc
movq %rax, 24(%rsp) # 8-byte Spill
movq %rbp, %rdi
callq malloc
movq %rax, %r13
movl %r14d, %eax
movq %r14, 168(%rsp) # 8-byte Spill
testl %r14d, %r14d
movq %rax, 144(%rsp) # 8-byte Spill
jle .LBB1_2
# %bb.1: # %.lr.ph.preheader
leaq (,%rax,4), %rdx
movq %r13, %rdi
xorl %esi, %esi
callq memset@PLT
.LBB1_2: # %._crit_edge
cmpq $0, 24(%rsp) # 8-byte Folded Reload
je .LBB1_21
# %bb.3:
leaq 136(%rsp), %rdi
callq hipEventCreate
leaq 48(%rsp), %rdi
callq hipEventCreate
movq 136(%rsp), %rdi
xorl %esi, %esi
callq hipEventRecord
leaq 40(%rsp), %rdi
movq 16(%rsp), %rsi # 8-byte Reload
callq hipMalloc
leaq 32(%rsp), %rdi
movq %r12, %rsi
callq hipMalloc
leaq 56(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movq 40(%rsp), %r14
movq 8(%rsp), %rcx # 8-byte Reload
movslq (%rcx), %rax
movslq 4(%rcx), %r12
imulq %rax, %r12
leaq 80(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
movq %rbp, 160(%rsp) # 8-byte Spill
movq 80(%rsp), %rbp
callq clock
movq %rbp, %rdi
movq %rax, %rsi
callq hiprandSetPseudoRandomGeneratorSeed
movq 80(%rsp), %rdi
movq %r14, %rsi
movq %r12, %rdx
callq hiprandGenerateUniform
movq 32(%rsp), %rax
movq %rax, 152(%rsp) # 8-byte Spill
movq 128(%rsp), %r14 # 8-byte Reload
movslq (%r14), %rax
movslq 4(%r14), %rbp
imulq %rax, %rbp
leaq 80(%rsp), %rdi
movl $400, %esi # imm = 0x190
callq hiprandCreateGenerator
movq 80(%rsp), %r12
callq clock
movq %r12, %rdi
movq %rax, %rsi
callq hiprandSetPseudoRandomGeneratorSeed
movq 80(%rsp), %rdi
movq 152(%rsp), %rsi # 8-byte Reload
movq %rbp, %rdx
callq hiprandGenerateUniform
movq 40(%rsp), %rsi
movq %rbx, %rdi
movq 16(%rsp), %r12 # 8-byte Reload
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movq 32(%rsp), %rsi
movq %r15, %rdi
movq %r12, %rdx
movl $2, %ecx
callq hipMemcpy
movl 68(%rsp), %ecx # 4-byte Reload
movl %ecx, %eax
movq %rax, %r12
shlq $32, %r12
orq %rax, %r12
movl (%r14), %eax
xorl %edx, %edx
divl %ecx
movl %eax, %ebp
movq 8(%rsp), %rax # 8-byte Reload
movl 4(%rax), %eax
movl %ecx, %r14d
xorl %edx, %edx
divl %ecx
# kill: def $eax killed $eax def $rax
shlq $32, %rax
orq %rax, %rbp
movl $.Lstr, %edi
callq puts@PLT
callq hipDeviceSynchronize
movq %rbp, %rdi
movl $1, %esi
movq %r12, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_5
# %bb.4:
movq 56(%rsp), %rax
movq 40(%rsp), %rcx
movq 32(%rsp), %rdx
movq 8(%rsp), %rsi # 8-byte Reload
movl (%rsi), %esi
movq 128(%rsp), %rdi # 8-byte Reload
movl (%rdi), %edi
movq %rax, 240(%rsp)
movq %rcx, 232(%rsp)
movq %rdx, 224(%rsp)
movl %esi, 76(%rsp)
movl %edi, 72(%rsp)
leaq 240(%rsp), %rax
movq %rax, 80(%rsp)
leaq 232(%rsp), %rax
movq %rax, 88(%rsp)
leaq 224(%rsp), %rax
movq %rax, 96(%rsp)
leaq 76(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 208(%rsp), %rdi
leaq 192(%rsp), %rsi
leaq 184(%rsp), %rdx
leaq 176(%rsp), %rcx
callq __hipPopCallConfiguration
movq 208(%rsp), %rsi
movl 216(%rsp), %edx
movq 192(%rsp), %rcx
movl 200(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, %edi
pushq 176(%rsp)
.cfi_adjust_cfa_offset 8
pushq 192(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_5:
movq 48(%rsp), %rdi
xorl %r12d, %r12d
xorl %esi, %esi
callq hipEventRecord
movq 48(%rsp), %rdi
callq hipEventSynchronize
movl $.Lstr.1, %edi
callq puts@PLT
movl $0, 80(%rsp)
movq 136(%rsp), %rsi
movq 48(%rsp), %rdx
leaq 80(%rsp), %rdi
callq hipEventElapsedTime
movss 80(%rsp), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
imull %r14d, %r14d
movb $1, %bpl
movl $.L.str.3, %edi
movl %r14d, %esi
movb $1, %al
callq printf
movq 56(%rsp), %rsi
movq 24(%rsp), %rdi # 8-byte Reload
movq 160(%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
callq clock
movq %rax, 16(%rsp) # 8-byte Spill
movq 8(%rsp), %rax # 8-byte Reload
movl (%rax), %eax
testq %rax, %rax
je .LBB1_13
# %bb.6: # %.preheader116.lr.ph
movq 8(%rsp), %rcx # 8-byte Reload
movl 4(%rcx), %ecx
xorl %edx, %edx
jmp .LBB1_7
.p2align 4, 0x90
.LBB1_12: # %._crit_edge120
# in Loop: Header=BB1_7 Depth=1
incl %edx
addl %eax, %r12d
cmpl %eax, %edx
je .LBB1_13
.LBB1_7: # %.preheader116
# =>This Loop Header: Depth=1
# Child Loop BB1_9 Depth 2
# Child Loop BB1_10 Depth 3
testq %rcx, %rcx
je .LBB1_12
# %bb.8: # %.preheader.lr.ph
# in Loop: Header=BB1_7 Depth=1
movl %eax, %esi
imull %edx, %esi
xorl %edi, %edi
.p2align 4, 0x90
.LBB1_9: # %.preheader
# Parent Loop BB1_7 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_10 Depth 3
leal (%rsi,%rdi), %r8d
movss (%r13,%r8,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rax, %r9
movl %r12d, %r10d
movl %edi, %r11d
.p2align 4, 0x90
.LBB1_10: # Parent Loop BB1_7 Depth=1
# Parent Loop BB1_9 Depth=2
# => This Inner Loop Header: Depth=3
movl %r10d, %r14d
movss (%rbx,%r14,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
movl %r11d, %r14d
mulss (%r15,%r14,4), %xmm1
addss %xmm1, %xmm0
addl %eax, %r11d
incl %r10d
decq %r9
jne .LBB1_10
# %bb.11: # in Loop: Header=BB1_9 Depth=2
movss %xmm0, (%r13,%r8,4)
incq %rdi
cmpq %rcx, %rdi
jne .LBB1_9
jmp .LBB1_12
.LBB1_13: # %._crit_edge122
callq clock
subl 16(%rsp), %eax # 4-byte Folded Reload
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
movl $.L.str.4, %edi
movb $1, %al
callq printf
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
cmpl $0, 168(%rsp) # 4-byte Folded Reload
jle .LBB1_20
# %bb.14: # %.lr.ph126.preheader
movq 144(%rsp), %rcx # 8-byte Reload
decq %rcx
movb $1, %bpl
xorl %r12d, %r12d
movaps .LCPI1_0(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movaps .LCPI1_1(%rip), %xmm4 # xmm4 = [NaN,NaN]
movsd .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero
movq 8(%rsp), %r14 # 8-byte Reload
.p2align 4, 0x90
.LBB1_15: # %.lr.ph126
# =>This Inner Loop Header: Depth=1
movq 24(%rsp), %rax # 8-byte Reload
movss (%rax,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movaps %xmm0, %xmm1
subss (%r13,%r12,4), %xmm1
cvtss2sd %xmm0, %xmm0
andps %xmm3, %xmm1
xorps %xmm6, %xmm6
cvtss2sd %xmm1, %xmm6
movl (%r14), %eax
xorps %xmm1, %xmm1
cvtsi2sd %rax, %xmm1
movaps %xmm0, %xmm5
andps %xmm4, %xmm5
divsd %xmm5, %xmm6
divsd %xmm1, %xmm6
ucomisd %xmm2, %xmm6
jbe .LBB1_17
# %bb.16: # in Loop: Header=BB1_15 Depth=1
movl %eax, %eax
xorps %xmm1, %xmm1
cvtsi2ss %rax, %xmm1
mulss .LCPI1_3(%rip), %xmm1
cvtss2sd %xmm1, %xmm1
movl $.L.str.6, %edi
movl %r12d, %esi
movb $3, %al
movq %rcx, %rbp
movsd %xmm6, 16(%rsp) # 8-byte Spill
callq printf
movsd 16(%rsp), %xmm6 # 8-byte Reload
# xmm6 = mem[0],zero
movsd .LCPI1_2(%rip), %xmm2 # xmm2 = mem[0],zero
movaps .LCPI1_1(%rip), %xmm4 # xmm4 = [NaN,NaN]
movaps .LCPI1_0(%rip), %xmm3 # xmm3 = [NaN,NaN,NaN,NaN]
movq %rbp, %rcx
xorl %ebp, %ebp
.LBB1_17: # in Loop: Header=BB1_15 Depth=1
ucomisd %xmm2, %xmm6
ja .LBB1_19
# %bb.18: # in Loop: Header=BB1_15 Depth=1
leaq 1(%r12), %rax
cmpq %r12, %rcx
movq %rax, %r12
jne .LBB1_15
.LBB1_19: # %._crit_edge127.loopexit
andb $1, %bpl
.LBB1_20: # %._crit_edge127
testb %bpl, %bpl
movl $.L.str.9, %eax
movl $.L.str.8, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi # 8-byte Reload
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 56(%rsp), %rdi
callq hipFree
xorb $1, %bpl
movzbl %bpl, %eax
addq $248, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_21:
.cfi_def_cfa_offset 304
movq stderr(%rip), %rcx
movl $.L.str, %edi
movl $34, %esi
movl $1, %edx
callq fwrite@PLT
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z14MatrixMultiplyiPPciRK4dim3S3_, .Lfunc_end1-_Z14MatrixMultiplyiPPciRK4dim3S3_
.cfi_endproc
# -- End function
.section .text._Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii,"axG",@progbits,_Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii,comdat
.weak _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii # -- Begin function _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii
.p2align 4, 0x90
.type _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii,@function
_Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii: # @_Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
movl %r8d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
movq %rsp, %rax
movq %rax, 112(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii, .Lfunc_end2-_Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii
.cfi_endproc
# -- End function
.text
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movl $.Lstr.2, %edi
callq puts@PLT
movabsq $1374389535040, %rax # imm = 0x14000000140
movq %rax, 12(%rsp)
movl $1, 20(%rsp)
movq %rax, (%rsp)
movl $1, 8(%rsp)
movl $.L.str.11, %edi
movl $320, %esi # imm = 0x140
movl $320, %edx # imm = 0x140
movl $320, %ecx # imm = 0x140
movl $320, %r8d # imm = 0x140
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rcx
movq %rsp, %r8
movl $32, %edx
callq _Z14MatrixMultiplyiPPciRK4dim3S3_
movl %eax, %edi
callq exit
.Lfunc_end3:
.size main, .Lfunc_end3-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB4_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB4_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end4:
.size __hip_module_ctor, .Lfunc_end4-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB5_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB5_2:
retq
.Lfunc_end5:
.size __hip_module_dtor, .Lfunc_end5-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Failed to allocate host matrix C!\n"
.size .L.str, 35
.type _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,@object # @_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.section .rodata._Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,"aG",@progbits,_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii,comdat
.weak _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.p2align 3, 0x0
_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii:
.quad _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii
.size _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii, 8
.type .L.str.3,@object # @.str.3
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.3:
.asciz "Time spent executing by the GPU = %.3f msec, WorkgroupSize= %u threads/block\n"
.size .L.str.3, 78
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Time spent executing by the CPU: %.3f msec\n"
.size .L.str.4, 44
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Checking computed result for correctness: "
.size .L.str.5, 43
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Error! Matrix[%05d]=%.8f, ref=%.8f error term is > %E\n"
.size .L.str.6, 55
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Result = PASS"
.size .L.str.8, 14
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Result = FAIL"
.size .L.str.9, 14
.type .L.str.11,@object # @.str.11
.L.str.11:
.asciz "MatrixA(%d,%d), MatrixB(%d,%d)\n"
.size .L.str.11, 32
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13MatrixMulCUDAILi32EEvPfS0_S0_ii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "Computing result using CUDA Kernel..."
.size .Lstr, 38
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "done"
.size .Lstr.1, 5
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "[Matrix Multiply Using CUDA] - Starting..."
.size .Lstr.2, 43
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__MatrixMulCUDAILi32EEvPfS0_S0_ii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13MatrixMulCUDAILi32EEvPfS0_S0_ii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void mul(float *d_A, float *d_B, float *d_C, int n);
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n);
int main()
{
int n;
int i, j;
float **h_Mat1, **h_Mat2, **h_Mat3;
printf("Enter the dimension of square matrix, n for n X n: ");
scanf("%d", &n);
h_Mat1 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat1[i] = (float *) malloc(n * sizeof(float));
}
h_Mat2 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat2[i] = (float *) malloc(n * sizeof(float));
}
h_Mat3 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat3[i] = (float *) malloc(n * sizeof(float));
}
srand(time(0));
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat1[i][j] = rand() % 1000;
h_Mat2[i][j] = rand() % 1000;
}
}
matMul(h_Mat1, h_Mat2, h_Mat3, n);
return 0;
}
__global__
void mul(float *d_A, float *d_B, float *d_C, int n)
{
int i, j, k;
i = blockIdx.y * blockDim.y + threadIdx.y;
j = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n || j >= n)
{
return;
}
d_C[i * n + j] = 0;
for (k = 0; k < n; ++k)
{
d_C[i * n + j] += d_A[i * n + k] * d_B[k * n + j];
}
return;
}
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n)
{
int size = n * n * sizeof(float);
int i, j, k;
float *h_A, *h_B, *h_C;
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
cudaError_t err = cudaSuccess;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_A[i * n + j] = h_Mat1[i][j];
h_B[i * n + j] = h_Mat2[i][j];
}
}
err = cudaMalloc((void **) &d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_B, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_C, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Launching CUDA mul kernel with (%d, %d, %d) blocks and (%d, %d, %d) threads per block.\n", (n + 15) / 16, (n + 15) / 16, 1, 16, 16, 1);
dim3 grid((n + 15) / 16, (n + 15) / 16, 1);
dim3 block(16, 16, 1);
mul<<<block, grid>>>(d_A, d_B, d_C, n);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch mul kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat3[i][j] = 0;
for (k = 0; k < n; ++k)
{
h_Mat3[i][j] += h_Mat1[i][k] * h_Mat2[k][j];
}
if (fabs(h_C[i * n + j] - h_Mat3[i][j]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element (%d, %d)!\n", i, j);
exit(EXIT_FAILURE);
}
h_Mat3[i][j] = h_C[i * n + j];
}
}
printf("TEST PASSED\n");
return;
} | code for sm_80
Function : _Z3mulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R9, R9, c[0x0][0x4], R0 ; /* 0x0000010009097a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x178], P0 ; /* 0x00005e0008007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fe200078e02ff */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f06270 */
/*00f0*/ IADD3 R2, R8, R9, RZ ; /* 0x0000000908027210 */
/* 0x000fcc0007ffe0ff */
/*0100*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0207 */
/*0110*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe40007ffe0ff */
/*0140*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R6, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300067812 */
/* 0x000fe400078ec0ff */
/*0170*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fd20000000f00 */
/*0180*/ @!P0 BRA 0xce0 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R10, -R6, c[0x0][0x178], RZ ; /* 0x00005e00060a7a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*01c0*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD.WIDE R14, R8, R7, c[0x0][0x168] ; /* 0x00005a00080e7625 */
/* 0x000fe200078e0207 */
/*01e0*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f04270 */
/*01f0*/ @!P0 BRA 0xb10 ; /* 0x0000091000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0220*/ @!P1 BRA 0x7d0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0250*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*0270*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fca00078e0204 */
/*0280*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FFMA R19, R12, R16, R13 ; /* 0x000000100c137223 */
/* 0x004fe4000000000d */
/*02a0*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x008fc600078e020e */
/*02b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*02c0*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ FFMA R21, R16, R17, R19 ; /* 0x0000001110157223 */
/* 0x004fc40000000013 */
/*02f0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0300*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ee4000c1e1900 */
/*0330*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*0340*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0350*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*0360*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000e64000c1e1900 */
/*0380*/ FFMA R19, R18, R12, R23 ; /* 0x0000000c12137223 */
/* 0x002fc40000000017 */
/*0390*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*03a0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*03b0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x004fc40000000013 */
/*03e0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*03f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000ee4000c1e1900 */
/*0420*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*0430*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0440*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*0450*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0460*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000e64000c1e1900 */
/*0470*/ FFMA R19, R18, R12, R23 ; /* 0x0000000c12137223 */
/* 0x002fc40000000017 */
/*0480*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0490*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*04a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R16, [R4.64+0x1c] ; /* 0x00001c0404107981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x004fc40000000013 */
/*04d0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*04e0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*04f0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000ee4000c1e1900 */
/*0510*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*0520*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0530*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*0540*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0550*/ LDG.E R12, [R4.64+0x24] ; /* 0x00002404040c7981 */
/* 0x000e64000c1e1900 */
/*0560*/ FFMA R19, R18, R12, R23 ; /* 0x0000000c12137223 */
/* 0x002fc40000000017 */
/*0570*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0580*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0590*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000ea4000c1e1900 */
/*05b0*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x004fc40000000013 */
/*05c0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*05d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ LDG.E R14, [R4.64+0x2c] ; /* 0x00002c04040e7981 */
/* 0x000ee4000c1e1900 */
/*0600*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*0610*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0620*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0630*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ee8000c1e1900 */
/*0640*/ LDG.E R12, [R4.64+0x30] ; /* 0x00003004040c7981 */
/* 0x000ee4000c1e1900 */
/*0650*/ FFMA R25, R18, R12, R23 ; /* 0x0000000c12197223 */
/* 0x008fc40000000017 */
/*0660*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0670*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0007e8000c101904 */
/*0680*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e68000c1e1900 */
/*0690*/ LDG.E R16, [R4.64+0x34] ; /* 0x0000340404107981 */
/* 0x000e64000c1e1900 */
/*06a0*/ FFMA R21, R18, R16, R25 ; /* 0x0000001012157223 */
/* 0x002fc40000000019 */
/*06b0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*06c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*06d0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R14, [R4.64+0x38] ; /* 0x00003804040e7981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*0700*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x004fc40000000015 */
/*0710*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0720*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*0730*/ LDG.E R14, [R4.64+0x3c] ; /* 0x00003c04040e7981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0750*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe20003f24270 */
/*0760*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0770*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fc60007ffe0ff */
/*0780*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0790*/ FFMA R13, R12, R14, R23 ; /* 0x0000000e0c0d7223 */
/* 0x004fe40000000017 */
/*07a0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*07b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e4000c101904 */
/*07c0*/ @P1 BRA 0x240 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07d0*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*07e0*/ @!P1 BRA 0xaf0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07f0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0800*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ea2000c1e1900 */
/*0810*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*0820*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fca00078e0204 */
/*0830*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea4000c1e1900 */
/*0840*/ FFMA R19, R12, R16, R13 ; /* 0x000000100c137223 */
/* 0x004fe4000000000d */
/*0850*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x008fc600078e020e */
/*0860*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0870*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*0880*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea4000c1e1900 */
/*0890*/ FFMA R21, R16, R17, R19 ; /* 0x0000001110157223 */
/* 0x004fc40000000013 */
/*08a0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*08b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*08c0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*08d0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ee4000c1e1900 */
/*08e0*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*08f0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0900*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*0910*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0920*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000e64000c1e1900 */
/*0930*/ FFMA R19, R18, R12, R23 ; /* 0x0000000c12137223 */
/* 0x002fc40000000017 */
/*0940*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0950*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0960*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000ea4000c1e1900 */
/*0980*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x004fc40000000013 */
/*0990*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*09a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*09b0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*09c0*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000ee4000c1e1900 */
/*09d0*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*09e0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*09f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0a00*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000ee4000c1e1900 */
/*0a20*/ FFMA R25, R18, R12, R23 ; /* 0x0000000c12197223 */
/* 0x008fc40000000017 */
/*0a30*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x002fc600078e020e */
/*0a40*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0a50*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000ee8000c1e1900 */
/*0a60*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee2000c1e1900 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a90*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0212 */
/*0aa0*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fc40007ffe0ff */
/*0ab0*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R13, R12, R13, R25 ; /* 0x0000000d0c0d7223 */
/* 0x008fca0000000019 */
/*0ae0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0af0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0b00*/ @!P0 BRA 0xce0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0b10*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0b20*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000f22000c1e1900 */
/*0b30*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*0b40*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fca00078e0204 */
/*0b50*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000f24000c1e1900 */
/*0b60*/ FFMA R21, R12, R16, R13 ; /* 0x000000100c157223 */
/* 0x01cfe4000000000d */
/*0b70*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0b80*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0b90*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea4000c1e1900 */
/*0bb0*/ FFMA R23, R16, R17, R21 ; /* 0x0000001110177223 */
/* 0x004fc40000000015 */
/*0bc0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0bd0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0be0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0bf0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea2000c1e1900 */
/*0c00*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0c10*/ FFMA R25, R18, R14, R23 ; /* 0x0000000e12197223 */
/* 0x004fc40000000017 */
/*0c20*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0c30*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0c40*/ LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040e7981 */
/* 0x000ea8000c1e1900 */
/*0c50*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0c70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c80*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc60007ffe0ff */
/*0c90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ca0*/ FFMA R13, R12, R14, R25 ; /* 0x0000000e0c0d7223 */
/* 0x004fe40000000019 */
/*0cb0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0cc0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e4000c101904 */
/*0cd0*/ @P0 BRA 0xb10 ; /* 0xfffffe3000000947 */
/* 0x003fea000383ffff */
/*0ce0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0cf0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d00*/ IADD3 R4, R9, R11, RZ ; /* 0x0000000b09047210 */
/* 0x000fe20007ffe0ff */
/*0d10*/ IMAD R8, R11, c[0x0][0x178], R8 ; /* 0x00005e000b087a24 */
/* 0x000fc800078e0208 */
/*0d20*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*0d30*/ IMAD.WIDE R8, R8, R7, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0207 */
/*0d40*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x000fc80000000f00 */
/*0d50*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x000fe20000000f00 */
/*0d60*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x00232a000c1e1900 */
/*0d70*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000b22000c1e1900 */
/*0d80*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0d90*/ IADD3 R7, P1, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc40007f3e0ff */
/*0da0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0db0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fe200078e0208 */
/*0dc0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x020fc60000ffe4ff */
/*0dd0*/ FFMA R13, R10, R4, R13 ; /* 0x000000040a0d7223 */
/* 0x01cfca000000000d */
/*0de0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e6000c101904 */
/*0df0*/ @P0 BRA 0xd50 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0e00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e10*/ BRA 0xe10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void mul(float *d_A, float *d_B, float *d_C, int n);
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n);
int main()
{
int n;
int i, j;
float **h_Mat1, **h_Mat2, **h_Mat3;
printf("Enter the dimension of square matrix, n for n X n: ");
scanf("%d", &n);
h_Mat1 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat1[i] = (float *) malloc(n * sizeof(float));
}
h_Mat2 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat2[i] = (float *) malloc(n * sizeof(float));
}
h_Mat3 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat3[i] = (float *) malloc(n * sizeof(float));
}
srand(time(0));
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat1[i][j] = rand() % 1000;
h_Mat2[i][j] = rand() % 1000;
}
}
matMul(h_Mat1, h_Mat2, h_Mat3, n);
return 0;
}
__global__
void mul(float *d_A, float *d_B, float *d_C, int n)
{
int i, j, k;
i = blockIdx.y * blockDim.y + threadIdx.y;
j = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n || j >= n)
{
return;
}
d_C[i * n + j] = 0;
for (k = 0; k < n; ++k)
{
d_C[i * n + j] += d_A[i * n + k] * d_B[k * n + j];
}
return;
}
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n)
{
int size = n * n * sizeof(float);
int i, j, k;
float *h_A, *h_B, *h_C;
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
cudaError_t err = cudaSuccess;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_A[i * n + j] = h_Mat1[i][j];
h_B[i * n + j] = h_Mat2[i][j];
}
}
err = cudaMalloc((void **) &d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_B, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_C, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Launching CUDA mul kernel with (%d, %d, %d) blocks and (%d, %d, %d) threads per block.\n", (n + 15) / 16, (n + 15) / 16, 1, 16, 16, 1);
dim3 grid((n + 15) / 16, (n + 15) / 16, 1);
dim3 block(16, 16, 1);
mul<<<block, grid>>>(d_A, d_B, d_C, n);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch mul kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat3[i][j] = 0;
for (k = 0; k < n; ++k)
{
h_Mat3[i][j] += h_Mat1[i][k] * h_Mat2[k][j];
}
if (fabs(h_C[i * n + j] - h_Mat3[i][j]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element (%d, %d)!\n", i, j);
exit(EXIT_FAILURE);
}
h_Mat3[i][j] = h_C[i * n + j];
}
}
printf("TEST PASSED\n");
return;
} | .file "tmpxft_001899f8_00000000-6_2_matrix_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3mulPfS_S_iPfS_S_i
.type _Z27__device_stub__Z3mulPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3mulPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z3mulPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3mulPfS_S_iPfS_S_i
.globl _Z3mulPfS_S_i
.type _Z3mulPfS_S_i, @function
_Z3mulPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3mulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3mulPfS_S_i, .-_Z3mulPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocate device vector A (error code %s)!\n"
.align 8
.LC1:
.string "Failed to allocate device vector B (error code %s)!\n"
.align 8
.LC2:
.string "Failed to allocate device vector C (error code %s)!\n"
.align 8
.LC3:
.string "Failed to copy vector A from host to device (error code %s)!\n"
.align 8
.LC4:
.string "Failed to copy vector B from host to device (error code %s)!\n"
.align 8
.LC5:
.string "Launching CUDA mul kernel with (%d, %d, %d) blocks and (%d, %d, %d) threads per block.\n"
.align 8
.LC6:
.string "Failed to launch mul kernel (error code %s)!\n"
.align 8
.LC7:
.string "Failed to copy vector C from device to host (error code %s)!\n"
.align 8
.LC11:
.string "Result verification failed at element (%d, %d)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC12:
.string "TEST PASSED\n"
.text
.globl _Z6matMulPPfS0_S0_i
.type _Z6matMulPPfS0_S0_i, @function
_Z6matMulPPfS0_S0_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, 8(%rsp)
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movl %ecx, %r13d
imull %ecx, %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
testl %r12d, %r12d
jle .L12
movslq %r12d, %r10
leaq 0(,%r10,4), %rsi
movq (%rsp), %rcx
movq %r14, %rdx
salq $3, %r10
movl $0, %r9d
movq %rax, %r11
.L13:
movq (%rbx,%r9), %r8
movq 0(%rbp,%r9), %rdi
movl $0, %eax
.L14:
movss (%r8,%rax), %xmm0
movss %xmm0, (%rcx,%rax)
movss (%rdi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L14
addq %rsi, %rcx
addq %rsi, %rdx
addq $8, %r9
cmpq %r10, %r9
jne .L13
movq %r11, %r15
.L12:
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L37
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L38
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L39
movl $1, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L40
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L41
leal 30(%r12), %r14d
movl %r12d, %eax
addl $15, %eax
cmovns %eax, %r14d
sarl $4, %r14d
pushq $1
.cfi_def_cfa_offset 152
pushq $16
.cfi_def_cfa_offset 160
movl $16, %r9d
movl $1, %r8d
movl %r14d, %ecx
movl %r14d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, 64(%rsp)
movl %r14d, 68(%rsp)
movl $1, 72(%rsp)
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 144
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L20:
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L43
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L44
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %r12d, %r12d
jle .L23
movslq %r12d, %r10
leaq 0(,%r10,4), %rdi
movq %r15, %r11
movq 8(%rsp), %r9
movl $0, %r13d
movss .LC9(%rip), %xmm3
movsd .LC10(%rip), %xmm2
jmp .L24
.L37:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z27__device_stub__Z3mulPfS_S_iPfS_S_i
jmp .L20
.L43:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movss (%r11,%r8,4), %xmm1
addq (%rsi), %rcx
movaps %xmm1, %xmm0
subss (%rcx), %xmm0
andps %xmm3, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm2, %xmm0
ja .L45
movss %xmm1, (%rcx)
addq $1, %r8
cmpq %r10, %r8
je .L46
.L28:
movq %r9, %rsi
leaq 0(,%r8,4), %rcx
movq (%r9), %rax
movl $0x00000000, (%rax,%r8,4)
movl $0, %eax
.L25:
movq %rcx, %rdx
addq (%rsi), %rdx
movq 0(%rbp,%rax,2), %r14
movq (%rbx), %r15
movss (%r15,%rax), %xmm0
mulss (%r14,%rcx), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq %rdi, %rax
jne .L25
jmp .L47
.L45:
movl %r13d, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
addl $1, %r13d
addq %rdi, %r11
addq $8, %r9
addq $8, %rbx
cmpl %r13d, %r12d
je .L23
.L24:
movl $0, %r8d
jmp .L28
.L23:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z6matMulPPfS0_S0_i, .-_Z6matMulPPfS0_S0_i
.section .rodata.str1.8
.align 8
.LC13:
.string "Enter the dimension of square matrix, n for n X n: "
.section .rodata.str1.1
.LC14:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC13(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 20(%rsp), %rsi
leaq .LC14(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 20(%rsp), %ebx
movslq %ebx, %rbp
leaq 0(,%rbp,8), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L50
salq $2, %rbp
movq %rax, %rbx
leaq (%r12,%rax), %r13
.L51:
movq %rbp, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r13, %rbx
jne .L51
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, %rbx
leaq (%r12,%rax), %r13
.L52:
movq %rbp, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r13, %rbx
jne .L52
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rax, %rbx
addq %rax, %r12
.L53:
movq %rbp, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L53
.L58:
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl 20(%rsp), %ecx
testl %ecx, %ecx
jle .L54
movq %r15, %r12
movq %r14, %rbp
movl $0, %r13d
jmp .L55
.L56:
call rand@PLT
movq (%r12), %rcx
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx,%rbx,4)
call rand@PLT
movq 0(%rbp), %rcx
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx,%rbx,4)
addq $1, %rbx
cmpl %ebx, 20(%rsp)
jg .L56
.L57:
addl $1, %r13d
movl 20(%rsp), %ecx
addq $8, %r12
addq $8, %rbp
cmpl %r13d, %ecx
jle .L54
.L55:
movl $0, %ebx
cmpl $0, 20(%rsp)
jg .L56
jmp .L57
.L54:
movq 8(%rsp), %rdx
movq %r14, %rsi
movq %r15, %rdi
call _Z6matMulPPfS0_S0_i
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L68
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
jmp .L58
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z3mulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <cuda.h>
#include <cuda_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void mul(float *d_A, float *d_B, float *d_C, int n);
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n);
int main()
{
int n;
int i, j;
float **h_Mat1, **h_Mat2, **h_Mat3;
printf("Enter the dimension of square matrix, n for n X n: ");
scanf("%d", &n);
h_Mat1 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat1[i] = (float *) malloc(n * sizeof(float));
}
h_Mat2 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat2[i] = (float *) malloc(n * sizeof(float));
}
h_Mat3 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat3[i] = (float *) malloc(n * sizeof(float));
}
srand(time(0));
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat1[i][j] = rand() % 1000;
h_Mat2[i][j] = rand() % 1000;
}
}
matMul(h_Mat1, h_Mat2, h_Mat3, n);
return 0;
}
__global__
void mul(float *d_A, float *d_B, float *d_C, int n)
{
int i, j, k;
i = blockIdx.y * blockDim.y + threadIdx.y;
j = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n || j >= n)
{
return;
}
d_C[i * n + j] = 0;
for (k = 0; k < n; ++k)
{
d_C[i * n + j] += d_A[i * n + k] * d_B[k * n + j];
}
return;
}
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n)
{
int size = n * n * sizeof(float);
int i, j, k;
float *h_A, *h_B, *h_C;
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
cudaError_t err = cudaSuccess;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_A[i * n + j] = h_Mat1[i][j];
h_B[i * n + j] = h_Mat2[i][j];
}
}
err = cudaMalloc((void **) &d_A, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_B, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMalloc((void **) &d_C, size);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Launching CUDA mul kernel with (%d, %d, %d) blocks and (%d, %d, %d) threads per block.\n", (n + 15) / 16, (n + 15) / 16, 1, 16, 16, 1);
dim3 grid((n + 15) / 16, (n + 15) / 16, 1);
dim3 block(16, 16, 1);
mul<<<block, grid>>>(d_A, d_B, d_C, n);
err = cudaGetLastError();
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to launch mul kernel (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
err = cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
if (err != cudaSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", cudaGetErrorString(err));
exit(EXIT_FAILURE);
}
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat3[i][j] = 0;
for (k = 0; k < n; ++k)
{
h_Mat3[i][j] += h_Mat1[i][k] * h_Mat2[k][j];
}
if (fabs(h_C[i * n + j] - h_Mat3[i][j]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element (%d, %d)!\n", i, j);
exit(EXIT_FAILURE);
}
h_Mat3[i][j] = h_C[i * n + j];
}
}
printf("TEST PASSED\n");
return;
} | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void mul(float *d_A, float *d_B, float *d_C, int n);
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n);
int main()
{
int n;
int i, j;
float **h_Mat1, **h_Mat2, **h_Mat3;
printf("Enter the dimension of square matrix, n for n X n: ");
scanf("%d", &n);
h_Mat1 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat1[i] = (float *) malloc(n * sizeof(float));
}
h_Mat2 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat2[i] = (float *) malloc(n * sizeof(float));
}
h_Mat3 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat3[i] = (float *) malloc(n * sizeof(float));
}
srand(time(0));
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat1[i][j] = rand() % 1000;
h_Mat2[i][j] = rand() % 1000;
}
}
matMul(h_Mat1, h_Mat2, h_Mat3, n);
return 0;
}
__global__
void mul(float *d_A, float *d_B, float *d_C, int n)
{
int i, j, k;
i = blockIdx.y * blockDim.y + threadIdx.y;
j = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n || j >= n)
{
return;
}
d_C[i * n + j] = 0;
for (k = 0; k < n; ++k)
{
d_C[i * n + j] += d_A[i * n + k] * d_B[k * n + j];
}
return;
}
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n)
{
int size = n * n * sizeof(float);
int i, j, k;
float *h_A, *h_B, *h_C;
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
hipError_t err = hipSuccess;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_A[i * n + j] = h_Mat1[i][j];
h_B[i * n + j] = h_Mat2[i][j];
}
}
err = hipMalloc((void **) &d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_B, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_C, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Launching CUDA mul kernel with (%d, %d, %d) blocks and (%d, %d, %d) threads per block.\n", (n + 15) / 16, (n + 15) / 16, 1, 16, 16, 1);
dim3 grid((n + 15) / 16, (n + 15) / 16, 1);
dim3 block(16, 16, 1);
mul<<<block, grid>>>(d_A, d_B, d_C, n);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch mul kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat3[i][j] = 0;
for (k = 0; k < n; ++k)
{
h_Mat3[i][j] += h_Mat1[i][k] * h_Mat2[k][j];
}
if (fabs(h_C[i * n + j] - h_Mat3[i][j]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element (%d, %d)!\n", i, j);
exit(EXIT_FAILURE);
}
h_Mat3[i][j] = h_C[i * n + j];
}
}
printf("TEST PASSED\n");
return;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void mul(float *d_A, float *d_B, float *d_C, int n);
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n);
int main()
{
int n;
int i, j;
float **h_Mat1, **h_Mat2, **h_Mat3;
printf("Enter the dimension of square matrix, n for n X n: ");
scanf("%d", &n);
h_Mat1 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat1[i] = (float *) malloc(n * sizeof(float));
}
h_Mat2 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat2[i] = (float *) malloc(n * sizeof(float));
}
h_Mat3 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat3[i] = (float *) malloc(n * sizeof(float));
}
srand(time(0));
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat1[i][j] = rand() % 1000;
h_Mat2[i][j] = rand() % 1000;
}
}
matMul(h_Mat1, h_Mat2, h_Mat3, n);
return 0;
}
__global__
void mul(float *d_A, float *d_B, float *d_C, int n)
{
int i, j, k;
i = blockIdx.y * blockDim.y + threadIdx.y;
j = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n || j >= n)
{
return;
}
d_C[i * n + j] = 0;
for (k = 0; k < n; ++k)
{
d_C[i * n + j] += d_A[i * n + k] * d_B[k * n + j];
}
return;
}
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n)
{
int size = n * n * sizeof(float);
int i, j, k;
float *h_A, *h_B, *h_C;
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
hipError_t err = hipSuccess;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_A[i * n + j] = h_Mat1[i][j];
h_B[i * n + j] = h_Mat2[i][j];
}
}
err = hipMalloc((void **) &d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_B, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_C, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Launching CUDA mul kernel with (%d, %d, %d) blocks and (%d, %d, %d) threads per block.\n", (n + 15) / 16, (n + 15) / 16, 1, 16, 16, 1);
dim3 grid((n + 15) / 16, (n + 15) / 16, 1);
dim3 block(16, 16, 1);
mul<<<block, grid>>>(d_A, d_B, d_C, n);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch mul kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat3[i][j] = 0;
for (k = 0; k < n; ++k)
{
h_Mat3[i][j] += h_Mat1[i][k] * h_Mat2[k][j];
}
if (fabs(h_C[i * n + j] - h_Mat3[i][j]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element (%d, %d)!\n", i, j);
exit(EXIT_FAILURE);
}
h_Mat3[i][j] = h_C[i * n + j];
}
}
printf("TEST PASSED\n");
return;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulPfS_S_i
.globl _Z3mulPfS_S_i
.p2align 8
.type _Z3mulPfS_S_i,@function
_Z3mulPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_4
v_mul_lo_u32 v4, v2, s4
s_load_b64 s[2:3], s[0:1], 0x10
s_cmp_lt_i32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v4, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_cbranch_scc1 .LBB0_4
global_load_b32 v6, v[2:3], off
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s0, s4
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v1, v7
global_store_b32 v[2:3], v6, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulPfS_S_i, .Lfunc_end0-_Z3mulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
__global__
void mul(float *d_A, float *d_B, float *d_C, int n);
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n);
int main()
{
int n;
int i, j;
float **h_Mat1, **h_Mat2, **h_Mat3;
printf("Enter the dimension of square matrix, n for n X n: ");
scanf("%d", &n);
h_Mat1 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat1[i] = (float *) malloc(n * sizeof(float));
}
h_Mat2 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat2[i] = (float *) malloc(n * sizeof(float));
}
h_Mat3 = (float **) malloc(n * sizeof(float *));
for (i = 0; i < n; ++i)
{
h_Mat3[i] = (float *) malloc(n * sizeof(float));
}
srand(time(0));
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat1[i][j] = rand() % 1000;
h_Mat2[i][j] = rand() % 1000;
}
}
matMul(h_Mat1, h_Mat2, h_Mat3, n);
return 0;
}
__global__
void mul(float *d_A, float *d_B, float *d_C, int n)
{
int i, j, k;
i = blockIdx.y * blockDim.y + threadIdx.y;
j = blockIdx.x * blockDim.x + threadIdx.x;
if (i >= n || j >= n)
{
return;
}
d_C[i * n + j] = 0;
for (k = 0; k < n; ++k)
{
d_C[i * n + j] += d_A[i * n + k] * d_B[k * n + j];
}
return;
}
void matMul(float **h_Mat1, float **h_Mat2, float **h_Mat3, int n)
{
int size = n * n * sizeof(float);
int i, j, k;
float *h_A, *h_B, *h_C;
float *d_A = NULL, *d_B = NULL, *d_C = NULL;
hipError_t err = hipSuccess;
h_A = (float *) malloc(size);
h_B = (float *) malloc(size);
h_C = (float *) malloc(size);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_A[i * n + j] = h_Mat1[i][j];
h_B[i * n + j] = h_Mat2[i][j];
}
}
err = hipMalloc((void **) &d_A, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector A (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_B, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector B (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMalloc((void **) &d_C, size);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to allocate device vector C (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector A from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector B from host to device (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
printf("Launching CUDA mul kernel with (%d, %d, %d) blocks and (%d, %d, %d) threads per block.\n", (n + 15) / 16, (n + 15) / 16, 1, 16, 16, 1);
dim3 grid((n + 15) / 16, (n + 15) / 16, 1);
dim3 block(16, 16, 1);
mul<<<block, grid>>>(d_A, d_B, d_C, n);
err = hipGetLastError();
if (err != hipSuccess)
{
fprintf(stderr, "Failed to launch mul kernel (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
err = hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
if (err != hipSuccess)
{
fprintf(stderr, "Failed to copy vector C from device to host (error code %s)!\n", hipGetErrorString(err));
exit(EXIT_FAILURE);
}
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
for (i = 0; i < n; ++i)
{
for (j = 0; j < n; ++j)
{
h_Mat3[i][j] = 0;
for (k = 0; k < n; ++k)
{
h_Mat3[i][j] += h_Mat1[i][k] * h_Mat2[k][j];
}
if (fabs(h_C[i * n + j] - h_Mat3[i][j]) > 1e-5)
{
fprintf(stderr, "Result verification failed at element (%d, %d)!\n", i, j);
exit(EXIT_FAILURE);
}
h_Mat3[i][j] = h_C[i * n + j];
}
}
printf("TEST PASSED\n");
return;
} | .text
.file "2_matrix_multiplication.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %r13
leaq (,%r13,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movl %r13d, %ebp
testq %r13, %r13
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq (,%r13,4), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq malloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %rbp
jne .LBB0_2
.LBB0_3: # %._crit_edge
movq %r15, 16(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r14
testl %r13d, %r13d
jle .LBB0_6
# %bb.4: # %.lr.ph34
leaq (,%r13,4), %r12
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
callq malloc
movq %rax, (%r14,%r15,8)
incq %r15
cmpq %r15, %rbp
jne .LBB0_5
.LBB0_6: # %._crit_edge35
movq 16(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r15
testl %ebp, %ebp
jle .LBB0_9
# %bb.7: # %.lr.ph38
leaq (,%r13,4), %r12
movl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_8: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
callq malloc
movq %rax, (%r15,%rbp,8)
incq %rbp
cmpq %rbp, %r13
jne .LBB0_8
.LBB0_9: # %._crit_edge39
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl 12(%rsp), %ecx
testl %ecx, %ecx
jle .LBB0_15
# %bb.10: # %.preheader.preheader
xorl %r12d, %r12d
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_14: # %._crit_edge42
# in Loop: Header=BB0_11 Depth=1
incq %r12
movslq 12(%rsp), %rcx
cmpq %rcx, %r12
jge .LBB0_15
.LBB0_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_13 Depth 2
cmpl $0, 12(%rsp)
jle .LBB0_14
# %bb.12: # %.lr.ph41
# in Loop: Header=BB0_11 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_13: # Parent Loop BB0_11 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%rbx,%r12,8), %rax
movss %xmm0, (%rax,%r13,4)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%r14,%r12,8), %rax
movss %xmm0, (%rax,%r13,4)
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB0_13
jmp .LBB0_14
.LBB0_15: # %._crit_edge44
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
# kill: def $ecx killed $ecx killed $rcx
callq _Z6matMulPPfS0_S0_i
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z6matMulPPfS0_S0_i
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl _Z6matMulPPfS0_S0_i
.p2align 4, 0x90
.type _Z6matMulPPfS0_S0_i,@function
_Z6matMulPPfS0_S0_i: # @_Z6matMulPPfS0_S0_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, 40(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %r12
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movslq %eax, %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %rbp
movq %r13, (%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
movl %ebx, %r13d
testl %ebx, %ebx
jle .LBB1_5
# %bb.1: # %.preheader115.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.preheader115
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %eax, %esi
leaq (,%rsi,4), %rdx
addq %rbp, %rdx
leaq (%r14,%rsi,4), %rsi
movq (%r12,%rcx,8), %rdi
movq (%r15,%rcx,8), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi,%r9,4)
movss (%r8,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rdx,%r9,4)
incq %r9
cmpq %r9, %r13
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rcx
addl %ebx, %eax
cmpq %r13, %rcx
jne .LBB1_2
.LBB1_5: # %._crit_edge120
leaq 24(%rsp), %rdi
movq (%rsp), %rsi # 8-byte Reload
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.8:
leaq 16(%rsp), %rdi
movq (%rsp), %rsi # 8-byte Reload
callq hipMalloc
testl %eax, %eax
jne .LBB1_9
# %bb.10:
leaq 8(%rsp), %rdi
movq (%rsp), %rsi # 8-byte Reload
callq hipMalloc
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movq 24(%rsp), %rdi
movq %r14, %rsi
movq (%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movq 16(%rsp), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_15
# %bb.16:
leal 15(%rbx), %eax
leal 30(%rbx), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $4, %r14d
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.7, %edi
movl %r14d, %esi
movl %r14d, %edx
movl $1, %ecx
movl $16, %r8d
movl $16, %r9d
xorl %eax, %eax
pushq $1
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movq %r14, %rdx
shlq $32, %rdx
orq %r14, %rdx
movabsq $68719476752, %rdi # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_18
# %bb.17:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %ebx, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3mulPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_18:
callq hipGetLastError
testl %eax, %eax
movq 48(%rsp), %r14 # 8-byte Reload
jne .LBB1_19
# %bb.20:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq (%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_21
# %bb.22:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
testl %ebx, %ebx
movq 40(%rsp), %r10 # 8-byte Reload
jle .LBB1_30
# %bb.23: # %.preheader.lr.ph
xorl %edx, %edx
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_24: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_25 Depth 2
# Child Loop BB1_26 Depth 3
movq (%r10,%rdx,8), %rax
movl %edx, %ecx
imull %ebx, %ecx
movq (%r12,%rdx,8), %rsi
leaq (%r14,%rcx,4), %rdi
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_25: # %.lr.ph123
# Parent Loop BB1_24 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_26 Depth 3
movl $0, (%rax,%rcx,4)
xorps %xmm2, %xmm2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_26: # Parent Loop BB1_24 Depth=1
# Parent Loop BB1_25 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r8,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movq (%r15,%r8,8), %r9
mulss (%r9,%rcx,4), %xmm3
addss %xmm3, %xmm2
movss %xmm2, (%rax,%rcx,4)
incq %r8
cmpq %r8, %r13
jne .LBB1_26
# %bb.27: # %._crit_edge124
# in Loop: Header=BB1_25 Depth=2
movss (%rdi,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm3
subss (%rax,%rcx,4), %xmm3
andps %xmm0, %xmm3
cvtss2sd %xmm3, %xmm3
ucomisd %xmm1, %xmm3
ja .LBB1_31
# %bb.28: # in Loop: Header=BB1_25 Depth=2
movss %xmm2, (%rax,%rcx,4)
incq %rcx
cmpq %r13, %rcx
jne .LBB1_25
# %bb.29: # %._crit_edge127
# in Loop: Header=BB1_24 Depth=1
incq %rdx
cmpq %r13, %rdx
jne .LBB1_24
.LBB1_30: # %._crit_edge129
movl $.Lstr, %edi
callq puts@PLT
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_31:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rdi
movl $.L.str.10, %esi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_7
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB1_7
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_7
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB1_7
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB1_7
.LBB1_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB1_7
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
.LBB1_7:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z6matMulPPfS0_S0_i, .Lfunc_end1-_Z6matMulPPfS0_S0_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__mulPfS_S_i # -- Begin function _Z18__device_stub__mulPfS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__mulPfS_S_i,@function
_Z18__device_stub__mulPfS_S_i: # @_Z18__device_stub__mulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__mulPfS_S_i, .Lfunc_end2-_Z18__device_stub__mulPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the dimension of square matrix, n for n X n: "
.size .L.str, 52
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type _Z3mulPfS_S_i,@object # @_Z3mulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z3mulPfS_S_i
.p2align 3, 0x0
_Z3mulPfS_S_i:
.quad _Z18__device_stub__mulPfS_S_i
.size _Z3mulPfS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Failed to allocate device vector A (error code %s)!\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device vector B (error code %s)!\n"
.size .L.str.3, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate device vector C (error code %s)!\n"
.size .L.str.4, 53
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy vector A from host to device (error code %s)!\n"
.size .L.str.5, 62
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to copy vector B from host to device (error code %s)!\n"
.size .L.str.6, 62
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Launching CUDA mul kernel with (%d, %d, %d) blocks and (%d, %d, %d) threads per block.\n"
.size .L.str.7, 88
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to launch mul kernel (error code %s)!\n"
.size .L.str.8, 46
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to copy vector C from device to host (error code %s)!\n"
.size .L.str.9, 62
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Result verification failed at element (%d, %d)!\n"
.size .L.str.10, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mulPfS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "TEST PASSED"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z3mulPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R9, SR_CTAID.Y ; /* 0x0000000000097919 */
/* 0x000e280000002600 */
/*0020*/ S2R R0, SR_TID.Y ; /* 0x0000000000007919 */
/* 0x000e280000002200 */
/*0030*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e680000002500 */
/*0040*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e620000002100 */
/*0050*/ IMAD R9, R9, c[0x0][0x4], R0 ; /* 0x0000010009097a24 */
/* 0x001fca00078e0200 */
/*0060*/ ISETP.GE.AND P0, PT, R9, c[0x0][0x178], PT ; /* 0x00005e0009007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R8, R8, c[0x0][0x0], R3 ; /* 0x0000000008087a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R8, c[0x0][0x178], P0 ; /* 0x00005e0008007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R0, c[0x0][0x178] ; /* 0x00005e0000007a02 */
/* 0x000fe20000000f00 */
/*00b0*/ IMAD R9, R9, c[0x0][0x178], RZ ; /* 0x00005e0009097a24 */
/* 0x000fe200078e02ff */
/*00c0*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*00d0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00e0*/ ISETP.GE.AND P0, PT, R0, 0x1, PT ; /* 0x000000010000780c */
/* 0x000fe40003f06270 */
/*00f0*/ IADD3 R2, R8, R9, RZ ; /* 0x0000000908027210 */
/* 0x000fcc0007ffe0ff */
/*0100*/ IMAD.WIDE R2, R2, R7, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fca00078e0207 */
/*0110*/ STG.E [R2.64], RZ ; /* 0x000000ff02007986 */
/* 0x0001e2000c101904 */
/*0120*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0130*/ IADD3 R4, R0, -0x1, RZ ; /* 0xffffffff00047810 */
/* 0x000fe40007ffe0ff */
/*0140*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fe40000000f00 */
/*0150*/ ISETP.GE.U32.AND P0, PT, R4, 0x3, PT ; /* 0x000000030400780c */
/* 0x000fe40003f06070 */
/*0160*/ LOP3.LUT R6, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300067812 */
/* 0x000fe400078ec0ff */
/*0170*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fd20000000f00 */
/*0180*/ @!P0 BRA 0xce0 ; /* 0x00000b5000008947 */
/* 0x000fea0003800000 */
/*0190*/ IADD3 R10, -R6, c[0x0][0x178], RZ ; /* 0x00005e00060a7a10 */
/* 0x000fe20007ffe1ff */
/*01a0*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*01b0*/ HFMA2.MMA R11, -RZ, RZ, 0, 0 ; /* 0x00000000ff0b7435 */
/* 0x000fe200000001ff */
/*01c0*/ MOV R13, RZ ; /* 0x000000ff000d7202 */
/* 0x000fe20000000f00 */
/*01d0*/ IMAD.WIDE R14, R8, R7, c[0x0][0x168] ; /* 0x00005a00080e7625 */
/* 0x000fe200078e0207 */
/*01e0*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fda0003f04270 */
/*01f0*/ @!P0 BRA 0xb10 ; /* 0x0000091000008947 */
/* 0x000fea0003800000 */
/*0200*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*0210*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*0220*/ @!P1 BRA 0x7d0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0230*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0240*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0250*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ea2000c1e1900 */
/*0260*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*0270*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fca00078e0204 */
/*0280*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea4000c1e1900 */
/*0290*/ FFMA R19, R12, R16, R13 ; /* 0x000000100c137223 */
/* 0x004fe4000000000d */
/*02a0*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x008fc600078e020e */
/*02b0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*02c0*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*02d0*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea4000c1e1900 */
/*02e0*/ FFMA R21, R16, R17, R19 ; /* 0x0000001110157223 */
/* 0x004fc40000000013 */
/*02f0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0300*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*0310*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*0320*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ee4000c1e1900 */
/*0330*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*0340*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0350*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*0360*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0370*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000e64000c1e1900 */
/*0380*/ FFMA R19, R18, R12, R23 ; /* 0x0000000c12137223 */
/* 0x002fc40000000017 */
/*0390*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*03a0*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*03b0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*03c0*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000ea4000c1e1900 */
/*03d0*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x004fc40000000013 */
/*03e0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*03f0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*0400*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*0410*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000ee4000c1e1900 */
/*0420*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*0430*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0440*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*0450*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0460*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000e64000c1e1900 */
/*0470*/ FFMA R19, R18, R12, R23 ; /* 0x0000000c12137223 */
/* 0x002fc40000000017 */
/*0480*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0490*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*04a0*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*04b0*/ LDG.E R16, [R4.64+0x1c] ; /* 0x00001c0404107981 */
/* 0x000ea4000c1e1900 */
/*04c0*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x004fc40000000013 */
/*04d0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*04e0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*04f0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*0500*/ LDG.E R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000ee4000c1e1900 */
/*0510*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*0520*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0530*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*0540*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0550*/ LDG.E R12, [R4.64+0x24] ; /* 0x00002404040c7981 */
/* 0x000e64000c1e1900 */
/*0560*/ FFMA R19, R18, R12, R23 ; /* 0x0000000c12137223 */
/* 0x002fc40000000017 */
/*0570*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0580*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x000fe8000c101904 */
/*0590*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*05a0*/ LDG.E R16, [R4.64+0x28] ; /* 0x0000280404107981 */
/* 0x000ea4000c1e1900 */
/*05b0*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x004fc40000000013 */
/*05c0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*05d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*05e0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*05f0*/ LDG.E R14, [R4.64+0x2c] ; /* 0x00002c04040e7981 */
/* 0x000ee4000c1e1900 */
/*0600*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*0610*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0620*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0630*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ee8000c1e1900 */
/*0640*/ LDG.E R12, [R4.64+0x30] ; /* 0x00003004040c7981 */
/* 0x000ee4000c1e1900 */
/*0650*/ FFMA R25, R18, R12, R23 ; /* 0x0000000c12197223 */
/* 0x008fc40000000017 */
/*0660*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0670*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0007e8000c101904 */
/*0680*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000e68000c1e1900 */
/*0690*/ LDG.E R16, [R4.64+0x34] ; /* 0x0000340404107981 */
/* 0x000e64000c1e1900 */
/*06a0*/ FFMA R21, R18, R16, R25 ; /* 0x0000001012157223 */
/* 0x002fc40000000019 */
/*06b0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*06c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0007e8000c101904 */
/*06d0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*06e0*/ LDG.E R14, [R4.64+0x38] ; /* 0x00003804040e7981 */
/* 0x000ea2000c1e1900 */
/*06f0*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*0700*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x004fc40000000015 */
/*0710*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0720*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*0730*/ LDG.E R14, [R4.64+0x3c] ; /* 0x00003c04040e7981 */
/* 0x000ea8000c1e1900 */
/*0740*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0750*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe20003f24270 */
/*0760*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0770*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fc60007ffe0ff */
/*0780*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0790*/ FFMA R13, R12, R14, R23 ; /* 0x0000000e0c0d7223 */
/* 0x004fe40000000017 */
/*07a0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*07b0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0007e4000c101904 */
/*07c0*/ @P1 BRA 0x240 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07d0*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*07e0*/ @!P1 BRA 0xaf0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07f0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0800*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000ea2000c1e1900 */
/*0810*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*0820*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fca00078e0204 */
/*0830*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000ea4000c1e1900 */
/*0840*/ FFMA R19, R12, R16, R13 ; /* 0x000000100c137223 */
/* 0x004fe4000000000d */
/*0850*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x008fc600078e020e */
/*0860*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0870*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*0880*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea4000c1e1900 */
/*0890*/ FFMA R21, R16, R17, R19 ; /* 0x0000001110157223 */
/* 0x004fc40000000013 */
/*08a0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*08b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*08c0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*08d0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ee4000c1e1900 */
/*08e0*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*08f0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*0900*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0007e8000c101904 */
/*0910*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000e68000c1e1900 */
/*0920*/ LDG.E R12, [R4.64+0xc] ; /* 0x00000c04040c7981 */
/* 0x000e64000c1e1900 */
/*0930*/ FFMA R19, R18, R12, R23 ; /* 0x0000000c12137223 */
/* 0x002fc40000000017 */
/*0940*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0950*/ STG.E [R2.64], R19 ; /* 0x0000001302007986 */
/* 0x0003e8000c101904 */
/*0960*/ LDG.E R18, [R12.64] ; /* 0x000000040c127981 */
/* 0x000ea8000c1e1900 */
/*0970*/ LDG.E R16, [R4.64+0x10] ; /* 0x0000100404107981 */
/* 0x000ea4000c1e1900 */
/*0980*/ FFMA R21, R18, R16, R19 ; /* 0x0000001012157223 */
/* 0x004fc40000000013 */
/*0990*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*09a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0005e8000c101904 */
/*09b0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ee8000c1e1900 */
/*09c0*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000ee4000c1e1900 */
/*09d0*/ FFMA R23, R18, R14, R21 ; /* 0x0000000e12177223 */
/* 0x008fc40000000015 */
/*09e0*/ IMAD.WIDE R14, R0, 0x4, R16 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0210 */
/*09f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0a00*/ LDG.E R18, [R14.64] ; /* 0x000000040e127981 */
/* 0x000ee8000c1e1900 */
/*0a10*/ LDG.E R12, [R4.64+0x18] ; /* 0x00001804040c7981 */
/* 0x000ee4000c1e1900 */
/*0a20*/ FFMA R25, R18, R12, R23 ; /* 0x0000000c12197223 */
/* 0x008fc40000000017 */
/*0a30*/ IMAD.WIDE R18, R0, 0x4, R14 ; /* 0x0000000400127825 */
/* 0x002fc600078e020e */
/*0a40*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*0a50*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000ee8000c1e1900 */
/*0a60*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ee2000c1e1900 */
/*0a70*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a80*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a90*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fe200078e0212 */
/*0aa0*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fc40007ffe0ff */
/*0ab0*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe20007ffe0ff */
/*0ac0*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ad0*/ FFMA R13, R12, R13, R25 ; /* 0x0000000d0c0d7223 */
/* 0x008fca0000000019 */
/*0ae0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e8000c101904 */
/*0af0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0b00*/ @!P0 BRA 0xce0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0b10*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0b20*/ LDG.E R12, [R14.64] ; /* 0x000000040e0c7981 */
/* 0x000f22000c1e1900 */
/*0b30*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*0b40*/ IMAD.WIDE R4, R9, 0x4, R4 ; /* 0x0000000409047825 */
/* 0x000fca00078e0204 */
/*0b50*/ LDG.E R16, [R4.64] ; /* 0x0000000404107981 */
/* 0x000f24000c1e1900 */
/*0b60*/ FFMA R21, R12, R16, R13 ; /* 0x000000100c157223 */
/* 0x01cfe4000000000d */
/*0b70*/ IMAD.WIDE R12, R0, 0x4, R14 ; /* 0x00000004000c7825 */
/* 0x000fc600078e020e */
/*0b80*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0b90*/ LDG.E R16, [R12.64] ; /* 0x000000040c107981 */
/* 0x000ea8000c1e1900 */
/*0ba0*/ LDG.E R17, [R4.64+0x4] ; /* 0x0000040404117981 */
/* 0x000ea4000c1e1900 */
/*0bb0*/ FFMA R23, R16, R17, R21 ; /* 0x0000001110177223 */
/* 0x004fc40000000015 */
/*0bc0*/ IMAD.WIDE R16, R0, 0x4, R12 ; /* 0x0000000400107825 */
/* 0x000fc600078e020c */
/*0bd0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0be0*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0bf0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea2000c1e1900 */
/*0c00*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0c10*/ FFMA R25, R18, R14, R23 ; /* 0x0000000e12197223 */
/* 0x004fc40000000017 */
/*0c20*/ IMAD.WIDE R18, R0, 0x4, R16 ; /* 0x0000000400127825 */
/* 0x000fc600078e0210 */
/*0c30*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0c40*/ LDG.E R14, [R4.64+0xc] ; /* 0x00000c04040e7981 */
/* 0x000ea8000c1e1900 */
/*0c50*/ LDG.E R12, [R18.64] ; /* 0x00000004120c7981 */
/* 0x000ea2000c1e1900 */
/*0c60*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0c70*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c80*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc60007ffe0ff */
/*0c90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0ca0*/ FFMA R13, R12, R14, R25 ; /* 0x0000000e0c0d7223 */
/* 0x004fe40000000019 */
/*0cb0*/ IMAD.WIDE R14, R0, 0x4, R18 ; /* 0x00000004000e7825 */
/* 0x000fc600078e0212 */
/*0cc0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e4000c101904 */
/*0cd0*/ @P0 BRA 0xb10 ; /* 0xfffffe3000000947 */
/* 0x003fea000383ffff */
/*0ce0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fda0003f05270 */
/*0cf0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0d00*/ IADD3 R4, R9, R11, RZ ; /* 0x0000000b09047210 */
/* 0x000fe20007ffe0ff */
/*0d10*/ IMAD R8, R11, c[0x0][0x178], R8 ; /* 0x00005e000b087a24 */
/* 0x000fc800078e0208 */
/*0d20*/ IMAD.WIDE R4, R4, R7, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fc800078e0207 */
/*0d30*/ IMAD.WIDE R8, R8, R7, c[0x0][0x168] ; /* 0x00005a0008087625 */
/* 0x000fe200078e0207 */
/*0d40*/ MOV R7, R4 ; /* 0x0000000400077202 */
/* 0x000fc80000000f00 */
/*0d50*/ MOV R4, R7 ; /* 0x0000000700047202 */
/* 0x000fe20000000f00 */
/*0d60*/ LDG.E R10, [R8.64] ; /* 0x00000004080a7981 */
/* 0x00232a000c1e1900 */
/*0d70*/ LDG.E R4, [R4.64] ; /* 0x0000000404047981 */
/* 0x000b22000c1e1900 */
/*0d80*/ IADD3 R6, R6, -0x1, RZ ; /* 0xffffffff06067810 */
/* 0x000fe40007ffe0ff */
/*0d90*/ IADD3 R7, P1, R7, 0x4, RZ ; /* 0x0000000407077810 */
/* 0x000fc40007f3e0ff */
/*0da0*/ ISETP.NE.AND P0, PT, R6, RZ, PT ; /* 0x000000ff0600720c */
/* 0x000fe20003f05270 */
/*0db0*/ IMAD.WIDE R8, R0, 0x4, R8 ; /* 0x0000000400087825 */
/* 0x002fe200078e0208 */
/*0dc0*/ IADD3.X R5, RZ, R5, RZ, P1, !PT ; /* 0x00000005ff057210 */
/* 0x020fc60000ffe4ff */
/*0dd0*/ FFMA R13, R10, R4, R13 ; /* 0x000000040a0d7223 */
/* 0x01cfca000000000d */
/*0de0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e6000c101904 */
/*0df0*/ @P0 BRA 0xd50 ; /* 0xffffff5000000947 */
/* 0x000fea000383ffff */
/*0e00*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0e10*/ BRA 0xe10; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e80*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e90*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ea0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0eb0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ec0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ed0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ee0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0ef0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z3mulPfS_S_i
.globl _Z3mulPfS_S_i
.p2align 8
.type _Z3mulPfS_S_i,@function
_Z3mulPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v4, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
v_mad_u64_u32 v[2:3], null, s15, s3, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[4:5]
s_mov_b32 s2, exec_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_max_i32_e32 v1, v2, v0
v_cmpx_gt_i32_e64 s4, v1
s_cbranch_execz .LBB0_4
v_mul_lo_u32 v4, v2, s4
s_load_b64 s[2:3], s[0:1], 0x10
s_cmp_lt_i32 s4, 1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_add_nc_u32_e32 v1, v4, v0
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_mov_b32_e32 v1, 0
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s2, v2
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
global_store_b32 v[2:3], v1, off
s_cbranch_scc1 .LBB0_4
global_load_b32 v6, v[2:3], off
s_load_b128 s[0:3], s[0:1], 0x0
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v4, vcc_lo, s0, v4
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
s_mov_b32 s0, s4
.p2align 6
.LBB0_3:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v1, v7
global_store_b32 v[2:3], v6, off
s_cbranch_scc1 .LBB0_3
.LBB0_4:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z3mulPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z3mulPfS_S_i, .Lfunc_end0-_Z3mulPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z3mulPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z3mulPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_001899f8_00000000-6_2_matrix_multiplication.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2061:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2061:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z27__device_stub__Z3mulPfS_S_iPfS_S_i
.type _Z27__device_stub__Z3mulPfS_S_iPfS_S_i, @function
_Z27__device_stub__Z3mulPfS_S_iPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z3mulPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2083:
.size _Z27__device_stub__Z3mulPfS_S_iPfS_S_i, .-_Z27__device_stub__Z3mulPfS_S_iPfS_S_i
.globl _Z3mulPfS_S_i
.type _Z3mulPfS_S_i, @function
_Z3mulPfS_S_i:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z27__device_stub__Z3mulPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _Z3mulPfS_S_i, .-_Z3mulPfS_S_i
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "Failed to allocate device vector A (error code %s)!\n"
.align 8
.LC1:
.string "Failed to allocate device vector B (error code %s)!\n"
.align 8
.LC2:
.string "Failed to allocate device vector C (error code %s)!\n"
.align 8
.LC3:
.string "Failed to copy vector A from host to device (error code %s)!\n"
.align 8
.LC4:
.string "Failed to copy vector B from host to device (error code %s)!\n"
.align 8
.LC5:
.string "Launching CUDA mul kernel with (%d, %d, %d) blocks and (%d, %d, %d) threads per block.\n"
.align 8
.LC6:
.string "Failed to launch mul kernel (error code %s)!\n"
.align 8
.LC7:
.string "Failed to copy vector C from device to host (error code %s)!\n"
.align 8
.LC11:
.string "Result verification failed at element (%d, %d)!\n"
.section .rodata.str1.1,"aMS",@progbits,1
.LC12:
.string "TEST PASSED\n"
.text
.globl _Z6matMulPPfS0_S0_i
.type _Z6matMulPPfS0_S0_i, @function
_Z6matMulPPfS0_S0_i:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %rbx
movq %rsi, %rbp
movq %rdx, 8(%rsp)
movl %ecx, %r12d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movq $0, 24(%rsp)
movq $0, 32(%rsp)
movq $0, 40(%rsp)
movl %ecx, %r13d
imull %ecx, %r13d
sall $2, %r13d
movslq %r13d, %r13
movq %r13, %rdi
call malloc@PLT
movq %rax, (%rsp)
movq %r13, %rdi
call malloc@PLT
movq %rax, %r14
movq %r13, %rdi
call malloc@PLT
movq %rax, %r15
testl %r12d, %r12d
jle .L12
movslq %r12d, %r10
leaq 0(,%r10,4), %rsi
movq (%rsp), %rcx
movq %r14, %rdx
salq $3, %r10
movl $0, %r9d
movq %rax, %r11
.L13:
movq (%rbx,%r9), %r8
movq 0(%rbp,%r9), %rdi
movl $0, %eax
.L14:
movss (%r8,%rax), %xmm0
movss %xmm0, (%rcx,%rax)
movss (%rdi,%rax), %xmm0
movss %xmm0, (%rdx,%rax)
addq $4, %rax
cmpq %rsi, %rax
jne .L14
addq %rsi, %rcx
addq %rsi, %rdx
addq $8, %r9
cmpq %r10, %r9
jne .L13
movq %r11, %r15
.L12:
leaq 24(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L37
leaq 32(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L38
leaq 40(%rsp), %rdi
movq %r13, %rsi
call cudaMalloc@PLT
movl %eax, %edi
testl %eax, %eax
jne .L39
movl $1, %ecx
movq %r13, %rdx
movq (%rsp), %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L40
movl $1, %ecx
movq %r13, %rdx
movq %r14, %rsi
movq 32(%rsp), %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L41
leal 30(%r12), %r14d
movl %r12d, %eax
addl $15, %eax
cmovns %eax, %r14d
sarl $4, %r14d
pushq $1
.cfi_def_cfa_offset 152
pushq $16
.cfi_def_cfa_offset 160
movl $16, %r9d
movl $1, %r8d
movl %r14d, %ecx
movl %r14d, %edx
leaq .LC5(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r14d, 64(%rsp)
movl %r14d, 68(%rsp)
movl $1, 72(%rsp)
movl $16, 76(%rsp)
movl $16, 80(%rsp)
movl $1, 84(%rsp)
addq $16, %rsp
.cfi_def_cfa_offset 144
movl $0, %r9d
movl $0, %r8d
movq 48(%rsp), %rdx
movl $1, %ecx
movq 60(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L42
.L20:
call cudaGetLastError@PLT
movl %eax, %edi
testl %eax, %eax
jne .L43
movl $2, %ecx
movq %r13, %rdx
movq 40(%rsp), %rsi
movq %r15, %rdi
call cudaMemcpy@PLT
movl %eax, %edi
testl %eax, %eax
jne .L44
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 32(%rsp), %rdi
call cudaFree@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
testl %r12d, %r12d
jle .L23
movslq %r12d, %r10
leaq 0(,%r10,4), %rdi
movq %r15, %r11
movq 8(%rsp), %r9
movl $0, %r13d
movss .LC9(%rip), %xmm3
movsd .LC10(%rip), %xmm2
jmp .L24
.L37:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC0(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L38:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC1(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L39:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC2(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L40:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC3(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L41:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC4(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L42:
movl %r12d, %ecx
movq 40(%rsp), %rdx
movq 32(%rsp), %rsi
movq 24(%rsp), %rdi
call _Z27__device_stub__Z3mulPfS_S_iPfS_S_i
jmp .L20
.L43:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC6(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L44:
call cudaGetErrorString@PLT
movq %rax, %rcx
leaq .LC7(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L47:
movss (%r11,%r8,4), %xmm1
addq (%rsi), %rcx
movaps %xmm1, %xmm0
subss (%rcx), %xmm0
andps %xmm3, %xmm0
cvtss2sd %xmm0, %xmm0
comisd %xmm2, %xmm0
ja .L45
movss %xmm1, (%rcx)
addq $1, %r8
cmpq %r10, %r8
je .L46
.L28:
movq %r9, %rsi
leaq 0(,%r8,4), %rcx
movq (%r9), %rax
movl $0x00000000, (%rax,%r8,4)
movl $0, %eax
.L25:
movq %rcx, %rdx
addq (%rsi), %rdx
movq 0(%rbp,%rax,2), %r14
movq (%rbx), %r15
movss (%r15,%rax), %xmm0
mulss (%r14,%rcx), %xmm0
addss (%rdx), %xmm0
movss %xmm0, (%rdx)
addq $4, %rax
cmpq %rdi, %rax
jne .L25
jmp .L47
.L45:
movl %r13d, %ecx
leaq .LC11(%rip), %rdx
movl $2, %esi
movq stderr(%rip), %rdi
movl $0, %eax
call __fprintf_chk@PLT
movl $1, %edi
call exit@PLT
.L46:
addl $1, %r13d
addq %rdi, %r11
addq $8, %r9
addq $8, %rbx
cmpl %r13d, %r12d
je .L23
.L24:
movl $0, %r8d
jmp .L28
.L23:
leaq .LC12(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L48
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z6matMulPPfS0_S0_i, .-_Z6matMulPPfS0_S0_i
.section .rodata.str1.8
.align 8
.LC13:
.string "Enter the dimension of square matrix, n for n X n: "
.section .rodata.str1.1
.LC14:
.string "%d"
.text
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC13(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
leaq 20(%rsp), %rsi
leaq .LC14(%rip), %rdi
movl $0, %eax
call __isoc23_scanf@PLT
movl 20(%rsp), %ebx
movslq %ebx, %rbp
leaq 0(,%rbp,8), %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, %r15
testl %ebx, %ebx
jle .L50
salq $2, %rbp
movq %rax, %rbx
leaq (%r12,%rax), %r13
.L51:
movq %rbp, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r13, %rbx
jne .L51
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movq %rax, %rbx
leaq (%r12,%rax), %r13
.L52:
movq %rbp, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r13, %rbx
jne .L52
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movq %rax, %rbx
addq %rax, %r12
.L53:
movq %rbp, %rdi
call malloc@PLT
movq %rax, (%rbx)
addq $8, %rbx
cmpq %r12, %rbx
jne .L53
.L58:
movl $0, %edi
call time@PLT
movl %eax, %edi
call srand@PLT
movl 20(%rsp), %ecx
testl %ecx, %ecx
jle .L54
movq %r15, %r12
movq %r14, %rbp
movl $0, %r13d
jmp .L55
.L56:
call rand@PLT
movq (%r12), %rcx
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx,%rbx,4)
call rand@PLT
movq 0(%rbp), %rcx
movslq %eax, %rdx
imulq $274877907, %rdx, %rdx
sarq $38, %rdx
movl %eax, %esi
sarl $31, %esi
subl %esi, %edx
imull $1000, %edx, %edx
subl %edx, %eax
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rcx,%rbx,4)
addq $1, %rbx
cmpl %ebx, 20(%rsp)
jg .L56
.L57:
addl $1, %r13d
movl 20(%rsp), %ecx
addq $8, %r12
addq $8, %rbp
cmpl %r13d, %ecx
jle .L54
.L55:
movl $0, %ebx
cmpl $0, 20(%rsp)
jg .L56
jmp .L57
.L54:
movq 8(%rsp), %rdx
movq %r14, %rsi
movq %r15, %rdi
call _Z6matMulPPfS0_S0_i
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L68
movl $0, %eax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L50:
.cfi_restore_state
movq %r12, %rdi
call malloc@PLT
movq %rax, %r14
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
jmp .L58
.L68:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1
.LC15:
.string "_Z3mulPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2086:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC15(%rip), %rdx
movq %rdx, %rcx
leaq _Z3mulPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2086:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC9:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC10:
.long -1998362383
.long 1055193269
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "2_matrix_multiplication.hip"
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl $.L.str, %edi
xorl %eax, %eax
callq printf
leaq 12(%rsp), %rsi
movl $.L.str.1, %edi
xorl %eax, %eax
callq __isoc23_scanf
movslq 12(%rsp), %r13
leaq (,%r13,8), %r15
movq %r15, %rdi
callq malloc
movq %rax, %rbx
movl %r13d, %ebp
testq %r13, %r13
jle .LBB0_3
# %bb.1: # %.lr.ph
leaq (,%r13,4), %r14
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB0_2: # =>This Inner Loop Header: Depth=1
movq %r14, %rdi
callq malloc
movq %rax, (%rbx,%r12,8)
incq %r12
cmpq %r12, %rbp
jne .LBB0_2
.LBB0_3: # %._crit_edge
movq %r15, 16(%rsp) # 8-byte Spill
movq %r15, %rdi
callq malloc
movq %rax, %r14
testl %r13d, %r13d
jle .LBB0_6
# %bb.4: # %.lr.ph34
leaq (,%r13,4), %r12
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB0_5: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
callq malloc
movq %rax, (%r14,%r15,8)
incq %r15
cmpq %r15, %rbp
jne .LBB0_5
.LBB0_6: # %._crit_edge35
movq 16(%rsp), %rdi # 8-byte Reload
callq malloc
movq %rax, %r15
testl %ebp, %ebp
jle .LBB0_9
# %bb.7: # %.lr.ph38
leaq (,%r13,4), %r12
movl %r13d, %r13d
xorl %ebp, %ebp
.p2align 4, 0x90
.LBB0_8: # =>This Inner Loop Header: Depth=1
movq %r12, %rdi
callq malloc
movq %rax, (%r15,%rbp,8)
incq %rbp
cmpq %rbp, %r13
jne .LBB0_8
.LBB0_9: # %._crit_edge39
xorl %edi, %edi
callq time
movl %eax, %edi
callq srand
movl 12(%rsp), %ecx
testl %ecx, %ecx
jle .LBB0_15
# %bb.10: # %.preheader.preheader
xorl %r12d, %r12d
jmp .LBB0_11
.p2align 4, 0x90
.LBB0_14: # %._crit_edge42
# in Loop: Header=BB0_11 Depth=1
incq %r12
movslq 12(%rsp), %rcx
cmpq %rcx, %r12
jge .LBB0_15
.LBB0_11: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB0_13 Depth 2
cmpl $0, 12(%rsp)
jle .LBB0_14
# %bb.12: # %.lr.ph41
# in Loop: Header=BB0_11 Depth=1
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB0_13: # Parent Loop BB0_11 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%rbx,%r12,8), %rax
movss %xmm0, (%rax,%r13,4)
callq rand
cltq
imulq $274877907, %rax, %rcx # imm = 0x10624DD3
movq %rcx, %rdx
shrq $63, %rdx
sarq $38, %rcx
addl %edx, %ecx
imull $1000, %ecx, %ecx # imm = 0x3E8
subl %ecx, %eax
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movq (%r14,%r12,8), %rax
movss %xmm0, (%rax,%r13,4)
incq %r13
movslq 12(%rsp), %rax
cmpq %rax, %r13
jl .LBB0_13
jmp .LBB0_14
.LBB0_15: # %._crit_edge44
movq %rbx, %rdi
movq %r14, %rsi
movq %r15, %rdx
# kill: def $ecx killed $ecx killed $rcx
callq _Z6matMulPPfS0_S0_i
xorl %eax, %eax
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size main, .Lfunc_end0-main
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z6matMulPPfS0_S0_i
.LCPI1_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI1_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl _Z6matMulPPfS0_S0_i
.p2align 4, 0x90
.type _Z6matMulPPfS0_S0_i,@function
_Z6matMulPPfS0_S0_i: # @_Z6matMulPPfS0_S0_i
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %ecx, %ebx
movq %rdx, 40(%rsp) # 8-byte Spill
movq %rsi, %r15
movq %rdi, %r12
movl %ecx, %eax
imull %ecx, %eax
shll $2, %eax
movq $0, 24(%rsp)
movq $0, 16(%rsp)
movq $0, 8(%rsp)
movslq %eax, %r13
movq %r13, %rdi
callq malloc
movq %rax, %r14
movq %r13, %rdi
callq malloc
movq %rax, %rbp
movq %r13, (%rsp) # 8-byte Spill
movq %r13, %rdi
callq malloc
movq %rax, 48(%rsp) # 8-byte Spill
movl %ebx, %r13d
testl %ebx, %ebx
jle .LBB1_5
# %bb.1: # %.preheader115.lr.ph
xorl %eax, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_2: # %.preheader115
# =>This Loop Header: Depth=1
# Child Loop BB1_3 Depth 2
movl %eax, %esi
leaq (,%rsi,4), %rdx
addq %rbp, %rdx
leaq (%r14,%rsi,4), %rsi
movq (%r12,%rcx,8), %rdi
movq (%r15,%rcx,8), %r8
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_3: # Parent Loop BB1_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rdi,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rsi,%r9,4)
movss (%r8,%r9,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss %xmm0, (%rdx,%r9,4)
incq %r9
cmpq %r9, %r13
jne .LBB1_3
# %bb.4: # %._crit_edge
# in Loop: Header=BB1_2 Depth=1
incq %rcx
addl %ebx, %eax
cmpq %r13, %rcx
jne .LBB1_2
.LBB1_5: # %._crit_edge120
leaq 24(%rsp), %rdi
movq (%rsp), %rsi # 8-byte Reload
callq hipMalloc
testl %eax, %eax
jne .LBB1_6
# %bb.8:
leaq 16(%rsp), %rdi
movq (%rsp), %rsi # 8-byte Reload
callq hipMalloc
testl %eax, %eax
jne .LBB1_9
# %bb.10:
leaq 8(%rsp), %rdi
movq (%rsp), %rsi # 8-byte Reload
callq hipMalloc
testl %eax, %eax
jne .LBB1_11
# %bb.12:
movq 24(%rsp), %rdi
movq %r14, %rsi
movq (%rsp), %r14 # 8-byte Reload
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_13
# %bb.14:
movq 16(%rsp), %rdi
movq %rbp, %rsi
movq %r14, %rdx
movl $1, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_15
# %bb.16:
leal 15(%rbx), %eax
leal 30(%rbx), %r14d
testl %eax, %eax
cmovnsl %eax, %r14d
sarl $4, %r14d
subq $8, %rsp
.cfi_adjust_cfa_offset 8
movl $.L.str.7, %edi
movl %r14d, %esi
movl %r14d, %edx
movl $1, %ecx
movl $16, %r8d
movl $16, %r9d
xorl %eax, %eax
pushq $1
.cfi_adjust_cfa_offset 8
callq printf
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movq %r14, %rdx
shlq $32, %rdx
orq %r14, %rdx
movabsq $68719476752, %rdi # imm = 0x1000000010
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_18
# %bb.17:
movq 24(%rsp), %rax
movq 16(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 120(%rsp)
movq %rcx, 112(%rsp)
movq %rdx, 104(%rsp)
movl %ebx, 36(%rsp)
leaq 120(%rsp), %rax
movq %rax, 128(%rsp)
leaq 112(%rsp), %rax
movq %rax, 136(%rsp)
leaq 104(%rsp), %rax
movq %rax, 144(%rsp)
leaq 36(%rsp), %rax
movq %rax, 152(%rsp)
leaq 88(%rsp), %rdi
leaq 72(%rsp), %rsi
leaq 64(%rsp), %rdx
leaq 56(%rsp), %rcx
callq __hipPopCallConfiguration
movq 88(%rsp), %rsi
movl 96(%rsp), %edx
movq 72(%rsp), %rcx
movl 80(%rsp), %r8d
leaq 128(%rsp), %r9
movl $_Z3mulPfS_S_i, %edi
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_18:
callq hipGetLastError
testl %eax, %eax
movq 48(%rsp), %r14 # 8-byte Reload
jne .LBB1_19
# %bb.20:
movq 8(%rsp), %rsi
movq %r14, %rdi
movq (%rsp), %rdx # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
testl %eax, %eax
jne .LBB1_21
# %bb.22:
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
testl %ebx, %ebx
movq 40(%rsp), %r10 # 8-byte Reload
jle .LBB1_30
# %bb.23: # %.preheader.lr.ph
xorl %edx, %edx
movaps .LCPI1_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI1_1(%rip), %xmm1 # xmm1 = mem[0],zero
.p2align 4, 0x90
.LBB1_24: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_25 Depth 2
# Child Loop BB1_26 Depth 3
movq (%r10,%rdx,8), %rax
movl %edx, %ecx
imull %ebx, %ecx
movq (%r12,%rdx,8), %rsi
leaq (%r14,%rcx,4), %rdi
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB1_25: # %.lr.ph123
# Parent Loop BB1_24 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_26 Depth 3
movl $0, (%rax,%rcx,4)
xorps %xmm2, %xmm2
xorl %r8d, %r8d
.p2align 4, 0x90
.LBB1_26: # Parent Loop BB1_24 Depth=1
# Parent Loop BB1_25 Depth=2
# => This Inner Loop Header: Depth=3
movss (%rsi,%r8,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movq (%r15,%r8,8), %r9
mulss (%r9,%rcx,4), %xmm3
addss %xmm3, %xmm2
movss %xmm2, (%rax,%rcx,4)
incq %r8
cmpq %r8, %r13
jne .LBB1_26
# %bb.27: # %._crit_edge124
# in Loop: Header=BB1_25 Depth=2
movss (%rdi,%rcx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movaps %xmm2, %xmm3
subss (%rax,%rcx,4), %xmm3
andps %xmm0, %xmm3
cvtss2sd %xmm3, %xmm3
ucomisd %xmm1, %xmm3
ja .LBB1_31
# %bb.28: # in Loop: Header=BB1_25 Depth=2
movss %xmm2, (%rax,%rcx,4)
incq %rcx
cmpq %r13, %rcx
jne .LBB1_25
# %bb.29: # %._crit_edge127
# in Loop: Header=BB1_24 Depth=1
incq %rdx
cmpq %r13, %rdx
jne .LBB1_24
.LBB1_30: # %._crit_edge129
movl $.Lstr, %edi
callq puts@PLT
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB1_31:
.cfi_def_cfa_offset 224
movq stderr(%rip), %rdi
movl $.L.str.10, %esi
# kill: def $edx killed $edx killed $rdx
# kill: def $ecx killed $ecx killed $rcx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.LBB1_6:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.2, %esi
jmp .LBB1_7
.LBB1_9:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.3, %esi
jmp .LBB1_7
.LBB1_11:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.4, %esi
jmp .LBB1_7
.LBB1_13:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.5, %esi
jmp .LBB1_7
.LBB1_15:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.6, %esi
jmp .LBB1_7
.LBB1_19:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.8, %esi
jmp .LBB1_7
.LBB1_21:
movq stderr(%rip), %rbx
movl %eax, %edi
callq hipGetErrorString
movl $.L.str.9, %esi
.LBB1_7:
movq %rbx, %rdi
movq %rax, %rdx
xorl %eax, %eax
callq fprintf
movl $1, %edi
callq exit
.Lfunc_end1:
.size _Z6matMulPPfS0_S0_i, .Lfunc_end1-_Z6matMulPPfS0_S0_i
.cfi_endproc
# -- End function
.globl _Z18__device_stub__mulPfS_S_i # -- Begin function _Z18__device_stub__mulPfS_S_i
.p2align 4, 0x90
.type _Z18__device_stub__mulPfS_S_i,@function
_Z18__device_stub__mulPfS_S_i: # @_Z18__device_stub__mulPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z3mulPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end2:
.size _Z18__device_stub__mulPfS_S_i, .Lfunc_end2-_Z18__device_stub__mulPfS_S_i
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z3mulPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Enter the dimension of square matrix, n for n X n: "
.size .L.str, 52
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "%d"
.size .L.str.1, 3
.type _Z3mulPfS_S_i,@object # @_Z3mulPfS_S_i
.section .rodata,"a",@progbits
.globl _Z3mulPfS_S_i
.p2align 3, 0x0
_Z3mulPfS_S_i:
.quad _Z18__device_stub__mulPfS_S_i
.size _Z3mulPfS_S_i, 8
.type .L.str.2,@object # @.str.2
.section .rodata.str1.1,"aMS",@progbits,1
.L.str.2:
.asciz "Failed to allocate device vector A (error code %s)!\n"
.size .L.str.2, 53
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "Failed to allocate device vector B (error code %s)!\n"
.size .L.str.3, 53
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "Failed to allocate device vector C (error code %s)!\n"
.size .L.str.4, 53
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Failed to copy vector A from host to device (error code %s)!\n"
.size .L.str.5, 62
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "Failed to copy vector B from host to device (error code %s)!\n"
.size .L.str.6, 62
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz "Launching CUDA mul kernel with (%d, %d, %d) blocks and (%d, %d, %d) threads per block.\n"
.size .L.str.7, 88
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "Failed to launch mul kernel (error code %s)!\n"
.size .L.str.8, 46
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "Failed to copy vector C from device to host (error code %s)!\n"
.size .L.str.9, 62
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "Result verification failed at element (%d, %d)!\n"
.size .L.str.10, 49
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z3mulPfS_S_i"
.size .L__unnamed_1, 14
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "TEST PASSED"
.size .Lstr, 12
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z18__device_stub__mulPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z3mulPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
__global__ void matVectMult(float* d_B, float* d_C, float* d_A, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.f;
if(row < numElements && col < numElements) {
for(int i=0; i<numElements; i++)
sum += d_B[row+col*i];
d_A[row] = sum + d_C[row];
}
}
int main() {
// size of matrix and vector
int n = 512;
size_t vectorSize = n*sizeof(float);
size_t matrixSize = n*n*sizeof(float);
float *h_vA;
float *h_mB;
float *h_vC;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_vA = (float*) malloc( vectorSize );
h_mB = (float*) malloc( matrixSize );
h_vC = (float*) malloc( vectorSize );
// matrix initialization
for(int i=0; i<n; i++)
h_vC[i] = i;
for(int i=0; i<n*n; i++)
h_mB[i] = i;
// allocate data in device
cudaMalloc((void**)&d_A, vectorSize);
cudaMalloc((void**)&d_B, matrixSize);
cudaMalloc((void**)&d_C, vectorSize);
// copy inputs to device
cudaMemcpy(d_C, h_vC, vectorSize ,cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_mB, matrixSize ,cudaMemcpyHostToDevice);
// launch kernel
dim3 DimThreadsPerBlock(32,32,1);
dim3 DimBlocks(ceil((n*n)/32.0),ceil(n/32.0),1);
matVectMult<<< DimBlocks, DimThreadsPerBlock>>>(d_B,d_C,d_A, n);
// copy output to host
cudaMemcpy(h_vA, d_A, vectorSize,cudaMemcpyDeviceToHost);
// freeing space
free(h_vA);
free(h_mB);
free(h_vC);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
} | code for sm_80
Function : _Z11matVectMultPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R17, R17, c[0x0][0x0], R2 ; /* 0x0000000011117a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x178], PT ; /* 0x00005e0011007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R18, c[0x0][0x178] ; /* 0x00005e0000127a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x8e0 ; /* 0x000007f000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R18.reuse, -0x1, RZ ; /* 0xffffffff12027810 */
/* 0x040fe20007ffe0ff */
/*0100*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0110*/ LOP3.LUT R18, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312127812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fd60000000f00 */
/*0140*/ @!P0 BRA 0x830 ; /* 0x000006e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R20, -R18, c[0x0][0x178], RZ ; /* 0x00005e0012147a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0180*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0190*/ ISETP.GT.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fcc0003f04270 */
/*01a0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fce00078e0205 */
/*01b0*/ @!P0 BRA 0x730 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.GT.AND P1, PT, R20, 0xc, PT ; /* 0x0000000c1400780c */
/* 0x000fe40003f24270 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01e0*/ @!P1 BRA 0x540 ; /* 0x0000035000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ IMAD.WIDE R12, R17.reuse, 0x4, R4 ; /* 0x00000004110c7825 */
/* 0x040fe200078e0204 */
/*0210*/ LDG.E R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x0000a8000c1e1900 */
/*0220*/ LDG.E R19, [R12.64] ; /* 0x000000060c137981 */
/* 0x0002e2000c1e1900 */
/*0230*/ IMAD.WIDE R22, R17, 0x4, R12 ; /* 0x0000000411167825 */
/* 0x000fcc00078e020c */
/*0240*/ IMAD.WIDE R14, R17.reuse, 0x4, R22 ; /* 0x00000004110e7825 */
/* 0x040fe400078e0216 */
/*0250*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000968000c1e1900 */
/*0260*/ IMAD.WIDE R24, R17, 0x4, R14 ; /* 0x0000000411187825 */
/* 0x000fcc00078e020e */
/*0270*/ IMAD.WIDE R26, R17.reuse, 0x4, R24 ; /* 0x00000004111a7825 */
/* 0x040fe200078e0218 */
/*0280*/ LDG.E R23, [R14.64] ; /* 0x000000060e177981 */
/* 0x010968000c1e1900 */
/*0290*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000162000c1e1900 */
/*02a0*/ IMAD.WIDE R10, R17, 0x4, R26 ; /* 0x00000004110a7825 */
/* 0x000fca00078e021a */
/*02b0*/ LDG.E R28, [R10.64] ; /* 0x000000060a1c7981 */
/* 0x000362000c1e1900 */
/*02c0*/ IMAD.WIDE R6, R17, 0x4, R10 ; /* 0x0000000411067825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R25, [R26.64] ; /* 0x000000061a197981 */
/* 0x001166000c1e1900 */
/*02e0*/ IMAD.WIDE R8, R17.reuse, 0x4, R6 ; /* 0x0000000411087825 */
/* 0x040fe400078e0206 */
/*02f0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000168000c1e1900 */
/*0300*/ IMAD.WIDE R2, R17.reuse, 0x4, R8 ; /* 0x0000000411027825 */
/* 0x040fe200078e0208 */
/*0310*/ LDG.E R29, [R8.64] ; /* 0x00000006081d7981 */
/* 0x00016a000c1e1900 */
/*0320*/ IMAD.WIDE R4, R17, 0x4, R2 ; /* 0x0000000411047825 */
/* 0x000fc400078e0202 */
/*0330*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000168000c1e1900 */
/*0340*/ IMAD.WIDE R12, R17.reuse, 0x4, R4 ; /* 0x00000004110c7825 */
/* 0x042fe400078e0204 */
/*0350*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000f68000c1e1900 */
/*0360*/ IMAD.WIDE R14, R17, 0x4, R12 ; /* 0x00000004110e7825 */
/* 0x010fc400078e020c */
/*0370*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f28000c1e1900 */
/*0380*/ IMAD.WIDE R26, R17.reuse, 0x4, R14 ; /* 0x00000004111a7825 */
/* 0x041fe400078e020e */
/*0390*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f28000c1e1900 */
/*03a0*/ IMAD.WIDE R10, R17, 0x4, R26 ; /* 0x00000004110a7825 */
/* 0x000fc400078e021a */
/*03b0*/ LDG.E R26, [R26.64] ; /* 0x000000061a1a7981 */
/* 0x000f28000c1e1900 */
/*03c0*/ IMAD.WIDE R8, R17, 0x4, R10 ; /* 0x0000000411087825 */
/* 0x000fe200078e020a */
/*03d0*/ LDG.E R7, [R10.64] ; /* 0x000000060a077981 */
/* 0x000f28000c1e1900 */
/*03e0*/ LDG.E R3, [R8.64] ; /* 0x0000000608037981 */
/* 0x000f22000c1e1900 */
/*03f0*/ IADD3 R20, R20, -0x10, RZ ; /* 0xfffffff014147810 */
/* 0x000fc80007ffe0ff */
/*0400*/ ISETP.GT.AND P1, PT, R20, 0xc, PT ; /* 0x0000000c1400780c */
/* 0x000fe20003f24270 */
/*0410*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0420*/ FADD R16, R16, R21 ; /* 0x0000001510107221 */
/* 0x004fc80000000000 */
/*0430*/ FADD R19, R16, R19 ; /* 0x0000001310137221 */
/* 0x008fc80000000000 */
/*0440*/ FADD R22, R19, R22 ; /* 0x0000001613167221 */
/* 0x020fc80000000000 */
/*0450*/ FADD R23, R22, R23 ; /* 0x0000001716177221 */
/* 0x000fc80000000000 */
/*0460*/ FADD R24, R23, R24 ; /* 0x0000001817187221 */
/* 0x000fc80000000000 */
/*0470*/ FADD R25, R24, R25 ; /* 0x0000001918197221 */
/* 0x000fc80000000000 */
/*0480*/ FADD R25, R25, R28 ; /* 0x0000001c19197221 */
/* 0x000fc80000000000 */
/*0490*/ FADD R6, R25, R6 ; /* 0x0000000619067221 */
/* 0x000fc80000000000 */
/*04a0*/ FADD R29, R6, R29 ; /* 0x0000001d061d7221 */
/* 0x000fc80000000000 */
/*04b0*/ FADD R29, R29, R2 ; /* 0x000000021d1d7221 */
/* 0x000fc80000000000 */
/*04c0*/ FADD R29, R29, R4 ; /* 0x000000041d1d7221 */
/* 0x000fc80000000000 */
/*04d0*/ FADD R29, R29, R12 ; /* 0x0000000c1d1d7221 */
/* 0x010fc80000000000 */
/*04e0*/ FADD R29, R29, R14 ; /* 0x0000000e1d1d7221 */
/* 0x000fc80000000000 */
/*04f0*/ FADD R26, R29, R26 ; /* 0x0000001a1d1a7221 */
/* 0x000fc80000000000 */
/*0500*/ FADD R26, R26, R7 ; /* 0x000000071a1a7221 */
/* 0x000fe40000000000 */
/*0510*/ IMAD.WIDE R4, R17, 0x4, R8 ; /* 0x0000000411047825 */
/* 0x000fc800078e0208 */
/*0520*/ FADD R21, R26, R3 ; /* 0x000000031a157221 */
/* 0x000fe20000000000 */
/*0530*/ @P1 BRA 0x200 ; /* 0xfffffcc000001947 */
/* 0x000fea000383ffff */
/*0540*/ ISETP.GT.AND P1, PT, R20, 0x4, PT ; /* 0x000000041400780c */
/* 0x000fda0003f24270 */
/*0550*/ @!P1 BRA 0x710 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.WIDE R6, R17.reuse, 0x4, R4 ; /* 0x0000000411067825 */
/* 0x040fe400078e0204 */
/*0570*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x0000a8000c1e1900 */
/*0580*/ IMAD.WIDE R8, R17.reuse, 0x4, R6 ; /* 0x0000000411087825 */
/* 0x040fe400078e0206 */
/*0590*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ IMAD.WIDE R10, R17, 0x4, R8 ; /* 0x00000004110a7825 */
/* 0x000fc400078e0208 */
/*05b0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000f28000c1e1900 */
/*05c0*/ IMAD.WIDE R12, R17.reuse, 0x4, R10 ; /* 0x00000004110c7825 */
/* 0x040fe400078e020a */
/*05d0*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000f68000c1e1900 */
/*05e0*/ IMAD.WIDE R14, R17, 0x4, R12 ; /* 0x00000004110e7825 */
/* 0x000fc400078e020c */
/*05f0*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000f68000c1e1900 */
/*0600*/ IMAD.WIDE R22, R17.reuse, 0x4, R14 ; /* 0x0000000411167825 */
/* 0x040fe400078e020e */
/*0610*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000f68000c1e1900 */
/*0620*/ IMAD.WIDE R2, R17, 0x4, R22 ; /* 0x0000000411027825 */
/* 0x000fc400078e0216 */
/*0630*/ LDG.E R23, [R22.64] ; /* 0x0000000616177981 */
/* 0x000f68000c1e1900 */
/*0640*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x001f62000c1e1900 */
/*0650*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0660*/ IADD3 R20, R20, -0x8, RZ ; /* 0xfffffff814147810 */
/* 0x000fe20007ffe0ff */
/*0670*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0680*/ FADD R4, R21, R4 ; /* 0x0000000415047221 */
/* 0x004fc80000000000 */
/*0690*/ FADD R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x008fc80000000000 */
/*06a0*/ FADD R4, R4, R9 ; /* 0x0000000904047221 */
/* 0x010fc80000000000 */
/*06b0*/ FADD R4, R4, R11 ; /* 0x0000000b04047221 */
/* 0x020fc80000000000 */
/*06c0*/ FADD R4, R4, R13 ; /* 0x0000000d04047221 */
/* 0x000fc80000000000 */
/*06d0*/ FADD R4, R4, R15 ; /* 0x0000000f04047221 */
/* 0x000fc80000000000 */
/*06e0*/ FADD R4, R4, R23 ; /* 0x0000001704047221 */
/* 0x000fc80000000000 */
/*06f0*/ FADD R21, R4, R5 ; /* 0x0000000504157221 */
/* 0x000fe40000000000 */
/*0700*/ IMAD.WIDE R4, R17, 0x4, R2 ; /* 0x0000000411047825 */
/* 0x000fc800078e0202 */
/*0710*/ ISETP.NE.OR P0, PT, R20, RZ, P0 ; /* 0x000000ff1400720c */
/* 0x000fda0000705670 */
/*0720*/ @!P0 BRA 0x830 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0730*/ IMAD.WIDE R2, R17.reuse, 0x4, R4 ; /* 0x0000000411027825 */
/* 0x040fe400078e0204 */
/*0740*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*0750*/ IMAD.WIDE R6, R17.reuse, 0x4, R2 ; /* 0x0000000411067825 */
/* 0x040fe400078e0202 */
/*0760*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ee8000c1e1900 */
/*0770*/ IMAD.WIDE R8, R17, 0x4, R6 ; /* 0x0000000411087825 */
/* 0x000fe200078e0206 */
/*0780*/ LDG.E R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x000f28000c1e1900 */
/*0790*/ LDG.E R12, [R8.64] ; /* 0x00000006080c7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IADD3 R20, R20, -0x4, RZ ; /* 0xfffffffc14147810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000fffe03f */
/*07c0*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f05270 */
/*07d0*/ FADD R21, R4, R21 ; /* 0x0000001504157221 */
/* 0x004fe40000000000 */
/*07e0*/ IMAD.WIDE R4, R17, 0x4, R8 ; /* 0x0000000411047825 */
/* 0x000fc800078e0208 */
/*07f0*/ FADD R21, R21, R2 ; /* 0x0000000215157221 */
/* 0x008fc80000000000 */
/*0800*/ FADD R21, R21, R10 ; /* 0x0000000a15157221 */
/* 0x010fc80000000000 */
/*0810*/ FADD R21, R21, R12 ; /* 0x0000000c15157221 */
/* 0x020fe20000000000 */
/*0820*/ @P0 BRA 0x730 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0830*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fda0003f05270 */
/*0840*/ @!P0 BRA 0x8e0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0850*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0860*/ IMAD R2, R17, UR4, R0 ; /* 0x0000000411027c24 */
/* 0x000fd2000f8e0200 */
/*0870*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0880*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x0000a2000c1e1900 */
/*0890*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fc80007ffe0ff */
/*08a0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f05270 */
/*08b0*/ IMAD.WIDE R2, R17, 0x4, R2 ; /* 0x0000000411027825 */
/* 0x001fc800078e0202 */
/*08c0*/ FADD R21, R4, R21 ; /* 0x0000001504157221 */
/* 0x004fd00000000000 */
/*08d0*/ @P0 BRA 0x880 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*08e0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*08f0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0900*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0205 */
/*0920*/ FADD R21, R2, R21 ; /* 0x0000001502157221 */
/* 0x004fca0000000000 */
/*0930*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x000fe2000c101906 */
/*0940*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0950*/ BRA 0x950; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
__global__ void matVectMult(float* d_B, float* d_C, float* d_A, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.f;
if(row < numElements && col < numElements) {
for(int i=0; i<numElements; i++)
sum += d_B[row+col*i];
d_A[row] = sum + d_C[row];
}
}
int main() {
// size of matrix and vector
int n = 512;
size_t vectorSize = n*sizeof(float);
size_t matrixSize = n*n*sizeof(float);
float *h_vA;
float *h_mB;
float *h_vC;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_vA = (float*) malloc( vectorSize );
h_mB = (float*) malloc( matrixSize );
h_vC = (float*) malloc( vectorSize );
// matrix initialization
for(int i=0; i<n; i++)
h_vC[i] = i;
for(int i=0; i<n*n; i++)
h_mB[i] = i;
// allocate data in device
cudaMalloc((void**)&d_A, vectorSize);
cudaMalloc((void**)&d_B, matrixSize);
cudaMalloc((void**)&d_C, vectorSize);
// copy inputs to device
cudaMemcpy(d_C, h_vC, vectorSize ,cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_mB, matrixSize ,cudaMemcpyHostToDevice);
// launch kernel
dim3 DimThreadsPerBlock(32,32,1);
dim3 DimBlocks(ceil((n*n)/32.0),ceil(n/32.0),1);
matVectMult<<< DimBlocks, DimThreadsPerBlock>>>(d_B,d_C,d_A, n);
// copy output to host
cudaMemcpy(h_vA, d_A, vectorSize,cudaMemcpyDeviceToHost);
// freeing space
free(h_vA);
free(h_mB);
free(h_vC);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
} | .file "tmpxft_0012f94f_00000000-6_matrix_vect_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i
.type _Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i, @function
_Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11matVectMultPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i, .-_Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i
.globl _Z11matVectMultPfS_S_i
.type _Z11matVectMultPfS_S_i, @function
_Z11matVectMultPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11matVectMultPfS_S_i, .-_Z11matVectMultPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $2048, %edi
call malloc@PLT
movq %rax, %r12
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbp
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L12
movl $0, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $262144, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $8192, 44(%rsp)
movl $16, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $512, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11matVectMultPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matVectMultPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
__global__ void matVectMult(float* d_B, float* d_C, float* d_A, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.f;
if(row < numElements && col < numElements) {
for(int i=0; i<numElements; i++)
sum += d_B[row+col*i];
d_A[row] = sum + d_C[row];
}
}
int main() {
// size of matrix and vector
int n = 512;
size_t vectorSize = n*sizeof(float);
size_t matrixSize = n*n*sizeof(float);
float *h_vA;
float *h_mB;
float *h_vC;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_vA = (float*) malloc( vectorSize );
h_mB = (float*) malloc( matrixSize );
h_vC = (float*) malloc( vectorSize );
// matrix initialization
for(int i=0; i<n; i++)
h_vC[i] = i;
for(int i=0; i<n*n; i++)
h_mB[i] = i;
// allocate data in device
cudaMalloc((void**)&d_A, vectorSize);
cudaMalloc((void**)&d_B, matrixSize);
cudaMalloc((void**)&d_C, vectorSize);
// copy inputs to device
cudaMemcpy(d_C, h_vC, vectorSize ,cudaMemcpyHostToDevice);
cudaMemcpy(d_B, h_mB, matrixSize ,cudaMemcpyHostToDevice);
// launch kernel
dim3 DimThreadsPerBlock(32,32,1);
dim3 DimBlocks(ceil((n*n)/32.0),ceil(n/32.0),1);
matVectMult<<< DimBlocks, DimThreadsPerBlock>>>(d_B,d_C,d_A, n);
// copy output to host
cudaMemcpy(h_vA, d_A, vectorSize,cudaMemcpyDeviceToHost);
// freeing space
free(h_vA);
free(h_mB);
free(h_vC);
cudaFree(d_A);
cudaFree(d_B);
cudaFree(d_C);
} | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matVectMult(float* d_B, float* d_C, float* d_A, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.f;
if(row < numElements && col < numElements) {
for(int i=0; i<numElements; i++)
sum += d_B[row+col*i];
d_A[row] = sum + d_C[row];
}
}
int main() {
// size of matrix and vector
int n = 512;
size_t vectorSize = n*sizeof(float);
size_t matrixSize = n*n*sizeof(float);
float *h_vA;
float *h_mB;
float *h_vC;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_vA = (float*) malloc( vectorSize );
h_mB = (float*) malloc( matrixSize );
h_vC = (float*) malloc( vectorSize );
// matrix initialization
for(int i=0; i<n; i++)
h_vC[i] = i;
for(int i=0; i<n*n; i++)
h_mB[i] = i;
// allocate data in device
hipMalloc((void**)&d_A, vectorSize);
hipMalloc((void**)&d_B, matrixSize);
hipMalloc((void**)&d_C, vectorSize);
// copy inputs to device
hipMemcpy(d_C, h_vC, vectorSize ,hipMemcpyHostToDevice);
hipMemcpy(d_B, h_mB, matrixSize ,hipMemcpyHostToDevice);
// launch kernel
dim3 DimThreadsPerBlock(32,32,1);
dim3 DimBlocks(ceil((n*n)/32.0),ceil(n/32.0),1);
matVectMult<<< DimBlocks, DimThreadsPerBlock>>>(d_B,d_C,d_A, n);
// copy output to host
hipMemcpy(h_vA, d_A, vectorSize,hipMemcpyDeviceToHost);
// freeing space
free(h_vA);
free(h_mB);
free(h_vC);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matVectMult(float* d_B, float* d_C, float* d_A, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.f;
if(row < numElements && col < numElements) {
for(int i=0; i<numElements; i++)
sum += d_B[row+col*i];
d_A[row] = sum + d_C[row];
}
}
int main() {
// size of matrix and vector
int n = 512;
size_t vectorSize = n*sizeof(float);
size_t matrixSize = n*n*sizeof(float);
float *h_vA;
float *h_mB;
float *h_vC;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_vA = (float*) malloc( vectorSize );
h_mB = (float*) malloc( matrixSize );
h_vC = (float*) malloc( vectorSize );
// matrix initialization
for(int i=0; i<n; i++)
h_vC[i] = i;
for(int i=0; i<n*n; i++)
h_mB[i] = i;
// allocate data in device
hipMalloc((void**)&d_A, vectorSize);
hipMalloc((void**)&d_B, matrixSize);
hipMalloc((void**)&d_C, vectorSize);
// copy inputs to device
hipMemcpy(d_C, h_vC, vectorSize ,hipMemcpyHostToDevice);
hipMemcpy(d_B, h_mB, matrixSize ,hipMemcpyHostToDevice);
// launch kernel
dim3 DimThreadsPerBlock(32,32,1);
dim3 DimBlocks(ceil((n*n)/32.0),ceil(n/32.0),1);
matVectMult<<< DimBlocks, DimThreadsPerBlock>>>(d_B,d_C,d_A, n);
// copy output to host
hipMemcpy(h_vA, d_A, vectorSize,hipMemcpyDeviceToHost);
// freeing space
free(h_vA);
free(h_mB);
free(h_vC);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11matVectMultPfS_S_i
.globl _Z11matVectMultPfS_S_i
.p2align 8
.type _Z11matVectMultPfS_S_i,@function
_Z11matVectMultPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v2, v0
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s4, s4, -1
s_cmp_eq_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_nc_u32_e32 v2, v2, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v3
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v4, 0
.LBB0_5:
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matVectMultPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11matVectMultPfS_S_i, .Lfunc_end0-_Z11matVectMultPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matVectMultPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matVectMultPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include <stdio.h>
__global__ void matVectMult(float* d_B, float* d_C, float* d_A, int numElements){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
float sum = 0.f;
if(row < numElements && col < numElements) {
for(int i=0; i<numElements; i++)
sum += d_B[row+col*i];
d_A[row] = sum + d_C[row];
}
}
int main() {
// size of matrix and vector
int n = 512;
size_t vectorSize = n*sizeof(float);
size_t matrixSize = n*n*sizeof(float);
float *h_vA;
float *h_mB;
float *h_vC;
float *d_A;
float *d_B;
float *d_C;
// allocate data in host
h_vA = (float*) malloc( vectorSize );
h_mB = (float*) malloc( matrixSize );
h_vC = (float*) malloc( vectorSize );
// matrix initialization
for(int i=0; i<n; i++)
h_vC[i] = i;
for(int i=0; i<n*n; i++)
h_mB[i] = i;
// allocate data in device
hipMalloc((void**)&d_A, vectorSize);
hipMalloc((void**)&d_B, matrixSize);
hipMalloc((void**)&d_C, vectorSize);
// copy inputs to device
hipMemcpy(d_C, h_vC, vectorSize ,hipMemcpyHostToDevice);
hipMemcpy(d_B, h_mB, matrixSize ,hipMemcpyHostToDevice);
// launch kernel
dim3 DimThreadsPerBlock(32,32,1);
dim3 DimBlocks(ceil((n*n)/32.0),ceil(n/32.0),1);
matVectMult<<< DimBlocks, DimThreadsPerBlock>>>(d_B,d_C,d_A, n);
// copy output to host
hipMemcpy(h_vA, d_A, vectorSize,hipMemcpyDeviceToHost);
// freeing space
free(h_vA);
free(h_mB);
free(h_vC);
hipFree(d_A);
hipFree(d_B);
hipFree(d_C);
} | .text
.file "matrix_vect_mult.hip"
.globl _Z26__device_stub__matVectMultPfS_S_i # -- Begin function _Z26__device_stub__matVectMultPfS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__matVectMultPfS_S_i,@function
_Z26__device_stub__matVectMultPfS_S_i: # @_Z26__device_stub__matVectMultPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matVectMultPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__matVectMultPfS_S_i, .Lfunc_end0-_Z26__device_stub__matVectMultPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $512, %rax # imm = 0x200
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $262144, %rax # imm = 0x40000
jne .LBB1_3
# %bb.4:
leaq 24(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $68719484928, %rdi # imm = 0x1000002000
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $512, 36(%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11matVectMultPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 24(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matVectMultPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11matVectMultPfS_S_i,@object # @_Z11matVectMultPfS_S_i
.section .rodata,"a",@progbits
.globl _Z11matVectMultPfS_S_i
.p2align 3, 0x0
_Z11matVectMultPfS_S_i:
.quad _Z26__device_stub__matVectMultPfS_S_i
.size _Z11matVectMultPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11matVectMultPfS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__matVectMultPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11matVectMultPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z11matVectMultPfS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R17, SR_CTAID.X ; /* 0x0000000000117919 */
/* 0x000e280000002500 */
/*0020*/ S2R R2, SR_TID.X ; /* 0x0000000000027919 */
/* 0x000e280000002100 */
/*0030*/ S2R R0, SR_CTAID.Y ; /* 0x0000000000007919 */
/* 0x000e680000002600 */
/*0040*/ S2R R3, SR_TID.Y ; /* 0x0000000000037919 */
/* 0x000e620000002200 */
/*0050*/ IMAD R17, R17, c[0x0][0x0], R2 ; /* 0x0000000011117a24 */
/* 0x001fca00078e0202 */
/*0060*/ ISETP.GE.AND P0, PT, R17, c[0x0][0x178], PT ; /* 0x00005e0011007a0c */
/* 0x000fe20003f06270 */
/*0070*/ IMAD R0, R0, c[0x0][0x4], R3 ; /* 0x0000010000007a24 */
/* 0x002fca00078e0203 */
/*0080*/ ISETP.GE.OR P0, PT, R0, c[0x0][0x178], P0 ; /* 0x00005e0000007a0c */
/* 0x000fda0000706670 */
/*0090*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00a0*/ MOV R18, c[0x0][0x178] ; /* 0x00005e0000127a02 */
/* 0x000fe20000000f00 */
/*00b0*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fe20000000a00 */
/*00c0*/ HFMA2.MMA R21, -RZ, RZ, 0, 0 ; /* 0x00000000ff157435 */
/* 0x000fe400000001ff */
/*00d0*/ ISETP.GE.AND P0, PT, R18, 0x1, PT ; /* 0x000000011200780c */
/* 0x000fda0003f06270 */
/*00e0*/ @!P0 BRA 0x8e0 ; /* 0x000007f000008947 */
/* 0x000fea0003800000 */
/*00f0*/ IADD3 R2, R18.reuse, -0x1, RZ ; /* 0xffffffff12027810 */
/* 0x040fe20007ffe0ff */
/*0100*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0110*/ LOP3.LUT R18, R18, 0x3, RZ, 0xc0, !PT ; /* 0x0000000312127812 */
/* 0x000fe400078ec0ff */
/*0120*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe40003f06070 */
/*0130*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fd60000000f00 */
/*0140*/ @!P0 BRA 0x830 ; /* 0x000006e000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R20, -R18, c[0x0][0x178], RZ ; /* 0x00005e0012147a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fe200000001ff */
/*0170*/ UMOV UR4, URZ ; /* 0x0000003f00047c82 */
/* 0x000fe20008000000 */
/*0180*/ MOV R21, RZ ; /* 0x000000ff00157202 */
/* 0x000fe40000000f00 */
/*0190*/ ISETP.GT.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fcc0003f04270 */
/*01a0*/ IMAD.WIDE R4, R0, R5, c[0x0][0x160] ; /* 0x0000580000047625 */
/* 0x000fce00078e0205 */
/*01b0*/ @!P0 BRA 0x730 ; /* 0x0000057000008947 */
/* 0x000fea0003800000 */
/*01c0*/ ISETP.GT.AND P1, PT, R20, 0xc, PT ; /* 0x0000000c1400780c */
/* 0x000fe40003f24270 */
/*01d0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01e0*/ @!P1 BRA 0x540 ; /* 0x0000035000009947 */
/* 0x000fea0003800000 */
/*01f0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0200*/ IMAD.WIDE R12, R17.reuse, 0x4, R4 ; /* 0x00000004110c7825 */
/* 0x040fe200078e0204 */
/*0210*/ LDG.E R16, [R4.64] ; /* 0x0000000604107981 */
/* 0x0000a8000c1e1900 */
/*0220*/ LDG.E R19, [R12.64] ; /* 0x000000060c137981 */
/* 0x0002e2000c1e1900 */
/*0230*/ IMAD.WIDE R22, R17, 0x4, R12 ; /* 0x0000000411167825 */
/* 0x000fcc00078e020c */
/*0240*/ IMAD.WIDE R14, R17.reuse, 0x4, R22 ; /* 0x00000004110e7825 */
/* 0x040fe400078e0216 */
/*0250*/ LDG.E R22, [R22.64] ; /* 0x0000000616167981 */
/* 0x000968000c1e1900 */
/*0260*/ IMAD.WIDE R24, R17, 0x4, R14 ; /* 0x0000000411187825 */
/* 0x000fcc00078e020e */
/*0270*/ IMAD.WIDE R26, R17.reuse, 0x4, R24 ; /* 0x00000004111a7825 */
/* 0x040fe200078e0218 */
/*0280*/ LDG.E R23, [R14.64] ; /* 0x000000060e177981 */
/* 0x010968000c1e1900 */
/*0290*/ LDG.E R24, [R24.64] ; /* 0x0000000618187981 */
/* 0x000162000c1e1900 */
/*02a0*/ IMAD.WIDE R10, R17, 0x4, R26 ; /* 0x00000004110a7825 */
/* 0x000fca00078e021a */
/*02b0*/ LDG.E R28, [R10.64] ; /* 0x000000060a1c7981 */
/* 0x000362000c1e1900 */
/*02c0*/ IMAD.WIDE R6, R17, 0x4, R10 ; /* 0x0000000411067825 */
/* 0x000fc600078e020a */
/*02d0*/ LDG.E R25, [R26.64] ; /* 0x000000061a197981 */
/* 0x001166000c1e1900 */
/*02e0*/ IMAD.WIDE R8, R17.reuse, 0x4, R6 ; /* 0x0000000411087825 */
/* 0x040fe400078e0206 */
/*02f0*/ LDG.E R6, [R6.64] ; /* 0x0000000606067981 */
/* 0x000168000c1e1900 */
/*0300*/ IMAD.WIDE R2, R17.reuse, 0x4, R8 ; /* 0x0000000411027825 */
/* 0x040fe200078e0208 */
/*0310*/ LDG.E R29, [R8.64] ; /* 0x00000006081d7981 */
/* 0x00016a000c1e1900 */
/*0320*/ IMAD.WIDE R4, R17, 0x4, R2 ; /* 0x0000000411047825 */
/* 0x000fc400078e0202 */
/*0330*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000168000c1e1900 */
/*0340*/ IMAD.WIDE R12, R17.reuse, 0x4, R4 ; /* 0x00000004110c7825 */
/* 0x042fe400078e0204 */
/*0350*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000f68000c1e1900 */
/*0360*/ IMAD.WIDE R14, R17, 0x4, R12 ; /* 0x00000004110e7825 */
/* 0x010fc400078e020c */
/*0370*/ LDG.E R12, [R12.64] ; /* 0x000000060c0c7981 */
/* 0x000f28000c1e1900 */
/*0380*/ IMAD.WIDE R26, R17.reuse, 0x4, R14 ; /* 0x00000004111a7825 */
/* 0x041fe400078e020e */
/*0390*/ LDG.E R14, [R14.64] ; /* 0x000000060e0e7981 */
/* 0x000f28000c1e1900 */
/*03a0*/ IMAD.WIDE R10, R17, 0x4, R26 ; /* 0x00000004110a7825 */
/* 0x000fc400078e021a */
/*03b0*/ LDG.E R26, [R26.64] ; /* 0x000000061a1a7981 */
/* 0x000f28000c1e1900 */
/*03c0*/ IMAD.WIDE R8, R17, 0x4, R10 ; /* 0x0000000411087825 */
/* 0x000fe200078e020a */
/*03d0*/ LDG.E R7, [R10.64] ; /* 0x000000060a077981 */
/* 0x000f28000c1e1900 */
/*03e0*/ LDG.E R3, [R8.64] ; /* 0x0000000608037981 */
/* 0x000f22000c1e1900 */
/*03f0*/ IADD3 R20, R20, -0x10, RZ ; /* 0xfffffff014147810 */
/* 0x000fc80007ffe0ff */
/*0400*/ ISETP.GT.AND P1, PT, R20, 0xc, PT ; /* 0x0000000c1400780c */
/* 0x000fe20003f24270 */
/*0410*/ UIADD3 UR4, UR4, 0x10, URZ ; /* 0x0000001004047890 */
/* 0x000fe2000fffe03f */
/*0420*/ FADD R16, R16, R21 ; /* 0x0000001510107221 */
/* 0x004fc80000000000 */
/*0430*/ FADD R19, R16, R19 ; /* 0x0000001310137221 */
/* 0x008fc80000000000 */
/*0440*/ FADD R22, R19, R22 ; /* 0x0000001613167221 */
/* 0x020fc80000000000 */
/*0450*/ FADD R23, R22, R23 ; /* 0x0000001716177221 */
/* 0x000fc80000000000 */
/*0460*/ FADD R24, R23, R24 ; /* 0x0000001817187221 */
/* 0x000fc80000000000 */
/*0470*/ FADD R25, R24, R25 ; /* 0x0000001918197221 */
/* 0x000fc80000000000 */
/*0480*/ FADD R25, R25, R28 ; /* 0x0000001c19197221 */
/* 0x000fc80000000000 */
/*0490*/ FADD R6, R25, R6 ; /* 0x0000000619067221 */
/* 0x000fc80000000000 */
/*04a0*/ FADD R29, R6, R29 ; /* 0x0000001d061d7221 */
/* 0x000fc80000000000 */
/*04b0*/ FADD R29, R29, R2 ; /* 0x000000021d1d7221 */
/* 0x000fc80000000000 */
/*04c0*/ FADD R29, R29, R4 ; /* 0x000000041d1d7221 */
/* 0x000fc80000000000 */
/*04d0*/ FADD R29, R29, R12 ; /* 0x0000000c1d1d7221 */
/* 0x010fc80000000000 */
/*04e0*/ FADD R29, R29, R14 ; /* 0x0000000e1d1d7221 */
/* 0x000fc80000000000 */
/*04f0*/ FADD R26, R29, R26 ; /* 0x0000001a1d1a7221 */
/* 0x000fc80000000000 */
/*0500*/ FADD R26, R26, R7 ; /* 0x000000071a1a7221 */
/* 0x000fe40000000000 */
/*0510*/ IMAD.WIDE R4, R17, 0x4, R8 ; /* 0x0000000411047825 */
/* 0x000fc800078e0208 */
/*0520*/ FADD R21, R26, R3 ; /* 0x000000031a157221 */
/* 0x000fe20000000000 */
/*0530*/ @P1 BRA 0x200 ; /* 0xfffffcc000001947 */
/* 0x000fea000383ffff */
/*0540*/ ISETP.GT.AND P1, PT, R20, 0x4, PT ; /* 0x000000041400780c */
/* 0x000fda0003f24270 */
/*0550*/ @!P1 BRA 0x710 ; /* 0x000001b000009947 */
/* 0x000fea0003800000 */
/*0560*/ IMAD.WIDE R6, R17.reuse, 0x4, R4 ; /* 0x0000000411067825 */
/* 0x040fe400078e0204 */
/*0570*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x0000a8000c1e1900 */
/*0580*/ IMAD.WIDE R8, R17.reuse, 0x4, R6 ; /* 0x0000000411087825 */
/* 0x040fe400078e0206 */
/*0590*/ LDG.E R7, [R6.64] ; /* 0x0000000606077981 */
/* 0x000ee8000c1e1900 */
/*05a0*/ IMAD.WIDE R10, R17, 0x4, R8 ; /* 0x00000004110a7825 */
/* 0x000fc400078e0208 */
/*05b0*/ LDG.E R9, [R8.64] ; /* 0x0000000608097981 */
/* 0x000f28000c1e1900 */
/*05c0*/ IMAD.WIDE R12, R17.reuse, 0x4, R10 ; /* 0x00000004110c7825 */
/* 0x040fe400078e020a */
/*05d0*/ LDG.E R11, [R10.64] ; /* 0x000000060a0b7981 */
/* 0x000f68000c1e1900 */
/*05e0*/ IMAD.WIDE R14, R17, 0x4, R12 ; /* 0x00000004110e7825 */
/* 0x000fc400078e020c */
/*05f0*/ LDG.E R13, [R12.64] ; /* 0x000000060c0d7981 */
/* 0x000f68000c1e1900 */
/*0600*/ IMAD.WIDE R22, R17.reuse, 0x4, R14 ; /* 0x0000000411167825 */
/* 0x040fe400078e020e */
/*0610*/ LDG.E R15, [R14.64] ; /* 0x000000060e0f7981 */
/* 0x000f68000c1e1900 */
/*0620*/ IMAD.WIDE R2, R17, 0x4, R22 ; /* 0x0000000411027825 */
/* 0x000fc400078e0216 */
/*0630*/ LDG.E R23, [R22.64] ; /* 0x0000000616177981 */
/* 0x000f68000c1e1900 */
/*0640*/ LDG.E R5, [R2.64] ; /* 0x0000000602057981 */
/* 0x001f62000c1e1900 */
/*0650*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0660*/ IADD3 R20, R20, -0x8, RZ ; /* 0xfffffff814147810 */
/* 0x000fe20007ffe0ff */
/*0670*/ UIADD3 UR4, UR4, 0x8, URZ ; /* 0x0000000804047890 */
/* 0x000fe2000fffe03f */
/*0680*/ FADD R4, R21, R4 ; /* 0x0000000415047221 */
/* 0x004fc80000000000 */
/*0690*/ FADD R4, R4, R7 ; /* 0x0000000704047221 */
/* 0x008fc80000000000 */
/*06a0*/ FADD R4, R4, R9 ; /* 0x0000000904047221 */
/* 0x010fc80000000000 */
/*06b0*/ FADD R4, R4, R11 ; /* 0x0000000b04047221 */
/* 0x020fc80000000000 */
/*06c0*/ FADD R4, R4, R13 ; /* 0x0000000d04047221 */
/* 0x000fc80000000000 */
/*06d0*/ FADD R4, R4, R15 ; /* 0x0000000f04047221 */
/* 0x000fc80000000000 */
/*06e0*/ FADD R4, R4, R23 ; /* 0x0000001704047221 */
/* 0x000fc80000000000 */
/*06f0*/ FADD R21, R4, R5 ; /* 0x0000000504157221 */
/* 0x000fe40000000000 */
/*0700*/ IMAD.WIDE R4, R17, 0x4, R2 ; /* 0x0000000411047825 */
/* 0x000fc800078e0202 */
/*0710*/ ISETP.NE.OR P0, PT, R20, RZ, P0 ; /* 0x000000ff1400720c */
/* 0x000fda0000705670 */
/*0720*/ @!P0 BRA 0x830 ; /* 0x0000010000008947 */
/* 0x000fea0003800000 */
/*0730*/ IMAD.WIDE R2, R17.reuse, 0x4, R4 ; /* 0x0000000411027825 */
/* 0x040fe400078e0204 */
/*0740*/ LDG.E R4, [R4.64] ; /* 0x0000000604047981 */
/* 0x000ea8000c1e1900 */
/*0750*/ IMAD.WIDE R6, R17.reuse, 0x4, R2 ; /* 0x0000000411067825 */
/* 0x040fe400078e0202 */
/*0760*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ee8000c1e1900 */
/*0770*/ IMAD.WIDE R8, R17, 0x4, R6 ; /* 0x0000000411087825 */
/* 0x000fe200078e0206 */
/*0780*/ LDG.E R10, [R6.64] ; /* 0x00000006060a7981 */
/* 0x000f28000c1e1900 */
/*0790*/ LDG.E R12, [R8.64] ; /* 0x00000006080c7981 */
/* 0x000f62000c1e1900 */
/*07a0*/ IADD3 R20, R20, -0x4, RZ ; /* 0xfffffffc14147810 */
/* 0x000fe20007ffe0ff */
/*07b0*/ UIADD3 UR4, UR4, 0x4, URZ ; /* 0x0000000404047890 */
/* 0x000fc6000fffe03f */
/*07c0*/ ISETP.NE.AND P0, PT, R20, RZ, PT ; /* 0x000000ff1400720c */
/* 0x000fe20003f05270 */
/*07d0*/ FADD R21, R4, R21 ; /* 0x0000001504157221 */
/* 0x004fe40000000000 */
/*07e0*/ IMAD.WIDE R4, R17, 0x4, R8 ; /* 0x0000000411047825 */
/* 0x000fc800078e0208 */
/*07f0*/ FADD R21, R21, R2 ; /* 0x0000000215157221 */
/* 0x008fc80000000000 */
/*0800*/ FADD R21, R21, R10 ; /* 0x0000000a15157221 */
/* 0x010fc80000000000 */
/*0810*/ FADD R21, R21, R12 ; /* 0x0000000c15157221 */
/* 0x020fe20000000000 */
/*0820*/ @P0 BRA 0x730 ; /* 0xffffff0000000947 */
/* 0x000fea000383ffff */
/*0830*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fda0003f05270 */
/*0840*/ @!P0 BRA 0x8e0 ; /* 0x0000009000008947 */
/* 0x000fea0003800000 */
/*0850*/ HFMA2.MMA R3, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff037435 */
/* 0x000fe200000001ff */
/*0860*/ IMAD R2, R17, UR4, R0 ; /* 0x0000000411027c24 */
/* 0x000fd2000f8e0200 */
/*0870*/ IMAD.WIDE R2, R2, R3, c[0x0][0x160] ; /* 0x0000580002027625 */
/* 0x000fca00078e0203 */
/*0880*/ LDG.E R4, [R2.64] ; /* 0x0000000602047981 */
/* 0x0000a2000c1e1900 */
/*0890*/ IADD3 R18, R18, -0x1, RZ ; /* 0xffffffff12127810 */
/* 0x000fc80007ffe0ff */
/*08a0*/ ISETP.NE.AND P0, PT, R18, RZ, PT ; /* 0x000000ff1200720c */
/* 0x000fe20003f05270 */
/*08b0*/ IMAD.WIDE R2, R17, 0x4, R2 ; /* 0x0000000411027825 */
/* 0x001fc800078e0202 */
/*08c0*/ FADD R21, R4, R21 ; /* 0x0000001504157221 */
/* 0x004fd00000000000 */
/*08d0*/ @P0 BRA 0x880 ; /* 0xffffffa000000947 */
/* 0x000fea000383ffff */
/*08e0*/ MOV R5, 0x4 ; /* 0x0000000400057802 */
/* 0x000fca0000000f00 */
/*08f0*/ IMAD.WIDE R2, R0, R5, c[0x0][0x168] ; /* 0x00005a0000027625 */
/* 0x000fcc00078e0205 */
/*0900*/ LDG.E R2, [R2.64] ; /* 0x0000000602027981 */
/* 0x000ea2000c1e1900 */
/*0910*/ IMAD.WIDE R4, R0, R5, c[0x0][0x170] ; /* 0x00005c0000047625 */
/* 0x000fc800078e0205 */
/*0920*/ FADD R21, R2, R21 ; /* 0x0000001502157221 */
/* 0x004fca0000000000 */
/*0930*/ STG.E [R4.64], R21 ; /* 0x0000001504007986 */
/* 0x000fe2000c101906 */
/*0940*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0950*/ BRA 0x950; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0960*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0970*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0980*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0990*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*09f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z11matVectMultPfS_S_i
.globl _Z11matVectMultPfS_S_i
.p2align 8
.type _Z11matVectMultPfS_S_i,@function
_Z11matVectMultPfS_S_i:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x2c
s_load_b32 s4, s[0:1], 0x18
v_bfe_u32 v2, v0, 10, 10
v_and_b32_e32 v3, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s3, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
v_mad_u64_u32 v[1:2], null, s14, s2, v[3:4]
s_mov_b32 s2, exec_lo
v_max_i32_e32 v2, v0, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_i32_e64 s4, v2
s_cbranch_execz .LBB0_6
s_cmp_lt_i32 s4, 1
s_cbranch_scc1 .LBB0_4
s_load_b64 s[2:3], s[0:1], 0x0
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v2, v0
.LBB0_3:
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
v_ashrrev_i32_e32 v3, 31, v2
s_add_i32 s4, s4, -1
s_cmp_eq_u32 s4, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[5:6], 2, v[2:3]
v_add_nc_u32_e32 v2, v2, v1
s_waitcnt lgkmcnt(0)
v_add_co_u32 v5, vcc_lo, s2, v5
s_delay_alu instid0(VALU_DEP_3)
v_add_co_ci_u32_e32 v6, vcc_lo, s3, v6, vcc_lo
global_load_b32 v3, v[5:6], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v4, v4, v3
s_cbranch_scc0 .LBB0_3
s_branch .LBB0_5
.LBB0_4:
v_mov_b32_e32 v4, 0
.LBB0_5:
s_load_b128 s[0:3], s[0:1], 0x8
v_ashrrev_i32_e32 v1, 31, v0
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[0:1]
s_waitcnt lgkmcnt(0)
v_add_co_u32 v2, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
v_add_co_u32 v0, vcc_lo, s2, v0
v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
global_load_b32 v2, v[2:3], off
s_waitcnt vmcnt(0)
v_add_f32_e32 v2, v4, v2
global_store_b32 v[0:1], v2, off
.LBB0_6:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z11matVectMultPfS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z11matVectMultPfS_S_i, .Lfunc_end0-_Z11matVectMultPfS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z11matVectMultPfS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z11matVectMultPfS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0012f94f_00000000-6_matrix_vect_mult.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2060:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i
.type _Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i, @function
_Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i:
.LFB2082:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z11matVectMultPfS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2082:
.size _Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i, .-_Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i
.globl _Z11matVectMultPfS_S_i
.type _Z11matVectMultPfS_S_i, @function
_Z11matVectMultPfS_S_i:
.LFB2083:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2083:
.size _Z11matVectMultPfS_S_i, .-_Z11matVectMultPfS_S_i
.globl main
.type main, @function
main:
.LFB2057:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
subq $64, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $2048, %edi
call malloc@PLT
movq %rax, %r12
movl $1048576, %edi
call malloc@PLT
movq %rax, %rbp
movl $2048, %edi
call malloc@PLT
movq %rax, %rbx
movl $0, %eax
.L12:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, (%rbx,%rax,4)
addq $1, %rax
cmpq $512, %rax
jne .L12
movl $0, %eax
.L13:
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
movss %xmm0, 0(%rbp,%rax,4)
addq $1, %rax
cmpq $262144, %rax
jne .L13
leaq 8(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
leaq 16(%rsp), %rdi
movl $1048576, %esi
call cudaMalloc@PLT
leaq 24(%rsp), %rdi
movl $2048, %esi
call cudaMalloc@PLT
movl $1, %ecx
movl $2048, %edx
movq %rbx, %rsi
movq 24(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movl $1048576, %edx
movq %rbp, %rsi
movq 16(%rsp), %rdi
call cudaMemcpy@PLT
movl $32, 32(%rsp)
movl $32, 36(%rsp)
movl $8192, 44(%rsp)
movl $16, 48(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 32(%rsp), %rdx
movl $1, %ecx
movq 44(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L19
.L14:
movl $2, %ecx
movl $2048, %edx
movq 8(%rsp), %rsi
movq %r12, %rdi
call cudaMemcpy@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L20
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %rbp
.cfi_def_cfa_offset 16
popq %r12
.cfi_def_cfa_offset 8
ret
.L19:
.cfi_restore_state
movl $512, %ecx
movq 8(%rsp), %rdx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z36__device_stub__Z11matVectMultPfS_S_iPfS_S_i
jmp .L14
.L20:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size main, .-main
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z11matVectMultPfS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z11matVectMultPfS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "matrix_vect_mult.hip"
.globl _Z26__device_stub__matVectMultPfS_S_i # -- Begin function _Z26__device_stub__matVectMultPfS_S_i
.p2align 4, 0x90
.type _Z26__device_stub__matVectMultPfS_S_i,@function
_Z26__device_stub__matVectMultPfS_S_i: # @_Z26__device_stub__matVectMultPfS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z11matVectMultPfS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end0:
.size _Z26__device_stub__matVectMultPfS_S_i, .Lfunc_end0-_Z26__device_stub__matVectMultPfS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $144, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %rbx
movl $1048576, %edi # imm = 0x100000
callq malloc
movq %rax, %r14
movl $2048, %edi # imm = 0x800
callq malloc
movq %rax, %r15
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_1: # =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r15,%rax,4)
incq %rax
cmpq $512, %rax # imm = 0x200
jne .LBB1_1
# %bb.2: # %.preheader.preheader
xorl %eax, %eax
.p2align 4, 0x90
.LBB1_3: # %.preheader
# =>This Inner Loop Header: Depth=1
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
movss %xmm0, (%r14,%rax,4)
incq %rax
cmpq $262144, %rax # imm = 0x40000
jne .LBB1_3
# %bb.4:
leaq 24(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
leaq 16(%rsp), %rdi
movl $1048576, %esi # imm = 0x100000
callq hipMalloc
leaq 8(%rsp), %rdi
movl $2048, %esi # imm = 0x800
callq hipMalloc
movq 8(%rsp), %rdi
movl $2048, %edx # imm = 0x800
movq %r15, %rsi
movl $1, %ecx
callq hipMemcpy
movq 16(%rsp), %rdi
movl $1048576, %edx # imm = 0x100000
movq %r14, %rsi
movl $1, %ecx
callq hipMemcpy
movabsq $68719484928, %rdi # imm = 0x1000002000
movabsq $137438953504, %rdx # imm = 0x2000000020
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_6
# %bb.5:
movq 16(%rsp), %rax
movq 8(%rsp), %rcx
movq 24(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $512, 36(%rsp) # imm = 0x200
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 36(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z11matVectMultPfS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_6:
movq 24(%rsp), %rsi
movl $2048, %edx # imm = 0x800
movq %rbx, %rdi
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
movq 24(%rsp), %rdi
callq hipFree
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size main, .Lfunc_end1-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB2_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB2_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z11matVectMultPfS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end2:
.size __hip_module_ctor, .Lfunc_end2-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB3_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB3_2:
retq
.Lfunc_end3:
.size __hip_module_dtor, .Lfunc_end3-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z11matVectMultPfS_S_i,@object # @_Z11matVectMultPfS_S_i
.section .rodata,"a",@progbits
.globl _Z11matVectMultPfS_S_i
.p2align 3, 0x0
_Z11matVectMultPfS_S_i:
.quad _Z26__device_stub__matVectMultPfS_S_i
.size _Z11matVectMultPfS_S_i, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z11matVectMultPfS_S_i"
.size .L__unnamed_1, 23
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z26__device_stub__matVectMultPfS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z11matVectMultPfS_S_i
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "cuda_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cstdio>
#include <chrono>
typedef std::chrono::high_resolution_clock Clock;
#define ITER 65535
// Version CPU de la función suma de vectores
void vector_add_cpu(int *a, int *b, int *c, int n) {
int i;
// Add the vector elements a and b to the vector c
for (i = 0; i < n; ++i) {
c[i] = a[i] + b[i];
}
}
// Versión GPU de la función suma de vectores
__global__ void vector_add_gpu(int *gpu_a, int *gpu_b, int *gpu_c, int n) {
int i = threadIdx.x;
// No es necesario el loop for por que el runtime de CUDA
// maneja estos hilos ITER veces
gpu_c[i] = gpu_a[i] + gpu_b[i];
}
int main() {
int *a, *b, *c;
int *gpu_a, *gpu_b, *gpu_c;
a = (int *)malloc(ITER * sizeof(int));
b = (int *)malloc(ITER * sizeof(int));
c = (int *)malloc(ITER * sizeof(int));
// Necesitamos variables accesibles en CUDA,
// para eso cudaMallocManaged nos las provee
cudaMallocManaged(&gpu_a, ITER * sizeof(int));
cudaMallocManaged(&gpu_b, ITER * sizeof(int));
cudaMallocManaged(&gpu_c, ITER * sizeof(int));
for (int i = 0; i < ITER; ++i) {
a[i] = i;
b[i] = i;
c[i] = i;
}
// Llama a la versión CPU y la temporiza
auto cpu_start = Clock::now();
vector_add_cpu(a, b, c, ITER);
auto cpu_end = Clock::now();
std::cout << "vector_add_cpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(cpu_end - cpu_start).count()
<< " nanoseconds.\n";
// Llama a la versión GPU y la temporiza
// Los triples <> es una extensión del runtime CUDA que permite
// que los parametros de una llamada al kernel CUDA sean pasados
// En este ejemplo estamos pasando un thread block con ITER threads
auto gpu_start = Clock::now();
vector_add_gpu <<<1, ITER>>> (gpu_a, gpu_b, gpu_c, ITER);
cudaDeviceSynchronize();
auto gpu_end = Clock::now();
std::cout << "vector_add_gpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(gpu_end - gpu_start).count()
<< " nanoseconds.\n";
// Libere la memoria basada en la función GPU allocations
cudaFree(a);
cudaFree(b);
cudaFree(c);
// Libere la memoria basada en la función CPU allocations
free(a);
free(b);
free(c);
return 0;
} | code for sm_80
Function : _Z14vector_add_gpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "cuda_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cstdio>
#include <chrono>
typedef std::chrono::high_resolution_clock Clock;
#define ITER 65535
// Version CPU de la función suma de vectores
void vector_add_cpu(int *a, int *b, int *c, int n) {
int i;
// Add the vector elements a and b to the vector c
for (i = 0; i < n; ++i) {
c[i] = a[i] + b[i];
}
}
// Versión GPU de la función suma de vectores
__global__ void vector_add_gpu(int *gpu_a, int *gpu_b, int *gpu_c, int n) {
int i = threadIdx.x;
// No es necesario el loop for por que el runtime de CUDA
// maneja estos hilos ITER veces
gpu_c[i] = gpu_a[i] + gpu_b[i];
}
int main() {
int *a, *b, *c;
int *gpu_a, *gpu_b, *gpu_c;
a = (int *)malloc(ITER * sizeof(int));
b = (int *)malloc(ITER * sizeof(int));
c = (int *)malloc(ITER * sizeof(int));
// Necesitamos variables accesibles en CUDA,
// para eso cudaMallocManaged nos las provee
cudaMallocManaged(&gpu_a, ITER * sizeof(int));
cudaMallocManaged(&gpu_b, ITER * sizeof(int));
cudaMallocManaged(&gpu_c, ITER * sizeof(int));
for (int i = 0; i < ITER; ++i) {
a[i] = i;
b[i] = i;
c[i] = i;
}
// Llama a la versión CPU y la temporiza
auto cpu_start = Clock::now();
vector_add_cpu(a, b, c, ITER);
auto cpu_end = Clock::now();
std::cout << "vector_add_cpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(cpu_end - cpu_start).count()
<< " nanoseconds.\n";
// Llama a la versión GPU y la temporiza
// Los triples <> es una extensión del runtime CUDA que permite
// que los parametros de una llamada al kernel CUDA sean pasados
// En este ejemplo estamos pasando un thread block con ITER threads
auto gpu_start = Clock::now();
vector_add_gpu <<<1, ITER>>> (gpu_a, gpu_b, gpu_c, ITER);
cudaDeviceSynchronize();
auto gpu_end = Clock::now();
std::cout << "vector_add_gpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(gpu_end - gpu_start).count()
<< " nanoseconds.\n";
// Libere la memoria basada en la función GPU allocations
cudaFree(a);
cudaFree(b);
cudaFree(c);
// Libere la memoria basada en la función CPU allocations
free(a);
free(b);
free(c);
return 0;
} | .file "tmpxft_0011e3f8_00000000-6_sumVectors.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14vector_add_cpuPiS_S_i
.type _Z14vector_add_cpuPiS_S_i, @function
_Z14vector_add_cpuPiS_S_i:
.LFB3768:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3768:
.size _Z14vector_add_cpuPiS_S_i, .-_Z14vector_add_cpuPiS_S_i
.globl _Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i
.type _Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i, @function
_Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i:
.LFB3796:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14vector_add_gpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i, .-_Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i
.globl _Z14vector_add_gpuPiS_S_i
.type _Z14vector_add_gpuPiS_S_i, @function
_Z14vector_add_gpuPiS_S_i:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z14vector_add_gpuPiS_S_i, .-_Z14vector_add_gpuPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vector_add_cpu: "
.LC1:
.string " nanoseconds.\n"
.LC2:
.string "vector_add_gpu: "
.text
.globl main
.type main, @function
main:
.LFB3769:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $262140, %edi
call malloc@PLT
movq %rax, %r12
movl $262140, %edi
call malloc@PLT
movq %rax, %rbp
movl $262140, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1, %edx
movl $262140, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $262140, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $262140, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L16:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $65535, %rax
jne .L16
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
movl $65535, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z14vector_add_cpuPiS_S_i
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
subq %r14, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
movl $65535, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
subq %r14, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r12, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $65535, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3769:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z14vector_add_gpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14vector_add_gpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "cuda_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cstdio>
#include <chrono>
typedef std::chrono::high_resolution_clock Clock;
#define ITER 65535
// Version CPU de la función suma de vectores
void vector_add_cpu(int *a, int *b, int *c, int n) {
int i;
// Add the vector elements a and b to the vector c
for (i = 0; i < n; ++i) {
c[i] = a[i] + b[i];
}
}
// Versión GPU de la función suma de vectores
__global__ void vector_add_gpu(int *gpu_a, int *gpu_b, int *gpu_c, int n) {
int i = threadIdx.x;
// No es necesario el loop for por que el runtime de CUDA
// maneja estos hilos ITER veces
gpu_c[i] = gpu_a[i] + gpu_b[i];
}
int main() {
int *a, *b, *c;
int *gpu_a, *gpu_b, *gpu_c;
a = (int *)malloc(ITER * sizeof(int));
b = (int *)malloc(ITER * sizeof(int));
c = (int *)malloc(ITER * sizeof(int));
// Necesitamos variables accesibles en CUDA,
// para eso cudaMallocManaged nos las provee
cudaMallocManaged(&gpu_a, ITER * sizeof(int));
cudaMallocManaged(&gpu_b, ITER * sizeof(int));
cudaMallocManaged(&gpu_c, ITER * sizeof(int));
for (int i = 0; i < ITER; ++i) {
a[i] = i;
b[i] = i;
c[i] = i;
}
// Llama a la versión CPU y la temporiza
auto cpu_start = Clock::now();
vector_add_cpu(a, b, c, ITER);
auto cpu_end = Clock::now();
std::cout << "vector_add_cpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(cpu_end - cpu_start).count()
<< " nanoseconds.\n";
// Llama a la versión GPU y la temporiza
// Los triples <> es una extensión del runtime CUDA que permite
// que los parametros de una llamada al kernel CUDA sean pasados
// En este ejemplo estamos pasando un thread block con ITER threads
auto gpu_start = Clock::now();
vector_add_gpu <<<1, ITER>>> (gpu_a, gpu_b, gpu_c, ITER);
cudaDeviceSynchronize();
auto gpu_end = Clock::now();
std::cout << "vector_add_gpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(gpu_end - gpu_start).count()
<< " nanoseconds.\n";
// Libere la memoria basada en la función GPU allocations
cudaFree(a);
cudaFree(b);
cudaFree(c);
// Libere la memoria basada en la función CPU allocations
free(a);
free(b);
free(c);
return 0;
} | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cstdio>
#include <chrono>
typedef std::chrono::high_resolution_clock Clock;
#define ITER 65535
// Version CPU de la función suma de vectores
void vector_add_cpu(int *a, int *b, int *c, int n) {
int i;
// Add the vector elements a and b to the vector c
for (i = 0; i < n; ++i) {
c[i] = a[i] + b[i];
}
}
// Versión GPU de la función suma de vectores
__global__ void vector_add_gpu(int *gpu_a, int *gpu_b, int *gpu_c, int n) {
int i = threadIdx.x;
// No es necesario el loop for por que el runtime de CUDA
// maneja estos hilos ITER veces
gpu_c[i] = gpu_a[i] + gpu_b[i];
}
int main() {
int *a, *b, *c;
int *gpu_a, *gpu_b, *gpu_c;
a = (int *)malloc(ITER * sizeof(int));
b = (int *)malloc(ITER * sizeof(int));
c = (int *)malloc(ITER * sizeof(int));
// Necesitamos variables accesibles en CUDA,
// para eso cudaMallocManaged nos las provee
hipMallocManaged(&gpu_a, ITER * sizeof(int));
hipMallocManaged(&gpu_b, ITER * sizeof(int));
hipMallocManaged(&gpu_c, ITER * sizeof(int));
for (int i = 0; i < ITER; ++i) {
a[i] = i;
b[i] = i;
c[i] = i;
}
// Llama a la versión CPU y la temporiza
auto cpu_start = Clock::now();
vector_add_cpu(a, b, c, ITER);
auto cpu_end = Clock::now();
std::cout << "vector_add_cpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(cpu_end - cpu_start).count()
<< " nanoseconds.\n";
// Llama a la versión GPU y la temporiza
// Los triples <> es una extensión del runtime CUDA que permite
// que los parametros de una llamada al kernel CUDA sean pasados
// En este ejemplo estamos pasando un thread block con ITER threads
auto gpu_start = Clock::now();
vector_add_gpu <<<1, ITER>>> (gpu_a, gpu_b, gpu_c, ITER);
hipDeviceSynchronize();
auto gpu_end = Clock::now();
std::cout << "vector_add_gpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(gpu_end - gpu_start).count()
<< " nanoseconds.\n";
// Libere la memoria basada en la función GPU allocations
hipFree(a);
hipFree(b);
hipFree(c);
// Libere la memoria basada en la función CPU allocations
free(a);
free(b);
free(c);
return 0;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cstdio>
#include <chrono>
typedef std::chrono::high_resolution_clock Clock;
#define ITER 65535
// Version CPU de la función suma de vectores
void vector_add_cpu(int *a, int *b, int *c, int n) {
int i;
// Add the vector elements a and b to the vector c
for (i = 0; i < n; ++i) {
c[i] = a[i] + b[i];
}
}
// Versión GPU de la función suma de vectores
__global__ void vector_add_gpu(int *gpu_a, int *gpu_b, int *gpu_c, int n) {
int i = threadIdx.x;
// No es necesario el loop for por que el runtime de CUDA
// maneja estos hilos ITER veces
gpu_c[i] = gpu_a[i] + gpu_b[i];
}
int main() {
int *a, *b, *c;
int *gpu_a, *gpu_b, *gpu_c;
a = (int *)malloc(ITER * sizeof(int));
b = (int *)malloc(ITER * sizeof(int));
c = (int *)malloc(ITER * sizeof(int));
// Necesitamos variables accesibles en CUDA,
// para eso cudaMallocManaged nos las provee
hipMallocManaged(&gpu_a, ITER * sizeof(int));
hipMallocManaged(&gpu_b, ITER * sizeof(int));
hipMallocManaged(&gpu_c, ITER * sizeof(int));
for (int i = 0; i < ITER; ++i) {
a[i] = i;
b[i] = i;
c[i] = i;
}
// Llama a la versión CPU y la temporiza
auto cpu_start = Clock::now();
vector_add_cpu(a, b, c, ITER);
auto cpu_end = Clock::now();
std::cout << "vector_add_cpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(cpu_end - cpu_start).count()
<< " nanoseconds.\n";
// Llama a la versión GPU y la temporiza
// Los triples <> es una extensión del runtime CUDA que permite
// que los parametros de una llamada al kernel CUDA sean pasados
// En este ejemplo estamos pasando un thread block con ITER threads
auto gpu_start = Clock::now();
vector_add_gpu <<<1, ITER>>> (gpu_a, gpu_b, gpu_c, ITER);
hipDeviceSynchronize();
auto gpu_end = Clock::now();
std::cout << "vector_add_gpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(gpu_end - gpu_start).count()
<< " nanoseconds.\n";
// Libere la memoria basada en la función GPU allocations
hipFree(a);
hipFree(b);
hipFree(c);
// Libere la memoria basada en la función CPU allocations
free(a);
free(b);
free(c);
return 0;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14vector_add_gpuPiS_S_i
.globl _Z14vector_add_gpuPiS_S_i
.p2align 8
.type _Z14vector_add_gpuPiS_S_i,@function
_Z14vector_add_gpuPiS_S_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14vector_add_gpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14vector_add_gpuPiS_S_i, .Lfunc_end0-_Z14vector_add_gpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14vector_add_gpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14vector_add_gpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include "hip/hip_runtime.h"
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <cstdio>
#include <chrono>
typedef std::chrono::high_resolution_clock Clock;
#define ITER 65535
// Version CPU de la función suma de vectores
void vector_add_cpu(int *a, int *b, int *c, int n) {
int i;
// Add the vector elements a and b to the vector c
for (i = 0; i < n; ++i) {
c[i] = a[i] + b[i];
}
}
// Versión GPU de la función suma de vectores
__global__ void vector_add_gpu(int *gpu_a, int *gpu_b, int *gpu_c, int n) {
int i = threadIdx.x;
// No es necesario el loop for por que el runtime de CUDA
// maneja estos hilos ITER veces
gpu_c[i] = gpu_a[i] + gpu_b[i];
}
int main() {
int *a, *b, *c;
int *gpu_a, *gpu_b, *gpu_c;
a = (int *)malloc(ITER * sizeof(int));
b = (int *)malloc(ITER * sizeof(int));
c = (int *)malloc(ITER * sizeof(int));
// Necesitamos variables accesibles en CUDA,
// para eso cudaMallocManaged nos las provee
hipMallocManaged(&gpu_a, ITER * sizeof(int));
hipMallocManaged(&gpu_b, ITER * sizeof(int));
hipMallocManaged(&gpu_c, ITER * sizeof(int));
for (int i = 0; i < ITER; ++i) {
a[i] = i;
b[i] = i;
c[i] = i;
}
// Llama a la versión CPU y la temporiza
auto cpu_start = Clock::now();
vector_add_cpu(a, b, c, ITER);
auto cpu_end = Clock::now();
std::cout << "vector_add_cpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(cpu_end - cpu_start).count()
<< " nanoseconds.\n";
// Llama a la versión GPU y la temporiza
// Los triples <> es una extensión del runtime CUDA que permite
// que los parametros de una llamada al kernel CUDA sean pasados
// En este ejemplo estamos pasando un thread block con ITER threads
auto gpu_start = Clock::now();
vector_add_gpu <<<1, ITER>>> (gpu_a, gpu_b, gpu_c, ITER);
hipDeviceSynchronize();
auto gpu_end = Clock::now();
std::cout << "vector_add_gpu: "
<< std::chrono::duration_cast<std::chrono::nanoseconds>(gpu_end - gpu_start).count()
<< " nanoseconds.\n";
// Libere la memoria basada en la función GPU allocations
hipFree(a);
hipFree(b);
hipFree(c);
// Libere la memoria basada en la función CPU allocations
free(a);
free(b);
free(c);
return 0;
} | .text
.file "sumVectors.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14vector_add_cpuPiS_S_i # -- Begin function _Z14vector_add_cpuPiS_S_i
.p2align 4, 0x90
.type _Z14vector_add_cpuPiS_S_i,@function
_Z14vector_add_cpuPiS_S_i: # @_Z14vector_add_cpuPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z14vector_add_cpuPiS_S_i, .Lfunc_end0-_Z14vector_add_cpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__vector_add_gpuPiS_S_i # -- Begin function _Z29__device_stub__vector_add_gpuPiS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__vector_add_gpuPiS_S_i,@function
_Z29__device_stub__vector_add_gpuPiS_S_i: # @_Z29__device_stub__vector_add_gpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14vector_add_gpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z29__device_stub__vector_add_gpuPiS_S_i, .Lfunc_end1-_Z29__device_stub__vector_add_gpuPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $262140, %edi # imm = 0x3FFFC
callq malloc
movq %rax, %rbx
movl $262140, %edi # imm = 0x3FFFC
callq malloc
movq %rax, %r14
movl $262140, %edi # imm = 0x3FFFC
callq malloc
movq %rax, %r15
leaq 32(%rsp), %rdi
movl $262140, %esi # imm = 0x3FFFC
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $262140, %esi # imm = 0x3FFFC
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $262140, %esi # imm = 0x3FFFC
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
movl %eax, (%r14,%rax,4)
movl %eax, (%r15,%rax,4)
incq %rax
cmpq $65535, %rax # imm = 0xFFFF
jne .LBB2_1
# %bb.2:
xorl %r13d, %r13d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %eax
addl (%rbx,%r13,4), %eax
movl %eax, (%r15,%r13,4)
incq %r13
cmpq $65535, %r13 # imm = 0xFFFF
jne .LBB2_3
# %bb.4: # %_Z14vector_add_cpuPiS_S_i.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r13
movl $_ZSt4cout, %edi
movq %r13, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.1, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 65534(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $65535, 12(%rsp) # imm = 0xFFFF
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14vector_add_gpuPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r13
movl $_ZSt4cout, %edi
movq %r13, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.1, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq %r15, %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14vector_add_gpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14vector_add_gpuPiS_S_i,@object # @_Z14vector_add_gpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z14vector_add_gpuPiS_S_i
.p2align 3, 0x0
_Z14vector_add_gpuPiS_S_i:
.quad _Z29__device_stub__vector_add_gpuPiS_S_i
.size _Z14vector_add_gpuPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "vector_add_cpu: "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " nanoseconds.\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "vector_add_gpu: "
.size .L.str.2, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14vector_add_gpuPiS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__vector_add_gpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14vector_add_gpuPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z14vector_add_gpuPiS_S_i
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R6, SR_TID.X ; /* 0x0000000000067919 */
/* 0x000e220000002100 */
/*0020*/ HFMA2.MMA R7, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff077435 */
/* 0x000fe200000001ff */
/*0030*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fd20000000a00 */
/*0040*/ IMAD.WIDE R2, R6, R7, c[0x0][0x160] ; /* 0x0000580006027625 */
/* 0x001fc800078e0207 */
/*0050*/ IMAD.WIDE R4, R6.reuse, R7.reuse, c[0x0][0x168] ; /* 0x00005a0006047625 */
/* 0x0c0fe400078e0207 */
/*0060*/ LDG.E R2, [R2.64] ; /* 0x0000000402027981 */
/* 0x000ea8000c1e1900 */
/*0070*/ LDG.E R5, [R4.64] ; /* 0x0000000404057981 */
/* 0x000ea2000c1e1900 */
/*0080*/ IMAD.WIDE R6, R6, R7, c[0x0][0x170] ; /* 0x00005c0006067625 */
/* 0x000fe200078e0207 */
/*0090*/ IADD3 R9, R2, R5, RZ ; /* 0x0000000502097210 */
/* 0x004fca0007ffe0ff */
/*00a0*/ STG.E [R6.64], R9 ; /* 0x0000000906007986 */
/* 0x000fe2000c101904 */
/*00b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00c0*/ BRA 0xc0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*00d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*00f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z14vector_add_gpuPiS_S_i
.globl _Z14vector_add_gpuPiS_S_i
.p2align 8
.type _Z14vector_add_gpuPiS_S_i,@function
_Z14vector_add_gpuPiS_S_i:
s_load_b128 s[4:7], s[0:1], 0x0
v_lshlrev_b32_e32 v0, 2, v0
s_load_b64 s[0:1], s[0:1], 0x10
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b32 v1, v0, s[4:5]
global_load_b32 v2, v0, s[6:7]
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v1, v2, v1
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z14vector_add_gpuPiS_S_i
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 28
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 8
.amdhsa_reserve_vcc 0
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z14vector_add_gpuPiS_S_i, .Lfunc_end0-_Z14vector_add_gpuPiS_S_i
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 28
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z14vector_add_gpuPiS_S_i
.private_segment_fixed_size: 0
.sgpr_count: 8
.sgpr_spill_count: 0
.symbol: _Z14vector_add_gpuPiS_S_i.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011e3f8_00000000-6_sumVectors.cudafe1.cpp"
.text
#APP
.globl _ZSt21ios_base_library_initv
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3774:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3774:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z14vector_add_cpuPiS_S_i
.type _Z14vector_add_cpuPiS_S_i, @function
_Z14vector_add_cpuPiS_S_i:
.LFB3768:
.cfi_startproc
endbr64
testl %ecx, %ecx
jle .L3
movslq %ecx, %rcx
leaq 0(,%rcx,4), %r8
movl $0, %eax
.L5:
movl (%rsi,%rax), %ecx
addl (%rdi,%rax), %ecx
movl %ecx, (%rdx,%rax)
addq $4, %rax
cmpq %r8, %rax
jne .L5
.L3:
ret
.cfi_endproc
.LFE3768:
.size _Z14vector_add_cpuPiS_S_i, .-_Z14vector_add_cpuPiS_S_i
.globl _Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i
.type _Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i, @function
_Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i:
.LFB3796:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movl %ecx, 4(%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
leaq 4(%rsp), %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L11
.L7:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L12
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L11:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z14vector_add_gpuPiS_S_i(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L7
.L12:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3796:
.size _Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i, .-_Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i
.globl _Z14vector_add_gpuPiS_S_i
.type _Z14vector_add_gpuPiS_S_i, @function
_Z14vector_add_gpuPiS_S_i:
.LFB3797:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3797:
.size _Z14vector_add_gpuPiS_S_i, .-_Z14vector_add_gpuPiS_S_i
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "vector_add_cpu: "
.LC1:
.string " nanoseconds.\n"
.LC2:
.string "vector_add_gpu: "
.text
.globl main
.type main, @function
main:
.LFB3769:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
subq $64, %rsp
.cfi_def_cfa_offset 112
movq %fs:40, %rax
movq %rax, 56(%rsp)
xorl %eax, %eax
movl $262140, %edi
call malloc@PLT
movq %rax, %r12
movl $262140, %edi
call malloc@PLT
movq %rax, %rbp
movl $262140, %edi
call malloc@PLT
movq %rax, %rbx
leaq 8(%rsp), %rdi
movl $1, %edx
movl $262140, %esi
call cudaMallocManaged@PLT
leaq 16(%rsp), %rdi
movl $1, %edx
movl $262140, %esi
call cudaMallocManaged@PLT
leaq 24(%rsp), %rdi
movl $1, %edx
movl $262140, %esi
call cudaMallocManaged@PLT
movl $0, %eax
.L16:
movl %eax, (%r12,%rax,4)
movl %eax, 0(%rbp,%rax,4)
movl %eax, (%rbx,%rax,4)
addq $1, %rax
cmpq $65535, %rax
jne .L16
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
movl $65535, %ecx
movq %rbx, %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z14vector_add_cpuPiS_S_i
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
leaq .LC0(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
subq %r14, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r14
movl $65535, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 44(%rsp), %rdx
movl $1, %ecx
movq 32(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L21
.L17:
call cudaDeviceSynchronize@PLT
call _ZNSt6chrono3_V212system_clock3nowEv@PLT
movq %rax, %r13
leaq .LC2(%rip), %rsi
leaq _ZSt4cout(%rip), %rdi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %rax, %rdi
movq %r13, %rsi
subq %r14, %rsi
call _ZNSo9_M_insertIlEERSoT_@PLT
movq %rax, %rdi
leaq .LC1(%rip), %rsi
call _ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
movq %r12, %rdi
call cudaFree@PLT
movq %rbp, %rdi
call cudaFree@PLT
movq %rbx, %rdi
call cudaFree@PLT
movq %r12, %rdi
call free@PLT
movq %rbp, %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 56(%rsp), %rax
subq %fs:40, %rax
jne .L22
movl $0, %eax
addq $64, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L21:
.cfi_restore_state
movl $65535, %ecx
movq 24(%rsp), %rdx
movq 16(%rsp), %rsi
movq 8(%rsp), %rdi
call _Z39__device_stub__Z14vector_add_gpuPiS_S_iPiS_S_i
jmp .L17
.L22:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE3769:
.size main, .-main
.section .rodata.str1.1
.LC3:
.string "_Z14vector_add_gpuPiS_S_i"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3799:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC3(%rip), %rdx
movq %rdx, %rcx
leaq _Z14vector_add_gpuPiS_S_i(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE3799:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "sumVectors.hip"
# Start of file scope inline assembly
.globl _ZSt21ios_base_library_initv
# End of file scope inline assembly
.globl _Z14vector_add_cpuPiS_S_i # -- Begin function _Z14vector_add_cpuPiS_S_i
.p2align 4, 0x90
.type _Z14vector_add_cpuPiS_S_i,@function
_Z14vector_add_cpuPiS_S_i: # @_Z14vector_add_cpuPiS_S_i
.cfi_startproc
# %bb.0:
testl %ecx, %ecx
jle .LBB0_3
# %bb.1: # %.lr.ph.preheader
movl %ecx, %eax
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB0_2: # %.lr.ph
# =>This Inner Loop Header: Depth=1
movl (%rsi,%rcx,4), %r8d
addl (%rdi,%rcx,4), %r8d
movl %r8d, (%rdx,%rcx,4)
incq %rcx
cmpq %rcx, %rax
jne .LBB0_2
.LBB0_3: # %._crit_edge
retq
.Lfunc_end0:
.size _Z14vector_add_cpuPiS_S_i, .Lfunc_end0-_Z14vector_add_cpuPiS_S_i
.cfi_endproc
# -- End function
.globl _Z29__device_stub__vector_add_gpuPiS_S_i # -- Begin function _Z29__device_stub__vector_add_gpuPiS_S_i
.p2align 4, 0x90
.type _Z29__device_stub__vector_add_gpuPiS_S_i,@function
_Z29__device_stub__vector_add_gpuPiS_S_i: # @_Z29__device_stub__vector_add_gpuPiS_S_i
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movl %ecx, 4(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 4(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z14vector_add_gpuPiS_S_i, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end1:
.size _Z29__device_stub__vector_add_gpuPiS_S_i, .Lfunc_end1-_Z29__device_stub__vector_add_gpuPiS_S_i
.cfi_endproc
# -- End function
.globl main # -- Begin function main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $144, %rsp
.cfi_def_cfa_offset 192
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $262140, %edi # imm = 0x3FFFC
callq malloc
movq %rax, %rbx
movl $262140, %edi # imm = 0x3FFFC
callq malloc
movq %rax, %r14
movl $262140, %edi # imm = 0x3FFFC
callq malloc
movq %rax, %r15
leaq 32(%rsp), %rdi
movl $262140, %esi # imm = 0x3FFFC
movl $1, %edx
callq hipMallocManaged
leaq 24(%rsp), %rdi
movl $262140, %esi # imm = 0x3FFFC
movl $1, %edx
callq hipMallocManaged
leaq 16(%rsp), %rdi
movl $262140, %esi # imm = 0x3FFFC
movl $1, %edx
callq hipMallocManaged
xorl %eax, %eax
.p2align 4, 0x90
.LBB2_1: # =>This Inner Loop Header: Depth=1
movl %eax, (%rbx,%rax,4)
movl %eax, (%r14,%rax,4)
movl %eax, (%r15,%rax,4)
incq %rax
cmpq $65535, %rax # imm = 0xFFFF
jne .LBB2_1
# %bb.2:
xorl %r13d, %r13d
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
.p2align 4, 0x90
.LBB2_3: # %.lr.ph.i
# =>This Inner Loop Header: Depth=1
movl (%r14,%r13,4), %eax
addl (%rbx,%r13,4), %eax
movl %eax, (%r15,%r13,4)
incq %r13
cmpq $65535, %r13 # imm = 0xFFFF
jne .LBB2_3
# %bb.4: # %_Z14vector_add_cpuPiS_S_i.exit
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl $_ZSt4cout, %edi
movl $.L.str, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r13
movl $_ZSt4cout, %edi
movq %r13, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.1, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r12
movabsq $4294967297, %rdi # imm = 0x100000001
leaq 65534(%rdi), %rdx
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB2_6
# %bb.5:
movq 32(%rsp), %rax
movq 24(%rsp), %rcx
movq 16(%rsp), %rdx
movq %rax, 104(%rsp)
movq %rcx, 96(%rsp)
movq %rdx, 88(%rsp)
movl $65535, 12(%rsp) # imm = 0xFFFF
leaq 104(%rsp), %rax
movq %rax, 112(%rsp)
leaq 96(%rsp), %rax
movq %rax, 120(%rsp)
leaq 88(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 72(%rsp), %rdi
leaq 56(%rsp), %rsi
leaq 48(%rsp), %rdx
leaq 40(%rsp), %rcx
callq __hipPopCallConfiguration
movq 72(%rsp), %rsi
movl 80(%rsp), %edx
movq 56(%rsp), %rcx
movl 64(%rsp), %r8d
leaq 112(%rsp), %r9
movl $_Z14vector_add_gpuPiS_S_i, %edi
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
pushq 56(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB2_6:
callq hipDeviceSynchronize
callq _ZNSt6chrono3_V212system_clock3nowEv
movq %rax, %r13
movl $_ZSt4cout, %edi
movl $.L.str.2, %esi
movl $16, %edx
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
subq %r12, %r13
movl $_ZSt4cout, %edi
movq %r13, %rsi
callq _ZNSo9_M_insertIlEERSoT_
movl $.L.str.1, %esi
movl $14, %edx
movq %rax, %rdi
callq _ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
movq %rbx, %rdi
callq hipFree
movq %r14, %rdi
callq hipFree
movq %r15, %rdi
callq hipFree
movq %rbx, %rdi
callq free
movq %r14, %rdi
callq free
movq %r15, %rdi
callq free
xorl %eax, %eax
addq $144, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size main, .Lfunc_end2-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB3_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB3_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z14vector_add_gpuPiS_S_i, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end3:
.size __hip_module_ctor, .Lfunc_end3-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB4_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB4_2:
retq
.Lfunc_end4:
.size __hip_module_dtor, .Lfunc_end4-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z14vector_add_gpuPiS_S_i,@object # @_Z14vector_add_gpuPiS_S_i
.section .rodata,"a",@progbits
.globl _Z14vector_add_gpuPiS_S_i
.p2align 3, 0x0
_Z14vector_add_gpuPiS_S_i:
.quad _Z29__device_stub__vector_add_gpuPiS_S_i
.size _Z14vector_add_gpuPiS_S_i, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "vector_add_cpu: "
.size .L.str, 17
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz " nanoseconds.\n"
.size .L.str.1, 15
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "vector_add_gpu: "
.size .L.str.2, 17
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z14vector_add_gpuPiS_S_i"
.size .L__unnamed_1, 26
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z29__device_stub__vector_add_gpuPiS_S_i
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z14vector_add_gpuPiS_S_i
.addrsig_sym _ZSt4cout
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #define N 64
#define B 1
#define T 64
__global__ void dl(int* in)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// The warps in this block take different paths; the synctreads calls
// will cause a deadlock.
if(tid > 31)
{
if(tid % 2 == 0)
in[tid]++;
__syncthreads();
}
else {
if(tid % 2 == 1)
in[tid]--;
__syncthreads();
}
} | code for sm_80
Function : _Z2dlPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0060*/ ISETP.GT.AND P0, PT, R0.reuse, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x040fe40003f04270 */
/*0070*/ LEA.HI R2, R0, R0, RZ, 0x1 ; /* 0x0000000000027211 */
/* 0x000fc800078f08ff */
/*0080*/ LOP3.LUT R5, R2, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe02057812 */
/* 0x000fe200078ec0ff */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.IADD R5, R0, 0x1, -R5 ; /* 0x0000000100057824 */
/* 0x000fe400078e0a05 */
/*00b0*/ @P0 BRA 0x140 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f05270 */
/*00d0*/ @P0 BRA 0x110 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ IADD3 R5, R0, -0x1, RZ ; /* 0xffffffff00057810 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0110*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0150*/ @P0 BRA 0x190 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0160*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0170*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0180*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0190*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #define N 64
#define B 1
#define T 64
__global__ void dl(int* in)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// The warps in this block take different paths; the synctreads calls
// will cause a deadlock.
if(tid > 31)
{
if(tid % 2 == 0)
in[tid]++;
__syncthreads();
}
else {
if(tid % 2 == 1)
in[tid]--;
__syncthreads();
}
} | .file "tmpxft_0011b9b8_00000000-6_barrier3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21__device_stub__Z2dlPiPi
.type _Z21__device_stub__Z2dlPiPi, @function
_Z21__device_stub__Z2dlPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2dlPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z21__device_stub__Z2dlPiPi, .-_Z21__device_stub__Z2dlPiPi
.globl _Z2dlPi
.type _Z2dlPi, @function
_Z2dlPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z2dlPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2dlPi, .-_Z2dlPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2dlPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2dlPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #define N 64
#define B 1
#define T 64
__global__ void dl(int* in)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// The warps in this block take different paths; the synctreads calls
// will cause a deadlock.
if(tid > 31)
{
if(tid % 2 == 0)
in[tid]++;
__syncthreads();
}
else {
if(tid % 2 == 1)
in[tid]--;
__syncthreads();
}
} | #include <hip/hip_runtime.h>
#define N 64
#define B 1
#define T 64
__global__ void dl(int* in)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// The warps in this block take different paths; the synctreads calls
// will cause a deadlock.
if(tid > 31)
{
if(tid % 2 == 0)
in[tid]++;
__syncthreads();
}
else {
if(tid % 2 == 1)
in[tid]--;
__syncthreads();
}
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#define N 64
#define B 1
#define T 64
__global__ void dl(int* in)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// The warps in this block take different paths; the synctreads calls
// will cause a deadlock.
if(tid > 31)
{
if(tid % 2 == 0)
in[tid]++;
__syncthreads();
}
else {
if(tid % 2 == 1)
in[tid]--;
__syncthreads();
}
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2dlPi
.globl _Z2dlPi
.p2align 8
.type _Z2dlPi,@function
_Z2dlPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 32, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
v_and_b32_e32 v0, 0x80000001, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v0
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, -1, v2
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt_vscnt null, 0x0
s_barrier
.LBB0_4:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_8
v_and_b32_e32 v0, 1, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt_vscnt null, 0x0
s_barrier
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2dlPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2dlPi, .Lfunc_end0-_Z2dlPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2dlPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2dlPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#define N 64
#define B 1
#define T 64
__global__ void dl(int* in)
{
int tid = threadIdx.x + blockIdx.x * blockDim.x;
// The warps in this block take different paths; the synctreads calls
// will cause a deadlock.
if(tid > 31)
{
if(tid % 2 == 0)
in[tid]++;
__syncthreads();
}
else {
if(tid % 2 == 1)
in[tid]--;
__syncthreads();
}
} | .text
.file "barrier3.hip"
.globl _Z17__device_stub__dlPi # -- Begin function _Z17__device_stub__dlPi
.p2align 4, 0x90
.type _Z17__device_stub__dlPi,@function
_Z17__device_stub__dlPi: # @_Z17__device_stub__dlPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z2dlPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z17__device_stub__dlPi, .Lfunc_end0-_Z17__device_stub__dlPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2dlPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2dlPi,@object # @_Z2dlPi
.section .rodata,"a",@progbits
.globl _Z2dlPi
.p2align 3, 0x0
_Z2dlPi:
.quad _Z17__device_stub__dlPi
.size _Z2dlPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2dlPi"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__dlPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2dlPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z2dlPi
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fe400078e0203 */
/*0050*/ IMAD.MOV.U32 R3, RZ, RZ, 0x4 ; /* 0x00000004ff037424 */
/* 0x000fc600078e00ff */
/*0060*/ ISETP.GT.AND P0, PT, R0.reuse, 0x1f, PT ; /* 0x0000001f0000780c */
/* 0x040fe40003f04270 */
/*0070*/ LEA.HI R2, R0, R0, RZ, 0x1 ; /* 0x0000000000027211 */
/* 0x000fc800078f08ff */
/*0080*/ LOP3.LUT R5, R2, 0xfffffffe, RZ, 0xc0, !PT ; /* 0xfffffffe02057812 */
/* 0x000fe200078ec0ff */
/*0090*/ IMAD.WIDE R2, R0, R3, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e0203 */
/*00a0*/ IMAD.IADD R5, R0, 0x1, -R5 ; /* 0x0000000100057824 */
/* 0x000fe400078e0a05 */
/*00b0*/ @P0 BRA 0x140 ; /* 0x0000008000000947 */
/* 0x000fea0003800000 */
/*00c0*/ ISETP.NE.AND P0, PT, R5, 0x1, PT ; /* 0x000000010500780c */
/* 0x000fda0003f05270 */
/*00d0*/ @P0 BRA 0x110 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*00e0*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*00f0*/ IADD3 R5, R0, -0x1, RZ ; /* 0xffffffff00057810 */
/* 0x004fca0007ffe0ff */
/*0100*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0110*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0140*/ ISETP.NE.AND P0, PT, R5, RZ, PT ; /* 0x000000ff0500720c */
/* 0x000fda0003f05270 */
/*0150*/ @P0 BRA 0x190 ; /* 0x0000003000000947 */
/* 0x000fea0003800000 */
/*0160*/ LDG.E R0, [R2.64] ; /* 0x0000000402007981 */
/* 0x000ea4000c1e1900 */
/*0170*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x004fca0007ffe0ff */
/*0180*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x0001e4000c101904 */
/*0190*/ WARPSYNC 0xffffffff ; /* 0xffffffff00007948 */
/* 0x000fe20003800000 */
/*01a0*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*01b0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*01c0*/ BRA 0x1c0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*01d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*01f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0200*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0210*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0220*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0230*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0240*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0250*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0260*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0270*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z2dlPi
.globl _Z2dlPi
.p2align 8
.type _Z2dlPi,@function
_Z2dlPi:
s_clause 0x1
s_load_b32 s2, s[0:1], 0x14
s_load_b64 s[0:1], s[0:1], 0x0
s_waitcnt lgkmcnt(0)
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
s_mov_b32 s2, exec_lo
v_cmpx_gt_i32_e32 32, v1
s_xor_b32 s2, exec_lo, s2
s_cbranch_execz .LBB0_4
v_and_b32_e32 v0, 0x80000001, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 1, v0
s_cbranch_execz .LBB0_3
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, -1, v2
global_store_b32 v[0:1], v2, off
.LBB0_3:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt_vscnt null, 0x0
s_barrier
.LBB0_4:
s_and_not1_saveexec_b32 s2, s2
s_cbranch_execz .LBB0_8
v_and_b32_e32 v0, 1, v1
s_mov_b32 s3, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_7
v_mov_b32_e32 v2, 0
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[0:1], 2, v[1:2]
v_add_co_u32 v0, vcc_lo, s0, v0
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
global_load_b32 v2, v[0:1], off
s_waitcnt vmcnt(0)
v_add_nc_u32_e32 v2, 1, v2
global_store_b32 v[0:1], v2, off
.LBB0_7:
s_or_b32 exec_lo, exec_lo, s3
s_waitcnt_vscnt null, 0x0
s_barrier
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s2
buffer_gl0_inv
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z2dlPi
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 264
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 3
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z2dlPi, .Lfunc_end0-_Z2dlPi
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .offset: 8
.size: 4
.value_kind: hidden_block_count_x
- .offset: 12
.size: 4
.value_kind: hidden_block_count_y
- .offset: 16
.size: 4
.value_kind: hidden_block_count_z
- .offset: 20
.size: 2
.value_kind: hidden_group_size_x
- .offset: 22
.size: 2
.value_kind: hidden_group_size_y
- .offset: 24
.size: 2
.value_kind: hidden_group_size_z
- .offset: 26
.size: 2
.value_kind: hidden_remainder_x
- .offset: 28
.size: 2
.value_kind: hidden_remainder_y
- .offset: 30
.size: 2
.value_kind: hidden_remainder_z
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 64
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 72
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 264
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z2dlPi
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z2dlPi.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 3
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0011b9b8_00000000-6_barrier3.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z21__device_stub__Z2dlPiPi
.type _Z21__device_stub__Z2dlPiPi, @function
_Z21__device_stub__Z2dlPiPi:
.LFB2051:
.cfi_startproc
endbr64
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 8(%rsp)
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rax
movq %rax, 80(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
leaq 24(%rsp), %rcx
leaq 16(%rsp), %rdx
leaq 44(%rsp), %rsi
leaq 32(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 24(%rsp)
.cfi_def_cfa_offset 120
pushq 24(%rsp)
.cfi_def_cfa_offset 128
leaq 96(%rsp), %r9
movq 60(%rsp), %rcx
movl 68(%rsp), %r8d
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
leaq _Z2dlPi(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 112
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z21__device_stub__Z2dlPiPi, .-_Z21__device_stub__Z2dlPiPi
.globl _Z2dlPi
.type _Z2dlPi, @function
_Z2dlPi:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z21__device_stub__Z2dlPiPi
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z2dlPi, .-_Z2dlPi
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z2dlPi"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z2dlPi(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "barrier3.hip"
.globl _Z17__device_stub__dlPi # -- Begin function _Z17__device_stub__dlPi
.p2align 4, 0x90
.type _Z17__device_stub__dlPi,@function
_Z17__device_stub__dlPi: # @_Z17__device_stub__dlPi
.cfi_startproc
# %bb.0:
subq $72, %rsp
.cfi_def_cfa_offset 80
movq %rdi, 64(%rsp)
leaq 64(%rsp), %rax
movq %rax, (%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
movq %rsp, %r9
movl $_Z2dlPi, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $88, %rsp
.cfi_adjust_cfa_offset -88
retq
.Lfunc_end0:
.size _Z17__device_stub__dlPi, .Lfunc_end0-_Z17__device_stub__dlPi
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z2dlPi, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z2dlPi,@object # @_Z2dlPi
.section .rodata,"a",@progbits
.globl _Z2dlPi
.p2align 3, 0x0
_Z2dlPi:
.quad _Z17__device_stub__dlPi
.size _Z2dlPi, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z2dlPi"
.size .L__unnamed_1, 8
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z17__device_stub__dlPi
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z2dlPi
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | //
// Created by Sowmya Parameshwara on 11/10/16.
//
/**
*
* 1) Input is stored by transposing the matrix, so that the attributes of a column are stored in a single row. This
* will optimise the algorithm since all threads in a block will access nearby elements, while normalising.
* 2) Each row is normalised at a time for calculating standardscore, the calculated values are stored in output matrix by transposing.
* 3) Number of threads in a block is set as 16 (This value determined by checking performance for different values). The number of blocks
* is decided based on matrix size "N" and number of threads.
* 4) The contents of a row are divided among the blocks. In each block,Each thread populates one elements of the block into shared data.
* We then calculate partial sum without divergence, on the data stored in shared memory.
* 5) Once all blocks compute partial sum, we launch a kernel function on a single block by passing the calculated values from the previous step.
* This will calculate the final sum and final squared sum. To this final block we ensure the size of the partial sum array passed equals
the next nearest power of 2 of "the number of blocks", as partial sum algorithm works only for powers of 2.
* 6) The above data is used to calculate standard deviation for that row using the formula ((totalSquareSum + N*powf(mean, 2.0) - 2 * mean * totalSum)/(float)N)
* 7) The above value is used to calculate standard score for every element in that row.
* 8) The above step repeats for every row, calculating the standard score for all elements in the row.
*
* Steps to compile and execute on Jarvis :
* 1) qlogin -q interactive.q (Launches interactive session).
* 2) nvcc matrixNorm.cu -o matrixNorm (Compile code on jarvis).
* 3) cd hw4 (Code is available here).
* 4) ./matrixNorm 15000 4 <Argument 1 : Size of matrix, Argument 2 : Random seed value>
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#include <cuda_runtime.h>
/* Program Parameters */
#define MAXN 15000 /* Max value of N */
int N; /* Matrix size */
/* Matrices */
volatile float A[MAXN][MAXN], B[MAXN][MAXN];
/* junk */
#define randm() 4|2[uid]&3
/* Prototype */
void matrixNorm();
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
if (argc == 3) {
seed = atoi(argv[2]);
srand(seed);
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
if (N < 1 || N > MAXN) {
printf("N = %i is out of range.\n", N);
exit(0);
}
}
else {
printf("Usage: %s <matrix_dimension> [random seed]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
printf("\nInitializing...\n");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (col = 0; col < N; col++) {
for (row = 0; row < N; row++) {
printf("%5.2f%s", A[row][col], (row < N-1) ? ", " : ";\n\t");
}
}
}
}
void print_B() {
int row, col;
if (N < 10) {
printf("\nB =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%1.10f%s", B[row][col], (col < N-1) ? ", " : ";\n\t");
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
clock_t etstart2, etstop2; /* Elapsed times using times() */
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop; /* CPU times for my processes */
/* Process program parameters */
parameters(argc, argv);
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\nStarting clock.\n");
gettimeofday(&etstart, &tzdummy);
etstart2 = times(&cputstart);
/* Gaussian Elimination */
matrixNorm();
/* Stop Clock */
gettimeofday(&etstop, &tzdummy);
etstop2 = times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display output */
print_B();
/* Display timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
/**
* Method to calculate the partial sum without divergence in all the blocks.
*/
__global__ void block_sum(const float *hostInput, float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[1024];
__shared__ float sharedSquareData[1024];
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
if(i < n) {
x = hostInput[i];
}
sharedSumData[tx] = x;
sharedSquareData[tx] = x*x;
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result of this block
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[blockIdx.x] = sharedSumData[0];
squareResults[blockIdx.x] = sharedSquareData[0];
}
}
/**
* Method to calculate the sum of the results calculated from all the blocks in the previous step.
*/
__global__ void single_block_reduction(float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[256];
__shared__ float sharedSquareData[256];
int tx = threadIdx.x;
if(tx < n) {
sharedSumData[tx] = sumResults[tx];
sharedSquareData[tx] = squareResults[tx];
}
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = n/2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[0] = sharedSumData[0];
squareResults[0] = sharedSquareData[0];
}
}
float* sum (float *hostInput, size_t n, float *deviceMatrixA, float *sumResults, float *squareResults,int numOfThreadsPerBlock,int numOfBlocks,int next) {
cudaMemcpy( deviceMatrixA, hostInput, sizeof(float) * N, cudaMemcpyHostToDevice );
/* dim3 dimGrid(numOfBlocks, 1, 1);
dim3 dimBlock(numOfThreadsPerBlock, 1, 1);*/
block_sum<<<numOfBlocks,numOfThreadsPerBlock>>> (deviceMatrixA, sumResults, squareResults, n);
/* float *sumResultsInput = 0;
float *squareResultsInput = 0;
cudaMalloc((void**)&sumResultsInput, sizeof(float) * next);
cudaMemset(sumResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(sumResultsInput, sumResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice );
cudaMalloc((void**)&squareResultsInput, sizeof(float) * next);
cudaMemset(squareResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(squareResultsInput, squareResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice ); */
single_block_reduction<<<1,numOfBlocks>>>(sumResults,squareResults,next);
float * results = (float *)malloc(sizeof(float) * 2);
cudaMemcpy(&results[0], &sumResults[0], sizeof(float) , cudaMemcpyDeviceToHost );
cudaMemcpy(&results[1], &squareResults[0], sizeof(float) , cudaMemcpyDeviceToHost );
return results;
}
void matrixNorm() {
int row, col;
float mu, sigma;
printf("Computing Parallely.\n");
size_t numOfThreadsPerBlock = 16;
size_t numOfBlocks = N/numOfThreadsPerBlock + (((N)%numOfThreadsPerBlock) ? 1 : 0);
int next = pow(2, ceil(log(numOfBlocks)/log(2)));
float *sumResults = 0;
cudaMalloc((void**)&sumResults, sizeof(float) * (next));
cudaMemset(sumResults, 0.0, sizeof(float) * next);
float *squareResults = 0;
cudaMalloc((void**)&squareResults, sizeof(float) * (next));
cudaMemset(squareResults, 0.0, sizeof(float) * next);
float *deviceMatrixA = 0;
cudaMalloc( (void**)&deviceMatrixA, sizeof(float) * N);
for (row=0; row < N; row++) {
mu = 0.0;
float *hostResults;
hostResults = sum ((float *)A[row], N, deviceMatrixA, sumResults, squareResults,numOfThreadsPerBlock,numOfBlocks,next);
mu = hostResults[0] / (float) N;
sigma = (hostResults[1] + N*powf(mu, 2.0) - 2 * mu * hostResults[0])/(float)N;
for (col=0; col < N; col++) {
if (sigma == 0.0) {
B[col][row] = 0.0;
} else {
B[col][row] = (A[row][col] - mu) / sigma;
}
}
}
cudaFree(sumResults);
cudaFree(squareResults);
cudaFree(deviceMatrixA);
} | code for sm_80
Function : _Z22single_block_reductionPfS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ ISETP.GE.U32.AND P0, PT, R7.reuse, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x041fe20003f06070 */
/*0040*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x000fe200078e00ff */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R7 ; /* 0x0000001fff027819 */
/* 0x000fc80000011407 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @!P0 SHF.L.U64.HI R5, R7, 0x2, R2 ; /* 0x0000000207058819 */
/* 0x000fe40000010202 */
/*0080*/ @!P0 IADD3 R2, P1, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000028a10 */
/* 0x040fe40007f3e0ff */
/*0090*/ @!P0 IADD3 R4, P2, R0, c[0x0][0x168], RZ ; /* 0x00005a0000048a10 */
/* 0x000fe40007f5e0ff */
/*00a0*/ @!P0 IADD3.X R3, R5.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005038a10 */
/* 0x040fe40000ffe4ff */
/*00b0*/ @!P0 IADD3.X R5, R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005058a10 */
/* 0x000fc600017fe4ff */
/*00c0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000402028981 */
/* 0x0000a8000c1e1900 */
/*00d0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fca00078e00ff */
/*0100*/ SHF.R.U64 R3, R6, R9, c[0x0][0x174] ; /* 0x00005d0006037619 */
/* 0x001fe20000001209 */
/*0110*/ @!P0 STS [R7.X4], R2 ; /* 0x0000000207008388 */
/* 0x0041e80000004800 */
/*0120*/ @!P0 STS [R7.X4+0x400], R4 ; /* 0x0004000407008388 */
/* 0x0081e80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f06270 */
/*0150*/ @!P0 BRA 0x270 ; /* 0x0000011000008947 */
/* 0x001fea0003800000 */
/*0160*/ ISETP.GE.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fe20003f06270 */
/*0170*/ BSSY B0, 0x230 ; /* 0x000000b000007945 */
/* 0x000fd80003800000 */
/*0180*/ @P0 BRA 0x220 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*0190*/ IMAD R2, R3, 0x4, R0 ; /* 0x0000000403027824 */
/* 0x000fe200078e0200 */
/*01a0*/ LDS R4, [R7.X4] ; /* 0x0000000007047984 */
/* 0x000fe80000004800 */
/*01b0*/ LDS R5, [R2] ; /* 0x0000000002057984 */
/* 0x000e240000000800 */
/*01c0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fe40000000000 */
/*01d0*/ LDS R5, [R7.X4+0x400] ; /* 0x0004000007057984 */
/* 0x000fe80000004800 */
/*01e0*/ STS [R7.X4], R4 ; /* 0x0000000407007388 */
/* 0x000fe80000004800 */
/*01f0*/ LDS R6, [R2+0x400] ; /* 0x0004000002067984 */
/* 0x000e240000000800 */
/*0200*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0210*/ STS [R7.X4+0x400], R5 ; /* 0x0004000507007388 */
/* 0x0001e40000004800 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0250*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0260*/ @P0 BRA 0x160 ; /* 0xfffffef000000947 */
/* 0x000fea000383ffff */
/*0270*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x001e220000000800 */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*02c0*/ LDS R9, [0x400] ; /* 0x00040000ff097984 */
/* 0x000e620000000800 */
/*02d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*02e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*02f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*0300*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9block_sumPKfPfS1_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R8, c[0x0][0x0], R7 ; /* 0x0000000008007a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0060*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @!P0 LEA R2, P1, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000028a11 */
/* 0x000fc800078210ff */
/*0090*/ @!P0 LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P1 ; /* 0x0000590000038a11 */
/* 0x000fe200008f1403 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fcc00078e00ff */
/*00b0*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000602008981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00e0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*00f0*/ FMUL R4, R0, R0 ; /* 0x0000000000047220 */
/* 0x004fe20000400000 */
/*0100*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*0110*/ STS [R7.X4+0x1000], R4 ; /* 0x0010000407007388 */
/* 0x0001e80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @!P0 BRA 0x270 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0150*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0160*/ ISETP.GE.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fe20003f06270 */
/*0170*/ BSSY B0, 0x230 ; /* 0x000000b000007945 */
/* 0x000fd80003800000 */
/*0180*/ @P0 BRA 0x220 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*0190*/ IMAD R2, R3, 0x4, R0 ; /* 0x0000000403027824 */
/* 0x000fe200078e0200 */
/*01a0*/ LDS R4, [R7.X4] ; /* 0x0000000007047984 */
/* 0x000fe80000004800 */
/*01b0*/ LDS R5, [R2] ; /* 0x0000000002057984 */
/* 0x000e240000000800 */
/*01c0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fe40000000000 */
/*01d0*/ LDS R5, [R7.X4+0x1000] ; /* 0x0010000007057984 */
/* 0x000fe80000004800 */
/*01e0*/ STS [R7.X4], R4 ; /* 0x0000000407007388 */
/* 0x000fe80000004800 */
/*01f0*/ LDS R6, [R2+0x1000] ; /* 0x0010000002067984 */
/* 0x000e240000000800 */
/*0200*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0210*/ STS [R7.X4+0x1000], R5 ; /* 0x0010000507007388 */
/* 0x0001e40000004800 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0250*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0260*/ @P0 BRA 0x160 ; /* 0xfffffef000000947 */
/* 0x000fea000383ffff */
/*0270*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000e220000000800 */
/*02a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*02b0*/ LDS R9, [0x1000] ; /* 0x00100000ff097984 */
/* 0x000e6e0000000800 */
/*02c0*/ IMAD.WIDE.U32 R2, R8, R5, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x000fc800078e0005 */
/*02d0*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fe200078e0005 */
/*02e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101906 */
/*02f0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101906 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by Sowmya Parameshwara on 11/10/16.
//
/**
*
* 1) Input is stored by transposing the matrix, so that the attributes of a column are stored in a single row. This
* will optimise the algorithm since all threads in a block will access nearby elements, while normalising.
* 2) Each row is normalised at a time for calculating standardscore, the calculated values are stored in output matrix by transposing.
* 3) Number of threads in a block is set as 16 (This value determined by checking performance for different values). The number of blocks
* is decided based on matrix size "N" and number of threads.
* 4) The contents of a row are divided among the blocks. In each block,Each thread populates one elements of the block into shared data.
* We then calculate partial sum without divergence, on the data stored in shared memory.
* 5) Once all blocks compute partial sum, we launch a kernel function on a single block by passing the calculated values from the previous step.
* This will calculate the final sum and final squared sum. To this final block we ensure the size of the partial sum array passed equals
the next nearest power of 2 of "the number of blocks", as partial sum algorithm works only for powers of 2.
* 6) The above data is used to calculate standard deviation for that row using the formula ((totalSquareSum + N*powf(mean, 2.0) - 2 * mean * totalSum)/(float)N)
* 7) The above value is used to calculate standard score for every element in that row.
* 8) The above step repeats for every row, calculating the standard score for all elements in the row.
*
* Steps to compile and execute on Jarvis :
* 1) qlogin -q interactive.q (Launches interactive session).
* 2) nvcc matrixNorm.cu -o matrixNorm (Compile code on jarvis).
* 3) cd hw4 (Code is available here).
* 4) ./matrixNorm 15000 4 <Argument 1 : Size of matrix, Argument 2 : Random seed value>
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#include <cuda_runtime.h>
/* Program Parameters */
#define MAXN 15000 /* Max value of N */
int N; /* Matrix size */
/* Matrices */
volatile float A[MAXN][MAXN], B[MAXN][MAXN];
/* junk */
#define randm() 4|2[uid]&3
/* Prototype */
void matrixNorm();
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
if (argc == 3) {
seed = atoi(argv[2]);
srand(seed);
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
if (N < 1 || N > MAXN) {
printf("N = %i is out of range.\n", N);
exit(0);
}
}
else {
printf("Usage: %s <matrix_dimension> [random seed]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
printf("\nInitializing...\n");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (col = 0; col < N; col++) {
for (row = 0; row < N; row++) {
printf("%5.2f%s", A[row][col], (row < N-1) ? ", " : ";\n\t");
}
}
}
}
void print_B() {
int row, col;
if (N < 10) {
printf("\nB =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%1.10f%s", B[row][col], (col < N-1) ? ", " : ";\n\t");
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
clock_t etstart2, etstop2; /* Elapsed times using times() */
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop; /* CPU times for my processes */
/* Process program parameters */
parameters(argc, argv);
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\nStarting clock.\n");
gettimeofday(&etstart, &tzdummy);
etstart2 = times(&cputstart);
/* Gaussian Elimination */
matrixNorm();
/* Stop Clock */
gettimeofday(&etstop, &tzdummy);
etstop2 = times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display output */
print_B();
/* Display timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
/**
* Method to calculate the partial sum without divergence in all the blocks.
*/
__global__ void block_sum(const float *hostInput, float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[1024];
__shared__ float sharedSquareData[1024];
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
if(i < n) {
x = hostInput[i];
}
sharedSumData[tx] = x;
sharedSquareData[tx] = x*x;
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result of this block
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[blockIdx.x] = sharedSumData[0];
squareResults[blockIdx.x] = sharedSquareData[0];
}
}
/**
* Method to calculate the sum of the results calculated from all the blocks in the previous step.
*/
__global__ void single_block_reduction(float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[256];
__shared__ float sharedSquareData[256];
int tx = threadIdx.x;
if(tx < n) {
sharedSumData[tx] = sumResults[tx];
sharedSquareData[tx] = squareResults[tx];
}
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = n/2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[0] = sharedSumData[0];
squareResults[0] = sharedSquareData[0];
}
}
float* sum (float *hostInput, size_t n, float *deviceMatrixA, float *sumResults, float *squareResults,int numOfThreadsPerBlock,int numOfBlocks,int next) {
cudaMemcpy( deviceMatrixA, hostInput, sizeof(float) * N, cudaMemcpyHostToDevice );
/* dim3 dimGrid(numOfBlocks, 1, 1);
dim3 dimBlock(numOfThreadsPerBlock, 1, 1);*/
block_sum<<<numOfBlocks,numOfThreadsPerBlock>>> (deviceMatrixA, sumResults, squareResults, n);
/* float *sumResultsInput = 0;
float *squareResultsInput = 0;
cudaMalloc((void**)&sumResultsInput, sizeof(float) * next);
cudaMemset(sumResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(sumResultsInput, sumResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice );
cudaMalloc((void**)&squareResultsInput, sizeof(float) * next);
cudaMemset(squareResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(squareResultsInput, squareResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice ); */
single_block_reduction<<<1,numOfBlocks>>>(sumResults,squareResults,next);
float * results = (float *)malloc(sizeof(float) * 2);
cudaMemcpy(&results[0], &sumResults[0], sizeof(float) , cudaMemcpyDeviceToHost );
cudaMemcpy(&results[1], &squareResults[0], sizeof(float) , cudaMemcpyDeviceToHost );
return results;
}
void matrixNorm() {
int row, col;
float mu, sigma;
printf("Computing Parallely.\n");
size_t numOfThreadsPerBlock = 16;
size_t numOfBlocks = N/numOfThreadsPerBlock + (((N)%numOfThreadsPerBlock) ? 1 : 0);
int next = pow(2, ceil(log(numOfBlocks)/log(2)));
float *sumResults = 0;
cudaMalloc((void**)&sumResults, sizeof(float) * (next));
cudaMemset(sumResults, 0.0, sizeof(float) * next);
float *squareResults = 0;
cudaMalloc((void**)&squareResults, sizeof(float) * (next));
cudaMemset(squareResults, 0.0, sizeof(float) * next);
float *deviceMatrixA = 0;
cudaMalloc( (void**)&deviceMatrixA, sizeof(float) * N);
for (row=0; row < N; row++) {
mu = 0.0;
float *hostResults;
hostResults = sum ((float *)A[row], N, deviceMatrixA, sumResults, squareResults,numOfThreadsPerBlock,numOfBlocks,next);
mu = hostResults[0] / (float) N;
sigma = (hostResults[1] + N*powf(mu, 2.0) - 2 * mu * hostResults[0])/(float)N;
for (col=0; col < N; col++) {
if (sigma == 0.0) {
B[col][row] = 0.0;
} else {
B[col][row] = (A[row][col] - mu) / sigma;
}
}
}
cudaFree(sumResults);
cudaFree(squareResults);
cudaFree(deviceMatrixA);
} | .file "tmpxft_000bf033_00000000-6_matrixNorm.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2081:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2081:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z9time_seedv
.type _Z9time_seedv, @function
_Z9time_seedv:
.LFB2070:
.cfi_startproc
endbr64
subq $56, %rsp
.cfi_def_cfa_offset 64
movq %fs:40, %rax
movq %rax, 40(%rsp)
xorl %eax, %eax
leaq 8(%rsp), %rsi
leaq 16(%rsp), %rdi
call gettimeofday@PLT
movl 24(%rsp), %eax
movq 40(%rsp), %rdx
subq %fs:40, %rdx
jne .L6
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L6:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2070:
.size _Z9time_seedv, .-_Z9time_seedv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "Random seed = %i\n"
.LC1:
.string "N = %i is out of range.\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC2:
.string "Usage: %s <matrix_dimension> [random seed]\n"
.section .rodata.str1.1
.LC3:
.string "\nMatrix dimension N = %i.\n"
.text
.globl _Z10parametersiPPc
.type _Z10parametersiPPc, @function
_Z10parametersiPPc:
.LFB2071:
.cfi_startproc
endbr64
pushq %rbp
.cfi_def_cfa_offset 16
.cfi_offset 6, -16
pushq %rbx
.cfi_def_cfa_offset 24
.cfi_offset 3, -24
subq $8, %rsp
.cfi_def_cfa_offset 32
movl %edi, %ebx
movq %rsi, %rbp
call _Z9time_seedv
movl %eax, %edi
call srand@PLT
cmpl $3, %ebx
je .L13
cmpl $1, %ebx
jg .L9
movq 0(%rbp), %rdx
leaq .LC2(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L13:
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %ebx
movl %eax, %edi
call srand@PLT
movl %ebx, %edx
leaq .LC0(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
.L9:
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movl %eax, %edx
movl %eax, N(%rip)
subl $1, %eax
cmpl $14999, %eax
jbe .L11
leaq .LC1(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L11:
leaq .LC3(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addq $8, %rsp
.cfi_def_cfa_offset 24
popq %rbx
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2071:
.size _Z10parametersiPPc, .-_Z10parametersiPPc
.section .rodata.str1.1
.LC4:
.string "\nInitializing...\n"
.text
.globl _Z17initialize_inputsv
.type _Z17initialize_inputsv, @function
_Z17initialize_inputsv:
.LFB2072:
.cfi_startproc
endbr64
pushq %r14
.cfi_def_cfa_offset 16
.cfi_offset 14, -16
pushq %r13
.cfi_def_cfa_offset 24
.cfi_offset 13, -24
pushq %r12
.cfi_def_cfa_offset 32
.cfi_offset 12, -32
pushq %rbp
.cfi_def_cfa_offset 40
.cfi_offset 6, -40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset 3, -48
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %r14d
leaq A(%rip), %r13
leaq B(%rip), %r12
cmpl $0, N(%rip)
jg .L15
.L14:
popq %rbx
.cfi_remember_state
.cfi_def_cfa_offset 40
popq %rbp
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r13
.cfi_def_cfa_offset 16
popq %r14
.cfi_def_cfa_offset 8
ret
.L17:
.cfi_restore_state
call rand@PLT
pxor %xmm0, %xmm0
cvtsi2ssl %eax, %xmm0
mulss .LC5(%rip), %xmm0
movslq %ebx, %rax
addq %rbp, %rax
movss %xmm0, 0(%r13,%rax,4)
movl $0x00000000, (%r12,%rax,4)
addl $1, %ebx
cmpl %ebx, N(%rip)
jg .L17
.L18:
addl $1, %r14d
cmpl %r14d, N(%rip)
jle .L14
.L15:
movl $0, %ebx
cmpl $0, N(%rip)
jle .L18
movslq %r14d, %rbp
imulq $15000, %rbp, %rbp
jmp .L17
.cfi_endproc
.LFE2072:
.size _Z17initialize_inputsv, .-_Z17initialize_inputsv
.section .rodata.str1.1
.LC7:
.string ", "
.LC8:
.string ";\n\t"
.LC9:
.string "\nA =\n\t"
.LC10:
.string "%5.2f%s"
.text
.globl _Z12print_inputsv
.type _Z12print_inputsv, @function
_Z12print_inputsv:
.LFB2073:
.cfi_startproc
endbr64
cmpl $9, N(%rip)
jle .L41
ret
.L41:
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $8, %rsp
.cfi_def_cfa_offset 64
leaq .LC9(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %ebp
leaq .LC8(%rip), %r15
leaq .LC7(%rip), %r14
leaq A(%rip), %r13
leaq .LC10(%rip), %r12
cmpl $0, N(%rip)
jg .L27
.L25:
addq $8, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L29:
.cfi_restore_state
subl $1, %eax
cmpl %ebx, %eax
movq %r14, %rcx
cmovle %r15, %rcx
movslq %ebp, %rdx
movslq %ebx, %rax
imulq $15000, %rax, %rax
addq %rdx, %rax
movss 0(%r13,%rax,4), %xmm0
cvtss2sd %xmm0, %xmm0
movq %rcx, %rdx
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
movl N(%rip), %eax
cmpl %ebx, %eax
jg .L29
.L30:
addl $1, %ebp
cmpl %ebp, N(%rip)
jle .L25
.L27:
movl N(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jg .L29
jmp .L30
.cfi_endproc
.LFE2073:
.size _Z12print_inputsv, .-_Z12print_inputsv
.section .rodata.str1.1
.LC11:
.string "\nB =\n\t"
.LC12:
.string "%1.10f%s"
.text
.globl _Z7print_Bv
.type _Z7print_Bv, @function
_Z7print_Bv:
.LFB2074:
.cfi_startproc
endbr64
cmpl $9, N(%rip)
jle .L58
ret
.L58:
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $24, %rsp
.cfi_def_cfa_offset 80
leaq .LC11(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, 12(%rsp)
leaq .LC8(%rip), %r15
leaq .LC7(%rip), %r14
leaq B(%rip), %r13
leaq .LC12(%rip), %r12
cmpl $0, N(%rip)
jg .L44
.L42:
addq $24, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L46:
.cfi_restore_state
subl $1, %eax
cmpl %ebx, %eax
movq %r14, %rdx
cmovle %r15, %rdx
movslq %ebx, %rax
addq %rbp, %rax
movss 0(%r13,%rax,4), %xmm0
cvtss2sd %xmm0, %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addl $1, %ebx
movl N(%rip), %eax
cmpl %ebx, %eax
jg .L46
.L47:
addl $1, 12(%rsp)
movl 12(%rsp), %eax
cmpl %eax, N(%rip)
jle .L42
.L44:
movl N(%rip), %eax
movl $0, %ebx
testl %eax, %eax
jle .L47
movslq 12(%rsp), %rbp
imulq $15000, %rbp, %rbp
jmp .L46
.cfi_endproc
.LFE2074:
.size _Z7print_Bv, .-_Z7print_Bv
.globl _Z35__device_stub__Z9block_sumPKfPfS1_mPKfPfS1_m
.type _Z35__device_stub__Z9block_sumPKfPfS1_mPKfPfS1_m, @function
_Z35__device_stub__Z9block_sumPKfPfS1_mPKfPfS1_m:
.LFB2103:
.cfi_startproc
endbr64
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %rcx, (%rsp)
movq %fs:40, %rax
movq %rax, 136(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 136(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $152, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 168
pushq 40(%rsp)
.cfi_def_cfa_offset 176
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z9block_sumPKfPfS1_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2103:
.size _Z35__device_stub__Z9block_sumPKfPfS1_mPKfPfS1_m, .-_Z35__device_stub__Z9block_sumPKfPfS1_mPKfPfS1_m
.globl _Z9block_sumPKfPfS1_m
.type _Z9block_sumPKfPfS1_m, @function
_Z9block_sumPKfPfS1_m:
.LFB2104:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z35__device_stub__Z9block_sumPKfPfS1_mPKfPfS1_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2104:
.size _Z9block_sumPKfPfS1_m, .-_Z9block_sumPKfPfS1_m
.globl _Z45__device_stub__Z22single_block_reductionPfS_mPfS_m
.type _Z45__device_stub__Z22single_block_reductionPfS_mPfS_m, @function
_Z45__device_stub__Z22single_block_reductionPfS_mPfS_m:
.LFB2105:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movq %rdx, 8(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 8(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L71
.L67:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L72
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L71:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z22single_block_reductionPfS_m(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L67
.L72:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2105:
.size _Z45__device_stub__Z22single_block_reductionPfS_mPfS_m, .-_Z45__device_stub__Z22single_block_reductionPfS_mPfS_m
.globl _Z22single_block_reductionPfS_m
.type _Z22single_block_reductionPfS_m, @function
_Z22single_block_reductionPfS_m:
.LFB2106:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z45__device_stub__Z22single_block_reductionPfS_mPfS_m
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2106:
.size _Z22single_block_reductionPfS_m, .-_Z22single_block_reductionPfS_m
.globl _Z3sumPfmS_S_S_iii
.type _Z3sumPfmS_S_S_iii, @function
_Z3sumPfmS_S_S_iii:
.LFB2076:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rsi, %r14
movq %rdx, %rbx
movq %rcx, %r12
movq %r8, %rbp
movl %r9d, %r13d
movl 96(%rsp), %r15d
movslq N(%rip), %rdx
salq $2, %rdx
movl $1, %ecx
movq %rdi, %rsi
movq %rbx, %rdi
call cudaMemcpy@PLT
movl %r13d, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl %r15d, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L79
.L76:
movl %r15d, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 8(%rsp)
movl $1, 12(%rsp)
movl $1, 16(%rsp)
movl $0, %r9d
movl $0, %r8d
movq 20(%rsp), %rdx
movl $1, %ecx
movq 8(%rsp), %rdi
movl $1, %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L77:
movl $8, %edi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movl $4, %edx
movq %r12, %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
leaq 4(%rbx), %rdi
movl $2, %ecx
movl $4, %edx
movq %rbp, %rsi
call cudaMemcpy@PLT
movq %rbx, %rax
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
movq %r14, %rcx
movq %rbp, %rdx
movq %r12, %rsi
movq %rbx, %rdi
call _Z35__device_stub__Z9block_sumPKfPfS1_mPKfPfS1_m
jmp .L76
.L80:
movslq 104(%rsp), %rdx
movq %rbp, %rsi
movq %r12, %rdi
call _Z45__device_stub__Z22single_block_reductionPfS_mPfS_m
jmp .L77
.cfi_endproc
.LFE2076:
.size _Z3sumPfmS_S_S_iii, .-_Z3sumPfmS_S_S_iii
.section .rodata.str1.1
.LC13:
.string "Computing Parallely.\n"
.text
.globl _Z10matrixNormv
.type _Z10matrixNormv, @function
_Z10matrixNormv:
.LFB2077:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 24(%rsp)
xorl %eax, %eax
leaq .LC13(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
movl N(%rip), %eax
testb $15, %al
setne %dl
movzbl %dl, %edx
cltq
shrq $4, %rax
leaq (%rdx,%rax), %r14
pxor %xmm0, %xmm0
cvtsi2sdq %r14, %xmm0
call log@PLT
divsd .LC14(%rip), %xmm0
movapd %xmm0, %xmm1
movsd .LC19(%rip), %xmm3
movapd %xmm0, %xmm2
andpd %xmm3, %xmm2
movsd .LC15(%rip), %xmm4
ucomisd %xmm2, %xmm4
jbe .L84
cvttsd2siq %xmm0, %rax
pxor %xmm2, %xmm2
cvtsi2sdq %rax, %xmm2
cmpnlesd %xmm2, %xmm1
movsd .LC17(%rip), %xmm4
andpd %xmm4, %xmm1
addsd %xmm2, %xmm1
andnpd %xmm0, %xmm3
orpd %xmm3, %xmm1
.L84:
movsd .LC18(%rip), %xmm0
call pow@PLT
cvttsd2sil %xmm0, %r15d
movq $0, (%rsp)
movslq %r15d, %rbx
salq $2, %rbx
movq %rsp, %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq (%rsp), %rdi
call cudaMemset@PLT
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
movq %rbx, %rdx
movl $0, %esi
movq 8(%rsp), %rdi
call cudaMemset@PLT
movq $0, 16(%rsp)
movslq N(%rip), %rsi
salq $2, %rsi
leaq 16(%rsp), %rdi
call cudaMalloc@PLT
movl N(%rip), %ecx
testl %ecx, %ecx
jle .L85
leaq A(%rip), %r13
movl $0, %r12d
movq %r13, %rbp
leaq B(%rip), %rbx
jmp .L91
.L87:
movslq %eax, %rdx
leaq (%rdi,%rdx), %r8
movss 0(%rbp,%r8,4), %xmm1
subss %xmm2, %xmm1
divss %xmm0, %xmm1
imulq $15000, %rdx, %rdx
addq %rsi, %rdx
movss %xmm1, (%rbx,%rdx,4)
.L89:
addl $1, %eax
cmpl %eax, %ecx
je .L86
.L90:
pxor %xmm5, %xmm5
ucomiss %xmm5, %xmm0
jp .L87
jne .L87
movslq %eax, %rdx
imulq $15000, %rdx, %rdx
addq %rsi, %rdx
movl $0x00000000, (%rbx,%rdx,4)
jmp .L89
.L86:
addl $1, %r12d
addq $60000, %r13
cmpl %r12d, %ecx
jle .L85
.L91:
movslq %ecx, %rsi
pushq %r15
.cfi_def_cfa_offset 104
pushq %r14
.cfi_def_cfa_offset 112
movl $16, %r9d
movq 24(%rsp), %r8
movq 16(%rsp), %rcx
movq 32(%rsp), %rdx
movq %r13, %rdi
call _Z3sumPfmS_S_S_iii
movss (%rax), %xmm4
movl N(%rip), %ecx
pxor %xmm1, %xmm1
cvtsi2ssl %ecx, %xmm1
movaps %xmm4, %xmm2
divss %xmm1, %xmm2
movaps %xmm2, %xmm0
mulss %xmm2, %xmm0
mulss %xmm1, %xmm0
addss 4(%rax), %xmm0
movaps %xmm2, %xmm3
addss %xmm2, %xmm3
mulss %xmm4, %xmm3
subss %xmm3, %xmm0
divss %xmm1, %xmm0
addq $16, %rsp
.cfi_def_cfa_offset 96
testl %ecx, %ecx
jle .L86
movl $0, %eax
movslq %r12d, %rsi
imulq $15000, %rsi, %rdi
jmp .L90
.L85:
movq (%rsp), %rdi
call cudaFree@PLT
movq 8(%rsp), %rdi
call cudaFree@PLT
movq 16(%rsp), %rdi
call cudaFree@PLT
movq 24(%rsp), %rax
subq %fs:40, %rax
jne .L97
addq $40, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L97:
.cfi_restore_state
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2077:
.size _Z10matrixNormv, .-_Z10matrixNormv
.section .rodata.str1.1
.LC20:
.string "\nStarting clock.\n"
.LC21:
.string "Stopped clock.\n"
.LC23:
.string "\nElapsed time = %g ms.\n"
.section .rodata.str1.8
.align 8
.LC25:
.string "(CPU times are accurate to the nearest %g ms)\n"
.align 8
.LC27:
.string "My total CPU time for parent = %g ms.\n"
.align 8
.LC28:
.string "My system CPU time for parent = %g ms.\n"
.align 8
.LC29:
.string "My total CPU time for child processes = %g ms.\n"
.align 8
.LC30:
.string "--------------------------------------------\n"
.text
.globl main
.type main, @function
main:
.LFB2075:
.cfi_startproc
endbr64
pushq %r12
.cfi_def_cfa_offset 16
.cfi_offset 12, -16
pushq %rbp
.cfi_def_cfa_offset 24
.cfi_offset 6, -24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset 3, -32
addq $-128, %rsp
.cfi_def_cfa_offset 160
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
call _Z10parametersiPPc
call _Z17initialize_inputsv
call _Z12print_inputsv
leaq .LC20(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
leaq 8(%rsp), %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
call gettimeofday@PLT
leaq 48(%rsp), %rdi
call times@PLT
call _Z10matrixNormv
leaq 32(%rsp), %rdi
movq %rbx, %rsi
call gettimeofday@PLT
leaq 80(%rsp), %rdi
call times@PLT
leaq .LC21(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
imulq $1000000, 16(%rsp), %r12
movq 40(%rsp), %rbx
imulq $1000000, 32(%rsp), %rbp
subq 24(%rsp), %rbp
call _Z7print_Bv
leaq (%rbx,%rbp), %rax
subq %r12, %rax
js .L99
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
.L100:
divss .LC22(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC23(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movsd .LC24(%rip), %xmm0
leaq .LC25(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
addq 80(%rsp), %rax
subq 56(%rsp), %rax
subq 48(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC26(%rip), %xmm0
mulss .LC22(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC27(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 88(%rsp), %rax
subq 56(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC26(%rip), %xmm0
mulss .LC22(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC28(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq 104(%rsp), %rax
addq 96(%rsp), %rax
subq 72(%rsp), %rax
subq 64(%rsp), %rax
pxor %xmm0, %xmm0
cvtsi2ssq %rax, %xmm0
divss .LC26(%rip), %xmm0
mulss .LC22(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
leaq .LC29(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
leaq .LC30(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $0, %edi
call exit@PLT
.L99:
movq %rax, %rdx
shrq %rdx
andl $1, %eax
orq %rax, %rdx
pxor %xmm0, %xmm0
cvtsi2ssq %rdx, %xmm0
addss %xmm0, %xmm0
jmp .L100
.cfi_endproc
.LFE2075:
.size main, .-main
.section .rodata.str1.8
.align 8
.LC31:
.string "_Z22single_block_reductionPfS_m"
.section .rodata.str1.1
.LC32:
.string "_Z9block_sumPKfPfS1_m"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2108:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC31(%rip), %rdx
movq %rdx, %rcx
leaq _Z22single_block_reductionPfS_m(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC32(%rip), %rdx
movq %rdx, %rcx
leaq _Z9block_sumPKfPfS1_m(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2108:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.globl B
.bss
.align 32
.type B, @object
.size B, 900000000
B:
.zero 900000000
.globl A
.align 32
.type A, @object
.size A, 900000000
A:
.zero 900000000
.globl N
.align 4
.type N, @object
.size N, 4
N:
.zero 4
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC5:
.long 939524096
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC14:
.long -17155601
.long 1072049730
.align 8
.LC15:
.long 0
.long 1127219200
.align 8
.LC17:
.long 0
.long 1072693248
.align 8
.LC18:
.long 0
.long 1073741824
.align 8
.LC19:
.long -1
.long 2147483647
.section .rodata.cst4
.align 4
.LC22:
.long 1148846080
.section .rodata.cst8
.align 8
.LC24:
.long -755914244
.long 1062232653
.section .rodata.cst4
.align 4
.LC26:
.long 1232348160
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by Sowmya Parameshwara on 11/10/16.
//
/**
*
* 1) Input is stored by transposing the matrix, so that the attributes of a column are stored in a single row. This
* will optimise the algorithm since all threads in a block will access nearby elements, while normalising.
* 2) Each row is normalised at a time for calculating standardscore, the calculated values are stored in output matrix by transposing.
* 3) Number of threads in a block is set as 16 (This value determined by checking performance for different values). The number of blocks
* is decided based on matrix size "N" and number of threads.
* 4) The contents of a row are divided among the blocks. In each block,Each thread populates one elements of the block into shared data.
* We then calculate partial sum without divergence, on the data stored in shared memory.
* 5) Once all blocks compute partial sum, we launch a kernel function on a single block by passing the calculated values from the previous step.
* This will calculate the final sum and final squared sum. To this final block we ensure the size of the partial sum array passed equals
the next nearest power of 2 of "the number of blocks", as partial sum algorithm works only for powers of 2.
* 6) The above data is used to calculate standard deviation for that row using the formula ((totalSquareSum + N*powf(mean, 2.0) - 2 * mean * totalSum)/(float)N)
* 7) The above value is used to calculate standard score for every element in that row.
* 8) The above step repeats for every row, calculating the standard score for all elements in the row.
*
* Steps to compile and execute on Jarvis :
* 1) qlogin -q interactive.q (Launches interactive session).
* 2) nvcc matrixNorm.cu -o matrixNorm (Compile code on jarvis).
* 3) cd hw4 (Code is available here).
* 4) ./matrixNorm 15000 4 <Argument 1 : Size of matrix, Argument 2 : Random seed value>
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#include <cuda_runtime.h>
/* Program Parameters */
#define MAXN 15000 /* Max value of N */
int N; /* Matrix size */
/* Matrices */
volatile float A[MAXN][MAXN], B[MAXN][MAXN];
/* junk */
#define randm() 4|2[uid]&3
/* Prototype */
void matrixNorm();
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
if (argc == 3) {
seed = atoi(argv[2]);
srand(seed);
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
if (N < 1 || N > MAXN) {
printf("N = %i is out of range.\n", N);
exit(0);
}
}
else {
printf("Usage: %s <matrix_dimension> [random seed]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
printf("\nInitializing...\n");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (col = 0; col < N; col++) {
for (row = 0; row < N; row++) {
printf("%5.2f%s", A[row][col], (row < N-1) ? ", " : ";\n\t");
}
}
}
}
void print_B() {
int row, col;
if (N < 10) {
printf("\nB =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%1.10f%s", B[row][col], (col < N-1) ? ", " : ";\n\t");
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
clock_t etstart2, etstop2; /* Elapsed times using times() */
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop; /* CPU times for my processes */
/* Process program parameters */
parameters(argc, argv);
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\nStarting clock.\n");
gettimeofday(&etstart, &tzdummy);
etstart2 = times(&cputstart);
/* Gaussian Elimination */
matrixNorm();
/* Stop Clock */
gettimeofday(&etstop, &tzdummy);
etstop2 = times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display output */
print_B();
/* Display timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
/**
* Method to calculate the partial sum without divergence in all the blocks.
*/
__global__ void block_sum(const float *hostInput, float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[1024];
__shared__ float sharedSquareData[1024];
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
if(i < n) {
x = hostInput[i];
}
sharedSumData[tx] = x;
sharedSquareData[tx] = x*x;
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result of this block
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[blockIdx.x] = sharedSumData[0];
squareResults[blockIdx.x] = sharedSquareData[0];
}
}
/**
* Method to calculate the sum of the results calculated from all the blocks in the previous step.
*/
__global__ void single_block_reduction(float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[256];
__shared__ float sharedSquareData[256];
int tx = threadIdx.x;
if(tx < n) {
sharedSumData[tx] = sumResults[tx];
sharedSquareData[tx] = squareResults[tx];
}
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = n/2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[0] = sharedSumData[0];
squareResults[0] = sharedSquareData[0];
}
}
float* sum (float *hostInput, size_t n, float *deviceMatrixA, float *sumResults, float *squareResults,int numOfThreadsPerBlock,int numOfBlocks,int next) {
cudaMemcpy( deviceMatrixA, hostInput, sizeof(float) * N, cudaMemcpyHostToDevice );
/* dim3 dimGrid(numOfBlocks, 1, 1);
dim3 dimBlock(numOfThreadsPerBlock, 1, 1);*/
block_sum<<<numOfBlocks,numOfThreadsPerBlock>>> (deviceMatrixA, sumResults, squareResults, n);
/* float *sumResultsInput = 0;
float *squareResultsInput = 0;
cudaMalloc((void**)&sumResultsInput, sizeof(float) * next);
cudaMemset(sumResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(sumResultsInput, sumResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice );
cudaMalloc((void**)&squareResultsInput, sizeof(float) * next);
cudaMemset(squareResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(squareResultsInput, squareResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice ); */
single_block_reduction<<<1,numOfBlocks>>>(sumResults,squareResults,next);
float * results = (float *)malloc(sizeof(float) * 2);
cudaMemcpy(&results[0], &sumResults[0], sizeof(float) , cudaMemcpyDeviceToHost );
cudaMemcpy(&results[1], &squareResults[0], sizeof(float) , cudaMemcpyDeviceToHost );
return results;
}
void matrixNorm() {
int row, col;
float mu, sigma;
printf("Computing Parallely.\n");
size_t numOfThreadsPerBlock = 16;
size_t numOfBlocks = N/numOfThreadsPerBlock + (((N)%numOfThreadsPerBlock) ? 1 : 0);
int next = pow(2, ceil(log(numOfBlocks)/log(2)));
float *sumResults = 0;
cudaMalloc((void**)&sumResults, sizeof(float) * (next));
cudaMemset(sumResults, 0.0, sizeof(float) * next);
float *squareResults = 0;
cudaMalloc((void**)&squareResults, sizeof(float) * (next));
cudaMemset(squareResults, 0.0, sizeof(float) * next);
float *deviceMatrixA = 0;
cudaMalloc( (void**)&deviceMatrixA, sizeof(float) * N);
for (row=0; row < N; row++) {
mu = 0.0;
float *hostResults;
hostResults = sum ((float *)A[row], N, deviceMatrixA, sumResults, squareResults,numOfThreadsPerBlock,numOfBlocks,next);
mu = hostResults[0] / (float) N;
sigma = (hostResults[1] + N*powf(mu, 2.0) - 2 * mu * hostResults[0])/(float)N;
for (col=0; col < N; col++) {
if (sigma == 0.0) {
B[col][row] = 0.0;
} else {
B[col][row] = (A[row][col] - mu) / sigma;
}
}
}
cudaFree(sumResults);
cudaFree(squareResults);
cudaFree(deviceMatrixA);
} | //
// Created by Sowmya Parameshwara on 11/10/16.
//
/**
*
* 1) Input is stored by transposing the matrix, so that the attributes of a column are stored in a single row. This
* will optimise the algorithm since all threads in a block will access nearby elements, while normalising.
* 2) Each row is normalised at a time for calculating standardscore, the calculated values are stored in output matrix by transposing.
* 3) Number of threads in a block is set as 16 (This value determined by checking performance for different values). The number of blocks
* is decided based on matrix size "N" and number of threads.
* 4) The contents of a row are divided among the blocks. In each block,Each thread populates one elements of the block into shared data.
* We then calculate partial sum without divergence, on the data stored in shared memory.
* 5) Once all blocks compute partial sum, we launch a kernel function on a single block by passing the calculated values from the previous step.
* This will calculate the final sum and final squared sum. To this final block we ensure the size of the partial sum array passed equals
the next nearest power of 2 of "the number of blocks", as partial sum algorithm works only for powers of 2.
* 6) The above data is used to calculate standard deviation for that row using the formula ((totalSquareSum + N*powf(mean, 2.0) - 2 * mean * totalSum)/(float)N)
* 7) The above value is used to calculate standard score for every element in that row.
* 8) The above step repeats for every row, calculating the standard score for all elements in the row.
*
* Steps to compile and execute on Jarvis :
* 1) qlogin -q interactive.q (Launches interactive session).
* 2) nvcc matrixNorm.cu -o matrixNorm (Compile code on jarvis).
* 3) cd hw4 (Code is available here).
* 4) ./matrixNorm 15000 4 <Argument 1 : Size of matrix, Argument 2 : Random seed value>
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
/* Program Parameters */
#define MAXN 15000 /* Max value of N */
int N; /* Matrix size */
/* Matrices */
volatile float A[MAXN][MAXN], B[MAXN][MAXN];
/* junk */
#define randm() 4|2[uid]&3
/* Prototype */
void matrixNorm();
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
if (argc == 3) {
seed = atoi(argv[2]);
srand(seed);
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
if (N < 1 || N > MAXN) {
printf("N = %i is out of range.\n", N);
exit(0);
}
}
else {
printf("Usage: %s <matrix_dimension> [random seed]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
printf("\nInitializing...\n");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (col = 0; col < N; col++) {
for (row = 0; row < N; row++) {
printf("%5.2f%s", A[row][col], (row < N-1) ? ", " : ";\n\t");
}
}
}
}
void print_B() {
int row, col;
if (N < 10) {
printf("\nB =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%1.10f%s", B[row][col], (col < N-1) ? ", " : ";\n\t");
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
clock_t etstart2, etstop2; /* Elapsed times using times() */
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop; /* CPU times for my processes */
/* Process program parameters */
parameters(argc, argv);
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\nStarting clock.\n");
gettimeofday(&etstart, &tzdummy);
etstart2 = times(&cputstart);
/* Gaussian Elimination */
matrixNorm();
/* Stop Clock */
gettimeofday(&etstop, &tzdummy);
etstop2 = times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display output */
print_B();
/* Display timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
/**
* Method to calculate the partial sum without divergence in all the blocks.
*/
__global__ void block_sum(const float *hostInput, float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[1024];
__shared__ float sharedSquareData[1024];
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
if(i < n) {
x = hostInput[i];
}
sharedSumData[tx] = x;
sharedSquareData[tx] = x*x;
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result of this block
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[blockIdx.x] = sharedSumData[0];
squareResults[blockIdx.x] = sharedSquareData[0];
}
}
/**
* Method to calculate the sum of the results calculated from all the blocks in the previous step.
*/
__global__ void single_block_reduction(float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[256];
__shared__ float sharedSquareData[256];
int tx = threadIdx.x;
if(tx < n) {
sharedSumData[tx] = sumResults[tx];
sharedSquareData[tx] = squareResults[tx];
}
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = n/2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[0] = sharedSumData[0];
squareResults[0] = sharedSquareData[0];
}
}
float* sum (float *hostInput, size_t n, float *deviceMatrixA, float *sumResults, float *squareResults,int numOfThreadsPerBlock,int numOfBlocks,int next) {
hipMemcpy( deviceMatrixA, hostInput, sizeof(float) * N, hipMemcpyHostToDevice );
/* dim3 dimGrid(numOfBlocks, 1, 1);
dim3 dimBlock(numOfThreadsPerBlock, 1, 1);*/
block_sum<<<numOfBlocks,numOfThreadsPerBlock>>> (deviceMatrixA, sumResults, squareResults, n);
/* float *sumResultsInput = 0;
float *squareResultsInput = 0;
cudaMalloc((void**)&sumResultsInput, sizeof(float) * next);
cudaMemset(sumResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(sumResultsInput, sumResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice );
cudaMalloc((void**)&squareResultsInput, sizeof(float) * next);
cudaMemset(squareResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(squareResultsInput, squareResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice ); */
single_block_reduction<<<1,numOfBlocks>>>(sumResults,squareResults,next);
float * results = (float *)malloc(sizeof(float) * 2);
hipMemcpy(&results[0], &sumResults[0], sizeof(float) , hipMemcpyDeviceToHost );
hipMemcpy(&results[1], &squareResults[0], sizeof(float) , hipMemcpyDeviceToHost );
return results;
}
void matrixNorm() {
int row, col;
float mu, sigma;
printf("Computing Parallely.\n");
size_t numOfThreadsPerBlock = 16;
size_t numOfBlocks = N/numOfThreadsPerBlock + (((N)%numOfThreadsPerBlock) ? 1 : 0);
int next = pow(2, ceil(log(numOfBlocks)/log(2)));
float *sumResults = 0;
hipMalloc((void**)&sumResults, sizeof(float) * (next));
hipMemset(sumResults, 0.0, sizeof(float) * next);
float *squareResults = 0;
hipMalloc((void**)&squareResults, sizeof(float) * (next));
hipMemset(squareResults, 0.0, sizeof(float) * next);
float *deviceMatrixA = 0;
hipMalloc( (void**)&deviceMatrixA, sizeof(float) * N);
for (row=0; row < N; row++) {
mu = 0.0;
float *hostResults;
hostResults = sum ((float *)A[row], N, deviceMatrixA, sumResults, squareResults,numOfThreadsPerBlock,numOfBlocks,next);
mu = hostResults[0] / (float) N;
sigma = (hostResults[1] + N*powf(mu, 2.0) - 2 * mu * hostResults[0])/(float)N;
for (col=0; col < N; col++) {
if (sigma == 0.0) {
B[col][row] = 0.0;
} else {
B[col][row] = (A[row][col] - mu) / sigma;
}
}
}
hipFree(sumResults);
hipFree(squareResults);
hipFree(deviceMatrixA);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | //
// Created by Sowmya Parameshwara on 11/10/16.
//
/**
*
* 1) Input is stored by transposing the matrix, so that the attributes of a column are stored in a single row. This
* will optimise the algorithm since all threads in a block will access nearby elements, while normalising.
* 2) Each row is normalised at a time for calculating standardscore, the calculated values are stored in output matrix by transposing.
* 3) Number of threads in a block is set as 16 (This value determined by checking performance for different values). The number of blocks
* is decided based on matrix size "N" and number of threads.
* 4) The contents of a row are divided among the blocks. In each block,Each thread populates one elements of the block into shared data.
* We then calculate partial sum without divergence, on the data stored in shared memory.
* 5) Once all blocks compute partial sum, we launch a kernel function on a single block by passing the calculated values from the previous step.
* This will calculate the final sum and final squared sum. To this final block we ensure the size of the partial sum array passed equals
the next nearest power of 2 of "the number of blocks", as partial sum algorithm works only for powers of 2.
* 6) The above data is used to calculate standard deviation for that row using the formula ((totalSquareSum + N*powf(mean, 2.0) - 2 * mean * totalSum)/(float)N)
* 7) The above value is used to calculate standard score for every element in that row.
* 8) The above step repeats for every row, calculating the standard score for all elements in the row.
*
* Steps to compile and execute on Jarvis :
* 1) qlogin -q interactive.q (Launches interactive session).
* 2) nvcc matrixNorm.cu -o matrixNorm (Compile code on jarvis).
* 3) cd hw4 (Code is available here).
* 4) ./matrixNorm 15000 4 <Argument 1 : Size of matrix, Argument 2 : Random seed value>
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
/* Program Parameters */
#define MAXN 15000 /* Max value of N */
int N; /* Matrix size */
/* Matrices */
volatile float A[MAXN][MAXN], B[MAXN][MAXN];
/* junk */
#define randm() 4|2[uid]&3
/* Prototype */
void matrixNorm();
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
if (argc == 3) {
seed = atoi(argv[2]);
srand(seed);
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
if (N < 1 || N > MAXN) {
printf("N = %i is out of range.\n", N);
exit(0);
}
}
else {
printf("Usage: %s <matrix_dimension> [random seed]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
printf("\nInitializing...\n");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (col = 0; col < N; col++) {
for (row = 0; row < N; row++) {
printf("%5.2f%s", A[row][col], (row < N-1) ? ", " : ";\n\t");
}
}
}
}
void print_B() {
int row, col;
if (N < 10) {
printf("\nB =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%1.10f%s", B[row][col], (col < N-1) ? ", " : ";\n\t");
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
clock_t etstart2, etstop2; /* Elapsed times using times() */
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop; /* CPU times for my processes */
/* Process program parameters */
parameters(argc, argv);
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\nStarting clock.\n");
gettimeofday(&etstart, &tzdummy);
etstart2 = times(&cputstart);
/* Gaussian Elimination */
matrixNorm();
/* Stop Clock */
gettimeofday(&etstop, &tzdummy);
etstop2 = times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display output */
print_B();
/* Display timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
/**
* Method to calculate the partial sum without divergence in all the blocks.
*/
__global__ void block_sum(const float *hostInput, float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[1024];
__shared__ float sharedSquareData[1024];
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
if(i < n) {
x = hostInput[i];
}
sharedSumData[tx] = x;
sharedSquareData[tx] = x*x;
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result of this block
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[blockIdx.x] = sharedSumData[0];
squareResults[blockIdx.x] = sharedSquareData[0];
}
}
/**
* Method to calculate the sum of the results calculated from all the blocks in the previous step.
*/
__global__ void single_block_reduction(float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[256];
__shared__ float sharedSquareData[256];
int tx = threadIdx.x;
if(tx < n) {
sharedSumData[tx] = sumResults[tx];
sharedSquareData[tx] = squareResults[tx];
}
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = n/2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[0] = sharedSumData[0];
squareResults[0] = sharedSquareData[0];
}
}
float* sum (float *hostInput, size_t n, float *deviceMatrixA, float *sumResults, float *squareResults,int numOfThreadsPerBlock,int numOfBlocks,int next) {
hipMemcpy( deviceMatrixA, hostInput, sizeof(float) * N, hipMemcpyHostToDevice );
/* dim3 dimGrid(numOfBlocks, 1, 1);
dim3 dimBlock(numOfThreadsPerBlock, 1, 1);*/
block_sum<<<numOfBlocks,numOfThreadsPerBlock>>> (deviceMatrixA, sumResults, squareResults, n);
/* float *sumResultsInput = 0;
float *squareResultsInput = 0;
cudaMalloc((void**)&sumResultsInput, sizeof(float) * next);
cudaMemset(sumResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(sumResultsInput, sumResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice );
cudaMalloc((void**)&squareResultsInput, sizeof(float) * next);
cudaMemset(squareResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(squareResultsInput, squareResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice ); */
single_block_reduction<<<1,numOfBlocks>>>(sumResults,squareResults,next);
float * results = (float *)malloc(sizeof(float) * 2);
hipMemcpy(&results[0], &sumResults[0], sizeof(float) , hipMemcpyDeviceToHost );
hipMemcpy(&results[1], &squareResults[0], sizeof(float) , hipMemcpyDeviceToHost );
return results;
}
void matrixNorm() {
int row, col;
float mu, sigma;
printf("Computing Parallely.\n");
size_t numOfThreadsPerBlock = 16;
size_t numOfBlocks = N/numOfThreadsPerBlock + (((N)%numOfThreadsPerBlock) ? 1 : 0);
int next = pow(2, ceil(log(numOfBlocks)/log(2)));
float *sumResults = 0;
hipMalloc((void**)&sumResults, sizeof(float) * (next));
hipMemset(sumResults, 0.0, sizeof(float) * next);
float *squareResults = 0;
hipMalloc((void**)&squareResults, sizeof(float) * (next));
hipMemset(squareResults, 0.0, sizeof(float) * next);
float *deviceMatrixA = 0;
hipMalloc( (void**)&deviceMatrixA, sizeof(float) * N);
for (row=0; row < N; row++) {
mu = 0.0;
float *hostResults;
hostResults = sum ((float *)A[row], N, deviceMatrixA, sumResults, squareResults,numOfThreadsPerBlock,numOfBlocks,next);
mu = hostResults[0] / (float) N;
sigma = (hostResults[1] + N*powf(mu, 2.0) - 2 * mu * hostResults[0])/(float)N;
for (col=0; col < N; col++) {
if (sigma == 0.0) {
B[col][row] = 0.0;
} else {
B[col][row] = (A[row][col] - mu) / sigma;
}
}
}
hipFree(sumResults);
hipFree(squareResults);
hipFree(deviceMatrixA);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9block_sumPKfPfS1_m
.globl _Z9block_sumPKfPfS1_m
.p2align 8
.type _Z9block_sumPKfPfS1_m,@function
_Z9block_sumPKfPfS1_m:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_mov_b32 s2, s15
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt vmcnt(0)
v_dual_mul_f32 v2, v3, v3 :: v_dual_lshlrev_b32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_2addr_stride64_b32 v1, v3, v2 offset1:16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
v_or_b32_e32 v2, 0x1000, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v3, s4, v0, 2
ds_load_2addr_stride64_b32 v[3:4], v3 offset1:16
ds_load_b32 v5, v1
ds_load_b32 v6, v2
s_waitcnt lgkmcnt(0)
v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
ds_store_b32 v1, v3
ds_store_b32 v2, v4
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v2, 0
s_load_b128 s[4:7], s[0:1], 0x8
s_lshl_b64 s[0:1], s[2:3], 2
ds_load_2addr_stride64_b32 v[0:1], v2 offset1:16
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_clause 0x1
global_store_b32 v2, v0, s[2:3]
global_store_b32 v2, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9block_sumPKfPfS1_m
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9block_sumPKfPfS1_m, .Lfunc_end0-_Z9block_sumPKfPfS1_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22single_block_reductionPfS_m
.globl _Z22single_block_reductionPfS_m
.p2align 8
.type _Z22single_block_reductionPfS_m,@function
_Z22single_block_reductionPfS_m:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[4:5], v[0:1]
s_cbranch_execz .LBB1_2
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[0:1]
global_load_b32 v3, v1, s[2:3]
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v1, v2, v3 offset1:4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s6
v_alignbit_b32 v1, s5, s4, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, 1, v1
s_cbranch_vccnz .LBB1_7
v_lshlrev_b32_e32 v2, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 0x400, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s4
v_lshrrev_b32_e32 v4, 1, v1
v_cmp_gt_u32_e32 vcc_lo, 2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v1, v4
s_cbranch_vccnz .LBB1_7
.LBB1_5:
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v0, v1
s_cbranch_execz .LBB1_4
v_add_lshl_u32 v4, v1, v0, 2
ds_load_2addr_stride64_b32 v[4:5], v4 offset1:4
ds_load_b32 v6, v2
ds_load_b32 v7, v3
s_waitcnt lgkmcnt(0)
v_dual_add_f32 v4, v4, v6 :: v_dual_add_f32 v5, v5, v7
ds_store_b32 v2, v4
ds_store_b32 v3, v5
s_branch .LBB1_4
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
v_mov_b32_e32 v2, 0
ds_load_2addr_stride64_b32 v[0:1], v2 offset1:4
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v2, v0, s[0:1]
global_store_b32 v2, v1, s[2:3]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22single_block_reductionPfS_m
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z22single_block_reductionPfS_m, .Lfunc_end1-_Z22single_block_reductionPfS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9block_sumPKfPfS1_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9block_sumPKfPfS1_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22single_block_reductionPfS_m
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z22single_block_reductionPfS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by Sowmya Parameshwara on 11/10/16.
//
/**
*
* 1) Input is stored by transposing the matrix, so that the attributes of a column are stored in a single row. This
* will optimise the algorithm since all threads in a block will access nearby elements, while normalising.
* 2) Each row is normalised at a time for calculating standardscore, the calculated values are stored in output matrix by transposing.
* 3) Number of threads in a block is set as 16 (This value determined by checking performance for different values). The number of blocks
* is decided based on matrix size "N" and number of threads.
* 4) The contents of a row are divided among the blocks. In each block,Each thread populates one elements of the block into shared data.
* We then calculate partial sum without divergence, on the data stored in shared memory.
* 5) Once all blocks compute partial sum, we launch a kernel function on a single block by passing the calculated values from the previous step.
* This will calculate the final sum and final squared sum. To this final block we ensure the size of the partial sum array passed equals
the next nearest power of 2 of "the number of blocks", as partial sum algorithm works only for powers of 2.
* 6) The above data is used to calculate standard deviation for that row using the formula ((totalSquareSum + N*powf(mean, 2.0) - 2 * mean * totalSum)/(float)N)
* 7) The above value is used to calculate standard score for every element in that row.
* 8) The above step repeats for every row, calculating the standard score for all elements in the row.
*
* Steps to compile and execute on Jarvis :
* 1) qlogin -q interactive.q (Launches interactive session).
* 2) nvcc matrixNorm.cu -o matrixNorm (Compile code on jarvis).
* 3) cd hw4 (Code is available here).
* 4) ./matrixNorm 15000 4 <Argument 1 : Size of matrix, Argument 2 : Random seed value>
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <math.h>
#include <sys/types.h>
#include <sys/times.h>
#include <sys/time.h>
#include <time.h>
#include <hip/hip_runtime.h>
/* Program Parameters */
#define MAXN 15000 /* Max value of N */
int N; /* Matrix size */
/* Matrices */
volatile float A[MAXN][MAXN], B[MAXN][MAXN];
/* junk */
#define randm() 4|2[uid]&3
/* Prototype */
void matrixNorm();
/* returns a seed for srand based on the time */
unsigned int time_seed() {
struct timeval t;
struct timezone tzdummy;
gettimeofday(&t, &tzdummy);
return (unsigned int)(t.tv_usec);
}
/* Set the program parameters from the command-line arguments */
void parameters(int argc, char **argv) {
int seed = 0; /* Random seed */
char uid[32]; /*User name */
/* Read command-line arguments */
srand(time_seed()); /* Randomize */
if (argc == 3) {
seed = atoi(argv[2]);
srand(seed);
printf("Random seed = %i\n", seed);
}
if (argc >= 2) {
N = atoi(argv[1]);
if (N < 1 || N > MAXN) {
printf("N = %i is out of range.\n", N);
exit(0);
}
}
else {
printf("Usage: %s <matrix_dimension> [random seed]\n",
argv[0]);
exit(0);
}
/* Print parameters */
printf("\nMatrix dimension N = %i.\n", N);
}
/* Initialize A and B*/
void initialize_inputs() {
int row, col;
printf("\nInitializing...\n");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
A[row][col] = (float)rand() / 32768.0;
B[row][col] = 0.0;
}
}
}
/* Print input matrices */
void print_inputs() {
int row, col;
if (N < 10) {
printf("\nA =\n\t");
for (col = 0; col < N; col++) {
for (row = 0; row < N; row++) {
printf("%5.2f%s", A[row][col], (row < N-1) ? ", " : ";\n\t");
}
}
}
}
void print_B() {
int row, col;
if (N < 10) {
printf("\nB =\n\t");
for (row = 0; row < N; row++) {
for (col = 0; col < N; col++) {
printf("%1.10f%s", B[row][col], (col < N-1) ? ", " : ";\n\t");
}
}
}
}
int main(int argc, char **argv) {
/* Timing variables */
struct timeval etstart, etstop; /* Elapsed times using gettimeofday() */
struct timezone tzdummy;
clock_t etstart2, etstop2; /* Elapsed times using times() */
unsigned long long usecstart, usecstop;
struct tms cputstart, cputstop; /* CPU times for my processes */
/* Process program parameters */
parameters(argc, argv);
initialize_inputs();
/* Print input matrices */
print_inputs();
/* Start Clock */
printf("\nStarting clock.\n");
gettimeofday(&etstart, &tzdummy);
etstart2 = times(&cputstart);
/* Gaussian Elimination */
matrixNorm();
/* Stop Clock */
gettimeofday(&etstop, &tzdummy);
etstop2 = times(&cputstop);
printf("Stopped clock.\n");
usecstart = (unsigned long long)etstart.tv_sec * 1000000 + etstart.tv_usec;
usecstop = (unsigned long long)etstop.tv_sec * 1000000 + etstop.tv_usec;
/* Display output */
print_B();
/* Display timing results */
printf("\nElapsed time = %g ms.\n",
(float)(usecstop - usecstart)/(float)1000);
printf("(CPU times are accurate to the nearest %g ms)\n",
1.0/(float)CLOCKS_PER_SEC * 1000.0);
printf("My total CPU time for parent = %g ms.\n",
(float)( (cputstop.tms_utime + cputstop.tms_stime) -
(cputstart.tms_utime + cputstart.tms_stime) ) /
(float)CLOCKS_PER_SEC * 1000);
printf("My system CPU time for parent = %g ms.\n",
(float)(cputstop.tms_stime - cputstart.tms_stime) /
(float)CLOCKS_PER_SEC * 1000);
printf("My total CPU time for child processes = %g ms.\n",
(float)( (cputstop.tms_cutime + cputstop.tms_cstime) -
(cputstart.tms_cutime + cputstart.tms_cstime) ) /
(float)CLOCKS_PER_SEC * 1000);
/* Contrary to the man pages, this appears not to include the parent */
printf("--------------------------------------------\n");
exit(0);
}
/**
* Method to calculate the partial sum without divergence in all the blocks.
*/
__global__ void block_sum(const float *hostInput, float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[1024];
__shared__ float sharedSquareData[1024];
int i = blockIdx.x * blockDim.x + threadIdx.x;
int tx = threadIdx.x;
float x = 0;
if(i < n) {
x = hostInput[i];
}
sharedSumData[tx] = x;
sharedSquareData[tx] = x*x;
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = blockDim.x / 2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result of this block
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[blockIdx.x] = sharedSumData[0];
squareResults[blockIdx.x] = sharedSquareData[0];
}
}
/**
* Method to calculate the sum of the results calculated from all the blocks in the previous step.
*/
__global__ void single_block_reduction(float *sumResults, float *squareResults, const size_t n)
{
__shared__ float sharedSumData[256];
__shared__ float sharedSquareData[256];
int tx = threadIdx.x;
if(tx < n) {
sharedSumData[tx] = sumResults[tx];
sharedSquareData[tx] = squareResults[tx];
}
__syncthreads();
// block-wide reduction in _shared_ mem
for(int offset = n/2;
offset > 0;
offset >>= 1)
{
if(tx < offset)
{
sharedSumData[tx] += sharedSumData[tx + offset];
sharedSquareData[tx] += sharedSquareData[tx + offset];
}
__syncthreads();
}
// finally, thread 0 writes the calculated result
if(threadIdx.x == 0)
{
// note that the result is per-block
// not per-thread
sumResults[0] = sharedSumData[0];
squareResults[0] = sharedSquareData[0];
}
}
float* sum (float *hostInput, size_t n, float *deviceMatrixA, float *sumResults, float *squareResults,int numOfThreadsPerBlock,int numOfBlocks,int next) {
hipMemcpy( deviceMatrixA, hostInput, sizeof(float) * N, hipMemcpyHostToDevice );
/* dim3 dimGrid(numOfBlocks, 1, 1);
dim3 dimBlock(numOfThreadsPerBlock, 1, 1);*/
block_sum<<<numOfBlocks,numOfThreadsPerBlock>>> (deviceMatrixA, sumResults, squareResults, n);
/* float *sumResultsInput = 0;
float *squareResultsInput = 0;
cudaMalloc((void**)&sumResultsInput, sizeof(float) * next);
cudaMemset(sumResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(sumResultsInput, sumResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice );
cudaMalloc((void**)&squareResultsInput, sizeof(float) * next);
cudaMemset(squareResultsInput, 0.0, sizeof(float) * next);
cudaMemcpy(squareResultsInput, squareResults, sizeof(float) * numOfBlocks , cudaMemcpyDeviceToDevice ); */
single_block_reduction<<<1,numOfBlocks>>>(sumResults,squareResults,next);
float * results = (float *)malloc(sizeof(float) * 2);
hipMemcpy(&results[0], &sumResults[0], sizeof(float) , hipMemcpyDeviceToHost );
hipMemcpy(&results[1], &squareResults[0], sizeof(float) , hipMemcpyDeviceToHost );
return results;
}
void matrixNorm() {
int row, col;
float mu, sigma;
printf("Computing Parallely.\n");
size_t numOfThreadsPerBlock = 16;
size_t numOfBlocks = N/numOfThreadsPerBlock + (((N)%numOfThreadsPerBlock) ? 1 : 0);
int next = pow(2, ceil(log(numOfBlocks)/log(2)));
float *sumResults = 0;
hipMalloc((void**)&sumResults, sizeof(float) * (next));
hipMemset(sumResults, 0.0, sizeof(float) * next);
float *squareResults = 0;
hipMalloc((void**)&squareResults, sizeof(float) * (next));
hipMemset(squareResults, 0.0, sizeof(float) * next);
float *deviceMatrixA = 0;
hipMalloc( (void**)&deviceMatrixA, sizeof(float) * N);
for (row=0; row < N; row++) {
mu = 0.0;
float *hostResults;
hostResults = sum ((float *)A[row], N, deviceMatrixA, sumResults, squareResults,numOfThreadsPerBlock,numOfBlocks,next);
mu = hostResults[0] / (float) N;
sigma = (hostResults[1] + N*powf(mu, 2.0) - 2 * mu * hostResults[0])/(float)N;
for (col=0; col < N; col++) {
if (sigma == 0.0) {
B[col][row] = 0.0;
} else {
B[col][row] = (A[row][col] - mu) / sigma;
}
}
}
hipFree(sumResults);
hipFree(squareResults);
hipFree(deviceMatrixA);
} | .text
.file "matrixNorm.hip"
.globl _Z9time_seedv # -- Begin function _Z9time_seedv
.p2align 4, 0x90
.type _Z9time_seedv,@function
_Z9time_seedv: # @_Z9time_seedv
.cfi_startproc
# %bb.0:
subq $24, %rsp
.cfi_def_cfa_offset 32
movq %rsp, %rdi
leaq 16(%rsp), %rsi
callq gettimeofday
movl 8(%rsp), %eax
addq $24, %rsp
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z9time_seedv, .Lfunc_end0-_Z9time_seedv
.cfi_endproc
# -- End function
.globl _Z10parametersiPPc # -- Begin function _Z10parametersiPPc
.p2align 4, 0x90
.type _Z10parametersiPPc,@function
_Z10parametersiPPc: # @_Z10parametersiPPc
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
subq $32, %rsp
.cfi_def_cfa_offset 64
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
leaq 8(%rsp), %rdi
leaq 24(%rsp), %rsi
callq gettimeofday
movl 16(%rsp), %edi
callq srand
cmpl $3, %ebp
jne .LBB1_2
# %bb.1:
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movl %r14d, %edi
callq srand
movl $.L.str, %edi
movl %r14d, %esi
xorl %eax, %eax
callq printf
.LBB1_2:
cmpl $2, %ebp
jl .LBB1_5
# %bb.3:
movq 8(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movl %eax, N(%rip)
leal -15001(%rax), %ecx
cmpl $-15001, %ecx # imm = 0xC567
jbe .LBB1_4
# %bb.6:
movl $.L.str.3, %edi
movl %eax, %esi
xorl %eax, %eax
addq $32, %rsp
.cfi_def_cfa_offset 32
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
jmp printf # TAILCALL
.LBB1_5:
.cfi_def_cfa_offset 64
movq (%rbx), %rsi
movl $.L.str.2, %edi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.LBB1_4:
movl $.L.str.1, %edi
movl %eax, %esi
xorl %eax, %eax
callq printf
xorl %edi, %edi
callq exit
.Lfunc_end1:
.size _Z10parametersiPPc, .Lfunc_end1-_Z10parametersiPPc
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z17initialize_inputsv
.LCPI2_0:
.long 0x38000000 # float 3.05175781E-5
.text
.globl _Z17initialize_inputsv
.p2align 4, 0x90
.type _Z17initialize_inputsv,@function
_Z17initialize_inputsv: # @_Z17initialize_inputsv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %rbx
.cfi_def_cfa_offset 32
.cfi_offset %rbx, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr, %edi
callq puts@PLT
cmpl $0, N(%rip)
jle .LBB2_6
# %bb.1: # %.preheader.preheader
xorl %ebx, %ebx
xorl %r14d, %r14d
jmp .LBB2_2
.p2align 4, 0x90
.LBB2_5: # %._crit_edge
# in Loop: Header=BB2_2 Depth=1
incq %r14
movslq N(%rip), %rax
addq $60000, %rbx # imm = 0xEA60
cmpq %rax, %r14
jge .LBB2_6
.LBB2_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB2_4 Depth 2
cmpl $0, N(%rip)
jle .LBB2_5
# %bb.3: # %.lr.ph.preheader
# in Loop: Header=BB2_2 Depth=1
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB2_4: # %.lr.ph
# Parent Loop BB2_2 Depth=1
# => This Inner Loop Header: Depth=2
callq rand
movss .LCPI2_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
xorps %xmm0, %xmm0
cvtsi2ss %eax, %xmm0
mulss %xmm1, %xmm0
movss %xmm0, A(%rbx,%r15,4)
movl $0, B(%rbx,%r15,4)
incq %r15
movslq N(%rip), %rax
cmpq %rax, %r15
jl .LBB2_4
jmp .LBB2_5
.LBB2_6: # %._crit_edge11
popq %rbx
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end2:
.size _Z17initialize_inputsv, .Lfunc_end2-_Z17initialize_inputsv
.cfi_endproc
# -- End function
.globl _Z12print_inputsv # -- Begin function _Z12print_inputsv
.p2align 4, 0x90
.type _Z12print_inputsv,@function
_Z12print_inputsv: # @_Z12print_inputsv
.cfi_startproc
# %bb.0:
cmpl $9, N(%rip)
jg .LBB3_8
# %bb.1:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.5, %edi
xorl %eax, %eax
callq printf
cmpl $0, N(%rip)
jle .LBB3_7
# %bb.2: # %.preheader.preheader
movl $A, %ebx
xorl %r14d, %r14d
movl $.L.str.7, %r15d
jmp .LBB3_3
.p2align 4, 0x90
.LBB3_6: # %._crit_edge
# in Loop: Header=BB3_3 Depth=1
incq %r14
movslq N(%rip), %rax
addq $4, %rbx
cmpq %rax, %r14
jge .LBB3_7
.LBB3_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_5 Depth 2
movl N(%rip), %eax
testl %eax, %eax
jle .LBB3_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB3_3 Depth=1
movq %rbx, %r12
xorl %r13d, %r13d
.p2align 4, 0x90
.LBB3_5: # %.lr.ph
# Parent Loop BB3_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r12), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
decl %eax
cltq
cmpq %rax, %r13
movl $.L.str.8, %esi
cmovlq %r15, %rsi
movl $.L.str.6, %edi
movb $1, %al
callq printf
incq %r13
movslq N(%rip), %rax
addq $60000, %r12 # imm = 0xEA60
cmpq %rax, %r13
jl .LBB3_5
jmp .LBB3_6
.LBB3_7:
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r13
.cfi_restore %r14
.cfi_restore %r15
.LBB3_8: # %.loopexit
retq
.Lfunc_end3:
.size _Z12print_inputsv, .Lfunc_end3-_Z12print_inputsv
.cfi_endproc
# -- End function
.globl _Z7print_Bv # -- Begin function _Z7print_Bv
.p2align 4, 0x90
.type _Z7print_Bv,@function
_Z7print_Bv: # @_Z7print_Bv
.cfi_startproc
# %bb.0:
cmpl $9, N(%rip)
jg .LBB4_8
# %bb.1:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r12
.cfi_def_cfa_offset 32
pushq %rbx
.cfi_def_cfa_offset 40
pushq %rax
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -40
.cfi_offset %r12, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.L.str.9, %edi
xorl %eax, %eax
callq printf
cmpl $0, N(%rip)
jle .LBB4_7
# %bb.2: # %.preheader.preheader
movl $B, %ebx
xorl %r14d, %r14d
movl $.L.str.7, %r15d
jmp .LBB4_3
.p2align 4, 0x90
.LBB4_6: # %._crit_edge
# in Loop: Header=BB4_3 Depth=1
incq %r14
movslq N(%rip), %rax
addq $60000, %rbx # imm = 0xEA60
cmpq %rax, %r14
jge .LBB4_7
.LBB4_3: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_5 Depth 2
movl N(%rip), %eax
testl %eax, %eax
jle .LBB4_6
# %bb.4: # %.lr.ph.preheader
# in Loop: Header=BB4_3 Depth=1
xorl %r12d, %r12d
.p2align 4, 0x90
.LBB4_5: # %.lr.ph
# Parent Loop BB4_3 Depth=1
# => This Inner Loop Header: Depth=2
movss (%rbx,%r12,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
decl %eax
cltq
cmpq %rax, %r12
movl $.L.str.8, %esi
cmovlq %r15, %rsi
movl $.L.str.10, %edi
movb $1, %al
callq printf
incq %r12
movslq N(%rip), %rax
cmpq %rax, %r12
jl .LBB4_5
jmp .LBB4_6
.LBB4_7:
addq $8, %rsp
.cfi_def_cfa_offset 40
popq %rbx
.cfi_def_cfa_offset 32
popq %r12
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
.cfi_restore %rbx
.cfi_restore %r12
.cfi_restore %r14
.cfi_restore %r15
.LBB4_8: # %.loopexit
retq
.Lfunc_end4:
.size _Z7print_Bv, .Lfunc_end4-_Z7print_Bv
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI5_0:
.long 0x447a0000 # float 1000
.LCPI5_2:
.long 0x49742400 # float 1.0E+6
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3f50624dd2f1a9fc # double 0.001
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %r14
.cfi_def_cfa_offset 16
pushq %rbx
.cfi_def_cfa_offset 24
subq $104, %rsp
.cfi_def_cfa_offset 128
.cfi_offset %rbx, -24
.cfi_offset %r14, -16
callq _Z10parametersiPPc
callq _Z17initialize_inputsv
callq _Z12print_inputsv
movl $.Lstr.1, %edi
callq puts@PLT
leaq 16(%rsp), %rdi
leaq 96(%rsp), %rbx
movq %rbx, %rsi
callq gettimeofday
leaq 64(%rsp), %rdi
callq times
callq _Z10matrixNormv
movq %rsp, %rdi
movq %rbx, %rsi
callq gettimeofday
leaq 32(%rsp), %rdi
callq times
movl $.Lstr.2, %edi
callq puts@PLT
movq (%rsp), %rbx
movq 8(%rsp), %r14
subq 16(%rsp), %rbx
subq 24(%rsp), %r14
callq _Z7print_Bv
imulq $1000000, %rbx, %rax # imm = 0xF4240
addq %r14, %rax
js .LBB5_1
# %bb.2:
cvtsi2ss %rax, %xmm0
jmp .LBB5_3
.LBB5_1:
movq %rax, %rcx
shrq %rcx
andl $1, %eax
orq %rcx, %rax
cvtsi2ss %rax, %xmm0
addss %xmm0, %xmm0
.LBB5_3:
divss .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.13, %edi
movb $1, %al
callq printf
movsd .LCPI5_1(%rip), %xmm0 # xmm0 = mem[0],zero
movl $.L.str.14, %edi
movb $1, %al
callq printf
movq 40(%rsp), %rbx
movq 72(%rsp), %r14
movq 32(%rsp), %rax
addq %rbx, %rax
movq 64(%rsp), %rcx
addq %r14, %rcx
subq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI5_2(%rip), %xmm0
mulss .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.15, %edi
movb $1, %al
callq printf
subq %r14, %rbx
xorps %xmm0, %xmm0
cvtsi2ss %rbx, %xmm0
divss .LCPI5_2(%rip), %xmm0
mulss .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.16, %edi
movb $1, %al
callq printf
movq 56(%rsp), %rax
movq 80(%rsp), %rcx
addq 48(%rsp), %rax
addq 88(%rsp), %rcx
subq %rcx, %rax
xorps %xmm0, %xmm0
cvtsi2ss %rax, %xmm0
divss .LCPI5_2(%rip), %xmm0
mulss .LCPI5_0(%rip), %xmm0
cvtss2sd %xmm0, %xmm0
movl $.L.str.17, %edi
movb $1, %al
callq printf
movl $.Lstr.3, %edi
callq puts@PLT
xorl %edi, %edi
callq exit
.Lfunc_end5:
.size main, .Lfunc_end5-main
.cfi_endproc
# -- End function
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z10matrixNormv
.LCPI6_0:
.quad 0x3fe62e42fefa39ef # double 0.69314718055994529
.text
.globl _Z10matrixNormv
.p2align 4, 0x90
.type _Z10matrixNormv,@function
_Z10matrixNormv: # @_Z10matrixNormv
.cfi_startproc
# %bb.0:
pushq %r15
.cfi_def_cfa_offset 16
pushq %r14
.cfi_def_cfa_offset 24
pushq %r13
.cfi_def_cfa_offset 32
pushq %r12
.cfi_def_cfa_offset 40
pushq %rbx
.cfi_def_cfa_offset 48
subq $32, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -48
.cfi_offset %r12, -40
.cfi_offset %r13, -32
.cfi_offset %r14, -24
.cfi_offset %r15, -16
movl $.Lstr.4, %edi
callq puts@PLT
movslq N(%rip), %rax
movq %rax, %r14
shrq $4, %r14
andl $15, %eax
cmpq $1, %rax
sbbq $-1, %r14
cvtsi2sd %r14, %xmm0
callq log
divsd .LCPI6_0(%rip), %xmm0
callq ceil@PLT
callq exp2@PLT
cvttsd2si %xmm0, %r15d
movq $0, 16(%rsp)
movslq %r15d, %rbx
shlq $2, %rbx
leaq 16(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 16(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq $0, 8(%rsp)
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 8(%rsp), %rdi
xorl %esi, %esi
movq %rbx, %rdx
callq hipMemset
movq $0, 24(%rsp)
movslq N(%rip), %rsi
shlq $2, %rsi
leaq 24(%rsp), %rdi
callq hipMalloc
movl N(%rip), %eax
testl %eax, %eax
jle .LBB6_8
# %bb.1: # %.lr.ph33
movl $B, %ebx
movl $A, %r12d
xorl %r13d, %r13d
jmp .LBB6_2
.p2align 4, 0x90
.LBB6_7: # %._crit_edge
# in Loop: Header=BB6_2 Depth=1
incq %r13
movslq N(%rip), %rax
addq $4, %rbx
addq $60000, %r12 # imm = 0xEA60
cmpq %rax, %r13
jge .LBB6_8
.LBB6_2: # =>This Loop Header: Depth=1
# Child Loop BB6_4 Depth 2
imulq $60000, %r13, %rcx # imm = 0xEA60
leaq A(%rcx), %rdi
movslq %eax, %rsi
movq 24(%rsp), %rdx
movq 16(%rsp), %rcx
movq 8(%rsp), %r8
movl $16, %r9d
pushq %r15
.cfi_adjust_cfa_offset 8
pushq %r14
.cfi_adjust_cfa_offset 8
callq _Z3sumPfmS_S_S_iii
addq $16, %rsp
.cfi_adjust_cfa_offset -16
movl N(%rip), %ecx
testl %ecx, %ecx
jle .LBB6_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB6_2 Depth=1
xorps %xmm2, %xmm2
cvtsi2ss %ecx, %xmm2
movss (%rax), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm3, %xmm0
divss %xmm2, %xmm0
movaps %xmm0, %xmm1
mulss %xmm0, %xmm1
mulss %xmm2, %xmm1
addss 4(%rax), %xmm1
movaps %xmm0, %xmm4
addss %xmm0, %xmm4
mulss %xmm3, %xmm4
subss %xmm4, %xmm1
divss %xmm2, %xmm1
movq %rbx, %rax
xorl %edx, %edx
jmp .LBB6_4
.p2align 4, 0x90
.LBB6_6: # in Loop: Header=BB6_4 Depth=2
movss %xmm2, (%rax)
incq %rdx
addq $60000, %rax # imm = 0xEA60
cmpq %rdx, %rcx
je .LBB6_7
.LBB6_4: # Parent Loop BB6_2 Depth=1
# => This Inner Loop Header: Depth=2
xorps %xmm2, %xmm2
ucomiss %xmm2, %xmm1
jne .LBB6_5
jnp .LBB6_6
.LBB6_5: # in Loop: Header=BB6_4 Depth=2
movss (%r12,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
subss %xmm0, %xmm2
divss %xmm1, %xmm2
jmp .LBB6_6
.LBB6_8: # %._crit_edge34
movq 16(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movq 24(%rsp), %rdi
callq hipFree
addq $32, %rsp
.cfi_def_cfa_offset 48
popq %rbx
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
retq
.Lfunc_end6:
.size _Z10matrixNormv, .Lfunc_end6-_Z10matrixNormv
.cfi_endproc
# -- End function
.globl _Z24__device_stub__block_sumPKfPfS1_m # -- Begin function _Z24__device_stub__block_sumPKfPfS1_m
.p2align 4, 0x90
.type _Z24__device_stub__block_sumPKfPfS1_m,@function
_Z24__device_stub__block_sumPKfPfS1_m: # @_Z24__device_stub__block_sumPKfPfS1_m
.cfi_startproc
# %bb.0:
subq $120, %rsp
.cfi_def_cfa_offset 128
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
movq %rcx, 48(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rax
movq %rax, 104(%rsp)
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9block_sumPKfPfS1_m, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $136, %rsp
.cfi_adjust_cfa_offset -136
retq
.Lfunc_end7:
.size _Z24__device_stub__block_sumPKfPfS1_m, .Lfunc_end7-_Z24__device_stub__block_sumPKfPfS1_m
.cfi_endproc
# -- End function
.globl _Z37__device_stub__single_block_reductionPfS_m # -- Begin function _Z37__device_stub__single_block_reductionPfS_m
.p2align 4, 0x90
.type _Z37__device_stub__single_block_reductionPfS_m,@function
_Z37__device_stub__single_block_reductionPfS_m: # @_Z37__device_stub__single_block_reductionPfS_m
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movq %rdx, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22single_block_reductionPfS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end8:
.size _Z37__device_stub__single_block_reductionPfS_m, .Lfunc_end8-_Z37__device_stub__single_block_reductionPfS_m
.cfi_endproc
# -- End function
.globl _Z3sumPfmS_S_S_iii # -- Begin function _Z3sumPfmS_S_S_iii
.p2align 4, 0x90
.type _Z3sumPfmS_S_S_iii,@function
_Z3sumPfmS_S_S_iii: # @_Z3sumPfmS_S_S_iii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $120, %rsp
.cfi_def_cfa_offset 176
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movq %r8, (%rsp) # 8-byte Spill
movq %rcx, %r14
movq %rdx, %rbp
movq %rsi, %r13
movq %rdi, %rsi
movl 176(%rsp), %r15d
movabsq $4294967296, %r12 # imm = 0x100000000
movslq N(%rip), %rdx
shlq $2, %rdx
movq %rbp, %rdi
movl $1, %ecx
callq hipMemcpy
orq %r12, %r15
movl %ebx, %edx
orq %r12, %rdx
movq %r15, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_2
# %bb.1:
movq %rbp, 72(%rsp)
movq %r14, 64(%rsp)
movq (%rsp), %rax # 8-byte Reload
movq %rax, 56(%rsp)
movq %r13, 16(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 8(%rsp), %rdx
leaq 112(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z9block_sumPKfPfS1_m, %edi
pushq 112(%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_2:
incq %r12
movq %r12, %rdi
movl $1, %esi
movq %r15, %rdx
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB9_4
# %bb.3:
movslq 184(%rsp), %rax
movq %r14, 72(%rsp)
movq (%rsp), %rcx # 8-byte Reload
movq %rcx, 64(%rsp)
movq %rax, 56(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 56(%rsp), %rax
movq %rax, 96(%rsp)
leaq 40(%rsp), %rdi
leaq 24(%rsp), %rsi
leaq 16(%rsp), %rdx
leaq 8(%rsp), %rcx
callq __hipPopCallConfiguration
movq 40(%rsp), %rsi
movl 48(%rsp), %edx
movq 24(%rsp), %rcx
movl 32(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z22single_block_reductionPfS_m, %edi
pushq 8(%rsp)
.cfi_adjust_cfa_offset 8
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB9_4:
movl $8, %edi
callq malloc
movq %rax, %rbx
movl $4, %edx
movq %rax, %rdi
movq %r14, %rsi
movl $2, %ecx
callq hipMemcpy
leaq 4(%rbx), %rdi
movl $4, %edx
movq (%rsp), %rsi # 8-byte Reload
movl $2, %ecx
callq hipMemcpy
movq %rbx, %rax
addq $120, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end9:
.size _Z3sumPfmS_S_S_iii, .Lfunc_end9-_Z3sumPfmS_S_S_iii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB10_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB10_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z9block_sumPKfPfS1_m, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z22single_block_reductionPfS_m, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end10:
.size __hip_module_ctor, .Lfunc_end10-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB11_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB11_2:
retq
.Lfunc_end11:
.size __hip_module_dtor, .Lfunc_end11-__hip_module_dtor
.cfi_endproc
# -- End function
.type N,@object # @N
.bss
.globl N
.p2align 2, 0x0
N:
.long 0 # 0x0
.size N, 4
.type A,@object # @A
.globl A
.p2align 4, 0x0
A:
.zero 900000000
.size A, 900000000
.type B,@object # @B
.globl B
.p2align 4, 0x0
B:
.zero 900000000
.size B, 900000000
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "Random seed = %i\n"
.size .L.str, 18
.type .L.str.1,@object # @.str.1
.L.str.1:
.asciz "N = %i is out of range.\n"
.size .L.str.1, 25
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "Usage: %s <matrix_dimension> [random seed]\n"
.size .L.str.2, 44
.type .L.str.3,@object # @.str.3
.L.str.3:
.asciz "\nMatrix dimension N = %i.\n"
.size .L.str.3, 27
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "\nA =\n\t"
.size .L.str.5, 7
.type .L.str.6,@object # @.str.6
.L.str.6:
.asciz "%5.2f%s"
.size .L.str.6, 8
.type .L.str.7,@object # @.str.7
.L.str.7:
.asciz ", "
.size .L.str.7, 3
.type .L.str.8,@object # @.str.8
.L.str.8:
.asciz "
.size .L.str.8, 4
.type .L.str.9,@object # @.str.9
.L.str.9:
.asciz "\nB =\n\t"
.size .L.str.9, 7
.type .L.str.10,@object # @.str.10
.L.str.10:
.asciz "%1.10f%s"
.size .L.str.10, 9
.type .L.str.13,@object # @.str.13
.L.str.13:
.asciz "\nElapsed time = %g ms.\n"
.size .L.str.13, 24
.type .L.str.14,@object # @.str.14
.L.str.14:
.asciz "(CPU times are accurate to the nearest %g ms)\n"
.size .L.str.14, 47
.type .L.str.15,@object # @.str.15
.L.str.15:
.asciz "My total CPU time for parent = %g ms.\n"
.size .L.str.15, 39
.type .L.str.16,@object # @.str.16
.L.str.16:
.asciz "My system CPU time for parent = %g ms.\n"
.size .L.str.16, 40
.type .L.str.17,@object # @.str.17
.L.str.17:
.asciz "My total CPU time for child processes = %g ms.\n"
.size .L.str.17, 48
.type _Z9block_sumPKfPfS1_m,@object # @_Z9block_sumPKfPfS1_m
.section .rodata,"a",@progbits
.globl _Z9block_sumPKfPfS1_m
.p2align 3, 0x0
_Z9block_sumPKfPfS1_m:
.quad _Z24__device_stub__block_sumPKfPfS1_m
.size _Z9block_sumPKfPfS1_m, 8
.type _Z22single_block_reductionPfS_m,@object # @_Z22single_block_reductionPfS_m
.globl _Z22single_block_reductionPfS_m
.p2align 3, 0x0
_Z22single_block_reductionPfS_m:
.quad _Z37__device_stub__single_block_reductionPfS_m
.size _Z22single_block_reductionPfS_m, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z9block_sumPKfPfS1_m"
.size .L__unnamed_1, 22
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z22single_block_reductionPfS_m"
.size .L__unnamed_2, 32
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "\nInitializing..."
.size .Lstr, 17
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "\nStarting clock."
.size .Lstr.1, 17
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "Stopped clock."
.size .Lstr.2, 15
.type .Lstr.3,@object # @str.3
.Lstr.3:
.asciz "--------------------------------------------"
.size .Lstr.3, 45
.type .Lstr.4,@object # @str.4
.Lstr.4:
.asciz "Computing Parallely."
.size .Lstr.4, 21
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z24__device_stub__block_sumPKfPfS1_m
.addrsig_sym _Z37__device_stub__single_block_reductionPfS_m
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym A
.addrsig_sym B
.addrsig_sym _Z9block_sumPKfPfS1_m
.addrsig_sym _Z22single_block_reductionPfS_m
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z22single_block_reductionPfS_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e220000002100 */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ ISETP.GE.U32.AND P0, PT, R7.reuse, c[0x0][0x170], PT ; /* 0x00005c0007007a0c */
/* 0x041fe20003f06070 */
/*0040*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x000fe200078e00ff */
/*0050*/ SHF.R.S32.HI R2, RZ, 0x1f, R7 ; /* 0x0000001fff027819 */
/* 0x000fc80000011407 */
/*0060*/ ISETP.GE.U32.AND.EX P0, PT, R2, c[0x0][0x174], PT, P0 ; /* 0x00005d0002007a0c */
/* 0x000fda0003f06100 */
/*0070*/ @!P0 SHF.L.U64.HI R5, R7, 0x2, R2 ; /* 0x0000000207058819 */
/* 0x000fe40000010202 */
/*0080*/ @!P0 IADD3 R2, P1, R0.reuse, c[0x0][0x160], RZ ; /* 0x0000580000028a10 */
/* 0x040fe40007f3e0ff */
/*0090*/ @!P0 IADD3 R4, P2, R0, c[0x0][0x168], RZ ; /* 0x00005a0000048a10 */
/* 0x000fe40007f5e0ff */
/*00a0*/ @!P0 IADD3.X R3, R5.reuse, c[0x0][0x164], RZ, P1, !PT ; /* 0x0000590005038a10 */
/* 0x040fe40000ffe4ff */
/*00b0*/ @!P0 IADD3.X R5, R5, c[0x0][0x16c], RZ, P2, !PT ; /* 0x00005b0005058a10 */
/* 0x000fc600017fe4ff */
/*00c0*/ @!P0 LDG.E R2, [R2.64] ; /* 0x0000000402028981 */
/* 0x0000a8000c1e1900 */
/*00d0*/ @!P0 LDG.E R4, [R4.64] ; /* 0x0000000404048981 */
/* 0x000ee2000c1e1900 */
/*00e0*/ IMAD.MOV.U32 R6, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff067624 */
/* 0x000fe400078e00ff */
/*00f0*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x000fca00078e00ff */
/*0100*/ SHF.R.U64 R3, R6, R9, c[0x0][0x174] ; /* 0x00005d0006037619 */
/* 0x001fe20000001209 */
/*0110*/ @!P0 STS [R7.X4], R2 ; /* 0x0000000207008388 */
/* 0x0041e80000004800 */
/*0120*/ @!P0 STS [R7.X4+0x400], R4 ; /* 0x0004000407008388 */
/* 0x0081e80000004800 */
/*0130*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe20000010000 */
/*0140*/ ISETP.GE.AND P0, PT, R3, 0x1, PT ; /* 0x000000010300780c */
/* 0x000fda0003f06270 */
/*0150*/ @!P0 BRA 0x270 ; /* 0x0000011000008947 */
/* 0x001fea0003800000 */
/*0160*/ ISETP.GE.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fe20003f06270 */
/*0170*/ BSSY B0, 0x230 ; /* 0x000000b000007945 */
/* 0x000fd80003800000 */
/*0180*/ @P0 BRA 0x220 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*0190*/ IMAD R2, R3, 0x4, R0 ; /* 0x0000000403027824 */
/* 0x000fe200078e0200 */
/*01a0*/ LDS R4, [R7.X4] ; /* 0x0000000007047984 */
/* 0x000fe80000004800 */
/*01b0*/ LDS R5, [R2] ; /* 0x0000000002057984 */
/* 0x000e240000000800 */
/*01c0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fe40000000000 */
/*01d0*/ LDS R5, [R7.X4+0x400] ; /* 0x0004000007057984 */
/* 0x000fe80000004800 */
/*01e0*/ STS [R7.X4], R4 ; /* 0x0000000407007388 */
/* 0x000fe80000004800 */
/*01f0*/ LDS R6, [R2+0x400] ; /* 0x0004000002067984 */
/* 0x000e240000000800 */
/*0200*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0210*/ STS [R7.X4+0x400], R5 ; /* 0x0004000507007388 */
/* 0x0001e40000004800 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0250*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0260*/ @P0 BRA 0x160 ; /* 0xfffffef000000947 */
/* 0x000fea000383ffff */
/*0270*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x000fda0003f05270 */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x001e220000000800 */
/*02a0*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe400078e00ff */
/*02b0*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe200078e00ff */
/*02c0*/ LDS R9, [0x400] ; /* 0x00040000ff097984 */
/* 0x000e620000000800 */
/*02d0*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff047624 */
/* 0x000fe400078e00ff */
/*02e0*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff057624 */
/* 0x000fe200078e00ff */
/*02f0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101904 */
/*0300*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101904 */
/*0310*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0320*/ BRA 0x320; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
..........
Function : _Z9block_sumPKfPfS1_m
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ S2R R8, SR_CTAID.X ; /* 0x0000000000087919 */
/* 0x000e220000002500 */
/*0020*/ ULDC.64 UR6, c[0x0][0x118] ; /* 0x0000460000067ab9 */
/* 0x000fc60000000a00 */
/*0030*/ S2R R7, SR_TID.X ; /* 0x0000000000077919 */
/* 0x000e240000002100 */
/*0040*/ IMAD R0, R8, c[0x0][0x0], R7 ; /* 0x0000000008007a24 */
/* 0x001fca00078e0207 */
/*0050*/ ISETP.GE.U32.AND P0, PT, R0, c[0x0][0x178], PT ; /* 0x00005e0000007a0c */
/* 0x000fe40003f06070 */
/*0060*/ SHF.R.S32.HI R3, RZ, 0x1f, R0 ; /* 0x0000001fff037819 */
/* 0x000fc80000011400 */
/*0070*/ ISETP.GE.U32.AND.EX P0, PT, R3, c[0x0][0x17c], PT, P0 ; /* 0x00005f0003007a0c */
/* 0x000fda0003f06100 */
/*0080*/ @!P0 LEA R2, P1, R0, c[0x0][0x160], 0x2 ; /* 0x0000580000028a11 */
/* 0x000fc800078210ff */
/*0090*/ @!P0 LEA.HI.X R3, R0, c[0x0][0x164], R3, 0x2, P1 ; /* 0x0000590000038a11 */
/* 0x000fe200008f1403 */
/*00a0*/ IMAD.MOV.U32 R0, RZ, RZ, RZ ; /* 0x000000ffff007224 */
/* 0x000fcc00078e00ff */
/*00b0*/ @!P0 LDG.E R0, [R2.64] ; /* 0x0000000602008981 */
/* 0x000ea2000c1e1900 */
/*00c0*/ ULDC UR4, c[0x0][0x0] ; /* 0x0000000000047ab9 */
/* 0x000fe40000000800 */
/*00d0*/ USHF.R.U32.HI UR4, URZ, 0x1, UR4 ; /* 0x000000013f047899 */
/* 0x000fcc0008011604 */
/*00e0*/ ISETP.NE.AND P0, PT, RZ, UR4, PT ; /* 0x00000004ff007c0c */
/* 0x000fe2000bf05270 */
/*00f0*/ FMUL R4, R0, R0 ; /* 0x0000000000047220 */
/* 0x004fe20000400000 */
/*0100*/ STS [R7.X4], R0 ; /* 0x0000000007007388 */
/* 0x0001e80000004800 */
/*0110*/ STS [R7.X4+0x1000], R4 ; /* 0x0010000407007388 */
/* 0x0001e80000004800 */
/*0120*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fec0000010000 */
/*0130*/ @!P0 BRA 0x270 ; /* 0x0000013000008947 */
/* 0x000fea0003800000 */
/*0140*/ IMAD.SHL.U32 R0, R7, 0x4, RZ ; /* 0x0000000407007824 */
/* 0x001fe200078e00ff */
/*0150*/ MOV R3, UR4 ; /* 0x0000000400037c02 */
/* 0x000fc80008000f00 */
/*0160*/ ISETP.GE.AND P0, PT, R7, R3, PT ; /* 0x000000030700720c */
/* 0x000fe20003f06270 */
/*0170*/ BSSY B0, 0x230 ; /* 0x000000b000007945 */
/* 0x000fd80003800000 */
/*0180*/ @P0 BRA 0x220 ; /* 0x0000009000000947 */
/* 0x001fea0003800000 */
/*0190*/ IMAD R2, R3, 0x4, R0 ; /* 0x0000000403027824 */
/* 0x000fe200078e0200 */
/*01a0*/ LDS R4, [R7.X4] ; /* 0x0000000007047984 */
/* 0x000fe80000004800 */
/*01b0*/ LDS R5, [R2] ; /* 0x0000000002057984 */
/* 0x000e240000000800 */
/*01c0*/ FADD R4, R4, R5 ; /* 0x0000000504047221 */
/* 0x001fe40000000000 */
/*01d0*/ LDS R5, [R7.X4+0x1000] ; /* 0x0010000007057984 */
/* 0x000fe80000004800 */
/*01e0*/ STS [R7.X4], R4 ; /* 0x0000000407007388 */
/* 0x000fe80000004800 */
/*01f0*/ LDS R6, [R2+0x1000] ; /* 0x0010000002067984 */
/* 0x000e240000000800 */
/*0200*/ FADD R5, R5, R6 ; /* 0x0000000605057221 */
/* 0x001fca0000000000 */
/*0210*/ STS [R7.X4+0x1000], R5 ; /* 0x0010000507007388 */
/* 0x0001e40000004800 */
/*0220*/ BSYNC B0 ; /* 0x0000000000007941 */
/* 0x000fea0003800000 */
/*0230*/ SHF.R.U32.HI R3, RZ, 0x1, R3 ; /* 0x00000001ff037819 */
/* 0x000fe20000011603 */
/*0240*/ BAR.SYNC.DEFER_BLOCKING 0x0 ; /* 0x0000000000007b1d */
/* 0x000fe60000010000 */
/*0250*/ ISETP.NE.AND P0, PT, R3, RZ, PT ; /* 0x000000ff0300720c */
/* 0x000fda0003f05270 */
/*0260*/ @P0 BRA 0x160 ; /* 0xfffffef000000947 */
/* 0x000fea000383ffff */
/*0270*/ ISETP.NE.AND P0, PT, R7, RZ, PT ; /* 0x000000ff0700720c */
/* 0x001fda0003f05270 */
/*0280*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*0290*/ LDS R7, [RZ] ; /* 0x00000000ff077984 */
/* 0x000e220000000800 */
/*02a0*/ HFMA2.MMA R5, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff057435 */
/* 0x000fc600000001ff */
/*02b0*/ LDS R9, [0x1000] ; /* 0x00100000ff097984 */
/* 0x000e6e0000000800 */
/*02c0*/ IMAD.WIDE.U32 R2, R8, R5, c[0x0][0x168] ; /* 0x00005a0008027625 */
/* 0x000fc800078e0005 */
/*02d0*/ IMAD.WIDE.U32 R4, R8, R5, c[0x0][0x170] ; /* 0x00005c0008047625 */
/* 0x000fe200078e0005 */
/*02e0*/ STG.E [R2.64], R7 ; /* 0x0000000702007986 */
/* 0x001fe8000c101906 */
/*02f0*/ STG.E [R4.64], R9 ; /* 0x0000000904007986 */
/* 0x002fe2000c101906 */
/*0300*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0310*/ BRA 0x310; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0320*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0330*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0340*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0350*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0360*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0370*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0380*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0390*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03a0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03b0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*03f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z9block_sumPKfPfS1_m
.globl _Z9block_sumPKfPfS1_m
.p2align 8
.type _Z9block_sumPKfPfS1_m,@function
_Z9block_sumPKfPfS1_m:
s_clause 0x1
s_load_b32 s3, s[0:1], 0x2c
s_load_b64 s[4:5], s[0:1], 0x18
s_mov_b32 s2, s15
v_mov_b32_e32 v3, 0
s_waitcnt lgkmcnt(0)
s_and_b32 s3, s3, 0xffff
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
v_ashrrev_i32_e32 v2, 31, v1
s_delay_alu instid0(VALU_DEP_1)
v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[1:2]
s_and_saveexec_b32 s4, vcc_lo
s_cbranch_execz .LBB0_2
s_load_b64 s[6:7], s[0:1], 0x0
v_lshlrev_b64 v[1:2], 2, v[1:2]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v1, vcc_lo, s6, v1
v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
global_load_b32 v3, v[1:2], off
.LBB0_2:
s_or_b32 exec_lo, exec_lo, s4
s_waitcnt vmcnt(0)
v_dual_mul_f32 v2, v3, v3 :: v_dual_lshlrev_b32 v1, 2, v0
s_cmp_lt_u32 s3, 2
ds_store_2addr_stride64_b32 v1, v3, v2 offset1:16
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
v_or_b32_e32 v2, 0x1000, v1
s_set_inst_prefetch_distance 0x1
s_branch .LBB0_5
.p2align 6
.LBB0_4:
s_or_b32 exec_lo, exec_lo, s5
s_cmp_lt_u32 s3, 4
s_mov_b32 s3, s4
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
s_cbranch_scc1 .LBB0_7
.LBB0_5:
s_lshr_b32 s4, s3, 1
s_mov_b32 s5, exec_lo
v_cmpx_gt_u32_e64 s4, v0
s_cbranch_execz .LBB0_4
v_add_lshl_u32 v3, s4, v0, 2
ds_load_2addr_stride64_b32 v[3:4], v3 offset1:16
ds_load_b32 v5, v1
ds_load_b32 v6, v2
s_waitcnt lgkmcnt(0)
v_dual_add_f32 v3, v3, v5 :: v_dual_add_f32 v4, v4, v6
ds_store_b32 v1, v3
ds_store_b32 v2, v4
s_branch .LBB0_4
.LBB0_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s3, 0
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB0_9
v_mov_b32_e32 v2, 0
s_load_b128 s[4:7], s[0:1], 0x8
s_lshl_b64 s[0:1], s[2:3], 2
ds_load_2addr_stride64_b32 v[0:1], v2 offset1:16
s_waitcnt lgkmcnt(0)
s_add_u32 s2, s4, s0
s_addc_u32 s3, s5, s1
s_add_u32 s0, s6, s0
s_addc_u32 s1, s7, s1
s_clause 0x1
global_store_b32 v2, v0, s[2:3]
global_store_b32 v2, v1, s[0:1]
.LBB0_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z9block_sumPKfPfS1_m
.amdhsa_group_segment_fixed_size 8192
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 288
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 7
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z9block_sumPKfPfS1_m, .Lfunc_end0-_Z9block_sumPKfPfS1_m
.section .AMDGPU.csdata,"",@progbits
.text
.protected _Z22single_block_reductionPfS_m
.globl _Z22single_block_reductionPfS_m
.p2align 8
.type _Z22single_block_reductionPfS_m,@function
_Z22single_block_reductionPfS_m:
s_clause 0x1
s_load_b64 s[4:5], s[0:1], 0x10
s_load_b128 s[0:3], s[0:1], 0x0
v_mov_b32_e32 v1, 0
s_mov_b32 s6, exec_lo
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_gt_u64_e64 s[4:5], v[0:1]
s_cbranch_execz .LBB1_2
v_lshlrev_b32_e32 v1, 2, v0
s_clause 0x1
global_load_b32 v2, v1, s[0:1]
global_load_b32 v3, v1, s[2:3]
s_waitcnt vmcnt(0)
ds_store_2addr_stride64_b32 v1, v2, v3 offset1:4
.LBB1_2:
s_or_b32 exec_lo, exec_lo, s6
v_alignbit_b32 v1, s5, s4, 1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_cmp_gt_i32_e32 vcc_lo, 1, v1
s_cbranch_vccnz .LBB1_7
v_lshlrev_b32_e32 v2, 2, v0
s_delay_alu instid0(VALU_DEP_1)
v_add_nc_u32_e32 v3, 0x400, v2
s_set_inst_prefetch_distance 0x1
s_branch .LBB1_5
.p2align 6
.LBB1_4:
s_or_b32 exec_lo, exec_lo, s4
v_lshrrev_b32_e32 v4, 1, v1
v_cmp_gt_u32_e32 vcc_lo, 2, v1
s_waitcnt lgkmcnt(0)
s_barrier
buffer_gl0_inv
v_mov_b32_e32 v1, v4
s_cbranch_vccnz .LBB1_7
.LBB1_5:
s_mov_b32 s4, exec_lo
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_lt_i32_e64 v0, v1
s_cbranch_execz .LBB1_4
v_add_lshl_u32 v4, v1, v0, 2
ds_load_2addr_stride64_b32 v[4:5], v4 offset1:4
ds_load_b32 v6, v2
ds_load_b32 v7, v3
s_waitcnt lgkmcnt(0)
v_dual_add_f32 v4, v4, v6 :: v_dual_add_f32 v5, v5, v7
ds_store_b32 v2, v4
ds_store_b32 v3, v5
s_branch .LBB1_4
.LBB1_7:
s_set_inst_prefetch_distance 0x2
s_mov_b32 s4, exec_lo
v_cmpx_eq_u32_e32 0, v0
s_cbranch_execz .LBB1_9
v_mov_b32_e32 v2, 0
ds_load_2addr_stride64_b32 v[0:1], v2 offset1:4
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_store_b32 v2, v0, s[0:1]
global_store_b32 v2, v1, s[2:3]
.LBB1_9:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z22single_block_reductionPfS_m
.amdhsa_group_segment_fixed_size 2048
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 24
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 8
.amdhsa_next_free_sgpr 7
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end1:
.size _Z22single_block_reductionPfS_m, .Lfunc_end1-_Z22single_block_reductionPfS_m
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 8
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: hidden_block_count_x
- .offset: 36
.size: 4
.value_kind: hidden_block_count_y
- .offset: 40
.size: 4
.value_kind: hidden_block_count_z
- .offset: 44
.size: 2
.value_kind: hidden_group_size_x
- .offset: 46
.size: 2
.value_kind: hidden_group_size_y
- .offset: 48
.size: 2
.value_kind: hidden_group_size_z
- .offset: 50
.size: 2
.value_kind: hidden_remainder_x
- .offset: 52
.size: 2
.value_kind: hidden_remainder_y
- .offset: 54
.size: 2
.value_kind: hidden_remainder_z
- .offset: 72
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 96
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 8192
.kernarg_segment_align: 8
.kernarg_segment_size: 288
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z9block_sumPKfPfS1_m
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z9block_sumPKfPfS1_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 7
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 8
.value_kind: by_value
.group_segment_fixed_size: 2048
.kernarg_segment_align: 8
.kernarg_segment_size: 24
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z22single_block_reductionPfS_m
.private_segment_fixed_size: 0
.sgpr_count: 9
.sgpr_spill_count: 0
.symbol: _Z22single_block_reductionPfS_m.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 8
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include "includes.h"
__global__ void findMaxIndMultipleDetector(float *input, int* maxInd, int size)
{
int maxIndex = 0;
int count = 1;
for (int i = 1; i < size; i++){
if (input[maxIndex] < input[i]){
maxIndex = i;
count = 1;
}
else if (input[maxIndex] == input[i]){
count++;
}
}
if(count>1)
maxInd[0] = -1;
else
maxInd[0] = maxIndex;
} | code for sm_80
Function : _Z26findMaxIndMultipleDetectorPfPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f06270 */
/*0060*/ @!P0 BRA 0x650 ; /* 0x000005e000008947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R0, R2, -0x2, RZ ; /* 0xfffffffe02007810 */
/* 0x000fe20007ffe0ff */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R6, -R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fc600078e00ff */
/*00e0*/ LOP3.LUT P0, R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fce000780c0ff */
/*00f0*/ @!P1 BRA 0x4e0 ; /* 0x000003e000009947 */
/* 0x000fec0003800000 */
/*0100*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0130*/ LOP3.LUT R7, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300077812 */
/* 0x000fe200078ec0ff */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R7, R7, -c[0x0][0x170], RZ ; /* 0x80005c0007077a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0190*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea6000c1e1900 */
/*01a0*/ IMAD.WIDE R8, R5, R8, c[0x0][0x160] ; /* 0x0000580005087625 */
/* 0x000fe200078e0208 */
/*01b0*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000ee8000c1e1900 */
/*01c0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000f28000c1e1900 */
/*01e0*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000f62000c1e1900 */
/*01f0*/ FSETP.GEU.AND P3, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x004fda0003f6e000 */
/*0200*/ @P3 FSETP.NEU.AND P1, PT, R11, R10, PT ; /* 0x0000000a0b00320b */
/* 0x000fe20003f2d000 */
/*0210*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a3224 */
/* 0x000fe200078e000b */
/*0220*/ IADD3 R11, P4, R2, 0x4, RZ ; /* 0x00000004020b7810 */
/* 0x000fc80007f9e0ff */
/*0230*/ FSETP.GEU.AND P2, PT, R10, R13, PT ; /* 0x0000000d0a00720b */
/* 0x008fe20003f4e000 */
/*0240*/ IMAD.X R14, RZ, RZ, R3, P4 ; /* 0x000000ffff0e7224 */
/* 0x000fe400020e0603 */
/*0250*/ @P3 IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b3224 */
/* 0x000fe400078e0008 */
/*0260*/ @P3 IMAD.MOV.U32 R14, RZ, RZ, R9 ; /* 0x000000ffff0e3224 */
/* 0x000fe400078e0009 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000b */
/*0280*/ IMAD.MOV.U32 R9, RZ, RZ, R14 ; /* 0x000000ffff097224 */
/* 0x000fc800078e000e */
/*0290*/ @P2 FSETP.NEU.AND P4, PT, R10, R13, PT ; /* 0x0000000d0a00220b */
/* 0x000fe40003f8d000 */
/*02a0*/ @P2 LDG.E R13, [R8.64] ; /* 0x00000004080d2981 */
/* 0x000122000c1e1900 */
/*02b0*/ PLOP3.LUT P5, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003fae170 */
/*02c0*/ @P3 PLOP3.LUT P5, PT, P1, PT, PT, 0x80, 0x0 ; /* 0x000000000000381c */
/* 0x000fe40000faf070 */
/*02d0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f2e170 */
/*02e0*/ @P2 PLOP3.LUT P1, PT, P4, PT, PT, 0x80, 0x0 ; /* 0x000000000000281c */
/* 0x000fe2000272f070 */
/*02f0*/ HFMA2.MMA R10, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0a7435 */
/* 0x000fe200000001ff */
/*0300*/ @P3 IADD3 R11, R4, 0x1, RZ ; /* 0x00000001040b3810 */
/* 0x000fce0007ffe0ff */
/*0310*/ @P5 IMAD.MOV R11, RZ, RZ, R4 ; /* 0x000000ffff0b5224 */
/* 0x000fe400078e0204 */
/*0320*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0330*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a3224 */
/* 0x000fe400078e000b */
/*0340*/ @P3 IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff043224 */
/* 0x000fe200078e0005 */
/*0350*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x000fe40007ffe0ff */
/*0360*/ @P2 IADD3 R11, R10, 0x1, RZ ; /* 0x000000010a0b2810 */
/* 0x000fe20007ffe0ff */
/*0370*/ @P1 IMAD.MOV R11, RZ, RZ, R10 ; /* 0x000000ffff0b1224 */
/* 0x000fc400078e020a */
/*0380*/ @P2 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff052224 */
/* 0x000fe400078e0004 */
/*0390*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x001fe400078e00ff */
/*03a0*/ @P2 IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff092224 */
/* 0x000fca00078e000b */
/*03b0*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ FSETP.GEU.AND P4, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x010fc80003f8e000 */
/*03d0*/ FSEL R8, R12, R13, !P4 ; /* 0x0000000d0c087208 */
/* 0x000fc80006000000 */
/*03e0*/ FSETP.GEU.AND P3, PT, R8, R15, PT ; /* 0x0000000f0800720b */
/* 0x020fe40003f6e000 */
/*03f0*/ FSETP.NEU.AND P1, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x000fc60003f2d000 */
/*0400*/ @!P4 IADD3 R5, R0, 0x2, RZ ; /* 0x000000020005c810 */
/* 0x000fe40007ffe0ff */
/*0410*/ FSETP.NEU.AND P2, PT, R8, R15, PT ; /* 0x0000000f0800720b */
/* 0x000fcc0003f4d000 */
/*0420*/ @!P3 IADD3 R5, R0.reuse, 0x3, RZ ; /* 0x000000030005b810 */
/* 0x040fe40007ffe0ff */
/*0430*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*0440*/ @P1 IMAD.MOV R4, RZ, RZ, R9 ; /* 0x000000ffff041224 */
/* 0x000fc800078e0209 */
/*0450*/ IMAD.IADD R8, R7, 0x1, R0 ; /* 0x0000000107087824 */
/* 0x000fca00078e0200 */
/*0460*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0470*/ SEL R9, RZ, 0x1, P2 ; /* 0x00000001ff097807 */
/* 0x000fe40001000000 */
/*0480*/ SEL R4, R4, 0x1, P4 ; /* 0x0000000104047807 */
/* 0x000fe40002000000 */
/*0490*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc60007f5e0ff */
/*04a0*/ IMAD.IADD R4, R4, 0x1, R9 ; /* 0x0000000104047824 */
/* 0x000fe400078e0209 */
/*04b0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fc600010e0603 */
/*04c0*/ SEL R4, R4, 0x1, P3 ; /* 0x0000000104047807 */
/* 0x000fe20001800000 */
/*04d0*/ @P1 BRA 0x180 ; /* 0xfffffca000001947 */
/* 0x000fea000383ffff */
/*04e0*/ @!P0 BRA 0x650 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*04f0*/ MOV R12, 0x4 ; /* 0x00000004000c7802 */
/* 0x000fe20000000f00 */
/*0500*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0006 */
/*0510*/ IMAD.WIDE R2, R0, R12, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020c */
/*0520*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*0530*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*0540*/ IMAD.WIDE R2, R12, R5, c[0x0][0x160] ; /* 0x000058000c027625 */
/* 0x000fc800078e0205 */
/*0550*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*0560*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*0570*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ IADD3 R9, R4, 0x1, RZ ; /* 0x0000000104097810 */
/* 0x000fc40007ffe0ff */
/*05b0*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*05c0*/ IADD3 R10, P3, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fca0007f7e0ff */
/*05d0*/ IMAD.X R11, RZ, RZ, R11, P3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200018e060b */
/*05e0*/ FSETP.NEU.AND P1, PT, R3.reuse, R6.reuse, PT ; /* 0x000000060300720b */
/* 0x0c4fe40003f2d000 */
/*05f0*/ FSETP.GEU.AND P0, PT, R3, R6, PT ; /* 0x000000060300720b */
/* 0x000fc80003f0e000 */
/*0600*/ SEL R5, R0.reuse, R5, !P0 ; /* 0x0000000500057207 */
/* 0x040fe40004000000 */
/*0610*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fca0007ffe0ff */
/*0620*/ @P1 IMAD.MOV R9, RZ, RZ, R4 ; /* 0x000000ffff091224 */
/* 0x000fca00078e0204 */
/*0630*/ SEL R4, R9, 0x1, P0 ; /* 0x0000000109047807 */
/* 0x000fe20000000000 */
/*0640*/ @P2 BRA 0x540 ; /* 0xfffffef000002947 */
/* 0x000fea000383ffff */
/*0650*/ ISETP.GT.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f04270 */
/*0660*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0670*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0680*/ SEL R5, R5, 0xffffffff, !P0 ; /* 0xffffffff05057807 */
/* 0x000fca0004000000 */
/*0690*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include "includes.h"
__global__ void findMaxIndMultipleDetector(float *input, int* maxInd, int size)
{
int maxIndex = 0;
int count = 1;
for (int i = 1; i < size; i++){
if (input[maxIndex] < input[i]){
maxIndex = i;
count = 1;
}
else if (input[maxIndex] == input[i]){
count++;
}
}
if(count>1)
maxInd[0] = -1;
else
maxInd[0] = maxIndex;
} | .file "tmpxft_0013f3aa_00000000-6_findMaxIndMultipleDetector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii
.type _Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii, @function
_Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26findMaxIndMultipleDetectorPfPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii, .-_Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii
.globl _Z26findMaxIndMultipleDetectorPfPii
.type _Z26findMaxIndMultipleDetectorPfPii, @function
_Z26findMaxIndMultipleDetectorPfPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26findMaxIndMultipleDetectorPfPii, .-_Z26findMaxIndMultipleDetectorPfPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26findMaxIndMultipleDetectorPfPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26findMaxIndMultipleDetectorPfPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include "includes.h"
__global__ void findMaxIndMultipleDetector(float *input, int* maxInd, int size)
{
int maxIndex = 0;
int count = 1;
for (int i = 1; i < size; i++){
if (input[maxIndex] < input[i]){
maxIndex = i;
count = 1;
}
else if (input[maxIndex] == input[i]){
count++;
}
}
if(count>1)
maxInd[0] = -1;
else
maxInd[0] = maxIndex;
} | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void findMaxIndMultipleDetector(float *input, int* maxInd, int size)
{
int maxIndex = 0;
int count = 1;
for (int i = 1; i < size; i++){
if (input[maxIndex] < input[i]){
maxIndex = i;
count = 1;
}
else if (input[maxIndex] == input[i]){
count++;
}
}
if(count>1)
maxInd[0] = -1;
else
maxInd[0] = maxIndex;
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void findMaxIndMultipleDetector(float *input, int* maxInd, int size)
{
int maxIndex = 0;
int count = 1;
for (int i = 1; i < size; i++){
if (input[maxIndex] < input[i]){
maxIndex = i;
count = 1;
}
else if (input[maxIndex] == input[i]){
count++;
}
}
if(count>1)
maxInd[0] = -1;
else
maxInd[0] = maxIndex;
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26findMaxIndMultipleDetectorPfPii
.globl _Z26findMaxIndMultipleDetectorPfPii
.p2align 8
.type _Z26findMaxIndMultipleDetectorPfPii,@function
_Z26findMaxIndMultipleDetectorPfPii:
s_load_b32 s8, s[0:1], 0x10
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 2
s_cbranch_scc1 .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s6, 0
s_mov_b32 s9, 1
s_mov_b32 s10, 1
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, 4
s_addc_u32 s5, s3, 0
.p2align 6
.LBB0_2:
s_ashr_i32 s7, s6, 31
s_mov_b32 s11, 1
s_lshl_b64 s[12:13], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s2, s12
s_addc_u32 s15, s3, s13
s_load_b32 s12, s[4:5], 0x0
s_load_b32 s13, s[14:15], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e64 s7, s13, s12
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s7
s_mov_b32 s7, s9
s_cbranch_vccnz .LBB0_6
v_cmp_neq_f32_e64 s7, s13, s12
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_5
s_add_i32 s10, s10, 1
.LBB0_5:
s_mov_b32 s7, s6
s_mov_b32 s11, s10
.LBB0_6:
s_add_i32 s9, s9, 1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s8, s9
s_cbranch_scc1 .LBB0_8
s_mov_b32 s10, s11
s_mov_b32 s6, s7
s_branch .LBB0_2
.LBB0_8:
s_cmp_lt_i32 s11, 2
s_cselect_b32 s2, s7, -1
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26findMaxIndMultipleDetectorPfPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26findMaxIndMultipleDetectorPfPii, .Lfunc_end0-_Z26findMaxIndMultipleDetectorPfPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26findMaxIndMultipleDetectorPfPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26findMaxIndMultipleDetectorPfPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <hip/hip_runtime.h>
#include "includes.h"
__global__ void findMaxIndMultipleDetector(float *input, int* maxInd, int size)
{
int maxIndex = 0;
int count = 1;
for (int i = 1; i < size; i++){
if (input[maxIndex] < input[i]){
maxIndex = i;
count = 1;
}
else if (input[maxIndex] == input[i]){
count++;
}
}
if(count>1)
maxInd[0] = -1;
else
maxInd[0] = maxIndex;
} | .text
.file "findMaxIndMultipleDetector.hip"
.globl _Z41__device_stub__findMaxIndMultipleDetectorPfPii # -- Begin function _Z41__device_stub__findMaxIndMultipleDetectorPfPii
.p2align 4, 0x90
.type _Z41__device_stub__findMaxIndMultipleDetectorPfPii,@function
_Z41__device_stub__findMaxIndMultipleDetectorPfPii: # @_Z41__device_stub__findMaxIndMultipleDetectorPfPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26findMaxIndMultipleDetectorPfPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z41__device_stub__findMaxIndMultipleDetectorPfPii, .Lfunc_end0-_Z41__device_stub__findMaxIndMultipleDetectorPfPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26findMaxIndMultipleDetectorPfPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26findMaxIndMultipleDetectorPfPii,@object # @_Z26findMaxIndMultipleDetectorPfPii
.section .rodata,"a",@progbits
.globl _Z26findMaxIndMultipleDetectorPfPii
.p2align 3, 0x0
_Z26findMaxIndMultipleDetectorPfPii:
.quad _Z41__device_stub__findMaxIndMultipleDetectorPfPii
.size _Z26findMaxIndMultipleDetectorPfPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26findMaxIndMultipleDetectorPfPii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__findMaxIndMultipleDetectorPfPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26findMaxIndMultipleDetectorPfPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z26findMaxIndMultipleDetectorPfPii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x170] ; /* 0x00005c00ff027624 */
/* 0x000fe200078e00ff */
/*0020*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*0030*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe400078e00ff */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*0050*/ ISETP.GE.AND P0, PT, R2, 0x2, PT ; /* 0x000000020200780c */
/* 0x000fda0003f06270 */
/*0060*/ @!P0 BRA 0x650 ; /* 0x000005e000008947 */
/* 0x000fea0003800000 */
/*0070*/ IADD3 R0, R2, -0x2, RZ ; /* 0xfffffffe02007810 */
/* 0x000fe20007ffe0ff */
/*0080*/ IMAD.MOV.U32 R6, RZ, RZ, 0x1 ; /* 0x00000001ff067424 */
/* 0x000fe400078e00ff */
/*0090*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe200078e00ff */
/*00a0*/ ISETP.GE.U32.AND P1, PT, R0, 0x3, PT ; /* 0x000000030000780c */
/* 0x000fe20003f26070 */
/*00b0*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*00c0*/ IADD3 R6, -R6, c[0x0][0x170], RZ ; /* 0x00005c0006067a10 */
/* 0x000fe20007ffe1ff */
/*00d0*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fc600078e00ff */
/*00e0*/ LOP3.LUT P0, R6, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306067812 */
/* 0x000fce000780c0ff */
/*00f0*/ @!P1 BRA 0x4e0 ; /* 0x000003e000009947 */
/* 0x000fec0003800000 */
/*0100*/ IADD3 R0, R2, -0x1, RZ ; /* 0xffffffff02007810 */
/* 0x000fe20007ffe0ff */
/*0110*/ IMAD.MOV.U32 R5, RZ, RZ, RZ ; /* 0x000000ffff057224 */
/* 0x000fe400078e00ff */
/*0120*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x160] ; /* 0x00005800ff027624 */
/* 0x000fe200078e00ff */
/*0130*/ LOP3.LUT R7, R0, 0x3, RZ, 0xc0, !PT ; /* 0x0000000300077812 */
/* 0x000fe200078ec0ff */
/*0140*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x164] ; /* 0x00005900ff037624 */
/* 0x000fe400078e00ff */
/*0150*/ IMAD.MOV.U32 R0, RZ, RZ, 0x1 ; /* 0x00000001ff007424 */
/* 0x000fe200078e00ff */
/*0160*/ IADD3 R7, R7, -c[0x0][0x170], RZ ; /* 0x80005c0007077a10 */
/* 0x000fe20007ffe0ff */
/*0170*/ IMAD.MOV.U32 R4, RZ, RZ, 0x1 ; /* 0x00000001ff047424 */
/* 0x000fe400078e00ff */
/*0180*/ IMAD.MOV.U32 R8, RZ, RZ, 0x4 ; /* 0x00000004ff087424 */
/* 0x000fe200078e00ff */
/*0190*/ LDG.E R10, [R2.64+0x4] ; /* 0x00000404020a7981 */
/* 0x000ea6000c1e1900 */
/*01a0*/ IMAD.WIDE R8, R5, R8, c[0x0][0x160] ; /* 0x0000580005087625 */
/* 0x000fe200078e0208 */
/*01b0*/ LDG.E R13, [R2.64+0x8] ; /* 0x00000804020d7981 */
/* 0x000ee8000c1e1900 */
/*01c0*/ LDG.E R11, [R8.64] ; /* 0x00000004080b7981 */
/* 0x000ea8000c1e1900 */
/*01d0*/ LDG.E R12, [R2.64+0xc] ; /* 0x00000c04020c7981 */
/* 0x000f28000c1e1900 */
/*01e0*/ LDG.E R15, [R2.64+0x10] ; /* 0x00001004020f7981 */
/* 0x000f62000c1e1900 */
/*01f0*/ FSETP.GEU.AND P3, PT, R11, R10, PT ; /* 0x0000000a0b00720b */
/* 0x004fda0003f6e000 */
/*0200*/ @P3 FSETP.NEU.AND P1, PT, R11, R10, PT ; /* 0x0000000a0b00320b */
/* 0x000fe20003f2d000 */
/*0210*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a3224 */
/* 0x000fe200078e000b */
/*0220*/ IADD3 R11, P4, R2, 0x4, RZ ; /* 0x00000004020b7810 */
/* 0x000fc80007f9e0ff */
/*0230*/ FSETP.GEU.AND P2, PT, R10, R13, PT ; /* 0x0000000d0a00720b */
/* 0x008fe20003f4e000 */
/*0240*/ IMAD.X R14, RZ, RZ, R3, P4 ; /* 0x000000ffff0e7224 */
/* 0x000fe400020e0603 */
/*0250*/ @P3 IMAD.MOV.U32 R11, RZ, RZ, R8 ; /* 0x000000ffff0b3224 */
/* 0x000fe400078e0008 */
/*0260*/ @P3 IMAD.MOV.U32 R14, RZ, RZ, R9 ; /* 0x000000ffff0e3224 */
/* 0x000fe400078e0009 */
/*0270*/ IMAD.MOV.U32 R8, RZ, RZ, R11 ; /* 0x000000ffff087224 */
/* 0x000fe400078e000b */
/*0280*/ IMAD.MOV.U32 R9, RZ, RZ, R14 ; /* 0x000000ffff097224 */
/* 0x000fc800078e000e */
/*0290*/ @P2 FSETP.NEU.AND P4, PT, R10, R13, PT ; /* 0x0000000d0a00220b */
/* 0x000fe40003f8d000 */
/*02a0*/ @P2 LDG.E R13, [R8.64] ; /* 0x00000004080d2981 */
/* 0x000122000c1e1900 */
/*02b0*/ PLOP3.LUT P5, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003fae170 */
/*02c0*/ @P3 PLOP3.LUT P5, PT, P1, PT, PT, 0x80, 0x0 ; /* 0x000000000000381c */
/* 0x000fe40000faf070 */
/*02d0*/ PLOP3.LUT P1, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f2e170 */
/*02e0*/ @P2 PLOP3.LUT P1, PT, P4, PT, PT, 0x80, 0x0 ; /* 0x000000000000281c */
/* 0x000fe2000272f070 */
/*02f0*/ HFMA2.MMA R10, -RZ, RZ, 0, 5.9604644775390625e-08 ; /* 0x00000001ff0a7435 */
/* 0x000fe200000001ff */
/*0300*/ @P3 IADD3 R11, R4, 0x1, RZ ; /* 0x00000001040b3810 */
/* 0x000fce0007ffe0ff */
/*0310*/ @P5 IMAD.MOV R11, RZ, RZ, R4 ; /* 0x000000ffff0b5224 */
/* 0x000fe400078e0204 */
/*0320*/ IMAD.MOV.U32 R4, RZ, RZ, R0 ; /* 0x000000ffff047224 */
/* 0x000fe400078e0000 */
/*0330*/ @P3 IMAD.MOV.U32 R10, RZ, RZ, R11 ; /* 0x000000ffff0a3224 */
/* 0x000fe400078e000b */
/*0340*/ @P3 IMAD.MOV.U32 R4, RZ, RZ, R5 ; /* 0x000000ffff043224 */
/* 0x000fe200078e0005 */
/*0350*/ IADD3 R5, R0, 0x1, RZ ; /* 0x0000000100057810 */
/* 0x000fe40007ffe0ff */
/*0360*/ @P2 IADD3 R11, R10, 0x1, RZ ; /* 0x000000010a0b2810 */
/* 0x000fe20007ffe0ff */
/*0370*/ @P1 IMAD.MOV R11, RZ, RZ, R10 ; /* 0x000000ffff0b1224 */
/* 0x000fc400078e020a */
/*0380*/ @P2 IMAD.MOV.U32 R5, RZ, RZ, R4 ; /* 0x000000ffff052224 */
/* 0x000fe400078e0004 */
/*0390*/ IMAD.MOV.U32 R9, RZ, RZ, 0x1 ; /* 0x00000001ff097424 */
/* 0x001fe400078e00ff */
/*03a0*/ @P2 IMAD.MOV.U32 R9, RZ, RZ, R11 ; /* 0x000000ffff092224 */
/* 0x000fca00078e000b */
/*03b0*/ IADD3 R4, R9, 0x1, RZ ; /* 0x0000000109047810 */
/* 0x000fe40007ffe0ff */
/*03c0*/ FSETP.GEU.AND P4, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x010fc80003f8e000 */
/*03d0*/ FSEL R8, R12, R13, !P4 ; /* 0x0000000d0c087208 */
/* 0x000fc80006000000 */
/*03e0*/ FSETP.GEU.AND P3, PT, R8, R15, PT ; /* 0x0000000f0800720b */
/* 0x020fe40003f6e000 */
/*03f0*/ FSETP.NEU.AND P1, PT, R13, R12, PT ; /* 0x0000000c0d00720b */
/* 0x000fc60003f2d000 */
/*0400*/ @!P4 IADD3 R5, R0, 0x2, RZ ; /* 0x000000020005c810 */
/* 0x000fe40007ffe0ff */
/*0410*/ FSETP.NEU.AND P2, PT, R8, R15, PT ; /* 0x0000000f0800720b */
/* 0x000fcc0003f4d000 */
/*0420*/ @!P3 IADD3 R5, R0.reuse, 0x3, RZ ; /* 0x000000030005b810 */
/* 0x040fe40007ffe0ff */
/*0430*/ IADD3 R0, R0, 0x4, RZ ; /* 0x0000000400007810 */
/* 0x000fe20007ffe0ff */
/*0440*/ @P1 IMAD.MOV R4, RZ, RZ, R9 ; /* 0x000000ffff041224 */
/* 0x000fc800078e0209 */
/*0450*/ IMAD.IADD R8, R7, 0x1, R0 ; /* 0x0000000107087824 */
/* 0x000fca00078e0200 */
/*0460*/ ISETP.NE.AND P1, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f25270 */
/*0470*/ SEL R9, RZ, 0x1, P2 ; /* 0x00000001ff097807 */
/* 0x000fe40001000000 */
/*0480*/ SEL R4, R4, 0x1, P4 ; /* 0x0000000104047807 */
/* 0x000fe40002000000 */
/*0490*/ IADD3 R2, P2, R2, 0x10, RZ ; /* 0x0000001002027810 */
/* 0x000fc60007f5e0ff */
/*04a0*/ IMAD.IADD R4, R4, 0x1, R9 ; /* 0x0000000104047824 */
/* 0x000fe400078e0209 */
/*04b0*/ IMAD.X R3, RZ, RZ, R3, P2 ; /* 0x000000ffff037224 */
/* 0x000fc600010e0603 */
/*04c0*/ SEL R4, R4, 0x1, P3 ; /* 0x0000000104047807 */
/* 0x000fe20001800000 */
/*04d0*/ @P1 BRA 0x180 ; /* 0xfffffca000001947 */
/* 0x000fea000383ffff */
/*04e0*/ @!P0 BRA 0x650 ; /* 0x0000016000008947 */
/* 0x000fea0003800000 */
/*04f0*/ MOV R12, 0x4 ; /* 0x00000004000c7802 */
/* 0x000fe20000000f00 */
/*0500*/ IMAD.MOV.U32 R8, RZ, RZ, R6 ; /* 0x000000ffff087224 */
/* 0x000fc800078e0006 */
/*0510*/ IMAD.WIDE R2, R0, R12, c[0x0][0x160] ; /* 0x0000580000027625 */
/* 0x000fc800078e020c */
/*0520*/ IMAD.MOV.U32 R10, RZ, RZ, R2 ; /* 0x000000ffff0a7224 */
/* 0x000fe400078e0002 */
/*0530*/ IMAD.MOV.U32 R11, RZ, RZ, R3 ; /* 0x000000ffff0b7224 */
/* 0x000fe400078e0003 */
/*0540*/ IMAD.WIDE R2, R12, R5, c[0x0][0x160] ; /* 0x000058000c027625 */
/* 0x000fc800078e0205 */
/*0550*/ IMAD.MOV.U32 R6, RZ, RZ, R10 ; /* 0x000000ffff067224 */
/* 0x000fe400078e000a */
/*0560*/ IMAD.MOV.U32 R7, RZ, RZ, R11 ; /* 0x000000ffff077224 */
/* 0x000fe200078e000b */
/*0570*/ LDG.E R3, [R2.64] ; /* 0x0000000402037981 */
/* 0x000ea8000c1e1900 */
/*0580*/ LDG.E R6, [R6.64] ; /* 0x0000000406067981 */
/* 0x000ea2000c1e1900 */
/*0590*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fe40007ffe0ff */
/*05a0*/ IADD3 R9, R4, 0x1, RZ ; /* 0x0000000104097810 */
/* 0x000fc40007ffe0ff */
/*05b0*/ ISETP.NE.AND P2, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe40003f45270 */
/*05c0*/ IADD3 R10, P3, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x000fca0007f7e0ff */
/*05d0*/ IMAD.X R11, RZ, RZ, R11, P3 ; /* 0x000000ffff0b7224 */
/* 0x000fe200018e060b */
/*05e0*/ FSETP.NEU.AND P1, PT, R3.reuse, R6.reuse, PT ; /* 0x000000060300720b */
/* 0x0c4fe40003f2d000 */
/*05f0*/ FSETP.GEU.AND P0, PT, R3, R6, PT ; /* 0x000000060300720b */
/* 0x000fc80003f0e000 */
/*0600*/ SEL R5, R0.reuse, R5, !P0 ; /* 0x0000000500057207 */
/* 0x040fe40004000000 */
/*0610*/ IADD3 R0, R0, 0x1, RZ ; /* 0x0000000100007810 */
/* 0x000fca0007ffe0ff */
/*0620*/ @P1 IMAD.MOV R9, RZ, RZ, R4 ; /* 0x000000ffff091224 */
/* 0x000fca00078e0204 */
/*0630*/ SEL R4, R9, 0x1, P0 ; /* 0x0000000109047807 */
/* 0x000fe20000000000 */
/*0640*/ @P2 BRA 0x540 ; /* 0xfffffef000002947 */
/* 0x000fea000383ffff */
/*0650*/ ISETP.GT.AND P0, PT, R4, 0x1, PT ; /* 0x000000010400780c */
/* 0x000fe20003f04270 */
/*0660*/ IMAD.MOV.U32 R2, RZ, RZ, c[0x0][0x168] ; /* 0x00005a00ff027624 */
/* 0x000fe400078e00ff */
/*0670*/ IMAD.MOV.U32 R3, RZ, RZ, c[0x0][0x16c] ; /* 0x00005b00ff037624 */
/* 0x000fe200078e00ff */
/*0680*/ SEL R5, R5, 0xffffffff, !P0 ; /* 0xffffffff05057807 */
/* 0x000fca0004000000 */
/*0690*/ STG.E [R2.64], R5 ; /* 0x0000000502007986 */
/* 0x000fe2000c101904 */
/*06a0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*06b0*/ BRA 0x6b0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*06c0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06d0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06e0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*06f0*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0700*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0710*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0720*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0730*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0740*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0750*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0760*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0770*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z26findMaxIndMultipleDetectorPfPii
.globl _Z26findMaxIndMultipleDetectorPfPii
.p2align 8
.type _Z26findMaxIndMultipleDetectorPfPii,@function
_Z26findMaxIndMultipleDetectorPfPii:
s_load_b32 s8, s[0:1], 0x10
s_mov_b32 s2, 0
s_waitcnt lgkmcnt(0)
s_cmp_lt_i32 s8, 2
s_cbranch_scc1 .LBB0_9
s_load_b64 s[2:3], s[0:1], 0x0
s_mov_b32 s6, 0
s_mov_b32 s9, 1
s_mov_b32 s10, 1
s_waitcnt lgkmcnt(0)
s_add_u32 s4, s2, 4
s_addc_u32 s5, s3, 0
.p2align 6
.LBB0_2:
s_ashr_i32 s7, s6, 31
s_mov_b32 s11, 1
s_lshl_b64 s[12:13], s[6:7], 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s14, s2, s12
s_addc_u32 s15, s3, s13
s_load_b32 s12, s[4:5], 0x0
s_load_b32 s13, s[14:15], 0x0
s_waitcnt lgkmcnt(0)
v_cmp_lt_f32_e64 s7, s13, s12
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s7
s_mov_b32 s7, s9
s_cbranch_vccnz .LBB0_6
v_cmp_neq_f32_e64 s7, s13, s12
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 vcc_lo, exec_lo, s7
s_cbranch_vccnz .LBB0_5
s_add_i32 s10, s10, 1
.LBB0_5:
s_mov_b32 s7, s6
s_mov_b32 s11, s10
.LBB0_6:
s_add_i32 s9, s9, 1
s_add_u32 s4, s4, 4
s_addc_u32 s5, s5, 0
s_cmp_eq_u32 s8, s9
s_cbranch_scc1 .LBB0_8
s_mov_b32 s10, s11
s_mov_b32 s6, s7
s_branch .LBB0_2
.LBB0_8:
s_cmp_lt_i32 s11, 2
s_cselect_b32 s2, s7, -1
.LBB0_9:
s_load_b64 s[0:1], s[0:1], 0x8
v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
s_waitcnt lgkmcnt(0)
global_store_b32 v0, v1, s[0:1]
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z26findMaxIndMultipleDetectorPfPii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 20
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 2
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z26findMaxIndMultipleDetectorPfPii, .Lfunc_end0-_Z26findMaxIndMultipleDetectorPfPii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .offset: 16
.size: 4
.value_kind: by_value
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 20
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z26findMaxIndMultipleDetectorPfPii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z26findMaxIndMultipleDetectorPfPii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 2
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0013f3aa_00000000-6_findMaxIndMultipleDetector.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2029:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii
.type _Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii, @function
_Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii:
.LFB2051:
.cfi_startproc
endbr64
subq $136, %rsp
.cfi_def_cfa_offset 144
movq %rdi, 24(%rsp)
movq %rsi, 16(%rsp)
movl %edx, 12(%rsp)
movq %fs:40, %rax
movq %rax, 120(%rsp)
xorl %eax, %eax
leaq 24(%rsp), %rax
movq %rax, 96(%rsp)
leaq 16(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 120(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $136, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 152
pushq 40(%rsp)
.cfi_def_cfa_offset 160
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26findMaxIndMultipleDetectorPfPii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2051:
.size _Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii, .-_Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii
.globl _Z26findMaxIndMultipleDetectorPfPii
.type _Z26findMaxIndMultipleDetectorPfPii, @function
_Z26findMaxIndMultipleDetectorPfPii:
.LFB2052:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z49__device_stub__Z26findMaxIndMultipleDetectorPfPiiPfPii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2052:
.size _Z26findMaxIndMultipleDetectorPfPii, .-_Z26findMaxIndMultipleDetectorPfPii
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26findMaxIndMultipleDetectorPfPii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26findMaxIndMultipleDetectorPfPii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2054:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "findMaxIndMultipleDetector.hip"
.globl _Z41__device_stub__findMaxIndMultipleDetectorPfPii # -- Begin function _Z41__device_stub__findMaxIndMultipleDetectorPfPii
.p2align 4, 0x90
.type _Z41__device_stub__findMaxIndMultipleDetectorPfPii,@function
_Z41__device_stub__findMaxIndMultipleDetectorPfPii: # @_Z41__device_stub__findMaxIndMultipleDetectorPfPii
.cfi_startproc
# %bb.0:
subq $104, %rsp
.cfi_def_cfa_offset 112
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26findMaxIndMultipleDetectorPfPii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $120, %rsp
.cfi_adjust_cfa_offset -120
retq
.Lfunc_end0:
.size _Z41__device_stub__findMaxIndMultipleDetectorPfPii, .Lfunc_end0-_Z41__device_stub__findMaxIndMultipleDetectorPfPii
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26findMaxIndMultipleDetectorPfPii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26findMaxIndMultipleDetectorPfPii,@object # @_Z26findMaxIndMultipleDetectorPfPii
.section .rodata,"a",@progbits
.globl _Z26findMaxIndMultipleDetectorPfPii
.p2align 3, 0x0
_Z26findMaxIndMultipleDetectorPfPii:
.quad _Z41__device_stub__findMaxIndMultipleDetectorPfPii
.size _Z26findMaxIndMultipleDetectorPfPii, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26findMaxIndMultipleDetectorPfPii"
.size .L__unnamed_1, 36
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__findMaxIndMultipleDetectorPfPii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26findMaxIndMultipleDetectorPfPii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
CUresult result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
__global__ void myFirstKernel(void) {
printf("Hi from the very best kernel\n");
} | code for sm_80
Function : _Z13myFirstKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
CUresult result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
__global__ void myFirstKernel(void) {
printf("Hi from the very best kernel\n");
} | .file "tmpxft_00138c04_00000000-6_secondFile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13myFirstKernelvv
.type _Z32__device_stub__Z13myFirstKernelvv, @function
_Z32__device_stub__Z13myFirstKernelvv:
.LFB2081:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13myFirstKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z32__device_stub__Z13myFirstKernelvv, .-_Z32__device_stub__Z13myFirstKernelvv
.globl _Z13myFirstKernelv
.type _Z13myFirstKernelv, @function
_Z13myFirstKernelv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13myFirstKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z13myFirstKernelv, .-_Z13myFirstKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13myFirstKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13myFirstKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <cuda.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
CUresult result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
__global__ void myFirstKernel(void) {
printf("Hi from the very best kernel\n");
} | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
hipError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
__global__ void myFirstKernel(void) {
printf("Hi from the very best kernel\n");
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
hipError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
__global__ void myFirstKernel(void) {
printf("Hi from the very best kernel\n");
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13myFirstKernelv
.globl _Z13myFirstKernelv
.p2align 8
.type _Z13myFirstKernelv,@function
_Z13myFirstKernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 30
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13myFirstKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13myFirstKernelv, .Lfunc_end0-_Z13myFirstKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hi from the very best kernel\n"
.size .str, 30
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13myFirstKernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z13myFirstKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | /**
* Copyright 1993-2012 NVIDIA Corporation. All rights reserved.
*
* Please refer to the NVIDIA end user license agreement (EULA) associated
* with this source code for terms and conditions that govern your use of
* this software. Any use, reproduction, disclosure, or distribution of
* this software and related documentation outside the terms of the EULA
* is strictly prohibited.
*/
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
/**
* This macro checks return value of the CUDA runtime call and exits
* the application if the call failed.
*
* See cuda.h for error code descriptions.
*/
#define CHECK_CUDA_RESULT(N) { \
hipError_t result = N; \
if (result != 0) { \
printf("CUDA call on line %d returned error %d\n", __LINE__, \
result); \
exit(1); \
} }
__global__ void myFirstKernel(void) {
printf("Hi from the very best kernel\n");
} | .text
.file "secondFile.hip"
.globl _Z28__device_stub__myFirstKernelv # -- Begin function _Z28__device_stub__myFirstKernelv
.p2align 4, 0x90
.type _Z28__device_stub__myFirstKernelv,@function
_Z28__device_stub__myFirstKernelv: # @_Z28__device_stub__myFirstKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13myFirstKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__myFirstKernelv, .Lfunc_end0-_Z28__device_stub__myFirstKernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13myFirstKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13myFirstKernelv,@object # @_Z13myFirstKernelv
.section .rodata,"a",@progbits
.globl _Z13myFirstKernelv
.p2align 3, 0x0
_Z13myFirstKernelv:
.quad _Z28__device_stub__myFirstKernelv
.size _Z13myFirstKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13myFirstKernelv"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__myFirstKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13myFirstKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13myFirstKernelv
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ IMAD.MOV.U32 R1, RZ, RZ, c[0x0][0x28] ; /* 0x00000a00ff017624 */
/* 0x000fe400078e00ff */
/*0010*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x000fe20000000f00 */
/*0020*/ IMAD.MOV.U32 R4, RZ, RZ, c[0x4][0x8] ; /* 0x01000200ff047624 */
/* 0x000fe200078e00ff */
/*0030*/ CS2R R6, SRZ ; /* 0x0000000000067805 */
/* 0x000fe2000001ff00 */
/*0040*/ IMAD.MOV.U32 R5, RZ, RZ, c[0x4][0xc] ; /* 0x01000300ff057624 */
/* 0x000fe200078e00ff */
/*0050*/ LDC.64 R2, c[0x4][R0] ; /* 0x0100000000027b82 */
/* 0x00006c0000000a00 */
/*0060*/ LEPC R8 ; /* 0x000000000008734e */
/* 0x000fe40000000000 */
/*0070*/ MOV R11, 0xe0 ; /* 0x000000e0000b7802 */
/* 0x000fe40000000f00 */
/*0080*/ MOV R20, 0x60 ; /* 0x0000006000147802 */
/* 0x000fe40000000f00 */
/*0090*/ MOV R21, 0x0 ; /* 0x0000000000157802 */
/* 0x000fe40000000f00 */
/*00a0*/ MOV R0, 0x0 ; /* 0x0000000000007802 */
/* 0x001fc40000000f00 */
/*00b0*/ IADD3 R20, P0, P1, -R20, R11, R8 ; /* 0x0000000b14147210 */
/* 0x000fc8000791e108 */
/*00c0*/ IADD3.X R21, ~R0, R21, R9, P0, P1 ; /* 0x0000001500157210 */
/* 0x000fc800007e2509 */
/*00d0*/ CALL.ABS.NOINC R2 ; /* 0x0000000002007343 */
/* 0x002fea0003c00000 */
/*00e0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*00f0*/ BRA 0xf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0100*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0110*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0120*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0130*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0140*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0150*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0160*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0170*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13myFirstKernelv
.globl _Z13myFirstKernelv
.p2align 8
.type _Z13myFirstKernelv,@function
_Z13myFirstKernelv:
s_load_b64 s[2:3], s[0:1], 0x50
v_mbcnt_lo_u32_b32 v20, -1, 0
v_mov_b32_e32 v6, 0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v20
v_readfirstlane_b32 s0, v4
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v4
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_6
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
s_waitcnt lgkmcnt(0)
global_load_b64 v[8:9], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[5:6], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v2, v2, v9
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v3, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v3, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v5, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
global_load_b64 v[6:7], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[6:7], v[8:9]
s_cbranch_execz .LBB0_5
s_mov_b32 s5, 0
.p2align 6
.LBB0_3:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[10:11], v0, s[2:3]
v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v1, v1, v8
v_and_b32_e32 v7, v2, v9
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
v_mov_b32_e32 v1, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
v_mov_b32_e32 v6, v2
global_load_b64 v[6:7], v[5:6], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_3
s_or_b32 exec_lo, exec_lo, s5
.LBB0_5:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_6:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v5, 0
v_readfirstlane_b32 s4, v6
v_readfirstlane_b32 s5, v7
s_mov_b32 s8, exec_lo
s_waitcnt lgkmcnt(0)
s_clause 0x1
global_load_b64 v[8:9], v5, s[2:3] offset:40
global_load_b128 v[0:3], v5, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v8
v_readfirstlane_b32 s7, v9
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_8
v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v10, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v11, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_8:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_lshlrev_b64 v[4:5], 6, v[4:5]
s_waitcnt vmcnt(0)
v_add_co_u32 v2, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s9, v3, vcc_lo
v_mov_b32_e32 v3, 0
s_mov_b32 s8, 0
s_delay_alu instid0(VALU_DEP_3)
v_add_co_u32 v6, vcc_lo, v2, v4
v_mov_b32_e32 v2, 33
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v4, v3
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v8, s8
v_dual_mov_b32 v9, s9 :: v_dual_mov_b32 v10, s10
v_mov_b32_e32 v11, s11
s_clause 0x3
global_store_b128 v[6:7], v[2:5], off
global_store_b128 v[6:7], v[8:11], off offset:16
global_store_b128 v[6:7], v[8:11], off offset:32
global_store_b128 v[6:7], v[8:11], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_16
v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s4
v_mov_b32_e32 v12, s5
s_clause 0x1
global_load_b64 v[13:14], v10, s[2:3] offset:32 glc
global_load_b64 v[2:3], v10, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[8:9], v[13:14], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[13:14]
s_cbranch_execz .LBB0_12
s_mov_b32 s9, 0
.LBB0_11:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[8:9], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_11
.LBB0_12:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_14
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_14:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_16
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_16:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_20
.p2align 6
.LBB0_17:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_19
s_sleep 1
s_cbranch_execnz .LBB0_20
s_branch .LBB0_22
.p2align 6
.LBB0_19:
s_branch .LBB0_22
.LBB0_20:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_17
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_17
.LBB0_22:
global_load_b64 v[22:23], v[6:7], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_26
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_26
s_mov_b32 s0, 0
.LBB0_25:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_25
.LBB0_26:
s_or_b32 exec_lo, exec_lo, s1
s_getpc_b64 s[4:5]
s_add_u32 s4, s4, .str@rel32@lo+4
s_addc_u32 s5, s5, .str@rel32@hi+12
s_mov_b32 s0, -1
s_cmp_lg_u64 s[4:5], 0
s_cbranch_scc0 .LBB0_105
s_waitcnt vmcnt(0)
v_dual_mov_b32 v1, v23 :: v_dual_and_b32 v0, -3, v22
v_mov_b32_e32 v25, 0
s_mov_b64 s[6:7], 30
s_branch .LBB0_29
.LBB0_28:
s_or_b32 exec_lo, exec_lo, s1
s_sub_u32 s6, s6, s8
s_subb_u32 s7, s7, s9
s_add_u32 s4, s4, s8
s_addc_u32 s5, s5, s9
s_cmp_lg_u64 s[6:7], 0
s_cbranch_scc0 .LBB0_104
.LBB0_29:
v_cmp_lt_u64_e64 s0, s[6:7], 56
s_delay_alu instid0(VALU_DEP_1)
s_and_b32 s0, s0, exec_lo
s_cselect_b32 s8, s6, 56
s_cselect_b32 s9, s7, 0
s_cmp_gt_u32 s8, 7
s_mov_b32 s0, -1
s_cbranch_scc1 .LBB0_34
v_mov_b32_e32 v2, 0
v_mov_b32_e32 v3, 0
s_cmp_eq_u32 s8, 0
s_cbranch_scc1 .LBB0_33
s_lshl_b64 s[0:1], s[8:9], 3
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[4:5]
.LBB0_32:
global_load_u8 v4, v25, s[12:13]
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v4
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[4:5], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s0, s10
v_or_b32_e32 v2, v4, v2
v_or_b32_e32 v3, v5, v3
s_cbranch_scc1 .LBB0_32
.LBB0_33:
s_mov_b32 s0, 0
s_mov_b32 s15, 0
.LBB0_34:
s_and_not1_b32 vcc_lo, exec_lo, s0
s_mov_b64 s[0:1], s[4:5]
s_cbranch_vccnz .LBB0_36
global_load_b64 v[2:3], v25, s[4:5]
s_add_i32 s15, s8, -8
s_add_u32 s0, s4, 8
s_addc_u32 s1, s5, 0
.LBB0_36:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_41
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_40
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_39:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v6, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v6
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[6:7], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v4, v6, v4
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v5, v7, v5
s_cbranch_scc1 .LBB0_39
.LBB0_40:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_42
s_branch .LBB0_43
.LBB0_41:
.LBB0_42:
global_load_b64 v[4:5], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_43:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_48
v_mov_b32_e32 v6, 0
v_mov_b32_e32 v7, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_47
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_46:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v8, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v8
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[8:9], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v6, v8, v6
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v7, v9, v7
s_cbranch_scc1 .LBB0_46
.LBB0_47:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_49
s_branch .LBB0_50
.LBB0_48:
.LBB0_49:
global_load_b64 v[6:7], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_50:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_55
v_mov_b32_e32 v8, 0
v_mov_b32_e32 v9, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_54
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_53:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v10, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v10
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[10:11], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v8, v10, v8
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v9, v11, v9
s_cbranch_scc1 .LBB0_53
.LBB0_54:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_56
s_branch .LBB0_57
.LBB0_55:
.LBB0_56:
global_load_b64 v[8:9], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_57:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_62
v_mov_b32_e32 v10, 0
v_mov_b32_e32 v11, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_61
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_60:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v12, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v12
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[12:13], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s14, s12
v_or_b32_e32 v10, v12, v10
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v11, v13, v11
s_cbranch_scc1 .LBB0_60
.LBB0_61:
s_mov_b32 s15, 0
s_cbranch_execz .LBB0_63
s_branch .LBB0_64
.LBB0_62:
.LBB0_63:
global_load_b64 v[10:11], v25, s[0:1]
s_add_i32 s15, s14, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_64:
s_cmp_gt_u32 s15, 7
s_cbranch_scc1 .LBB0_69
v_mov_b32_e32 v12, 0
v_mov_b32_e32 v13, 0
s_cmp_eq_u32 s15, 0
s_cbranch_scc1 .LBB0_68
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], 0
.LBB0_67:
s_delay_alu instid0(SALU_CYCLE_1)
s_add_u32 s16, s0, s12
s_addc_u32 s17, s1, s13
s_add_u32 s12, s12, 1
global_load_u8 v14, v25, s[16:17]
s_addc_u32 s13, s13, 0
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v14
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
v_lshlrev_b64 v[14:15], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_cmp_lg_u32 s15, s12
v_or_b32_e32 v12, v14, v12
s_delay_alu instid0(VALU_DEP_2)
v_or_b32_e32 v13, v15, v13
s_cbranch_scc1 .LBB0_67
.LBB0_68:
s_mov_b32 s14, 0
s_cbranch_execz .LBB0_70
s_branch .LBB0_71
.LBB0_69:
.LBB0_70:
global_load_b64 v[12:13], v25, s[0:1]
s_add_i32 s14, s15, -8
s_add_u32 s0, s0, 8
s_addc_u32 s1, s1, 0
.LBB0_71:
s_cmp_gt_u32 s14, 7
s_cbranch_scc1 .LBB0_76
v_mov_b32_e32 v14, 0
v_mov_b32_e32 v15, 0
s_cmp_eq_u32 s14, 0
s_cbranch_scc1 .LBB0_75
s_mov_b64 s[10:11], 0
s_mov_b64 s[12:13], s[0:1]
.LBB0_74:
global_load_u8 v16, v25, s[12:13]
s_add_i32 s14, s14, -1
s_waitcnt vmcnt(0)
v_and_b32_e32 v24, 0xffff, v16
s_delay_alu instid0(VALU_DEP_1)
v_lshlrev_b64 v[16:17], s10, v[24:25]
s_add_u32 s10, s10, 8
s_addc_u32 s11, s11, 0
s_add_u32 s12, s12, 1
s_addc_u32 s13, s13, 0
s_cmp_lg_u32 s14, 0
v_or_b32_e32 v14, v16, v14
v_or_b32_e32 v15, v17, v15
s_cbranch_scc1 .LBB0_74
.LBB0_75:
s_cbranch_execz .LBB0_77
s_branch .LBB0_78
.LBB0_76:
.LBB0_77:
global_load_b64 v[14:15], v25, s[0:1]
.LBB0_78:
v_mov_b32_e32 v24, v20
v_mov_b32_e32 v26, 0
v_mov_b32_e32 v27, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s0, v24
v_cmp_eq_u32_e64 s0, s0, v24
s_delay_alu instid0(VALU_DEP_1)
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_84
global_load_b64 v[18:19], v25, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[26:27], v25, s[2:3]
s_mov_b32 s10, exec_lo
s_waitcnt vmcnt(1)
v_and_b32_e32 v17, v17, v19
v_and_b32_e32 v16, v16, v18
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_lo_u32 v17, v17, 24
v_mul_hi_u32 v21, v16, 24
v_mul_lo_u32 v16, v16, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v17, v21, v17
s_waitcnt vmcnt(0)
v_add_co_u32 v16, vcc_lo, v26, v16
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v17, vcc_lo, v27, v17, vcc_lo
global_load_b64 v[16:17], v[16:17], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[26:27], v[18:19]
s_cbranch_execz .LBB0_83
s_mov_b32 s11, 0
.p2align 6
.LBB0_81:
s_sleep 1
s_clause 0x1
global_load_b64 v[16:17], v25, s[2:3] offset:40
global_load_b64 v[28:29], v25, s[2:3]
v_dual_mov_b32 v18, v26 :: v_dual_mov_b32 v19, v27
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v16, v16, v18
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[26:27], null, v16, 24, v[28:29]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v16, v27 :: v_dual_and_b32 v17, v17, v19
v_mad_u64_u32 v[27:28], null, v17, 24, v[16:17]
global_load_b64 v[16:17], v[26:27], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[26:27], v25, v[16:19], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[26:27], v[18:19]
s_or_b32 s11, vcc_lo, s11
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s11
s_cbranch_execnz .LBB0_81
s_or_b32 exec_lo, exec_lo, s11
.LBB0_83:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s10
.LBB0_84:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
s_clause 0x1
global_load_b64 v[28:29], v25, s[2:3] offset:40
global_load_b128 v[16:19], v25, s[2:3]
v_readfirstlane_b32 s10, v26
v_readfirstlane_b32 s11, v27
s_mov_b32 s14, exec_lo
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s12, v28
v_readfirstlane_b32 s13, v29
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[12:13], s[10:11], s[12:13]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_86
v_dual_mov_b32 v26, s14 :: v_dual_mov_b32 v27, 0
s_mul_i32 s14, s13, 24
s_mul_hi_u32 s15, s12, 24
v_dual_mov_b32 v28, 2 :: v_dual_mov_b32 v29, 1
s_add_i32 s15, s15, s14
s_mul_i32 s14, s12, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v30, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v31, vcc_lo, s15, v17, vcc_lo
global_store_b128 v[30:31], v[26:29], off offset:8
.LBB0_86:
s_or_b32 exec_lo, exec_lo, s1
v_cmp_gt_u64_e64 vcc_lo, s[6:7], 56
v_or_b32_e32 v21, 2, v0
s_lshl_b64 s[14:15], s[12:13], 12
v_lshlrev_b64 v[26:27], 6, v[24:25]
s_lshl_b32 s1, s8, 2
s_delay_alu instid0(SALU_CYCLE_1)
s_add_i32 s1, s1, 28
v_cndmask_b32_e32 v0, v21, v0, vcc_lo
s_waitcnt vmcnt(0)
v_add_co_u32 v18, vcc_lo, v18, s14
v_add_co_ci_u32_e32 v19, vcc_lo, s15, v19, vcc_lo
s_and_b32 s1, s1, 0x1e0
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v18, vcc_lo, v18, v26
v_and_or_b32 v0, v0, 0xffffff1f, s1
v_add_co_ci_u32_e32 v19, vcc_lo, v19, v27, vcc_lo
s_clause 0x3
global_store_b128 v[18:19], v[0:3], off
global_store_b128 v[18:19], v[4:7], off offset:16
global_store_b128 v[18:19], v[8:11], off offset:32
global_store_b128 v[18:19], v[12:15], off offset:48
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_94
s_clause 0x1
global_load_b64 v[8:9], v25, s[2:3] offset:32 glc
global_load_b64 v[0:1], v25, s[2:3] offset:40
v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v0
v_readfirstlane_b32 s15, v1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[14:15], s[14:15], s[10:11]
s_mul_i32 s15, s15, 24
s_mul_hi_u32 s16, s14, 24
s_mul_i32 s14, s14, 24
s_add_i32 s16, s16, s15
v_add_co_u32 v4, vcc_lo, v16, s14
v_add_co_ci_u32_e32 v5, vcc_lo, s16, v17, vcc_lo
s_mov_b32 s14, exec_lo
global_store_b64 v[4:5], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v25, v[6:9], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[2:3], v[8:9]
s_cbranch_execz .LBB0_90
s_mov_b32 s15, 0
.LBB0_89:
v_dual_mov_b32 v0, s10 :: v_dual_mov_b32 v1, s11
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[0:1], v25, v[0:3], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
s_or_b32 s15, vcc_lo, s15
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s15
s_cbranch_execnz .LBB0_89
.LBB0_90:
s_or_b32 exec_lo, exec_lo, s14
global_load_b64 v[0:1], v25, s[2:3] offset:16
s_mov_b32 s15, exec_lo
s_mov_b32 s14, exec_lo
v_mbcnt_lo_u32_b32 v2, s15, 0
s_delay_alu instid0(VALU_DEP_1)
v_cmpx_eq_u32_e32 0, v2
s_cbranch_execz .LBB0_92
s_bcnt1_i32_b32 s15, s15
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v2, s15
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_92:
s_or_b32 exec_lo, exec_lo, s14
s_waitcnt vmcnt(0)
global_load_b64 v[2:3], v[0:1], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
s_cbranch_vccnz .LBB0_94
global_load_b32 v24, v[0:1], off offset:24
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s14, v24
s_waitcnt_vscnt null, 0x0
global_store_b64 v[2:3], v[24:25], off
s_and_b32 m0, s14, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_94:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s13, 24
s_mul_hi_u32 s13, s12, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s13, s13, s1
s_mul_i32 s1, s12, 24
v_add_co_u32 v0, vcc_lo, v16, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s13, v17, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_98
.p2align 6
.LBB0_95:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_97
s_sleep 1
s_cbranch_execnz .LBB0_98
s_branch .LBB0_100
.p2align 6
.LBB0_97:
s_branch .LBB0_100
.LBB0_98:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_95
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_95
.LBB0_100:
global_load_b64 v[0:1], v[18:19], off
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_28
s_clause 0x2
global_load_b64 v[4:5], v25, s[2:3] offset:40
global_load_b64 v[8:9], v25, s[2:3] offset:24 glc
global_load_b64 v[6:7], v25, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v10, vcc_lo, v4, 1
v_add_co_ci_u32_e32 v11, vcc_lo, 0, v5, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v2, vcc_lo, v10, s10
v_add_co_ci_u32_e32 v3, vcc_lo, s11, v11, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
v_dual_cndmask_b32 v3, v3, v11 :: v_dual_cndmask_b32 v2, v2, v10
v_and_b32_e32 v5, v3, v5
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_and_b32_e32 v4, v2, v4
v_mul_hi_u32 v10, v4, 24
v_mul_lo_u32 v4, v4, 24
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
v_add_co_u32 v6, vcc_lo, v6, v4
v_mov_b32_e32 v4, v8
v_mul_lo_u32 v5, v5, 24
v_add_nc_u32_e32 v5, v10, v5
s_delay_alu instid0(VALU_DEP_1)
v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
v_mov_b32_e32 v5, v9
global_store_b64 v[6:7], v[8:9], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[8:9]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_28
s_mov_b32 s0, 0
.LBB0_103:
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[8:9], v25, v[2:5], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[4:5]
v_dual_mov_b32 v4, v8 :: v_dual_mov_b32 v5, v9
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_103
s_branch .LBB0_28
.LBB0_104:
s_mov_b32 s0, 0
.LBB0_105:
s_delay_alu instid0(SALU_CYCLE_1)
s_and_b32 vcc_lo, exec_lo, s0
s_cbranch_vccz .LBB0_132
v_readfirstlane_b32 s0, v20
v_mov_b32_e32 v4, 0
v_mov_b32_e32 v5, 0
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_eq_u32_e64 s0, s0, v20
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_112
s_waitcnt vmcnt(0)
v_mov_b32_e32 v0, 0
s_mov_b32 s4, exec_lo
global_load_b64 v[6:7], v0, s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[3:4], v0, s[2:3]
s_waitcnt vmcnt(1)
v_and_b32_e32 v1, v1, v6
v_and_b32_e32 v2, v2, v7
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_mul_hi_u32 v5, v1, 24
v_mul_lo_u32 v2, v2, 24
v_mul_lo_u32 v1, v1, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_add_nc_u32_e32 v2, v5, v2
s_waitcnt vmcnt(0)
v_add_co_u32 v1, vcc_lo, v3, v1
s_delay_alu instid0(VALU_DEP_2)
v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
global_load_b64 v[4:5], v[1:2], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmpx_ne_u64_e64 v[4:5], v[6:7]
s_cbranch_execz .LBB0_111
s_mov_b32 s5, 0
.p2align 6
.LBB0_109:
s_sleep 1
s_clause 0x1
global_load_b64 v[1:2], v0, s[2:3] offset:40
global_load_b64 v[8:9], v0, s[2:3]
v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
s_waitcnt vmcnt(1)
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_and_b32_e32 v1, v1, v6
s_waitcnt vmcnt(0)
v_mad_u64_u32 v[3:4], null, v1, 24, v[8:9]
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_dual_mov_b32 v1, v4 :: v_dual_and_b32 v2, v2, v7
v_mad_u64_u32 v[4:5], null, v2, 24, v[1:2]
global_load_b64 v[4:5], v[3:4], off glc
s_waitcnt vmcnt(0)
global_atomic_cmpswap_b64 v[4:5], v0, v[4:7], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
s_or_b32 s5, vcc_lo, s5
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s5
s_cbranch_execnz .LBB0_109
s_or_b32 exec_lo, exec_lo, s5
.LBB0_111:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s4
.LBB0_112:
s_delay_alu instid0(SALU_CYCLE_1)
s_or_b32 exec_lo, exec_lo, s1
v_mov_b32_e32 v21, 0
v_readfirstlane_b32 s4, v4
v_readfirstlane_b32 s5, v5
s_mov_b32 s8, exec_lo
s_clause 0x1
global_load_b64 v[6:7], v21, s[2:3] offset:40
global_load_b128 v[0:3], v21, s[2:3]
s_waitcnt vmcnt(1)
v_readfirstlane_b32 s6, v6
v_readfirstlane_b32 s7, v7
s_delay_alu instid0(VALU_DEP_1)
s_and_b64 s[6:7], s[4:5], s[6:7]
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_114
v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, 0
s_mul_i32 s8, s7, 24
s_mul_hi_u32 s9, s6, 24
v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
s_add_i32 s9, s9, s8
s_mul_i32 s8, s6, 24
s_waitcnt vmcnt(0)
v_add_co_u32 v8, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v9, vcc_lo, s9, v1, vcc_lo
global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_114:
s_or_b32 exec_lo, exec_lo, s1
s_lshl_b64 s[8:9], s[6:7], 12
v_and_or_b32 v22, v22, 0xffffff1d, 34
s_waitcnt vmcnt(0)
v_add_co_u32 v4, vcc_lo, v2, s8
v_add_co_ci_u32_e32 v5, vcc_lo, s9, v3, vcc_lo
v_lshlrev_b64 v[2:3], 6, v[20:21]
s_mov_b32 s8, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
s_mov_b32 s9, s8
s_mov_b32 s10, s8
s_mov_b32 s11, s8
v_add_co_u32 v8, vcc_lo, v4, v2
v_mov_b32_e32 v6, 0
v_add_co_ci_u32_e32 v9, vcc_lo, v5, v3, vcc_lo
v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v5, s11
v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, s10
s_delay_alu instid0(VALU_DEP_4)
v_mov_b32_e32 v7, v6
s_clause 0x4
global_store_b64 v[8:9], v[22:23], off
global_store_b128 v[8:9], v[2:5], off offset:8
global_store_b128 v[8:9], v[2:5], off offset:24
global_store_b128 v[8:9], v[2:5], off offset:40
global_store_b64 v[8:9], v[6:7], off offset:56
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_122
v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s4
v_mov_b32_e32 v10, s5
s_clause 0x1
global_load_b64 v[11:12], v8, s[2:3] offset:32 glc
global_load_b64 v[2:3], v8, s[2:3] offset:40
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
v_readfirstlane_b32 s9, v3
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b64 s[8:9], s[8:9], s[4:5]
s_mul_i32 s9, s9, 24
s_mul_hi_u32 s10, s8, 24
s_mul_i32 s8, s8, 24
s_add_i32 s10, s10, s9
v_add_co_u32 v6, vcc_lo, v0, s8
v_add_co_ci_u32_e32 v7, vcc_lo, s10, v1, vcc_lo
s_mov_b32 s8, exec_lo
global_store_b64 v[6:7], v[11:12], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[4:5], v8, v[9:12], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmpx_ne_u64_e64 v[4:5], v[11:12]
s_cbranch_execz .LBB0_118
s_mov_b32 s9, 0
.LBB0_117:
v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5
s_sleep 1
global_store_b64 v[6:7], v[4:5], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v8, v[2:5], s[2:3] offset:32 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
s_or_b32 s9, vcc_lo, s9
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s9
s_cbranch_execnz .LBB0_117
.LBB0_118:
s_or_b32 exec_lo, exec_lo, s8
v_mov_b32_e32 v2, 0
s_mov_b32 s9, exec_lo
s_mov_b32 s8, exec_lo
v_mbcnt_lo_u32_b32 v4, s9, 0
global_load_b64 v[2:3], v2, s[2:3] offset:16
v_cmpx_eq_u32_e32 0, v4
s_cbranch_execz .LBB0_120
s_bcnt1_i32_b32 s9, s9
s_delay_alu instid0(SALU_CYCLE_1)
v_dual_mov_b32 v5, 0 :: v_dual_mov_b32 v4, s9
s_waitcnt vmcnt(0)
global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_120:
s_or_b32 exec_lo, exec_lo, s8
s_waitcnt vmcnt(0)
global_load_b64 v[4:5], v[2:3], off offset:16
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
s_cbranch_vccnz .LBB0_122
global_load_b32 v2, v[2:3], off offset:24
v_mov_b32_e32 v3, 0
s_waitcnt vmcnt(0)
v_readfirstlane_b32 s8, v2
s_waitcnt_vscnt null, 0x0
global_store_b64 v[4:5], v[2:3], off
s_and_b32 m0, s8, 0xff
s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_122:
s_or_b32 exec_lo, exec_lo, s1
s_mul_i32 s1, s7, 24
s_mul_hi_u32 s7, s6, 24
s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
s_add_i32 s7, s7, s1
s_mul_i32 s1, s6, 24
v_add_co_u32 v0, vcc_lo, v0, s1
v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v0, 20
v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
s_branch .LBB0_126
.p2align 6
.LBB0_123:
s_or_b32 exec_lo, exec_lo, s1
s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
v_readfirstlane_b32 s1, v2
s_cmp_eq_u32 s1, 0
s_cbranch_scc1 .LBB0_125
s_sleep 1
s_cbranch_execnz .LBB0_126
s_branch .LBB0_128
.p2align 6
.LBB0_125:
s_branch .LBB0_128
.LBB0_126:
v_mov_b32_e32 v2, 1
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_123
global_load_b32 v2, v[0:1], off glc
s_waitcnt vmcnt(0)
buffer_gl1_inv
buffer_gl0_inv
v_and_b32_e32 v2, 1, v2
s_branch .LBB0_123
.LBB0_128:
s_and_saveexec_b32 s1, s0
s_cbranch_execz .LBB0_132
v_mov_b32_e32 v6, 0
s_clause 0x2
global_load_b64 v[2:3], v6, s[2:3] offset:40
global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
global_load_b64 v[4:5], v6, s[2:3]
s_waitcnt vmcnt(2)
v_add_co_u32 v9, vcc_lo, v2, 1
v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_add_co_u32 v0, vcc_lo, v9, s4
v_add_co_ci_u32_e32 v1, vcc_lo, s5, v10, vcc_lo
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
v_and_b32_e32 v3, v1, v3
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_and_b32_e32 v2, v0, v2
v_mul_lo_u32 v3, v3, 24
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mul_hi_u32 v9, v2, 24
v_mul_lo_u32 v2, v2, 24
v_add_nc_u32_e32 v3, v9, v3
s_waitcnt vmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
v_add_co_u32 v4, vcc_lo, v4, v2
v_mov_b32_e32 v2, v7
v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
v_mov_b32_e32 v3, v8
global_store_b64 v[4:5], v[7:8], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
s_and_b32 exec_lo, exec_lo, vcc_lo
s_cbranch_execz .LBB0_132
s_mov_b32 s0, 0
.LBB0_131:
s_sleep 1
global_store_b64 v[4:5], v[2:3], off
s_waitcnt_vscnt null, 0x0
global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[2:3] offset:24 glc
s_waitcnt vmcnt(0)
v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
s_or_b32 s0, vcc_lo, s0
s_delay_alu instid0(SALU_CYCLE_1)
s_and_not1_b32 exec_lo, exec_lo, s0
s_cbranch_execnz .LBB0_131
.LBB0_132:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13myFirstKernelv
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 256
.amdhsa_user_sgpr_count 15
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 0
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 0
.amdhsa_next_free_vgpr 32
.amdhsa_next_free_sgpr 18
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13myFirstKernelv, .Lfunc_end0-_Z13myFirstKernelv
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type .str,@object
.section .rodata.str1.1,"aMS",@progbits,1
.str:
.asciz "Hi from the very best kernel\n"
.size .str, 30
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .offset: 0
.size: 4
.value_kind: hidden_block_count_x
- .offset: 4
.size: 4
.value_kind: hidden_block_count_y
- .offset: 8
.size: 4
.value_kind: hidden_block_count_z
- .offset: 12
.size: 2
.value_kind: hidden_group_size_x
- .offset: 14
.size: 2
.value_kind: hidden_group_size_y
- .offset: 16
.size: 2
.value_kind: hidden_group_size_z
- .offset: 18
.size: 2
.value_kind: hidden_remainder_x
- .offset: 20
.size: 2
.value_kind: hidden_remainder_y
- .offset: 22
.size: 2
.value_kind: hidden_remainder_z
- .offset: 40
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 48
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 56
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 64
.size: 2
.value_kind: hidden_grid_dims
- .offset: 80
.size: 8
.value_kind: hidden_hostcall_buffer
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 256
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13myFirstKernelv
.private_segment_fixed_size: 0
.sgpr_count: 20
.sgpr_spill_count: 0
.symbol: _Z13myFirstKernelv.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 32
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00138c04_00000000-6_secondFile.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2059:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2059:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z32__device_stub__Z13myFirstKernelvv
.type _Z32__device_stub__Z13myFirstKernelvv, @function
_Z32__device_stub__Z13myFirstKernelvv:
.LFB2081:
.cfi_startproc
endbr64
subq $88, %rsp
.cfi_def_cfa_offset 96
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl $1, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl $1, 36(%rsp)
leaq 8(%rsp), %rcx
movq %rsp, %rdx
leaq 28(%rsp), %rsi
leaq 16(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 8(%rsp)
.cfi_def_cfa_offset 104
pushq 8(%rsp)
.cfi_def_cfa_offset 112
leaq 80(%rsp), %r9
movq 44(%rsp), %rcx
movl 52(%rsp), %r8d
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
leaq _Z13myFirstKernelv(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 96
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2081:
.size _Z32__device_stub__Z13myFirstKernelvv, .-_Z32__device_stub__Z13myFirstKernelvv
.globl _Z13myFirstKernelv
.type _Z13myFirstKernelv, @function
_Z13myFirstKernelv:
.LFB2082:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z32__device_stub__Z13myFirstKernelvv
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2082:
.size _Z13myFirstKernelv, .-_Z13myFirstKernelv
.section .rodata.str1.1,"aMS",@progbits,1
.LC0:
.string "_Z13myFirstKernelv"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2084:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z13myFirstKernelv(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2084:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "secondFile.hip"
.globl _Z28__device_stub__myFirstKernelv # -- Begin function _Z28__device_stub__myFirstKernelv
.p2align 4, 0x90
.type _Z28__device_stub__myFirstKernelv,@function
_Z28__device_stub__myFirstKernelv: # @_Z28__device_stub__myFirstKernelv
.cfi_startproc
# %bb.0:
subq $56, %rsp
.cfi_def_cfa_offset 64
leaq 32(%rsp), %rdi
leaq 16(%rsp), %rsi
leaq 8(%rsp), %rdx
movq %rsp, %rcx
callq __hipPopCallConfiguration
movq 32(%rsp), %rsi
movl 40(%rsp), %edx
movq 16(%rsp), %rcx
movl 24(%rsp), %r8d
leaq 48(%rsp), %r9
movl $_Z13myFirstKernelv, %edi
pushq (%rsp)
.cfi_adjust_cfa_offset 8
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $72, %rsp
.cfi_adjust_cfa_offset -72
retq
.Lfunc_end0:
.size _Z28__device_stub__myFirstKernelv, .Lfunc_end0-_Z28__device_stub__myFirstKernelv
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB1_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB1_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13myFirstKernelv, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end1:
.size __hip_module_ctor, .Lfunc_end1-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB2_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB2_2:
retq
.Lfunc_end2:
.size __hip_module_dtor, .Lfunc_end2-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z13myFirstKernelv,@object # @_Z13myFirstKernelv
.section .rodata,"a",@progbits
.globl _Z13myFirstKernelv
.p2align 3, 0x0
_Z13myFirstKernelv:
.quad _Z28__device_stub__myFirstKernelv
.size _Z13myFirstKernelv, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z13myFirstKernelv"
.size .L__unnamed_1, 19
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__myFirstKernelv
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z13myFirstKernelv
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA device assembly. | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <cuda.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void matrixMulCPU(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C[i*wB+j] = 0.0;
for (k=0; k<wA; k++)
C[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
__global__ void matrixMultGPU(float* a, float* b, float* c, int nColsA,
int nRowsC, int nColsC){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < nRowsC && col < nColsC){
for(int i = 0; i < nColsA; ++i){
//In b[], nColsA = nRowsB
c[row * nColsC + col] += a[row * nColsA + i] * b[i * nColsA + col];
}
}
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*1.0f;
else
M[i*wM+j] = -1.0f/(float)(wM);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int diff(float *A, float *B, int hA, int wA, int wB, float *C_gpu)
{
float *C_cpu;
int size_C = wB * hA;
C_cpu = (float*)malloc(size_C*sizeof(float));
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C_cpu[i*wB+j] = 0.0;
for (k=0; k<wA; k++){
C_cpu[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
//printf("\n\nMATRIX C_cpu\n");print_matrix(C_cpu, hA, wB);
for (i=0; i<hA; i++)
for (j=0; j<wB; j++)
if (fabsf(C_cpu[i*wB+j]-C_gpu[i*wB+j])>1e-5)
{
printf("[%i,%i]: %f!=%f\n", i, j, C_cpu[i*wB+j], C_gpu[i*wB+j]);
return(0);
}
return(1);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C;
float *a_GPU, *b_GPU, *c_GPU, *gpu_c_host;
int hA, wA, hB, wB;
double t0, t1;
int i;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
//init matrix sizes
int size_A = wA * hA;
int size_B = wB * hB;
int size_C = wB * hA;
// CPU Init A and B, malloc C
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA, 1.0);
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB, 2.0);
C = (float*)malloc(size_B*sizeof(float));
for (i = 0; i < (hA*wB); i++) {
C[i] = 0.0;
}
//GPU malloc A,B and C
cudaMalloc((void **)&a_GPU, size_A * sizeof(float));
cudaMalloc((void **)&b_GPU, size_B * sizeof(float));
cudaMalloc((void **)&c_GPU, size_C * sizeof(float));
//CPU -> GPU
cudaMemcpy(a_GPU,A,size_A * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(b_GPU,B,size_B * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(c_GPU,C,size_C * sizeof(float),cudaMemcpyHostToDevice);
//GPU Grid and Block ini
//Define BlockSize
dim3 dimBlock(16,16);
//Define grid size
//What happend if C's matrix size it's a prime number?
int grid_x_size = ceil((float)wB / 16);
int grid_y_size = ceil((float)hA / 16);
printf("grid_x_size = %i, grid_y_size = %i\n",grid_x_size, grid_y_size);
dim3 dimGrid(grid_x_size, grid_y_size);
//Start GPU timer
t0 = wtime();
//Invoque kernel
matrixMultGPU<<<dimGrid,dimBlock>>>(a_GPU, b_GPU, c_GPU, wA, hA, wB);
//Wait for the kernel
cudaThreadSynchronize();
//Stop timer and print value
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
//GPU result to host
gpu_c_host = (float *)malloc(size_C * sizeof(float));
cudaMemcpy(gpu_c_host,c_GPU,size_C * sizeof(float),cudaMemcpyDeviceToHost);
if (!diff(A, B, hA, wA, wB, gpu_c_host)){
printf("ERROR=GPU.vs.CPU matrix mult differs\n");
}
else{
printf("GPU.vs.CPU matrix is equal! :D\n");
}
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nGPU C\n");print_matrix(gpu_c_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(gpu_c_host);
/* Free GPU */
cudaFree(a_GPU);
cudaFree(b_GPU);
cudaFree(c_GPU);
return (1);
} | code for sm_80
Function : _Z13matrixMultGPUPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R6, c[0x0][0x178] ; /* 0x00005e0000067a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x002fca00078e0202 */
/*0090*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x17c], P0 ; /* 0x00005f0007007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R8, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306087812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD R2, R7, c[0x0][0x180], R0 ; /* 0x0000600007027a24 */
/* 0x000fe200078e0200 */
/*0120*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fc80000000f00 */
/*0130*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fce00078e0209 */
/*0140*/ @!P0 BRA 0xcb0 ; /* 0x00000b6000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R10, -R8, c[0x0][0x178], RZ ; /* 0x00005e00080a7a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000162000c1e1900 */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R12, R7, c[0x0][0x178], RZ ; /* 0x00005e00070c7a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD.WIDE R14, R0, R9, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x000fe200078e0209 */
/*01b0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fd60000000f00 */
/*01c0*/ @!P0 BRA 0xae0 ; /* 0x0000091000008947 */
/* 0x001fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7a0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x004ea2000c1e1900 */
/*0230*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R4, R12, 0x4, R4 ; /* 0x000000040c047825 */
/* 0x000fca00078e0204 */
/*0250*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea4000c1e1900 */
/*0260*/ FFMA R13, R16, R17, R13 ; /* 0x00000011100d7223 */
/* 0x024fe4000000000d */
/*0270*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc600078e020e */
/*0280*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ FFMA R21, R18, R19, R13 ; /* 0x0000001312157223 */
/* 0x004fc4000000000d */
/*02c0*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*02d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*0310*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*0320*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R13, [R4.64+0xc] ; /* 0x00000c04040d7981 */
/* 0x001ee2000c1e1900 */
/*0350*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0360*/ FFMA R13, R20, R13, R23 ; /* 0x0000000d140d7223 */
/* 0x008fca0000000017 */
/*0370*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000e64000c1e1900 */
/*03a0*/ FFMA R21, R20, R18, R13 ; /* 0x0000001214157223 */
/* 0x002fc4000000000d */
/*03b0*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*03c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*0400*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*0410*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0430*/ LDG.E R13, [R4.64+0x18] ; /* 0x00001804040d7981 */
/* 0x001ee2000c1e1900 */
/*0440*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0450*/ FFMA R13, R20, R13, R23 ; /* 0x0000000d140d7223 */
/* 0x008fca0000000017 */
/*0460*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0470*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0480*/ LDG.E R18, [R4.64+0x1c] ; /* 0x00001c0404127981 */
/* 0x000e64000c1e1900 */
/*0490*/ FFMA R21, R20, R18, R13 ; /* 0x0000001214157223 */
/* 0x002fc4000000000d */
/*04a0*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*04b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*04f0*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*0500*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0510*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0520*/ LDG.E R13, [R4.64+0x24] ; /* 0x00002404040d7981 */
/* 0x001ee2000c1e1900 */
/*0530*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0540*/ FFMA R13, R20, R13, R23 ; /* 0x0000000d140d7223 */
/* 0x008fca0000000017 */
/*0550*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0560*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0570*/ LDG.E R18, [R4.64+0x28] ; /* 0x0000280404127981 */
/* 0x000e64000c1e1900 */
/*0580*/ FFMA R21, R20, R18, R13 ; /* 0x0000001214157223 */
/* 0x002fc4000000000d */
/*0590*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*05a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*05b0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*05c0*/ LDG.E R14, [R4.64+0x2c] ; /* 0x00002c04040e7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*05e0*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*05f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0600*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R13, [R4.64+0x30] ; /* 0x00003004040d7981 */
/* 0x001ea2000c1e1900 */
/*0620*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0630*/ FFMA R13, R20, R13, R23 ; /* 0x0000000d140d7223 */
/* 0x004fca0000000017 */
/*0640*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0650*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R18, [R4.64+0x34] ; /* 0x0000340404127981 */
/* 0x000ea4000c1e1900 */
/*0670*/ FFMA R25, R20, R18, R13 ; /* 0x0000001214197223 */
/* 0x004fc4000000000d */
/*0680*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*0690*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*06a0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e68000c1e1900 */
/*06b0*/ LDG.E R14, [R4.64+0x38] ; /* 0x00003804040e7981 */
/* 0x000e62000c1e1900 */
/*06c0*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ FFMA R23, R20, R14, R25 ; /* 0x0000000e14177223 */
/* 0x002fc40000000019 */
/*06e0*/ IMAD.WIDE R20, R6, 0x4, R18 ; /* 0x0000000406147825 */
/* 0x000fc600078e0212 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0700*/ LDG.E R13, [R4.64+0x3c] ; /* 0x00003c04040d7981 */
/* 0x001ee8000c1e1900 */
/*0710*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ee2000c1e1900 */
/*0720*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe20003f24270 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0740*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fc60007ffe0ff */
/*0750*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0760*/ FFMA R13, R14, R13, R23 ; /* 0x0000000d0e0d7223 */
/* 0x008fe40000000017 */
/*0770*/ IMAD.WIDE R14, R6, 0x4, R20 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0214 */
/*0780*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e4000c101904 */
/*0790*/ @P1 BRA 0x210 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xac0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*07d0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*07f0*/ IMAD.WIDE R4, R12, 0x4, R4 ; /* 0x000000040c047825 */
/* 0x000fca00078e0204 */
/*0800*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ee4000c1e1900 */
/*0810*/ FFMA R13, R16, R17, R13 ; /* 0x00000011100d7223 */
/* 0x02cfe4000000000d */
/*0820*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc600078e020e */
/*0830*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000ea4000c1e1900 */
/*0860*/ FFMA R21, R18, R19, R13 ; /* 0x0000001312157223 */
/* 0x004fc4000000000d */
/*0870*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*0880*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0890*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea4000c1e1900 */
/*08b0*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*08c0*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*08d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*08e0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*08f0*/ LDG.E R13, [R4.64+0xc] ; /* 0x00000c04040d7981 */
/* 0x001ee2000c1e1900 */
/*0900*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0910*/ FFMA R13, R20, R13, R23 ; /* 0x0000000d140d7223 */
/* 0x008fca0000000017 */
/*0920*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0930*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0940*/ LDG.E R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000e64000c1e1900 */
/*0950*/ FFMA R21, R20, R18, R13 ; /* 0x0000001214157223 */
/* 0x002fc4000000000d */
/*0960*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*0970*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0980*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0990*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*09b0*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*09c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09d0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R13, [R4.64+0x18] ; /* 0x00001804040d7981 */
/* 0x001ea2000c1e1900 */
/*09f0*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0a00*/ FFMA R25, R20, R13, R23 ; /* 0x0000000d14197223 */
/* 0x004fca0000000017 */
/*0a10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a60*/ IMAD.WIDE R14, R6, 0x4, R16 ; /* 0x00000004060e7825 */
/* 0x000fe200078e0210 */
/*0a70*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fc40007ffe0ff */
/*0a80*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R13, R18, R13, R25 ; /* 0x0000000d120d7223 */
/* 0x004fca0000000019 */
/*0ab0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*0ac0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xcb0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0af0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee2000c1e1900 */
/*0b00*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*0b10*/ IMAD.WIDE R4, R12, 0x4, R4 ; /* 0x000000040c047825 */
/* 0x000fca00078e0204 */
/*0b20*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ FFMA R13, R16, R17, R13 ; /* 0x00000011100d7223 */
/* 0x02efe4000000000d */
/*0b40*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc600078e020e */
/*0b50*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ FFMA R23, R18, R19, R13 ; /* 0x0000001312177223 */
/* 0x004fc4000000000d */
/*0b90*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*0ba0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0bb0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ FFMA R25, R20, R14, R23 ; /* 0x0000000e14197223 */
/* 0x004fc40000000017 */
/*0bf0*/ IMAD.WIDE R20, R6, 0x4, R18 ; /* 0x0000000406147825 */
/* 0x000fc600078e0212 */
/*0c00*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0c10*/ LDG.E R13, [R4.64+0xc] ; /* 0x00000c04040d7981 */
/* 0x001ea8000c1e1900 */
/*0c20*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ea2000c1e1900 */
/*0c30*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0c40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c50*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0c70*/ FFMA R13, R14, R13, R25 ; /* 0x0000000d0e0d7223 */
/* 0x004fe40000000019 */
/*0c80*/ IMAD.WIDE R14, R6, 0x4, R20 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0214 */
/*0c90*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e4000c101904 */
/*0ca0*/ @P0 BRA 0xae0 ; /* 0xfffffe3000000947 */
/* 0x002fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cd0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x026162000c1e1900 */
/*0ce0*/ IMAD R4, R7, c[0x0][0x178], R11 ; /* 0x00005e0007047a24 */
/* 0x000fe400078e020b */
/*0cf0*/ IMAD R0, R11, c[0x0][0x178], R0 ; /* 0x00005e000b007a24 */
/* 0x000fe400078e0200 */
/*0d00*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0209 */
/*0d10*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fe40000000f00 */
/*0d20*/ MOV R11, R5 ; /* 0x00000005000b7202 */
/* 0x000fe20000000f00 */
/*0d30*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x001fca00078e0209 */
/*0d40*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0010a8000c1e1900 */
/*0d50*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x0002a2000c1e1900 */
/*0d60*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*0d70*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0d80*/ IMAD.WIDE R4, R6, 0x4, R4 ; /* 0x0000000406047825 */
/* 0x001fe200078e0204 */
/*0d90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x002fc80007f3e0ff */
/*0da0*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0db0*/ FFMA R13, R0, R7, R13 ; /* 0x00000007000d7223 */
/* 0x024fca000000000d */
/*0dc0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*0dd0*/ @P0 BRA 0xd40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0de0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0df0*/ BRA 0xdf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <cuda.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void matrixMulCPU(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C[i*wB+j] = 0.0;
for (k=0; k<wA; k++)
C[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
__global__ void matrixMultGPU(float* a, float* b, float* c, int nColsA,
int nRowsC, int nColsC){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < nRowsC && col < nColsC){
for(int i = 0; i < nColsA; ++i){
//In b[], nColsA = nRowsB
c[row * nColsC + col] += a[row * nColsA + i] * b[i * nColsA + col];
}
}
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*1.0f;
else
M[i*wM+j] = -1.0f/(float)(wM);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int diff(float *A, float *B, int hA, int wA, int wB, float *C_gpu)
{
float *C_cpu;
int size_C = wB * hA;
C_cpu = (float*)malloc(size_C*sizeof(float));
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C_cpu[i*wB+j] = 0.0;
for (k=0; k<wA; k++){
C_cpu[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
//printf("\n\nMATRIX C_cpu\n");print_matrix(C_cpu, hA, wB);
for (i=0; i<hA; i++)
for (j=0; j<wB; j++)
if (fabsf(C_cpu[i*wB+j]-C_gpu[i*wB+j])>1e-5)
{
printf("[%i,%i]: %f!=%f\n", i, j, C_cpu[i*wB+j], C_gpu[i*wB+j]);
return(0);
}
return(1);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C;
float *a_GPU, *b_GPU, *c_GPU, *gpu_c_host;
int hA, wA, hB, wB;
double t0, t1;
int i;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
//init matrix sizes
int size_A = wA * hA;
int size_B = wB * hB;
int size_C = wB * hA;
// CPU Init A and B, malloc C
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA, 1.0);
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB, 2.0);
C = (float*)malloc(size_B*sizeof(float));
for (i = 0; i < (hA*wB); i++) {
C[i] = 0.0;
}
//GPU malloc A,B and C
cudaMalloc((void **)&a_GPU, size_A * sizeof(float));
cudaMalloc((void **)&b_GPU, size_B * sizeof(float));
cudaMalloc((void **)&c_GPU, size_C * sizeof(float));
//CPU -> GPU
cudaMemcpy(a_GPU,A,size_A * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(b_GPU,B,size_B * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(c_GPU,C,size_C * sizeof(float),cudaMemcpyHostToDevice);
//GPU Grid and Block ini
//Define BlockSize
dim3 dimBlock(16,16);
//Define grid size
//What happend if C's matrix size it's a prime number?
int grid_x_size = ceil((float)wB / 16);
int grid_y_size = ceil((float)hA / 16);
printf("grid_x_size = %i, grid_y_size = %i\n",grid_x_size, grid_y_size);
dim3 dimGrid(grid_x_size, grid_y_size);
//Start GPU timer
t0 = wtime();
//Invoque kernel
matrixMultGPU<<<dimGrid,dimBlock>>>(a_GPU, b_GPU, c_GPU, wA, hA, wB);
//Wait for the kernel
cudaThreadSynchronize();
//Stop timer and print value
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
//GPU result to host
gpu_c_host = (float *)malloc(size_C * sizeof(float));
cudaMemcpy(gpu_c_host,c_GPU,size_C * sizeof(float),cudaMemcpyDeviceToHost);
if (!diff(A, B, hA, wA, wB, gpu_c_host)){
printf("ERROR=GPU.vs.CPU matrix mult differs\n");
}
else{
printf("GPU.vs.CPU matrix is equal! :D\n");
}
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nGPU C\n");print_matrix(gpu_c_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(gpu_c_host);
/* Free GPU */
cudaFree(a_GPU);
cudaFree(b_GPU);
cudaFree(c_GPU);
return (1);
} | .file "tmpxft_00142082_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq _ZZ5wtimevE3tv0(%rip), %rdi
call gettimeofday@PLT
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax
addq 8+_ZZ5wtimevE3tv0(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5wtimev, .-_Z5wtimev
.globl _Z12matrixMulCPUPfS_iiiS_
.type _Z12matrixMulCPUPfS_iiiS_, @function
_Z12matrixMulCPUPfS_iiiS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -8(%rsp)
movl %edx, -12(%rsp)
testl %edx, %edx
jle .L5
movq %rdi, %rbx
movl %ecx, %ebp
movl %r8d, %r11d
movslq %r8d, %rdi
salq $2, %rdi
movl $0, %r13d
movl $0, %ecx
movl $0, %edx
movslq %ebp, %r14
movq %r9, %r8
movq %r14, %rsi
jmp .L7
.L11:
movslq %ecx, %rax
leaq (%r8,%rax,4), %r10
movq -8(%rsp), %r14
movslq %r13d, %rax
leaq (%rbx,%rax,4), %r15
addq %rsi, %rax
leaq (%rbx,%rax,4), %r9
movl $0, %r12d
movl %edx, -20(%rsp)
movl %ecx, -16(%rsp)
.L10:
movq %r10, %rcx
movl $0x00000000, (%r10)
testl %ebp, %ebp
jle .L8
movq %r14, %rdx
movq %r15, %rax
.L9:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L9
.L8:
addl $1, %r12d
addq $4, %r10
addq $4, %r14
cmpl %r12d, %r11d
jne .L10
movl -20(%rsp), %edx
movl -16(%rsp), %ecx
.L12:
addl $1, %edx
addl %r11d, %ecx
addl %ebp, %r13d
cmpl %edx, -12(%rsp)
je .L5
.L7:
testl %r11d, %r11d
jg .L11
jmp .L12
.L5:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12matrixMulCPUPfS_iiiS_, .-_Z12matrixMulCPUPfS_iiiS_
.globl _Z11init_matrixPfiif
.type _Z11init_matrixPfiif, @function
_Z11init_matrixPfiif:
.LFB2059:
.cfi_startproc
endbr64
movq %rdi, %r9
testl %esi, %esi
jle .L16
movl $0, %r8d
movl $0, %edi
movss .LC2(%rip), %xmm3
jmp .L18
.L26:
leal (%rax,%r8), %ecx
movslq %ecx, %rcx
movss %xmm0, (%r9,%rcx,4)
.L20:
addl $1, %eax
cmpl %eax, %edx
je .L22
.L21:
cmpl %eax, %edi
je .L26
leal (%rax,%r8), %ecx
movslq %ecx, %rcx
pxor %xmm2, %xmm2
cvtsi2ssl %edx, %xmm2
movaps %xmm3, %xmm1
divss %xmm2, %xmm1
movss %xmm1, (%r9,%rcx,4)
jmp .L20
.L22:
addl $1, %edi
addl %edx, %r8d
cmpl %edi, %esi
je .L16
.L18:
movl $0, %eax
testl %edx, %edx
jg .L21
jmp .L22
.L16:
ret
.cfi_endproc
.LFE2059:
.size _Z11init_matrixPfiif, .-_Z11init_matrixPfiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%4.1f "
.LC4:
.string "\n"
.text
.globl _Z12print_matrixPfii
.type _Z12print_matrixPfii, @function
_Z12print_matrixPfii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L27
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r12
jmp .L29
.L31:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L30:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L30
.L32:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L27
.L29:
testl %r15d, %r15d
jg .L31
jmp .L32
.L27:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12print_matrixPfii, .-_Z12print_matrixPfii
.section .rodata.str1.1
.LC7:
.string "[%i,%i]: %f!=%f\n"
.text
.globl _Z4diffPfS_iiiS_
.type _Z4diffPfS_iiiS_, @function
_Z4diffPfS_iiiS_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, 16(%rsp)
movl %edx, %r15d
movl %ecx, %ebp
movl %r8d, %ebx
movq %r9, 32(%rsp)
movl %r8d, %edi
imull %edx, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
testl %r15d, %r15d
jle .L49
movq %rax, %r14
movslq %ebx, %rcx
leaq 0(,%rcx,4), %rsi
movl $0, %edx
movl $0, %eax
movl $0, %r13d
movslq %ebp, %rdi
movq %rdi, 24(%rsp)
movq %r14, 8(%rsp)
movl %r13d, 4(%rsp)
movq %rcx, 40(%rsp)
movl %r15d, %edi
jmp .L37
.L42:
movslq %eax, %r8
movq 8(%rsp), %rcx
leaq (%rcx,%r8,4), %r9
movq 16(%rsp), %r11
movslq %edx, %r8
leaq (%r12,%r8,4), %r15
movq 24(%rsp), %rcx
addq %rcx, %r8
leaq (%r12,%r8,4), %r8
movl $0, %r10d
.L40:
movq %r9, %r14
movl $0x00000000, (%r9)
testl %ebp, %ebp
jle .L38
movq %r11, %r13
movq %r15, %rcx
pxor %xmm1, %xmm1
.L39:
movss (%rcx), %xmm0
mulss 0(%r13), %xmm0
addss %xmm0, %xmm1
addq $4, %rcx
addq %rsi, %r13
cmpq %r8, %rcx
jne .L39
movss %xmm1, (%r14)
.L38:
addl $1, %r10d
addq $4, %r9
addq $4, %r11
cmpl %r10d, %ebx
jne .L40
.L43:
movl 4(%rsp), %ecx
leal 1(%rcx), %r8d
addl %ebx, %eax
addl %ebp, %edx
cmpl %r8d, %edi
je .L50
movl %r8d, 4(%rsp)
.L37:
testl %ebx, %ebx
jg .L42
jmp .L43
.L58:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %eax, %ecx
movl %esi, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
.L35:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
leal 1(%rsi), %eax
addl %ebx, %edi
cmpl %esi, %r13d
je .L51
movl %eax, %esi
.L41:
testl %ebx, %ebx
jle .L48
movslq %edi, %rdx
salq $2, %rdx
leaq (%r14,%rdx), %r9
addq %r8, %rdx
movl $0, %eax
.L46:
movss (%r9,%rax,4), %xmm0
movss (%rdx,%rax,4), %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps %xmm4, %xmm2
cvtss2sd %xmm2, %xmm2
comisd %xmm3, %xmm2
ja .L58
addq $1, %rax
cmpq %rcx, %rax
jne .L46
jmp .L48
.L50:
movq 8(%rsp), %r14
movl 4(%rsp), %r13d
movq 40(%rsp), %rcx
movl $0, %edi
movl $0, %esi
movss .LC5(%rip), %xmm4
movsd .LC6(%rip), %xmm3
movq 32(%rsp), %r8
jmp .L41
.L49:
movl $1, %eax
jmp .L35
.L51:
movl $1, %eax
jmp .L35
.cfi_endproc
.LFE2061:
.size _Z4diffPfS_iiiS_, .-_Z4diffPfS_iiiS_
.globl _Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii
.type _Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii, @function
_Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13matrixMultGPUPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii, .-_Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii
.globl _Z13matrixMultGPUPfS_S_iii
.type _Z13matrixMultGPUPfS_S_iii, @function
_Z13matrixMultGPUPfS_S_iii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z13matrixMultGPUPfS_S_iii, .-_Z13matrixMultGPUPfS_S_iii
.section .rodata.str1.1
.LC8:
.string "./exec hA hB/WA wB\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC13:
.string "grid_x_size = %i, grid_y_size = %i\n"
.section .rodata.str1.1
.LC14:
.string "Time GPU=%f\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "ERROR=GPU.vs.CPU matrix mult differs\n"
.align 8
.LC16:
.string "GPU.vs.CPU matrix is equal! :D\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %esi
movq stdout(%rip), %rdi
call setbuf@PLT
cmpl $4, %ebx
jne .L79
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 20(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 16(%rsp)
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 24(%rsp)
movl %ebx, %r12d
imull %eax, %r12d
movl %r14d, %ebp
imull %eax, %ebp
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movss .LC9(%rip), %xmm0
movl 16(%rsp), %edx
movl 20(%rsp), %esi
movq %rax, %rdi
call _Z11init_matrixPfiif
movslq %r12d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movss .LC10(%rip), %xmm0
movl 24(%rsp), %edx
movl 16(%rsp), %esi
movq %rax, %rdi
call _Z11init_matrixPfiif
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
testl %ebp, %ebp
jle .L69
movslq %ebp, %rdx
leaq (%rax,%rdx,4), %rdx
.L70:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L70
.L69:
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq %ebp, %rbp
salq $2, %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 64(%rsp)
movl $16, 68(%rsp)
movl $1, 72(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC11(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC17(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC12(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L71
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L71:
cvttss2sil %xmm3, %r12d
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC11(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC17(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC12(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L72
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L72:
cvttss2sil %xmm3, %ebx
movl %ebx, %ecx
movl %r12d, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, 76(%rsp)
movl %ebx, 80(%rsp)
movl $1, 84(%rsp)
call _Z5wtimev
movsd %xmm0, 24(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L73:
call cudaThreadSynchronize@PLT
call _Z5wtimev
subsd 24(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %r9
movl %r13d, %r8d
movl 16(%rsp), %ecx
movl 20(%rsp), %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call _Z4diffPfS_iiiS_
testl %eax, %eax
jne .L74
leaq .LC15(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L75:
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L81
movl $1, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L80:
movl %r13d, %r9d
movl %r14d, %r8d
movl 16(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii
jmp .L73
.L74:
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L75
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z13matrixMultGPUPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matrixMultGPUPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ5wtimevE3tv0
.comm _ZZ5wtimevE3tv0,16,16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long -1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC5:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC6:
.long -1998362383
.long 1055193269
.section .rodata.cst4
.align 4
.LC9:
.long 1065353216
.align 4
.LC10:
.long 1073741824
.align 4
.LC11:
.long 1031798784
.align 4
.LC12:
.long 1258291200
.set .LC17,.LC5
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <cuda.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void matrixMulCPU(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C[i*wB+j] = 0.0;
for (k=0; k<wA; k++)
C[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
__global__ void matrixMultGPU(float* a, float* b, float* c, int nColsA,
int nRowsC, int nColsC){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < nRowsC && col < nColsC){
for(int i = 0; i < nColsA; ++i){
//In b[], nColsA = nRowsB
c[row * nColsC + col] += a[row * nColsA + i] * b[i * nColsA + col];
}
}
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*1.0f;
else
M[i*wM+j] = -1.0f/(float)(wM);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int diff(float *A, float *B, int hA, int wA, int wB, float *C_gpu)
{
float *C_cpu;
int size_C = wB * hA;
C_cpu = (float*)malloc(size_C*sizeof(float));
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C_cpu[i*wB+j] = 0.0;
for (k=0; k<wA; k++){
C_cpu[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
//printf("\n\nMATRIX C_cpu\n");print_matrix(C_cpu, hA, wB);
for (i=0; i<hA; i++)
for (j=0; j<wB; j++)
if (fabsf(C_cpu[i*wB+j]-C_gpu[i*wB+j])>1e-5)
{
printf("[%i,%i]: %f!=%f\n", i, j, C_cpu[i*wB+j], C_gpu[i*wB+j]);
return(0);
}
return(1);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C;
float *a_GPU, *b_GPU, *c_GPU, *gpu_c_host;
int hA, wA, hB, wB;
double t0, t1;
int i;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
//init matrix sizes
int size_A = wA * hA;
int size_B = wB * hB;
int size_C = wB * hA;
// CPU Init A and B, malloc C
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA, 1.0);
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB, 2.0);
C = (float*)malloc(size_B*sizeof(float));
for (i = 0; i < (hA*wB); i++) {
C[i] = 0.0;
}
//GPU malloc A,B and C
cudaMalloc((void **)&a_GPU, size_A * sizeof(float));
cudaMalloc((void **)&b_GPU, size_B * sizeof(float));
cudaMalloc((void **)&c_GPU, size_C * sizeof(float));
//CPU -> GPU
cudaMemcpy(a_GPU,A,size_A * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(b_GPU,B,size_B * sizeof(float),cudaMemcpyHostToDevice);
cudaMemcpy(c_GPU,C,size_C * sizeof(float),cudaMemcpyHostToDevice);
//GPU Grid and Block ini
//Define BlockSize
dim3 dimBlock(16,16);
//Define grid size
//What happend if C's matrix size it's a prime number?
int grid_x_size = ceil((float)wB / 16);
int grid_y_size = ceil((float)hA / 16);
printf("grid_x_size = %i, grid_y_size = %i\n",grid_x_size, grid_y_size);
dim3 dimGrid(grid_x_size, grid_y_size);
//Start GPU timer
t0 = wtime();
//Invoque kernel
matrixMultGPU<<<dimGrid,dimBlock>>>(a_GPU, b_GPU, c_GPU, wA, hA, wB);
//Wait for the kernel
cudaThreadSynchronize();
//Stop timer and print value
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
//GPU result to host
gpu_c_host = (float *)malloc(size_C * sizeof(float));
cudaMemcpy(gpu_c_host,c_GPU,size_C * sizeof(float),cudaMemcpyDeviceToHost);
if (!diff(A, B, hA, wA, wB, gpu_c_host)){
printf("ERROR=GPU.vs.CPU matrix mult differs\n");
}
else{
printf("GPU.vs.CPU matrix is equal! :D\n");
}
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nGPU C\n");print_matrix(gpu_c_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(gpu_c_host);
/* Free GPU */
cudaFree(a_GPU);
cudaFree(b_GPU);
cudaFree(c_GPU);
return (1);
} | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void matrixMulCPU(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C[i*wB+j] = 0.0;
for (k=0; k<wA; k++)
C[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
__global__ void matrixMultGPU(float* a, float* b, float* c, int nColsA,
int nRowsC, int nColsC){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < nRowsC && col < nColsC){
for(int i = 0; i < nColsA; ++i){
//In b[], nColsA = nRowsB
c[row * nColsC + col] += a[row * nColsA + i] * b[i * nColsA + col];
}
}
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*1.0f;
else
M[i*wM+j] = -1.0f/(float)(wM);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int diff(float *A, float *B, int hA, int wA, int wB, float *C_gpu)
{
float *C_cpu;
int size_C = wB * hA;
C_cpu = (float*)malloc(size_C*sizeof(float));
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C_cpu[i*wB+j] = 0.0;
for (k=0; k<wA; k++){
C_cpu[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
//printf("\n\nMATRIX C_cpu\n");print_matrix(C_cpu, hA, wB);
for (i=0; i<hA; i++)
for (j=0; j<wB; j++)
if (fabsf(C_cpu[i*wB+j]-C_gpu[i*wB+j])>1e-5)
{
printf("[%i,%i]: %f!=%f\n", i, j, C_cpu[i*wB+j], C_gpu[i*wB+j]);
return(0);
}
return(1);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C;
float *a_GPU, *b_GPU, *c_GPU, *gpu_c_host;
int hA, wA, hB, wB;
double t0, t1;
int i;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
//init matrix sizes
int size_A = wA * hA;
int size_B = wB * hB;
int size_C = wB * hA;
// CPU Init A and B, malloc C
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA, 1.0);
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB, 2.0);
C = (float*)malloc(size_B*sizeof(float));
for (i = 0; i < (hA*wB); i++) {
C[i] = 0.0;
}
//GPU malloc A,B and C
hipMalloc((void **)&a_GPU, size_A * sizeof(float));
hipMalloc((void **)&b_GPU, size_B * sizeof(float));
hipMalloc((void **)&c_GPU, size_C * sizeof(float));
//CPU -> GPU
hipMemcpy(a_GPU,A,size_A * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(b_GPU,B,size_B * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(c_GPU,C,size_C * sizeof(float),hipMemcpyHostToDevice);
//GPU Grid and Block ini
//Define BlockSize
dim3 dimBlock(16,16);
//Define grid size
//What happend if C's matrix size it's a prime number?
int grid_x_size = ceil((float)wB / 16);
int grid_y_size = ceil((float)hA / 16);
printf("grid_x_size = %i, grid_y_size = %i\n",grid_x_size, grid_y_size);
dim3 dimGrid(grid_x_size, grid_y_size);
//Start GPU timer
t0 = wtime();
//Invoque kernel
matrixMultGPU<<<dimGrid,dimBlock>>>(a_GPU, b_GPU, c_GPU, wA, hA, wB);
//Wait for the kernel
hipDeviceSynchronize();
//Stop timer and print value
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
//GPU result to host
gpu_c_host = (float *)malloc(size_C * sizeof(float));
hipMemcpy(gpu_c_host,c_GPU,size_C * sizeof(float),hipMemcpyDeviceToHost);
if (!diff(A, B, hA, wA, wB, gpu_c_host)){
printf("ERROR=GPU.vs.CPU matrix mult differs\n");
}
else{
printf("GPU.vs.CPU matrix is equal! :D\n");
}
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nGPU C\n");print_matrix(gpu_c_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(gpu_c_host);
/* Free GPU */
hipFree(a_GPU);
hipFree(b_GPU);
hipFree(c_GPU);
return (1);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD device assembly. | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void matrixMulCPU(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C[i*wB+j] = 0.0;
for (k=0; k<wA; k++)
C[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
__global__ void matrixMultGPU(float* a, float* b, float* c, int nColsA,
int nRowsC, int nColsC){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < nRowsC && col < nColsC){
for(int i = 0; i < nColsA; ++i){
//In b[], nColsA = nRowsB
c[row * nColsC + col] += a[row * nColsA + i] * b[i * nColsA + col];
}
}
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*1.0f;
else
M[i*wM+j] = -1.0f/(float)(wM);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int diff(float *A, float *B, int hA, int wA, int wB, float *C_gpu)
{
float *C_cpu;
int size_C = wB * hA;
C_cpu = (float*)malloc(size_C*sizeof(float));
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C_cpu[i*wB+j] = 0.0;
for (k=0; k<wA; k++){
C_cpu[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
//printf("\n\nMATRIX C_cpu\n");print_matrix(C_cpu, hA, wB);
for (i=0; i<hA; i++)
for (j=0; j<wB; j++)
if (fabsf(C_cpu[i*wB+j]-C_gpu[i*wB+j])>1e-5)
{
printf("[%i,%i]: %f!=%f\n", i, j, C_cpu[i*wB+j], C_gpu[i*wB+j]);
return(0);
}
return(1);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C;
float *a_GPU, *b_GPU, *c_GPU, *gpu_c_host;
int hA, wA, hB, wB;
double t0, t1;
int i;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
//init matrix sizes
int size_A = wA * hA;
int size_B = wB * hB;
int size_C = wB * hA;
// CPU Init A and B, malloc C
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA, 1.0);
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB, 2.0);
C = (float*)malloc(size_B*sizeof(float));
for (i = 0; i < (hA*wB); i++) {
C[i] = 0.0;
}
//GPU malloc A,B and C
hipMalloc((void **)&a_GPU, size_A * sizeof(float));
hipMalloc((void **)&b_GPU, size_B * sizeof(float));
hipMalloc((void **)&c_GPU, size_C * sizeof(float));
//CPU -> GPU
hipMemcpy(a_GPU,A,size_A * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(b_GPU,B,size_B * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(c_GPU,C,size_C * sizeof(float),hipMemcpyHostToDevice);
//GPU Grid and Block ini
//Define BlockSize
dim3 dimBlock(16,16);
//Define grid size
//What happend if C's matrix size it's a prime number?
int grid_x_size = ceil((float)wB / 16);
int grid_y_size = ceil((float)hA / 16);
printf("grid_x_size = %i, grid_y_size = %i\n",grid_x_size, grid_y_size);
dim3 dimGrid(grid_x_size, grid_y_size);
//Start GPU timer
t0 = wtime();
//Invoque kernel
matrixMultGPU<<<dimGrid,dimBlock>>>(a_GPU, b_GPU, c_GPU, wA, hA, wB);
//Wait for the kernel
hipDeviceSynchronize();
//Stop timer and print value
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
//GPU result to host
gpu_c_host = (float *)malloc(size_C * sizeof(float));
hipMemcpy(gpu_c_host,c_GPU,size_C * sizeof(float),hipMemcpyDeviceToHost);
if (!diff(A, B, hA, wA, wB, gpu_c_host)){
printf("ERROR=GPU.vs.CPU matrix mult differs\n");
}
else{
printf("GPU.vs.CPU matrix is equal! :D\n");
}
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nGPU C\n");print_matrix(gpu_c_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(gpu_c_host);
/* Free GPU */
hipFree(a_GPU);
hipFree(b_GPU);
hipFree(c_GPU);
return (1);
} | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13matrixMultGPUPfS_S_iii
.globl _Z13matrixMultGPUPfS_S_iii
.p2align 8
.type _Z13matrixMultGPUPfS_S_iii,@function
_Z13matrixMultGPUPfS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s15, s6, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_cmp_gt_i32_e32 vcc_lo, s5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v0
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s4, 0
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s5
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v4, s3, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v4, v4, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v6, v[2:3], off
s_mov_b32 s0, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v1, v7
global_store_b32 v[2:3], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13matrixMultGPUPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13matrixMultGPUPfS_S_iii, .Lfunc_end0-_Z13matrixMultGPUPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13matrixMultGPUPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13matrixMultGPUPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | #include <stdio.h>
#include <malloc.h>
#include <stdlib.h>
#include <math.h>
#include <sys/time.h>
#include <hip/hip_runtime.h>
double wtime(void)
{
static struct timeval tv0;
double time_;
gettimeofday(&tv0,(struct timezone*)0);
time_=(double)((tv0.tv_usec + (tv0.tv_sec)*1000000));
return( time_/1000000);
}
void matrixMulCPU(float *A, float *B, int hA, int wA, int wB, float *C)
{
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C[i*wB+j] = 0.0;
for (k=0; k<wA; k++)
C[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
__global__ void matrixMultGPU(float* a, float* b, float* c, int nColsA,
int nRowsC, int nColsC){
int row = blockIdx.y * blockDim.y + threadIdx.y;
int col = blockIdx.x * blockDim.x + threadIdx.x;
if(row < nRowsC && col < nColsC){
for(int i = 0; i < nColsA; ++i){
//In b[], nColsA = nRowsB
c[row * nColsC + col] += a[row * nColsA + i] * b[i * nColsA + col];
}
}
}
void init_matrix(float *M, int hM, int wM, float k)
{
int i,j;
for (i=0; i<hM; i++)
for (j=0; j<wM; j++)
if (i==j)
M[i*wM+j] = k*1.0f;
else
M[i*wM+j] = -1.0f/(float)(wM);
}
void print_matrix(float *M, int hM, int wM)
{
int i,j;
for (i=0; i<hM; i++){
// printf("Line %i: ", i);
for (j=0; j<wM; j++)
printf("%4.1f ", M[i*wM+j]);
printf("\n");
}
}
int diff(float *A, float *B, int hA, int wA, int wB, float *C_gpu)
{
float *C_cpu;
int size_C = wB * hA;
C_cpu = (float*)malloc(size_C*sizeof(float));
int i,j,k;
for (i=0; i<hA; i++)
for (j=0; j<wB; j++){
C_cpu[i*wB+j] = 0.0;
for (k=0; k<wA; k++){
C_cpu[i*wB+j] += A[i*wA+k]*B[k*wB+j];
}
}
//printf("\n\nMATRIX C_cpu\n");print_matrix(C_cpu, hA, wB);
for (i=0; i<hA; i++)
for (j=0; j<wB; j++)
if (fabsf(C_cpu[i*wB+j]-C_gpu[i*wB+j])>1e-5)
{
printf("[%i,%i]: %f!=%f\n", i, j, C_cpu[i*wB+j], C_gpu[i*wB+j]);
return(0);
}
return(1);
}
////////////////////////////////////////////////////////////////////////////////
// Program main
////////////////////////////////////////////////////////////////////////////////
int main(int argc, char** argv)
{
// Matrix variables
float *A, *B, *C;
float *a_GPU, *b_GPU, *c_GPU, *gpu_c_host;
int hA, wA, hB, wB;
double t0, t1;
int i;
setbuf(stdout, NULL);
if (argc!=4){
printf("./exec hA hB/WA wB\n");
exit(-1);
}
hA = atoi(argv[1]);
hB = wA = atoi(argv[2]);
wB = atoi(argv[3]);
//init matrix sizes
int size_A = wA * hA;
int size_B = wB * hB;
int size_C = wB * hA;
// CPU Init A and B, malloc C
A = (float*)malloc(size_A*sizeof(float));
init_matrix(A, hA, wA, 1.0);
B = (float*)malloc(size_B*sizeof(float));
init_matrix(B, hB, wB, 2.0);
C = (float*)malloc(size_B*sizeof(float));
for (i = 0; i < (hA*wB); i++) {
C[i] = 0.0;
}
//GPU malloc A,B and C
hipMalloc((void **)&a_GPU, size_A * sizeof(float));
hipMalloc((void **)&b_GPU, size_B * sizeof(float));
hipMalloc((void **)&c_GPU, size_C * sizeof(float));
//CPU -> GPU
hipMemcpy(a_GPU,A,size_A * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(b_GPU,B,size_B * sizeof(float),hipMemcpyHostToDevice);
hipMemcpy(c_GPU,C,size_C * sizeof(float),hipMemcpyHostToDevice);
//GPU Grid and Block ini
//Define BlockSize
dim3 dimBlock(16,16);
//Define grid size
//What happend if C's matrix size it's a prime number?
int grid_x_size = ceil((float)wB / 16);
int grid_y_size = ceil((float)hA / 16);
printf("grid_x_size = %i, grid_y_size = %i\n",grid_x_size, grid_y_size);
dim3 dimGrid(grid_x_size, grid_y_size);
//Start GPU timer
t0 = wtime();
//Invoque kernel
matrixMultGPU<<<dimGrid,dimBlock>>>(a_GPU, b_GPU, c_GPU, wA, hA, wB);
//Wait for the kernel
hipDeviceSynchronize();
//Stop timer and print value
t1 = wtime(); printf("Time GPU=%f\n", t1-t0);
//GPU result to host
gpu_c_host = (float *)malloc(size_C * sizeof(float));
hipMemcpy(gpu_c_host,c_GPU,size_C * sizeof(float),hipMemcpyDeviceToHost);
if (!diff(A, B, hA, wA, wB, gpu_c_host)){
printf("ERROR=GPU.vs.CPU matrix mult differs\n");
}
else{
printf("GPU.vs.CPU matrix is equal! :D\n");
}
// print Matrix
//printf("\n\nMATRIX A\n");print_matrix(A, hA, wA);
//printf("\n\nMATRIX B\n");print_matrix(B, hB, wB);
//printf("\n\nGPU C\n");print_matrix(gpu_c_host, hA, wB);
/* Free CPU */
free(A);
free(B);
free(gpu_c_host);
/* Free GPU */
hipFree(a_GPU);
hipFree(b_GPU);
hipFree(c_GPU);
return (1);
} | .text
.file "main.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5wtimev, .Lfunc_end0-_Z5wtimev
.cfi_endproc
# -- End function
.globl _Z12matrixMulCPUPfS_iiiS_ # -- Begin function _Z12matrixMulCPUPfS_iiiS_
.p2align 4, 0x90
.type _Z12matrixMulCPUPfS_iiiS_,@function
_Z12matrixMulCPUPfS_iiiS_: # @_Z12matrixMulCPUPfS_iiiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB1_9
# %bb.1: # %.preheader.lr.ph
movslq %r8d, %rdi
movl %edx, %edx
movl %edi, %r10d
movl %ecx, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge31
# in Loop: Header=BB1_2 Depth=1
incq %r15
addl %ecx, %r14d
cmpq %rdx, %r15
je .LBB1_9
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
testl %r8d, %r8d
jle .LBB1_8
# %bb.3: # %.lr.ph30
# in Loop: Header=BB1_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %r13
movq -16(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
incq %rax
addq $4, %rsi
cmpq %r10, %rax
je .LBB1_8
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
movl $0, (%r13,%rax,4)
testl %ecx, %ecx
jle .LBB1_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB1_4 Depth=2
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rsi, %rbp
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r13,%rax,4)
incq %r9
addq %rbx, %rbp
cmpq %r9, %r11
jne .LBB1_6
jmp .LBB1_7
.LBB1_9: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12matrixMulCPUPfS_iiiS_, .Lfunc_end1-_Z12matrixMulCPUPfS_iiiS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__matrixMultGPUPfS_S_iii # -- Begin function _Z28__device_stub__matrixMultGPUPfS_S_iii
.p2align 4, 0x90
.type _Z28__device_stub__matrixMultGPUPfS_S_iii,@function
_Z28__device_stub__matrixMultGPUPfS_S_iii: # @_Z28__device_stub__matrixMultGPUPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13matrixMultGPUPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z28__device_stub__matrixMultGPUPfS_S_iii, .Lfunc_end2-_Z28__device_stub__matrixMultGPUPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11init_matrixPfiif
.LCPI3_0:
.long 0xbf800000 # float -1
.text
.globl _Z11init_matrixPfiif
.p2align 4, 0x90
.type _Z11init_matrixPfiif,@function
_Z11init_matrixPfiif: # @_Z11init_matrixPfiif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_8
# %bb.1: # %.preheader.lr.ph
cvtsi2ss %edx, %xmm2
movl %esi, %eax
movl %edx, %ecx
xorl %esi, %esi
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm2, %xmm1
xorl %r8d, %r8d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r8
addl %edx, %esi
cmpq %rax, %r8
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %edx, %edx
jle .LBB3_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %esi, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # %select.end
# in Loop: Header=BB3_4 Depth=2
movss %xmm2, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
je .LBB3_7
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm2
cmpq %r10, %r8
je .LBB3_6
# %bb.5: # %select.false.sink
# in Loop: Header=BB3_4 Depth=2
movaps %xmm1, %xmm2
jmp .LBB3_6
.LBB3_8: # %._crit_edge21
retq
.Lfunc_end3:
.size _Z11init_matrixPfiif, .Lfunc_end3-_Z11init_matrixPfiif
.cfi_endproc
# -- End function
.globl _Z12print_matrixPfii # -- Begin function _Z12print_matrixPfii
.p2align 4, 0x90
.type _Z12print_matrixPfii,@function
_Z12print_matrixPfii: # @_Z12print_matrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
testl %ebx, %ebx
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB4_4
jmp .LBB4_5
.LBB4_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z12print_matrixPfii, .Lfunc_end4-_Z12print_matrixPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z4diffPfS_iiiS_
.LCPI5_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl _Z4diffPfS_iiiS_
.p2align 4, 0x90
.type _Z4diffPfS_iiiS_,@function
_Z4diffPfS_iiiS_: # @_Z4diffPfS_iiiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 16(%rsp) # 8-byte Spill
movl %r8d, %ebp
movl %ecx, %r15d
movl %edx, %ebx
movq %rsi, 32(%rsp) # 8-byte Spill
movq %rdi, 24(%rsp) # 8-byte Spill
movl %r8d, %eax
imull %edx, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movl %ebx, %edi
movl %ebp, %r8d
movl %ebx, 4(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB5_10
# %bb.1: # %.preheader61.lr.ph
movslq %ebp, %rax
movl %r15d, %edx
leaq (,%rax,4), %rsi
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_9: # %._crit_edge69
# in Loop: Header=BB5_2 Depth=1
incq %r10
addl %r15d, %r9d
cmpq %rdi, %r10
je .LBB5_10
.LBB5_2: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
# Child Loop BB5_6 Depth 3
testl %ebp, %ebp
jle .LBB5_9
# %bb.3: # %.lr.ph68
# in Loop: Header=BB5_2 Depth=1
movl %r9d, %ecx
movq 24(%rsp), %r11 # 8-byte Reload
leaq (%r11,%rcx,4), %r11
movq %r10, %rcx
imulq %rax, %rcx
movq 8(%rsp), %rbx # 8-byte Reload
leaq (%rbx,%rcx,4), %rbx
movq 32(%rsp), %r13 # 8-byte Reload
xorl %r14d, %r14d
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_8: # in Loop: Header=BB5_4 Depth=2
incq %r14
addq $4, %r13
cmpq %r8, %r14
je .LBB5_9
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_6 Depth 3
movl $0, (%rbx,%r14,4)
testl %r15d, %r15d
jle .LBB5_8
# %bb.5: # %.lr.ph
# in Loop: Header=BB5_4 Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r13, %r12
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_6: # Parent Loop BB5_2 Depth=1
# Parent Loop BB5_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
incq %rcx
addq %rsi, %r12
cmpq %rcx, %rdx
jne .LBB5_6
# %bb.7: # %._crit_edge
# in Loop: Header=BB5_4 Depth=2
movss %xmm0, (%rbx,%r14,4)
jmp .LBB5_8
.LBB5_10: # %.preheader60
movl $1, %ecx
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB5_18
# %bb.11: # %.preheader.lr.ph
xorl %r9d, %r9d
movaps .LCPI5_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %esi, %esi
movq 16(%rsp), %rbx # 8-byte Reload
jmp .LBB5_12
.p2align 4, 0x90
.LBB5_17: # %._crit_edge73
# in Loop: Header=BB5_12 Depth=1
incq %rsi
addl %ebp, %r9d
cmpq %rdi, %rsi
je .LBB5_18
.LBB5_12: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
testl %ebp, %ebp
jle .LBB5_17
# %bb.13: # %.lr.ph72
# in Loop: Header=BB5_12 Depth=1
movl %r9d, %eax
leaq (%rbx,%rax,4), %r10
movq 8(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r11
xorl %edx, %edx
.p2align 4, 0x90
.LBB5_14: # Parent Loop BB5_12 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r11,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%r10,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB5_15
# %bb.16: # in Loop: Header=BB5_14 Depth=2
incq %rdx
cmpq %rdx, %r8
jne .LBB5_14
jmp .LBB5_17
.LBB5_15:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
movb $2, %al
callq printf
xorl %ecx, %ecx
.LBB5_18: # %.loopexit
movl %ecx, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z4diffPfS_iiiS_, .Lfunc_end5-_Z4diffPfS_iiiS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x3f800000 # float 1
.LCPI6_1:
.long 0xbf800000 # float -1
.LCPI6_2:
.long 0x40000000 # float 2
.LCPI6_3:
.long 0x3d800000 # float 0.0625
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI6_4:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movq stdout(%rip), %rdi
xorl %esi, %esi
callq setbuf
cmpl $4, %ebp
jne .LBB6_22
# %bb.1:
movq 8(%rbx), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $2, %rdi
movq %rdi, %r15
callq malloc
testl %ebp, %ebp
jle .LBB6_9
# %bb.2: # %.preheader.lr.ph.i
cvtsi2ss %r14d, %xmm2
movl %ebp, %r8d
movl %r14d, %ecx
movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI6_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm2, %xmm1
xorl %edx, %edx
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_8: # %._crit_edge.i
# in Loop: Header=BB6_3 Depth=1
incq %rdx
addl %r14d, %r13d
cmpq %r8, %rdx
je .LBB6_9
.LBB6_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
testl %r14d, %r14d
jle .LBB6_8
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB6_3 Depth=1
movl %r13d, %esi
leaq (%rax,%rsi,4), %rsi
xorl %edi, %edi
jmp .LBB6_5
.p2align 4, 0x90
.LBB6_7: # %select.end
# in Loop: Header=BB6_5 Depth=2
movss %xmm2, (%rsi,%rdi,4)
incq %rdi
cmpq %rdi, %rcx
je .LBB6_8
.LBB6_5: # Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm2
cmpq %rdi, %rdx
je .LBB6_7
# %bb.6: # %select.false.sink
# in Loop: Header=BB6_5 Depth=2
movaps %xmm1, %xmm2
jmp .LBB6_7
.LBB6_9: # %_Z11init_matrixPfiif.exit
movq %rax, 64(%rsp) # 8-byte Spill
movl %r12d, %ebx
movq %rbp, 24(%rsp) # 8-byte Spill
imull %ebp, %ebx
movl %r14d, %eax
imull %r12d, %eax
movslq %eax, %rbp
shlq $2, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %r13
cvtsi2ss %r12d, %xmm3
testl %r14d, %r14d
jle .LBB6_17
# %bb.10: # %.preheader.lr.ph.i67
movl %r14d, %eax
movl %r12d, %ecx
xorl %edx, %edx
movss .LCPI6_2(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI6_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm3, %xmm1
xorl %esi, %esi
jmp .LBB6_11
.p2align 4, 0x90
.LBB6_16: # %._crit_edge.i71
# in Loop: Header=BB6_11 Depth=1
incq %rsi
addl %r12d, %edx
cmpq %rax, %rsi
je .LBB6_17
.LBB6_11: # %.preheader.i69
# =>This Loop Header: Depth=1
# Child Loop BB6_13 Depth 2
testl %r12d, %r12d
jle .LBB6_16
# %bb.12: # %.lr.ph.i74
# in Loop: Header=BB6_11 Depth=1
movl %edx, %edi
leaq (,%rdi,4), %rdi
addq %r13, %rdi
xorl %r8d, %r8d
jmp .LBB6_13
.p2align 4, 0x90
.LBB6_15: # %select.end98
# in Loop: Header=BB6_13 Depth=2
movss %xmm2, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
je .LBB6_16
.LBB6_13: # Parent Loop BB6_11 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm2
cmpq %r8, %rsi
je .LBB6_15
# %bb.14: # %select.false.sink99
# in Loop: Header=BB6_13 Depth=2
movaps %xmm1, %xmm2
jmp .LBB6_15
.LBB6_17: # %_Z11init_matrixPfiif.exit79
movss %xmm3, 16(%rsp) # 4-byte Spill
movq %rbp, %rdi
callq malloc
movq %rax, (%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB6_19
# %bb.18: # %.lr.ph.preheader
movl %ebx, %edx
shlq $2, %rdx
movq (%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
callq memset@PLT
.LBB6_19: # %._crit_edge
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movslq %ebx, %rbx
shlq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq (%rsp), %rsi # 8-byte Reload
movq %rbx, (%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI6_3(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebp
xorps %xmm0, %xmm0
cvtsi2ssl 24(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI6_3(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebx
movl $.L.str.4, %edi
movl %ebp, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
shlq $32, %rbx
orq %rbp, %rbx
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
movq _ZZ5wtimevE3tv0+8(%rip), %r15
movq _ZZ5wtimevE3tv0(%rip), %rbp
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_21
# %bb.20:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r14d, 60(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 56(%rsp)
movl %r12d, 52(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z13matrixMultGPUPfS_S_iii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_21:
imulq $1000000, %rbp, %rax # imm = 0xF4240
addq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_4(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_4(%rip), %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq (%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
movq 8(%rsp), %rsi
movq %rax, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 64(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r13, %rsi
movq 24(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movl %r14d, %ecx
movl %r12d, %r8d
movq %rbp, %r9
callq _Z4diffPfS_iiiS_
testl %eax, %eax
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $1, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_22:
.cfi_def_cfa_offset 256
movl $.Lstr.2, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matrixMultGPUPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZZ5wtimevE3tv0,@object # @_ZZ5wtimevE3tv0
.local _ZZ5wtimevE3tv0
.comm _ZZ5wtimevE3tv0,16,8
.type _Z13matrixMultGPUPfS_S_iii,@object # @_Z13matrixMultGPUPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z13matrixMultGPUPfS_S_iii
.p2align 3, 0x0
_Z13matrixMultGPUPfS_S_iii:
.quad _Z28__device_stub__matrixMultGPUPfS_S_iii
.size _Z13matrixMultGPUPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4.1f "
.size .L.str, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "[%i,%i]: %f!=%f\n"
.size .L.str.2, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "grid_x_size = %i, grid_y_size = %i\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time GPU=%f\n"
.size .L.str.5, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13matrixMultGPUPfS_S_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "ERROR=GPU.vs.CPU matrix mult differs"
.size .Lstr, 37
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "GPU.vs.CPU matrix is equal! :D"
.size .Lstr.1, 31
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "./exec hA hB/WA wB"
.size .Lstr.2, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__matrixMultGPUPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZZ5wtimevE3tv0
.addrsig_sym _Z13matrixMultGPUPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA device assembly to AMD device assembly. | code for sm_80
Function : _Z13matrixMultGPUPfS_S_iii
.headerflags @"EF_CUDA_TEXMODE_UNIFIED EF_CUDA_64BIT_ADDRESS EF_CUDA_SM80 EF_CUDA_VIRTUAL_SM(EF_CUDA_SM80)"
/*0000*/ MOV R1, c[0x0][0x28] ; /* 0x00000a0000017a02 */
/* 0x000fe40000000f00 */
/*0010*/ S2R R0, SR_CTAID.X ; /* 0x0000000000007919 */
/* 0x000e220000002500 */
/*0020*/ MOV R6, c[0x0][0x178] ; /* 0x00005e0000067a02 */
/* 0x000fc60000000f00 */
/*0030*/ S2R R3, SR_TID.X ; /* 0x0000000000037919 */
/* 0x000e280000002100 */
/*0040*/ S2R R7, SR_CTAID.Y ; /* 0x0000000000077919 */
/* 0x000e680000002600 */
/*0050*/ S2R R2, SR_TID.Y ; /* 0x0000000000027919 */
/* 0x000e620000002200 */
/*0060*/ IMAD R0, R0, c[0x0][0x0], R3 ; /* 0x0000000000007a24 */
/* 0x001fca00078e0203 */
/*0070*/ ISETP.GE.AND P0, PT, R0, c[0x0][0x180], PT ; /* 0x0000600000007a0c */
/* 0x000fe20003f06270 */
/*0080*/ IMAD R7, R7, c[0x0][0x4], R2 ; /* 0x0000010007077a24 */
/* 0x002fca00078e0202 */
/*0090*/ ISETP.GE.OR P0, PT, R7, c[0x0][0x17c], P0 ; /* 0x00005f0007007a0c */
/* 0x000fc80000706670 */
/*00a0*/ ISETP.LT.OR P0, PT, R6, 0x1, P0 ; /* 0x000000010600780c */
/* 0x000fda0000701670 */
/*00b0*/ @P0 EXIT ; /* 0x000000000000094d */
/* 0x000fea0003800000 */
/*00c0*/ IADD3 R2, R6.reuse, -0x1, RZ ; /* 0xffffffff06027810 */
/* 0x040fe20007ffe0ff */
/*00d0*/ HFMA2.MMA R9, -RZ, RZ, 0, 2.384185791015625e-07 ; /* 0x00000004ff097435 */
/* 0x000fe200000001ff */
/*00e0*/ ULDC.64 UR4, c[0x0][0x118] ; /* 0x0000460000047ab9 */
/* 0x000fe20000000a00 */
/*00f0*/ LOP3.LUT R8, R6, 0x3, RZ, 0xc0, !PT ; /* 0x0000000306087812 */
/* 0x000fe400078ec0ff */
/*0100*/ ISETP.GE.U32.AND P0, PT, R2, 0x3, PT ; /* 0x000000030200780c */
/* 0x000fe20003f06070 */
/*0110*/ IMAD R2, R7, c[0x0][0x180], R0 ; /* 0x0000600007027a24 */
/* 0x000fe200078e0200 */
/*0120*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fc80000000f00 */
/*0130*/ IMAD.WIDE R2, R2, R9, c[0x0][0x170] ; /* 0x00005c0002027625 */
/* 0x000fce00078e0209 */
/*0140*/ @!P0 BRA 0xcb0 ; /* 0x00000b6000008947 */
/* 0x000fea0003800000 */
/*0150*/ IADD3 R10, -R8, c[0x0][0x178], RZ ; /* 0x00005e00080a7a10 */
/* 0x000fe20007ffe1ff */
/*0160*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x000162000c1e1900 */
/*0170*/ ULDC.64 UR6, c[0x0][0x160] ; /* 0x0000580000067ab9 */
/* 0x000fe20000000a00 */
/*0180*/ IMAD R12, R7, c[0x0][0x178], RZ ; /* 0x00005e00070c7a24 */
/* 0x000fe200078e02ff */
/*0190*/ ISETP.GT.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f04270 */
/*01a0*/ IMAD.WIDE R14, R0, R9, c[0x0][0x168] ; /* 0x00005a00000e7625 */
/* 0x000fe200078e0209 */
/*01b0*/ MOV R11, RZ ; /* 0x000000ff000b7202 */
/* 0x000fd60000000f00 */
/*01c0*/ @!P0 BRA 0xae0 ; /* 0x0000091000008947 */
/* 0x001fea0003800000 */
/*01d0*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe40003f24270 */
/*01e0*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x80, 0x0 ; /* 0x000000000000781c */
/* 0x000fd60003f0f070 */
/*01f0*/ @!P1 BRA 0x7a0 ; /* 0x000005a000009947 */
/* 0x000fea0003800000 */
/*0200*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe40003f0e170 */
/*0210*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0220*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x004ea2000c1e1900 */
/*0230*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*0240*/ IMAD.WIDE R4, R12, 0x4, R4 ; /* 0x000000040c047825 */
/* 0x000fca00078e0204 */
/*0250*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ea4000c1e1900 */
/*0260*/ FFMA R13, R16, R17, R13 ; /* 0x00000011100d7223 */
/* 0x024fe4000000000d */
/*0270*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc600078e020e */
/*0280*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0290*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*02a0*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000ea4000c1e1900 */
/*02b0*/ FFMA R21, R18, R19, R13 ; /* 0x0000001312157223 */
/* 0x004fc4000000000d */
/*02c0*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*02d0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*02e0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*02f0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea4000c1e1900 */
/*0300*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*0310*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*0320*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0330*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0340*/ LDG.E R13, [R4.64+0xc] ; /* 0x00000c04040d7981 */
/* 0x001ee2000c1e1900 */
/*0350*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0360*/ FFMA R13, R20, R13, R23 ; /* 0x0000000d140d7223 */
/* 0x008fca0000000017 */
/*0370*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0380*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0390*/ LDG.E R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000e64000c1e1900 */
/*03a0*/ FFMA R21, R20, R18, R13 ; /* 0x0000001214157223 */
/* 0x002fc4000000000d */
/*03b0*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*03c0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*03d0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*03e0*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000ea4000c1e1900 */
/*03f0*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*0400*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*0410*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0420*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0430*/ LDG.E R13, [R4.64+0x18] ; /* 0x00001804040d7981 */
/* 0x001ee2000c1e1900 */
/*0440*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0450*/ FFMA R13, R20, R13, R23 ; /* 0x0000000d140d7223 */
/* 0x008fca0000000017 */
/*0460*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0470*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0480*/ LDG.E R18, [R4.64+0x1c] ; /* 0x00001c0404127981 */
/* 0x000e64000c1e1900 */
/*0490*/ FFMA R21, R20, R18, R13 ; /* 0x0000001214157223 */
/* 0x002fc4000000000d */
/*04a0*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*04b0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*04c0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*04d0*/ LDG.E R14, [R4.64+0x20] ; /* 0x00002004040e7981 */
/* 0x000ea4000c1e1900 */
/*04e0*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*04f0*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*0500*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0510*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*0520*/ LDG.E R13, [R4.64+0x24] ; /* 0x00002404040d7981 */
/* 0x001ee2000c1e1900 */
/*0530*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0540*/ FFMA R13, R20, R13, R23 ; /* 0x0000000d140d7223 */
/* 0x008fca0000000017 */
/*0550*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0560*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0570*/ LDG.E R18, [R4.64+0x28] ; /* 0x0000280404127981 */
/* 0x000e64000c1e1900 */
/*0580*/ FFMA R21, R20, R18, R13 ; /* 0x0000001214157223 */
/* 0x002fc4000000000d */
/*0590*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*05a0*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x000fe8000c101904 */
/*05b0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*05c0*/ LDG.E R14, [R4.64+0x2c] ; /* 0x00002c04040e7981 */
/* 0x000ea4000c1e1900 */
/*05d0*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*05e0*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*05f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0600*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ea8000c1e1900 */
/*0610*/ LDG.E R13, [R4.64+0x30] ; /* 0x00003004040d7981 */
/* 0x001ea2000c1e1900 */
/*0620*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0630*/ FFMA R13, R20, R13, R23 ; /* 0x0000000d140d7223 */
/* 0x004fca0000000017 */
/*0640*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0650*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000ea8000c1e1900 */
/*0660*/ LDG.E R18, [R4.64+0x34] ; /* 0x0000340404127981 */
/* 0x000ea4000c1e1900 */
/*0670*/ FFMA R25, R20, R18, R13 ; /* 0x0000001214197223 */
/* 0x004fc4000000000d */
/*0680*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*0690*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0005e8000c101904 */
/*06a0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000e68000c1e1900 */
/*06b0*/ LDG.E R14, [R4.64+0x38] ; /* 0x00003804040e7981 */
/* 0x000e62000c1e1900 */
/*06c0*/ IADD3 R10, R10, -0x10, RZ ; /* 0xfffffff00a0a7810 */
/* 0x000fe20007ffe0ff */
/*06d0*/ FFMA R23, R20, R14, R25 ; /* 0x0000000e14177223 */
/* 0x002fc40000000019 */
/*06e0*/ IMAD.WIDE R20, R6, 0x4, R18 ; /* 0x0000000406147825 */
/* 0x000fc600078e0212 */
/*06f0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*0700*/ LDG.E R13, [R4.64+0x3c] ; /* 0x00003c04040d7981 */
/* 0x001ee8000c1e1900 */
/*0710*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ee2000c1e1900 */
/*0720*/ ISETP.GT.AND P1, PT, R10, 0xc, PT ; /* 0x0000000c0a00780c */
/* 0x000fe20003f24270 */
/*0730*/ UIADD3 UR6, UP0, UR6, 0x40, URZ ; /* 0x0000004006067890 */
/* 0x000fe2000ff1e03f */
/*0740*/ IADD3 R11, R11, 0x10, RZ ; /* 0x000000100b0b7810 */
/* 0x000fc60007ffe0ff */
/*0750*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0760*/ FFMA R13, R14, R13, R23 ; /* 0x0000000d0e0d7223 */
/* 0x008fe40000000017 */
/*0770*/ IMAD.WIDE R14, R6, 0x4, R20 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0214 */
/*0780*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0005e4000c101904 */
/*0790*/ @P1 BRA 0x210 ; /* 0xfffffa7000001947 */
/* 0x000fea000383ffff */
/*07a0*/ ISETP.GT.AND P1, PT, R10, 0x4, PT ; /* 0x000000040a00780c */
/* 0x000fda0003f24270 */
/*07b0*/ @!P1 BRA 0xac0 ; /* 0x0000030000009947 */
/* 0x000fea0003800000 */
/*07c0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*07d0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee2000c1e1900 */
/*07e0*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*07f0*/ IMAD.WIDE R4, R12, 0x4, R4 ; /* 0x000000040c047825 */
/* 0x000fca00078e0204 */
/*0800*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ee4000c1e1900 */
/*0810*/ FFMA R13, R16, R17, R13 ; /* 0x00000011100d7223 */
/* 0x02cfe4000000000d */
/*0820*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc600078e020e */
/*0830*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0840*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0850*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000ea4000c1e1900 */
/*0860*/ FFMA R21, R18, R19, R13 ; /* 0x0000001312157223 */
/* 0x004fc4000000000d */
/*0870*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*0880*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0890*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*08a0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea4000c1e1900 */
/*08b0*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*08c0*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*08d0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0005e8000c101904 */
/*08e0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ee8000c1e1900 */
/*08f0*/ LDG.E R13, [R4.64+0xc] ; /* 0x00000c04040d7981 */
/* 0x001ee2000c1e1900 */
/*0900*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0910*/ FFMA R13, R20, R13, R23 ; /* 0x0000000d140d7223 */
/* 0x008fca0000000017 */
/*0920*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0930*/ LDG.E R20, [R16.64] ; /* 0x0000000410147981 */
/* 0x000e68000c1e1900 */
/*0940*/ LDG.E R18, [R4.64+0x10] ; /* 0x0000100404127981 */
/* 0x000e64000c1e1900 */
/*0950*/ FFMA R21, R20, R18, R13 ; /* 0x0000001214157223 */
/* 0x002fc4000000000d */
/*0960*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*0970*/ STG.E [R2.64], R21 ; /* 0x0000001502007986 */
/* 0x0003e8000c101904 */
/*0980*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0990*/ LDG.E R14, [R4.64+0x14] ; /* 0x00001404040e7981 */
/* 0x000ea4000c1e1900 */
/*09a0*/ FFMA R23, R20, R14, R21 ; /* 0x0000000e14177223 */
/* 0x004fc40000000015 */
/*09b0*/ IMAD.WIDE R14, R6, 0x4, R18 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0212 */
/*09c0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*09d0*/ LDG.E R20, [R14.64] ; /* 0x000000040e147981 */
/* 0x000ea8000c1e1900 */
/*09e0*/ LDG.E R13, [R4.64+0x18] ; /* 0x00001804040d7981 */
/* 0x001ea2000c1e1900 */
/*09f0*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc800078e020e */
/*0a00*/ FFMA R25, R20, R13, R23 ; /* 0x0000000d14197223 */
/* 0x004fca0000000017 */
/*0a10*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0a20*/ LDG.E R13, [R4.64+0x1c] ; /* 0x00001c04040d7981 */
/* 0x000ea8000c1e1900 */
/*0a30*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea2000c1e1900 */
/*0a40*/ UIADD3 UR6, UP0, UR6, 0x20, URZ ; /* 0x0000002006067890 */
/* 0x000fe2000ff1e03f */
/*0a50*/ PLOP3.LUT P0, PT, PT, PT, PT, 0x8, 0x0 ; /* 0x000000000000781c */
/* 0x000fe20003f0e170 */
/*0a60*/ IMAD.WIDE R14, R6, 0x4, R16 ; /* 0x00000004060e7825 */
/* 0x000fe200078e0210 */
/*0a70*/ IADD3 R11, R11, 0x8, RZ ; /* 0x000000080b0b7810 */
/* 0x000fc40007ffe0ff */
/*0a80*/ IADD3 R10, R10, -0x8, RZ ; /* 0xfffffff80a0a7810 */
/* 0x000fe20007ffe0ff */
/*0a90*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0aa0*/ FFMA R13, R18, R13, R25 ; /* 0x0000000d120d7223 */
/* 0x004fca0000000019 */
/*0ab0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e8000c101904 */
/*0ac0*/ ISETP.NE.OR P0, PT, R10, RZ, P0 ; /* 0x000000ff0a00720c */
/* 0x000fda0000705670 */
/*0ad0*/ @!P0 BRA 0xcb0 ; /* 0x000001d000008947 */
/* 0x000fea0003800000 */
/*0ae0*/ MOV R4, UR6 ; /* 0x0000000600047c02 */
/* 0x000fe20008000f00 */
/*0af0*/ LDG.E R16, [R14.64] ; /* 0x000000040e107981 */
/* 0x000ee2000c1e1900 */
/*0b00*/ MOV R5, UR7 ; /* 0x0000000700057c02 */
/* 0x000fca0008000f00 */
/*0b10*/ IMAD.WIDE R4, R12, 0x4, R4 ; /* 0x000000040c047825 */
/* 0x000fca00078e0204 */
/*0b20*/ LDG.E R17, [R4.64] ; /* 0x0000000404117981 */
/* 0x000ee4000c1e1900 */
/*0b30*/ FFMA R13, R16, R17, R13 ; /* 0x00000011100d7223 */
/* 0x02efe4000000000d */
/*0b40*/ IMAD.WIDE R16, R6, 0x4, R14 ; /* 0x0000000406107825 */
/* 0x000fc600078e020e */
/*0b50*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e8000c101904 */
/*0b60*/ LDG.E R18, [R16.64] ; /* 0x0000000410127981 */
/* 0x000ea8000c1e1900 */
/*0b70*/ LDG.E R19, [R4.64+0x4] ; /* 0x0000040404137981 */
/* 0x000ea4000c1e1900 */
/*0b80*/ FFMA R23, R18, R19, R13 ; /* 0x0000001312177223 */
/* 0x004fc4000000000d */
/*0b90*/ IMAD.WIDE R18, R6, 0x4, R16 ; /* 0x0000000406127825 */
/* 0x000fc600078e0210 */
/*0ba0*/ STG.E [R2.64], R23 ; /* 0x0000001702007986 */
/* 0x0003e8000c101904 */
/*0bb0*/ LDG.E R20, [R18.64] ; /* 0x0000000412147981 */
/* 0x000ea8000c1e1900 */
/*0bc0*/ LDG.E R14, [R4.64+0x8] ; /* 0x00000804040e7981 */
/* 0x000ea2000c1e1900 */
/*0bd0*/ IADD3 R10, R10, -0x4, RZ ; /* 0xfffffffc0a0a7810 */
/* 0x000fe20007ffe0ff */
/*0be0*/ FFMA R25, R20, R14, R23 ; /* 0x0000000e14197223 */
/* 0x004fc40000000017 */
/*0bf0*/ IMAD.WIDE R20, R6, 0x4, R18 ; /* 0x0000000406147825 */
/* 0x000fc600078e0212 */
/*0c00*/ STG.E [R2.64], R25 ; /* 0x0000001902007986 */
/* 0x0003e8000c101904 */
/*0c10*/ LDG.E R13, [R4.64+0xc] ; /* 0x00000c04040d7981 */
/* 0x001ea8000c1e1900 */
/*0c20*/ LDG.E R14, [R20.64] ; /* 0x00000004140e7981 */
/* 0x000ea2000c1e1900 */
/*0c30*/ ISETP.NE.AND P0, PT, R10, RZ, PT ; /* 0x000000ff0a00720c */
/* 0x000fe20003f05270 */
/*0c40*/ UIADD3 UR6, UP0, UR6, 0x10, URZ ; /* 0x0000001006067890 */
/* 0x000fe2000ff1e03f */
/*0c50*/ IADD3 R11, R11, 0x4, RZ ; /* 0x000000040b0b7810 */
/* 0x000fc60007ffe0ff */
/*0c60*/ UIADD3.X UR7, URZ, UR7, URZ, UP0, !UPT ; /* 0x000000073f077290 */
/* 0x000fe200087fe43f */
/*0c70*/ FFMA R13, R14, R13, R25 ; /* 0x0000000d0e0d7223 */
/* 0x004fe40000000019 */
/*0c80*/ IMAD.WIDE R14, R6, 0x4, R20 ; /* 0x00000004060e7825 */
/* 0x000fc600078e0214 */
/*0c90*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0003e4000c101904 */
/*0ca0*/ @P0 BRA 0xae0 ; /* 0xfffffe3000000947 */
/* 0x002fea000383ffff */
/*0cb0*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fda0003f05270 */
/*0cc0*/ @!P0 EXIT ; /* 0x000000000000894d */
/* 0x000fea0003800000 */
/*0cd0*/ LDG.E R13, [R2.64] ; /* 0x00000004020d7981 */
/* 0x026162000c1e1900 */
/*0ce0*/ IMAD R4, R7, c[0x0][0x178], R11 ; /* 0x00005e0007047a24 */
/* 0x000fe400078e020b */
/*0cf0*/ IMAD R0, R11, c[0x0][0x178], R0 ; /* 0x00005e000b007a24 */
/* 0x000fe400078e0200 */
/*0d00*/ IMAD.WIDE R4, R4, R9, c[0x0][0x160] ; /* 0x0000580004047625 */
/* 0x000fca00078e0209 */
/*0d10*/ MOV R10, R4 ; /* 0x00000004000a7202 */
/* 0x000fe40000000f00 */
/*0d20*/ MOV R11, R5 ; /* 0x00000005000b7202 */
/* 0x000fe20000000f00 */
/*0d30*/ IMAD.WIDE R4, R0, R9, c[0x0][0x168] ; /* 0x00005a0000047625 */
/* 0x001fca00078e0209 */
/*0d40*/ LDG.E R0, [R4.64] ; /* 0x0000000404007981 */
/* 0x0010a8000c1e1900 */
/*0d50*/ LDG.E R7, [R10.64] ; /* 0x000000040a077981 */
/* 0x0002a2000c1e1900 */
/*0d60*/ IADD3 R8, R8, -0x1, RZ ; /* 0xffffffff08087810 */
/* 0x000fc80007ffe0ff */
/*0d70*/ ISETP.NE.AND P0, PT, R8, RZ, PT ; /* 0x000000ff0800720c */
/* 0x000fe20003f05270 */
/*0d80*/ IMAD.WIDE R4, R6, 0x4, R4 ; /* 0x0000000406047825 */
/* 0x001fe200078e0204 */
/*0d90*/ IADD3 R10, P1, R10, 0x4, RZ ; /* 0x000000040a0a7810 */
/* 0x002fc80007f3e0ff */
/*0da0*/ IADD3.X R11, RZ, R11, RZ, P1, !PT ; /* 0x0000000bff0b7210 */
/* 0x000fe20000ffe4ff */
/*0db0*/ FFMA R13, R0, R7, R13 ; /* 0x00000007000d7223 */
/* 0x024fca000000000d */
/*0dc0*/ STG.E [R2.64], R13 ; /* 0x0000000d02007986 */
/* 0x0001e2000c101904 */
/*0dd0*/ @P0 BRA 0xd40 ; /* 0xffffff6000000947 */
/* 0x000fea000383ffff */
/*0de0*/ EXIT ; /* 0x000000000000794d */
/* 0x000fea0003800000 */
/*0df0*/ BRA 0xdf0; /* 0xfffffff000007947 */
/* 0x000fc0000383ffff */
/*0e00*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e10*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e20*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e30*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e40*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e50*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e60*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
/*0e70*/ NOP; /* 0x0000000000007918 */
/* 0x000fc00000000000 */
.......... | .text
.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
.protected _Z13matrixMultGPUPfS_S_iii
.globl _Z13matrixMultGPUPfS_S_iii
.p2align 8
.type _Z13matrixMultGPUPfS_S_iii,@function
_Z13matrixMultGPUPfS_S_iii:
s_clause 0x2
s_load_b32 s2, s[0:1], 0x34
s_load_b64 s[4:5], s[0:1], 0x18
s_load_b32 s3, s[0:1], 0x20
v_bfe_u32 v1, v0, 10, 10
v_and_b32_e32 v2, 0x3ff, v0
s_waitcnt lgkmcnt(0)
s_lshr_b32 s6, s2, 16
s_and_b32 s2, s2, 0xffff
s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
v_mad_u64_u32 v[4:5], null, s15, s6, v[1:2]
v_mad_u64_u32 v[0:1], null, s14, s2, v[2:3]
v_cmp_gt_i32_e32 vcc_lo, s5, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
v_cmp_gt_i32_e64 s2, s3, v0
s_and_b32 s2, vcc_lo, s2
s_cmp_gt_i32 s4, 0
s_cselect_b32 s5, -1, 0
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
s_and_b32 s2, s2, s5
s_and_saveexec_b32 s5, s2
s_cbranch_execz .LBB0_3
s_load_b64 s[6:7], s[0:1], 0x10
v_mad_u64_u32 v[1:2], null, v4, s3, v[0:1]
s_load_b128 s[0:3], s[0:1], 0x0
v_mul_lo_u32 v4, v4, s4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_ashrrev_i32_e32 v2, 31, v1
v_ashrrev_i32_e32 v5, 31, v4
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
v_lshlrev_b64 v[2:3], 2, v[1:2]
v_lshlrev_b64 v[4:5], 2, v[4:5]
s_waitcnt lgkmcnt(0)
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v2, vcc_lo, s6, v2
v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
v_add_co_u32 v4, vcc_lo, s0, v4
v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
global_load_b32 v6, v[2:3], off
s_mov_b32 s0, s4
.p2align 6
.LBB0_2:
v_ashrrev_i32_e32 v1, 31, v0
s_add_i32 s0, s0, -1
s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
s_cmp_lg_u32 s0, 0
v_lshlrev_b64 v[7:8], 2, v[0:1]
v_add_nc_u32_e32 v0, s4, v0
s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
v_add_co_u32 v7, vcc_lo, s2, v7
v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
global_load_b32 v1, v[4:5], off
global_load_b32 v7, v[7:8], off
v_add_co_u32 v4, vcc_lo, v4, 4
v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
s_waitcnt vmcnt(0)
v_fmac_f32_e32 v6, v1, v7
global_store_b32 v[2:3], v6, off
s_cbranch_scc1 .LBB0_2
.LBB0_3:
s_nop 0
s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
s_endpgm
.section .rodata,"a",@progbits
.p2align 6, 0x0
.amdhsa_kernel _Z13matrixMultGPUPfS_S_iii
.amdhsa_group_segment_fixed_size 0
.amdhsa_private_segment_fixed_size 0
.amdhsa_kernarg_size 296
.amdhsa_user_sgpr_count 14
.amdhsa_user_sgpr_dispatch_ptr 0
.amdhsa_user_sgpr_queue_ptr 0
.amdhsa_user_sgpr_kernarg_segment_ptr 1
.amdhsa_user_sgpr_dispatch_id 0
.amdhsa_user_sgpr_private_segment_size 0
.amdhsa_wavefront_size32 1
.amdhsa_uses_dynamic_stack 0
.amdhsa_enable_private_segment 0
.amdhsa_system_sgpr_workgroup_id_x 1
.amdhsa_system_sgpr_workgroup_id_y 1
.amdhsa_system_sgpr_workgroup_id_z 0
.amdhsa_system_sgpr_workgroup_info 0
.amdhsa_system_vgpr_workitem_id 1
.amdhsa_next_free_vgpr 9
.amdhsa_next_free_sgpr 16
.amdhsa_float_round_mode_32 0
.amdhsa_float_round_mode_16_64 0
.amdhsa_float_denorm_mode_32 3
.amdhsa_float_denorm_mode_16_64 3
.amdhsa_dx10_clamp 1
.amdhsa_ieee_mode 1
.amdhsa_fp16_overflow 0
.amdhsa_workgroup_processor_mode 1
.amdhsa_memory_ordered 1
.amdhsa_forward_progress 0
.amdhsa_shared_vgpr_count 0
.amdhsa_exception_fp_ieee_invalid_op 0
.amdhsa_exception_fp_denorm_src 0
.amdhsa_exception_fp_ieee_div_zero 0
.amdhsa_exception_fp_ieee_overflow 0
.amdhsa_exception_fp_ieee_underflow 0
.amdhsa_exception_fp_ieee_inexact 0
.amdhsa_exception_int_div_zero 0
.end_amdhsa_kernel
.text
.Lfunc_end0:
.size _Z13matrixMultGPUPfS_S_iii, .Lfunc_end0-_Z13matrixMultGPUPfS_S_iii
.section .AMDGPU.csdata,"",@progbits
.text
.p2alignl 7, 3214868480
.fill 96, 4, 3214868480
.type __hip_cuid_,@object
.section .bss,"aw",@nobits
.globl __hip_cuid_
__hip_cuid_:
.byte 0
.size __hip_cuid_, 1
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym __hip_cuid_
.amdgpu_metadata
---
amdhsa.kernels:
- .args:
- .address_space: global
.offset: 0
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 8
.size: 8
.value_kind: global_buffer
- .address_space: global
.offset: 16
.size: 8
.value_kind: global_buffer
- .offset: 24
.size: 4
.value_kind: by_value
- .offset: 28
.size: 4
.value_kind: by_value
- .offset: 32
.size: 4
.value_kind: by_value
- .offset: 40
.size: 4
.value_kind: hidden_block_count_x
- .offset: 44
.size: 4
.value_kind: hidden_block_count_y
- .offset: 48
.size: 4
.value_kind: hidden_block_count_z
- .offset: 52
.size: 2
.value_kind: hidden_group_size_x
- .offset: 54
.size: 2
.value_kind: hidden_group_size_y
- .offset: 56
.size: 2
.value_kind: hidden_group_size_z
- .offset: 58
.size: 2
.value_kind: hidden_remainder_x
- .offset: 60
.size: 2
.value_kind: hidden_remainder_y
- .offset: 62
.size: 2
.value_kind: hidden_remainder_z
- .offset: 80
.size: 8
.value_kind: hidden_global_offset_x
- .offset: 88
.size: 8
.value_kind: hidden_global_offset_y
- .offset: 96
.size: 8
.value_kind: hidden_global_offset_z
- .offset: 104
.size: 2
.value_kind: hidden_grid_dims
.group_segment_fixed_size: 0
.kernarg_segment_align: 8
.kernarg_segment_size: 296
.language: OpenCL C
.language_version:
- 2
- 0
.max_flat_workgroup_size: 1024
.name: _Z13matrixMultGPUPfS_S_iii
.private_segment_fixed_size: 0
.sgpr_count: 18
.sgpr_spill_count: 0
.symbol: _Z13matrixMultGPUPfS_S_iii.kd
.uniform_work_group_size: 1
.uses_dynamic_stack: false
.vgpr_count: 9
.vgpr_spill_count: 0
.wavefront_size: 32
.workgroup_processor_mode: 1
amdhsa.target: amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
- 1
- 2
...
.end_amdgpu_metadata |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_00142082_00000000-6_main.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2065:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2065:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z5wtimev
.type _Z5wtimev, @function
_Z5wtimev:
.LFB2057:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl $0, %esi
leaq _ZZ5wtimevE3tv0(%rip), %rdi
call gettimeofday@PLT
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax
addq 8+_ZZ5wtimevE3tv0(%rip), %rax
pxor %xmm0, %xmm0
cvtsi2sdq %rax, %xmm0
divsd .LC0(%rip), %xmm0
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2057:
.size _Z5wtimev, .-_Z5wtimev
.globl _Z12matrixMulCPUPfS_iiiS_
.type _Z12matrixMulCPUPfS_iiiS_, @function
_Z12matrixMulCPUPfS_iiiS_:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
movq %rsi, -8(%rsp)
movl %edx, -12(%rsp)
testl %edx, %edx
jle .L5
movq %rdi, %rbx
movl %ecx, %ebp
movl %r8d, %r11d
movslq %r8d, %rdi
salq $2, %rdi
movl $0, %r13d
movl $0, %ecx
movl $0, %edx
movslq %ebp, %r14
movq %r9, %r8
movq %r14, %rsi
jmp .L7
.L11:
movslq %ecx, %rax
leaq (%r8,%rax,4), %r10
movq -8(%rsp), %r14
movslq %r13d, %rax
leaq (%rbx,%rax,4), %r15
addq %rsi, %rax
leaq (%rbx,%rax,4), %r9
movl $0, %r12d
movl %edx, -20(%rsp)
movl %ecx, -16(%rsp)
.L10:
movq %r10, %rcx
movl $0x00000000, (%r10)
testl %ebp, %ebp
jle .L8
movq %r14, %rdx
movq %r15, %rax
.L9:
movss (%rax), %xmm0
mulss (%rdx), %xmm0
addss (%rcx), %xmm0
movss %xmm0, (%rcx)
addq $4, %rax
addq %rdi, %rdx
cmpq %r9, %rax
jne .L9
.L8:
addl $1, %r12d
addq $4, %r10
addq $4, %r14
cmpl %r12d, %r11d
jne .L10
movl -20(%rsp), %edx
movl -16(%rsp), %ecx
.L12:
addl $1, %edx
addl %r11d, %ecx
addl %ebp, %r13d
cmpl %edx, -12(%rsp)
je .L5
.L7:
testl %r11d, %r11d
jg .L11
jmp .L12
.L5:
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2058:
.size _Z12matrixMulCPUPfS_iiiS_, .-_Z12matrixMulCPUPfS_iiiS_
.globl _Z11init_matrixPfiif
.type _Z11init_matrixPfiif, @function
_Z11init_matrixPfiif:
.LFB2059:
.cfi_startproc
endbr64
movq %rdi, %r9
testl %esi, %esi
jle .L16
movl $0, %r8d
movl $0, %edi
movss .LC2(%rip), %xmm3
jmp .L18
.L26:
leal (%rax,%r8), %ecx
movslq %ecx, %rcx
movss %xmm0, (%r9,%rcx,4)
.L20:
addl $1, %eax
cmpl %eax, %edx
je .L22
.L21:
cmpl %eax, %edi
je .L26
leal (%rax,%r8), %ecx
movslq %ecx, %rcx
pxor %xmm2, %xmm2
cvtsi2ssl %edx, %xmm2
movaps %xmm3, %xmm1
divss %xmm2, %xmm1
movss %xmm1, (%r9,%rcx,4)
jmp .L20
.L22:
addl $1, %edi
addl %edx, %r8d
cmpl %edi, %esi
je .L16
.L18:
movl $0, %eax
testl %edx, %edx
jg .L21
jmp .L22
.L16:
ret
.cfi_endproc
.LFE2059:
.size _Z11init_matrixPfiif, .-_Z11init_matrixPfiif
.section .rodata.str1.1,"aMS",@progbits,1
.LC3:
.string "%4.1f "
.LC4:
.string "\n"
.text
.globl _Z12print_matrixPfii
.type _Z12print_matrixPfii, @function
_Z12print_matrixPfii:
.LFB2060:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $40, %rsp
.cfi_def_cfa_offset 96
movq %rdi, 16(%rsp)
movl %esi, 12(%rsp)
testl %esi, %esi
jle .L27
movl %edx, %r15d
movl $0, %r14d
movl $0, %r13d
movslq %edx, %rax
movq %rax, 24(%rsp)
leaq .LC3(%rip), %r12
jmp .L29
.L31:
movslq %r14d, %rax
movq 16(%rsp), %rcx
leaq (%rcx,%rax,4), %rbx
movq 24(%rsp), %rdx
addq %rdx, %rax
leaq (%rcx,%rax,4), %rbp
.L30:
pxor %xmm0, %xmm0
cvtss2sd (%rbx), %xmm0
movq %r12, %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
addq $4, %rbx
cmpq %rbp, %rbx
jne .L30
.L32:
leaq .LC4(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
addl $1, %r13d
addl %r15d, %r14d
cmpl %r13d, 12(%rsp)
je .L27
.L29:
testl %r15d, %r15d
jg .L31
jmp .L32
.L27:
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2060:
.size _Z12print_matrixPfii, .-_Z12print_matrixPfii
.section .rodata.str1.1
.LC7:
.string "[%i,%i]: %f!=%f\n"
.text
.globl _Z4diffPfS_iiiS_
.type _Z4diffPfS_iiiS_, @function
_Z4diffPfS_iiiS_:
.LFB2061:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $56, %rsp
.cfi_def_cfa_offset 112
movq %rdi, %r12
movq %rsi, 16(%rsp)
movl %edx, %r15d
movl %ecx, %ebp
movl %r8d, %ebx
movq %r9, 32(%rsp)
movl %r8d, %edi
imull %edx, %edi
movslq %edi, %rdi
salq $2, %rdi
call malloc@PLT
testl %r15d, %r15d
jle .L49
movq %rax, %r14
movslq %ebx, %rcx
leaq 0(,%rcx,4), %rsi
movl $0, %edx
movl $0, %eax
movl $0, %r13d
movslq %ebp, %rdi
movq %rdi, 24(%rsp)
movq %r14, 8(%rsp)
movl %r13d, 4(%rsp)
movq %rcx, 40(%rsp)
movl %r15d, %edi
jmp .L37
.L42:
movslq %eax, %r8
movq 8(%rsp), %rcx
leaq (%rcx,%r8,4), %r9
movq 16(%rsp), %r11
movslq %edx, %r8
leaq (%r12,%r8,4), %r15
movq 24(%rsp), %rcx
addq %rcx, %r8
leaq (%r12,%r8,4), %r8
movl $0, %r10d
.L40:
movq %r9, %r14
movl $0x00000000, (%r9)
testl %ebp, %ebp
jle .L38
movq %r11, %r13
movq %r15, %rcx
pxor %xmm1, %xmm1
.L39:
movss (%rcx), %xmm0
mulss 0(%r13), %xmm0
addss %xmm0, %xmm1
addq $4, %rcx
addq %rsi, %r13
cmpq %r8, %rcx
jne .L39
movss %xmm1, (%r14)
.L38:
addl $1, %r10d
addq $4, %r9
addq $4, %r11
cmpl %r10d, %ebx
jne .L40
.L43:
movl 4(%rsp), %ecx
leal 1(%rcx), %r8d
addl %ebx, %eax
addl %ebp, %edx
cmpl %r8d, %edi
je .L50
movl %r8d, 4(%rsp)
.L37:
testl %ebx, %ebx
jg .L42
jmp .L43
.L58:
cvtss2sd %xmm0, %xmm0
cvtss2sd %xmm1, %xmm1
movl %eax, %ecx
movl %esi, %edx
leaq .LC7(%rip), %rsi
movl $2, %edi
movl $2, %eax
call __printf_chk@PLT
movl $0, %eax
.L35:
addq $56, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L48:
.cfi_restore_state
leal 1(%rsi), %eax
addl %ebx, %edi
cmpl %esi, %r13d
je .L51
movl %eax, %esi
.L41:
testl %ebx, %ebx
jle .L48
movslq %edi, %rdx
salq $2, %rdx
leaq (%r14,%rdx), %r9
addq %r8, %rdx
movl $0, %eax
.L46:
movss (%r9,%rax,4), %xmm0
movss (%rdx,%rax,4), %xmm1
movaps %xmm0, %xmm2
subss %xmm1, %xmm2
andps %xmm4, %xmm2
cvtss2sd %xmm2, %xmm2
comisd %xmm3, %xmm2
ja .L58
addq $1, %rax
cmpq %rcx, %rax
jne .L46
jmp .L48
.L50:
movq 8(%rsp), %r14
movl 4(%rsp), %r13d
movq 40(%rsp), %rcx
movl $0, %edi
movl $0, %esi
movss .LC5(%rip), %xmm4
movsd .LC6(%rip), %xmm3
movq 32(%rsp), %r8
jmp .L41
.L49:
movl $1, %eax
jmp .L35
.L51:
movl $1, %eax
jmp .L35
.cfi_endproc
.LFE2061:
.size _Z4diffPfS_iiiS_, .-_Z4diffPfS_iiiS_
.globl _Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii
.type _Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii, @function
_Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii:
.LFB2087:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movq %rdi, 40(%rsp)
movq %rsi, 32(%rsp)
movq %rdx, 24(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
leaq 40(%rsp), %rax
movq %rax, 112(%rsp)
leaq 32(%rsp), %rax
movq %rax, 120(%rsp)
leaq 24(%rsp), %rax
movq %rax, 128(%rsp)
leaq 20(%rsp), %rax
movq %rax, 136(%rsp)
leaq 16(%rsp), %rax
movq %rax, 144(%rsp)
leaq 12(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L63
.L59:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L64
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L63:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 200
pushq 56(%rsp)
.cfi_def_cfa_offset 208
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z13matrixMultGPUPfS_S_iii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L59
.L64:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2087:
.size _Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii, .-_Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii
.globl _Z13matrixMultGPUPfS_S_iii
.type _Z13matrixMultGPUPfS_S_iii, @function
_Z13matrixMultGPUPfS_S_iii:
.LFB2088:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
call _Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2088:
.size _Z13matrixMultGPUPfS_S_iii, .-_Z13matrixMultGPUPfS_S_iii
.section .rodata.str1.1
.LC8:
.string "./exec hA hB/WA wB\n"
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC13:
.string "grid_x_size = %i, grid_y_size = %i\n"
.section .rodata.str1.1
.LC14:
.string "Time GPU=%f\n"
.section .rodata.str1.8
.align 8
.LC15:
.string "ERROR=GPU.vs.CPU matrix mult differs\n"
.align 8
.LC16:
.string "GPU.vs.CPU matrix is equal! :D\n"
.text
.globl main
.type main, @function
main:
.LFB2062:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movl %edi, %ebx
movq %rsi, %rbp
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $0, %esi
movq stdout(%rip), %rdi
call setbuf@PLT
cmpl $4, %ebx
jne .L79
movq 8(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r14
movl %eax, 20(%rsp)
movq 16(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %rbx
movl %eax, 16(%rsp)
movq 24(%rbp), %rdi
movl $10, %edx
movl $0, %esi
call __isoc23_strtol@PLT
movq %rax, %r13
movl %eax, 24(%rsp)
movl %ebx, %r12d
imull %eax, %r12d
movl %r14d, %ebp
imull %eax, %ebp
imull %r14d, %ebx
movslq %ebx, %rbx
salq $2, %rbx
movq %rbx, %rdi
call malloc@PLT
movq %rax, %r15
movss .LC9(%rip), %xmm0
movl 16(%rsp), %edx
movl 20(%rsp), %esi
movq %rax, %rdi
call _Z11init_matrixPfiif
movslq %r12d, %r12
salq $2, %r12
movq %r12, %rdi
call malloc@PLT
movq %rax, 8(%rsp)
movss .LC10(%rip), %xmm0
movl 24(%rsp), %edx
movl 16(%rsp), %esi
movq %rax, %rdi
call _Z11init_matrixPfiif
movq %r12, %rdi
call malloc@PLT
movq %rax, 24(%rsp)
testl %ebp, %ebp
jle .L69
movslq %ebp, %rdx
leaq (%rax,%rdx,4), %rdx
.L70:
movl $0x00000000, (%rax)
addq $4, %rax
cmpq %rdx, %rax
jne .L70
.L69:
leaq 40(%rsp), %rdi
movq %rbx, %rsi
call cudaMalloc@PLT
leaq 48(%rsp), %rdi
movq %r12, %rsi
call cudaMalloc@PLT
movslq %ebp, %rbp
salq $2, %rbp
leaq 56(%rsp), %rdi
movq %rbp, %rsi
call cudaMalloc@PLT
movl $1, %ecx
movq %rbx, %rdx
movq %r15, %rsi
movq 40(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %r12, %rdx
movq 8(%rsp), %rsi
movq 48(%rsp), %rdi
call cudaMemcpy@PLT
movl $1, %ecx
movq %rbp, %rdx
movq 24(%rsp), %rsi
movq 56(%rsp), %rdi
call cudaMemcpy@PLT
movl $16, 64(%rsp)
movl $16, 68(%rsp)
movl $1, 72(%rsp)
pxor %xmm0, %xmm0
cvtsi2ssl %r13d, %xmm0
mulss .LC11(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC17(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC12(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L71
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L71:
cvttss2sil %xmm3, %r12d
pxor %xmm0, %xmm0
cvtsi2ssl %r14d, %xmm0
mulss .LC11(%rip), %xmm0
movaps %xmm0, %xmm3
movss .LC17(%rip), %xmm2
movaps %xmm0, %xmm1
andps %xmm2, %xmm1
movss .LC12(%rip), %xmm4
ucomiss %xmm1, %xmm4
jbe .L72
cvttss2sil %xmm0, %eax
pxor %xmm1, %xmm1
cvtsi2ssl %eax, %xmm1
cmpnless %xmm1, %xmm3
movss .LC9(%rip), %xmm4
andps %xmm4, %xmm3
addss %xmm1, %xmm3
andnps %xmm0, %xmm2
orps %xmm2, %xmm3
.L72:
cvttss2sil %xmm3, %ebx
movl %ebx, %ecx
movl %r12d, %edx
leaq .LC13(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl %r12d, 76(%rsp)
movl %ebx, 80(%rsp)
movl $1, 84(%rsp)
call _Z5wtimev
movsd %xmm0, 24(%rsp)
movl 72(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 64(%rsp), %rdx
movq 76(%rsp), %rdi
movl 84(%rsp), %esi
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L80
.L73:
call cudaThreadSynchronize@PLT
call _Z5wtimev
subsd 24(%rsp), %xmm0
leaq .LC14(%rip), %rsi
movl $2, %edi
movl $1, %eax
call __printf_chk@PLT
movq %rbp, %rdi
call malloc@PLT
movq %rax, %rbx
movl $2, %ecx
movq %rbp, %rdx
movq 56(%rsp), %rsi
movq %rax, %rdi
call cudaMemcpy@PLT
movq %rbx, %r9
movl %r13d, %r8d
movl 16(%rsp), %ecx
movl 20(%rsp), %edx
movq 8(%rsp), %rsi
movq %r15, %rdi
call _Z4diffPfS_iiiS_
testl %eax, %eax
jne .L74
leaq .LC15(%rip), %rsi
movl $2, %edi
call __printf_chk@PLT
.L75:
movq %r15, %rdi
call free@PLT
movq 8(%rsp), %rdi
call free@PLT
movq %rbx, %rdi
call free@PLT
movq 40(%rsp), %rdi
call cudaFree@PLT
movq 48(%rsp), %rdi
call cudaFree@PLT
movq 56(%rsp), %rdi
call cudaFree@PLT
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L81
movl $1, %eax
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L79:
.cfi_restore_state
leaq .LC8(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
movl $-1, %edi
call exit@PLT
.L80:
movl %r13d, %r9d
movl %r14d, %r8d
movl 16(%rsp), %ecx
movq 56(%rsp), %rdx
movq 48(%rsp), %rsi
movq 40(%rsp), %rdi
call _Z40__device_stub__Z13matrixMultGPUPfS_S_iiiPfS_S_iii
jmp .L73
.L74:
leaq .LC16(%rip), %rsi
movl $2, %edi
movl $0, %eax
call __printf_chk@PLT
jmp .L75
.L81:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2062:
.size main, .-main
.section .rodata.str1.1
.LC18:
.string "_Z13matrixMultGPUPfS_S_iii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2090:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rdi
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC18(%rip), %rdx
movq %rdx, %rcx
leaq _Z13matrixMultGPUPfS_S_iii(%rip), %rsi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2090:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.local _ZZ5wtimevE3tv0
.comm _ZZ5wtimevE3tv0,16,16
.section .rodata.cst8,"aM",@progbits,8
.align 8
.LC0:
.long 0
.long 1093567616
.section .rodata.cst4,"aM",@progbits,4
.align 4
.LC2:
.long -1082130432
.section .rodata.cst16,"aM",@progbits,16
.align 16
.LC5:
.long 2147483647
.long 0
.long 0
.long 0
.section .rodata.cst8
.align 8
.LC6:
.long -1998362383
.long 1055193269
.section .rodata.cst4
.align 4
.LC9:
.long 1065353216
.align 4
.LC10:
.long 1073741824
.align 4
.LC11:
.long 1031798784
.align 4
.LC12:
.long 1258291200
.set .LC17,.LC5
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "main.hip"
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0 # -- Begin function _Z5wtimev
.LCPI0_0:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl _Z5wtimev
.p2align 4, 0x90
.type _Z5wtimev,@function
_Z5wtimev: # @_Z5wtimev
.cfi_startproc
# %bb.0:
pushq %rax
.cfi_def_cfa_offset 16
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
cvtsi2sd %rax, %xmm0
divsd .LCPI0_0(%rip), %xmm0
popq %rax
.cfi_def_cfa_offset 8
retq
.Lfunc_end0:
.size _Z5wtimev, .Lfunc_end0-_Z5wtimev
.cfi_endproc
# -- End function
.globl _Z12matrixMulCPUPfS_iiiS_ # -- Begin function _Z12matrixMulCPUPfS_iiiS_
.p2align 4, 0x90
.type _Z12matrixMulCPUPfS_iiiS_,@function
_Z12matrixMulCPUPfS_iiiS_: # @_Z12matrixMulCPUPfS_iiiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, -8(%rsp) # 8-byte Spill
movq %rsi, -16(%rsp) # 8-byte Spill
movq %rdi, -24(%rsp) # 8-byte Spill
testl %edx, %edx
jle .LBB1_9
# %bb.1: # %.preheader.lr.ph
movslq %r8d, %rdi
movl %edx, %edx
movl %edi, %r10d
movl %ecx, %r11d
leaq (,%rdi,4), %rbx
xorl %r14d, %r14d
xorl %r15d, %r15d
jmp .LBB1_2
.p2align 4, 0x90
.LBB1_8: # %._crit_edge31
# in Loop: Header=BB1_2 Depth=1
incq %r15
addl %ecx, %r14d
cmpq %rdx, %r15
je .LBB1_9
.LBB1_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB1_4 Depth 2
# Child Loop BB1_6 Depth 3
testl %r8d, %r8d
jle .LBB1_8
# %bb.3: # %.lr.ph30
# in Loop: Header=BB1_2 Depth=1
movl %r14d, %eax
movq -24(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %r12
movq %r15, %rax
imulq %rdi, %rax
movq -8(%rsp), %rsi # 8-byte Reload
leaq (%rsi,%rax,4), %r13
movq -16(%rsp), %rsi # 8-byte Reload
xorl %eax, %eax
jmp .LBB1_4
.p2align 4, 0x90
.LBB1_7: # %._crit_edge
# in Loop: Header=BB1_4 Depth=2
incq %rax
addq $4, %rsi
cmpq %r10, %rax
je .LBB1_8
.LBB1_4: # Parent Loop BB1_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB1_6 Depth 3
movl $0, (%r13,%rax,4)
testl %ecx, %ecx
jle .LBB1_7
# %bb.5: # %.lr.ph
# in Loop: Header=BB1_4 Depth=2
movss (%r13,%rax,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %rsi, %rbp
xorl %r9d, %r9d
.p2align 4, 0x90
.LBB1_6: # Parent Loop BB1_2 Depth=1
# Parent Loop BB1_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r12,%r9,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%rbp), %xmm1
addss %xmm1, %xmm0
movss %xmm0, (%r13,%rax,4)
incq %r9
addq %rbx, %rbp
cmpq %r9, %r11
jne .LBB1_6
jmp .LBB1_7
.LBB1_9: # %._crit_edge33
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z12matrixMulCPUPfS_iiiS_, .Lfunc_end1-_Z12matrixMulCPUPfS_iiiS_
.cfi_endproc
# -- End function
.globl _Z28__device_stub__matrixMultGPUPfS_S_iii # -- Begin function _Z28__device_stub__matrixMultGPUPfS_S_iii
.p2align 4, 0x90
.type _Z28__device_stub__matrixMultGPUPfS_S_iii,@function
_Z28__device_stub__matrixMultGPUPfS_S_iii: # @_Z28__device_stub__matrixMultGPUPfS_S_iii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 88(%rsp)
movq %rsi, 80(%rsp)
movq %rdx, 72(%rsp)
movl %ecx, 20(%rsp)
movl %r8d, 16(%rsp)
movl %r9d, 12(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 72(%rsp), %rax
movq %rax, 112(%rsp)
leaq 20(%rsp), %rax
movq %rax, 120(%rsp)
leaq 16(%rsp), %rax
movq %rax, 128(%rsp)
leaq 12(%rsp), %rax
movq %rax, 136(%rsp)
leaq 56(%rsp), %rdi
leaq 40(%rsp), %rsi
leaq 32(%rsp), %rdx
leaq 24(%rsp), %rcx
callq __hipPopCallConfiguration
movq 56(%rsp), %rsi
movl 64(%rsp), %edx
movq 40(%rsp), %rcx
movl 48(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z13matrixMultGPUPfS_S_iii, %edi
pushq 24(%rsp)
.cfi_adjust_cfa_offset 8
pushq 40(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z28__device_stub__matrixMultGPUPfS_S_iii, .Lfunc_end2-_Z28__device_stub__matrixMultGPUPfS_S_iii
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function _Z11init_matrixPfiif
.LCPI3_0:
.long 0xbf800000 # float -1
.text
.globl _Z11init_matrixPfiif
.p2align 4, 0x90
.type _Z11init_matrixPfiif,@function
_Z11init_matrixPfiif: # @_Z11init_matrixPfiif
.cfi_startproc
# %bb.0:
testl %esi, %esi
jle .LBB3_8
# %bb.1: # %.preheader.lr.ph
cvtsi2ss %edx, %xmm2
movl %esi, %eax
movl %edx, %ecx
xorl %esi, %esi
movss .LCPI3_0(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm2, %xmm1
xorl %r8d, %r8d
jmp .LBB3_2
.p2align 4, 0x90
.LBB3_7: # %._crit_edge
# in Loop: Header=BB3_2 Depth=1
incq %r8
addl %edx, %esi
cmpq %rax, %r8
je .LBB3_8
.LBB3_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB3_4 Depth 2
testl %edx, %edx
jle .LBB3_7
# %bb.3: # %.lr.ph
# in Loop: Header=BB3_2 Depth=1
movl %esi, %r9d
leaq (%rdi,%r9,4), %r9
xorl %r10d, %r10d
jmp .LBB3_4
.p2align 4, 0x90
.LBB3_6: # %select.end
# in Loop: Header=BB3_4 Depth=2
movss %xmm2, (%r9,%r10,4)
incq %r10
cmpq %r10, %rcx
je .LBB3_7
.LBB3_4: # Parent Loop BB3_2 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm2
cmpq %r10, %r8
je .LBB3_6
# %bb.5: # %select.false.sink
# in Loop: Header=BB3_4 Depth=2
movaps %xmm1, %xmm2
jmp .LBB3_6
.LBB3_8: # %._crit_edge21
retq
.Lfunc_end3:
.size _Z11init_matrixPfiif, .Lfunc_end3-_Z11init_matrixPfiif
.cfi_endproc
# -- End function
.globl _Z12print_matrixPfii # -- Begin function _Z12print_matrixPfii
.p2align 4, 0x90
.type _Z12print_matrixPfii,@function
_Z12print_matrixPfii: # @_Z12print_matrixPfii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $24, %rsp
.cfi_def_cfa_offset 80
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rdi, 8(%rsp) # 8-byte Spill
testl %esi, %esi
jle .LBB4_6
# %bb.1: # %.preheader.lr.ph
movl %edx, %ebx
movl %esi, %eax
movq %rax, 16(%rsp) # 8-byte Spill
movl %edx, %r12d
xorl %r13d, %r13d
xorl %ebp, %ebp
jmp .LBB4_2
.p2align 4, 0x90
.LBB4_5: # %._crit_edge
# in Loop: Header=BB4_2 Depth=1
movl $10, %edi
callq putchar@PLT
incq %rbp
addl %ebx, %r13d
cmpq 16(%rsp), %rbp # 8-byte Folded Reload
je .LBB4_6
.LBB4_2: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB4_4 Depth 2
testl %ebx, %ebx
jle .LBB4_5
# %bb.3: # %.lr.ph
# in Loop: Header=BB4_2 Depth=1
movl %r13d, %eax
movq 8(%rsp), %rcx # 8-byte Reload
leaq (%rcx,%rax,4), %r14
xorl %r15d, %r15d
.p2align 4, 0x90
.LBB4_4: # Parent Loop BB4_2 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r14,%r15,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
cvtss2sd %xmm0, %xmm0
movl $.L.str, %edi
movb $1, %al
callq printf
incq %r15
cmpq %r15, %r12
jne .LBB4_4
jmp .LBB4_5
.LBB4_6: # %._crit_edge13
addq $24, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end4:
.size _Z12print_matrixPfii, .Lfunc_end4-_Z12print_matrixPfii
.cfi_endproc
# -- End function
.section .rodata.cst16,"aM",@progbits,16
.p2align 4, 0x0 # -- Begin function _Z4diffPfS_iiiS_
.LCPI5_0:
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.long 0x7fffffff # float NaN
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI5_1:
.quad 0x3ee4f8b588e368f1 # double 1.0000000000000001E-5
.text
.globl _Z4diffPfS_iiiS_
.p2align 4, 0x90
.type _Z4diffPfS_iiiS_,@function
_Z4diffPfS_iiiS_: # @_Z4diffPfS_iiiS_
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $40, %rsp
.cfi_def_cfa_offset 96
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %r9, 16(%rsp) # 8-byte Spill
movl %r8d, %ebp
movl %ecx, %r15d
movl %edx, %ebx
movq %rsi, 32(%rsp) # 8-byte Spill
movq %rdi, 24(%rsp) # 8-byte Spill
movl %r8d, %eax
imull %edx, %eax
movslq %eax, %rdi
shlq $2, %rdi
callq malloc
movq %rax, 8(%rsp) # 8-byte Spill
movl %ebx, %edi
movl %ebp, %r8d
movl %ebx, 4(%rsp) # 4-byte Spill
testl %ebx, %ebx
jle .LBB5_10
# %bb.1: # %.preheader61.lr.ph
movslq %ebp, %rax
movl %r15d, %edx
leaq (,%rax,4), %rsi
xorl %r9d, %r9d
xorl %r10d, %r10d
jmp .LBB5_2
.p2align 4, 0x90
.LBB5_9: # %._crit_edge69
# in Loop: Header=BB5_2 Depth=1
incq %r10
addl %r15d, %r9d
cmpq %rdi, %r10
je .LBB5_10
.LBB5_2: # %.preheader61
# =>This Loop Header: Depth=1
# Child Loop BB5_4 Depth 2
# Child Loop BB5_6 Depth 3
testl %ebp, %ebp
jle .LBB5_9
# %bb.3: # %.lr.ph68
# in Loop: Header=BB5_2 Depth=1
movl %r9d, %ecx
movq 24(%rsp), %r11 # 8-byte Reload
leaq (%r11,%rcx,4), %r11
movq %r10, %rcx
imulq %rax, %rcx
movq 8(%rsp), %rbx # 8-byte Reload
leaq (%rbx,%rcx,4), %rbx
movq 32(%rsp), %r13 # 8-byte Reload
xorl %r14d, %r14d
jmp .LBB5_4
.p2align 4, 0x90
.LBB5_8: # in Loop: Header=BB5_4 Depth=2
incq %r14
addq $4, %r13
cmpq %r8, %r14
je .LBB5_9
.LBB5_4: # Parent Loop BB5_2 Depth=1
# => This Loop Header: Depth=2
# Child Loop BB5_6 Depth 3
movl $0, (%rbx,%r14,4)
testl %r15d, %r15d
jle .LBB5_8
# %bb.5: # %.lr.ph
# in Loop: Header=BB5_4 Depth=2
movss (%rbx,%r14,4), %xmm0 # xmm0 = mem[0],zero,zero,zero
movq %r13, %r12
xorl %ecx, %ecx
.p2align 4, 0x90
.LBB5_6: # Parent Loop BB5_2 Depth=1
# Parent Loop BB5_4 Depth=2
# => This Inner Loop Header: Depth=3
movss (%r11,%rcx,4), %xmm1 # xmm1 = mem[0],zero,zero,zero
mulss (%r12), %xmm1
addss %xmm1, %xmm0
incq %rcx
addq %rsi, %r12
cmpq %rcx, %rdx
jne .LBB5_6
# %bb.7: # %._crit_edge
# in Loop: Header=BB5_4 Depth=2
movss %xmm0, (%rbx,%r14,4)
jmp .LBB5_8
.LBB5_10: # %.preheader60
movl $1, %ecx
cmpl $0, 4(%rsp) # 4-byte Folded Reload
jle .LBB5_18
# %bb.11: # %.preheader.lr.ph
xorl %r9d, %r9d
movaps .LCPI5_0(%rip), %xmm0 # xmm0 = [NaN,NaN,NaN,NaN]
movsd .LCPI5_1(%rip), %xmm1 # xmm1 = mem[0],zero
xorl %esi, %esi
movq 16(%rsp), %rbx # 8-byte Reload
jmp .LBB5_12
.p2align 4, 0x90
.LBB5_17: # %._crit_edge73
# in Loop: Header=BB5_12 Depth=1
incq %rsi
addl %ebp, %r9d
cmpq %rdi, %rsi
je .LBB5_18
.LBB5_12: # %.preheader
# =>This Loop Header: Depth=1
# Child Loop BB5_14 Depth 2
testl %ebp, %ebp
jle .LBB5_17
# %bb.13: # %.lr.ph72
# in Loop: Header=BB5_12 Depth=1
movl %r9d, %eax
leaq (%rbx,%rax,4), %r10
movq 8(%rsp), %rdx # 8-byte Reload
leaq (%rdx,%rax,4), %r11
xorl %edx, %edx
.p2align 4, 0x90
.LBB5_14: # Parent Loop BB5_12 Depth=1
# => This Inner Loop Header: Depth=2
movss (%r11,%rdx,4), %xmm2 # xmm2 = mem[0],zero,zero,zero
movss (%r10,%rdx,4), %xmm3 # xmm3 = mem[0],zero,zero,zero
movaps %xmm2, %xmm4
subss %xmm3, %xmm4
andps %xmm0, %xmm4
cvtss2sd %xmm4, %xmm4
ucomisd %xmm1, %xmm4
ja .LBB5_15
# %bb.16: # in Loop: Header=BB5_14 Depth=2
incq %rdx
cmpq %rdx, %r8
jne .LBB5_14
jmp .LBB5_17
.LBB5_15:
xorps %xmm0, %xmm0
cvtss2sd %xmm2, %xmm0
xorps %xmm1, %xmm1
cvtss2sd %xmm3, %xmm1
movl $.L.str.2, %edi
# kill: def $esi killed $esi killed $rsi
# kill: def $edx killed $edx killed $rdx
movb $2, %al
callq printf
xorl %ecx, %ecx
.LBB5_18: # %.loopexit
movl %ecx, %eax
addq $40, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z4diffPfS_iiiS_, .Lfunc_end5-_Z4diffPfS_iiiS_
.cfi_endproc
# -- End function
.section .rodata.cst4,"aM",@progbits,4
.p2align 2, 0x0 # -- Begin function main
.LCPI6_0:
.long 0x3f800000 # float 1
.LCPI6_1:
.long 0xbf800000 # float -1
.LCPI6_2:
.long 0x40000000 # float 2
.LCPI6_3:
.long 0x3d800000 # float 0.0625
.section .rodata.cst8,"aM",@progbits,8
.p2align 3, 0x0
.LCPI6_4:
.quad 0x412e848000000000 # double 1.0E+6
.text
.globl main
.p2align 4, 0x90
.type main,@function
main: # @main
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $200, %rsp
.cfi_def_cfa_offset 256
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movq %rsi, %rbx
movl %edi, %ebp
movq stdout(%rip), %rdi
xorl %esi, %esi
callq setbuf
cmpl $4, %ebp
jne .LBB6_22
# %bb.1:
movq 8(%rbx), %rdi
xorl %r13d, %r13d
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %rbp
movq 16(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r14
movq 24(%rbx), %rdi
xorl %esi, %esi
movl $10, %edx
callq __isoc23_strtol
movq %rax, %r12
movl %ebp, %eax
imull %r14d, %eax
movslq %eax, %rdi
shlq $2, %rdi
movq %rdi, %r15
callq malloc
testl %ebp, %ebp
jle .LBB6_9
# %bb.2: # %.preheader.lr.ph.i
cvtsi2ss %r14d, %xmm2
movl %ebp, %r8d
movl %r14d, %ecx
movss .LCPI6_0(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI6_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm2, %xmm1
xorl %edx, %edx
jmp .LBB6_3
.p2align 4, 0x90
.LBB6_8: # %._crit_edge.i
# in Loop: Header=BB6_3 Depth=1
incq %rdx
addl %r14d, %r13d
cmpq %r8, %rdx
je .LBB6_9
.LBB6_3: # %.preheader.i
# =>This Loop Header: Depth=1
# Child Loop BB6_5 Depth 2
testl %r14d, %r14d
jle .LBB6_8
# %bb.4: # %.lr.ph.i
# in Loop: Header=BB6_3 Depth=1
movl %r13d, %esi
leaq (%rax,%rsi,4), %rsi
xorl %edi, %edi
jmp .LBB6_5
.p2align 4, 0x90
.LBB6_7: # %select.end
# in Loop: Header=BB6_5 Depth=2
movss %xmm2, (%rsi,%rdi,4)
incq %rdi
cmpq %rdi, %rcx
je .LBB6_8
.LBB6_5: # Parent Loop BB6_3 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm2
cmpq %rdi, %rdx
je .LBB6_7
# %bb.6: # %select.false.sink
# in Loop: Header=BB6_5 Depth=2
movaps %xmm1, %xmm2
jmp .LBB6_7
.LBB6_9: # %_Z11init_matrixPfiif.exit
movq %rax, 64(%rsp) # 8-byte Spill
movl %r12d, %ebx
movq %rbp, 24(%rsp) # 8-byte Spill
imull %ebp, %ebx
movl %r14d, %eax
imull %r12d, %eax
movslq %eax, %rbp
shlq $2, %rbp
movq %rbp, %rdi
callq malloc
movq %rax, %r13
cvtsi2ss %r12d, %xmm3
testl %r14d, %r14d
jle .LBB6_17
# %bb.10: # %.preheader.lr.ph.i67
movl %r14d, %eax
movl %r12d, %ecx
xorl %edx, %edx
movss .LCPI6_2(%rip), %xmm0 # xmm0 = mem[0],zero,zero,zero
movss .LCPI6_1(%rip), %xmm1 # xmm1 = mem[0],zero,zero,zero
divss %xmm3, %xmm1
xorl %esi, %esi
jmp .LBB6_11
.p2align 4, 0x90
.LBB6_16: # %._crit_edge.i71
# in Loop: Header=BB6_11 Depth=1
incq %rsi
addl %r12d, %edx
cmpq %rax, %rsi
je .LBB6_17
.LBB6_11: # %.preheader.i69
# =>This Loop Header: Depth=1
# Child Loop BB6_13 Depth 2
testl %r12d, %r12d
jle .LBB6_16
# %bb.12: # %.lr.ph.i74
# in Loop: Header=BB6_11 Depth=1
movl %edx, %edi
leaq (,%rdi,4), %rdi
addq %r13, %rdi
xorl %r8d, %r8d
jmp .LBB6_13
.p2align 4, 0x90
.LBB6_15: # %select.end98
# in Loop: Header=BB6_13 Depth=2
movss %xmm2, (%rdi,%r8,4)
incq %r8
cmpq %r8, %rcx
je .LBB6_16
.LBB6_13: # Parent Loop BB6_11 Depth=1
# => This Inner Loop Header: Depth=2
movaps %xmm0, %xmm2
cmpq %r8, %rsi
je .LBB6_15
# %bb.14: # %select.false.sink99
# in Loop: Header=BB6_13 Depth=2
movaps %xmm1, %xmm2
jmp .LBB6_15
.LBB6_17: # %_Z11init_matrixPfiif.exit79
movss %xmm3, 16(%rsp) # 4-byte Spill
movq %rbp, %rdi
callq malloc
movq %rax, (%rsp) # 8-byte Spill
testl %ebx, %ebx
jle .LBB6_19
# %bb.18: # %.lr.ph.preheader
movl %ebx, %edx
shlq $2, %rdx
movq (%rsp), %rdi # 8-byte Reload
xorl %esi, %esi
callq memset@PLT
.LBB6_19: # %._crit_edge
leaq 40(%rsp), %rdi
movq %r15, %rsi
callq hipMalloc
leaq 32(%rsp), %rdi
movq %rbp, %rsi
callq hipMalloc
movslq %ebx, %rbx
shlq $2, %rbx
leaq 8(%rsp), %rdi
movq %rbx, %rsi
callq hipMalloc
movq 40(%rsp), %rdi
movq 64(%rsp), %rsi # 8-byte Reload
movq %r15, %rdx
movl $1, %ecx
callq hipMemcpy
movq 32(%rsp), %rdi
movq %r13, %rsi
movq %rbp, %rdx
movl $1, %ecx
callq hipMemcpy
movq 8(%rsp), %rdi
movq (%rsp), %rsi # 8-byte Reload
movq %rbx, (%rsp) # 8-byte Spill
movq %rbx, %rdx
movl $1, %ecx
callq hipMemcpy
movss 16(%rsp), %xmm0 # 4-byte Reload
# xmm0 = mem[0],zero,zero,zero
mulss .LCPI6_3(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebp
xorps %xmm0, %xmm0
cvtsi2ssl 24(%rsp), %xmm0 # 4-byte Folded Reload
mulss .LCPI6_3(%rip), %xmm0
callq ceilf@PLT
cvttss2si %xmm0, %ebx
movl $.L.str.4, %edi
movl %ebp, %esi
movl %ebx, %edx
xorl %eax, %eax
callq printf
shlq $32, %rbx
orq %rbp, %rbx
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
movq _ZZ5wtimevE3tv0+8(%rip), %r15
movq _ZZ5wtimevE3tv0(%rip), %rbp
movabsq $68719476752, %rdx # imm = 0x1000000010
movq %rbx, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB6_21
# %bb.20:
movq 40(%rsp), %rax
movq 32(%rsp), %rcx
movq 8(%rsp), %rdx
movq %rax, 136(%rsp)
movq %rcx, 128(%rsp)
movq %rdx, 120(%rsp)
movl %r14d, 60(%rsp)
movq 24(%rsp), %rax # 8-byte Reload
movl %eax, 56(%rsp)
movl %r12d, 52(%rsp)
leaq 136(%rsp), %rax
movq %rax, 144(%rsp)
leaq 128(%rsp), %rax
movq %rax, 152(%rsp)
leaq 120(%rsp), %rax
movq %rax, 160(%rsp)
leaq 60(%rsp), %rax
movq %rax, 168(%rsp)
leaq 56(%rsp), %rax
movq %rax, 176(%rsp)
leaq 52(%rsp), %rax
movq %rax, 184(%rsp)
leaq 104(%rsp), %rdi
leaq 88(%rsp), %rsi
leaq 80(%rsp), %rdx
leaq 72(%rsp), %rcx
callq __hipPopCallConfiguration
movq 104(%rsp), %rsi
movl 112(%rsp), %edx
movq 88(%rsp), %rcx
movl 96(%rsp), %r8d
leaq 144(%rsp), %r9
movl $_Z13matrixMultGPUPfS_S_iii, %edi
pushq 72(%rsp)
.cfi_adjust_cfa_offset 8
pushq 88(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB6_21:
imulq $1000000, %rbp, %rax # imm = 0xF4240
addq %r15, %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_4(%rip), %xmm0
movsd %xmm0, 16(%rsp) # 8-byte Spill
callq hipDeviceSynchronize
movl $_ZZ5wtimevE3tv0, %edi
xorl %esi, %esi
callq gettimeofday
imulq $1000000, _ZZ5wtimevE3tv0(%rip), %rax # imm = 0xF4240
addq _ZZ5wtimevE3tv0+8(%rip), %rax
xorps %xmm0, %xmm0
cvtsi2sd %rax, %xmm0
divsd .LCPI6_4(%rip), %xmm0
subsd 16(%rsp), %xmm0 # 8-byte Folded Reload
movl $.L.str.5, %edi
movb $1, %al
callq printf
movq (%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
callq malloc
movq %rax, %rbp
movq 8(%rsp), %rsi
movq %rax, %rdi
movq %rbx, %rdx
movl $2, %ecx
callq hipMemcpy
movq 64(%rsp), %rbx # 8-byte Reload
movq %rbx, %rdi
movq %r13, %rsi
movq 24(%rsp), %rdx # 8-byte Reload
# kill: def $edx killed $edx killed $rdx
movl %r14d, %ecx
movl %r12d, %r8d
movq %rbp, %r9
callq _Z4diffPfS_iiiS_
testl %eax, %eax
movl $.Lstr, %eax
movl $.Lstr.1, %edi
cmoveq %rax, %rdi
callq puts@PLT
movq %rbx, %rdi
callq free
movq %r13, %rdi
callq free
movq %rbp, %rdi
callq free
movq 40(%rsp), %rdi
callq hipFree
movq 32(%rsp), %rdi
callq hipFree
movq 8(%rsp), %rdi
callq hipFree
movl $1, %eax
addq $200, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.LBB6_22:
.cfi_def_cfa_offset 256
movl $.Lstr.2, %edi
callq puts@PLT
movl $-1, %edi
callq exit
.Lfunc_end6:
.size main, .Lfunc_end6-main
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
subq $40, %rsp
.cfi_def_cfa_offset 48
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB7_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB7_2:
movq __hip_gpubin_handle(%rip), %rdi
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z13matrixMultGPUPfS_S_iii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $40, %rsp
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end7:
.size __hip_module_ctor, .Lfunc_end7-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB8_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB8_2:
retq
.Lfunc_end8:
.size __hip_module_dtor, .Lfunc_end8-__hip_module_dtor
.cfi_endproc
# -- End function
.type _ZZ5wtimevE3tv0,@object # @_ZZ5wtimevE3tv0
.local _ZZ5wtimevE3tv0
.comm _ZZ5wtimevE3tv0,16,8
.type _Z13matrixMultGPUPfS_S_iii,@object # @_Z13matrixMultGPUPfS_S_iii
.section .rodata,"a",@progbits
.globl _Z13matrixMultGPUPfS_S_iii
.p2align 3, 0x0
_Z13matrixMultGPUPfS_S_iii:
.quad _Z28__device_stub__matrixMultGPUPfS_S_iii
.size _Z13matrixMultGPUPfS_S_iii, 8
.type .L.str,@object # @.str
.section .rodata.str1.1,"aMS",@progbits,1
.L.str:
.asciz "%4.1f "
.size .L.str, 7
.type .L.str.2,@object # @.str.2
.L.str.2:
.asciz "[%i,%i]: %f!=%f\n"
.size .L.str.2, 17
.type .L.str.4,@object # @.str.4
.L.str.4:
.asciz "grid_x_size = %i, grid_y_size = %i\n"
.size .L.str.4, 36
.type .L.str.5,@object # @.str.5
.L.str.5:
.asciz "Time GPU=%f\n"
.size .L.str.5, 13
.type .L__unnamed_1,@object # @0
.L__unnamed_1:
.asciz "_Z13matrixMultGPUPfS_S_iii"
.size .L__unnamed_1, 27
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.type .Lstr,@object # @str
.section .rodata.str1.1,"aMS",@progbits,1
.Lstr:
.asciz "ERROR=GPU.vs.CPU matrix mult differs"
.size .Lstr, 37
.type .Lstr.1,@object # @str.1
.Lstr.1:
.asciz "GPU.vs.CPU matrix is equal! :D"
.size .Lstr.1, 31
.type .Lstr.2,@object # @str.2
.Lstr.2:
.asciz "./exec hA hB/WA wB"
.size .Lstr.2, 19
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z28__device_stub__matrixMultGPUPfS_S_iii
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _ZZ5wtimevE3tv0
.addrsig_sym _Z13matrixMultGPUPfS_S_iii
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting CUDA source code to CUDA host assembly. | //
// Created by saleh on 7/23/18.
//
#include <stdio.h>
#include <cuda_runtime_api.h>
#include <vector_types.h>
#define BLOCK_SIZE 256
// reduce sum over specific axis
__global__ void kernel_reduce_sum_3d_try01(const float * __restrict__ g_idata,
float * __restrict__ g_odata,
int dim0, int dim1, int dim2,
int overaxis0, int overaxis1,int overaxis2) {
// dim0, dim1, dim2 : TTT, TFF, FTF, FFT
if(overaxis0==1 && overaxis1==0 && overaxis2==0){ // TFF
/* Each thread handles 4 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 4
*
* */
// static shared memory
__shared__ float smem[BLOCK_SIZE*4];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid4 = 4 * threadIdx.x;
// global index
unsigned int idx4 = 4 * (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
float tmpSum1 = 0;
float tmpSum2 = 0;
float tmpSum3 = 0;
int offset = dim1*dim2;
int i=0;
for(i=0;i<dim0;i++){
if(idx4 + 0 <= offset) tmpSum0 += g_idata[idx4 + i*offset + 0];
if(idx4 + 1 <= offset) tmpSum1 += g_idata[idx4 + i*offset + 1];
if(idx4 + 2 <= offset) tmpSum2 += g_idata[idx4 + i*offset + 2];
if(idx4 + 3 <= offset) tmpSum3 += g_idata[idx4 + i*offset + 3];
}
if(idx4 + 0 <= offset) smem[tid4 + 0] = tmpSum0;
if(idx4 + 1 <= offset) smem[tid4 + 1] = tmpSum1;
if(idx4 + 2 <= offset) smem[tid4 + 2] = tmpSum2;
if(idx4 + 3 <= offset) smem[tid4 + 3] = tmpSum3;
__syncthreads();
unsigned int oindx = idx4;
if(idx4 + 0 <= offset) g_odata[oindx + 0] = smem[tid4 + 0];
if(idx4 + 1 <= offset) g_odata[oindx + 1] = smem[tid4 + 1];
if(idx4 + 2 <= offset) g_odata[oindx + 2] = smem[tid4 + 2];
if(idx4 + 3 <= offset) g_odata[oindx + 3] = smem[tid4 + 3];
}
}
void reduce_sum_3d_try01(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x / 4, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x / 4, 1);
dim3 grid_overdim2 ((dim0*dim1 + block.x - 1) / block.x / 4, 1);
dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);
kernel_reduce_sum_3d_try01 <<< grid, block >>> (
g_idata,
g_odata,
dim0, dim1, dim2,
overaxis0, overaxis1,overaxis2);
}
__global__ void kernel_reduce_sum_3d_try02(
const float* __restrict__ g_idata,
float* __restrict__ g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
if (overaxis0 == 0 && overaxis1 == 1 && overaxis2 == 0) { // FTF
/* Each thread handles 1 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 1
*
* */
// static shared memory
__shared__ float smem_store[BLOCK_SIZE];
//__shared__ float smem_load[BLOCK_SIZE];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid = threadIdx.x;
// global index
unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
unsigned int i = 0;
unsigned int src_index ;
unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);
//Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
int thrd_d0 = (idx) / (1*dim2);
int thrd_d2 = (idx - thrd_d0*dim2);
//Only for debugging kernel
//printf("tid: %03d \tidx: %03d\td0: %02d\td2: %02d\n",tid,idx,thrd_d0,thrd_d2);
//Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
for (i = 0; i < dim1; i++) {
src_index = thrd_d0*dim1*dim2 + i * dim2 + thrd_d2;
printf("idx: %d : src_index: %d\n",idx,src_index);
if(src_index < _limit)
tmpSum0 += g_idata[src_index];
}
if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
__syncthreads();
unsigned int oindx = (unsigned int)( thrd_d0*dim2 + thrd_d2 );
if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];
}
else
{
if (overaxis0 == 0 && overaxis1 == 0 && overaxis2 == 1) { // FFT
/* Each thread handles 1 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 1
*
* */
// static shared memory
__shared__ float smem_store[BLOCK_SIZE];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid = threadIdx.x;
// global index
unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
unsigned int i = 0;
unsigned int src_index ;
unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);
//Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
int thrd_d0 = (idx) / (dim1*1);
int thrd_d1 = (idx - thrd_d0*dim1);
//Only for debugging kernel
printf("tid: %03d \tidx: %03d\td0: %02d\td1: %02d\n",tid,idx,thrd_d0,thrd_d1);
//Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
for (i = 0; i < dim2; i++) {
src_index = thrd_d0*dim1*dim2 + thrd_d1 * dim2 + i;
if(idx<15) printf("idx: %d : src_index: %d\n",idx,src_index);
if(src_index < _limit)
tmpSum0 += g_idata[src_index];
}
if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
__syncthreads();
unsigned int oindx = (unsigned int)( thrd_d0*dim1 + thrd_d1 );
if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];
}
}
}
void reduce_sum_3d_try02(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim2 ((dim0*dim1 + block.x - 1) / block.x, 1);
dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);
kernel_reduce_sum_3d_try02 <<< grid, block >>> (
g_idata,
g_odata,
dim0, dim1, dim2,
overaxis0, overaxis1,overaxis2);
}
__global__ void kernel_reduce_sum_3d_try03(
const float * __restrict__ g_idata,
float * __restrict__ g_odata,
const unsigned int dim0,
const unsigned int dim1,
const unsigned int dim2,
const bool overaxis0,
const bool overaxis1,
const bool overaxis2)
{
// WANING : dim0 means dim2 and dim2 means dim0
__shared__ float sm[BLOCK_SIZE];
if (overaxis2 && !overaxis1 && !overaxis0)
{
// Case 1 - sums in X-direction
// each threadblock is responsible for a separate row sum
unsigned int bidx = blockIdx.x;
unsigned int tidx = threadIdx.x;
sm[threadIdx.x] = 0;
while (tidx < dim0)
{
sm[threadIdx.x] += g_idata[bidx*dim0+tidx];
/*if(bidx==21){
//dbg
printf("thid: %04d\tg_index_to_read:%d\n",threadIdx.x,bidx*dim0+tidx);
}*/
tidx += blockDim.x;
} // block-stride loop
__syncthreads();
// parallel reduction
for (int i = blockDim.x>>1; i > 0; i>>=1)
{
if (threadIdx.x < i) sm[threadIdx.x] += sm[threadIdx.x + i];
__syncthreads();
}
if (!threadIdx.x) g_odata[bidx] = sm[0];
}
else if (!overaxis2 && overaxis1 && !overaxis0)
{
// Case 2 - sums in Y-direction
// each thread is responsible for a separate Y-column sum
unsigned int idx = threadIdx.x+blockDim.x*blockIdx.x;
if (idx < (dim0*dim2))
{
unsigned int tidx = idx%dim0 + (idx/dim0)*(dim0*dim1); //indices over input tensor (begining of axis1 slices)
float tsum = 0;
for (unsigned int i = 0; i < dim1; i++)
{
//printf("idx: %03d \t\t tidx: %03d\n",idx,tidx);
tsum += g_idata[tidx];
tidx += dim0;
}
g_odata[idx] = tsum;
}
}
else if (!overaxis2 && !overaxis1 && overaxis0)
{
// Case 3 - sums in Z-direction
// each thread is responsible for a separate Z-column sum
unsigned int idx = threadIdx.x + blockDim.x*blockIdx.x;
//printf("%d,%d,%d\n",dbg_blockid,dbg_thid,idx);
if (idx < (dim0*dim1))
{
unsigned int tidx = idx;
float tsum = 0;
for (int i = 0; i < dim2; i++)
{
//printf("%d,%d,%d,%d,%d\n",dbg_blockid,dbg_thid,idx,tidx,i);
//printf("idx:%02d, tidx:%02d, i=%02d\n",idx,tidx,i);
tsum += g_idata[tidx];
tidx += dim0*dim1;
}
g_odata[idx] = tsum;
}
}
else {
printf("reduce_sum: ERROR-NOTIMPLEMENTED\n");
}
}
void reduce_sum_3d_try03(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
bool overaxis0,
bool overaxis1,
bool overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim2 (dim0*dim1 , 1);
dim3 grid = overaxis0 ? (grid_overdim0) : (overaxis1 ? grid_overdim1 : grid_overdim2);
//printf("-------------------------------------------------------\n");
//printf("KERNEL_GRID : %d\n", grid.x);
//printf("KERNEL_BLOCK : %d\n", block.x);
kernel_reduce_sum_3d_try03 <<<grid, block>>> (
g_idata, g_odata,
dim2, dim1, dim0,
overaxis0, overaxis1,overaxis2);
} | .file "tmpxft_0017dcad_00000000-6_reduce_sum_3d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
.type _Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii, @function
_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii, .-_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
.globl _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
.type _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, @function
_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, .-_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
.globl _Z19reduce_sum_3d_try01PfS_iiiiii
.type _Z19reduce_sum_3d_try01PfS_iiiiii, @function
_Z19reduce_sum_3d_try01PfS_iiiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r14
movq %rsi, %r15
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
movl %r9d, %r13d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl %ecx, %eax
imull %r8d, %eax
addl $255, %eax
shrl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl %r8d, %eax
imull %edx, %eax
addl $255, %eax
shrl $10, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %ecx, %eax
imull %edx, %eax
addl $255, %eax
shrl $10, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
leaq 24(%rsp), %rax
cmpl $1, %r9d
je .L12
leaq 36(%rsp), %rdx
leaq 48(%rsp), %rax
cmpl $1, 144(%rsp)
cmove %rdx, %rax
.L12:
movq (%rax), %rdi
movq %rdi, 60(%rsp)
movl 8(%rax), %esi
movl $256, 12(%rsp)
movl 20(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
movl %r13d, %r9d
movl %r12d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq %r15, %rsi
movq %r14, %rdi
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z19reduce_sum_3d_try01PfS_iiiiii, .-_Z19reduce_sum_3d_try01PfS_iiiiii
.globl _Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
.type _Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii, @function
_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii, .-_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
.globl _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
.type _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, @function
_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, .-_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
.globl _Z19reduce_sum_3d_try02PfS_iiiiii
.type _Z19reduce_sum_3d_try02PfS_iiiiii, @function
_Z19reduce_sum_3d_try02PfS_iiiiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r14
movq %rsi, %r15
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
movl %r9d, %r13d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl %ecx, %eax
imull %r8d, %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl %r8d, %eax
imull %edx, %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %ecx, %eax
imull %edx, %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
leaq 24(%rsp), %rax
cmpl $1, %r9d
je .L29
leaq 36(%rsp), %rdx
leaq 48(%rsp), %rax
cmpl $1, 144(%rsp)
cmove %rdx, %rax
.L29:
movq (%rax), %rdi
movq %rdi, 60(%rsp)
movl 8(%rax), %esi
movl $256, 12(%rsp)
movl 20(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L28:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
movl %r13d, %r9d
movl %r12d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq %r15, %rsi
movq %r14, %rdi
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L28
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z19reduce_sum_3d_try02PfS_iiiiii, .-_Z19reduce_sum_3d_try02PfS_iiiiii
.globl _Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
.type _Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb, @function
_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb:
.LFB2088:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movb %r9b, 16(%rsp)
movl 208(%rsp), %eax
movb %al, 12(%rsp)
movl 216(%rsp), %eax
movb %al, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rdi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb, .-_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
.globl _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
.type _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, @function
_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movzbl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movzbl %r9b, %r9d
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, .-_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
.globl _Z19reduce_sum_3d_try03PfS_iiibbb
.type _Z19reduce_sum_3d_try03PfS_iiibbb, @function
_Z19reduce_sum_3d_try03PfS_iiibbb:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movl %edx, %r12d
movl %ecx, %ebp
movl %r8d, %ebx
movl %r9d, %r13d
movl 160(%rsp), %r14d
movl 168(%rsp), %r15d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ecx, %eax
imull %r8d, %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl %r8d, %eax
imull %edx, %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ecx, %eax
imull %edx, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
leaq 40(%rsp), %rax
testb %r9b, %r9b
jne .L46
leaq 52(%rsp), %rdx
leaq 64(%rsp), %rax
testb %r14b, %r14b
cmovne %rdx, %rax
.L46:
movq (%rax), %rdi
movq %rdi, 76(%rsp)
movl 8(%rax), %esi
movl $256, 28(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L45:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movzbl %r15b, %r15d
pushq %r15
.cfi_def_cfa_offset 168
movzbl %r14b, %r14d
pushq %r14
.cfi_def_cfa_offset 176
movzbl %r13b, %r9d
movl %r12d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z19reduce_sum_3d_try03PfS_iiibbb, .-_Z19reduce_sum_3d_try03PfS_iiibbb
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb"
.align 8
.LC1:
.string "_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii"
.align 8
.LC2:
.string "_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: |
You are a helpful coding assistant specialized in converting CUDA source code to HIP/AMD source code. | //
// Created by saleh on 7/23/18.
//
#include <stdio.h>
#include <cuda_runtime_api.h>
#include <vector_types.h>
#define BLOCK_SIZE 256
// reduce sum over specific axis
__global__ void kernel_reduce_sum_3d_try01(const float * __restrict__ g_idata,
float * __restrict__ g_odata,
int dim0, int dim1, int dim2,
int overaxis0, int overaxis1,int overaxis2) {
// dim0, dim1, dim2 : TTT, TFF, FTF, FFT
if(overaxis0==1 && overaxis1==0 && overaxis2==0){ // TFF
/* Each thread handles 4 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 4
*
* */
// static shared memory
__shared__ float smem[BLOCK_SIZE*4];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid4 = 4 * threadIdx.x;
// global index
unsigned int idx4 = 4 * (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
float tmpSum1 = 0;
float tmpSum2 = 0;
float tmpSum3 = 0;
int offset = dim1*dim2;
int i=0;
for(i=0;i<dim0;i++){
if(idx4 + 0 <= offset) tmpSum0 += g_idata[idx4 + i*offset + 0];
if(idx4 + 1 <= offset) tmpSum1 += g_idata[idx4 + i*offset + 1];
if(idx4 + 2 <= offset) tmpSum2 += g_idata[idx4 + i*offset + 2];
if(idx4 + 3 <= offset) tmpSum3 += g_idata[idx4 + i*offset + 3];
}
if(idx4 + 0 <= offset) smem[tid4 + 0] = tmpSum0;
if(idx4 + 1 <= offset) smem[tid4 + 1] = tmpSum1;
if(idx4 + 2 <= offset) smem[tid4 + 2] = tmpSum2;
if(idx4 + 3 <= offset) smem[tid4 + 3] = tmpSum3;
__syncthreads();
unsigned int oindx = idx4;
if(idx4 + 0 <= offset) g_odata[oindx + 0] = smem[tid4 + 0];
if(idx4 + 1 <= offset) g_odata[oindx + 1] = smem[tid4 + 1];
if(idx4 + 2 <= offset) g_odata[oindx + 2] = smem[tid4 + 2];
if(idx4 + 3 <= offset) g_odata[oindx + 3] = smem[tid4 + 3];
}
}
void reduce_sum_3d_try01(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x / 4, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x / 4, 1);
dim3 grid_overdim2 ((dim0*dim1 + block.x - 1) / block.x / 4, 1);
dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);
kernel_reduce_sum_3d_try01 <<< grid, block >>> (
g_idata,
g_odata,
dim0, dim1, dim2,
overaxis0, overaxis1,overaxis2);
}
__global__ void kernel_reduce_sum_3d_try02(
const float* __restrict__ g_idata,
float* __restrict__ g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
if (overaxis0 == 0 && overaxis1 == 1 && overaxis2 == 0) { // FTF
/* Each thread handles 1 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 1
*
* */
// static shared memory
__shared__ float smem_store[BLOCK_SIZE];
//__shared__ float smem_load[BLOCK_SIZE];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid = threadIdx.x;
// global index
unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
unsigned int i = 0;
unsigned int src_index ;
unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);
//Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
int thrd_d0 = (idx) / (1*dim2);
int thrd_d2 = (idx - thrd_d0*dim2);
//Only for debugging kernel
//printf("tid: %03d \tidx: %03d\td0: %02d\td2: %02d\n",tid,idx,thrd_d0,thrd_d2);
//Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
for (i = 0; i < dim1; i++) {
src_index = thrd_d0*dim1*dim2 + i * dim2 + thrd_d2;
printf("idx: %d : src_index: %d\n",idx,src_index);
if(src_index < _limit)
tmpSum0 += g_idata[src_index];
}
if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
__syncthreads();
unsigned int oindx = (unsigned int)( thrd_d0*dim2 + thrd_d2 );
if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];
}
else
{
if (overaxis0 == 0 && overaxis1 == 0 && overaxis2 == 1) { // FFT
/* Each thread handles 1 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 1
*
* */
// static shared memory
__shared__ float smem_store[BLOCK_SIZE];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid = threadIdx.x;
// global index
unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
unsigned int i = 0;
unsigned int src_index ;
unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);
//Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
int thrd_d0 = (idx) / (dim1*1);
int thrd_d1 = (idx - thrd_d0*dim1);
//Only for debugging kernel
printf("tid: %03d \tidx: %03d\td0: %02d\td1: %02d\n",tid,idx,thrd_d0,thrd_d1);
//Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
for (i = 0; i < dim2; i++) {
src_index = thrd_d0*dim1*dim2 + thrd_d1 * dim2 + i;
if(idx<15) printf("idx: %d : src_index: %d\n",idx,src_index);
if(src_index < _limit)
tmpSum0 += g_idata[src_index];
}
if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
__syncthreads();
unsigned int oindx = (unsigned int)( thrd_d0*dim1 + thrd_d1 );
if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];
}
}
}
void reduce_sum_3d_try02(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim2 ((dim0*dim1 + block.x - 1) / block.x, 1);
dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);
kernel_reduce_sum_3d_try02 <<< grid, block >>> (
g_idata,
g_odata,
dim0, dim1, dim2,
overaxis0, overaxis1,overaxis2);
}
__global__ void kernel_reduce_sum_3d_try03(
const float * __restrict__ g_idata,
float * __restrict__ g_odata,
const unsigned int dim0,
const unsigned int dim1,
const unsigned int dim2,
const bool overaxis0,
const bool overaxis1,
const bool overaxis2)
{
// WANING : dim0 means dim2 and dim2 means dim0
__shared__ float sm[BLOCK_SIZE];
if (overaxis2 && !overaxis1 && !overaxis0)
{
// Case 1 - sums in X-direction
// each threadblock is responsible for a separate row sum
unsigned int bidx = blockIdx.x;
unsigned int tidx = threadIdx.x;
sm[threadIdx.x] = 0;
while (tidx < dim0)
{
sm[threadIdx.x] += g_idata[bidx*dim0+tidx];
/*if(bidx==21){
//dbg
printf("thid: %04d\tg_index_to_read:%d\n",threadIdx.x,bidx*dim0+tidx);
}*/
tidx += blockDim.x;
} // block-stride loop
__syncthreads();
// parallel reduction
for (int i = blockDim.x>>1; i > 0; i>>=1)
{
if (threadIdx.x < i) sm[threadIdx.x] += sm[threadIdx.x + i];
__syncthreads();
}
if (!threadIdx.x) g_odata[bidx] = sm[0];
}
else if (!overaxis2 && overaxis1 && !overaxis0)
{
// Case 2 - sums in Y-direction
// each thread is responsible for a separate Y-column sum
unsigned int idx = threadIdx.x+blockDim.x*blockIdx.x;
if (idx < (dim0*dim2))
{
unsigned int tidx = idx%dim0 + (idx/dim0)*(dim0*dim1); //indices over input tensor (begining of axis1 slices)
float tsum = 0;
for (unsigned int i = 0; i < dim1; i++)
{
//printf("idx: %03d \t\t tidx: %03d\n",idx,tidx);
tsum += g_idata[tidx];
tidx += dim0;
}
g_odata[idx] = tsum;
}
}
else if (!overaxis2 && !overaxis1 && overaxis0)
{
// Case 3 - sums in Z-direction
// each thread is responsible for a separate Z-column sum
unsigned int idx = threadIdx.x + blockDim.x*blockIdx.x;
//printf("%d,%d,%d\n",dbg_blockid,dbg_thid,idx);
if (idx < (dim0*dim1))
{
unsigned int tidx = idx;
float tsum = 0;
for (int i = 0; i < dim2; i++)
{
//printf("%d,%d,%d,%d,%d\n",dbg_blockid,dbg_thid,idx,tidx,i);
//printf("idx:%02d, tidx:%02d, i=%02d\n",idx,tidx,i);
tsum += g_idata[tidx];
tidx += dim0*dim1;
}
g_odata[idx] = tsum;
}
}
else {
printf("reduce_sum: ERROR-NOTIMPLEMENTED\n");
}
}
void reduce_sum_3d_try03(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
bool overaxis0,
bool overaxis1,
bool overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim2 (dim0*dim1 , 1);
dim3 grid = overaxis0 ? (grid_overdim0) : (overaxis1 ? grid_overdim1 : grid_overdim2);
//printf("-------------------------------------------------------\n");
//printf("KERNEL_GRID : %d\n", grid.x);
//printf("KERNEL_BLOCK : %d\n", block.x);
kernel_reduce_sum_3d_try03 <<<grid, block>>> (
g_idata, g_odata,
dim2, dim1, dim0,
overaxis0, overaxis1,overaxis2);
} | //
// Created by saleh on 7/23/18.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <hip/hip_vector_types.h>
#define BLOCK_SIZE 256
// reduce sum over specific axis
__global__ void kernel_reduce_sum_3d_try01(const float * __restrict__ g_idata,
float * __restrict__ g_odata,
int dim0, int dim1, int dim2,
int overaxis0, int overaxis1,int overaxis2) {
// dim0, dim1, dim2 : TTT, TFF, FTF, FFT
if(overaxis0==1 && overaxis1==0 && overaxis2==0){ // TFF
/* Each thread handles 4 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 4
*
* */
// static shared memory
__shared__ float smem[BLOCK_SIZE*4];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid4 = 4 * threadIdx.x;
// global index
unsigned int idx4 = 4 * (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
float tmpSum1 = 0;
float tmpSum2 = 0;
float tmpSum3 = 0;
int offset = dim1*dim2;
int i=0;
for(i=0;i<dim0;i++){
if(idx4 + 0 <= offset) tmpSum0 += g_idata[idx4 + i*offset + 0];
if(idx4 + 1 <= offset) tmpSum1 += g_idata[idx4 + i*offset + 1];
if(idx4 + 2 <= offset) tmpSum2 += g_idata[idx4 + i*offset + 2];
if(idx4 + 3 <= offset) tmpSum3 += g_idata[idx4 + i*offset + 3];
}
if(idx4 + 0 <= offset) smem[tid4 + 0] = tmpSum0;
if(idx4 + 1 <= offset) smem[tid4 + 1] = tmpSum1;
if(idx4 + 2 <= offset) smem[tid4 + 2] = tmpSum2;
if(idx4 + 3 <= offset) smem[tid4 + 3] = tmpSum3;
__syncthreads();
unsigned int oindx = idx4;
if(idx4 + 0 <= offset) g_odata[oindx + 0] = smem[tid4 + 0];
if(idx4 + 1 <= offset) g_odata[oindx + 1] = smem[tid4 + 1];
if(idx4 + 2 <= offset) g_odata[oindx + 2] = smem[tid4 + 2];
if(idx4 + 3 <= offset) g_odata[oindx + 3] = smem[tid4 + 3];
}
}
void reduce_sum_3d_try01(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x / 4, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x / 4, 1);
dim3 grid_overdim2 ((dim0*dim1 + block.x - 1) / block.x / 4, 1);
dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);
kernel_reduce_sum_3d_try01 <<< grid, block >>> (
g_idata,
g_odata,
dim0, dim1, dim2,
overaxis0, overaxis1,overaxis2);
}
__global__ void kernel_reduce_sum_3d_try02(
const float* __restrict__ g_idata,
float* __restrict__ g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
if (overaxis0 == 0 && overaxis1 == 1 && overaxis2 == 0) { // FTF
/* Each thread handles 1 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 1
*
* */
// static shared memory
__shared__ float smem_store[BLOCK_SIZE];
//__shared__ float smem_load[BLOCK_SIZE];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid = threadIdx.x;
// global index
unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
unsigned int i = 0;
unsigned int src_index ;
unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);
//Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
int thrd_d0 = (idx) / (1*dim2);
int thrd_d2 = (idx - thrd_d0*dim2);
//Only for debugging kernel
//printf("tid: %03d \tidx: %03d\td0: %02d\td2: %02d\n",tid,idx,thrd_d0,thrd_d2);
//Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
for (i = 0; i < dim1; i++) {
src_index = thrd_d0*dim1*dim2 + i * dim2 + thrd_d2;
printf("idx: %d : src_index: %d\n",idx,src_index);
if(src_index < _limit)
tmpSum0 += g_idata[src_index];
}
if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
__syncthreads();
unsigned int oindx = (unsigned int)( thrd_d0*dim2 + thrd_d2 );
if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];
}
else
{
if (overaxis0 == 0 && overaxis1 == 0 && overaxis2 == 1) { // FFT
/* Each thread handles 1 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 1
*
* */
// static shared memory
__shared__ float smem_store[BLOCK_SIZE];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid = threadIdx.x;
// global index
unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
unsigned int i = 0;
unsigned int src_index ;
unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);
//Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
int thrd_d0 = (idx) / (dim1*1);
int thrd_d1 = (idx - thrd_d0*dim1);
//Only for debugging kernel
printf("tid: %03d \tidx: %03d\td0: %02d\td1: %02d\n",tid,idx,thrd_d0,thrd_d1);
//Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
for (i = 0; i < dim2; i++) {
src_index = thrd_d0*dim1*dim2 + thrd_d1 * dim2 + i;
if(idx<15) printf("idx: %d : src_index: %d\n",idx,src_index);
if(src_index < _limit)
tmpSum0 += g_idata[src_index];
}
if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
__syncthreads();
unsigned int oindx = (unsigned int)( thrd_d0*dim1 + thrd_d1 );
if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];
}
}
}
void reduce_sum_3d_try02(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim2 ((dim0*dim1 + block.x - 1) / block.x, 1);
dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);
kernel_reduce_sum_3d_try02 <<< grid, block >>> (
g_idata,
g_odata,
dim0, dim1, dim2,
overaxis0, overaxis1,overaxis2);
}
__global__ void kernel_reduce_sum_3d_try03(
const float * __restrict__ g_idata,
float * __restrict__ g_odata,
const unsigned int dim0,
const unsigned int dim1,
const unsigned int dim2,
const bool overaxis0,
const bool overaxis1,
const bool overaxis2)
{
// WANING : dim0 means dim2 and dim2 means dim0
__shared__ float sm[BLOCK_SIZE];
if (overaxis2 && !overaxis1 && !overaxis0)
{
// Case 1 - sums in X-direction
// each threadblock is responsible for a separate row sum
unsigned int bidx = blockIdx.x;
unsigned int tidx = threadIdx.x;
sm[threadIdx.x] = 0;
while (tidx < dim0)
{
sm[threadIdx.x] += g_idata[bidx*dim0+tidx];
/*if(bidx==21){
//dbg
printf("thid: %04d\tg_index_to_read:%d\n",threadIdx.x,bidx*dim0+tidx);
}*/
tidx += blockDim.x;
} // block-stride loop
__syncthreads();
// parallel reduction
for (int i = blockDim.x>>1; i > 0; i>>=1)
{
if (threadIdx.x < i) sm[threadIdx.x] += sm[threadIdx.x + i];
__syncthreads();
}
if (!threadIdx.x) g_odata[bidx] = sm[0];
}
else if (!overaxis2 && overaxis1 && !overaxis0)
{
// Case 2 - sums in Y-direction
// each thread is responsible for a separate Y-column sum
unsigned int idx = threadIdx.x+blockDim.x*blockIdx.x;
if (idx < (dim0*dim2))
{
unsigned int tidx = idx%dim0 + (idx/dim0)*(dim0*dim1); //indices over input tensor (begining of axis1 slices)
float tsum = 0;
for (unsigned int i = 0; i < dim1; i++)
{
//printf("idx: %03d \t\t tidx: %03d\n",idx,tidx);
tsum += g_idata[tidx];
tidx += dim0;
}
g_odata[idx] = tsum;
}
}
else if (!overaxis2 && !overaxis1 && overaxis0)
{
// Case 3 - sums in Z-direction
// each thread is responsible for a separate Z-column sum
unsigned int idx = threadIdx.x + blockDim.x*blockIdx.x;
//printf("%d,%d,%d\n",dbg_blockid,dbg_thid,idx);
if (idx < (dim0*dim1))
{
unsigned int tidx = idx;
float tsum = 0;
for (int i = 0; i < dim2; i++)
{
//printf("%d,%d,%d,%d,%d\n",dbg_blockid,dbg_thid,idx,tidx,i);
//printf("idx:%02d, tidx:%02d, i=%02d\n",idx,tidx,i);
tsum += g_idata[tidx];
tidx += dim0*dim1;
}
g_odata[idx] = tsum;
}
}
else {
printf("reduce_sum: ERROR-NOTIMPLEMENTED\n");
}
}
void reduce_sum_3d_try03(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
bool overaxis0,
bool overaxis1,
bool overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim2 (dim0*dim1 , 1);
dim3 grid = overaxis0 ? (grid_overdim0) : (overaxis1 ? grid_overdim1 : grid_overdim2);
//printf("-------------------------------------------------------\n");
//printf("KERNEL_GRID : %d\n", grid.x);
//printf("KERNEL_BLOCK : %d\n", block.x);
kernel_reduce_sum_3d_try03 <<<grid, block>>> (
g_idata, g_odata,
dim2, dim1, dim0,
overaxis0, overaxis1,overaxis2);
} |
You are a helpful coding assistant specialized in converting HIP source code to AMD host assembly. | //
// Created by saleh on 7/23/18.
//
#include <hip/hip_runtime.h>
#include <stdio.h>
#include <hip/hip_runtime_api.h>
#include <hip/hip_vector_types.h>
#define BLOCK_SIZE 256
// reduce sum over specific axis
__global__ void kernel_reduce_sum_3d_try01(const float * __restrict__ g_idata,
float * __restrict__ g_odata,
int dim0, int dim1, int dim2,
int overaxis0, int overaxis1,int overaxis2) {
// dim0, dim1, dim2 : TTT, TFF, FTF, FFT
if(overaxis0==1 && overaxis1==0 && overaxis2==0){ // TFF
/* Each thread handles 4 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 4
*
* */
// static shared memory
__shared__ float smem[BLOCK_SIZE*4];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid4 = 4 * threadIdx.x;
// global index
unsigned int idx4 = 4 * (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
float tmpSum1 = 0;
float tmpSum2 = 0;
float tmpSum3 = 0;
int offset = dim1*dim2;
int i=0;
for(i=0;i<dim0;i++){
if(idx4 + 0 <= offset) tmpSum0 += g_idata[idx4 + i*offset + 0];
if(idx4 + 1 <= offset) tmpSum1 += g_idata[idx4 + i*offset + 1];
if(idx4 + 2 <= offset) tmpSum2 += g_idata[idx4 + i*offset + 2];
if(idx4 + 3 <= offset) tmpSum3 += g_idata[idx4 + i*offset + 3];
}
if(idx4 + 0 <= offset) smem[tid4 + 0] = tmpSum0;
if(idx4 + 1 <= offset) smem[tid4 + 1] = tmpSum1;
if(idx4 + 2 <= offset) smem[tid4 + 2] = tmpSum2;
if(idx4 + 3 <= offset) smem[tid4 + 3] = tmpSum3;
__syncthreads();
unsigned int oindx = idx4;
if(idx4 + 0 <= offset) g_odata[oindx + 0] = smem[tid4 + 0];
if(idx4 + 1 <= offset) g_odata[oindx + 1] = smem[tid4 + 1];
if(idx4 + 2 <= offset) g_odata[oindx + 2] = smem[tid4 + 2];
if(idx4 + 3 <= offset) g_odata[oindx + 3] = smem[tid4 + 3];
}
}
void reduce_sum_3d_try01(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x / 4, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x / 4, 1);
dim3 grid_overdim2 ((dim0*dim1 + block.x - 1) / block.x / 4, 1);
dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);
kernel_reduce_sum_3d_try01 <<< grid, block >>> (
g_idata,
g_odata,
dim0, dim1, dim2,
overaxis0, overaxis1,overaxis2);
}
__global__ void kernel_reduce_sum_3d_try02(
const float* __restrict__ g_idata,
float* __restrict__ g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
if (overaxis0 == 0 && overaxis1 == 1 && overaxis2 == 0) { // FTF
/* Each thread handles 1 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 1
*
* */
// static shared memory
__shared__ float smem_store[BLOCK_SIZE];
//__shared__ float smem_load[BLOCK_SIZE];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid = threadIdx.x;
// global index
unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
unsigned int i = 0;
unsigned int src_index ;
unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);
//Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
int thrd_d0 = (idx) / (1*dim2);
int thrd_d2 = (idx - thrd_d0*dim2);
//Only for debugging kernel
//printf("tid: %03d \tidx: %03d\td0: %02d\td2: %02d\n",tid,idx,thrd_d0,thrd_d2);
//Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
for (i = 0; i < dim1; i++) {
src_index = thrd_d0*dim1*dim2 + i * dim2 + thrd_d2;
printf("idx: %d : src_index: %d\n",idx,src_index);
if(src_index < _limit)
tmpSum0 += g_idata[src_index];
}
if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
__syncthreads();
unsigned int oindx = (unsigned int)( thrd_d0*dim2 + thrd_d2 );
if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];
}
else
{
if (overaxis0 == 0 && overaxis1 == 0 && overaxis2 == 1) { // FFT
/* Each thread handles 1 pairs of elements.
* BlockDim is 1D
* BlockDim should be dividable by 1
*
* */
// static shared memory
__shared__ float smem_store[BLOCK_SIZE];
// set thread ID
//unsigned int tid = threadIdx.x;
unsigned int tid = threadIdx.x;
// global index
unsigned int idx = (blockIdx.x * blockDim.x + threadIdx.x);
// unrolling
float tmpSum0 = 0;
unsigned int i = 0;
unsigned int src_index ;
unsigned int _limit = (unsigned int)(dim0 * dim1 * dim2);
//Indices over output's matrix (NOT OVER INPUT) (OUTPUT'S CONSIDERED AS A ROW-MAJOR MATRIX)
int thrd_d0 = (idx) / (dim1*1);
int thrd_d1 = (idx - thrd_d0*dim1);
//Only for debugging kernel
printf("tid: %03d \tidx: %03d\td0: %02d\td1: %02d\n",tid,idx,thrd_d0,thrd_d1);
//Merging the thread's DIM1 element from all DIM1's elements of current DIM0.
for (i = 0; i < dim2; i++) {
src_index = thrd_d0*dim1*dim2 + thrd_d1 * dim2 + i;
if(idx<15) printf("idx: %d : src_index: %d\n",idx,src_index);
if(src_index < _limit)
tmpSum0 += g_idata[src_index];
}
if (src_index + 0 < _limit) smem_store[tid + 0] = tmpSum0;
__syncthreads();
unsigned int oindx = (unsigned int)( thrd_d0*dim1 + thrd_d1 );
if (src_index + 0 <= _limit) g_odata[oindx + 0] = smem_store[tid + 0];
}
}
}
void reduce_sum_3d_try02(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
int overaxis0,
int overaxis1,
int overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim2 ((dim0*dim1 + block.x - 1) / block.x, 1);
dim3 grid = (overaxis0==1)?(grid_overdim0):(overaxis1==1?grid_overdim1:grid_overdim2);
kernel_reduce_sum_3d_try02 <<< grid, block >>> (
g_idata,
g_odata,
dim0, dim1, dim2,
overaxis0, overaxis1,overaxis2);
}
__global__ void kernel_reduce_sum_3d_try03(
const float * __restrict__ g_idata,
float * __restrict__ g_odata,
const unsigned int dim0,
const unsigned int dim1,
const unsigned int dim2,
const bool overaxis0,
const bool overaxis1,
const bool overaxis2)
{
// WANING : dim0 means dim2 and dim2 means dim0
__shared__ float sm[BLOCK_SIZE];
if (overaxis2 && !overaxis1 && !overaxis0)
{
// Case 1 - sums in X-direction
// each threadblock is responsible for a separate row sum
unsigned int bidx = blockIdx.x;
unsigned int tidx = threadIdx.x;
sm[threadIdx.x] = 0;
while (tidx < dim0)
{
sm[threadIdx.x] += g_idata[bidx*dim0+tidx];
/*if(bidx==21){
//dbg
printf("thid: %04d\tg_index_to_read:%d\n",threadIdx.x,bidx*dim0+tidx);
}*/
tidx += blockDim.x;
} // block-stride loop
__syncthreads();
// parallel reduction
for (int i = blockDim.x>>1; i > 0; i>>=1)
{
if (threadIdx.x < i) sm[threadIdx.x] += sm[threadIdx.x + i];
__syncthreads();
}
if (!threadIdx.x) g_odata[bidx] = sm[0];
}
else if (!overaxis2 && overaxis1 && !overaxis0)
{
// Case 2 - sums in Y-direction
// each thread is responsible for a separate Y-column sum
unsigned int idx = threadIdx.x+blockDim.x*blockIdx.x;
if (idx < (dim0*dim2))
{
unsigned int tidx = idx%dim0 + (idx/dim0)*(dim0*dim1); //indices over input tensor (begining of axis1 slices)
float tsum = 0;
for (unsigned int i = 0; i < dim1; i++)
{
//printf("idx: %03d \t\t tidx: %03d\n",idx,tidx);
tsum += g_idata[tidx];
tidx += dim0;
}
g_odata[idx] = tsum;
}
}
else if (!overaxis2 && !overaxis1 && overaxis0)
{
// Case 3 - sums in Z-direction
// each thread is responsible for a separate Z-column sum
unsigned int idx = threadIdx.x + blockDim.x*blockIdx.x;
//printf("%d,%d,%d\n",dbg_blockid,dbg_thid,idx);
if (idx < (dim0*dim1))
{
unsigned int tidx = idx;
float tsum = 0;
for (int i = 0; i < dim2; i++)
{
//printf("%d,%d,%d,%d,%d\n",dbg_blockid,dbg_thid,idx,tidx,i);
//printf("idx:%02d, tidx:%02d, i=%02d\n",idx,tidx,i);
tsum += g_idata[tidx];
tidx += dim0*dim1;
}
g_odata[idx] = tsum;
}
}
else {
printf("reduce_sum: ERROR-NOTIMPLEMENTED\n");
}
}
void reduce_sum_3d_try03(
float* g_idata,
float* g_odata,
int dim0,
int dim1,
int dim2,
bool overaxis0,
bool overaxis1,
bool overaxis2)
{
dim3 block (BLOCK_SIZE, 1);
dim3 grid_overdim0 ((dim1*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim1 ((dim0*dim2 + block.x - 1) / block.x, 1);
dim3 grid_overdim2 (dim0*dim1 , 1);
dim3 grid = overaxis0 ? (grid_overdim0) : (overaxis1 ? grid_overdim1 : grid_overdim2);
//printf("-------------------------------------------------------\n");
//printf("KERNEL_GRID : %d\n", grid.x);
//printf("KERNEL_BLOCK : %d\n", block.x);
kernel_reduce_sum_3d_try03 <<<grid, block>>> (
g_idata, g_odata,
dim2, dim1, dim0,
overaxis0, overaxis1,overaxis2);
} | .text
.file "reduce_sum_3d.hip"
.globl _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii # -- Begin function _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
.p2align 4, 0x90
.type _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii,@function
_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii: # @_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii, .Lfunc_end0-_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
.cfi_endproc
# -- End function
.globl _Z19reduce_sum_3d_try01PfS_iiiiii # -- Begin function _Z19reduce_sum_3d_try01PfS_iiiiii
.p2align 4, 0x90
.type _Z19reduce_sum_3d_try01PfS_iiiiii,@function
_Z19reduce_sum_3d_try01PfS_iiiiii: # @_Z19reduce_sum_3d_try01PfS_iiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
movl %r8d, %eax
imull %ecx, %eax
cmpl $1, 224(%rsp)
movl %ecx, %edi
cmovel %r8d, %edi
imull %edx, %edi
cmpl $1, %r9d
cmovel %eax, %edi
addl $255, %edi
shrl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl 232(%rsp), %eax
movq %r13, 88(%rsp)
movq %r12, 80(%rsp)
movl %r15d, 28(%rsp)
movl %r14d, 24(%rsp)
movl %ebp, 20(%rsp)
movl %ebx, 16(%rsp)
movl 224(%rsp), %ecx
movl %ecx, 12(%rsp)
movl %eax, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z19reduce_sum_3d_try01PfS_iiiiii, .Lfunc_end1-_Z19reduce_sum_3d_try01PfS_iiiiii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii # -- Begin function _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
.p2align 4, 0x90
.type _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii,@function
_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii: # @_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii, .Lfunc_end2-_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
.cfi_endproc
# -- End function
.globl _Z19reduce_sum_3d_try02PfS_iiiiii # -- Begin function _Z19reduce_sum_3d_try02PfS_iiiiii
.p2align 4, 0x90
.type _Z19reduce_sum_3d_try02PfS_iiiiii,@function
_Z19reduce_sum_3d_try02PfS_iiiiii: # @_Z19reduce_sum_3d_try02PfS_iiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
movl %r8d, %eax
imull %ecx, %eax
cmpl $1, 224(%rsp)
movl %ecx, %edi
cmovel %r8d, %edi
imull %edx, %edi
cmpl $1, %r9d
cmovel %eax, %edi
addl $255, %edi
shrl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movl 232(%rsp), %eax
movq %r13, 88(%rsp)
movq %r12, 80(%rsp)
movl %r15d, 28(%rsp)
movl %r14d, 24(%rsp)
movl %ebp, 20(%rsp)
movl %ebx, 16(%rsp)
movl 224(%rsp), %ecx
movl %ecx, 12(%rsp)
movl %eax, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z19reduce_sum_3d_try02PfS_iiiiii, .Lfunc_end3-_Z19reduce_sum_3d_try02PfS_iiiiii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb # -- Begin function _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
.p2align 4, 0x90
.type _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb,@function
_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb: # @_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movzbl 168(%rsp), %eax
movzbl 160(%rsp), %r10d
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movb %r9b, 3(%rsp)
movb %r10b, 2(%rsp)
movb %al, 1(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 3(%rsp), %rax
movq %rax, 120(%rsp)
leaq 2(%rsp), %rax
movq %rax, 128(%rsp)
leaq 1(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb, .Lfunc_end4-_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
.cfi_endproc
# -- End function
.globl _Z19reduce_sum_3d_try03PfS_iiibbb # -- Begin function _Z19reduce_sum_3d_try03PfS_iiibbb
.p2align 4, 0x90
.type _Z19reduce_sum_3d_try03PfS_iiibbb,@function
_Z19reduce_sum_3d_try03PfS_iiibbb: # @_Z19reduce_sum_3d_try03PfS_iiibbb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r15d
movl %ecx, %r14d
movl %edx, %ebp
movl %r8d, %ecx
imull %r14d, %ecx
addl $255, %ecx
shrl $8, %ecx
movl %r8d, %edx
imull %ebp, %edx
addl $255, %edx
shrl $8, %edx
movl %r14d, %eax
imull %ebp, %eax
cmpb $0, 208(%rsp)
cmovnel %edx, %eax
movq %rsi, %r12
testl %r9d, %r9d
cmovnel %ecx, %eax
movq %rdi, %r13
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rax
orq $256, %rdx # imm = 0x100
movq %rax, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movzbl 216(%rsp), %eax
movq %r13, 72(%rsp)
movq %r12, 64(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
movb %bl, 3(%rsp)
movzbl 208(%rsp), %ecx
movb %cl, 2(%rsp)
movb %al, 1(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 3(%rsp), %rax
movq %rax, 120(%rsp)
leaq 2(%rsp), %rax
movq %rax, 128(%rsp)
leaq 1(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z19reduce_sum_3d_try03PfS_iiibbb, .Lfunc_end5-_Z19reduce_sum_3d_try03PfS_iiibbb
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii,@object # @_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
.section .rodata,"a",@progbits
.globl _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
.p2align 3, 0x0
_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii:
.quad _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
.size _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, 8
.type _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii,@object # @_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
.globl _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
.p2align 3, 0x0
_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii:
.quad _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
.size _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, 8
.type _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb,@object # @_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
.globl _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
.p2align 3, 0x0
_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb:
.quad _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
.size _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii"
.size .L__unnamed_1, 42
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii"
.size .L__unnamed_2, 42
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb"
.size .L__unnamed_3, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
.addrsig_sym _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
.addrsig_sym _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
.addrsig_sym _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
.addrsig_sym _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
You are a helpful coding assistant specialized in converting from CUDA host assembly to AMD host assembly. | .file "tmpxft_0017dcad_00000000-6_reduce_sum_3d.cudafe1.cpp"
.text
#APP
#NO_APP
.type _ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2062:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaUnregisterFatBinary@PLT
addq $8, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2062:
.size _ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
.globl _Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
.type _Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii, @function
_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii:
.LFB2084:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L7
.L3:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L8
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L7:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L3
.L8:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2084:
.size _Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii, .-_Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
.globl _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
.type _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, @function
_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii:
.LFB2085:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2085:
.size _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, .-_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
.globl _Z19reduce_sum_3d_try01PfS_iiiiii
.type _Z19reduce_sum_3d_try01PfS_iiiiii, @function
_Z19reduce_sum_3d_try01PfS_iiiiii:
.LFB2057:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r14
movq %rsi, %r15
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
movl %r9d, %r13d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl %ecx, %eax
imull %r8d, %eax
addl $255, %eax
shrl $10, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl %r8d, %eax
imull %edx, %eax
addl $255, %eax
shrl $10, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %ecx, %eax
imull %edx, %eax
addl $255, %eax
shrl $10, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
leaq 24(%rsp), %rax
cmpl $1, %r9d
je .L12
leaq 36(%rsp), %rdx
leaq 48(%rsp), %rax
cmpl $1, 144(%rsp)
cmove %rdx, %rax
.L12:
movq (%rax), %rdi
movq %rdi, 60(%rsp)
movl 8(%rax), %esi
movl $256, 12(%rsp)
movl 20(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L18
.L11:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L19
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L18:
.cfi_restore_state
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
movl %r13d, %r9d
movl %r12d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq %r15, %rsi
movq %r14, %rdi
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try01PKfPfiiiiiiPKfPfiiiiii
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L11
.L19:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2057:
.size _Z19reduce_sum_3d_try01PfS_iiiiii, .-_Z19reduce_sum_3d_try01PfS_iiiiii
.globl _Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
.type _Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii, @function
_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii:
.LFB2086:
.cfi_startproc
endbr64
subq $184, %rsp
.cfi_def_cfa_offset 192
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
movq %fs:40, %rax
movq %rax, 168(%rsp)
xorl %eax, %eax
movq %rdi, 16(%rsp)
leaq 16(%rsp), %rax
movq %rax, 96(%rsp)
movq %rsi, 24(%rsp)
leaq 24(%rsp), %rax
movq %rax, 104(%rsp)
leaq 12(%rsp), %rax
movq %rax, 112(%rsp)
leaq 8(%rsp), %rax
movq %rax, 120(%rsp)
leaq 4(%rsp), %rax
movq %rax, 128(%rsp)
movq %rsp, %rax
movq %rax, 136(%rsp)
leaq 192(%rsp), %rax
movq %rax, 144(%rsp)
leaq 200(%rsp), %rax
movq %rax, 152(%rsp)
movl $1, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
leaq 40(%rsp), %rcx
leaq 32(%rsp), %rdx
leaq 60(%rsp), %rsi
leaq 48(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L24
.L20:
movq 168(%rsp), %rax
subq %fs:40, %rax
jne .L25
addq $184, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L24:
.cfi_restore_state
pushq 40(%rsp)
.cfi_def_cfa_offset 200
pushq 40(%rsp)
.cfi_def_cfa_offset 208
leaq 112(%rsp), %r9
movq 76(%rsp), %rcx
movl 84(%rsp), %r8d
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
leaq _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 192
jmp .L20
.L25:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2086:
.size _Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii, .-_Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
.globl _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
.type _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, @function
_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii:
.LFB2087:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2087:
.size _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, .-_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
.globl _Z19reduce_sum_3d_try02PfS_iiiiii
.type _Z19reduce_sum_3d_try02PfS_iiiiii, @function
_Z19reduce_sum_3d_try02PfS_iiiiii:
.LFB2058:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $88, %rsp
.cfi_def_cfa_offset 144
movq %rdi, %r14
movq %rsi, %r15
movl %edx, %ebx
movl %ecx, %ebp
movl %r8d, %r12d
movl %r9d, %r13d
movq %fs:40, %rax
movq %rax, 72(%rsp)
xorl %eax, %eax
movl $1, 16(%rsp)
movl $1, 20(%rsp)
movl %ecx, %eax
imull %r8d, %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 24(%rsp)
movl $1, 28(%rsp)
movl $1, 32(%rsp)
movl %r8d, %eax
imull %edx, %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 36(%rsp)
movl $1, 40(%rsp)
movl $1, 44(%rsp)
movl %ecx, %eax
imull %edx, %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 48(%rsp)
movl $1, 52(%rsp)
movl $1, 56(%rsp)
leaq 24(%rsp), %rax
cmpl $1, %r9d
je .L29
leaq 36(%rsp), %rdx
leaq 48(%rsp), %rax
cmpl $1, 144(%rsp)
cmove %rdx, %rax
.L29:
movq (%rax), %rdi
movq %rdi, 60(%rsp)
movl 8(%rax), %esi
movl $256, 12(%rsp)
movl 20(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 12(%rsp), %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L35
.L28:
movq 72(%rsp), %rax
subq %fs:40, %rax
jne .L36
addq $88, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L35:
.cfi_restore_state
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 152
movl 152(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 160
movl %r13d, %r9d
movl %r12d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq %r15, %rsi
movq %r14, %rdi
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try02PKfPfiiiiiiPKfPfiiiiii
addq $16, %rsp
.cfi_def_cfa_offset 144
jmp .L28
.L36:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2058:
.size _Z19reduce_sum_3d_try02PfS_iiiiii, .-_Z19reduce_sum_3d_try02PfS_iiiiii
.globl _Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
.type _Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb, @function
_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb:
.LFB2088:
.cfi_startproc
endbr64
subq $200, %rsp
.cfi_def_cfa_offset 208
movl %edx, 28(%rsp)
movl %ecx, 24(%rsp)
movl %r8d, 20(%rsp)
movb %r9b, 16(%rsp)
movl 208(%rsp), %eax
movb %al, 12(%rsp)
movl 216(%rsp), %eax
movb %al, 8(%rsp)
movq %fs:40, %rax
movq %rax, 184(%rsp)
xorl %eax, %eax
movq %rdi, 32(%rsp)
leaq 32(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsi, 40(%rsp)
leaq 40(%rsp), %rax
movq %rax, 120(%rsp)
leaq 28(%rsp), %rax
movq %rax, 128(%rsp)
leaq 24(%rsp), %rax
movq %rax, 136(%rsp)
leaq 20(%rsp), %rax
movq %rax, 144(%rsp)
leaq 16(%rsp), %rax
movq %rax, 152(%rsp)
leaq 12(%rsp), %rax
movq %rax, 160(%rsp)
leaq 8(%rsp), %rax
movq %rax, 168(%rsp)
movl $1, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
movl $1, 76(%rsp)
movl $1, 80(%rsp)
movl $1, 84(%rsp)
leaq 56(%rsp), %rcx
leaq 48(%rsp), %rdx
leaq 76(%rsp), %rsi
leaq 64(%rsp), %rdi
call __cudaPopCallConfiguration@PLT
testl %eax, %eax
je .L41
.L37:
movq 184(%rsp), %rax
subq %fs:40, %rax
jne .L42
addq $200, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 8
ret
.L41:
.cfi_restore_state
pushq 56(%rsp)
.cfi_def_cfa_offset 216
pushq 56(%rsp)
.cfi_def_cfa_offset 224
leaq 128(%rsp), %r9
movq 92(%rsp), %rcx
movl 100(%rsp), %r8d
movq 80(%rsp), %rsi
movl 88(%rsp), %edx
leaq _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb(%rip), %rdi
call cudaLaunchKernel@PLT
addq $16, %rsp
.cfi_def_cfa_offset 208
jmp .L37
.L42:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2088:
.size _Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb, .-_Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
.globl _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
.type _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, @function
_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb:
.LFB2089:
.cfi_startproc
endbr64
subq $8, %rsp
.cfi_def_cfa_offset 16
movzbl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 24
movzbl 24(%rsp), %eax
pushq %rax
.cfi_def_cfa_offset 32
movzbl %r9b, %r9d
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
addq $24, %rsp
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2089:
.size _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, .-_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
.globl _Z19reduce_sum_3d_try03PfS_iiibbb
.type _Z19reduce_sum_3d_try03PfS_iiibbb, @function
_Z19reduce_sum_3d_try03PfS_iiibbb:
.LFB2059:
.cfi_startproc
endbr64
pushq %r15
.cfi_def_cfa_offset 16
.cfi_offset 15, -16
pushq %r14
.cfi_def_cfa_offset 24
.cfi_offset 14, -24
pushq %r13
.cfi_def_cfa_offset 32
.cfi_offset 13, -32
pushq %r12
.cfi_def_cfa_offset 40
.cfi_offset 12, -40
pushq %rbp
.cfi_def_cfa_offset 48
.cfi_offset 6, -48
pushq %rbx
.cfi_def_cfa_offset 56
.cfi_offset 3, -56
subq $104, %rsp
.cfi_def_cfa_offset 160
movq %rdi, (%rsp)
movq %rsi, 8(%rsp)
movl %edx, %r12d
movl %ecx, %ebp
movl %r8d, %ebx
movl %r9d, %r13d
movl 160(%rsp), %r14d
movl 168(%rsp), %r15d
movq %fs:40, %rax
movq %rax, 88(%rsp)
xorl %eax, %eax
movl $1, 32(%rsp)
movl $1, 36(%rsp)
movl %ecx, %eax
imull %r8d, %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 40(%rsp)
movl $1, 44(%rsp)
movl $1, 48(%rsp)
movl %r8d, %eax
imull %edx, %eax
addl $255, %eax
shrl $8, %eax
movl %eax, 52(%rsp)
movl $1, 56(%rsp)
movl $1, 60(%rsp)
movl %ecx, %eax
imull %edx, %eax
movl %eax, 64(%rsp)
movl $1, 68(%rsp)
movl $1, 72(%rsp)
leaq 40(%rsp), %rax
testb %r9b, %r9b
jne .L46
leaq 52(%rsp), %rdx
leaq 64(%rsp), %rax
testb %r14b, %r14b
cmovne %rdx, %rax
.L46:
movq (%rax), %rdi
movq %rdi, 76(%rsp)
movl 8(%rax), %esi
movl $256, 28(%rsp)
movl 36(%rsp), %ecx
movl $0, %r9d
movl $0, %r8d
movq 28(%rsp), %rdx
call __cudaPushCallConfiguration@PLT
testl %eax, %eax
je .L52
.L45:
movq 88(%rsp), %rax
subq %fs:40, %rax
jne .L53
addq $104, %rsp
.cfi_remember_state
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %rbp
.cfi_def_cfa_offset 40
popq %r12
.cfi_def_cfa_offset 32
popq %r13
.cfi_def_cfa_offset 24
popq %r14
.cfi_def_cfa_offset 16
popq %r15
.cfi_def_cfa_offset 8
ret
.L52:
.cfi_restore_state
movzbl %r15b, %r15d
pushq %r15
.cfi_def_cfa_offset 168
movzbl %r14b, %r14d
pushq %r14
.cfi_def_cfa_offset 176
movzbl %r13b, %r9d
movl %r12d, %r8d
movl %ebp, %ecx
movl %ebx, %edx
movq 24(%rsp), %rsi
movq 16(%rsp), %rdi
call _Z55__device_stub__Z26kernel_reduce_sum_3d_try03PKfPfjjjbbbPKfPfjjjbbb
addq $16, %rsp
.cfi_def_cfa_offset 160
jmp .L45
.L53:
call __stack_chk_fail@PLT
.cfi_endproc
.LFE2059:
.size _Z19reduce_sum_3d_try03PfS_iiibbb, .-_Z19reduce_sum_3d_try03PfS_iiibbb
.section .rodata.str1.8,"aMS",@progbits,1
.align 8
.LC0:
.string "_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb"
.align 8
.LC1:
.string "_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii"
.align 8
.LC2:
.string "_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii"
.text
.type _ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2091:
.cfi_startproc
endbr64
pushq %rbx
.cfi_def_cfa_offset 16
.cfi_offset 3, -16
leaq _ZL15__fatDeviceText(%rip), %rdi
call __cudaRegisterFatBinary@PLT
movq %rax, %rbx
movq %rax, _ZL20__cudaFatCubinHandle(%rip)
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC0(%rip), %rdx
movq %rdx, %rcx
leaq _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb(%rip), %rsi
movq %rax, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC1(%rip), %rdx
movq %rdx, %rcx
leaq _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
pushq $0
.cfi_def_cfa_offset 24
pushq $0
.cfi_def_cfa_offset 32
pushq $0
.cfi_def_cfa_offset 40
pushq $0
.cfi_def_cfa_offset 48
movl $0, %r9d
movl $-1, %r8d
leaq .LC2(%rip), %rdx
movq %rdx, %rcx
leaq _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii(%rip), %rsi
movq %rbx, %rdi
call __cudaRegisterFunction@PLT
addq $32, %rsp
.cfi_def_cfa_offset 16
movq _ZL20__cudaFatCubinHandle(%rip), %rdi
call __cudaRegisterFatBinaryEnd@PLT
leaq _ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
call atexit@PLT
popq %rbx
.cfi_def_cfa_offset 8
ret
.cfi_endproc
.LFE2091:
.size _ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
.section .init_array,"aw"
.align 8
.quad _ZL24__sti____cudaRegisterAllv
.section .nvFatBinSegment,"aw"
.align 8
.type _ZL15__fatDeviceText, @object
.size _ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
.long 1180844977
.long 1
.quad fatbinData
.quad 0
.local _ZL20__cudaFatCubinHandle
.comm _ZL20__cudaFatCubinHandle,8,8
.ident "GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
.section .note.GNU-stack,"",@progbits
.section .note.gnu.property,"a"
.align 8
.long 1f - 0f
.long 4f - 1f
.long 5
0:
.string "GNU"
1:
.align 8
.long 0xc0000002
.long 3f - 2f
2:
.long 0x3
3:
.align 8
4: | .text
.file "reduce_sum_3d.hip"
.globl _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii # -- Begin function _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
.p2align 4, 0x90
.type _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii,@function
_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii: # @_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end0:
.size _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii, .Lfunc_end0-_Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
.cfi_endproc
# -- End function
.globl _Z19reduce_sum_3d_try01PfS_iiiiii # -- Begin function _Z19reduce_sum_3d_try01PfS_iiiiii
.p2align 4, 0x90
.type _Z19reduce_sum_3d_try01PfS_iiiiii,@function
_Z19reduce_sum_3d_try01PfS_iiiiii: # @_Z19reduce_sum_3d_try01PfS_iiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
movl %r8d, %eax
imull %ecx, %eax
cmpl $1, 224(%rsp)
movl %ecx, %edi
cmovel %r8d, %edi
imull %edx, %edi
cmpl $1, %r9d
cmovel %eax, %edi
addl $255, %edi
shrl $10, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB1_2
# %bb.1:
movl 232(%rsp), %eax
movq %r13, 88(%rsp)
movq %r12, 80(%rsp)
movl %r15d, 28(%rsp)
movl %r14d, 24(%rsp)
movl %ebp, 20(%rsp)
movl %ebx, 16(%rsp)
movl 224(%rsp), %ecx
movl %ecx, 12(%rsp)
movl %eax, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB1_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end1:
.size _Z19reduce_sum_3d_try01PfS_iiiiii, .Lfunc_end1-_Z19reduce_sum_3d_try01PfS_iiiiii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii # -- Begin function _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
.p2align 4, 0x90
.type _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii,@function
_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii: # @_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movl %r9d, (%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
movq %rsp, %rax
movq %rax, 120(%rsp)
leaq 160(%rsp), %rax
movq %rax, 128(%rsp)
leaq 168(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end2:
.size _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii, .Lfunc_end2-_Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
.cfi_endproc
# -- End function
.globl _Z19reduce_sum_3d_try02PfS_iiiiii # -- Begin function _Z19reduce_sum_3d_try02PfS_iiiiii
.p2align 4, 0x90
.type _Z19reduce_sum_3d_try02PfS_iiiiii,@function
_Z19reduce_sum_3d_try02PfS_iiiiii: # @_Z19reduce_sum_3d_try02PfS_iiiiii
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $168, %rsp
.cfi_def_cfa_offset 224
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %ebp
movl %ecx, %r14d
movl %edx, %r15d
movq %rsi, %r12
movq %rdi, %r13
movl %r8d, %eax
imull %ecx, %eax
cmpl $1, 224(%rsp)
movl %ecx, %edi
cmovel %r8d, %edi
imull %edx, %edi
cmpl $1, %r9d
cmovel %eax, %edi
addl $255, %edi
shrl $8, %edi
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rdi
orq $256, %rdx # imm = 0x100
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB3_2
# %bb.1:
movl 232(%rsp), %eax
movq %r13, 88(%rsp)
movq %r12, 80(%rsp)
movl %r15d, 28(%rsp)
movl %r14d, 24(%rsp)
movl %ebp, 20(%rsp)
movl %ebx, 16(%rsp)
movl 224(%rsp), %ecx
movl %ecx, 12(%rsp)
movl %eax, 8(%rsp)
leaq 88(%rsp), %rax
movq %rax, 96(%rsp)
leaq 80(%rsp), %rax
movq %rax, 104(%rsp)
leaq 28(%rsp), %rax
movq %rax, 112(%rsp)
leaq 24(%rsp), %rax
movq %rax, 120(%rsp)
leaq 20(%rsp), %rax
movq %rax, 128(%rsp)
leaq 16(%rsp), %rax
movq %rax, 136(%rsp)
leaq 12(%rsp), %rax
movq %rax, 144(%rsp)
leaq 8(%rsp), %rax
movq %rax, 152(%rsp)
leaq 64(%rsp), %rdi
leaq 48(%rsp), %rsi
leaq 40(%rsp), %rdx
leaq 32(%rsp), %rcx
callq __hipPopCallConfiguration
movq 64(%rsp), %rsi
movl 72(%rsp), %edx
movq 48(%rsp), %rcx
movl 56(%rsp), %r8d
leaq 96(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, %edi
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
pushq 48(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB3_2:
addq $168, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end3:
.size _Z19reduce_sum_3d_try02PfS_iiiiii, .Lfunc_end3-_Z19reduce_sum_3d_try02PfS_iiiiii
.cfi_endproc
# -- End function
.globl _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb # -- Begin function _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
.p2align 4, 0x90
.type _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb,@function
_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb: # @_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
.cfi_startproc
# %bb.0:
subq $152, %rsp
.cfi_def_cfa_offset 160
movzbl 168(%rsp), %eax
movzbl 160(%rsp), %r10d
movq %rdi, 72(%rsp)
movq %rsi, 64(%rsp)
movl %edx, 12(%rsp)
movl %ecx, 8(%rsp)
movl %r8d, 4(%rsp)
movb %r9b, 3(%rsp)
movb %r10b, 2(%rsp)
movb %al, 1(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 3(%rsp), %rax
movq %rax, 120(%rsp)
leaq 2(%rsp), %rax
movq %rax, 128(%rsp)
leaq 1(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $168, %rsp
.cfi_adjust_cfa_offset -168
retq
.Lfunc_end4:
.size _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb, .Lfunc_end4-_Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
.cfi_endproc
# -- End function
.globl _Z19reduce_sum_3d_try03PfS_iiibbb # -- Begin function _Z19reduce_sum_3d_try03PfS_iiibbb
.p2align 4, 0x90
.type _Z19reduce_sum_3d_try03PfS_iiibbb,@function
_Z19reduce_sum_3d_try03PfS_iiibbb: # @_Z19reduce_sum_3d_try03PfS_iiibbb
.cfi_startproc
# %bb.0:
pushq %rbp
.cfi_def_cfa_offset 16
pushq %r15
.cfi_def_cfa_offset 24
pushq %r14
.cfi_def_cfa_offset 32
pushq %r13
.cfi_def_cfa_offset 40
pushq %r12
.cfi_def_cfa_offset 48
pushq %rbx
.cfi_def_cfa_offset 56
subq $152, %rsp
.cfi_def_cfa_offset 208
.cfi_offset %rbx, -56
.cfi_offset %r12, -48
.cfi_offset %r13, -40
.cfi_offset %r14, -32
.cfi_offset %r15, -24
.cfi_offset %rbp, -16
movl %r9d, %ebx
movl %r8d, %r15d
movl %ecx, %r14d
movl %edx, %ebp
movl %r8d, %ecx
imull %r14d, %ecx
addl $255, %ecx
shrl $8, %ecx
movl %r8d, %edx
imull %ebp, %edx
addl $255, %edx
shrl $8, %edx
movl %r14d, %eax
imull %ebp, %eax
cmpb $0, 208(%rsp)
cmovnel %edx, %eax
movq %rsi, %r12
testl %r9d, %r9d
cmovnel %ecx, %eax
movq %rdi, %r13
movabsq $4294967296, %rdx # imm = 0x100000000
orq %rdx, %rax
orq $256, %rdx # imm = 0x100
movq %rax, %rdi
movl $1, %esi
movl $1, %ecx
xorl %r8d, %r8d
xorl %r9d, %r9d
callq __hipPushCallConfiguration
testl %eax, %eax
jne .LBB5_2
# %bb.1:
movzbl 216(%rsp), %eax
movq %r13, 72(%rsp)
movq %r12, 64(%rsp)
movl %r15d, 12(%rsp)
movl %r14d, 8(%rsp)
movl %ebp, 4(%rsp)
movb %bl, 3(%rsp)
movzbl 208(%rsp), %ecx
movb %cl, 2(%rsp)
movb %al, 1(%rsp)
leaq 72(%rsp), %rax
movq %rax, 80(%rsp)
leaq 64(%rsp), %rax
movq %rax, 88(%rsp)
leaq 12(%rsp), %rax
movq %rax, 96(%rsp)
leaq 8(%rsp), %rax
movq %rax, 104(%rsp)
leaq 4(%rsp), %rax
movq %rax, 112(%rsp)
leaq 3(%rsp), %rax
movq %rax, 120(%rsp)
leaq 2(%rsp), %rax
movq %rax, 128(%rsp)
leaq 1(%rsp), %rax
movq %rax, 136(%rsp)
leaq 48(%rsp), %rdi
leaq 32(%rsp), %rsi
leaq 24(%rsp), %rdx
leaq 16(%rsp), %rcx
callq __hipPopCallConfiguration
movq 48(%rsp), %rsi
movl 56(%rsp), %edx
movq 32(%rsp), %rcx
movl 40(%rsp), %r8d
leaq 80(%rsp), %r9
movl $_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, %edi
pushq 16(%rsp)
.cfi_adjust_cfa_offset 8
pushq 32(%rsp)
.cfi_adjust_cfa_offset 8
callq hipLaunchKernel
addq $16, %rsp
.cfi_adjust_cfa_offset -16
.LBB5_2:
addq $152, %rsp
.cfi_def_cfa_offset 56
popq %rbx
.cfi_def_cfa_offset 48
popq %r12
.cfi_def_cfa_offset 40
popq %r13
.cfi_def_cfa_offset 32
popq %r14
.cfi_def_cfa_offset 24
popq %r15
.cfi_def_cfa_offset 16
popq %rbp
.cfi_def_cfa_offset 8
retq
.Lfunc_end5:
.size _Z19reduce_sum_3d_try03PfS_iiibbb, .Lfunc_end5-_Z19reduce_sum_3d_try03PfS_iiibbb
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_ctor
.type __hip_module_ctor,@function
__hip_module_ctor: # @__hip_module_ctor
.cfi_startproc
# %bb.0:
pushq %rbx
.cfi_def_cfa_offset 16
subq $32, %rsp
.cfi_def_cfa_offset 48
.cfi_offset %rbx, -16
cmpq $0, __hip_gpubin_handle(%rip)
jne .LBB6_2
# %bb.1:
movl $__hip_fatbin_wrapper, %edi
callq __hipRegisterFatBinary
movq %rax, __hip_gpubin_handle(%rip)
.LBB6_2:
movq __hip_gpubin_handle(%rip), %rbx
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, %esi
movl $.L__unnamed_1, %edx
movl $.L__unnamed_1, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, %esi
movl $.L__unnamed_2, %edx
movl $.L__unnamed_2, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
xorps %xmm0, %xmm0
movups %xmm0, 16(%rsp)
movups %xmm0, (%rsp)
movl $_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, %esi
movl $.L__unnamed_3, %edx
movl $.L__unnamed_3, %ecx
movq %rbx, %rdi
movl $-1, %r8d
xorl %r9d, %r9d
callq __hipRegisterFunction
movl $__hip_module_dtor, %edi
addq $32, %rsp
.cfi_def_cfa_offset 16
popq %rbx
.cfi_def_cfa_offset 8
jmp atexit # TAILCALL
.Lfunc_end6:
.size __hip_module_ctor, .Lfunc_end6-__hip_module_ctor
.cfi_endproc
# -- End function
.p2align 4, 0x90 # -- Begin function __hip_module_dtor
.type __hip_module_dtor,@function
__hip_module_dtor: # @__hip_module_dtor
.cfi_startproc
# %bb.0:
movq __hip_gpubin_handle(%rip), %rdi
testq %rdi, %rdi
je .LBB7_2
# %bb.1:
pushq %rax
.cfi_def_cfa_offset 16
callq __hipUnregisterFatBinary
movq $0, __hip_gpubin_handle(%rip)
addq $8, %rsp
.cfi_def_cfa_offset 8
.LBB7_2:
retq
.Lfunc_end7:
.size __hip_module_dtor, .Lfunc_end7-__hip_module_dtor
.cfi_endproc
# -- End function
.type _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii,@object # @_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
.section .rodata,"a",@progbits
.globl _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
.p2align 3, 0x0
_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii:
.quad _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
.size _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii, 8
.type _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii,@object # @_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
.globl _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
.p2align 3, 0x0
_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii:
.quad _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
.size _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii, 8
.type _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb,@object # @_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
.globl _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
.p2align 3, 0x0
_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb:
.quad _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
.size _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb, 8
.type .L__unnamed_1,@object # @0
.section .rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
.asciz "_Z26kernel_reduce_sum_3d_try01PKfPfiiiiii"
.size .L__unnamed_1, 42
.type .L__unnamed_2,@object # @1
.L__unnamed_2:
.asciz "_Z26kernel_reduce_sum_3d_try02PKfPfiiiiii"
.size .L__unnamed_2, 42
.type .L__unnamed_3,@object # @2
.L__unnamed_3:
.asciz "_Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb"
.size .L__unnamed_3, 42
.type __hip_fatbin_wrapper,@object # @__hip_fatbin_wrapper
.section .hipFatBinSegment,"a",@progbits
.p2align 3, 0x0
__hip_fatbin_wrapper:
.long 1212764230 # 0x48495046
.long 1 # 0x1
.quad __hip_fatbin
.quad 0
.size __hip_fatbin_wrapper, 24
.type __hip_gpubin_handle,@object # @__hip_gpubin_handle
.local __hip_gpubin_handle
.comm __hip_gpubin_handle,8,8
.section .init_array,"aw",@init_array
.p2align 3, 0x0
.quad __hip_module_ctor
.type __hip_cuid_,@object # @__hip_cuid_
.bss
.globl __hip_cuid_
__hip_cuid_:
.byte 0 # 0x0
.size __hip_cuid_, 1
.section ".linker-options","e",@llvm_linker_options
.ident "AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
.section ".note.GNU-stack","",@progbits
.addrsig
.addrsig_sym _Z41__device_stub__kernel_reduce_sum_3d_try01PKfPfiiiiii
.addrsig_sym _Z41__device_stub__kernel_reduce_sum_3d_try02PKfPfiiiiii
.addrsig_sym _Z41__device_stub__kernel_reduce_sum_3d_try03PKfPfjjjbbb
.addrsig_sym __hip_module_ctor
.addrsig_sym __hip_module_dtor
.addrsig_sym _Z26kernel_reduce_sum_3d_try01PKfPfiiiiii
.addrsig_sym _Z26kernel_reduce_sum_3d_try02PKfPfiiiiii
.addrsig_sym _Z26kernel_reduce_sum_3d_try03PKfPfjjjbbb
.addrsig_sym __hip_fatbin
.addrsig_sym __hip_fatbin_wrapper
.addrsig_sym __hip_cuid_ |
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